STM32F410Rx HAL User Manual: STM32F4xx HAL Drivers

STM32F410Rx HAL User Manual
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STM32F4xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32F410Rx HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization Functions

  • Data Structures
  • Files
  • Directories
Functions
Initialization and de-initialization Functions
HAL Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initializes the Flash interface the NVIC allocation and initial clock
          configuration. It initializes the systick also when timeout is needed
          and the backup domain when enabled.
      (+) de-Initializes common part of the HAL
      (+) Configure The time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) Systick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the systick.

This function is optional.

Return values:
HAL status

Definition at line 200 of file stm32f4xx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.

Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz). Set NVIC Group Priority to 4. Calls the HAL_MspInit() callback function defined in user file "stm32f4xx_hal_msp.c" to do the global low level hardware initialization

Note:
SysTick is used as time base for the HAL_Delay() function, the application need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation.
Return values:
HAL status

Definition at line 167 of file stm32f4xx_hal.c.

References __HAL_FLASH_DATA_CACHE_ENABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, __HAL_FLASH_PREFETCH_BUFFER_ENABLE, HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base.

The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 263 of file stm32f4xx_hal.c.

References HAL_NVIC_SetPriority(), HAL_RCC_GetHCLKFreq(), and HAL_SYSTICK_Config().

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 240 of file stm32f4xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initializes the MSP.

Return values:
None

Definition at line 229 of file stm32f4xx_hal.c.

Referenced by HAL_Init().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 419 of file stm32f4xx_hal.c.

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 455 of file stm32f4xx_hal.c.

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Return values:
None

Definition at line 437 of file stm32f4xx_hal.c.

void HAL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 410 of file stm32f4xx_hal.c.

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 446 of file stm32f4xx_hal.c.

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Return values:
None

Definition at line 428 of file stm32f4xx_hal.c.

void HAL_Delay ( __IO uint32_t Delay )

This function provides accurate delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay,: specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 338 of file stm32f4xx_hal.c.

References HAL_GetTick().

void HAL_DisableCompensationCell ( void )

Power-down the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 477 of file stm32f4xx_hal.c.

References CMPCR_CMP_PD_BB.

void HAL_EnableCompensationCell ( void )

Enables the I/O Compensation Cell.

Note:
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
Return values:
None

Definition at line 466 of file stm32f4xx_hal.c.

References CMPCR_CMP_PD_BB.

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 401 of file stm32f4xx_hal.c.

References IDCODE_DEVID_MASK.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 383 of file stm32f4xx_hal.c.

References __STM32F4xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 392 of file stm32f4xx_hal.c.

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 322 of file stm32f4xx_hal.c.

References uwTick.

Referenced by FLASH_WaitForLastOperation(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_Delay(), HAL_DMA_Abort(), HAL_DMA_PollForTransfer(), HAL_FMPI2C_IsDeviceReady(), HAL_I2C_IsDeviceReady(), HAL_IWDG_Refresh(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), HAL_PWREx_EnableBkUpReg(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_GenerateRandomNumber(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), I2S_WaitFlagStateUntilTimeout(), IRDA_WaitOnFlagUntilTimeout(), RTC_EnterInitMode(), SMARTCARD_WaitOnFlagUntilTimeout(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_WaitFlagStateUntilTimeout(), UART_WaitOnFlagUntilTimeout(), and USART_WaitOnFlagUntilTimeout().

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 311 of file stm32f4xx_hal.c.

References uwTick.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 373 of file stm32f4xx_hal.c.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 357 of file stm32f4xx_hal.c.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Cortex Lockup Enable

Defines
Cortex Lockup Enable
HAL Exported Macros

Defines

#define __HAL_SYSCFG_BREAK_PVD_LOCK()
SYSCFG Break Lockup lock Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input.

Define Documentation

#define __HAL_SYSCFG_BREAK_PVD_LOCK ( )
Value:
do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
                                              }while(0)

SYSCFG Break Lockup lock Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input.

Note:
The selected configuration is locked and can be unlocked by system reset

Definition at line 160 of file stm32f4xx_hal.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PVD Lock

Defines
PVD Lock
HAL Exported Macros

Defines

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()
SYSCFG Break PVD lock Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register.

Define Documentation

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK ( )
Value:
do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
                                                }while(0)

SYSCFG Break PVD lock Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register.

Note:
The selected configuration is locked and can be unlocked by system reset

Definition at line 174 of file stm32f4xx_hal.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: HAL Exported Macros

Modules | Defines
HAL Exported Macros
HAL

Modules

Cortex Lockup Enable
PVD Lock

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM()
Embedded SRAM mapped at 0x00000000.

Define Documentation

#define __HAL_DBGMCU_FREEZE_CAN1 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))

Definition at line 82 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_CAN2 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))

Definition at line 83 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

Definition at line 79 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))

Definition at line 80 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))

Definition at line 81 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))

Definition at line 78 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))

Definition at line 76 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))

Definition at line 84 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM10 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))

Definition at line 87 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM11 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))

Definition at line 88 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM12 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))

Definition at line 73 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM13 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))

Definition at line 74 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM14 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))

Definition at line 75 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))

Freeze/Unfreeze Peripherals in Debug mode.

Definition at line 67 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))

Definition at line 68 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))

Definition at line 69 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM5 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))

Definition at line 70 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))

Definition at line 71 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))

Definition at line 72 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM8 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))

Definition at line 85 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM9 ( ) (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))

Definition at line 86 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))

Definition at line 77 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_CAN1 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))

Definition at line 105 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_CAN2 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))

Definition at line 106 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))

Definition at line 102 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))

Definition at line 103 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))

Definition at line 104 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))

Definition at line 101 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_RTC ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))

Definition at line 99 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM1 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))

Definition at line 107 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM10 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))

Definition at line 110 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM11 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))

Definition at line 111 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM12 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))

Definition at line 96 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM13 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))

Definition at line 97 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM14 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))

Definition at line 98 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))

Definition at line 90 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM3 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))

Definition at line 91 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM4 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))

Definition at line 92 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM5 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))

Definition at line 93 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM6 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))

Definition at line 94 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM7 ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))

Definition at line 95 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM8 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))

Definition at line 108 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM9 ( ) (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))

Definition at line 109 of file stm32f4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))

Definition at line 100 of file stm32f4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FLASH ( ) (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))

Main Flash memory mapped at 0x00000000.

Definition at line 115 of file stm32f4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SRAM ( )
Value:
do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
                                                 }while(0);

Embedded SRAM mapped at 0x00000000.

Definition at line 125 of file stm32f4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH ( )
Value:
do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
                                                         SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
                                                        }while(0);

System Flash memory mapped at 0x00000000.

Definition at line 119 of file stm32f4xx_hal.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: HAL Private Variables

Variables
HAL Private Variables
HAL

Variables

__IO uint32_t uwTick

Variable Documentation

__IO uint32_t uwTick

Definition at line 106 of file stm32f4xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: HAL Private Constants

Defines
HAL Private Constants
HAL

Defines

#define | __STM32F4xx_HAL_VERSION_MAIN (0x01)
STM32F4xx HAL Driver version number V1.4.4.
#define | __STM32F4xx_HAL_VERSION_SUB1 (0x04)
#define | __STM32F4xx_HAL_VERSION_SUB2 (0x04)
#define | __STM32F4xx_HAL_VERSION_RC (0x00)
#define | __STM32F4xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | MEMRMP_OFFSET SYSCFG_OFFSET
#define | UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
#define | UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))
#define | CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U)
#define | CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
#define | CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))

Define Documentation

#define __STM32F4xx_HAL_VERSION
Value:
((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
                                        |(__STM32F4xx_HAL_VERSION_RC))

Definition at line 77 of file stm32f4xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32F4xx_HAL_VERSION_MAIN (0x01)

STM32F4xx HAL Driver version number V1.4.4.

[31:24] main version

Definition at line 73 of file stm32f4xx_hal.c.

#define __STM32F4xx_HAL_VERSION_RC (0x00)

[7:0] release candidate

Definition at line 76 of file stm32f4xx_hal.c.

#define __STM32F4xx_HAL_VERSION_SUB1 (0x04)

[23:16] sub1 version

Definition at line 74 of file stm32f4xx_hal.c.

#define __STM32F4xx_HAL_VERSION_SUB2 (0x04)

[15:8] sub2 version

Definition at line 75 of file stm32f4xx_hal.c.

#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)

Definition at line 95 of file stm32f4xx_hal.c.

#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))

Definition at line 96 of file stm32f4xx_hal.c.

Referenced by HAL_DisableCompensationCell(), and HAL_EnableCompensationCell().

#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U)

Definition at line 94 of file stm32f4xx_hal.c.

#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)

Definition at line 82 of file stm32f4xx_hal.c.

Referenced by HAL_GetDEVID().

#define MEMRMP_OFFSET SYSCFG_OFFSET

Definition at line 88 of file stm32f4xx_hal.c.

#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)

Definition at line 85 of file stm32f4xx_hal.c.

#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))

Definition at line 90 of file stm32f4xx_hal.c.

#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)

Definition at line 89 of file stm32f4xx_hal.c.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitializes the ADCx peripheral registers to their default reset values.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitializes the ADCx peripheral registers to their default reset values.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 336 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_DISABLE, ADC_CLEAR_ERRORCODE, assert_param, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.

Note:
This function is used to configure the global features of the ADC ( ClockPrescaler, Resolution, Data Alignment and number of conversion), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, DMA continuous request after the last transfer and End of conversion selection).
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 258 of file stm32f4xx_hal_adc.c.

References ADC_CLEAR_ERRORCODE, ADC_Init(), ADC_SOFTWARE_START, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, ADC_InitTypeDef::EOCSelection, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_DATA_ALIGN, IS_ADC_EOCSelection, IS_ADC_EXT_TRIG, IS_ADC_EXT_TRIG_EDGE, IS_ADC_REGULAR_LENGTH, IS_ADC_RESOLUTION, ADC_HandleTypeDef::Lock, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::Resolution, ADC_InitTypeDef::ScanConvMode, and ADC_HandleTypeDef::State.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitializes the ADC MSP.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 398 of file stm32f4xx_hal_adc.c.

Referenced by HAL_ADC_DeInit().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initializes the ADC MSP.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 383 of file stm32f4xx_hal_adc.c.

Referenced by HAL_ADC_Init().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
ADC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC and starts conversion of the regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Disables ADC and stop conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for regular conversion complete.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Disables the interrupt and stop ADC conversion of regular channels.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Gets the converted value from data register of regular channel.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion half DMA transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
Error ADC callback.

Detailed Description

IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular channel.
      (+) Stop conversion of regular channel.
      (+) Start conversion of regular channel and enable interrupt.
      (+) Stop conversion of regular channel and disable interrupt.
      (+) Start conversion of regular channel and enable DMA transfer.
      (+) Stop conversion of regular channel and disable DMA transfer.
      (+) Handle ADC interrupt request.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Regular conversion complete callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1190 of file stm32f4xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), and HAL_ADC_IRQHandler().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Regular conversion half DMA transfer callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1205 of file stm32f4xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt(), and ADC_MultiModeDMAHalfConvCplt().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

Error ADC callback.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1235 of file stm32f4xx_hal_adc.c.

Referenced by ADC_DMAError(), ADC_MultiModeDMAError(), and HAL_ADC_IRQHandler().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Gets the converted value from data register of regular channel.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
Converted value

Definition at line 1178 of file stm32f4xx_hal_adc.c.

References ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handles ADC interrupt request.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 868 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, __HAL_ADC_GET_IT_SOURCE, ADC_FLAG_AWD, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_FLAG_OVR, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_AWD, ADC_IT_EOC, ADC_IT_JEOC, ADC_IT_OVR, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADCEx_InjectedConvCpltCallback(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EOCSelection, IS_ADC_REGULAR_LENGTH, ADC_InitTypeDef::NbrOfConversion, and ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1220 of file stm32f4xx_hal_adc.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Poll for regular conversion complete.

Note:
ADC conversion flags EOS (end of sequence) and EOC (end of conversion) are cleared by this function.
This function cannot be used in a particular setup: ADC configured in DMA mode and polling for end of each conversion (ADC init parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. Nevertheless, polling can still be performed on the complete sequence.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 581 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_FLAG_EOC, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_REGULAR, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for conversion event.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
EventType,: the ADC event type. This parameter can be one of the following values:
  • ADC_AWD_EVENT: ADC Analog watch Dog event.
  • ADC_OVR_EVENT: ADC Overrun event.
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 666 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD_EVENT, ADC_FLAG_AWD, ADC_FLAG_OVR, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enables ADC and starts conversion of the regular channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 437 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, ADC_CLEAR_ERRORCODE, ADC_FLAG_EOC, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
pData,: The destination Buffer address.
Length,: The length of data to be transferred from ADC peripheral to memory.
Return values:
HAL status

Definition at line 1013 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_FLAG_EOC, ADC_IT_OVR, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enables the interrupt and starts ADC conversion of regular channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 728 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_FLAG_EOC, ADC_IT_EOC, ADC_IT_OVR, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Disables ADC and stop conversion of regular channels.

Note:
Caution: This function will stop also injected channels.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 538 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_DISABLE, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 1132 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_DISABLE, __HAL_ADC_DISABLE_IT, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Disables the interrupt and stop ADC conversion of regular channels.

Note:
Caution: This function will stop also injected channels.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 831 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_DISABLE, __HAL_ADC_DISABLE_IT, ADC_IT_EOC, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure regular channels.
      (+) Configure injected channels.
      (+) Configure multimode.
      (+) Configure the analog watch dog.

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configures the analog watchdog.

Note:
Analog watchdog thresholds can be modified while ADC conversion is on going. In this case, some constraints must be taken into account: The programmed threshold values are effective from the next ADC EOC (end of unitary conversion). Considering that registers write delay may happen due to bus activity, this might cause an uncertainty on the effective timing of the new programmed threshold values.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure that contains the configuration information of ADC analog watchdog.
Return values:
HAL status

Definition at line 1379 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_GET_RESOLUTION, ADC_IT_AWD, assert_param, ADC_AnalogWDGConfTypeDef::Channel, ADC_AnalogWDGConfTypeDef::HighThreshold, ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, ADC_AnalogWDGConfTypeDef::LowThreshold, and ADC_AnalogWDGConfTypeDef::WatchdogMode.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
sConfig,: ADC configuration structure.
Return values:
HAL status

Definition at line 1273 of file stm32f4xx_hal_adc.c.

References ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_SMPR1, ADC_SMPR2, ADC_SQR1_RK, ADC_SQR2_RK, ADC_SQR3_RK, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_ChannelConfTypeDef::Channel, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_ChannelConfTypeDef::Rank, and ADC_ChannelConfTypeDef::SamplingTime.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Peripheral State functions

Functions
ADC Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral State and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the ADC state
      (+) Check the ADC Error

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
ADC Error Code

Definition at line 1473 of file stm32f4xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

return the ADC state

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL state

Definition at line 1461 of file stm32f4xx_hal_adc.c.

References ADC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC | ADC Exported Functions

Functions

static void | ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct without initializing the ADC MSP.
static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Function Documentation

static void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1574 of file stm32f4xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_EOC, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_ConvCpltCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1640 of file stm32f4xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA().

static void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1627 of file stm32f4xx_hal_adc.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA().

static void ADC_Init ( ADC_HandleTypeDef * hadc ) [static]

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct without initializing the ADC MSP.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 1493 of file stm32f4xx_hal_adc.c.

References ADC_CR1_DISCONTINUOUS, ADC_CR1_SCANCONV, ADC_CR2_CONTINUOUS, ADC_CR2_DMAContReq, ADC_CR2_EOCSelection, ADC_SOFTWARE_START, ADC_SQR1, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, ADC_InitTypeDef::EOCSelection, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_REGULAR_DISC_NUMBER, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::Resolution, and ADC_InitTypeDef::ScanConvMode.

Referenced by HAL_ADC_Init().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Exported Types

Data Structures | Defines
ADC Exported Types
ADC

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration multi-mode structure definition. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000U)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001U)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U)

Define Documentation

#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U)

Out-of-window occurrence of analog watchdog 1

Definition at line 197 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U)

Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2

Definition at line 198 of file stm32f4xx_hal_adc.h.

#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U)

Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3

Definition at line 199 of file stm32f4xx_hal_adc.h.

#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U)

ADC is busy to internal process (initialization, calibration)

Definition at line 177 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U)

Configuration error occurrence

Definition at line 182 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U)

DMA error occurrence

Definition at line 183 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), ADC_MultiModeDMAConvCplt(), and ADC_MultiModeDMAError().

#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U)

Internal error occurrence

Definition at line 181 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U)

A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 192 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U)

Conversion data available on group injected

Definition at line 194 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U)

Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master (

Definition at line 202 of file stm32f4xx_hal_adc.h.

#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U)

ADC peripheral ready for use

Definition at line 176 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U)

A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 186 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U)

Conversion data available on group regular

Definition at line 188 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U)

Overrun occurrence

Definition at line 189 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U)

HAL ADC state machine: ADC states definition (bitfields)

ADC not yet initialized or disabled

Definition at line 175 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U)

TimeOut occurrence

Definition at line 178 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC and regular group initialization. More...

#include <stm32f4xx_hal_adc.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | DataAlign
uint32_t | ScanConvMode
uint32_t | EOCSelection
uint32_t | ContinuousConvMode
uint32_t | NbrOfConversion
uint32_t | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
uint32_t | DMAContinuousRequests

Detailed Description

Structure definition of ADC and regular group initialization.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
  • Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
  • For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 75 of file stm32f4xx_hal_adc.h.

Field Documentation

uint32_t ADC_InitTypeDef::ClockPrescaler

Select ADC clock prescaler. The clock is common for all the ADCs. This parameter can be a value of ADC Clock Prescaler

Definition at line 77 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ContinuousConvMode

Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 99 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Init(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::DataAlign

Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of ADC Data Align

Definition at line 82 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::DiscontinuousConvMode

Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE.

Definition at line 105 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::DMAContinuousRequests

Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) or in Continuous mode (DMA transfer unlimited, whatever number of conversions). Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). This parameter can be set to ENABLE or DISABLE.

Definition at line 119 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::EOCSelection

Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of ADC EOC Selection. Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence

Definition at line 92 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), and HAL_ADC_IRQHandler().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge by default. This parameter can be a value of ADC External Trigger Source Regular

Definition at line 112 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Selects the external trigger edge of regular group. If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of ADC External Trigger Edge Regular

Definition at line 116 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16.

Definition at line 102 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), HAL_ADC_Init(), and HAL_ADC_IRQHandler().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 109 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init().

uint32_t ADC_InitTypeDef::Resolution

Configures the ADC resolution. This parameter can be a value of ADC Resolution

Definition at line 80 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be set to ENABLE or DISABLE

Definition at line 85 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_adc.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32f4xx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime
uint32_t | Offset

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC can be either disabled or enabled without conversion on going on regular group.

Definition at line 133 of file stm32f4xx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specifies the channel to configure into ADC regular group. This parameter can be a value of ADC Common Channels

Definition at line 135 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Offset

Reserved for future use, can be set to 0

Definition at line 148 of file stm32f4xx_hal_adc.h.

uint32_t ADC_ChannelConfTypeDef::Rank

Specifies the rank in the regular group sequencer. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 137 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). This parameter can be a value of ADC Sampling Times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min).

Definition at line 139 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_adc.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

ADC Configuration multi-mode structure definition. More...

#include <stm32f4xx_hal_adc.h>

Data Fields

uint32_t | WatchdogMode
uint32_t | HighThreshold
uint32_t | LowThreshold
uint32_t | Channel
uint32_t | ITMode
uint32_t | WatchdogNumber

Detailed Description

ADC Configuration multi-mode structure definition.

Definition at line 154 of file stm32f4xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Configures ADC channel for the analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel This parameter can be a value of ADC Common Channels

Definition at line 162 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a 12-bit value.

Definition at line 158 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::ITMode

Specifies whether the analog watchdog is configured is interrupt mode or in polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 165 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a 12-bit value.

Definition at line 160 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configures the ADC analog watchdog mode. This parameter can be a value of ADC Analog Watchdog Selection

Definition at line 156 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Reserved for future use, can be set to 0

Definition at line 168 of file stm32f4xx_hal_adc.h.

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_adc.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32f4xx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
__IO uint32_t | NbrOfCurrentConversionRank
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode

Detailed Description

ADC handle Structure definition.

Definition at line 208 of file stm32f4xx_hal_adc.h.

Field Documentation

DMA_HandleTypeDef* ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 216 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

__IO uint32_t ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 222 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAError(), ADC_MultiModeDMAError(), HAL_ADC_GetError(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

ADC_InitTypeDef ADC_HandleTypeDef::Init

ADC required parameters

Definition at line 212 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Init(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

ADC_TypeDef* ADC_HandleTypeDef::Instance

Register base address

Definition at line 210 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_Init(), ADC_MultiModeDMAConvCplt(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

HAL_LockTypeDef ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 218 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

__IO uint32_t ADC_HandleTypeDef::NbrOfCurrentConversionRank

ADC number of current conversion rank

Definition at line 214 of file stm32f4xx_hal_adc.h.

__IO uint32_t ADC_HandleTypeDef::State

ADC communication state

Definition at line 220 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), ADC_MultiModeDMAConvCplt(), ADC_MultiModeDMAError(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_adc.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00U)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02U)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04U)

Define Documentation

#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U)

DMA transfer error

Definition at line 240 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAError(), ADC_MultiModeDMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U)

ADC IP internal error: if problem of clocking, enable/disable, erroneous state

Definition at line 237 of file stm32f4xx_hal_adc.h.

#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U)

No error

Definition at line 236 of file stm32f4xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U)

Overrun error

Definition at line 239 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Clock Prescaler

Defines
ADC Clock Prescaler
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)

Define Documentation

#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)

Definition at line 249 of file stm32f4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)

Definition at line 250 of file stm32f4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)

Definition at line 251 of file stm32f4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)

Definition at line 252 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Delay Between 2 Sampling Phases

Defines
ADC Delay Between 2 Sampling Phases
ADC Exported Constants

Defines

#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
#define | ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
#define | ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)

Define Documentation

#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))

Definition at line 265 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))

Definition at line 266 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

Definition at line 267 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)

Definition at line 268 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))

Definition at line 269 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))

Definition at line 270 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

Definition at line 271 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))

Definition at line 272 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))

Definition at line 273 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))

Definition at line 274 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)

Definition at line 275 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)

Definition at line 260 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)

Definition at line 261 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)

Definition at line 262 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

Definition at line 263 of file stm32f4xx_hal_adc.h.

#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)

Definition at line 264 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Resolution

Defines
ADC Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define | ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define | ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)

Define Documentation

#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)

Definition at line 284 of file stm32f4xx_hal_adc.h.

#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)

Definition at line 283 of file stm32f4xx_hal_adc.h.

#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)

Definition at line 286 of file stm32f4xx_hal_adc.h.

#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)

Definition at line 285 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC External Trigger Edge Regular

Defines
ADC External Trigger Edge Regular
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)

Definition at line 296 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)

Definition at line 294 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)

Definition at line 295 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)

Definition at line 297 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC External Trigger Source Regular

Defines
ADC External Trigger Source Regular
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define | ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define | ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
#define | ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
#define | ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
#define | ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)

Define Documentation

#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)

Definition at line 322 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)

Definition at line 307 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)

Definition at line 308 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)

Definition at line 309 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 310 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)

Definition at line 311 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))

Definition at line 312 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))

Definition at line 313 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 314 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)

Definition at line 315 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))

Definition at line 316 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))

Definition at line 317 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 318 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))

Definition at line 319 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))

Definition at line 320 of file stm32f4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))

Definition at line 321 of file stm32f4xx_hal_adc.h.

#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)

Definition at line 323 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADC_Init().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Data Align

Defines
ADC Data Align
ADC Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Define Documentation

#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Definition at line 332 of file stm32f4xx_hal_adc.h.

#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)

Definition at line 331 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Common Channels

Defines
ADC Common Channels
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 ((uint32_t)0x00000000U)
#define | ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
#define | ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)

Define Documentation

#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)

Definition at line 340 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)

Definition at line 341 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))

Definition at line 350 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 351 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))

Definition at line 352 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))

Definition at line 353 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))

Definition at line 354 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 355 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)

Definition at line 356 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))

Definition at line 357 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))

Definition at line 358 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)

Definition at line 342 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 343 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)

Definition at line 344 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))

Definition at line 345 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))

Definition at line 346 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))

Definition at line 347 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)

Definition at line 348 of file stm32f4xx_hal_adc.h.

#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))

Definition at line 349 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)

Definition at line 361 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)

Definition at line 360 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32F410Rx HAL User Manual: ADC Sampling Times

Defines
ADC Sampling Times
ADC Exported Constants

Defines

#define | ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
#define | ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define | ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define | ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
#define | ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
#define | ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)

Define Documentation

#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))

Definition at line 374 of file stm32f4xx_hal_adc.h.

#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))

Definition at line 375 of file stm32f4xx_hal_adc.h.

#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)

Definition at line 370 of file stm32f4xx_hal_adc.h.

#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)

Definition at line 371 of file stm32f4xx_hal_adc.h.

#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)

Definition at line 369 of file stm32f4xx_hal_adc.h.

#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)

Definition at line 376 of file stm32f4xx_hal_adc.h.

#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))

Definition at line 372 of file stm32f4xx_hal_adc.h.

#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)

Definition at line 373 of file stm32f4xx_hal_adc.h.

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STM32F410Rx HAL User Manual: ADC EOC Selection

Defines
ADC EOC Selection
ADC Exported Constants

Defines

#define | ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
#define | ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
#define | ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U)

Define Documentation

#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)

Definition at line 384 of file stm32f4xx_hal_adc.h.

#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)

Definition at line 385 of file stm32f4xx_hal_adc.h.

#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U)

reserved for future use

Definition at line 386 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Event Type

Defines
ADC Event Type
ADC Exported Constants

Defines

#define | ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)

Define Documentation

#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)

Definition at line 394 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)

Definition at line 395 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Analog Watchdog Selection

Defines
ADC Analog Watchdog Selection
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)

Definition at line 407 of file stm32f4xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)

Definition at line 406 of file stm32f4xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 408 of file stm32f4xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)

Definition at line 409 of file stm32f4xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))

Definition at line 404 of file stm32f4xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))

Definition at line 403 of file stm32f4xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 405 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Interrupts Definition

Defines
ADC Interrupts Definition
ADC Exported Constants

Defines

#define | ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define | ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define | ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define | ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)

Define Documentation

#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)

Definition at line 418 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)

Definition at line 417 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), and HAL_ADC_Stop_IT().

#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)

Definition at line 419 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)

Definition at line 420 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Flags Definition

Defines
ADC Flags Definition
ADC Exported Constants

Defines

#define | ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
#define | ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
#define | ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
#define | ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
#define | ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
#define | ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)

Define Documentation

#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)

Definition at line 428 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)

Definition at line 429 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)

Definition at line 430 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)

Definition at line 431 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)

Definition at line 433 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)

Definition at line 432 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Channels Type

Defines
ADC Channels Type
ADC Exported Constants

Defines

#define | ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
#define | ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U)
#define | ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U)

Define Documentation

#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)

Definition at line 441 of file stm32f4xx_hal_adc.h.

#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U)

reserved for future use

Definition at line 443 of file stm32f4xx_hal_adc.h.

#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U)

reserved for future use

Definition at line 442 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Exported Macros

Defines
ADC Exported Macros
ADC | ADCEx

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Check if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clear the ADC's pending flags.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__FLAG__))

Clear the ADC's pending flags.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__FLAG__,: ADC flag.
Return values:
None

Definition at line 506 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)

Disable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 475 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))

Disable the ADC end of conversion interrupt.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__INTERRUPT__,: ADC interrupt.
Return values:
None

Definition at line 491 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

#define __HAL_ADC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)

Enable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 468 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))

Enable the ADC end of conversion interrupt.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__INTERRUPT__,: ADC Interrupt.
Return values:
None

Definition at line 483 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected ADC's flag status.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__FLAG__,: ADC flag.
Return values:
None

Definition at line 514 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))

Check if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the ADC Handle.
__INTERRUPT__,: specifies the ADC interrupt source to check.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 498 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler().

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

Reset ADC handle state.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 461 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_STAB_DELAY_US ((uint32_t) 3U)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)

Define Documentation

#define ADC_STAB_DELAY_US ((uint32_t) 3U)

Definition at line 600 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)

Definition at line 604 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
#define | IS_ADC_SAMPLING_DELAY(DELAY)
#define | IS_ADC_RESOLUTION(RESOLUTION)
#define | IS_ADC_EXT_TRIG_EDGE(EDGE)
#define | IS_ADC_EXT_TRIG(REGTRIG)
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_EOCSelection(EOCSelection)
#define | IS_ADC_EVENT_TYPE(EVENT)
#define | IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define | IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE)
#define | IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
#define | IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
#define | IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
#define | IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
#define | IS_ADC_RANGE(RESOLUTION, ADC_VALUE)
#define | ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
Set ADC Regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
Enable ADC scan mode.
#define | ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
Enable the ADC end of conversion selection.
#define | ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
Enable the ADC DMA continuous request.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
Return resolution bits in CR1 register.

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to error code: "no error")

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 658 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_CR1_DISCONTINUOUS ( _NBR_DISCONTINUOUSCONV_ ) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))

Configures the number of discontinuous conversions for the regular group channels.

Parameters:
_NBR_DISCONTINUOUSCONV_,: Number of discontinuous conversions.
Return values:
None

Definition at line 802 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR1_SCANCONV ( _SCANCONV_MODE_ ) ((_SCANCONV_MODE_) << 8U)

Enable ADC scan mode.

Parameters:
_SCANCONV_MODE_,: Scan conversion mode.
Return values:
None

Definition at line 809 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR2_CONTINUOUS ( _CONTINUOUS_MODE_ ) ((_CONTINUOUS_MODE_) << 1U)

Enable ADC continuous conversion mode.

Parameters:
_CONTINUOUS_MODE_,: Continuous mode.
Return values:
None

Definition at line 795 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR2_DMAContReq ( _DMAContReq_MODE_ ) ((_DMAContReq_MODE_) << 9U)

Enable the ADC DMA continuous request.

Parameters:
_DMAContReq_MODE_,: DMA continuous request mode.
Return values:
None

Definition at line 823 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_CR2_EOCSelection ( _EOCSelection_MODE_ ) ((_EOCSelection_MODE_) << 10U)

Enable the ADC end of conversion selection.

Parameters:
_EOCSelection_MODE_,: End of conversion selection mode.
Return values:
None

Definition at line 816 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)

Return resolution bits in CR1 register.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 830 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_ENABLE ( __HANDLE__ )
Value:
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
  ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 622 of file stm32f4xx_hal_adc.h.

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 641 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_IS_SOFTWARE_START_REGULAR ( __HANDLE__ ) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)

Test if conversion trigger of regular group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 632 of file stm32f4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_SMPR1 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))

Set the ADC's sample time for channel numbers between 10 and 18.

Parameters:
_SAMPLETIME_,: Sample time parameter.
_CHANNELNB_,: Channel number.
Return values:
None

Definition at line 756 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR2 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))

Set the ADC's sample time for channel numbers between 0 and 9.

Parameters:
_SAMPLETIME_,: Sample time parameter.
_CHANNELNB_,: Channel number.
Return values:
None

Definition at line 764 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1 ( _NbrOfConversion_ ) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)

Set ADC Regular channel sequence length.

Parameters:
_NbrOfConversion_,: Regular channel sequence length.
Return values:
None

Definition at line 748 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))

Set the selected regular channel rank for rank between 13 and 16.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 788 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR2_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))

Set the selected regular channel rank for rank between 7 and 12.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 780 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR3_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))

Set the selected regular channel rank for rank between 1 and 6.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 772 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clears and sets specific bits of the handle State.

Note:
: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 651 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define IS_ADC_ANALOG_WATCHDOG ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))

Definition at line 722 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CHANNELS_TYPE ( CHANNEL_TYPE )
Value:
(((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))

Definition at line 729 of file stm32f4xx_hal_adc.h.

#define IS_ADC_CLOCKPRESCALER ( ADC_CLOCK )
Value:
(((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))

Definition at line 662 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_DATA_ALIGN ( ALIGN )
Value:
(((ALIGN) == ADC_DATAALIGN_RIGHT) || \
                                  ((ALIGN) == ADC_DATAALIGN_LEFT))

Definition at line 707 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOCSelection ( EOCSelection )
Value:
(((EOCSelection) == ADC_EOC_SINGLE_CONV)   || \
                                           ((EOCSelection) == ADC_EOC_SEQ_CONV)  || \
                                           ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))

Definition at line 717 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EVENT_TYPE ( EVENT )
Value:
(((EVENT) == ADC_AWD_EVENT) || \
                                  ((EVENT) == ADC_OVR_EVENT))

Definition at line 720 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXT_TRIG ( REGTRIG )
Value:
(((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
                                  ((REGTRIG) == ADC_SOFTWARE_START))

Definition at line 690 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXT_TRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))

Definition at line 686 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define IS_ADC_RANGE | ( | RESOLUTION,
 |  | ADC_VALUE
 | ) |
Value:
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= ((uint32_t)0x003FU))))

Definition at line 737 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGULAR_DISC_NUMBER ( NUMBER ) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))

Definition at line 736 of file stm32f4xx_hal_adc.h.

Referenced by ADC_Init().

#define IS_ADC_REGULAR_LENGTH ( LENGTH ) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))

Definition at line 734 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_REGULAR_RANK ( RANK ) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))

Definition at line 735 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RESOLUTION ( RESOLUTION )
Value:
(((RESOLUTION) == ADC_RESOLUTION_12B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
                                       ((RESOLUTION) == ADC_RESOLUTION_6B))

Definition at line 682 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_SAMPLE_TIME ( TIME )
Value:
(((TIME) == ADC_SAMPLETIME_3CYCLES)   || \
                                  ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \
                                  ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
                                  ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
                                  ((TIME) == ADC_SAMPLETIME_480CYCLES))

Definition at line 709 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SAMPLING_DELAY ( DELAY )
Value:
(((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))

Definition at line 666 of file stm32f4xx_hal_adc.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_THRESHOLD ( THRESHOLD ) ((THRESHOLD) <= ((uint32_t)0xFFFU))

Definition at line 732 of file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extended features functions

Functions
Extended features functions
ADC Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables the selected ADC software start conversion of the injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for injected conversion complete.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Gets the converted value from data register of injected channel.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Configures the ADC multi-mode.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of injected channel.
      (+) Stop conversion of injected channel.
      (+) Start multimode and enable DMA transfer.
      (+) Stop multimode and disable DMA transfer.
      (+) Get result of injected channel conversion.
      (+) Get result of multimode conversion.
      (+) Configure injected channels.
      (+) Configure multimode.

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
sConfigInjected,: ADC configuration structure for injected channel.
Return values:
None

Definition at line 786 of file stm32f4xx_hal_adc_ex.c.

References ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_GET_RESOLUTION, ADC_INJECTED_SOFTWARE_START, ADC_JSQR, ADC_SMPR1, ADC_SMPR2, ADC_SQR1, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_EXT_INJEC_TRIG, IS_ADC_EXT_INJEC_TRIG_EDGE, IS_ADC_INJECTED_LENGTH, IS_ADC_INJECTED_RANK, IS_ADC_RANGE, and IS_ADC_SAMPLE_TIME.

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non blocking mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
None

Definition at line 769 of file stm32f4xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Gets the converted value from data register of injected channel.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
InjectedRank,: the ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1: Injected Channel1 selected
  • ADC_INJECTED_RANK_2: Injected Channel2 selected
  • ADC_INJECTED_RANK_3: Injected Channel3 selected
  • ADC_INJECTED_RANK_4: Injected Channel4 selected
Return values:
None

Definition at line 546 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_FLAG_JEOC, ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Poll for injected conversion complete.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 417 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enables the selected ADC software start conversion of the injected channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 177 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, ADC_CLEAR_ERRORCODE, ADC_FLAG_JEOC, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enables the interrupt and starts ADC conversion of injected channels.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status.

Definition at line 266 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_FLAG_JEOC, ADC_IT_JEOC, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
In case of auto-injection mode, HAL_ADC_Stop must be used.
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 363 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 484 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE, __HAL_ADC_DISABLE_IT, ADC_IT_JEOC, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_MultiModeTypeDef * | multimode
 | ) |  |

Configures the ADC multi-mode.

Parameters:
hadc | : pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
multimode | : pointer to an ADC_MultiModeTypeDef structure that contains the configuration information for multimode.
Return values:
HAL status

Definition at line 942 of file stm32f4xx_hal_adc_ex.c.

References assert_param, ADC_MultiModeTypeDef::DMAAccessMode, IS_ADC_DMA_ACCESS_MODE, IS_ADC_MODE, IS_ADC_SAMPLING_DELAY, ADC_MultiModeTypeDef::Mode, and ADC_MultiModeTypeDef::TwoSamplingDelay.

uint32_t HAL_ADCEx_MultiModeGetValue ( ADC_HandleTypeDef * hadc )

Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
The converted data value.

Definition at line 757 of file stm32f4xx_hal_adc_ex.c.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.

Note:
Caution: This function must be used only with the ADC master.
Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
pData,: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
Length,: The length of data to be transferred from ADC peripheral to memory.
Return values:
HAL status

Definition at line 597 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_FLAG_EOC, ADC_IT_OVR, ADC_MultiModeDMAConvCplt(), ADC_MultiModeDMAError(), ADC_MultiModeDMAHalfConvCplt(), ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, ADC_InitTypeDef::DMAContinuousRequests, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXT_TRIG_EDGE, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.

Parameters:
hadc,: pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
Return values:
HAL status

Definition at line 710 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE, __HAL_ADC_DISABLE_IT, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Exported Functions

Modules | Functions
ADC Exported Functions
ADCEx

Modules

Extended features functions

Extended features functions.

Functions

static void | ADC_MultiModeDMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_MultiModeDMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | ADC_MultiModeDMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void ADC_MultiModeDMAConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 981 of file stm32f4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_EOC, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_ConvCpltCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADCEx_MultiModeStart_DMA().

static void ADC_MultiModeDMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1047 of file stm32f4xx_hal_adc_ex.c.

References ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and ADC_HandleTypeDef::State.

Referenced by HAL_ADCEx_MultiModeStart_DMA().

static void ADC_MultiModeDMAHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1034 of file stm32f4xx_hal_adc_ex.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADCEx_MultiModeStart_DMA().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADC Exported Types

ADC Configuration injected Channel structure definition. More...

#include <stm32f4xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedOffset
uint32_t | InjectedNbrOfConversion
uint32_t | InjectedDiscontinuousConvMode
uint32_t | AutoInjectedConv
uint32_t | ExternalTrigInjecConv
uint32_t | ExternalTrigInjecConvEdge

Detailed Description

ADC Configuration injected Channel structure definition.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
  • Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
  • For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.

Definition at line 74 of file stm32f4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 107 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of ADC External Trigger Source Injected Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 115 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge

Selects the external trigger edge of injected group. This parameter can be a value of ADC External Trigger Edge Injected. If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 123 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Selection of ADC channel to configure This parameter can be a value of ADC Common Channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.

Definition at line 76 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 100 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 95 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.

Definition at line 91 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Rank in the injected group sequencer This parameter must be a value of ADC Injected Rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted)

Definition at line 79 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). This parameter can be a value of ADC Sampling Times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min).

Definition at line 82 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_adc_ex.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC_MultiModeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_MultiModeTypeDef Struct Reference
ADC Exported Types

ADC Configuration multi-mode structure definition. More...

#include <stm32f4xx_hal_adc_ex.h>

Data Fields

uint32_t | Mode
uint32_t | DMAAccessMode
uint32_t | TwoSamplingDelay

Detailed Description

ADC Configuration multi-mode structure definition.

Definition at line 133 of file stm32f4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_MultiModeTypeDef::DMAAccessMode

Configures the Direct memory access mode for multi ADC mode. This parameter can be a value of ADC Direct Memory Access Mode For Multi Mode

Definition at line 137 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::Mode

Configures the ADC to operate in independent or multi mode. This parameter can be a value of ADC Common Mode

Definition at line 135 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::TwoSamplingDelay

Configures the Delay between 2 sampling phases. This parameter can be a value of ADC Delay Between 2 Sampling Phases

Definition at line 139 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_adc_ex.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Common Mode

Defines
ADC Common Mode
ADC Exported Constants

Defines

#define | ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))

Define Documentation

#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))

Definition at line 161 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))

Definition at line 158 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))

Definition at line 160 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))

Definition at line 159 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)

Definition at line 157 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)

Definition at line 156 of file stm32f4xx_hal_adc_ex.h.

#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)

Definition at line 155 of file stm32f4xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))

Definition at line 167 of file stm32f4xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))

Definition at line 164 of file stm32f4xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))

Definition at line 166 of file stm32f4xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))

Definition at line 165 of file stm32f4xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))

Definition at line 163 of file stm32f4xx_hal_adc_ex.h.

#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))

Definition at line 162 of file stm32f4xx_hal_adc_ex.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Direct Memory Access Mode For Multi Mode

Defines
ADC Direct Memory Access Mode For Multi Mode
ADC Exported Constants

Defines

#define | ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U)
#define | ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0)
#define | ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1)
#define | ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA)

Define Documentation

#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0)

DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)

Definition at line 176 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1)

DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)

Definition at line 177 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA)

DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)

Definition at line 178 of file stm32f4xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U)

DMA mode disabled

Definition at line 175 of file stm32f4xx_hal_adc_ex.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC External Trigger Edge Injected

Defines
ADC External Trigger Edge Injected
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)

Definition at line 188 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)

Definition at line 186 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)

Definition at line 187 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)

Definition at line 189 of file stm32f4xx_hal_adc_ex.h.

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STM32F410Rx HAL User Manual: ADC External Trigger Source Injected

Defines
ADC External Trigger Source Injected
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)

Definition at line 212 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000U)

Definition at line 197 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)

Definition at line 198 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)

Definition at line 199 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 200 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)

Definition at line 201 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))

Definition at line 202 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))

Definition at line 203 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 204 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)

Definition at line 205 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))

Definition at line 206 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))

Definition at line 207 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 208 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))

Definition at line 209 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))

Definition at line 210 of file stm32f4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))

Definition at line 211 of file stm32f4xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)

Definition at line 213 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

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STM32F410Rx HAL User Manual: ADC Injected Rank

Defines
ADC Injected Rank
ADC Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)

Define Documentation

#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)

Definition at line 221 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)

Definition at line 222 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)

Definition at line 223 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)

Definition at line 224 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

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STM32F410Rx HAL User Manual: ADC Specific Channels

Defines
ADC Specific Channels
ADC Exported Constants

Defines

#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)

Define Documentation

#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)

Definition at line 235 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32F410Rx HAL User Manual: ADC Private Constants

ADC Private Constants
ADCEx
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADCEx

Defines

#define | IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
#define | IS_ADC_MODE(MODE)
#define | IS_ADC_DMA_ACCESS_MODE(MODE)
#define | IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE)
#define | IS_ADC_EXT_INJEC_TRIG(INJTRIG)
#define | IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
#define | IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
#define | ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
Set the selected injected Channel rank.

Define Documentation

#define ADC_JSQR | ( | _CHANNELNB_,
 |  | _RANKNB_,
 |  | _JSQR_JL_
 | ) | (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))

Set the selected injected Channel rank.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
_JSQR_JL_,: Sequence length.
Return values:
None

Definition at line 368 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CHANNEL ( CHANNEL ) ((CHANNEL) <= ADC_CHANNEL_18)

Definition at line 311 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_DMA_ACCESS_MODE ( MODE )
Value:
(((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
                                      ((MODE) == ADC_DMAACCESSMODE_1)        || \
                                      ((MODE) == ADC_DMAACCESSMODE_2)        || \
                                      ((MODE) == ADC_DMAACCESSMODE_3))

Definition at line 333 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_EXT_INJEC_TRIG ( INJTRIG )
Value:
(((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)  || \
                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
                                        ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))

Definition at line 341 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXT_INJEC_TRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))

Definition at line 337 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_LENGTH ( LENGTH ) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))

Definition at line 358 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_RANK ( RANK ) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))

Definition at line 359 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_MODE ( MODE )
Value:
(((MODE) == ADC_MODE_INDEPENDENT)                 || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
                           ((MODE) == ADC_DUALMODE_INJECSIMULT)             || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT)               || \
                           ((MODE) == ADC_DUALMODE_INTERL)                  || \
                           ((MODE) == ADC_DUALMODE_ALTERTRIG)               || \
                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
                           ((MODE) == ADC_TRIPLEMODE_INJECSIMULT)           || \
                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT)             || \
                           ((MODE) == ADC_TRIPLEMODE_INTERL)                || \
                           ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))

Definition at line 320 of file stm32f4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

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STM32F410Rx HAL User Manual: ADC Private Functions

ADC Private Functions
ADCEx
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: CAN

CAN
STM32F4xx_HAL_Driver

CAN driver modules. More...

CAN driver modules.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: CEC

CEC
STM32F4xx_HAL_Driver

HAL CEC module driver. More...

HAL CEC module driver.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disables a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
Return values:
None

Definition at line 221 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enables a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
Return values:
None

Definition at line 205 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Sets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
PreemptPriority,: The preemption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority,: the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 183 of file stm32f4xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup,: The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 161 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiates a system reset request to reset the MCU.

Return values:
None

Definition at line 234 of file stm32f4xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb,: Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 247 of file stm32f4xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initializes and configures the Region and the memory to be protected.

Parameters:
MPU_Init,: Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 278 of file stm32f4xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clears the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
Return values:
None

Definition at line 398 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Gets active interrupt ( reads the active register in NVIC and returns the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 415 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 382 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Gets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
PriorityGroup,: the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
pPreemptPriority,: Pointer on the Preemptive priority value (starting from 0).
pSubPriority,: Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 349 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Gets the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 322 of file stm32f4xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Sets Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
Return values:
None

Definition at line 364 of file stm32f4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 459 of file stm32f4xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configures the SysTick clock source.

Parameters:
CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 432 of file stm32f4xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

This function handles SYSTICK interrupt request.

Return values:
None

Definition at line 450 of file stm32f4xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

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STM32F410Rx HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32f4xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 66 of file stm32f4xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 79 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 72 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 81 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 68 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 87 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 85 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 83 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 70 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 73 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 75 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of MPU TEX Levels

Definition at line 77 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_cortex.h
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STM32F410Rx HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U)

Define Documentation

#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 108 of file stm32f4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 110 of file stm32f4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 112 of file stm32f4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 114 of file stm32f4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 116 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_Init().

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STM32F410Rx HAL User Manual: CORTEX _SysTick clock source

Defines
CORTEX _SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)

Definition at line 126 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)

Definition at line 125 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: MPU HFNMI and PRIVILEGED Access control

Defines
MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)

Define Documentation

#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)

Definition at line 137 of file stm32f4xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)

Definition at line 139 of file stm32f4xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)

Definition at line 136 of file stm32f4xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)

Definition at line 138 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01U)
#define | MPU_REGION_DISABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00U)

Definition at line 148 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01U)

Definition at line 147 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)

Definition at line 157 of file stm32f4xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)

Definition at line 156 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)

Definition at line 166 of file stm32f4xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)

Definition at line 165 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)

Definition at line 174 of file stm32f4xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)

Definition at line 175 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)

Definition at line 183 of file stm32f4xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)

Definition at line 184 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: MPU TEX Levels

Defines
MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02U)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)

Definition at line 192 of file stm32f4xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)

Definition at line 193 of file stm32f4xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)

Definition at line 194 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)

Definition at line 204 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)

Definition at line 214 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)

Definition at line 224 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)

Definition at line 211 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)

Definition at line 221 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)

Definition at line 227 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)

Definition at line 207 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)

Definition at line 217 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)

Definition at line 205 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)

Definition at line 215 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)

Definition at line 225 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)

Definition at line 228 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)

Definition at line 208 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)

Definition at line 218 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)

Definition at line 202 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)

Definition at line 212 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)

Definition at line 222 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)

Definition at line 229 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)

Definition at line 209 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)

Definition at line 219 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)

Definition at line 206 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)

Definition at line 216 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)

Definition at line 226 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)

Definition at line 203 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)

Definition at line 213 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)

Definition at line 223 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)

Definition at line 210 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)

Definition at line 220 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)

Definition at line 240 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)

Definition at line 237 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)

Definition at line 241 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)

Definition at line 242 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)

Definition at line 238 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)

Definition at line 239 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07U)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)

Definition at line 250 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)

Definition at line 251 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)

Definition at line 252 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)

Definition at line 253 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)

Definition at line 254 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)

Definition at line 255 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)

Definition at line 256 of file stm32f4xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)

Definition at line 257 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 348 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 345 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 342 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 339 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                     ((STATE) == MPU_REGION_DISABLE))

Definition at line 336 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
                                         ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 362 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 355 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 371 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FFU)

Definition at line 400 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
                                ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 351 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) >= (IRQn_Type)0x00U)

Definition at line 330 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 326 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 320 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 328 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 332 of file stm32f4xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

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STM32F410Rx HAL User Manual: CORTEX Private Functions

Functions
CORTEX Private Functions
CORTEX

CORTEX private functions. More...

Functions

__STATIC_INLINE void | HAL_MPU_Disable (void)
Disables the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

CORTEX private functions.

Function Documentation

__STATIC_INLINE void HAL_MPU_Disable ( void )

Disables the MPU.

Return values:
None

Definition at line 418 of file stm32f4xx_hal_cortex.h.

__STATIC_INLINE void HAL_MPU_Enable ( uint32_t MPU_Control )

Enables the MPU.

Parameters:
MPU_Control,: Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 438 of file stm32f4xx_hal_cortex.h.

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STM32F410Rx HAL User Manual: CRC State Structure definition

Enumerations
CRC State Structure definition
CRC Exported Types

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef
Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 66 of file stm32f4xx_hal_crc.h.

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STM32F410Rx HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Handle Structure definition

#include <stm32f4xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State

Detailed Description

Definition at line 82 of file stm32f4xx_hal_crc.h.

Field Documentation

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 84 of file stm32f4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), and HAL_CRC_Init().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC locking object

Definition at line 86 of file stm32f4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 88 of file stm32f4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), and HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_crc.h
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STM32F410Rx HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Resets CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Resets CRC Data Register.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Stores a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 8-bit data stored in the Independent Data(ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Resets CRC Data Register.

Parameters:
__HANDLE__,: CRC handle
Return values:
None

Definition at line 116 of file stm32f4xx_hal_crc.h.

Referenced by HAL_CRC_Calculate().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Returns the 8-bit data stored in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
Return values:
8-bit value of the ID register

Definition at line 131 of file stm32f4xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Resets CRC handle state.

Parameters:
__HANDLE__,: CRC handle
Return values:
None

Definition at line 109 of file stm32f4xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Stores a 8-bit data in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
__VALUE__,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 124 of file stm32f4xx_hal_crc.h.

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STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
            ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP
      (+) DeInitialize CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitializes the CRC peripheral.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
HAL status

Definition at line 147 of file stm32f4xx_hal_crc.c.

References assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
HAL status

Definition at line 112 of file stm32f4xx_hal_crc.c.

References assert_param, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, CRC_HandleTypeDef::Lock, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitializes the CRC MSP.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
None

Definition at line 195 of file stm32f4xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
None

Definition at line 180 of file stm32f4xx_hal_crc.c.

Referenced by HAL_CRC_Init().

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STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Compute the 32-bit CRC value of 32-bit data buffer,
          using combination of the previous CRC value and the new one.
      (+) Compute the 32-bit CRC value of 32-bit data buffer,
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
pBuffer,: pointer to the buffer containing the data to be computed
BufferLength,: length of the buffer to be computed
Return values:
32-bit CRC

Definition at line 234 of file stm32f4xx_hal_crc.c.

References HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
pBuffer,: Pointer to the buffer containing the data to be computed
BufferLength,: Length of the buffer to be computed
Return values:
32-bit CRC

Definition at line 269 of file stm32f4xx_hal_crc.c.

References __HAL_CRC_DR_RESET, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Returns the CRC state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Returns the CRC state.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
HAL state

Definition at line 324 of file stm32f4xx_hal_crc.c.

References CRC_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: CRC Private Types

CRC Private Types
CRC
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STM32F410Rx HAL User Manual: CRC Private Defines

CRC Private Defines
CRC
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STM32F410Rx HAL User Manual: CRC Private Variables

CRC Private Variables
CRC
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STM32F410Rx HAL User Manual: CRC Private Constants

CRC Private Constants
CRC
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STM32F410Rx HAL User Manual: CRC Private Macros

CRC Private Macros
CRC
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STM32F410Rx HAL User Manual: CRC Private Functions Prototypes

CRC Private Functions Prototypes
CRC
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: CRC Private Functions

CRC Private Functions
CRC
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STM32F410Rx HAL User Manual: CRYP

CRYP
STM32F4xx_HAL_Driver

CRYP HAL module driver. More...

CRYP HAL module driver.

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STM32F410Rx HAL User Manual: CRYPEx

CRYPEx
STM32F4xx_HAL_Driver

CRYP Extension HAL module driver. More...

CRYP Extension HAL module driver.

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STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitializes the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initializes the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitializes the DAC MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitializes the DAC peripheral registers to their default reset values.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 269 of file stm32f4xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 232 of file stm32f4xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, DAC_HandleTypeDef::Lock, and DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitializes the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 320 of file stm32f4xx_hal_dac.c.

Referenced by HAL_DAC_DeInit().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initializes the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 305 of file stm32f4xx_hal_dac.c.

Referenced by HAL_DAC_Init().

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STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
DAC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.

Function Documentation

__weak void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 689 of file stm32f4xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1().

__weak void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 704 of file stm32f4xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1().

__weak void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 734 of file stm32f4xx_hal_dac.c.

Referenced by HAL_DAC_IRQHandler().

__weak void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 719 of file stm32f4xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1().

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 621 of file stm32f4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 643 of file stm32f4xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 361 of file stm32f4xx_hal_dac.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData,: The destination peripheral Buffer address.
Length,: The length of data to be transferred from memory to DAC peripheral
Alignment,: Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 452 of file stm32f4xx_hal_dac.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 420 of file stm32f4xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 571 of file stm32f4xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, DAC_CHANNEL_1, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC configuration structure.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 773 of file stm32f4xx_hal_dac.c.

References assert_param, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_ChannelConfTypeDef::DAC_Trigger, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_TRIGGER, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Alignment,: Specifies the data alignment. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data,: Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 829 of file stm32f4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

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STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DAC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

Peripheral State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Errors functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 689 of file stm32f4xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 704 of file stm32f4xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 734 of file stm32f4xx_hal_dac.c.

Referenced by HAL_DAC_IRQHandler().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 719 of file stm32f4xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1().

uint32_t HAL_DAC_GetError ( DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 894 of file stm32f4xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( DAC_HandleTypeDef * hdac )

return the DAC state

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 881 of file stm32f4xx_hal_dac.c.

References DAC_HandleTypeDef::State.

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 643 of file stm32f4xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: DAC Exported Functions

Modules | Functions
DAC Exported Functions
DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 909 of file stm32f4xx_hal_dac.c.

References HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 937 of file stm32f4xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 924 of file stm32f4xx_hal_dac.c.

References HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Exported Types

Data Structures | Enumerations
DAC Exported Types
DAC

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 70 of file stm32f4xx_hal_dac.h.

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STM32F410Rx HAL User Manual: DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32f4xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode

Detailed Description

DAC handle Structure definition.

Definition at line 82 of file stm32f4xx_hal_dac.h.

Field Documentation

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1

Definition at line 90 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2

Definition at line 92 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

__IO uint32_t DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 94 of file stm32f4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), and HAL_DAC_IRQHandler().

DAC_TypeDef* DAC_HandleTypeDef::Instance

Register base address

Definition at line 84 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 88 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Init().

__IO HAL_DAC_StateTypeDef DAC_HandleTypeDef::State

DAC communication state

Definition at line 86 of file stm32f4xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_dac.h
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STM32F410Rx HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32f4xx_hal_dac.h>

Data Fields

uint32_t | DAC_Trigger
uint32_t | DAC_OutputBuffer

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 101 of file stm32f4xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC Output Buffer

Definition at line 106 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC Trigger Selection

Definition at line 103 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_dac.h
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STM32F410Rx HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04U

DMA error

Definition at line 124 of file stm32f4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), and DAC_DMAErrorCh2().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U

DAC channel1 DAM underrun error

Definition at line 122 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U

DAC channel2 DAM underrun error

Definition at line 123 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_NONE 0x00U

No error

Definition at line 121 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Trigger Selection

Defines
DAC Trigger Selection
DAC Exported Constants

Defines

#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000U)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))

Define Documentation

#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 142 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U)

Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger

Definition at line 133 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))

Conversion started by software trigger for DAC channel

Definition at line 143 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 135 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 136 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM5 TRGO selected as external conversion trigger for DAC channel

Definition at line 137 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 138 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 139 of file stm32f4xx_hal_dac.h.

#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM8 TRGO selected as external conversion trigger for DAC channel

Definition at line 140 of file stm32f4xx_hal_dac.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Output Buffer

Defines
DAC Output Buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)

Definition at line 152 of file stm32f4xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)

Definition at line 151 of file stm32f4xx_hal_dac.h.

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STM32F410Rx HAL User Manual: DAC Channel Selection

Defines
DAC Channel Selection
DAC Exported Constants

Defines

#define | DAC_CHANNEL_1 ((uint32_t)0x00000000U)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010U)

Define Documentation

#define DAC_CHANNEL_1 ((uint32_t)0x00000000U)

Definition at line 160 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

#define DAC_CHANNEL_2 ((uint32_t)0x00000010U)

Definition at line 161 of file stm32f4xx_hal_dac.h.

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STM32F410Rx HAL User Manual: DAC Data Alignment

Defines
DAC Data Alignment
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008U)

Define Documentation

#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)

Definition at line 170 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)

Definition at line 169 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)

Definition at line 171 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Flags Definition

Defines
DAC Flags Definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 179 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 180 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

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STM32F410Rx HAL User Manual: DAC IT Definition

Defines
DAC IT Definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 188 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 189 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

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STM32F410Rx HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified DAC interrupt source is enabled or disabled.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DMA underrun 1 flag
  • DAC_FLAG_DMAUDR2: DMA underrun 2 flag
Return values:
None

Definition at line 265 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))

Disable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle
__DAC_Channel__,: specifies the DAC channel.
Return values:
None

Definition at line 221 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), and HAL_DAC_Stop_DMA().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt.
Return values:
None

Definition at line 235 of file stm32f4xx_hal_dac.h.

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))

Enable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle.
__DAC_Channel__,: specifies the DAC channel
Return values:
None

Definition at line 214 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start(), and HAL_DAC_Start_DMA().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt.
Return values:
None

Definition at line 228 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DMA underrun 1 flag
  • DAC_FLAG_DMAUDR2: DMA underrun 2 flag
Return values:
None

Definition at line 255 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified DAC interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: DAC handle
__INTERRUPT__,: DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
State of interruption (SET or RESET)

Definition at line 245 of file stm32f4xx_hal_dac.h.

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)

Reset DAC handle state.

Parameters:
__HANDLE__,: specifies the DAC handle.
Return values:
None

Definition at line 207 of file stm32f4xx_hal_dac.h.

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STM32F410Rx HAL User Manual: DAC Private Constants

DAC Private Constants
DAC
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
Set DHR12RD alignment.

Define Documentation

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000008U) + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 370 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000014U) + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 376 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000020U) + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 382 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 348 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_CHANNEL_1) || \
                                 ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 351 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0U)

Definition at line 347 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 353 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_TRIGGER_NONE) || \
                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

Definition at line 356 of file stm32f4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Private Functions

DAC Private Functions
DAC
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extended features functions

Functions
Extended features functions
DAC Exported Functions

Extended features functions. More...

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.

Detailed Description

Extended features functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.
      (+) Get result of dual mode conversion.

Function Documentation

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 272 of file stm32f4xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 287 of file stm32f4xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 317 of file stm32f4xx_hal_dac_ex.c.

Referenced by HAL_DAC_IRQHandler().

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Returns the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 110 of file stm32f4xx_hal_dac_ex.c.

References DAC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values: DAC_ALIGN_8B_R: 8bit right data alignment selected DAC_ALIGN_12B_L: 12bit left data alignment selected DAC_ALIGN_12B_R: 12bit right data alignment selected
Data1,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data2,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 233 of file stm32f4xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 302 of file stm32f4xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2().

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values: DAC_CHANNEL_1 / DAC_CHANNEL_2
Amplitude,: Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 193 of file stm32f4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enables or disables the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values: DAC_CHANNEL_1 / DAC_CHANNEL_2
Amplitude,: Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Return values:
HAL status

Definition at line 145 of file stm32f4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Exported Functions

Modules | Functions
DAC Exported Functions
DACEx

Modules

Extended features functions

Extended features functions.

Functions

__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 332 of file stm32f4xx_hal_dac_ex.c.

References HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 360 of file stm32f4xx_hal_dac_ex.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 347 of file stm32f4xx_hal_dac_ex.c.

References HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

__weak void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 272 of file stm32f4xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2().

__weak void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 287 of file stm32f4xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2().

__weak void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 317 of file stm32f4xx_hal_dac_ex.c.

Referenced by HAL_DAC_IRQHandler().

__weak void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 302 of file stm32f4xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC LFS Run Mask Triangle Amplitude

Defines
DAC LFS Run Mask Triangle Amplitude
DAC Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U)

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 71 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 81 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 82 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 72 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 73 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 74 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 75 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 76 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 77 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 78 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 79 of file stm32f4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 80 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U)

Select max triangle amplitude of 1

Definition at line 83 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023

Definition at line 92 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 127

Definition at line 89 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15

Definition at line 86 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 2047

Definition at line 93 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255

Definition at line 90 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)

Select max triangle amplitude of 3

Definition at line 84 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)

Select max triangle amplitude of 31

Definition at line 87 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095

Definition at line 94 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)

Select max triangle amplitude of 511

Definition at line 91 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63

Definition at line 88 of file stm32f4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)

Select max triangle amplitude of 7

Definition at line 85 of file stm32f4xx_hal_dac_ex.h.

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STM32F410Rx HAL User Manual: DAC Private Constants

DAC Private Constants
DACEx
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DACEx

Defines

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 144 of file stm32f4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DAC Private Functions

Functions
DAC Private Functions
DACEx

Functions

void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 332 of file stm32f4xx_hal_dac_ex.c.

References HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 360 of file stm32f4xx_hal_dac_ex.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 347 of file stm32f4xx_hal_dac_ex.c.

References HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DCMI

DCMI
STM32F4xx_HAL_Driver

DCMI HAL module driver. More...

DCMI HAL module driver.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DCMIEx

DCMIEx
STM32F4xx_HAL_Driver

DCMI Extended HAL module driver. More...

DCMI Extended HAL module driver.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

DMA Exported Types. More...

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_READY_MEM0 = 0x11U, HAL_DMA_STATE_READY_MEM1 = 0x21U,
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31U, HAL_DMA_STATE_READY_HALF_MEM1 = 0x41U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_BUSY_MEM0 = 0x12U,
HAL_DMA_STATE_BUSY_MEM1 = 0x22U, HAL_DMA_STATE_TIMEOUT = 0x03U, HAL_DMA_STATE_ERROR = 0x04U
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...

Detailed Description

DMA Exported Types.

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 139 of file stm32f4xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_READY_MEM0

DMA Mem0 process success

HAL_DMA_STATE_READY_MEM1

DMA Mem1 process success

HAL_DMA_STATE_READY_HALF_MEM0

DMA Mem0 Half process success

HAL_DMA_STATE_READY_HALF_MEM1

DMA Mem1 Half process success

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_BUSY_MEM0

DMA Mem0 process is ongoing

HAL_DMA_STATE_BUSY_MEM1

DMA Mem1 process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

HAL_DMA_STATE_ERROR

DMA error state

Definition at line 121 of file stm32f4xx_hal_dma.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32f4xx_hal_dma.h>

Data Fields

uint32_t | Channel
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority
uint32_t | FIFOMode
uint32_t | FIFOThreshold
uint32_t | MemBurst
uint32_t | PeriphBurst

Detailed Description

DMA Configuration Structure definition.

Definition at line 67 of file stm32f4xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Channel

Specifies the channel used for the specified stream. This parameter can be a value of DMA Channel selection

Definition at line 69 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 72 of file stm32f4xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), DMA_SetConfig(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::FIFOMode

Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of DMA FIFO direct mode

Note:
The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream

Definition at line 96 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::FIFOThreshold

Specifies the FIFO threshold level. This parameter can be a value of DMA FIFO threshold level

Definition at line 101 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemBurst

Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of DMA Memory burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 104 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 85 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 79 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Streamx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Stream

Definition at line 88 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphBurst

Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of DMA Peripheral burst

Note:
The burst mode is possible only if the address Increment mode is enabled.

Definition at line 110 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 82 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 76 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Streamx. This parameter can be a value of DMA Priority level

Definition at line 93 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_dma.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32f4xx_hal_dma.h>

Data Fields

DMA_Stream_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferM1CpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
uint32_t | StreamBaseAddress
uint32_t | StreamIndex

Detailed Description

DMA handle Structure definition.

Definition at line 148 of file stm32f4xx_hal_dma.h.

Field Documentation

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 168 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 152 of file stm32f4xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), DMA_SetConfig(), and HAL_DMA_Init().

DMA_Stream_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 150 of file stm32f4xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), DMA_MultiBufferSetConfig(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ChangeMemory(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), I2S_DMARxCplt(), I2S_DMATxCplt(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 154 of file stm32f4xx_hal_dma.h.

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 158 of file stm32f4xx_hal_dma.h.

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 156 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

uint32_t __DMA_HandleTypeDef::StreamBaseAddress

DMA Stream Base Address

Definition at line 170 of file stm32f4xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

uint32_t __DMA_HandleTypeDef::StreamIndex

DMA Stream Index

Definition at line 172 of file stm32f4xx_hal_dma.h.

Referenced by DMA_CalcBaseAndBitshift(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 160 of file stm32f4xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_IRQHandler(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Transmit_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 166 of file stm32f4xx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), ADC_MultiModeDMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_IRQHandler(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Transmit_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 162 of file stm32f4xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DMA_IRQHandler(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete Memory1 callback

Definition at line 164 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_dma.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

DMA Error Code. More...

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
#define | HAL_DMA_ERROR_FE ((uint32_t)0x00000002U)
#define | HAL_DMA_ERROR_DME ((uint32_t)0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Detailed Description

DMA Error Code.

Define Documentation

#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U)

Direct Mode error

Definition at line 193 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U)

FIFO error

Definition at line 192 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 190 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), and HAL_DMA_IRQHandler().

#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)

Transfer error

Definition at line 191 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Timeout error

Definition at line 194 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), and HAL_DMA_PollForTransfer().

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STM32F410Rx HAL User Manual: DMA Channel selection

Defines
DMA Channel selection
DMA Exported Constants

DMA channel selection. More...

Defines

#define | DMA_CHANNEL_0 ((uint32_t)0x00000000U)
#define | DMA_CHANNEL_1 ((uint32_t)0x02000000U)
#define | DMA_CHANNEL_2 ((uint32_t)0x04000000U)
#define | DMA_CHANNEL_3 ((uint32_t)0x06000000U)
#define | DMA_CHANNEL_4 ((uint32_t)0x08000000U)
#define | DMA_CHANNEL_5 ((uint32_t)0x0A000000U)
#define | DMA_CHANNEL_6 ((uint32_t)0x0C000000U)
#define | DMA_CHANNEL_7 ((uint32_t)0x0E000000U)

Detailed Description

DMA channel selection.

Define Documentation

#define DMA_CHANNEL_0 ((uint32_t)0x00000000U)

DMA Channel 0

Definition at line 203 of file stm32f4xx_hal_dma.h.

#define DMA_CHANNEL_1 ((uint32_t)0x02000000U)

DMA Channel 1

Definition at line 204 of file stm32f4xx_hal_dma.h.

#define DMA_CHANNEL_2 ((uint32_t)0x04000000U)

DMA Channel 2

Definition at line 205 of file stm32f4xx_hal_dma.h.

#define DMA_CHANNEL_3 ((uint32_t)0x06000000U)

DMA Channel 3

Definition at line 206 of file stm32f4xx_hal_dma.h.

#define DMA_CHANNEL_4 ((uint32_t)0x08000000U)

DMA Channel 4

Definition at line 207 of file stm32f4xx_hal_dma.h.

#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U)

DMA Channel 5

Definition at line 208 of file stm32f4xx_hal_dma.h.

#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U)

DMA Channel 6

Definition at line 209 of file stm32f4xx_hal_dma.h.

#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U)

DMA Channel 7

Definition at line 210 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

DMA data transfer direction. More...

Defines

#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Detailed Description

DMA data transfer direction.

Define Documentation

#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)

Memory to memory direction

Definition at line 221 of file stm32f4xx_hal_dma.h.

#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)

Memory to peripheral direction

Definition at line 220 of file stm32f4xx_hal_dma.h.

Referenced by DMA_MultiBufferSetConfig(), and DMA_SetConfig().

#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)

Peripheral to memory direction

Definition at line 219 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

DMA peripheral incremented mode. More...

Defines

#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000U)

Detailed Description

DMA peripheral incremented mode.

Define Documentation

#define DMA_PINC_DISABLE ((uint32_t)0x00000000U)

Peripheral increment mode disable

Definition at line 231 of file stm32f4xx_hal_dma.h.

#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)

Peripheral increment mode enable

Definition at line 230 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

DMA memory incremented mode. More...

Defines

#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000U)

Detailed Description

DMA memory incremented mode.

Define Documentation

#define DMA_MINC_DISABLE ((uint32_t)0x00000000U)

Memory increment mode disable

Definition at line 241 of file stm32f4xx_hal_dma.h.

#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)

Memory increment mode enable

Definition at line 240 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

DMA peripheral data size. More...

Defines

#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Detailed Description

DMA peripheral data size.

Define Documentation

#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)

Peripheral data alignment: Byte

Definition at line 250 of file stm32f4xx_hal_dma.h.

#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)

Peripheral data alignment: HalfWord

Definition at line 251 of file stm32f4xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)

Peripheral data alignment: Word

Definition at line 252 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

DMA memory data size. More...

Defines

#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Detailed Description

DMA memory data size.

Define Documentation

#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)

Memory data alignment: Byte

Definition at line 261 of file stm32f4xx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)

Memory data alignment: HalfWord

Definition at line 262 of file stm32f4xx_hal_dma.h.

#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)

Memory data alignment: Word

Definition at line 263 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

DMA mode. More...

Defines

#define | DMA_NORMAL ((uint32_t)0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)

Detailed Description

DMA mode.

Define Documentation

#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)

Circular mode

Definition at line 273 of file stm32f4xx_hal_dma.h.

#define DMA_NORMAL ((uint32_t)0x00000000U)

Normal mode

Definition at line 272 of file stm32f4xx_hal_dma.h.

#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)

Peripheral flow control mode

Definition at line 274 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

DMA priority levels. More...

Defines

#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Detailed Description

DMA priority levels.

Define Documentation

#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)

Priority level: High

Definition at line 285 of file stm32f4xx_hal_dma.h.

#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U)

Priority level: Low

Definition at line 283 of file stm32f4xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)

Priority level: Medium

Definition at line 284 of file stm32f4xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)

Priority level: Very High

Definition at line 286 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA FIFO direct mode

Defines
DMA FIFO direct mode
DMA Exported Constants

DMA FIFO direct mode. More...

Defines

#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

Detailed Description

DMA FIFO direct mode.

Define Documentation

#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)

FIFO mode disable

Definition at line 295 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)

FIFO mode enable

Definition at line 296 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

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STM32F410Rx HAL User Manual: DMA FIFO threshold level

Defines
DMA FIFO threshold level
DMA Exported Constants

DMA FIFO level. More...

Defines

#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

Detailed Description

DMA FIFO level.

Define Documentation

#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)

FIFO threshold 1 quart full configuration

Definition at line 305 of file stm32f4xx_hal_dma.h.

#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)

FIFO threshold 3 quarts full configuration

Definition at line 307 of file stm32f4xx_hal_dma.h.

#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)

FIFO threshold full configuration

Definition at line 308 of file stm32f4xx_hal_dma.h.

#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)

FIFO threshold half full configuration

Definition at line 306 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Memory burst

Defines
DMA Memory burst
DMA Exported Constants

DMA memory burst. More...

Defines

#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Detailed Description

DMA memory burst.

Define Documentation

#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)

Definition at line 320 of file stm32f4xx_hal_dma.h.

#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)

Definition at line 318 of file stm32f4xx_hal_dma.h.

#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)

Definition at line 319 of file stm32f4xx_hal_dma.h.

#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)

Definition at line 317 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA Peripheral burst

Defines
DMA Peripheral burst
DMA Exported Constants

DMA peripheral burst. More...

Defines

#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Detailed Description

DMA peripheral burst.

Define Documentation

#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)

Definition at line 332 of file stm32f4xx_hal_dma.h.

#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)

Definition at line 330 of file stm32f4xx_hal_dma.h.

#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)

Definition at line 331 of file stm32f4xx_hal_dma.h.

#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)

Definition at line 329 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

DMA interrupts definition. More...

Defines

#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080U)

Detailed Description

DMA interrupts definition.

Define Documentation

#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)

Definition at line 344 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_FE ((uint32_t)0x00000080U)

Definition at line 345 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)

Definition at line 342 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)

Definition at line 341 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)

Definition at line 343 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), HAL_DMA_Start_IT(), and HAL_DMAEx_MultiBufferStart_IT().

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STM32F410Rx HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

DMA flag definitions. More...

Defines

#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)

Detailed Description

DMA flag definitions.

Define Documentation

#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)

Definition at line 355 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)

Definition at line 360 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)

Definition at line 365 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)

Definition at line 370 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)

Definition at line 354 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)

Definition at line 359 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)

Definition at line 364 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)

Definition at line 369 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)

Definition at line 357 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)

Definition at line 362 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)

Definition at line 367 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)

Definition at line 372 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)

Definition at line 358 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)

Definition at line 363 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)

Definition at line 368 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)

Definition at line 373 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)

Definition at line 356 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)

Definition at line 361 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)

Definition at line 366 of file stm32f4xx_hal_dma.h.

#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)

Definition at line 371 of file stm32f4xx_hal_dma.h.

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STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Stream source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitializes the DMA peripheral.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 282 of file stm32f4xx_hal_dma.c.

References __HAL_DMA_DISABLE, DMA_CalcBaseAndBitshift(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_RESET, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 186 of file stm32f4xx_hal_dma.c.

References assert_param, DMA_InitTypeDef::Channel, DMA_InitTypeDef::Direction, DMA_CalcBaseAndBitshift(), DMA_FIFOMODE_DISABLE, DMA_FIFOMODE_ENABLE, __DMA_HandleTypeDef::ErrorCode, DMA_InitTypeDef::FIFOMode, DMA_InitTypeDef::FIFOThreshold, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_CHANNEL, IS_DMA_DIRECTION, IS_DMA_FIFO_MODE_STATE, IS_DMA_FIFO_THRESHOLD, IS_DMA_MEMORY_BURST, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_BURST, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, DMA_InitTypeDef::MemBurst, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphBurst, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, and __DMA_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I/O operation functions

Functions
I/O operation functions
DMA Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.

Detailed Description

I/O operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Note:
After disabling a DMA Stream, a check for wait until the DMA Stream is effectively disabled is added. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
Return values:
HAL status

Definition at line 439 of file stm32f4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_STATE_READY, HAL_DMA_STATE_TIMEOUT, HAL_GetTick(), HAL_TIMEOUT_DMA_ABORT, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_DAC_Stop_DMA(), HAL_I2S_DMAStop(), HAL_IRDA_DMAStop(), HAL_SPI_DMAStop(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_UART_DMAStop(), and HAL_USART_DMAStop().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMA interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
None

Definition at line 633 of file stm32f4xx_hal_dma.c.

References __HAL_DMA_DISABLE_IT, __HAL_DMA_GET_IT_SOURCE, DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_NONE, HAL_DMA_ERROR_TE, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY_HALF_MEM0, HAL_DMA_STATE_READY_HALF_MEM1, HAL_DMA_STATE_READY_MEM0, DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, DMA_Base_Registers::ISR, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, __DMA_HandleTypeDef::StreamIndex, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __DMA_HandleTypeDef::XferM1CpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CompleteLevel,: Specifies the DMA level complete.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 484 of file stm32f4xx_hal_dma.c.

References DMA_FLAG_DMEIF0_4, DMA_FLAG_FEIF0_4, DMA_FLAG_HTIF0_4, DMA_FLAG_TCIF0_4, DMA_FLAG_TEIF0_4, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_DME, HAL_DMA_ERROR_FE, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_ERROR, HAL_DMA_STATE_READY_HALF_MEM0, HAL_DMA_STATE_READY_HALF_MEM1, HAL_DMA_STATE_READY_MEM0, HAL_DMA_STATE_READY_MEM1, HAL_DMA_STATE_TIMEOUT, HAL_GetTick(), DMA_Base_Registers::IFCR, __DMA_HandleTypeDef::Instance, DMA_Base_Registers::ISR, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 368 of file stm32f4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), HAL_DMA_STATE_BUSY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 400 of file stm32f4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), HAL_DMA_STATE_BUSY, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Transmit_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2S_Receive_DMA(), HAL_I2S_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
DMA Exported Functions

Peripheral State functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                    ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
DMA Error Code

Definition at line 862 of file stm32f4xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Returns the DMA state.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL state

Definition at line 851 of file stm32f4xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA Private Constants

Defines
DMA Private Constants
DMA

DMA private defines and constants. More...

Defines

#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */

Detailed Description

DMA private defines and constants.

Define Documentation

#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */

Definition at line 140 of file stm32f4xx_hal_dma.c.

Referenced by HAL_DMA_Abort().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

DMA private macros. More...

Defines

#define | IS_DMA_CHANNEL(CHANNEL)
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Detailed Description

DMA private macros.

Define Documentation

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))

Definition at line 702 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define IS_DMA_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DMA_CHANNEL_0) || \
                                 ((CHANNEL) == DMA_CHANNEL_1) || \
                                 ((CHANNEL) == DMA_CHANNEL_2) || \
                                 ((CHANNEL) == DMA_CHANNEL_3) || \
                                 ((CHANNEL) == DMA_CHANNEL_4) || \
                                 ((CHANNEL) == DMA_CHANNEL_5) || \
                                 ((CHANNEL) == DMA_CHANNEL_6) || \
                                 ((CHANNEL) == DMA_CHANNEL_7))

Definition at line 689 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 698 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_MODE_STATE ( STATE )
Value:
(((STATE) == DMA_FIFOMODE_DISABLE ) || \
                                       ((STATE) == DMA_FIFOMODE_ENABLE))

Definition at line 727 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))

Definition at line 730 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_BURST ( BURST )
Value:
(((BURST) == DMA_MBURST_SINGLE) || \
                                    ((BURST) == DMA_MBURST_INC4)   || \
                                    ((BURST) == DMA_MBURST_INC8)   || \
                                    ((BURST) == DMA_MBURST_INC16))

Definition at line 735 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 714 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 707 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                           ((MODE) == DMA_CIRCULAR) || \
                           ((MODE) == DMA_PFCTRL))

Definition at line 718 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_BURST ( BURST )
Value:
(((BURST) == DMA_PBURST_SINGLE) || \
                                        ((BURST) == DMA_PBURST_INC4)   || \
                                        ((BURST) == DMA_PBURST_INC8)   || \
                                        ((BURST) == DMA_PBURST_INC16))

Definition at line 740 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 710 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 704 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 722 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

DMA private functions. More...

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static uint32_t | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.

Detailed Description

DMA private functions.

Function Documentation

static uint32_t DMA_CalcBaseAndBitshift ( DMA_HandleTypeDef * hdma ) [static]

Returns the DMA Stream base address depending on stream number.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
Stream base address

Definition at line 922 of file stm32f4xx_hal_dma.c.

References __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::StreamBaseAddress, and __DMA_HandleTypeDef::StreamIndex.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 888 of file stm32f4xx_hal_dma.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA

Data Structures | Modules | Defines
DMA
STM32F4xx_HAL_Driver

DMA HAL module driver. More...

Data Structures

struct | DMA_Base_Registers

Modules

DMA Exported Types

DMA Exported Types.

DMA Exported Constants

DMA Exported constants.

DMA Exported Functions

DMA Exported functions.

DMA Private Constants

DMA private defines and constants.

DMA Private Macros

DMA private macros.

DMA Private Functions

DMA private functions.

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or disabled.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Returns the number of remaining data units in the current DMAy Streamx transfer.

Detailed Description

DMA HAL module driver.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))

Clear the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
None

Definition at line 551 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)

Disable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 416 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))

Disable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 583 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define __HAL_DMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)

Enable the specified DMA Stream.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 409 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))

Enable the specified DMA Stream interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
None

Definition at line 568 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMAEx_MultiBufferStart_IT().

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->NDTR)

Returns the number of remaining data units in the current DMAy Streamx transfer.

Parameters:
__HANDLE__,: DMA handle
Return values:
The number of remaining data units in the current DMA Stream transfer.

Definition at line 627 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_GET_DME_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
   DMA_FLAG_DMEIF3_7)

Return the current DMA Stream direct mode error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified direct mode error flag index.

Definition at line 505 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_GET_FE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
   DMA_FLAG_FEIF3_7)

Return the current DMA Stream FIFO error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified FIFO error flag index.

Definition at line 485 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))

Get the DMA Stream pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCIFx: Transfer complete flag.
  • DMA_FLAG_HTIFx: Half transfer complete flag.
  • DMA_FLAG_TEIFx: Transfer error flag.
  • DMA_FLAG_DMEIFx: Direct mode error flag.
  • DMA_FLAG_FEIFx: FIFO error flag. Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 533 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_GET_FS ( __HANDLE__ ) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))

Return the current DMA Stream FIFO filled level.

Parameters:
__HANDLE__,: DMA handle
Return values:
The FIFO filling state.
  • DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
  • DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
  • DMA_FIFOStatus_HalfFull: if more than 1 half-full.
  • DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
  • DMA_FIFOStatus_Empty: when FIFO is empty
  • DMA_FIFOStatus_Full: when FIFO is full

Definition at line 402 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
   DMA_FLAG_HTIF3_7)

Return the current DMA Stream half transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 445 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) != DMA_IT_FE)? \
                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))

Check whether the specified DMA Stream interrupt is enabled or disabled.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask.
  • DMA_IT_HT: Half transfer complete interrupt mask.
  • DMA_IT_TE: Transfer error interrupt mask.
  • DMA_IT_FE: FIFO error interrupt mask.
  • DMA_IT_DME: Direct mode error interrupt.
Return values:
The state of DMA_IT.

Definition at line 598 of file stm32f4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
   DMA_FLAG_TCIF3_7)

Return the current DMA Stream transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 425 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
   DMA_FLAG_TEIF3_7)

Return the current DMA Stream transfer error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 465 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__,: specifies the DMA handle.
Return values:
None

Definition at line 388 of file stm32f4xx_hal_dma.h.

#define __HAL_DMA_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))

Writes the number of data units to be transferred on the DMA Stream.

Parameters:
__HANDLE__,: DMA handle
__COUNTER__,: Number of data units to be transferred (from 0 to 65535) Number of data items depends only on the Peripheral data format.
Note:
If Peripheral data format is Bytes: number of data units is equal to total number of bytes to be transferred.
If Peripheral data format is Half-Word: number of data units is equal to total number of bytes to be transferred / 2.
If Peripheral data format is Word: number of data units is equal to total number of bytes to be transferred / 4.
Return values:
The number of remaining data units in the current DMAy Streamx transfer.

Definition at line 619 of file stm32f4xx_hal_dma.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA_Base_Registers Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_Base_Registers Struct Reference
DMA

Data Fields

__IO uint32_t | ISR
__IO uint32_t | Reserved0
__IO uint32_t | IFCR

Detailed Description

Definition at line 128 of file stm32f4xx_hal_dma.c.

Field Documentation

__IO uint32_t DMA_Base_Registers::IFCR

DMA interrupt flag clear register

Definition at line 132 of file stm32f4xx_hal_dma.c.

Referenced by HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

__IO uint32_t DMA_Base_Registers::ISR

DMA interrupt status register

Definition at line 130 of file stm32f4xx_hal_dma.c.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

__IO uint32_t DMA_Base_Registers::Reserved0

Definition at line 131 of file stm32f4xx_hal_dma.c.

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_dma.c
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMAEx Exported Types

Enumerations
DMAEx Exported Types
DMAEx

DMAEx Exported types. More...

Enumerations

enum HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00U, MEMORY1 = 0x01U }
HAL DMA Memory definition. More...

Detailed Description

DMAEx Exported types.

Enumeration Type Documentation

enum HAL_DMA_MemoryTypeDef

HAL DMA Memory definition.

Enumerator:
MEMORY0

Memory 0

MEMORY1

Memory 1

Definition at line 66 of file stm32f4xx_hal_dma_ex.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extended features functions

Functions
Extended features functions
DMAEx Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.

Detailed Description

Extended features functions.

 ===============================================================================
                #####  Extended features functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer
      (+) Configure the source, destination address and data length and
          Start MultiBuffer DMA transfer with interrupt
      (+) Change on the fly the memory0 or memory1 address.

Function Documentation

HAL_StatusTypeDef HAL_DMAEx_ChangeMemory | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | Address,
 |  | HAL_DMA_MemoryTypeDef | memory
 | ) |  |

Change the memory0 or memory1 address on the fly.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Address,: The new address
memory,: the memory to be changed, This parameter can be one of the following values: MEMORY0 / MEMORY1
Note:
The MEMORY0 address can be changed only when the current transfer use MEMORY1 and the MEMORY1 address can be changed only when the current transfer use MEMORY0.
Return values:
HAL status

Definition at line 232 of file stm32f4xx_hal_dma_ex.c.

References __DMA_HandleTypeDef::Instance, and MEMORY0.

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 119 of file stm32f4xx_hal_dma_ex.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_MultiBufferSetConfig(), HAL_DMA_STATE_BUSY_MEM0, HAL_DMA_STATE_BUSY_MEM1, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | SecondMemAddress,
 |  | uint32_t | DataLength
 | ) |  |

Starts the multi_buffer DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
SecondMemAddress,: The second memory Buffer address in case of multi buffer Transfer
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 166 of file stm32f4xx_hal_dma_ex.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, __HAL_DMA_ENABLE_IT, assert_param, DMA_IT_DME, DMA_IT_FE, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_MultiBufferSetConfig(), HAL_DMA_STATE_BUSY_MEM0, HAL_DMA_STATE_BUSY_MEM1, __DMA_HandleTypeDef::Instance, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMAEx Private Functions

Functions
DMAEx Private Functions
DMAEx

DMAEx Private functions. More...

Functions

static void DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.

Detailed Description

DMAEx Private functions.

Function Documentation

static void DMA_MultiBufferSetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Set the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 269 of file stm32f4xx_hal_dma_ex.c.

References DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMAEx_MultiBufferStart(), and HAL_DMAEx_MultiBufferStart_IT().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ETH

ETH
STM32F4xx_HAL_Driver

ETH HAL module driver. More...

ETH HAL module driver.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue,: The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Sectors Erase: Sector which has been erased (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) Program: Address which was selected for data program
Return values:
None

Definition at line 397 of file stm32f4xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

This function handles FLASH interrupt request.

Return values:
None

Definition at line 279 of file stm32f4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::Bank, FLASH_Erase_Sector(), FLASH_FLAG_EOP, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_PGSERR, FLASH_FLAG_RDERR, FLASH_FLAG_WRPERR, FLASH_FlushCaches(), FLASH_IT_EOP, FLASH_IT_ERR, FLASH_MER_BIT, FLASH_PROC_MASSERASE, FLASH_PROC_NONE, FLASH_PROC_SECTERASE, FLASH_SetErrorCode(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_ProcessTypeDef::Sector, and FLASH_ProcessTypeDef::VoltageForErase.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue,: The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Sectors Erase: Sector number which returned an error Program: Address which was selected for data program
Return values:
None

Definition at line 414 of file stm32f4xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program byte, halfword, word or double word at a specified address.

Parameters:
TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 174 of file stm32f4xx_hal_flash.c.

References assert_param, FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), FLASH_Program_Word(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_BYTE, FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, FLASH_WaitForLastOperation(), and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program byte, halfword, word or double word at a specified address with interrupt enabled.

Parameters:
TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed
Return values:
HAL Status

Definition at line 232 of file stm32f4xx_hal_flash.c.

References __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_PROC_PROGRAM, FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), FLASH_Program_Word(), FLASH_TYPEPROGRAM_BYTE, FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Locks the FLASH control register access.

Return values:
HAL Status

Definition at line 466 of file stm32f4xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL Status

Definition at line 510 of file stm32f4xx_hal_flash.c.

References FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and OPTCR_BYTE0_ADDRESS.

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 498 of file stm32f4xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 478 of file stm32f4xx_hal_flash.c.

References FLASH_OPT_KEY1, and FLASH_OPT_KEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL Status

Definition at line 446 of file stm32f4xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Exported Functions

Peripheral Errors functions. More...

Functions

uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operationtimeout
Return values:
HAL Status

Definition at line 561 of file stm32f4xx_hal_flash.c.

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode,: The returned value can be a combination of:
  • HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
  • HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
  • HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
  • HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
  • HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
  • HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag

Definition at line 547 of file stm32f4xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

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STM32F410Rx HAL User Manual: FLASH Exported Functions

Modules | Functions
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

management functions

Peripheral State and Errors functions

Peripheral Errors functions.

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program a double word (64-bit) at a specified address.
static void | FLASH_Program_Word (uint32_t Address, uint32_t Data)
Program word (32-bit) at a specified address.
static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_Program_Byte (uint32_t Address, uint8_t Data)
Program byte (8-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.

Function Documentation

static void FLASH_Program_Byte | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  | [static]

Program byte (8-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 1.8V to 3.6V.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 693 of file stm32f4xx_hal_flash.c.

References assert_param, FLASH_PSIZE_BYTE, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_DoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  | [static]

Program a double word (64-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 2.7V to 3.6V and Vpp in the range 7V to 9V.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 617 of file stm32f4xx_hal_flash.c.

References assert_param, FLASH_PSIZE_DOUBLE_WORD, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_HalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  | [static]

Program a half-word (16-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 2.1V to 3.6V.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 668 of file stm32f4xx_hal_flash.c.

References assert_param, FLASH_PSIZE_HALF_WORD, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_Word | ( | uint32_t | Address,
 |  | uint32_t | Data
 | ) |  | [static]

Program word (32-bit) at a specified address.

Note:
This function must be used when the device voltage range is from 2.7V to 3.6V.
If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 643 of file stm32f4xx_hal_flash.c.

References assert_param, FLASH_PSIZE_WORD, and IS_FLASH_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_SetErrorCode ( void ) [static]

Set the specific FLASH error flag.

Return values:
None

Definition at line 710 of file stm32f4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_PGSERR, FLASH_FLAG_RDERR, FLASH_FLAG_WRPERR, HAL_FLASH_ERROR_OPERATION, HAL_FLASH_ERROR_PGA, HAL_FLASH_ERROR_PGP, HAL_FLASH_ERROR_PGS, HAL_FLASH_ERROR_RD, and HAL_FLASH_ERROR_WRP.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operationtimeout
Return values:
HAL Status

Definition at line 561 of file stm32f4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_BSY, FLASH_FLAG_EOP, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_PGSERR, FLASH_FLAG_RDERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), HAL_FLASH_ERROR_NONE, and HAL_GetTick().

Referenced by FLASH_OB_DisablePCROP(), FLASH_OB_DisableWRP(), FLASH_OB_EnablePCROP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

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STM32F410Rx HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum | FLASH_ProcedureTypeDef { FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM }
FLASH Procedure structure definition. More...

Enumeration Type Documentation

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_SECTERASE
FLASH_PROC_MASSERASE
FLASH_PROC_PROGRAM

Definition at line 65 of file stm32f4xx_hal_flash.h.

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STM32F410Rx HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32f4xx_hal_flash.h>

Data Fields

__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | NbSectorsToErase
__IO uint8_t | VoltageForErase
__IO uint32_t | Sector
__IO uint32_t | Bank
__IO uint32_t | Address
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

FLASH handle Structure definition.

Definition at line 76 of file stm32f4xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Definition at line 88 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::Bank

Definition at line 86 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

Definition at line 92 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_GetError().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

Definition at line 90 of file stm32f4xx_hal_flash.h.

__IO uint32_t FLASH_ProcessTypeDef::NbSectorsToErase

Definition at line 80 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Definition at line 78 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::Sector

Definition at line 84 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint8_t FLASH_ProcessTypeDef::VoltageForErase

Definition at line 82 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_flash.h
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STM32F410Rx HAL User Manual: FLASH Error Code

Defines
FLASH Error Code
FLASH Exported Constants

FLASH Error Code. More...

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FLASH_ERROR_RD ((uint32_t)0x00000001U)
#define | HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U)
#define | HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U)
#define | HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U)
#define | HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U)

Detailed Description

FLASH Error Code.

Define Documentation

#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 108 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U)

Operation Error

Definition at line 114 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U)

Programming Alignment error

Definition at line 112 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U)

Programming Parallelism error

Definition at line 111 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U)

Programming Sequence error

Definition at line 110 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000001U)

Read Protection error

Definition at line 109 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U)

Write protection error

Definition at line 113 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

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STM32F410Rx HAL User Manual: FLASH Type Program

Defines
FLASH Type Program
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U)
#define | FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U)
#define | FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U)
#define | FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U)

Define Documentation

#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U)

Program byte (8-bit) at a specified address

Definition at line 122 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U)

Program a double word (64-bit) at a specified address

Definition at line 125 of file stm32f4xx_hal_flash.h.

#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U)

Program a half-word (16-bit) at a specified address

Definition at line 123 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U)

Program a word (32-bit) at a specified address

Definition at line 124 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

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STM32F410Rx HAL User Manual: FLASH Flag definition

Defines
FLASH Flag definition
FLASH Exported Constants

Flag definition. More...

Defines

#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_SOP
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_PGPERR FLASH_SR_PGPERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_RDERR ((uint32_t)0x00000100U)
#define | FLASH_FLAG_BSY FLASH_SR_BSY

Detailed Description

Flag definition.

Define Documentation

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 141 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of Operation flag

Definition at line 134 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_OPERR FLASH_SR_SOP

FLASH operation Error flag

Definition at line 135 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR

FLASH Programming Alignment error flag

Definition at line 137 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR

FLASH Programming Parallelism error flag

Definition at line 138 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR

FLASH Programming Sequence error flag

Definition at line 139 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

#define FLASH_FLAG_RDERR ((uint32_t)0x00000100U)

Read Protection error flag (PCROP)

Definition at line 140 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

FLASH Write protected error flag

Definition at line 136 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Interrupt definition

Defines
FLASH Interrupt definition
FLASH Exported Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR ((uint32_t)0x02000000U)

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_EOP FLASH_CR_EOPIE

End of FLASH Operation Interrupt source

Definition at line 150 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_ERR ((uint32_t)0x02000000U)

Error Interrupt source

Definition at line 151 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Program Parallelism

Defines
FLASH Program Parallelism
FLASH Exported Constants

Defines

#define | FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define | FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U)
#define | FLASH_PSIZE_WORD ((uint32_t)0x00000200U)
#define | FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U)
#define | CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)

Define Documentation

#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)

Definition at line 163 of file stm32f4xx_hal_flash.h.

#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)

Definition at line 159 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_Byte().

#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U)

Definition at line 162 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_DoubleWord().

#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U)

Definition at line 160 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_HalfWord().

#define FLASH_PSIZE_WORD ((uint32_t)0x00000200U)

Definition at line 161 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_Erase_Sector(), and FLASH_Program_Word().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | RDP_KEY ((uint16_t)0x00A5U)
#define | FLASH_KEY1 ((uint32_t)0x45670123U)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define | FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define | FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)

Define Documentation

#define FLASH_KEY1 ((uint32_t)0x45670123U)

Definition at line 172 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)

Definition at line 173 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)

Definition at line 174 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)

Definition at line 175 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define RDP_KEY ((uint16_t)0x00A5U)

Definition at line 171 of file stm32f4xx_hal_flash.h.

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STM32F410Rx HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Resets the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Resets the FLASH data Cache.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))==(__FLAG__))
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
Clear the specified FLASH flag.

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ ) (FLASH->SR = (__FLAG__))

Clear the specified FLASH flag.

Parameters:
__FLAG__,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP : FLASH End of Operation flag
  • FLASH_FLAG_OPERR : FLASH operation Error flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
  • FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
  • FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
Return values:
none

Definition at line 305 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_DATA_CACHE_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_DCEN))

Disable the FLASH data cache.

Return values:
none

Definition at line 237 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_DATA_CACHE_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_DCEN)

Enable the FLASH data cache.

Return values:
none

Definition at line 231 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_DATA_CACHE_RESET ( )
Value:
do {FLASH->ACR |= FLASH_ACR_DCRST;  \
                                           FLASH->ACR &= ~FLASH_ACR_DCRST; \
                                          }while(0)

Resets the FLASH data Cache.

Note:
This function must be used only when the data Cache is disabled.
Return values:
None

Definition at line 253 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ ) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_ERR: Error Interrupt
Return values:
none

Definition at line 274 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ ) (FLASH->CR |= (__INTERRUPT__))

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ : FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_ERR: Error Interrupt
Return values:
none

Definition at line 264 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ ) ((FLASH->SR & (__FLAG__))==(__FLAG__))

Get the specified FLASH flag status.

Parameters:
__FLAG__,: specifies the FLASH flag to check. This parameter can be one of the following values:
  • FLASH_FLAG_EOP : FLASH End of Operation flag
  • FLASH_FLAG_OPERR : FLASH operation Error flag
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
  • FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
  • FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
  • FLASH_FLAG_BSY : FLASH Busy flag
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 290 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_GET_LATENCY ( ) (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

Get the FLASH Latency.

Return values:
FLASH Latency The value of this parameter depend on device used within the same series

Definition at line 201 of file stm32f4xx_hal_flash.h.

#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_ICEN))

Disable the FLASH instruction cache.

Return values:
none

Definition at line 225 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_ICEN)

Enable the FLASH instruction cache.

Return values:
none

Definition at line 219 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_INSTRUCTION_CACHE_RESET ( )
Value:
do {FLASH->ACR |= FLASH_ACR_ICRST;  \
                                                  FLASH->ACR &= ~FLASH_ACR_ICRST; \
                                                 }while(0)

Resets the FLASH instruction Cache.

Note:
This function must be used only when the Instruction Cache is disabled.
Return values:
None

Definition at line 244 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_PRFTEN))

Disable the FLASH prefetch buffer.

Return values:
none

Definition at line 213 of file stm32f4xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_PRFTEN)

Enable the FLASH prefetch buffer.

Return values:
none

Definition at line 207 of file stm32f4xx_hal_flash.h.

Referenced by HAL_Init().

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__,: FLASH Latency The value of this parameter depend on device used within the same series
Return values:
none

Definition at line 194 of file stm32f4xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 124 of file stm32f4xx_hal_flash.c.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
#define | ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00U)
ACR register byte 0 (Bits[7:0]) base address.
#define | OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14U)
OPTCR register byte 0 (Bits[7:0]) base address.
#define | OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15U)
OPTCR register byte 1 (Bits[15:8]) base address.
#define | OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16U)
OPTCR register byte 2 (Bits[23:16]) base address.
#define | OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17U)
OPTCR register byte 3 (Bits[31:24]) base address.

Define Documentation

#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00U)

ACR register byte 0 (Bits[7:0]) base address.

Definition at line 377 of file stm32f4xx_hal_flash.h.

#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */

Definition at line 114 of file stm32f4xx_hal_flash.c.

Referenced by HAL_FLASH_OB_Launch(), and HAL_FLASH_Program().

#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14U)

OPTCR register byte 0 (Bits[7:0]) base address.

Definition at line 381 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_OB_BOR_LevelConfig(), FLASH_OB_GetBOR(), FLASH_OB_UserConfig(), HAL_FLASH_OB_Launch(), and HAL_FLASHEx_AdvOBGetConfig().

#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15U)

OPTCR register byte 1 (Bits[15:8]) base address.

Definition at line 385 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP(), and FLASH_OB_RDP_LevelConfig().

#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16U)

OPTCR register byte 2 (Bits[23:16]) base address.

Definition at line 389 of file stm32f4xx_hal_flash.h.

Referenced by FLASH_OB_DisablePCROP(), FLASH_OB_DisableWRP(), FLASH_OB_EnablePCROP(), FLASH_OB_EnableWRP(), FLASH_OB_GetWRP(), and HAL_FLASHEx_AdvOBGetConfig().

#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17U)

OPTCR register byte 3 (Bits[31:24]) base address.

Definition at line 393 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OB_DeSelectPCROP(), and HAL_FLASHEx_OB_SelectPCROP().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Private macros to check input parameters

Defines
FLASH Private macros to check input parameters
FLASH Private Macros

Defines

#define IS_FLASH_TYPEPROGRAM(VALUE)

Define Documentation

#define IS_FLASH_TYPEPROGRAM ( VALUE )
Value:
(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))

Definition at line 407 of file stm32f4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Private Functions

FLASH Private Functions
FLASH
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
FLASHEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
Program option bytes.
void | HAL_FLASHEx_AdvOBGetConfig (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
Get the OBEX byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_OB_SelectPCROP (void)
Select the Protection Mode.
HAL_StatusTypeDef | HAL_FLASHEx_OB_DeSelectPCROP (void)
Deselect the Protection Mode.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extension FLASH
    programming operations.

Function Documentation

void HAL_FLASHEx_AdvOBGetConfig ( FLASH_AdvOBProgramInitTypeDef * pAdvOBInit )

Get the OBEX byte configuration.

Parameters:
pAdvOBInit,: pointer to an FLASH_AdvOBProgramInitTypeDef structure that contains the configuration information for the programming.
Return values:
None

Definition at line 441 of file stm32f4xx_hal_flash_ex.c.

References OPTCR_BYTE0_ADDRESS, OPTCR_BYTE2_ADDRESS, and FLASH_AdvOBProgramInitTypeDef::Sectors.

HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram ( FLASH_AdvOBProgramInitTypeDef * pAdvOBInit )

Program option bytes.

Parameters:
pAdvOBInit,: pointer to an FLASH_AdvOBProgramInitTypeDef structure that contains the configuration information for the programming.
Return values:
HAL Status

Definition at line 389 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_OB_DisablePCROP(), FLASH_OB_EnablePCROP(), IS_OBEX, IS_PCROPSTATE, OB_PCROP_STATE_ENABLE, OPTIONBYTE_PCROP, FLASH_AdvOBProgramInitTypeDef::OptionType, FLASH_AdvOBProgramInitTypeDef::PCROPState, and FLASH_AdvOBProgramInitTypeDef::Sectors.

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | SectorError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory sectors.

Parameters:
[in] pEraseInit,: pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] SectorError,: pointer to variable that contains the configuration information on faulty sector in case of error (0xFFFFFFFFU means that all the sectors have been correctly erased)
Return values:
HAL Status

Definition at line 178 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_Erase_Sector(), FLASH_FlushCaches(), FLASH_MassErase(), FLASH_MER_BIT, FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbSectors, FLASH_EraseInitTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.

Parameters:
pEraseInit,: pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 249 of file stm32f4xx_hal_flash_ex.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_ENABLE_IT, assert_param, FLASH_ProcessTypeDef::Bank, FLASH_EraseInitTypeDef::Banks, FLASH_Erase_Sector(), FLASH_FLAG_EOP, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_PGSERR, FLASH_FLAG_WRPERR, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_MassErase(), FLASH_PROC_MASSERASE, FLASH_PROC_SECTERASE, FLASH_TYPEERASE_MASSERASE, IS_FLASH_NBSECTORS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbSectors, FLASH_ProcessTypeDef::NbSectorsToErase, FLASH_ProcessTypeDef::ProcedureOnGoing, FLASH_EraseInitTypeDef::Sector, FLASH_ProcessTypeDef::Sector, FLASH_EraseInitTypeDef::TypeErase, FLASH_ProcessTypeDef::VoltageForErase, and FLASH_EraseInitTypeDef::VoltageRange.

HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP ( void )

Deselect the Protection Mode.

Note:
After PCROP activated Option Byte modification NOT POSSIBLE! excepted Global Read Out Protection modification (from level1 to level0)
Once SPRMOD bit is active unprotection of a protected sector is not possible
Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ STM32F469xx/STM32F479xx devices.
Return values:
HAL Status

Definition at line 496 of file stm32f4xx_hal_flash_ex.c.

References OB_PCROP_DESELECTED, and OPTCR_BYTE3_ADDRESS.

HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP ( void )

Select the Protection Mode.

Note:
After PCROP activated Option Byte modification NOT POSSIBLE! excepted Global Read Out Protection modification (from level1 to level0)
Once SPRMOD bit is active unprotection of a protected sector is not possible
Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ STM32F469xx/STM32F479xx devices.
Return values:
HAL Status

Definition at line 471 of file stm32f4xx_hal_flash_ex.c.

References OB_PCROP_SELECTED, and OPTCR_BYTE3_ADDRESS.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option byte configuration.

Parameters:
pOBInit,: pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
None

Definition at line 361 of file stm32f4xx_hal_flash_ex.c.

References FLASH_OBProgramInitTypeDef::BORLevel, FLASH_OB_GetBOR(), FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), OPTIONBYTE_BOR, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, and FLASH_OBProgramInitTypeDef::WRPSector.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program option bytes.

Parameters:
pOBInit,: pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL Status

Definition at line 302 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::Banks, FLASH_OBProgramInitTypeDef::BORLevel, FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), IS_OPTIONBYTE, IS_WRPSTATE, OB_IWDG_SW, OB_STDBY_NO_RST, OB_STOP_NO_RST, OB_WRPSTATE_ENABLE, OPTIONBYTE_BOR, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPSector, and FLASH_OBProgramInitTypeDef::WRPState.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASHEx Exported Functions

Modules | Functions
FLASHEx Exported Functions
FLASHEx

Modules

Extended IO operation functions

Extended IO operation functions.

Functions

void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.
static void | FLASH_MassErase (uint8_t VoltageRange, uint32_t Banks)
Mass erase of FLASH memory.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WRPSector, uint32_t Banks)
Enable the write protection of the desired bank 1 sectors.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WRPSector, uint32_t Banks)
Disable the write protection of the desired bank 1 sectors.
static HAL_StatusTypeDef | FLASH_OB_EnablePCROP (uint32_t Sector)
Enable the read/write protection (PCROP) of the desired sectors.
static HAL_StatusTypeDef | FLASH_OB_DisablePCROP (uint32_t Sector)
Disable the read/write protection (PCROP) of the desired sectors.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t Level)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
static HAL_StatusTypeDef | FLASH_OB_BOR_LevelConfig (uint8_t Level)
Set the BOR Level.
static uint8_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static uint16_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint8_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint8_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.

Function Documentation

void FLASH_Erase_Sector | ( | uint32_t | Sector,
 |  | uint8_t | VoltageRange
 | ) |  |

Erase the specified FLASH memory sector.

Parameters:
Sector,: FLASH sector to erase The value of this parameter depend on device used within the same series
VoltageRange,: The device voltage range which defines the erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
  • FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
  • FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
  • FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
Return values:
None

Definition at line 988 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_PSIZE_BYTE, FLASH_PSIZE_DOUBLE_WORD, FLASH_PSIZE_HALF_WORD, FLASH_PSIZE_WORD, FLASH_VOLTAGE_RANGE_1, FLASH_VOLTAGE_RANGE_2, FLASH_VOLTAGE_RANGE_3, IS_FLASH_SECTOR, and IS_VOLTAGERANGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

void FLASH_FlushCaches ( void )

Flush the instruction and data caches.

Return values:
None

Definition at line 1314 of file stm32f4xx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_DATA_CACHE_ENABLE, __HAL_FLASH_DATA_CACHE_RESET, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, and __HAL_FLASH_INSTRUCTION_CACHE_RESET.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

static void FLASH_MassErase | ( | uint8_t | VoltageRange,
 |  | uint32_t | Banks
 | ) |  | [static]

Mass erase of FLASH memory.

Parameters:
VoltageRange,: The device voltage range which defines the erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
  • FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
  • FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
  • FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
Banks,: Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
Return values:
None

Definition at line 959 of file stm32f4xx_hal_flash_ex.c.

References assert_param, IS_FLASH_BANK, and IS_VOLTAGERANGE.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig ( uint8_t Level ) [static]

Set the BOR Level.

Parameters:
Level,: specifies the Option Bytes BOR Reset Level. This parameter can be one of the following values:
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
  • OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
Return values:
HAL Status

Definition at line 1234 of file stm32f4xx_hal_flash_ex.c.

References assert_param, IS_OB_BOR_LEVEL, and OPTCR_BYTE0_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_DisablePCROP ( uint32_t Sector ) [static]

Disable the read/write protection (PCROP) of the desired sectors.

Note:
This function can be used only for STM32F401xx devices.
Parameters:
Sector specifies the sector(s) to be read/write protected or unprotected. This parameter can be one of the following values:
  • OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
  • OB_PCROP_Sector_All
Return values:
HAL Status

Definition at line 1133 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_PCROP, and OPTCR_BYTE2_ADDRESS.

Referenced by HAL_FLASHEx_AdvOBProgram().

static HAL_StatusTypeDef FLASH_OB_DisableWRP | ( | uint32_t | WRPSector,
 |  | uint32_t | Banks
 | ) |  | [static]

Disable the write protection of the desired bank 1 sectors.

Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM4 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
Parameters:
WRPSector,: specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series
Banks,: Enable write protection on all the sectors for the specific bank This parameter can be one of the following values:
  • FLASH_BANK_1: WRP on all sectors of bank1
Return values:
HAL Status

Definition at line 1074 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK, IS_OB_WRP_SECTOR, and OPTCR_BYTE2_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_EnablePCROP ( uint32_t Sector ) [static]

Enable the read/write protection (PCROP) of the desired sectors.

Note:
This function can be used only for STM32F401xx devices.
Parameters:
Sector specifies the sector(s) to be read/write protected or unprotected. This parameter can be one of the following values:
  • OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
  • OB_PCROP_Sector_All
Return values:
HAL Status

Definition at line 1105 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_PCROP, and OPTCR_BYTE2_ADDRESS.

Referenced by HAL_FLASHEx_AdvOBProgram().

static HAL_StatusTypeDef FLASH_OB_EnableWRP | ( | uint32_t | WRPSector,
 |  | uint32_t | Banks
 | ) |  | [static]

Enable the write protection of the desired bank 1 sectors.

Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM4 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
Parameters:
WRPSector,: specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series
Banks,: Enable write protection on all the sectors for the specific bank This parameter can be one of the following values:
  • FLASH_BANK_1: WRP on all sectors of bank1
Return values:
HAL Status

Definition at line 1038 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK, IS_OB_WRP_SECTOR, and OPTCR_BYTE2_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static uint8_t FLASH_OB_GetBOR ( void ) [static]

Returns the FLASH BOR level.

Return values:
uint8_t The FLASH BOR level:
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
  • OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V

Definition at line 1304 of file stm32f4xx_hal_flash_ex.c.

References OPTCR_BYTE0_ADDRESS.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint8_t FLASH_OB_GetRDP ( void ) [static]

Returns the FLASH Read Protection level.

Return values:
FLASH ReadOut Protection Status: This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection

Definition at line 1276 of file stm32f4xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, OB_RDP_LEVEL_2, and OPTCR_BYTE1_ADDRESS.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint8_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) and RST_STDBY(Bit2).

Definition at line 1252 of file stm32f4xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint16_t FLASH_OB_GetWRP ( void ) [static]

Return the FLASH Write Protection Option Bytes value.

Return values:
uint16_t FLASH Write Protection Option Bytes value

Definition at line 1262 of file stm32f4xx_hal_flash_ex.c.

References OPTCR_BYTE2_ADDRESS.

Referenced by HAL_FLASHEx_OBGetConfig().

static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig ( uint8_t Level ) [static]

Set the read protection level.

Parameters:
Level,: specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection
Note:
WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
Return values:
HAL Status

Definition at line 1165 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_RDP_LEVEL, and OPTCR_BYTE1_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_UserConfig | ( | uint8_t | Iwdg,
 |  | uint8_t | Stop,
 |  | uint8_t | Stdby
 | ) |  | [static]

Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

Parameters:
Iwdg,: Selects the IWDG mode This parameter can be one of the following values:
  • OB_IWDG_SW: Software IWDG selected
  • OB_IWDG_HW: Hardware IWDG selected
Stop,: Reset event when entering STOP mode. This parameter can be one of the following values:
  • OB_STOP_NO_RST: No reset generated when entering in STOP
  • OB_STOP_RST: Reset generated when entering in STOP
Stdby,: Reset event when entering Standby mode. This parameter can be one of the following values:
  • OB_STDBY_NO_RST: No reset generated when entering in STANDBY
  • OB_STDBY_RST: Reset generated when entering in STANDBY
Return values:
HAL Status

Definition at line 1199 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_IWDG_SOURCE, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, and OPTCR_BYTE0_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

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STM32F410Rx HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32f4xx_hal_flash_ex.h>

Data Fields

uint32_t | TypeErase
uint32_t | Banks
uint32_t | Sector
uint32_t | NbSectors
uint32_t | VoltageRange

Detailed Description

FLASH Erase structure definition.

Definition at line 65 of file stm32f4xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::Banks

Select banks to erase when Mass erase is enabled. This parameter must be a value of FLASH Banks

Definition at line 70 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::NbSectors

Number of sectors to be erased. This parameter must be a value between 1 and (max number of sectors - value of Initial sector)

Definition at line 76 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Sector

Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of FLASH Sectors

Definition at line 73 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or sector Erase. This parameter can be a value of FLASH Type Erase

Definition at line 67 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::VoltageRange

The device voltage range which defines the erase parallelism This parameter must be a value of FLASH Voltage Range

Definition at line 79 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_flash_ex.h
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STM32F410Rx HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32f4xx_hal_flash_ex.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPState
uint32_t | WRPSector
uint32_t | Banks
uint32_t | RDPLevel
uint32_t | BORLevel
uint8_t | USERConfig

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 87 of file stm32f4xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::Banks

Select banks for WRP activation/deactivation of all sectors. This parameter must be a value of FLASH Banks

Definition at line 98 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::BORLevel

Set the BOR Level. This parameter can be a value of FLASH BOR Reset Level

Definition at line 104 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a value of FLASH Option Type

Definition at line 89 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level. This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 101 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint8_t FLASH_OBProgramInitTypeDef::USERConfig

Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

Definition at line 107 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPSector

Specifies the sector(s) to be write protected. The value of this parameter depend on device used within the same series

Definition at line 95 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPState

Write protection activation or deactivation. This parameter can be a value of FLASH WRP State

Definition at line 92 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_flash_ex.h
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STM32F410Rx HAL User Manual: FLASH_AdvOBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_AdvOBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Advanced Option Bytes Program structure definition. More...

#include <stm32f4xx_hal_flash_ex.h>

Data Fields

uint32_t | OptionType
uint32_t | PCROPState
uint16_t | Sectors

Detailed Description

FLASH Advanced Option Bytes Program structure definition.

Definition at line 118 of file stm32f4xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_AdvOBProgramInitTypeDef::OptionType

Option byte to be configured for extension. This parameter can be a value of FLASH Advanced Option Type

Definition at line 120 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_AdvOBProgram().

uint32_t FLASH_AdvOBProgramInitTypeDef::PCROPState

PCROP activation or deactivation. This parameter can be a value of FLASH PCROP State

Definition at line 123 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_AdvOBProgram().

uint16_t FLASH_AdvOBProgramInitTypeDef::Sectors

specifies the sector(s) set for PCROP. This parameter can be a value of FLASH Option Bytes PC ReadWrite Protection

Definition at line 127 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_AdvOBGetConfig(), and HAL_FLASHEx_AdvOBProgram().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_flash_ex.h
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STM32F410Rx HAL User Manual: FLASH Type Erase

Defines
FLASH Type Erase
FLASH Exported Constants

Defines

#define | FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U)

Define Documentation

#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U)

Flash Mass erase activation

Definition at line 161 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U)

Sectors erase only

Definition at line 160 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH Voltage Range

Defines
FLASH Voltage Range
FLASH Exported Constants

Defines

#define | FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U)
#define | FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U)
#define | FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U)
#define | FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U)

Define Documentation

#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U)

Device operating range: 1.8V to 2.1V

Definition at line 169 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U)

Device operating range: 2.1V to 2.7V

Definition at line 170 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U)

Device operating range: 2.7V to 3.6V

Definition at line 171 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U)

Device operating range: 2.7V to 3.6V + External Vpp

Definition at line 172 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH WRP State

Defines
FLASH WRP State
FLASH Exported Constants

Defines

#define | OB_WRPSTATE_DISABLE ((uint32_t)0x00U)
#define | OB_WRPSTATE_ENABLE ((uint32_t)0x01U)

Define Documentation

#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U)

Disable the write protection of the desired bank 1 sectors

Definition at line 180 of file stm32f4xx_hal_flash_ex.h.

#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U)

Enable the write protection of the desired bank 1 sectors

Definition at line 181 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32F410Rx HAL User Manual: FLASH Option Type

Defines
FLASH Option Type
FLASH Exported Constants

Defines

#define | OPTIONBYTE_WRP ((uint32_t)0x01U)
#define | OPTIONBYTE_RDP ((uint32_t)0x02U)
#define | OPTIONBYTE_USER ((uint32_t)0x04U)
#define | OPTIONBYTE_BOR ((uint32_t)0x08U)

Define Documentation

#define OPTIONBYTE_BOR ((uint32_t)0x08U)

BOR option byte configuration

Definition at line 192 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP ((uint32_t)0x02U)

RDP option byte configuration

Definition at line 190 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER ((uint32_t)0x04U)

USER option byte configuration

Definition at line 191 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP ((uint32_t)0x01U)

WRP option byte configuration

Definition at line 189 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

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STM32F410Rx HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Exported Constants

Defines

#define | OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define | OB_RDP_LEVEL_1 ((uint8_t)0x55U)
#define | OB_RDP_LEVEL_2 ((uint8_t)0xCCU)

Define Documentation

#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)

Definition at line 200 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)

Definition at line 201 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU)

Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0

Definition at line 202 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

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STM32F410Rx HAL User Manual: FLASH Option Bytes IWatchdog

Defines
FLASH Option Bytes IWatchdog
FLASH Exported Constants

Defines

#define | OB_IWDG_SW ((uint8_t)0x20U)
#define | OB_IWDG_HW ((uint8_t)0x00U)

Define Documentation

#define OB_IWDG_HW ((uint8_t)0x00U)

Hardware IWDG selected

Definition at line 212 of file stm32f4xx_hal_flash_ex.h.

#define OB_IWDG_SW ((uint8_t)0x20U)

Software IWDG selected

Definition at line 211 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32F410Rx HAL User Manual: FLASH Option Bytes nRST_STOP

Defines
FLASH Option Bytes nRST_STOP
FLASH Exported Constants

Defines

#define | OB_STOP_NO_RST ((uint8_t)0x40U)
#define | OB_STOP_RST ((uint8_t)0x00U)

Define Documentation

#define OB_STOP_NO_RST ((uint8_t)0x40U)

No reset generated when entering in STOP

Definition at line 220 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OB_STOP_RST ((uint8_t)0x00U)

Reset generated when entering in STOP

Definition at line 221 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH Option Bytes nRST_STDBY

Defines
FLASH Option Bytes nRST_STDBY
FLASH Exported Constants

Defines

#define | OB_STDBY_NO_RST ((uint8_t)0x80U)
#define | OB_STDBY_RST ((uint8_t)0x00U)

Define Documentation

#define OB_STDBY_NO_RST ((uint8_t)0x80U)

No reset generated when entering in STANDBY

Definition at line 230 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OB_STDBY_RST ((uint8_t)0x00U)

Reset generated when entering in STANDBY

Definition at line 231 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH BOR Reset Level

Defines
FLASH BOR Reset Level
FLASH Exported Constants

Defines

#define | OB_BOR_LEVEL3 ((uint8_t)0x00U)
#define | OB_BOR_LEVEL2 ((uint8_t)0x04U)
#define | OB_BOR_LEVEL1 ((uint8_t)0x08U)
#define | OB_BOR_OFF ((uint8_t)0x0CU)

Define Documentation

#define OB_BOR_LEVEL1 ((uint8_t)0x08U)

Supply voltage ranges from 2.10 to 2.40 V

Definition at line 241 of file stm32f4xx_hal_flash_ex.h.

#define OB_BOR_LEVEL2 ((uint8_t)0x04U)

Supply voltage ranges from 2.40 to 2.70 V

Definition at line 240 of file stm32f4xx_hal_flash_ex.h.

#define OB_BOR_LEVEL3 ((uint8_t)0x00U)

Supply voltage ranges from 2.70 to 3.60 V

Definition at line 239 of file stm32f4xx_hal_flash_ex.h.

#define OB_BOR_OFF ((uint8_t)0x0CU)

Supply voltage ranges from 1.62 to 2.10 V

Definition at line 242 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH PCROP State

Defines
FLASH PCROP State
FLASH Exported Constants

Defines

#define | OB_PCROP_STATE_DISABLE ((uint32_t)0x00U)
#define | OB_PCROP_STATE_ENABLE ((uint32_t)0x01U)

Define Documentation

#define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U)

Disable PCROP

Definition at line 254 of file stm32f4xx_hal_flash_ex.h.

#define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U)

Enable PCROP

Definition at line 255 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_AdvOBProgram().

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STM32F410Rx HAL User Manual: FLASH Advanced Option Type

Defines
FLASH Advanced Option Type
FLASH Exported Constants

Defines

#define OPTIONBYTE_PCROP ((uint32_t)0x01U)

Define Documentation

#define OPTIONBYTE_PCROP ((uint32_t)0x01U)

PCROP option byte configuration

Definition at line 273 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_AdvOBProgram().

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STM32F410Rx HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

Define Documentation

#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero Latency cycle

Definition at line 309 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One Latency cycle

Definition at line 310 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two Latency cycles

Definition at line 311 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three Latency cycles

Definition at line 312 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four Latency cycles

Definition at line 313 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

FLASH Five Latency cycles

Definition at line 314 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

FLASH Six Latency cycles

Definition at line 315 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

FLASH Seven Latency cycles

Definition at line 316 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH Banks

Defines
FLASH Banks
FLASH Exported Constants

Defines

#define FLASH_BANK_1 ((uint32_t)1U)

Define Documentation

#define FLASH_BANK_1 ((uint32_t)1U)

Bank 1

Definition at line 338 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH Mass Erase bit

Defines
FLASH Mass Erase bit
FLASH Exported Constants

Defines

#define FLASH_MER_BIT (FLASH_CR_MER)

Define Documentation

#define FLASH_MER_BIT (FLASH_CR_MER)

only 1 MER Bit

Definition at line 355 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

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STM32F410Rx HAL User Manual: FLASH Sectors

Defines
FLASH Sectors
FLASH Exported Constants

Defines

#define | FLASH_SECTOR_0 ((uint32_t)0U)
#define | FLASH_SECTOR_1 ((uint32_t)1U)
#define | FLASH_SECTOR_2 ((uint32_t)2U)
#define | FLASH_SECTOR_3 ((uint32_t)3U)
#define | FLASH_SECTOR_4 ((uint32_t)4U)

Define Documentation

#define FLASH_SECTOR_0 ((uint32_t)0U)

Sector Number 0

Definition at line 424 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_SECTOR_1 ((uint32_t)1U)

Sector Number 1

Definition at line 425 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_SECTOR_2 ((uint32_t)2U)

Sector Number 2

Definition at line 426 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_SECTOR_3 ((uint32_t)3U)

Sector Number 3

Definition at line 427 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_SECTOR_4 ((uint32_t)4U)

Sector Number 4

Definition at line 428 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH Option Bytes Write Protection

Defines
FLASH Option Bytes Write Protection
FLASH Exported Constants

Defines

#define | OB_WRP_SECTOR_0 ((uint32_t)0x00000001U)
#define | OB_WRP_SECTOR_1 ((uint32_t)0x00000002U)
#define | OB_WRP_SECTOR_2 ((uint32_t)0x00000004U)
#define | OB_WRP_SECTOR_3 ((uint32_t)0x00000008U)
#define | OB_WRP_SECTOR_4 ((uint32_t)0x00000010U)
#define | OB_WRP_SECTOR_All ((uint32_t)0x00000FFFU)

Define Documentation

#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001U)

Write protection of Sector0

Definition at line 515 of file stm32f4xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002U)

Write protection of Sector1

Definition at line 516 of file stm32f4xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004U)

Write protection of Sector2

Definition at line 517 of file stm32f4xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008U)

Write protection of Sector3

Definition at line 518 of file stm32f4xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010U)

Write protection of Sector4

Definition at line 519 of file stm32f4xx_hal_flash_ex.h.

#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFFU)

Write protection of all Sectors

Definition at line 520 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH Option Bytes PC ReadWrite Protection

Defines
FLASH Option Bytes PC ReadWrite Protection
FLASH Exported Constants

Defines

#define | OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U)
#define | OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U)
#define | OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U)
#define | OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U)
#define | OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U)
#define | OB_PCROP_SECTOR_All ((uint32_t)0x00000FFFU)

Define Documentation

#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U)

PC Read/Write protection of Sector0

Definition at line 589 of file stm32f4xx_hal_flash_ex.h.

#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U)

PC Read/Write protection of Sector1

Definition at line 590 of file stm32f4xx_hal_flash_ex.h.

#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U)

PC Read/Write protection of Sector2

Definition at line 591 of file stm32f4xx_hal_flash_ex.h.

#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U)

PC Read/Write protection of Sector3

Definition at line 592 of file stm32f4xx_hal_flash_ex.h.

#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U)

PC Read/Write protection of Sector4

Definition at line 593 of file stm32f4xx_hal_flash_ex.h.

#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFFU)

PC Read/Write protection of all Sectors

Definition at line 594 of file stm32f4xx_hal_flash_ex.h.

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STM32F410Rx HAL User Manual: FLASH Dual Boot

FLASH Dual Boot
FLASH Exported Constants
Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Selection Protection Mode

Defines
FLASH Selection Protection Mode
FLASH Exported Constants

Defines

#define | OB_PCROP_DESELECTED ((uint8_t)0x00U)
#define | OB_PCROP_SELECTED ((uint8_t)0x80U)

Define Documentation

#define OB_PCROP_DESELECTED ((uint8_t)0x00U)

Disabled PcROP, nWPRi bits used for Write Protection on sector i

Definition at line 635 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OB_DeSelectPCROP().

#define OB_PCROP_SELECTED ((uint8_t)0x80U)

Enable PcROP, nWPRi bits used for PCRoP Protection on sector i

Definition at line 636 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OB_SelectPCROP().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASHEx

Defines

#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
#define | FLASH_SECTOR_TOTAL 5U

Define Documentation

#define FLASH_SECTOR_TOTAL 5U

Definition at line 708 of file stm32f4xx_hal_flash_ex.h.

#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */

Definition at line 100 of file stm32f4xx_hal_flash_ex.c.

Referenced by FLASH_OB_DisablePCROP(), FLASH_OB_DisableWRP(), FLASH_OB_EnablePCROP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), and HAL_FLASHEx_Erase().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Private macros to check input parameters

Defines
FLASH Private macros to check input parameters
FLASH Private Macros

Defines

#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_VOLTAGERANGE(RANGE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_PCROPSTATE(VALUE)
#define | IS_OBEX(VALUE) (((VALUE) == OPTIONBYTE_PCROP))
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#define | IS_FLASH_SECTOR(SECTOR)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define | IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define | IS_OB_PCROP(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define | IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))

Define Documentation

#define IS_FLASH_ADDRESS ( ADDRESS ) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))

Definition at line 870 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), and FLASH_Program_Word().

#define IS_FLASH_BANK ( BANK ) (((BANK) == FLASH_BANK_1))

Definition at line 824 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_LATENCY_0)  || \
                                   ((LATENCY) == FLASH_LATENCY_1)  || \
                                   ((LATENCY) == FLASH_LATENCY_2)  || \
                                   ((LATENCY) == FLASH_LATENCY_3)  || \
                                   ((LATENCY) == FLASH_LATENCY_4)  || \
                                   ((LATENCY) == FLASH_LATENCY_5)  || \
                                   ((LATENCY) == FLASH_LATENCY_6)  || \
                                   ((LATENCY) == FLASH_LATENCY_7))

Definition at line 805 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_NBSECTORS ( NBSECTORS ) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))

Definition at line 871 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_SECTOR ( SECTOR )
Value:
(((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
                                 ((SECTOR) == FLASH_SECTOR_4))

Definition at line 858 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector().

#define IS_FLASH_TYPEERASE ( VALUE )
Value:
(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 736 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_OB_BOR_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))

Definition at line 759 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_BOR_LevelConfig().

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 753 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_PCROP ( SECTOR ) ((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))

Definition at line 902 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisablePCROP(), and FLASH_OB_EnablePCROP().

#define IS_OB_PCROP_SELECT ( PCROP ) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))

Definition at line 918 of file stm32f4xx_hal_flash_ex.h.

#define IS_OB_RDP_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_RDP_LEVEL_0) ||\
                                ((LEVEL) == OB_RDP_LEVEL_1) ||\
                                ((LEVEL) == OB_RDP_LEVEL_2))

Definition at line 749 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_RDP_LevelConfig().

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 757 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

Definition at line 755 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRP_SECTOR ( SECTOR ) ((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))

Definition at line 886 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define IS_OBEX ( VALUE ) (((VALUE) == OPTIONBYTE_PCROP))

Definition at line 779 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_AdvOBProgram().

#define IS_OPTIONBYTE ( VALUE ) (((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))

Definition at line 747 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define IS_PCROPSTATE ( VALUE )
Value:
(((VALUE) == OB_PCROP_STATE_DISABLE) || \
                             ((VALUE) == OB_PCROP_STATE_ENABLE))

Definition at line 766 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_AdvOBProgram().

#define IS_VOLTAGERANGE ( RANGE )
Value:
(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))

Definition at line 739 of file stm32f4xx_hal_flash_ex.h.

Referenced by FLASH_Erase_Sector(), and FLASH_MassErase().

#define IS_WRPSTATE ( VALUE )
Value:
(((VALUE) == OB_WRPSTATE_DISABLE) || \
                           ((VALUE) == OB_WRPSTATE_ENABLE))

Definition at line 744 of file stm32f4xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASHEx

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.

Function Documentation

void FLASH_Erase_Sector | ( | uint32_t | Sector,
 |  | uint8_t | VoltageRange
 | ) |  |

Erase the specified FLASH memory sector.

Parameters:
Sector,: FLASH sector to erase The value of this parameter depend on device used within the same series
VoltageRange,: The device voltage range which defines the erase parallelism. This parameter can be one of the following values:
  • FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
  • FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
  • FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
  • FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
Return values:
None

Definition at line 988 of file stm32f4xx_hal_flash_ex.c.

References assert_param, FLASH_PSIZE_BYTE, FLASH_PSIZE_DOUBLE_WORD, FLASH_PSIZE_HALF_WORD, FLASH_PSIZE_WORD, FLASH_VOLTAGE_RANGE_1, FLASH_VOLTAGE_RANGE_2, FLASH_VOLTAGE_RANGE_3, IS_FLASH_SECTOR, and IS_VOLTAGERANGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

void FLASH_FlushCaches ( void )

Flush the instruction and data caches.

Return values:
None

Definition at line 1314 of file stm32f4xx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_DATA_CACHE_ENABLE, __HAL_FLASH_DATA_CACHE_RESET, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, and __HAL_FLASH_INSTRUCTION_CACHE_RESET.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operationtimeout
Return values:
HAL Status

Definition at line 561 of file stm32f4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_BSY, FLASH_FLAG_EOP, FLASH_FLAG_OPERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGPERR, FLASH_FLAG_PGSERR, FLASH_FLAG_RDERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), HAL_FLASH_ERROR_NONE, and HAL_GetTick().

Referenced by FLASH_OB_DisablePCROP(), FLASH_OB_DisableWRP(), FLASH_OB_EnablePCROP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASHEx_Private_Variables

Variables
FLASHEx_Private_Variables
FLASHEx

Variables

FLASH_ProcessTypeDef pFlash

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 124 of file stm32f4xx_hal_flash.c.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral features functions executed from internal RAM

Functions
Peripheral features functions executed from internal RAM
FLASH RAMFUNC Exported Functions

Peripheral Extended features functions. More...

Functions

__RAM_FUNC | HAL_FLASHEx_StopFlashInterfaceClk (void)
Stop the flash interface while System Run.
__RAM_FUNC | HAL_FLASHEx_StartFlashInterfaceClk (void)
Start the flash interface while System Run.
__RAM_FUNC | HAL_FLASHEx_EnableFlashSleepMode (void)
Enable the flash sleep while System Run.
__RAM_FUNC | HAL_FLASHEx_DisableFlashSleepMode (void)
Disable the flash sleep while System Run.

Detailed Description

Peripheral Extended features functions.

 ===============================================================================
                      ##### ramfunc functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions that should be executed from RAM
    transfers.

Function Documentation

__RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode ( void )

Disable the flash sleep while System Run.

Note:
This mode is only available for STM32F41xxx/STM32F446xx devices.
This mode couldn't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
Return values:
None

Definition at line 163 of file stm32f4xx_hal_flash_ramfunc.c.

References __HAL_RCC_PWR_CLK_ENABLE.

__RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode ( void )

Enable the flash sleep while System Run.

Note:
This mode is only available for STM32F41xxx/STM32F446xx devices.
This mode could n't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
Return values:
None

Definition at line 146 of file stm32f4xx_hal_flash_ramfunc.c.

References __HAL_RCC_PWR_CLK_ENABLE.

__RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk ( void )

Start the flash interface while System Run.

Note:
This mode is only available for STM32F411xx/STM32F446xx devices.
This mode couldn't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
Return values:
None

Definition at line 129 of file stm32f4xx_hal_flash_ramfunc.c.

References __HAL_RCC_PWR_CLK_ENABLE.

__RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk ( void )

Stop the flash interface while System Run.

Note:
This mode is only available for STM32F41xxx/STM32F446xx devices.
This mode couldn't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
Return values:
None

Definition at line 112 of file stm32f4xx_hal_flash_ramfunc.c.

References __HAL_RCC_PWR_CLK_ENABLE.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Private Define

Defines
FMPI2C Private Define
FMPI2C

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU)
#define | FMPI2C_TIMEOUT_ADDR ((uint32_t)10000U)
#define | FMPI2C_TIMEOUT_BUSY ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_DIR ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_RXNE ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_STOPF ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_TC ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_TCR ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_TXIS ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_FLAG ((uint32_t)25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | FMPI2C_STATE_MSK ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~HAL_FMPI2C_STATE_READY)))
#define | FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE))
#define | FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))
#define | FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))
#define | FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))
#define | FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))
#define | FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))
#define | FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))

Define Documentation

#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 259 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Master_ISR(), HAL_FMPI2C_Master_Abort_IT(), and HAL_FMPI2C_Master_Sequential_Receive_IT().

#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 258 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Master_ISR(), and HAL_FMPI2C_Master_Abort_IT().

#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 263 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Master_ISR().

#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 262 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Master_ISR().

#define FMPI2C_STATE_MSK ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~HAL_FMPI2C_STATE_READY)))

Mask State define, keep only RX and TX bits

Definition at line 256 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_DisableListen_IT().

#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE))

Default Value

Definition at line 257 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_DeInit(), HAL_FMPI2C_ER_IRQHandler(), and HAL_FMPI2C_Init().

#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 261 of file stm32f4xx_hal_fmpi2c.c.

#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 260 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Slave_ISR(), and HAL_FMPI2C_Master_Sequential_Transmit_IT().

#define FMPI2C_TIMEOUT_ADDR ((uint32_t)10000U)

10 s

Definition at line 241 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_Slave_Receive_DMA(), and HAL_FMPI2C_Slave_Transmit_DMA().

#define FMPI2C_TIMEOUT_BUSY ((uint32_t)25U)

25 ms

Definition at line 242 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), and HAL_FMPI2C_Slave_Transmit_DMA().

#define FMPI2C_TIMEOUT_DIR ((uint32_t)25U)

25 ms

Definition at line 243 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_Slave_Receive_DMA().

#define FMPI2C_TIMEOUT_FLAG ((uint32_t)25U)

25 ms

Definition at line 249 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

#define FMPI2C_TIMEOUT_RXNE ((uint32_t)25U)

25 ms

Definition at line 244 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMemReceiveCplt(), HAL_FMPI2C_Master_Receive_DMA(), and HAL_FMPI2C_Mem_Read_DMA().

#define FMPI2C_TIMEOUT_STOPF ((uint32_t)25U)

25 ms

Definition at line 245 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Slave_Receive(), and HAL_FMPI2C_Slave_Transmit().

#define FMPI2C_TIMEOUT_TC ((uint32_t)25U)

25 ms

Definition at line 246 of file stm32f4xx_hal_fmpi2c.c.

#define FMPI2C_TIMEOUT_TCR ((uint32_t)25U)

25 ms

Definition at line 247 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), and FMPI2C_DMAMemTransmitCplt().

#define FMPI2C_TIMEOUT_TXIS ((uint32_t)25U)

25 ms

Definition at line 248 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemTransmitCplt(), HAL_FMPI2C_Master_Transmit_DMA(), and HAL_FMPI2C_Mem_Write_DMA().

#define MAX_NBYTE_SIZE 255U

Definition at line 251 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_Master_ISR(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

#define SlaveAddr_MSK 0x06U

Definition at line 253 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Slave_ISR().

#define SlaveAddr_SHIFT 7U

Definition at line 252 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Slave_ISR().

#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU)

FMPI2C TIMING clear register Mask

Definition at line 240 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_Init().

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Private Functions

Functions
FMPI2C Private Functions
FMPI2C

Functions

static void | FMPI2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C master transmit process complete callback.
static void | FMPI2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C master receive process complete callback.
static void | FMPI2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C slave transmit process complete callback.
static void | FMPI2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C slave receive process complete callback.
static void | FMPI2C_DMAMemTransmitCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C Memory Write process complete callback.
static void | FMPI2C_DMAMemReceiveCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C Memory Read process complete callback.
static void | FMPI2C_DMAError (DMA_HandleTypeDef *hdma)
DMA FMPI2C communication error callback.
static HAL_StatusTypeDef | FMPI2C_RequestMemoryWrite (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | FMPI2C_RequestMemoryRead (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | FMPI2C_WaitOnFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles FMPI2C Communication Timeout.
static HAL_StatusTypeDef | FMPI2C_WaitOnTXISFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles FMPI2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | FMPI2C_WaitOnRXNEFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | FMPI2C_WaitOnSTOPFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | FMPI2C_IsAcknowledgeFailed (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles Acknowledge failed detection during an FMPI2C Communication.
static HAL_StatusTypeDef | FMPI2C_Master_ISR (FMPI2C_HandleTypeDef *hfmpi2c)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | FMPI2C_Slave_ISR (FMPI2C_HandleTypeDef *hfmpi2c)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static HAL_StatusTypeDef | FMPI2C_Enable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | FMPI2C_Disable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | FMPI2C_TransferConfig (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Function Documentation

static HAL_StatusTypeDef FMPI2C_Disable_IRQ | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
InterruptRequest | Value of FMPI2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4911 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_DISABLE_IT, FMPI2C_IT_ADDR, FMPI2C_IT_ADDRI, FMPI2C_IT_NACKI, FMPI2C_IT_RX, FMPI2C_IT_RXI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_IT_TX, FMPI2C_IT_TXI, HAL_FMPI2C_STATE_LISTEN, and FMPI2C_HandleTypeDef::State.

Referenced by FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_DisableListen_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), and HAL_FMPI2C_Slave_Sequential_Transmit_IT().

static void FMPI2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA FMPI2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4575 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_HandleTypeDef::ErrorCode, HAL_FMPI2C_ERROR_DMA, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::State, and FMPI2C_HandleTypeDef::XferCount.

Referenced by HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Slave_Receive_DMA(), and HAL_FMPI2C_Slave_Transmit_DMA().

static void FMPI2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA FMPI2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4031 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RESET_CR2, FMPI2C_TIMEOUT_RXNE, FMPI2C_TIMEOUT_STOPF, FMPI2C_TIMEOUT_TCR, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MasterRxCpltCallback(), HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmarx, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, and FMPI2C_HandleTypeDef::XferSize.

Referenced by HAL_FMPI2C_Master_Receive_DMA().

static void FMPI2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA FMPI2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 3821 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RESET_CR2, FMPI2C_TIMEOUT_STOPF, FMPI2C_TIMEOUT_TCR, FMPI2C_TIMEOUT_TXIS, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MasterTxCpltCallback(), HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmatx, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, and FMPI2C_HandleTypeDef::XferSize.

Referenced by HAL_FMPI2C_Master_Transmit_DMA().

static void FMPI2C_DMAMemReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA FMPI2C Memory Read process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4410 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RESET_CR2, FMPI2C_TIMEOUT_RXNE, FMPI2C_TIMEOUT_STOPF, FMPI2C_TIMEOUT_TCR, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MemRxCpltCallback(), HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmarx, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, and FMPI2C_HandleTypeDef::XferSize.

Referenced by HAL_FMPI2C_Mem_Read_DMA().

static void FMPI2C_DMAMemTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA FMPI2C Memory Write process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4251 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RESET_CR2, FMPI2C_TIMEOUT_STOPF, FMPI2C_TIMEOUT_TCR, FMPI2C_TIMEOUT_TXIS, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MemTxCpltCallback(), HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmatx, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, and FMPI2C_HandleTypeDef::XferSize.

Referenced by HAL_FMPI2C_Mem_Write_DMA().

static void FMPI2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA FMPI2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4197 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_STOPF, FMPI2C_TIMEOUT_BUSY, FMPI2C_TIMEOUT_STOPF, FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_SlaveRxCpltCallback(), HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::State, and FMPI2C_HandleTypeDef::XferCount.

Referenced by HAL_FMPI2C_Slave_Receive_DMA().

static void FMPI2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA FMPI2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 3979 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_STOPF, FMPI2C_TIMEOUT_BUSY, FMPI2C_TIMEOUT_STOPF, FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_SlaveTxCpltCallback(), HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::State, and FMPI2C_HandleTypeDef::XferCount.

Referenced by HAL_FMPI2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef FMPI2C_Enable_IRQ | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
InterruptRequest | Value of FMPI2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4874 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_ENABLE_IT, FMPI2C_IT_ADDR, FMPI2C_IT_ADDRI, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_RX, FMPI2C_IT_RXI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_IT_TX, and FMPI2C_IT_TXI.

Referenced by HAL_FMPI2C_EnableListen_IT(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), and HAL_FMPI2C_Slave_Sequential_Transmit_IT().

static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles Acknowledge failed detection during an FMPI2C Communication.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4769 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_AF, FMPI2C_FLAG_STOPF, FMPI2C_RESET_CR2, HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_STATE_READY, HAL_GetTick(), FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, and FMPI2C_HandleTypeDef::State.

Referenced by FMPI2C_WaitOnSTOPFlagUntilTimeout(), and FMPI2C_WaitOnTXISFlagUntilTimeout().

static HAL_StatusTypeDef FMPI2C_Master_ISR ( FMPI2C_HandleTypeDef * hfmpi2c ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
HAL status

Definition at line 3147 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_DISABLE, __HAL_FMPI2C_ENABLE, __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_Disable_IRQ(), FMPI2C_FLAG_AF, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TC, FMPI2C_FLAG_TCR, FMPI2C_FLAG_TXE, FMPI2C_FLAG_TXIS, FMPI2C_GET_STOP_MODE, FMPI2C_IT_RX, FMPI2C_IT_TX, FMPI2C_NO_OPTION_FRAME, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RESET_CR2, FMPI2C_STATE_MASTER_BUSY_RX, FMPI2C_STATE_MASTER_BUSY_TX, FMPI2C_STATE_MEM_BUSY_RX, FMPI2C_STATE_MEM_BUSY_TX, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MasterRxCpltCallback(), HAL_FMPI2C_MasterTxCpltCallback(), HAL_FMPI2C_MemRxCpltCallback(), HAL_FMPI2C_MemTxCpltCallback(), HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::PreviousState, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

Referenced by HAL_FMPI2C_EV_IRQHandler().

static HAL_StatusTypeDef FMPI2C_RequestMemoryRead | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3761 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_TC, FMPI2C_GENERATE_START_WRITE, FMPI2C_MEM_ADD_LSB, FMPI2C_MEM_ADD_MSB, FMPI2C_MEMADD_SIZE_8BIT, FMPI2C_SOFTEND_MODE, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, and FMPI2C_HandleTypeDef::Instance.

Referenced by HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), and HAL_FMPI2C_Mem_Read_IT().

static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3696 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_TCR, FMPI2C_GENERATE_START_WRITE, FMPI2C_MEM_ADD_LSB, FMPI2C_MEM_ADD_MSB, FMPI2C_MEMADD_SIZE_8BIT, FMPI2C_RELOAD_MODE, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, and FMPI2C_HandleTypeDef::Instance.

Referenced by HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

static HAL_StatusTypeDef FMPI2C_Slave_ISR ( FMPI2C_HandleTypeDef * hfmpi2c ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
HAL status

Definition at line 3400 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_DISABLE_IT, __HAL_FMPI2C_GET_FLAG, FMPI2C_InitTypeDef::AddressingMode, FMPI2C_HandleTypeDef::AddrEventCount, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_ADDRESSINGMODE_10BIT, FMPI2C_ADDRESSINGMODE_7BIT, FMPI2C_Disable_IRQ(), FMPI2C_FIRST_AND_LAST_FRAME, FMPI2C_FLAG_ADDR, FMPI2C_FLAG_AF, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TXE, FMPI2C_FLAG_TXIS, FMPI2C_GET_ADDR_MATCH, FMPI2C_GET_DIR, FMPI2C_GET_OWN_ADDRESS1, FMPI2C_GET_OWN_ADDRESS2, FMPI2C_IT_ADDR, FMPI2C_IT_ADDRI, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_RX, FMPI2C_IT_RXI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_IT_TX, FMPI2C_IT_TXI, FMPI2C_LAST_FRAME, FMPI2C_NEXT_FRAME, FMPI2C_NO_OPTION_FRAME, FMPI2C_RESET_CR2, FMPI2C_STATE_SLAVE_BUSY_TX, HAL_FMPI2C_AddrCallback(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_ListenCpltCallback(), HAL_FMPI2C_SlaveRxCpltCallback(), HAL_FMPI2C_SlaveTxCpltCallback(), HAL_FMPI2C_STATE_BUSY_RX_LISTEN, HAL_FMPI2C_STATE_BUSY_TX_LISTEN, HAL_FMPI2C_STATE_LISTEN, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Init, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::PreviousState, SlaveAddr_MSK, SlaveAddr_SHIFT, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

Referenced by HAL_FMPI2C_EV_IRQHandler().

static void FMPI2C_TransferConfig | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hfmpi2c | FMPI2C handle.
DevAddress | Specifies the slave address to be programmed.
Size | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the FMPI2C START condition generation. This parameter can be one of the following values:
  • FMPI2C_RELOAD_MODE Enable Reload mode .
  • FMPI2C_AUTOEND_MODE Enable Automatic end mode.
  • FMPI2C_SOFTEND_MODE Enable Software end mode.
Request New state of the FMPI2C START condition generation. This parameter can be one of the following values:
  • FMPI2C_NO_STARTSTOP Don't Generate stop and start condition.
  • FMPI2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • FMPI2C_GENERATE_START_READ Generate Restart for read request.
  • FMPI2C_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 4844 of file stm32f4xx_hal_fmpi2c.c.

References assert_param, FMPI2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_Master_ISR(), FMPI2C_RequestMemoryRead(), FMPI2C_RequestMemoryWrite(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles FMPI2C Communication Timeout.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Flag | Specifies the FMPI2C flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4601 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_FLAG, HAL_FMPI2C_STATE_READY, HAL_GetTick(), and FMPI2C_HandleTypeDef::State.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_RequestMemoryRead(), FMPI2C_RequestMemoryWrite(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Transmit(), and HAL_FMPI2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4722 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_RESET_CR2, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_STATE_READY, HAL_GetTick(), and FMPI2C_HandleTypeDef::State.

Referenced by HAL_FMPI2C_Slave_Receive().

static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles FMPI2C Communication Timeout for specific usage of STOP flag.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4687 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_STOPF, FMPI2C_IsAcknowledgeFailed(), HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_STATE_READY, HAL_GetTick(), and FMPI2C_HandleTypeDef::State.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Slave_Receive(), and HAL_FMPI2C_Slave_Transmit().

static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles FMPI2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4650 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_TXIS, FMPI2C_IsAcknowledgeFailed(), HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_STATE_READY, HAL_GetTick(), and FMPI2C_HandleTypeDef::State.

Referenced by FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_RequestMemoryRead(), FMPI2C_RequestMemoryWrite(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Slave_Transmit().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
FMPI2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_FMPI2C_Init (FMPI2C_HandleTypeDef *hfmpi2c)
Initializes the FMPI2C according to the specified parameters in the FMPI2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hfmpi2c)
DeInitialize the FMPI2C peripheral.
__weak void | HAL_FMPI2C_MspInit (FMPI2C_HandleTypeDef *hfmpi2c)
Initialize the FMPI2C MSP.
__weak void | HAL_FMPI2C_MspDeInit (FMPI2C_HandleTypeDef *hfmpi2c)
DeInitialize the FMPI2C MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the FMPI2Cx peripheral:

      (+) User must Implement HAL_FMPI2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_FMPI2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_FMPI2C_DeInit() to restore the default configuration
          of the selected FMPI2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_FMPI2C_DeInit ( FMPI2C_HandleTypeDef * hfmpi2c )

DeInitialize the FMPI2C peripheral.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
HAL status

Definition at line 432 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_DISABLE, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_STATE_NONE, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_MspDeInit(), HAL_FMPI2C_STATE_BUSY, HAL_FMPI2C_STATE_RESET, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::PreviousState, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Init ( FMPI2C_HandleTypeDef * hfmpi2c )

Initializes the FMPI2C according to the specified parameters in the FMPI2C_InitTypeDef and initialize the associated handle.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
HAL status

Definition at line 347 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_DISABLE, __HAL_FMPI2C_ENABLE, FMPI2C_InitTypeDef::AddressingMode, assert_param, FMPI2C_InitTypeDef::DualAddressMode, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_ADDRESSINGMODE_10BIT, FMPI2C_ADDRESSINGMODE_7BIT, FMPI2C_STATE_NONE, FMPI2C_InitTypeDef::GeneralCallMode, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_MspInit(), HAL_FMPI2C_STATE_BUSY, HAL_FMPI2C_STATE_READY, HAL_FMPI2C_STATE_RESET, FMPI2C_HandleTypeDef::Init, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_ADDRESSING_MODE, IS_FMPI2C_DUAL_ADDRESS, IS_FMPI2C_GENERAL_CALL, IS_FMPI2C_NO_STRETCH, IS_FMPI2C_OWN_ADDRESS1, IS_FMPI2C_OWN_ADDRESS2, IS_FMPI2C_OWN_ADDRESS2_MASK, FMPI2C_HandleTypeDef::Lock, FMPI2C_HandleTypeDef::Mode, FMPI2C_InitTypeDef::NoStretchMode, FMPI2C_InitTypeDef::OwnAddress1, FMPI2C_InitTypeDef::OwnAddress2, FMPI2C_InitTypeDef::OwnAddress2Masks, FMPI2C_HandleTypeDef::PreviousState, FMPI2C_HandleTypeDef::State, FMPI2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_FMPI2C_MspDeInit ( FMPI2C_HandleTypeDef * hfmpi2c )

DeInitialize the FMPI2C MSP.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 483 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_DeInit().

void HAL_FMPI2C_MspInit ( FMPI2C_HandleTypeDef * hfmpi2c )

Initialize the FMPI2C MSP.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 468 of file stm32f4xx_hal_fmpi2c.c.

Referenced by HAL_FMPI2C_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
FMPI2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_IsDeviceReady (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Sequential_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Sequential_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Sequential_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Sequential_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_EnableListen_IT (FMPI2C_HandleTypeDef *hfmpi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_DisableListen_IT (FMPI2C_HandleTypeDef *hfmpi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Abort_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress)
Abort a master/host FMPI2C process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FMPI2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated FMPI2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_FMPI2C_Master_Transmit()
        (++) HAL_FMPI2C_Master_Receive()
        (++) HAL_FMPI2C_Slave_Transmit()
        (++) HAL_FMPI2C_Slave_Receive()
        (++) HAL_FMPI2C_Mem_Write()
        (++) HAL_FMPI2C_Mem_Read()
        (++) HAL_FMPI2C_IsDeviceReady()

    (#) No Blocking mode functions with Interrupt are :
        (++) HAL_FMPI2C_Master_Transmit_IT()
        (++) HAL_FMPI2C_Master_Receive_IT()
        (++) HAL_FMPI2C_Slave_Transmit_IT()
        (++) HAL_FMPI2C_Slave_Receive_IT()
        (++) HAL_FMPI2C_Mem_Write_IT()
        (++) HAL_FMPI2C_Mem_Read_IT()

    (#) No Blocking mode functions with DMA are :
        (++) HAL_FMPI2C_Master_Transmit_DMA()
        (++) HAL_FMPI2C_Master_Receive_DMA()
        (++) HAL_FMPI2C_Slave_Transmit_DMA()
        (++) HAL_FMPI2C_Slave_Receive_DMA()
        (++) HAL_FMPI2C_Mem_Write_DMA()
        (++) HAL_FMPI2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in no Blocking mode:
        (++) HAL_FMPI2C_MemTxCpltCallback()
        (++) HAL_FMPI2C_MemRxCpltCallback()
        (++) HAL_FMPI2C_MasterTxCpltCallback()
        (++) HAL_FMPI2C_MasterRxCpltCallback()
        (++) HAL_FMPI2C_SlaveTxCpltCallback()
        (++) HAL_FMPI2C_SlaveRxCpltCallback()
        (++) HAL_FMPI2C_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT ( FMPI2C_HandleTypeDef * hfmpi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C
Return values:
HAL status

Definition at line 2728 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_Disable_IRQ(), FMPI2C_IT_ADDR, FMPI2C_STATE_MSK, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_LISTEN, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::PreviousState, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT ( FMPI2C_HandleTypeDef * hfmpi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
HAL status

Definition at line 2705 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_Enable_IRQ(), FMPI2C_IT_ADDR, HAL_FMPI2C_STATE_LISTEN, HAL_FMPI2C_STATE_READY, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2316 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, FMPI2C_InitTypeDef::AddressingMode, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_AF, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_STOPF, FMPI2C_GENERATE_START, FMPI2C_WaitOnFlagUntilTimeout(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_STATE_BUSY, HAL_FMPI2C_STATE_READY, HAL_FMPI2C_STATE_TIMEOUT, HAL_GetTick(), FMPI2C_HandleTypeDef::Init, FMPI2C_HandleTypeDef::Instance, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host FMPI2C process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
Return values:
HAL status

Definition at line 2760 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_Enable_IRQ(), FMPI2C_GENERATE_STOP, FMPI2C_IT_RX, FMPI2C_IT_TX, FMPI2C_STATE_MASTER_BUSY_RX, FMPI2C_STATE_MASTER_BUSY_TX, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_BUSY_TX, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::PreviousState, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Master_Receive | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 687 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_GENERATE_START_READ, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RESET_CR2, FMPI2C_TIMEOUT_STOPF, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in no blocking mode with DMA.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1389 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_DMAError(), FMPI2C_DMAMasterReceiveCplt(), FMPI2C_FLAG_BUSY, FMPI2C_FLAG_RXNE, FMPI2C_GENERATE_START_READ, FMPI2C_RELOAD_MODE, FMPI2C_TIMEOUT_RXNE, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmarx, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in no blocking mode with Interrupt.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1121 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_ENABLE_IT, __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_GENERATE_START_READ, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_RXI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_NO_OPTION_FRAME, FMPI2C_RELOAD_MODE, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master FMPI2C mode an amount of data in no blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of FMPI2C XferOptions definition
Return values:
HAL status

Definition at line 2510 of file stm32f4xx_hal_fmpi2c.c.

References assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_Enable_IRQ(), FMPI2C_GENERATE_START_READ, FMPI2C_IT_RX, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_STATE_MASTER_BUSY_RX, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, IS_FMPI2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::PreviousState, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master FMPI2C mode an amount of data in no blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of FMPI2C XferOptions definition
Return values:
HAL status

Definition at line 2434 of file stm32f4xx_hal_fmpi2c.c.

References assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_Enable_IRQ(), FMPI2C_GENERATE_START_WRITE, FMPI2C_IT_TX, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_STATE_SLAVE_BUSY_TX, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, IS_FMPI2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::PreviousState, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 565 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_GENERATE_START_WRITE, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RESET_CR2, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in no blocking mode with DMA.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1298 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_DMAError(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_FLAG_BUSY, FMPI2C_GENERATE_START_WRITE, FMPI2C_RELOAD_MODE, FMPI2C_TIMEOUT_TXIS, FMPI2C_TransferConfig(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmatx, FMPI2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in no blocking mode with Interrupt.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1047 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_ENABLE_IT, __HAL_FMPI2C_GET_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_GENERATE_START_WRITE, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_IT_TXI, FMPI2C_NO_OPTION_FRAME, FMPI2C_RELOAD_MODE, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Mem_Read | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1777 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_GENERATE_START_READ, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RequestMemoryRead(), FMPI2C_RESET_CR2, FMPI2C_TIMEOUT_STOPF, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_MEMADD_SIZE, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in no blocking mode with DMA from a specific memory address.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 2216 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_DMAError(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_FLAG_BUSY, FMPI2C_FLAG_RXNE, FMPI2C_GENERATE_START_READ, FMPI2C_RELOAD_MODE, FMPI2C_RequestMemoryRead(), FMPI2C_TIMEOUT_FLAG, FMPI2C_TIMEOUT_RXNE, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmarx, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_MEMADD_SIZE, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in no blocking mode with Interrupt from a specific memory address.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2011 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_ENABLE_IT, __HAL_FMPI2C_GET_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_GENERATE_START_READ, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_RXI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_NO_OPTION_FRAME, FMPI2C_RELOAD_MODE, FMPI2C_RequestMemoryRead(), FMPI2C_TIMEOUT_FLAG, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, IS_FMPI2C_MEMADD_SIZE, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Mem_Write | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1633 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TCR, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RequestMemoryWrite(), FMPI2C_RESET_CR2, FMPI2C_TIMEOUT_STOPF, FMPI2C_TransferConfig(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_MEMADD_SIZE, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in no blocking mode with DMA to a specific memory address.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2106 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_DMAError(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_FLAG_BUSY, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RequestMemoryWrite(), FMPI2C_TIMEOUT_FLAG, FMPI2C_TIMEOUT_TXIS, FMPI2C_TransferConfig(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmatx, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_MEMADD_SIZE, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in no blocking mode with Interrupt to a specific memory address.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1916 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_ENABLE_IT, __HAL_FMPI2C_GET_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_AUTOEND_MODE, FMPI2C_FLAG_BUSY, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_IT_TXI, FMPI2C_NO_OPTION_FRAME, FMPI2C_NO_STARTSTOP, FMPI2C_RELOAD_MODE, FMPI2C_RequestMemoryWrite(), FMPI2C_TIMEOUT_FLAG, FMPI2C_TransferConfig(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, IS_FMPI2C_MEMADD_SIZE, MAX_NBYTE_SIZE, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 933 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_ADDR, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_DIR, FMPI2C_FLAG_STOPF, FMPI2C_TIMEOUT_STOPF, FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_TIMEOUT, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in no blocking mode with DMA.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1557 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_DMAError(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_FLAG_ADDR, FMPI2C_FLAG_DIR, FMPI2C_TIMEOUT_ADDR, FMPI2C_TIMEOUT_DIR, FMPI2C_WaitOnFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmarx, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in no blocking mode with Interrupt.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1245 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_ENABLE_IT, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_IT_ADDRI, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_RXI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_NO_OPTION_FRAME, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of FMPI2C XferOptions definition
Return values:
HAL status

Definition at line 2647 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_FLAG_ADDR, FMPI2C_IT_ADDR, FMPI2C_IT_RX, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_RX_LISTEN, HAL_FMPI2C_STATE_LISTEN, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_TRANSFER_OPTIONS_REQUEST, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of FMPI2C XferOptions definition
Return values:
HAL status

Definition at line 2585 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, assert_param, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_FLAG_ADDR, FMPI2C_IT_ADDR, FMPI2C_IT_TX, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_TX_LISTEN, HAL_FMPI2C_STATE_LISTEN, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_TRANSFER_OPTIONS_REQUEST, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 802 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_InitTypeDef::AddressingMode, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_ADDRESSINGMODE_10BIT, FMPI2C_FLAG_ADDR, FMPI2C_FLAG_BUSY, FMPI2C_FLAG_DIR, FMPI2C_FLAG_STOPF, FMPI2C_TIMEOUT_STOPF, FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_ERROR_AF, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Init, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in no blocking mode with DMA.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1470 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, FMPI2C_InitTypeDef::AddressingMode, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_ADDRESSINGMODE_10BIT, FMPI2C_DMAError(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_FLAG_ADDR, FMPI2C_FLAG_DIR, FMPI2C_TIMEOUT_ADDR, FMPI2C_TIMEOUT_BUSY, FMPI2C_WaitOnFlagUntilTimeout(), HAL_DMA_Start_IT(), HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::hdmatx, FMPI2C_HandleTypeDef::Init, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and FMPI2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in no blocking mode with Interrupt.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1193 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_ENABLE_IT, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_IT_ADDRI, FMPI2C_IT_ERRI, FMPI2C_IT_NACKI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_IT_TXI, FMPI2C_NO_OPTION_FRAME, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::pBuffPtr, FMPI2C_HandleTypeDef::State, FMPI2C_HandleTypeDef::XferCount, FMPI2C_HandleTypeDef::XferOptions, and FMPI2C_HandleTypeDef::XferSize.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
FMPI2C Exported Functions

Functions

void | HAL_FMPI2C_EV_IRQHandler (FMPI2C_HandleTypeDef *hfmpi2c)
This function handles FMPI2C event interrupt request.
void | HAL_FMPI2C_ER_IRQHandler (FMPI2C_HandleTypeDef *hfmpi2c)
This function handles FMPI2C error interrupt request.
__weak void | HAL_FMPI2C_MasterTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Master Tx Transfer completed callback.
__weak void | HAL_FMPI2C_MasterRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Master Rx Transfer completed callback.
__weak void | HAL_FMPI2C_SlaveTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_FMPI2C_SlaveRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_FMPI2C_AddrCallback (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_FMPI2C_ListenCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Listen Complete callback.
__weak void | HAL_FMPI2C_MemTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_FMPI2C_MemRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_FMPI2C_ErrorCallback (FMPI2C_HandleTypeDef *hfmpi2c)
FMPI2C error callback.

Function Documentation

void HAL_FMPI2C_AddrCallback | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
TransferDirection,: Master request Transfer Direction (Write/Read), value of FMPI2C XferOptions definition
AddrMatchCode,: Address Match Code
Return values:
None

Definition at line 3006 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Slave_ISR().

void HAL_FMPI2C_ER_IRQHandler ( FMPI2C_HandleTypeDef * hfmpi2c )

This function handles FMPI2C error interrupt request.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 2890 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_CLEAR_FLAG, __HAL_FMPI2C_GET_FLAG, __HAL_FMPI2C_GET_IT_SOURCE, FMPI2C_HandleTypeDef::ErrorCode, FMPI2C_FLAG_ARLO, FMPI2C_FLAG_BERR, FMPI2C_FLAG_OVR, FMPI2C_IT_ERRI, FMPI2C_STATE_NONE, HAL_FMPI2C_ERROR_ARLO, HAL_FMPI2C_ERROR_BERR, HAL_FMPI2C_ERROR_NONE, HAL_FMPI2C_ERROR_OVR, HAL_FMPI2C_ErrorCallback(), HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_RX, HAL_FMPI2C_STATE_BUSY_TX, HAL_FMPI2C_STATE_LISTEN, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::PreviousState, and FMPI2C_HandleTypeDef::State.

void HAL_FMPI2C_ErrorCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

FMPI2C error callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 3068 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAError(), FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), and HAL_FMPI2C_ER_IRQHandler().

void HAL_FMPI2C_EV_IRQHandler ( FMPI2C_HandleTypeDef * hfmpi2c )

This function handles FMPI2C event interrupt request.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 2826 of file stm32f4xx_hal_fmpi2c.c.

References __HAL_FMPI2C_GET_IT_SOURCE, FMPI2C_CHECK_FLAG, FMPI2C_FLAG_ADDR, FMPI2C_FLAG_AF, FMPI2C_FLAG_RXNE, FMPI2C_FLAG_STOPF, FMPI2C_FLAG_TC, FMPI2C_FLAG_TCR, FMPI2C_FLAG_TXIS, FMPI2C_GET_ISR_REG, FMPI2C_IT_ADDRI, FMPI2C_IT_NACKI, FMPI2C_IT_RXI, FMPI2C_IT_STOPI, FMPI2C_IT_TCI, FMPI2C_IT_TXI, FMPI2C_Master_ISR(), FMPI2C_NO_OPTION_FRAME, FMPI2C_Slave_ISR(), HAL_FMPI2C_MODE_MASTER, HAL_FMPI2C_MODE_MEM, HAL_FMPI2C_MODE_SLAVE, HAL_FMPI2C_STATE_BUSY_RX_LISTEN, HAL_FMPI2C_STATE_BUSY_TX_LISTEN, HAL_FMPI2C_STATE_LISTEN, FMPI2C_HandleTypeDef::Mode, FMPI2C_HandleTypeDef::State, and FMPI2C_HandleTypeDef::XferOptions.

void HAL_FMPI2C_ListenCpltCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

Listen Complete callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 3023 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_Slave_ISR().

void HAL_FMPI2C_MasterRxCpltCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

Master Rx Transfer completed callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 2960 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMasterReceiveCplt(), and FMPI2C_Master_ISR().

void HAL_FMPI2C_MasterTxCpltCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

Master Tx Transfer completed callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 2945 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMasterTransmitCplt(), and FMPI2C_Master_ISR().

void HAL_FMPI2C_MemRxCpltCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

Memory Rx Transfer completed callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 3053 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMemReceiveCplt(), and FMPI2C_Master_ISR().

void HAL_FMPI2C_MemTxCpltCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

Memory Tx Transfer completed callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 3038 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMAMemTransmitCplt(), and FMPI2C_Master_ISR().

void HAL_FMPI2C_SlaveRxCpltCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

Slave Rx Transfer completed callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 2989 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMASlaveReceiveCplt(), and FMPI2C_Slave_ISR().

void HAL_FMPI2C_SlaveTxCpltCallback ( FMPI2C_HandleTypeDef * hfmpi2c )

Slave Tx Transfer completed callback.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
None

Definition at line 2974 of file stm32f4xx_hal_fmpi2c.c.

Referenced by FMPI2C_DMASlaveTransmitCplt(), and FMPI2C_Slave_ISR().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FMPI2C Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_FMPI2C_StateTypeDef | HAL_FMPI2C_GetState (FMPI2C_HandleTypeDef *hfmpi2c)
Return the FMPI2C handle state.
HAL_FMPI2C_ModeTypeDef | HAL_FMPI2C_GetMode (FMPI2C_HandleTypeDef *hfmpi2c)
Returns the FMPI2C Master, Slave, Memory or no mode.
uint32_t | HAL_FMPI2C_GetError (FMPI2C_HandleTypeDef *hfmpi2c)
Return the FMPI2C error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_FMPI2C_GetError ( FMPI2C_HandleTypeDef * hfmpi2c )

Return the FMPI2C error code.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
FMPI2C Error Code

Definition at line 3125 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_HandleTypeDef::ErrorCode.

HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode ( FMPI2C_HandleTypeDef * hfmpi2c )

Returns the FMPI2C Master, Slave, Memory or no mode.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for FMPI2C module
Return values:
HAL mode

Definition at line 3114 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_HandleTypeDef::Mode.

HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState ( FMPI2C_HandleTypeDef * hfmpi2c )

Return the FMPI2C handle state.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2C.
Return values:
HAL state

Definition at line 3102 of file stm32f4xx_hal_fmpi2c.c.

References FMPI2C_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FMPI2C_InitTypeDef Struct Reference
FMPI2C Configuration Structure definition

#include <stm32f4xx_hal_fmpi2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 68 of file stm32f4xx_hal_fmpi2c.h.

Field Documentation

uint32_t FMPI2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of FMPI2C addressing mode

Definition at line 77 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR(), HAL_FMPI2C_Init(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Slave_Transmit(), and HAL_FMPI2C_Slave_Transmit_DMA().

uint32_t FMPI2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of FMPI2C dual addressing mode

Definition at line 80 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

uint32_t FMPI2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of FMPI2C general call addressing mode

Definition at line 89 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

uint32_t FMPI2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of FMPI2C nostretch mode

Definition at line 92 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

uint32_t FMPI2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 74 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

uint32_t FMPI2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 83 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

uint32_t FMPI2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of FMPI2C own address2 masks

Definition at line 86 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

uint32_t FMPI2C_InitTypeDef::Timing

Specifies the FMPI2C_TIMINGR_register value. This parameter calculated by referring to FMPI2C initialization section in Reference manual

Definition at line 70 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_fmpi2c.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
FMPI2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_FMPI2C_StateTypeDef {
HAL_FMPI2C_STATE_RESET = 0x00U, HAL_FMPI2C_STATE_READY = 0x20U, HAL_FMPI2C_STATE_BUSY = 0x24U, HAL_FMPI2C_STATE_BUSY_TX = 0x21U,
HAL_FMPI2C_STATE_BUSY_RX = 0x22U, HAL_FMPI2C_STATE_LISTEN = 0x28U, HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, HAL_FMPI2C_STATE_ERROR = 0xE0U
}
enum HAL_FMPI2C_ModeTypeDef { HAL_FMPI2C_MODE_NONE = 0x00U, HAL_FMPI2C_MODE_MASTER = 0x10U, HAL_FMPI2C_MODE_SLAVE = 0x20U, HAL_FMPI2C_MODE_MEM = 0x40U }
HAL State structures definition. More...

Detailed Description

HAL State structure definition.

Enumeration Type Documentation

enum HAL_FMPI2C_ModeTypeDef

HAL State structures definition.

Enumerator:
HAL_FMPI2C_MODE_NONE

No FMPI2C communication on going

HAL_FMPI2C_MODE_MASTER

FMPI2C communication is in Master Mode

HAL_FMPI2C_MODE_SLAVE

FMPI2C communication is in Slave Mode

HAL_FMPI2C_MODE_MEM

FMPI2C communication is in Memory Mode

Definition at line 125 of file stm32f4xx_hal_fmpi2c.h.

enum HAL_FMPI2C_StateTypeDef
Enumerator:
HAL_FMPI2C_STATE_RESET

Peripheral is not yet Initialized

HAL_FMPI2C_STATE_READY

Peripheral Initialized and ready for use

HAL_FMPI2C_STATE_BUSY

An internal process is ongoing

HAL_FMPI2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_FMPI2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_FMPI2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_FMPI2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_FMPI2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_FMPI2C_STATE_TIMEOUT

Timeout state

HAL_FMPI2C_STATE_ERROR

Error

Definition at line 106 of file stm32f4xx_hal_fmpi2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Error Code definition

Defines
FMPI2C Error Code definition
FMPI2C Exported Types

FMPI2C Error Code definition. More...

Defines

#define | HAL_FMPI2C_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FMPI2C_ERROR_BERR ((uint32_t)0x00000001U)
#define | HAL_FMPI2C_ERROR_ARLO ((uint32_t)0x00000002U)
#define | HAL_FMPI2C_ERROR_AF ((uint32_t)0x00000004U)
#define | HAL_FMPI2C_ERROR_OVR ((uint32_t)0x00000008U)
#define | HAL_FMPI2C_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_FMPI2C_ERROR_TIMEOUT ((uint32_t)0x00000020U)
#define | HAL_FMPI2C_ERROR_SIZE ((uint32_t)0x00000040U)

Detailed Description

FMPI2C Error Code definition.

Define Documentation

#define HAL_FMPI2C_ERROR_AF ((uint32_t)0x00000004U)

ACKF error

Definition at line 145 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_RequestMemoryRead(), FMPI2C_RequestMemoryWrite(), FMPI2C_Slave_ISR(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive(), and HAL_FMPI2C_Slave_Transmit().

#define HAL_FMPI2C_ERROR_ARLO ((uint32_t)0x00000002U)

ARLO error

Definition at line 144 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_ER_IRQHandler().

#define HAL_FMPI2C_ERROR_BERR ((uint32_t)0x00000001U)

BERR error

Definition at line 143 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_ER_IRQHandler().

#define HAL_FMPI2C_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 147 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAError().

#define HAL_FMPI2C_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 142 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_Init(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit(), HAL_FMPI2C_Slave_Transmit_DMA(), and HAL_FMPI2C_Slave_Transmit_IT().

#define HAL_FMPI2C_ERROR_OVR ((uint32_t)0x00000008U)

OVR error

Definition at line 146 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_ER_IRQHandler().

#define HAL_FMPI2C_ERROR_SIZE ((uint32_t)0x00000040U)

Size Management error

Definition at line 149 of file stm32f4xx_hal_fmpi2c.h.

#define HAL_FMPI2C_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Timeout error

Definition at line 148 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), and HAL_FMPI2C_Slave_Receive().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C XferOptions definition

Defines
FMPI2C XferOptions definition
FMPI2C Exported Types

Defines

#define | FMPI2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)
#define | FMPI2C_FIRST_FRAME ((uint32_t)FMPI2C_SOFTEND_MODE)
#define | FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
#define | FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
#define | FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)

Define Documentation

#define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)

Definition at line 160 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

#define FMPI2C_FIRST_FRAME ((uint32_t)FMPI2C_SOFTEND_MODE)

Definition at line 158 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)

Definition at line 161 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

#define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))

Definition at line 159 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

#define FMPI2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)

Definition at line 157 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FMPI2C_HandleTypeDef Struct Reference
FMPI2C handle Structure definition

#include <stm32f4xx_hal_fmpi2c.h>

Data Fields

FMPI2C_TypeDef * | Instance
FMPI2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_FMPI2C_StateTypeDef | State
__IO HAL_FMPI2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount

Detailed Description

Definition at line 170 of file stm32f4xx_hal_fmpi2c.h.

Field Documentation

__IO uint32_t FMPI2C_HandleTypeDef::AddrEventCount

FMPI2C Address Event counter

Definition at line 198 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

__IO uint32_t FMPI2C_HandleTypeDef::ErrorCode

FMPI2C Error code

Definition at line 196 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAError(), FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_RequestMemoryRead(), FMPI2C_RequestMemoryWrite(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_GetError(), HAL_FMPI2C_Init(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit(), HAL_FMPI2C_Slave_Transmit_DMA(), and HAL_FMPI2C_Slave_Transmit_IT().

DMA_HandleTypeDef* FMPI2C_HandleTypeDef::hdmarx

FMPI2C Rx DMA handle parameters

Definition at line 188 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMemReceiveCplt(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Mem_Read_DMA(), and HAL_FMPI2C_Slave_Receive_DMA().

DMA_HandleTypeDef* FMPI2C_HandleTypeDef::hdmatx

FMPI2C Tx DMA handle parameters

Definition at line 186 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemTransmitCplt(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Slave_Transmit_DMA().

FMPI2C_InitTypeDef FMPI2C_HandleTypeDef::Init

FMPI2C communication parameters

Definition at line 174 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR(), HAL_FMPI2C_Init(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Slave_Transmit(), and HAL_FMPI2C_Slave_Transmit_DMA().

FMPI2C_TypeDef* FMPI2C_HandleTypeDef::Instance

FMPI2C registers base address

Definition at line 172 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAError(), FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_RequestMemoryRead(), FMPI2C_RequestMemoryWrite(), FMPI2C_Slave_ISR(), FMPI2C_TransferConfig(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_Init(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit(), HAL_FMPI2C_Slave_Transmit_DMA(), HAL_FMPI2C_Slave_Transmit_IT(), HAL_FMPI2CEx_ConfigAnalogFilter(), HAL_FMPI2CEx_ConfigDigitalFilter(), HAL_FMPI2CEx_DisableWakeUp(), and HAL_FMPI2CEx_EnableWakeUp().

HAL_LockTypeDef FMPI2C_HandleTypeDef::Lock

FMPI2C locking object

Definition at line 190 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

__IO HAL_FMPI2C_ModeTypeDef FMPI2C_HandleTypeDef::Mode

FMPI2C communication mode

Definition at line 194 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAError(), FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_DisableListen_IT(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_GetMode(), HAL_FMPI2C_Init(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit(), HAL_FMPI2C_Slave_Transmit_DMA(), and HAL_FMPI2C_Slave_Transmit_IT().

uint8_t* FMPI2C_HandleTypeDef::pBuffPtr

Pointer to FMPI2C transfer buffer

Definition at line 176 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit_DMA(), and HAL_FMPI2C_Slave_Transmit_IT().

__IO uint32_t FMPI2C_HandleTypeDef::PreviousState

FMPI2C communication Previous state

Definition at line 184 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_DisableListen_IT(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_Init(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), and HAL_FMPI2C_Master_Sequential_Transmit_IT().

__IO HAL_FMPI2C_StateTypeDef FMPI2C_HandleTypeDef::State

FMPI2C communication state

Definition at line 192 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_DMAError(), FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_DisableListen_IT(), HAL_FMPI2C_EnableListen_IT(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_GetState(), HAL_FMPI2C_Init(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit(), HAL_FMPI2C_Slave_Transmit_DMA(), HAL_FMPI2C_Slave_Transmit_IT(), HAL_FMPI2CEx_ConfigAnalogFilter(), HAL_FMPI2CEx_ConfigDigitalFilter(), HAL_FMPI2CEx_DisableWakeUp(), and HAL_FMPI2CEx_EnableWakeUp().

__IO uint16_t FMPI2C_HandleTypeDef::XferCount

FMPI2C transfer counter

Definition at line 180 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAError(), FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit_DMA(), and HAL_FMPI2C_Slave_Transmit_IT().

__IO uint32_t FMPI2C_HandleTypeDef::XferOptions

FMPI2C transfer options

Definition at line 182 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

uint16_t FMPI2C_HandleTypeDef::XferSize

FMPI2C transfer size

Definition at line 178 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit_DMA(), and HAL_FMPI2C_Slave_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_fmpi2c.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C addressing mode

Defines
FMPI2C addressing mode
FMPI2C Exported Constants

Defines

#define | FMPI2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U)
#define | FMPI2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U)

Define Documentation

#define FMPI2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U)

Definition at line 217 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR(), HAL_FMPI2C_Init(), HAL_FMPI2C_Slave_Transmit(), and HAL_FMPI2C_Slave_Transmit_DMA().

#define FMPI2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U)

Definition at line 216 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR(), and HAL_FMPI2C_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C dual addressing mode

Defines
FMPI2C dual addressing mode
FMPI2C Exported Constants

Defines

#define | FMPI2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define | FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN

Define Documentation

#define FMPI2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)

Definition at line 227 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN

Definition at line 228 of file stm32f4xx_hal_fmpi2c.h.

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STM32F410Rx HAL User Manual: FMPI2C own address2 masks

Defines
FMPI2C own address2 masks
FMPI2C Exported Constants

Defines

#define | FMPI2C_OA2_NOMASK ((uint8_t)0x00U)
#define | FMPI2C_OA2_MASK01 ((uint8_t)0x01U)
#define | FMPI2C_OA2_MASK02 ((uint8_t)0x02U)
#define | FMPI2C_OA2_MASK03 ((uint8_t)0x03U)
#define | FMPI2C_OA2_MASK04 ((uint8_t)0x04U)
#define | FMPI2C_OA2_MASK05 ((uint8_t)0x05U)
#define | FMPI2C_OA2_MASK06 ((uint8_t)0x06U)
#define | FMPI2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define FMPI2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 239 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 240 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 241 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 242 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 243 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 244 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 245 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 238 of file stm32f4xx_hal_fmpi2c.h.

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STM32F410Rx HAL User Manual: FMPI2C general call addressing mode

Defines
FMPI2C general call addressing mode
FMPI2C Exported Constants

Defines

#define | FMPI2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define | FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN

Define Documentation

#define FMPI2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)

Definition at line 254 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN

Definition at line 255 of file stm32f4xx_hal_fmpi2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C nostretch mode

Defines
FMPI2C nostretch mode
FMPI2C Exported Constants

Defines

#define | FMPI2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define | FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH

Define Documentation

#define FMPI2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)

Definition at line 264 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH

Definition at line 265 of file stm32f4xx_hal_fmpi2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Memory Address Size

Defines
FMPI2C Memory Address Size
FMPI2C Exported Constants

Defines

#define | FMPI2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define | FMPI2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U)

Define Documentation

#define FMPI2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U)

Definition at line 275 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)

Definition at line 274 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_RequestMemoryRead(), and FMPI2C_RequestMemoryWrite().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C XferDirection definition

Defines
FMPI2C XferDirection definition
FMPI2C Exported Constants

Defines

#define | FMPI2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
#define | FMPI2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)

Define Documentation

#define FMPI2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)

Definition at line 284 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)

Definition at line 285 of file stm32f4xx_hal_fmpi2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C ReloadEndMode definition

Defines
FMPI2C ReloadEndMode definition
FMPI2C Exported Constants

Defines

#define | FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD
#define | FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND
#define | FMPI2C_SOFTEND_MODE ((uint32_t)0x00000000U)

Define Documentation

#define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND

Definition at line 295 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

#define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD

Definition at line 294 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_Master_ISR(), FMPI2C_RequestMemoryWrite(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

#define FMPI2C_SOFTEND_MODE ((uint32_t)0x00000000U)

Definition at line 296 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_RequestMemoryRead().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C StartStopMode definition

Defines
FMPI2C StartStopMode definition
FMPI2C Exported Constants

Defines

#define | FMPI2C_NO_STARTSTOP ((uint32_t)0x00000000U)
#define | FMPI2C_GENERATE_STOP FMPI2C_CR2_STOP
#define | FMPI2C_GENERATE_START_READ (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
#define | FMPI2C_GENERATE_START_WRITE FMPI2C_CR2_START

Define Documentation

#define FMPI2C_GENERATE_START_READ (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)

Definition at line 308 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), and HAL_FMPI2C_Mem_Read_IT().

#define FMPI2C_GENERATE_START_WRITE FMPI2C_CR2_START

Definition at line 309 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_RequestMemoryRead(), FMPI2C_RequestMemoryWrite(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), and HAL_FMPI2C_Master_Transmit_IT().

#define FMPI2C_GENERATE_STOP FMPI2C_CR2_STOP

Definition at line 307 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Master_Abort_IT().

#define FMPI2C_NO_STARTSTOP ((uint32_t)0x00000000U)

Definition at line 306 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_Master_ISR(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Interrupt configuration definition

Defines
FMPI2C Interrupt configuration definition
FMPI2C Exported Constants

FMPI2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE
#define | FMPI2C_IT_TCI FMPI2C_CR1_TCIE
#define | FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE
#define | FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE
#define | FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE
#define | FMPI2C_IT_RXI FMPI2C_CR1_RXIE
#define | FMPI2C_IT_TXI FMPI2C_CR1_TXIE
#define | FMPI2C_IT_TX (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI)
#define | FMPI2C_IT_RX (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI)
#define | FMPI2C_IT_ADDR (FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI)

Detailed Description

FMPI2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define FMPI2C_IT_ADDR (FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI)

Definition at line 330 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_DisableListen_IT(), HAL_FMPI2C_EnableListen_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), and HAL_FMPI2C_Slave_Sequential_Transmit_IT().

#define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE

Definition at line 325 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Slave_Receive_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

#define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE

Definition at line 321 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

#define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE

Definition at line 324 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

#define FMPI2C_IT_RX (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI)

Definition at line 329 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Sequential_Receive_IT(), and HAL_FMPI2C_Slave_Sequential_Receive_IT().

#define FMPI2C_IT_RXI FMPI2C_CR1_RXIE

Definition at line 326 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Mem_Read_IT(), and HAL_FMPI2C_Slave_Receive_IT().

#define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE

Definition at line 323 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

#define FMPI2C_IT_TCI FMPI2C_CR1_TCIE

Definition at line 322 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

#define FMPI2C_IT_TX (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI)

Definition at line 328 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_Master_Abort_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), and HAL_FMPI2C_Slave_Sequential_Transmit_IT().

#define FMPI2C_IT_TXI FMPI2C_CR1_TXIE

Definition at line 327 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), FMPI2C_Enable_IRQ(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Write_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Flag definition

Defines
FMPI2C Flag definition
FMPI2C Exported Constants

Defines

#define | FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
#define | FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
#define | FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
#define | FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR
#define | FMPI2C_FLAG_AF FMPI2C_ISR_NACKF
#define | FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF
#define | FMPI2C_FLAG_TC FMPI2C_ISR_TC
#define | FMPI2C_FLAG_TCR FMPI2C_ISR_TCR
#define | FMPI2C_FLAG_BERR FMPI2C_ISR_BERR
#define | FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO
#define | FMPI2C_FLAG_OVR FMPI2C_ISR_OVR
#define | FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR
#define | FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
#define | FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT
#define | FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY
#define | FMPI2C_FLAG_DIR FMPI2C_ISR_DIR

Define Documentation

#define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR

Definition at line 343 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit(), and HAL_FMPI2C_Slave_Transmit_DMA().

#define FMPI2C_FLAG_AF FMPI2C_ISR_NACKF

Definition at line 344 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), HAL_FMPI2C_EV_IRQHandler(), and HAL_FMPI2C_IsDeviceReady().

#define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT

Definition at line 353 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO

Definition at line 349 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_ER_IRQHandler().

#define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR

Definition at line 348 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_ER_IRQHandler().

#define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY

Definition at line 354 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive(), and HAL_FMPI2C_Slave_Transmit().

#define FMPI2C_FLAG_DIR FMPI2C_ISR_DIR

Definition at line 355 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Transmit(), and HAL_FMPI2C_Slave_Transmit_DMA().

#define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR

Definition at line 350 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_ER_IRQHandler().

#define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR

Definition at line 351 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE

Definition at line 342 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Mem_Read(), and HAL_FMPI2C_Mem_Read_DMA().

#define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF

Definition at line 345 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Slave_Receive(), and HAL_FMPI2C_Slave_Transmit().

#define FMPI2C_FLAG_TC FMPI2C_ISR_TC

Definition at line 346 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), FMPI2C_RequestMemoryRead(), and HAL_FMPI2C_EV_IRQHandler().

#define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR

Definition at line 347 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_Master_ISR(), FMPI2C_RequestMemoryWrite(), HAL_FMPI2C_EV_IRQHandler(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Mem_Read(), and HAL_FMPI2C_Mem_Write().

#define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT

Definition at line 352 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE

Definition at line 340 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), and FMPI2C_Slave_ISR().

#define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS

Definition at line 341 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnTXISFlagUntilTimeout(), and HAL_FMPI2C_EV_IRQHandler().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Exported Macros

Defines
FMPI2C Exported Macros
FMPI2C

Defines

#define | __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
Reset FMPI2C handle state.
#define | __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified FMPI2C interrupt.
#define | __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified FMPI2C interrupt.
#define | __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified FMPI2C interrupt source is enabled or not.
#define | FMPI2C_FLAG_MASK ((uint32_t)0x0001FFFFU)
Check whether the specified FMPI2C flag is set or not.
#define | __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
#define | __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
Enable the specified FMPI2C peripheral.
#define | __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
Disable the specified FMPI2C peripheral.

Define Documentation

#define __HAL_FMPI2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
                                                                                ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • FMPI2C_FLAG_TXE Transmit data register empty
  • FMPI2C_FLAG_ADDR Address matched (slave mode)
  • FMPI2C_FLAG_AF Acknowledge failure received flag
  • FMPI2C_FLAG_STOPF STOP detection flag
  • FMPI2C_FLAG_BERR Bus error
  • FMPI2C_FLAG_ARLO Arbitration lost
  • FMPI2C_FLAG_OVR Overrun/Underrun
  • FMPI2C_FLAG_PECERR PEC error in reception
  • FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • FMPI2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 467 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_DMASlaveReceiveCplt(), FMPI2C_DMASlaveTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Slave_Receive(), HAL_FMPI2C_Slave_Receive_DMA(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Transmit(), and HAL_FMPI2C_Slave_Transmit_DMA().

#define __HAL_FMPI2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))

Disable the specified FMPI2C peripheral.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
Return values:
None

Definition at line 480 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_Init(), HAL_FMPI2CEx_ConfigAnalogFilter(), HAL_FMPI2CEx_ConfigDigitalFilter(), HAL_FMPI2CEx_DisableWakeUp(), and HAL_FMPI2CEx_EnableWakeUp().

#define __HAL_FMPI2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified FMPI2C interrupt.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
__INTERRUPT__,: specifies the interrupt source to disable. This parameter can be one of the following values:
  • FMPI2C_IT_ERRI Errors interrupt enable
  • FMPI2C_IT_TCI Transfer complete interrupt enable
  • FMPI2C_IT_STOPI STOP detection interrupt enable
  • FMPI2C_IT_NACKI NACK received interrupt enable
  • FMPI2C_IT_ADDRI Address match interrupt enable
  • FMPI2C_IT_RXI RX interrupt enable
  • FMPI2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 406 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Disable_IRQ(), and FMPI2C_Slave_ISR().

#define __HAL_FMPI2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))

Enable the specified FMPI2C peripheral.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
Return values:
None

Definition at line 474 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR(), HAL_FMPI2C_Init(), HAL_FMPI2CEx_ConfigAnalogFilter(), HAL_FMPI2CEx_ConfigDigitalFilter(), HAL_FMPI2CEx_DisableWakeUp(), and HAL_FMPI2CEx_EnableWakeUp().

#define __HAL_FMPI2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified FMPI2C interrupt.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
__INTERRUPT__,: specifies the interrupt source to enable. This parameter can be one of the following values:
  • FMPI2C_IT_ERRI Errors interrupt enable
  • FMPI2C_IT_TCI Transfer complete interrupt enable
  • FMPI2C_IT_STOPI STOP detection interrupt enable
  • FMPI2C_IT_NACKI NACK received interrupt enable
  • FMPI2C_IT_ADDRI Address match interrupt enable
  • FMPI2C_IT_RXI RX interrupt enable
  • FMPI2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 390 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Enable_IRQ(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Receive_IT(), and HAL_FMPI2C_Slave_Transmit_IT().

#define __HAL_FMPI2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))

Definition at line 448 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnFlagUntilTimeout(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), FMPI2C_WaitOnSTOPFlagUntilTimeout(), FMPI2C_WaitOnTXISFlagUntilTimeout(), HAL_FMPI2C_ER_IRQHandler(), HAL_FMPI2C_IsDeviceReady(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Receive_DMA(), HAL_FMPI2C_Master_Receive_IT(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Master_Transmit_DMA(), HAL_FMPI2C_Master_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

#define __HAL_FMPI2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified FMPI2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
__INTERRUPT__,: specifies the FMPI2C interrupt source to check. This parameter can be one of the following values:
  • FMPI2C_IT_ERRI Errors interrupt enable
  • FMPI2C_IT_TCI Transfer complete interrupt enable
  • FMPI2C_IT_STOPI STOP detection interrupt enable
  • FMPI2C_IT_NACKI NACK received interrupt enable
  • FMPI2C_IT_ADDRI Address match interrupt enable
  • FMPI2C_IT_RXI RX interrupt enable
  • FMPI2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 422 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_ER_IRQHandler(), and HAL_FMPI2C_EV_IRQHandler().

#define __HAL_FMPI2C_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)

Reset FMPI2C handle state.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
Return values:
None

Definition at line 373 of file stm32f4xx_hal_fmpi2c.h.

#define FMPI2C_FLAG_MASK ((uint32_t)0x0001FFFFU)

Check whether the specified FMPI2C flag is set or not.

Parameters:
__HANDLE__ specifies the FMPI2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • FMPI2C_FLAG_TXE Transmit data register empty
  • FMPI2C_FLAG_TXIS Transmit interrupt status
  • FMPI2C_FLAG_RXNE Receive data register not empty
  • FMPI2C_FLAG_ADDR Address matched (slave mode)
  • FMPI2C_FLAG_AF Acknowledge failure received flag
  • FMPI2C_FLAG_STOPF STOP detection flag
  • FMPI2C_FLAG_TC Transfer complete (master mode)
  • FMPI2C_FLAG_TCR Transfer complete reload
  • FMPI2C_FLAG_BERR Bus error
  • FMPI2C_FLAG_ARLO Arbitration lost
  • FMPI2C_FLAG_OVR Overrun/Underrun
  • FMPI2C_FLAG_PECERR PEC error in reception
  • FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • FMPI2C_FLAG_ALERT SMBus alert
  • FMPI2C_FLAG_BUSY Bus busy
  • FMPI2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 447 of file stm32f4xx_hal_fmpi2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Private Constants

FMPI2C Private Constants
FMPI2C
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Private Macros

Defines
FMPI2C Private Macros
FMPI2C

Defines

#define | IS_FMPI2C_ADDRESSING_MODE(MODE)
#define | IS_FMPI2C_DUAL_ADDRESS(ADDRESS)
#define | IS_FMPI2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_FMPI2C_GENERAL_CALL(CALL)
#define | IS_FMPI2C_NO_STRETCH(STRETCH)
#define | IS_FMPI2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
#define | FMPI2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U)
#define | FMPI2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
#define | FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
#define | FMPI2C_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
#define | FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
#define | FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
#define | IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FFU)
#define | IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | FMPI2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Define Documentation

#define FMPI2C_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))

Definition at line 640 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_EV_IRQHandler().

#define FMPI2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))

Definition at line 651 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_IsDeviceReady().

#define FMPI2C_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U)

Definition at line 636 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

#define FMPI2C_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)

Definition at line 637 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

#define FMPI2C_GET_ISR_REG ( __HANDLE__ ) ((__HANDLE__)->Instance->ISR)

Definition at line 639 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_EV_IRQHandler().

#define FMPI2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)

Definition at line 641 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

#define FMPI2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)

Definition at line 642 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Slave_ISR().

#define FMPI2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)

Definition at line 638 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_Master_ISR().

#define FMPI2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 649 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_RequestMemoryRead(), and FMPI2C_RequestMemoryWrite().

#define FMPI2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 648 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_RequestMemoryRead(), and FMPI2C_RequestMemoryWrite().

#define FMPI2C_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))

Definition at line 634 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_DMAMasterReceiveCplt(), FMPI2C_DMAMasterTransmitCplt(), FMPI2C_DMAMemReceiveCplt(), FMPI2C_DMAMemTransmitCplt(), FMPI2C_IsAcknowledgeFailed(), FMPI2C_Master_ISR(), FMPI2C_Slave_ISR(), FMPI2C_WaitOnRXNEFlagUntilTimeout(), HAL_FMPI2C_Master_Receive(), HAL_FMPI2C_Master_Transmit(), HAL_FMPI2C_Mem_Read(), and HAL_FMPI2C_Mem_Write().

#define IS_FMPI2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
                                          ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))

Definition at line 595 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

#define IS_FMPI2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
                                          ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))

Definition at line 598 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

#define IS_FMPI2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
                                          ((CALL) == FMPI2C_GENERALCALL_ENABLE))

Definition at line 610 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

#define IS_FMPI2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
                                          ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))

Definition at line 616 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), and HAL_FMPI2C_Mem_Write_IT().

#define IS_FMPI2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
                                          ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))

Definition at line 613 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

#define IS_FMPI2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= (uint32_t)0x000003FFU)

Definition at line 645 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

#define IS_FMPI2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 646 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

#define IS_FMPI2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == FMPI2C_OA2_NOMASK)  || \
                                          ((MASK) == FMPI2C_OA2_MASK01) || \
                                          ((MASK) == FMPI2C_OA2_MASK02) || \
                                          ((MASK) == FMPI2C_OA2_MASK03) || \
                                          ((MASK) == FMPI2C_OA2_MASK04) || \
                                          ((MASK) == FMPI2C_OA2_MASK05) || \
                                          ((MASK) == FMPI2C_OA2_MASK06) || \
                                          ((MASK) == FMPI2C_OA2_MASK07))

Definition at line 601 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Init().

#define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == FMPI2C_FIRST_FRAME)              || \
                                                       ((REQUEST) == FMPI2C_NEXT_FRAME)               || \
                                                       ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME)     || \
                                                       ((REQUEST) == FMPI2C_LAST_FRAME))

Definition at line 629 of file stm32f4xx_hal_fmpi2c.h.

Referenced by HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), and HAL_FMPI2C_Slave_Sequential_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == FMPI2C_RELOAD_MODE)   || \
                                          ((MODE) == FMPI2C_AUTOEND_MODE) || \
                                          ((MODE) == FMPI2C_AUTOEND_MODE |FMPI2C_RELOAD_MODE) || \
                                          ((MODE) == FMPI2C_SOFTEND_MODE))

Definition at line 619 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == FMPI2C_GENERATE_STOP)         || \
                                          ((REQUEST) == FMPI2C_GENERATE_START_READ)  || \
                                          ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
                                          ((REQUEST) == FMPI2C_NO_STARTSTOP))

Definition at line 624 of file stm32f4xx_hal_fmpi2c.h.

Referenced by FMPI2C_TransferConfig().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Extended Private Constants

FMPI2C Extended Private Constants
Extended features functions
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Extended Private Macros

Defines
FMPI2C Extended Private Macros
Extended features functions

Defines

#define | IS_FMPI2C_ANALOG_FILTER(FILTER)
#define | IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_FMPI2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_FMPI2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
                                            ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))

Definition at line 121 of file stm32f4xx_hal_fmpi2c_ex.h.

Referenced by HAL_FMPI2CEx_ConfigAnalogFilter().

#define IS_FMPI2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 124 of file stm32f4xx_hal_fmpi2c_ex.h.

Referenced by HAL_FMPI2CEx_ConfigDigitalFilter().

#define IS_FMPI2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
                                            (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))

Definition at line 126 of file stm32f4xx_hal_fmpi2c_ex.h.

Referenced by HAL_FMPI2CEx_DisableFastModePlus(), and HAL_FMPI2CEx_EnableFastModePlus().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Extended Private Functions

FMPI2C Extended Private Functions
Extended features functions
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extended features functions

Modules | Functions
Extended features functions
FMPI2C Extended Exported Functions

Extended features functions. More...

Modules

FMPI2C Extended Private Constants
FMPI2C Extended Private Macros
FMPI2C Extended Private Functions

Functions

HAL_StatusTypeDef | HAL_FMPI2CEx_ConfigAnalogFilter (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter)
Configure FMPI2C Analog noise filter.
HAL_StatusTypeDef | HAL_FMPI2CEx_ConfigDigitalFilter (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
Configure FMPI2C Digital noise filter.
HAL_StatusTypeDef | HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
Enable FMPI2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
Disable FMPI2C wakeup from stop mode.
void | HAL_FMPI2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the FMPI2C fast mode plus driving capability.
void | HAL_FMPI2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the FMPI2C fast mode plus driving capability.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters
      (+) Configure Wake Up Feature

Function Documentation

HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure FMPI2C Analog noise filter.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2Cx peripheral.
AnalogFilter | New state of the Analog filter.
Return values:
HAL status

Definition at line 115 of file stm32f4xx_hal_fmpi2c_ex.c.

References __HAL_FMPI2C_DISABLE, __HAL_FMPI2C_ENABLE, assert_param, HAL_FMPI2C_STATE_BUSY, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_ANALOG_FILTER, and FMPI2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter | ( | FMPI2C_HandleTypeDef * | hfmpi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure FMPI2C Digital noise filter.

Parameters:
hfmpi2c | Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2Cx peripheral.
DigitalFilter | Coefficient of digital noise filter between 0x00 and 0x0F.
Return values:
HAL status

Definition at line 159 of file stm32f4xx_hal_fmpi2c_ex.c.

References __HAL_FMPI2C_DISABLE, __HAL_FMPI2C_ENABLE, assert_param, HAL_FMPI2C_STATE_BUSY, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, IS_FMPI2C_DIGITAL_FILTER, and FMPI2C_HandleTypeDef::State.

void HAL_FMPI2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the FMPI2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the FMPI2C Extended Fast Mode Plus values
Return values:
None

Definition at line 307 of file stm32f4xx_hal_fmpi2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_FMPI2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp ( FMPI2C_HandleTypeDef * hfmpi2c )

Disable FMPI2C wakeup from stop mode.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2Cx peripheral.
Return values:
HAL status

Definition at line 250 of file stm32f4xx_hal_fmpi2c_ex.c.

References __HAL_FMPI2C_DISABLE, __HAL_FMPI2C_ENABLE, assert_param, HAL_FMPI2C_STATE_BUSY, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, and FMPI2C_HandleTypeDef::State.

void HAL_FMPI2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the FMPI2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the FMPI2C Extended Fast Mode Plus values
Return values:
None

Definition at line 289 of file stm32f4xx_hal_fmpi2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_FMPI2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp ( FMPI2C_HandleTypeDef * hfmpi2c )

Enable FMPI2C wakeup from stop mode.

Parameters:
hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains the configuration information for the specified FMPI2Cx peripheral.
Return values:
HAL status

Definition at line 210 of file stm32f4xx_hal_fmpi2c_ex.c.

References __HAL_FMPI2C_DISABLE, __HAL_FMPI2C_ENABLE, assert_param, HAL_FMPI2C_STATE_BUSY, HAL_FMPI2C_STATE_READY, FMPI2C_HandleTypeDef::Instance, and FMPI2C_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Extended Analog Filter

Defines
FMPI2C Extended Analog Filter
FMPI2C Extended Exported Constants

Defines

#define | FMPI2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define | FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF

Define Documentation

#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF

Definition at line 70 of file stm32f4xx_hal_fmpi2c_ex.h.

#define FMPI2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)

Definition at line 69 of file stm32f4xx_hal_fmpi2c_ex.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FMPI2C Extended Fast Mode Plus

Defines
FMPI2C Extended Fast Mode Plus
FMPI2C Extended Exported Constants

Defines

#define | FMPI2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL
#define | FMPI2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA

Define Documentation

#define FMPI2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL

Enable Fast Mode Plus on FMPI2C1 SCL pins

Definition at line 78 of file stm32f4xx_hal_fmpi2c_ex.h.

#define FMPI2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA

Enable Fast Mode Plus on FMPI2C1 SDA pins

Definition at line 79 of file stm32f4xx_hal_fmpi2c_ex.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]
    This section provides functions allowing to initialize and de-initialize the GPIOs
    to be ready for use.

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 314 of file stm32f4xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and GPIO_NUMBER.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
GPIO_Init,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 189 of file stm32f4xx_hal_gpio.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_GET_INDEX, GPIO_MODE, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_EVT, GPIO_MODE_IT, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_NUMBER, GPIO_OUTPUT_TYPE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

GPIO Read and Write. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

GPIO Read and Write.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callbacks.

Parameters:
GPIO_Pin,: Specifies the pins connected EXTI line
Return values:
None

Definition at line 520 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

This function handles EXTI interrupt request.

Parameters:
GPIO_Pin,: Specifies the pins connected EXTI line
Return values:
None

Definition at line 505 of file stm32f4xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx,: where x can be (A..F) to select the GPIO peripheral for STM32F4 family
GPIO_Pin,: specifies the port bit to be locked. This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 472 of file stm32f4xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 395 of file stm32f4xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggles the specified GPIO pins.

Parameters:
GPIOx,: Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
GPIO_Pin,: Specifies the pins to be toggled.
Return values:
None

Definition at line 453 of file stm32f4xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Sets or clears the selected data port bit.

Note:
This function uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx,: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState,: specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 430 of file stm32f4xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 86 of file stm32f4xx_hal_gpio.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32f4xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 65 of file stm32f4xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins. This parameter can be a value of GPIO Alternate Function Selection

Definition at line 79 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode define

Definition at line 70 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins define

Definition at line 67 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull define

Definition at line 73 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed define

Definition at line 76 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_gpio.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO pins define

Defines
GPIO pins define
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */

Definition at line 104 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */

Definition at line 105 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */

Definition at line 114 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */

Definition at line 115 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */

Definition at line 116 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */

Definition at line 117 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */

Definition at line 118 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */

Definition at line 119 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */

Definition at line 106 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */

Definition at line 107 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */

Definition at line 108 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */

Definition at line 109 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */

Definition at line 110 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */

Definition at line 111 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */

Definition at line 112 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */

Definition at line 113 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */

Definition at line 120 of file stm32f4xx_hal_gpio.h.

#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */

Definition at line 122 of file stm32f4xx_hal_gpio.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO mode define

Defines
GPIO mode define
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT ((uint32_t)0x00000000U)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002U)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012U)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003U)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x10110000U)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U)

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U)

Alternate Function Open Drain Mode

Definition at line 141 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U)

Alternate Function Push Pull Mode

Definition at line 140 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U)

Analog Mode

Definition at line 143 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U)

External Event Mode with Falling edge trigger detection

Definition at line 150 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U)

External Event Mode with Rising edge trigger detection

Definition at line 149 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 151 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_INPUT ((uint32_t)0x00000000U)

Input Floating Mode

Definition at line 137 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 146 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 145 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 147 of file stm32f4xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U)

Output Open Drain Mode

Definition at line 139 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U)

Output Push Pull Mode

Definition at line 138 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO speed define

Defines
GPIO speed define
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U)

range 25 MHz to 100 MHz, please refer to the product datasheet

Definition at line 162 of file stm32f4xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)

IO works at 2 MHz, please refer to the product datasheet

Definition at line 160 of file stm32f4xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U)

range 12,5 MHz to 50 MHz, please refer to the product datasheet

Definition at line 161 of file stm32f4xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U)

range 50 MHz to 200 MHz, please refer to the product datasheet

Definition at line 163 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

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STM32F410Rx HAL User Manual: GPIO pull define

Defines
GPIO pull define
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL ((uint32_t)0x00000000U)
#define | GPIO_PULLUP ((uint32_t)0x00000001U)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002U)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL ((uint32_t)0x00000000U)

No Pull-up or Pull-down activation

Definition at line 172 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_PULLDOWN ((uint32_t)0x00000002U)

Pull-down activation

Definition at line 174 of file stm32f4xx_hal_gpio.h.

#define GPIO_PULLUP ((uint32_t)0x00000001U)

Pull-up activation

Definition at line 173 of file stm32f4xx_hal_gpio.h.

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STM32F410Rx HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clears the EXTI's line pending flags.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 202 of file stm32f4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clears the EXTI's line pending bits.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 218 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 226 of file stm32f4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Checks whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 194 of file stm32f4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Checks whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 210 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

Defines

#define | GPIO_MODE ((uint32_t)0x00000003U)
#define | EXTI_MODE ((uint32_t)0x10000000U)
#define | GPIO_MODE_IT ((uint32_t)0x00010000U)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define | RISING_EDGE ((uint32_t)0x00100000U)
#define | FALLING_EDGE ((uint32_t)0x00200000U)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define | GPIO_NUMBER ((uint32_t)16U)

Define Documentation

#define EXTI_MODE ((uint32_t)0x10000000U)

Definition at line 145 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE ((uint32_t)0x00200000U)

Definition at line 149 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE ((uint32_t)0x00000003U)

Definition at line 144 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT ((uint32_t)0x00020000U)

Definition at line 147 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT ((uint32_t)0x00010000U)

Definition at line 146 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER ((uint32_t)16U)

Definition at line 152 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)

Definition at line 150 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define RISING_EDGE ((uint32_t)0x00100000U)

Definition at line 148 of file stm32f4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

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STM32F410Rx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Define Documentation

#define IS_GPIO_MODE ( MODE )
Value:
(((MODE) == GPIO_MODE_INPUT)              ||\
                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
                            ((MODE) == GPIO_MODE_AF_PP)              ||\
                            ((MODE) == GPIO_MODE_AF_OD)              ||\
                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
                            ((MODE) == GPIO_MODE_ANALOG))

Definition at line 284 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( PIN ) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)

Definition at line 283 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 282 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( PULL )
Value:
(((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
                            ((PULL) == GPIO_PULLDOWN))

Definition at line 298 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( SPEED )
Value:
(((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 296 of file stm32f4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

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STM32F410Rx HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIO
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STM32F410Rx HAL User Manual: GPIO Alternate Function Selection

Defines
GPIO Alternate Function Selection
GPIO Exported Constants

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01U) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_FMPI2C1 ((uint8_t)0x04U) /* FMPI2C1 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
#define | GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI2 ((uint8_t)0x06U) /* I2S2 Alternate Function mapping */
#define | GPIO_AF6_SPI5 ((uint8_t)0x06U) /* SPI5/I2S5 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
#define | GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF9_I2C2 ((uint8_t)0x09U) /* I2C2 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_FMPI2C1 ((uint8_t)0x09U) /* FMPI2C1 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
AF 15 selection.

Define Documentation

#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */

Definition at line 690 of file stm32f4xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */

AF 0 selection.

Definition at line 689 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */

Definition at line 692 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */

Definition at line 691 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */

Definition at line 693 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */

AF 15 selection.

Definition at line 755 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF1_LPTIM1 ((uint8_t)0x01U) /* LPTIM1 Alternate Function mapping */

Definition at line 699 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */

AF 1 selection.

Definition at line 698 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */

AF 2 selection.

Definition at line 704 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */

Definition at line 710 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */

AF 3 selection.

Definition at line 709 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04U) /* FMPI2C1 Alternate Function mapping */

Definition at line 717 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */

AF 4 selection.

Definition at line 715 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */

Definition at line 716 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */

AF 5 selection.

Definition at line 722 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */

Definition at line 724 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1 Alternate Function mapping */

AF 6 selection.

Definition at line 730 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* I2S2 Alternate Function mapping */

Definition at line 732 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI5 ((uint8_t)0x06U) /* SPI5/I2S5 Alternate Function mapping */

Definition at line 734 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */

AF 7 selection.

Definition at line 738 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */

Definition at line 739 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */

AF 8 selection.

Definition at line 744 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09U) /* FMPI2C1 Alternate Function mapping */

Definition at line 750 of file stm32f4xx_hal_gpio_ex.h.

#define GPIO_AF9_I2C2 ((uint8_t)0x09U) /* I2C2 Alternate Function mapping */

AF 9 selection.

Definition at line 749 of file stm32f4xx_hal_gpio_ex.h.

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STM32F410Rx HAL User Manual: GPIO Exported Macros

GPIO Exported Macros
GPIOEx
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO Exported Functions

GPIO Exported Functions
GPIOEx
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: GPIO Private Constants

GPIO Private Constants
GPIOEx
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STM32F410Rx HAL User Manual: GPIO Get Port Index

Defines
GPIO Get Port Index
GPIO Private Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
                                               ((__GPIOx__) == (GPIOB))? 1U :\
                                               ((__GPIOx__) == (GPIOC))? 2U :\
                                               ((__GPIOx__) == (GPIOH))? 7U : 8U)

Definition at line 1069 of file stm32f4xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

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STM32F410Rx HAL User Manual: GPIO Check Alternate Function

Defines
GPIO Check Alternate Function
GPIO Private Macros

Defines

#define IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U))

Define Documentation

#define IS_GPIO_AF ( AF ) (((AF) < 10U) || ((AF) == 15U))

Definition at line 1223 of file stm32f4xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

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STM32F410Rx HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIOEx
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STM32F410Rx HAL User Manual: HASH

HASH
STM32F4xx_HAL_Driver

HASH HAL module driver. More...

HASH HAL module driver.

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STM32F410Rx HAL User Manual: HASHEx

HASHEx
STM32F4xx_HAL_Driver

HASH Extension HAL module driver. More...

HASH Extension HAL module driver.

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STM32F410Rx HAL User Manual: HCD

HCD
STM32F4xx_HAL_Driver

HCD HAL module driver. More...

HCD HAL module driver.

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STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Communication Speed
        (++) Duty cycle
        (++) Addressing mode
        (++) Own Address 1
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitializes the I2C peripheral.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 424 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 342 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::ClockSpeed, I2C_InitTypeDef::DualAddressMode, I2C_InitTypeDef::DutyCycle, I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, HAL_RCC_GetPCLK1Freq(), I2C_FREQRANGE, I2C_RISE_TIME, I2C_SPEED, I2C_STATE_NONE, I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_CLOCK_SPEED, IS_I2C_DUAL_ADDRESS, IS_I2C_DUTY_CYCLE, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, I2C_HandleTypeDef::Lock, I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

I2C MSP DeInit.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 475 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

I2C MSP Init.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 460 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callbacks.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callbacks.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callbacks.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callbacks.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_ErrorCallback()

Function Documentation

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection | Master request Transfer Direction (Write/Read), value of I2C XferOptions definition
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 3451 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_Slave_ADDR().

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 1818 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_IT_ERR, I2C_IT_EVT, I2C_STATE_MSK, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 1792 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_IT_ERR, I2C_IT_EVT, I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3286 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __HAL_I2C_GET_IT_SOURCE, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, HAL_I2C_ErrorCallback(), HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERR, I2C_NO_OPTION_FRAME, I2C_Slave_AF(), I2C_STATE_NONE, I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callbacks.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 3513 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), and I2C_DMASlaveTransmitCplt().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3180 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __HAL_I2C_GET_IT_SOURCE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_MEM, I2C_FLAG_ADDR, I2C_FLAG_BTF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TRA, I2C_FLAG_TXE, I2C_IT_BUF, I2C_IT_EVT, I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_ADDR(), I2C_Slave_STOPF(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), I2C_SlaveTransmit_TXE(), and I2C_HandleTypeDef::Mode.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3067 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_TIMEOUT, I2C_7BIT_ADD_WRITE, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3468 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Slave_AF(), and I2C_Slave_STOPF().

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
Return values:
HAL status

Definition at line 2084 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_READY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 669 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_MasterRequestRead(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1967 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_FLAG_BUSY, I2C_MasterRequestRead(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1192 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_MasterRequestRead(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master mode an amount of data in no-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1411 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_MasterRequestRead(), I2C_NEXT_FRAME, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master mode an amount of data in no-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1309 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_BUSY, I2C_FLAG_TXE, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_MasterRequestWrite(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 557 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_MasterRequestWrite(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1854 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_FLAG_BUSY, I2C_FLAG_TXE, I2C_MasterRequestWrite(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1102 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_FLAG_TXE, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_MasterRequestWrite(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callbacks.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 3405 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_DMAMasterReceiveCplt(), I2C_MasterReceive_BTF(), and I2C_MasterReceive_RXNE().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callbacks.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 3390 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_DMAMasterTransmitCplt(), and I2C_MasterTransmit_BTF().

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2413 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_RequestMemoryRead(), I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in no-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 2944 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMAMemReceiveCplt(), I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_RequestMemoryRead(), I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in no-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2712 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_RequestMemoryRead(), I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2299 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_RequestMemoryWrite(), I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in no-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2831 of file stm32f4xx_hal_i2c.c.

References assert_param, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMAMemTransmitCplt(), I2C_FLAG_BUSY, I2C_FLAG_TXE, I2C_NO_OPTION_FRAME, I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in no-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2620 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_FLAG_TXE, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_RequestMemoryWrite(), I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callbacks.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 3498 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_DMAMemReceiveCplt(), I2C_MasterReceive_BTF(), and I2C_MasterReceive_RXNE().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callbacks.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 3483 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_DMAMemTransmitCplt(), and I2C_MasterTransmit_BTF().

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 990 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_CLEAR_STOPFLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2223 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_ADDR_SLAVE, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1619 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave mode an amount of data in no-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1738 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1680 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 875 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in no-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2132 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_ADDRESSINGMODE_7BIT, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_ADDR_SLAVE, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in no-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1560 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callbacks.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 3434 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_Slave_STOPF(), and I2C_SlaveReceive_RXNE().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callbacks.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 3419 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_DMASlaveTransmitCplt(), I2C_Slave_AF(), and I2C_SlaveTransmit_TXE().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2C Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Returns the I2C state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State, Mode and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 3569 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 3558 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Returns the I2C state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL state

Definition at line 3547 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Exported Functions

Modules | Functions
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

static HAL_StatusTypeDef | I2C_MasterTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Master.
static HAL_StatusTypeDef | I2C_MasterTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master transmitter.
static HAL_StatusTypeDef | I2C_MasterReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Master.
static HAL_StatusTypeDef | I2C_MasterReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master receiver.
static HAL_StatusTypeDef | I2C_SlaveTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave transmitter.
static HAL_StatusTypeDef | I2C_SlaveReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave receiver.
static HAL_StatusTypeDef | I2C_Slave_ADDR (I2C_HandleTypeDef *hi2c)
Handle ADD flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_STOPF (I2C_HandleTypeDef *hi2c)
Handle STOPF flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_AF (I2C_HandleTypeDef *hi2c)
static HAL_StatusTypeDef | I2C_MasterRequestWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
static HAL_StatusTypeDef | I2C_MasterRequestRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
Master sends target device address for read request.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for read request.
static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAMemTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Write process complete callback.
static void | I2C_DMAMemReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Read process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnMasterAddressFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
This function handles I2C Communication Timeout for Master addressing phase.
static HAL_StatusTypeDef | I2C_WaitOnTXEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of TXE flag.
static HAL_StatusTypeDef | I2C_WaitOnBTFFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of BTF flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c)
This function handles Acknowledge failed detection during an I2C Communication.

Function Documentation

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4705 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_DMA, HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4547 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Master_Receive_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4470 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Master_Transmit_DMA().

static void I2C_DMAMemReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C Memory Read process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4668 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMemTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C Memory Write process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4631 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4584 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_STOPFLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_STATE_READY, I2C_TIMEOUT_FLAG, I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Slave_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4507 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_TIMEOUT_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed ( I2C_HandleTypeDef * hi2c ) [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 4998 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

static HAL_StatusTypeDef I2C_MasterReceive_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Master receiver.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3745 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MSK, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterReceive_RXNE ( I2C_HandleTypeDef * hi2c ) [static]

Handle RXNE flag for Master.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3667 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NEXT_FRAME, I2C_STATE_MSK, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterRequestRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Timeout
 | ) |  | [static]

Master sends target device address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4147 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_10BIT_ADDRESS, I2C_10BIT_HEADER_READ, I2C_10BIT_HEADER_WRITE, I2C_7BIT_ADD_READ, I2C_ADDRESSINGMODE_7BIT, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADD10, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_TX, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), and HAL_I2C_Master_Sequential_Receive_IT().

static HAL_StatusTypeDef I2C_MasterRequestWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Timeout
 | ) |  | [static]
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4075 of file stm32f4xx_hal_i2c.c.

References I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_10BIT_ADDRESS, I2C_10BIT_HEADER_WRITE, I2C_7BIT_ADD_WRITE, I2C_ADDRESSINGMODE_7BIT, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADD10, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_RX, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Master_Transmit_IT().

static HAL_StatusTypeDef I2C_MasterTransmit_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Master transmitter.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3607 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_MSK, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterTransmit_TXE ( I2C_HandleTypeDef * hi2c ) [static]

Handle TXE flag for Master.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3584 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, I2C_IT_BUF, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4343 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_7BIT_ADD_READ, I2C_7BIT_ADD_WRITE, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), and I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_DMA().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4254 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_7BIT_ADD_WRITE, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), and I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_Slave_ADDR ( I2C_HandleTypeDef * hi2c ) [static]

Handle ADD flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3939 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_I2C_AddrCallback(), I2C_DIRECTION_RECEIVE, I2C_DIRECTION_TRANSMIT, I2C_FLAG_DUALF, I2C_FLAG_TRA, I2C_HandleTypeDef::Init, I2C_InitTypeDef::OwnAddress1, and I2C_InitTypeDef::OwnAddress2.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_Slave_AF ( I2C_HandleTypeDef * hi2c ) [static]
Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4013 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_FLAG_AF, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_MSK, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler().

static HAL_StatusTypeDef I2C_Slave_STOPF ( I2C_HandleTypeDef * hi2c ) [static]

Handle STOPF flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3971 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_STOPFLAG, __HAL_I2C_DISABLE_IT, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_STATE_SLAVE_BUSY_RX, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveReceive_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Slave receiver.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3922 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveReceive_RXNE ( I2C_HandleTypeDef * hi2c ) [static]

Handle RXNE flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3888 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_STATE_MSK, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveTransmit_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Slave transmitter.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3871 of file stm32f4xx_hal_i2c.c.

References I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveTransmit_TXE ( I2C_HandleTypeDef * hi2c ) [static]

Handle TXE flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3837 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_STATE_MSK, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of BTF flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4880 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_IsAcknowledgeFailed(), I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Flag | specifies the I2C flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4731 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_GetTick(), HAL_I2C_STATE_READY, I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for Master addressing phase.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Flag | specifies the I2C flag to check.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4790 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4954 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Mem_Read(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4918 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Slave_Receive(), and I2C_DMASlaveReceiveCplt().

static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Return values:
HAL status

Definition at line 4842 of file stm32f4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_TXE, I2C_IsAcknowledgeFailed(), I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Exported Types

Data Structures | Enumerations
I2C Exported Types
I2C

Data Structures

struct | I2C_InitTypeDef
I2C Configuration Structure definition. More...
struct | I2C_HandleTypeDef
I2C handle Structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
HAL State structures definition. More...
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef

HAL State structures definition.

Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 116 of file stm32f4xx_hal_i2c.h.

enum HAL_I2C_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 96 of file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Exported Types

I2C Configuration Structure definition. More...

#include <stm32f4xx_hal_i2c.h>

Data Fields

uint32_t | ClockSpeed
uint32_t | DutyCycle
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

I2C Configuration Structure definition.

Definition at line 65 of file stm32f4xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C addressing mode

Definition at line 76 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

uint32_t I2C_InitTypeDef::ClockSpeed

Specifies the clock frequency. This parameter must be set to a value lower than 400kHz

Definition at line 67 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C dual addressing mode

Definition at line 79 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::DutyCycle

Specifies the I2C fast mode duty cycle. This parameter can be a value of I2C duty cycle in fast mode

Definition at line 70 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C general call addressing mode

Definition at line 85 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C nostretch mode

Definition at line 88 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 73 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), and I2C_Slave_ADDR().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 82 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), and I2C_Slave_ADDR().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_i2c.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_HandleTypeDef Struct Reference
I2C Exported Types

I2C handle Structure definition. More...

#include <stm32f4xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode

Detailed Description

I2C handle Structure definition.

Definition at line 128 of file stm32f4xx_hal_i2c.h.

Field Documentation

__IO uint32_t I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 155 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

DMA_HandleTypeDef* I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 147 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Slave_Receive_DMA().

DMA_HandleTypeDef* I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 145 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Slave_Transmit_DMA().

I2C_InitTypeDef I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 132 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), and I2C_Slave_ADDR().

I2C_TypeDef* I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 130 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), I2C_SlaveTransmit_TXE(), and I2C_WaitOnMasterAddressFlagUntilTimeout().

HAL_LockTypeDef I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 149 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

__IO HAL_I2C_ModeTypeDef I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 153 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), and I2C_SlaveTransmit_TXE().

uint8_t* I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 134 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), and I2C_SlaveTransmit_TXE().

__IO uint32_t I2C_HandleTypeDef::PreviousState

I2C communication Previous state and mode context for internal usage

Definition at line 142 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_TXE(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

__IO HAL_I2C_StateTypeDef I2C_HandleTypeDef::State

I2C communication state

Definition at line 151 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_TXE(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

__IO uint16_t I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 138 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), and I2C_SlaveTransmit_TXE().

__IO uint32_t I2C_HandleTypeDef::XferOptions

I2C transfer options

Definition at line 140 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), and I2C_Slave_STOPF().

uint16_t I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 136 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_i2c.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Error Code

Defines
I2C Error Code
I2C Exported Constants

I2C Error Code. More...

Defines

#define | HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U)
#define | HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U)
#define | HAL_I2C_ERROR_AF ((uint32_t)0x00000004U)
#define | HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U)
#define | HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Detailed Description

I2C Error Code.

Define Documentation

#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U)

AF error

Definition at line 175 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_DMASlaveReceiveCplt(), I2C_IsAcknowledgeFailed(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), and I2C_WaitOnMasterAddressFlagUntilTimeout().

#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U)

ARLO error

Definition at line 174 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U)

BERR error

Definition at line 173 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 177 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_DMAError().

#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 172 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemReceiveCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U)

OVR error

Definition at line 176 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U)

Timeout Error

Definition at line 178 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C duty cycle in fast mode

Defines
I2C duty cycle in fast mode
I2C Exported Constants

Defines

#define | I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
#define | I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY

Define Documentation

#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY

Definition at line 187 of file stm32f4xx_hal_i2c.h.

#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)

Definition at line 186 of file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C addressing mode

Defines
I2C addressing mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
#define | I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))

Definition at line 196 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Transmit().

#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)

Definition at line 195 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Transmit_DMA(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C dual addressing mode

Defines
I2C dual addressing mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL

Define Documentation

#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)

Definition at line 204 of file stm32f4xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL

Definition at line 205 of file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C general call addressing mode

Defines
I2C general call addressing mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_ENGC

Define Documentation

#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)

Definition at line 213 of file stm32f4xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC

Definition at line 214 of file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C nostretch mode

Defines
I2C nostretch mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)

Definition at line 222 of file stm32f4xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 223 of file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)

Definition at line 232 of file stm32f4xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)

Definition at line 231 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C XferDirection definition

Defines
I2C XferDirection definition
I2C Exported Constants

Defines

#define | I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
#define | I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)

Definition at line 240 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_Slave_ADDR().

#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)

Definition at line 241 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_Slave_ADDR().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C XferOptions definition

Defines
I2C XferOptions definition
I2C Exported Constants

Defines

#define | I2C_FIRST_FRAME ((uint32_t)0x00000001U)
#define | I2C_NEXT_FRAME ((uint32_t)0x00000002U)
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
#define | I2C_LAST_FRAME ((uint32_t)0x00000008U)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)

Definition at line 251 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_MasterReceive_BTF(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), and I2C_Slave_AF().

#define I2C_FIRST_FRAME ((uint32_t)0x00000001U)

Definition at line 249 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_LAST_FRAME ((uint32_t)0x00000008U)

Definition at line 252 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), I2C_MasterReceive_BTF(), I2C_MasterTransmit_BTF(), and I2C_Slave_AF().

#define I2C_NEXT_FRAME ((uint32_t)0x00000002U)

Definition at line 250 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), I2C_MasterReceive_BTF(), and I2C_MasterReceive_RXNE().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

Defines

#define | I2C_IT_BUF I2C_CR2_ITBUFEN
#define | I2C_IT_EVT I2C_CR2_ITEVTEN
#define | I2C_IT_ERR I2C_CR2_ITERREN

Define Documentation

#define I2C_IT_BUF I2C_CR2_ITBUFEN

Definition at line 260 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), and I2C_SlaveTransmit_TXE().

#define I2C_IT_ERR I2C_CR2_ITERREN

Definition at line 262 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), and I2C_Slave_STOPF().

#define I2C_IT_EVT I2C_CR2_ITEVTEN

Definition at line 261 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), and I2C_Slave_STOPF().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)
#define | I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)
#define | I2C_FLAG_PECERR ((uint32_t)0x00011000U)
#define | I2C_FLAG_OVR ((uint32_t)0x00010800U)
#define | I2C_FLAG_AF ((uint32_t)0x00010400U)
#define | I2C_FLAG_ARLO ((uint32_t)0x00010200U)
#define | I2C_FLAG_BERR ((uint32_t)0x00010100U)
#define | I2C_FLAG_TXE ((uint32_t)0x00010080U)
#define | I2C_FLAG_RXNE ((uint32_t)0x00010040U)
#define | I2C_FLAG_STOPF ((uint32_t)0x00010010U)
#define | I2C_FLAG_ADD10 ((uint32_t)0x00010008U)
#define | I2C_FLAG_BTF ((uint32_t)0x00010004U)
#define | I2C_FLAG_ADDR ((uint32_t)0x00010002U)
#define | I2C_FLAG_SB ((uint32_t)0x00010001U)
#define | I2C_FLAG_DUALF ((uint32_t)0x00100080U)
#define | I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)
#define | I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)
#define | I2C_FLAG_GENCALL ((uint32_t)0x00100010U)
#define | I2C_FLAG_TRA ((uint32_t)0x00100004U)
#define | I2C_FLAG_BUSY ((uint32_t)0x00100002U)
#define | I2C_FLAG_MSL ((uint32_t)0x00100001U)

Define Documentation

#define I2C_FLAG_ADD10 ((uint32_t)0x00010008U)

Definition at line 280 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_FLAG_ADDR ((uint32_t)0x00010002U)

Definition at line 282 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_AF ((uint32_t)0x00010400U)

Definition at line 274 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_Slave_AF(), and I2C_WaitOnMasterAddressFlagUntilTimeout().

#define I2C_FLAG_ARLO ((uint32_t)0x00010200U)

Definition at line 275 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR ((uint32_t)0x00010100U)

Definition at line 276 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BTF ((uint32_t)0x00010004U)

Definition at line 281 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemTransmitCplt(), and I2C_WaitOnBTFFlagUntilTimeout().

#define I2C_FLAG_BUSY ((uint32_t)0x00100002U)

Definition at line 289 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

#define I2C_FLAG_DUALF ((uint32_t)0x00100080U)

Definition at line 284 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_Slave_ADDR().

#define I2C_FLAG_GENCALL ((uint32_t)0x00100010U)

Definition at line 287 of file stm32f4xx_hal_i2c.h.

#define I2C_FLAG_MSL ((uint32_t)0x00100001U)

Definition at line 290 of file stm32f4xx_hal_i2c.h.

#define I2C_FLAG_OVR ((uint32_t)0x00010800U)

Definition at line 273 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR ((uint32_t)0x00011000U)

Definition at line 272 of file stm32f4xx_hal_i2c.h.

#define I2C_FLAG_RXNE ((uint32_t)0x00010040U)

Definition at line 278 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_SB ((uint32_t)0x00010001U)

Definition at line 283 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)

Definition at line 270 of file stm32f4xx_hal_i2c.h.

#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)

Definition at line 286 of file stm32f4xx_hal_i2c.h.

#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)

Definition at line 285 of file stm32f4xx_hal_i2c.h.

#define I2C_FLAG_STOPF ((uint32_t)0x00010010U)

Definition at line 279 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)

Definition at line 271 of file stm32f4xx_hal_i2c.h.

#define I2C_FLAG_TRA ((uint32_t)0x00100004U)

Definition at line 288 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), and I2C_Slave_ADDR().

#define I2C_FLAG_TXE ((uint32_t)0x00010080U)

Definition at line 277 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), and I2C_WaitOnTXEFlagUntilTimeout().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2C interrupts.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2C interrupt source is enabled or disabled.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
Checks whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
#define | __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)
Clears the I2C ADDR pending flag.
#define | __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)
Clears the I2C STOPF pending flag.
#define | __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
Enable the I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
Disable the I2C peripheral.

Define Documentation

#define __HAL_I2C_CLEAR_ADDRFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR1;       \
    tmpreg = (__HANDLE__)->Instance->SR2;       \
    UNUSED(tmpreg);                             \
  } while(0)

Clears the I2C ADDR pending flag.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
Return values:
None

Definition at line 389 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), I2C_MasterRequestRead(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))

Clears the I2C pending flags which are cleared by writing 0 in a specific bit.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
Return values:
None

Definition at line 382 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), I2C_DMASlaveTransmitCplt(), I2C_IsAcknowledgeFailed(), I2C_Slave_AF(), I2C_WaitOnMasterAddressFlagUntilTimeout(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_CLEAR_STOPFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR1;       \
    (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;  \
    UNUSED(tmpreg);                             \
  } while(0)

Clears the I2C STOPF pending flag.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
Return values:
None

Definition at line 402 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), I2C_DMASlaveReceiveCplt(), and I2C_Slave_STOPF().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)

Disable the I2C peripheral.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 422 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), and HAL_I2C_Init().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))

Definition at line 322 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), and I2C_SlaveTransmit_TXE().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)

Enable the I2C peripheral.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 415 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable or disable the specified I2C interrupts.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2C_IT_BUF: Buffer interrupt enable
  • I2C_IT_EVT: Event interrupt enable
  • I2C_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 321 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), and HAL_I2C_Slave_Transmit_IT().

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))

Checks whether the specified I2C flag is set or not.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag
  • I2C_FLAG_BERR: Bus error flag
  • I2C_FLAG_TXE: Data register empty flag
  • I2C_FLAG_RXNE: Data register not empty flag
  • I2C_FLAG_STOPF: Stop detection flag
  • I2C_FLAG_ADD10: 10-bit header sent flag
  • I2C_FLAG_BTF: Byte transfer finished flag
  • I2C_FLAG_ADDR: Address sent flag Address matched flag
  • I2C_FLAG_SB: Start bit flag
  • I2C_FLAG_DUALF: Dual flag
  • I2C_FLAG_SMBHOST: SMBus host header
  • I2C_FLAG_SMBDEFAULT: SMBus default header
  • I2C_FLAG_GENCALL: General call header flag
  • I2C_FLAG_TRA: Transmitter/Receiver flag
  • I2C_FLAG_BUSY: Bus busy flag
  • I2C_FLAG_MSL: Master/Slave flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 365 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_Slave_ADDR(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2C interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__INTERRUPT__,: specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_BUF: Buffer interrupt enable
  • I2C_IT_EVT: Event interrupt enable
  • I2C_IT_ERR: Error interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 334 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), and HAL_I2C_EV_IRQHandler().

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

Reset I2C handle state.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
Return values:
None

Definition at line 309 of file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Private Constants

Defines
I2C Private Constants
I2C

Defines

#define | I2C_TIMEOUT_FLAG ((uint32_t)35U)
#define | I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000U)
#define | I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000U)
#define | I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)

Define Documentation

#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)

Definition at line 522 of file stm32f4xx_hal_i2c.h.

#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)

XferOptions default value

Definition at line 243 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_BTF(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), and I2C_Slave_STOPF().

#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 249 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_MasterReceive_BTF(), and I2C_MasterRequestWrite().

#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 248 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), and I2C_MasterRequestRead().

#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY)))

Mask State define, keep only RX and TX bits

Definition at line 246 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), I2C_SlaveReceive_RXNE(), and I2C_SlaveTransmit_TXE().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 247 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_MasterTransmit_BTF(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 251 of file stm32f4xx_hal_i2c.c.

Referenced by I2C_Slave_STOPF().

#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 250 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000U)

Timeout 10 s

Definition at line 241 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000U)

Timeout 10 s

Definition at line 242 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

#define I2C_TIMEOUT_FLAG ((uint32_t)35U)

Timeout 35 ms

Definition at line 240 of file stm32f4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), I2C_DMAMasterTransmitCplt(), I2C_DMAMemTransmitCplt(), I2C_DMASlaveReceiveCplt(), and I2C_DMASlaveTransmitCplt().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Private macros to check input parameters

Defines
I2C Private macros to check input parameters
I2C Private Macros

Defines

#define | IS_I2C_DUTY_CYCLE(CYCLE)
#define | IS_I2C_ADDRESSING_MODE(ADDRESS)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)

Define Documentation

#define IS_I2C_ADDRESSING_MODE ( ADDRESS )
Value:
(((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 555 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_CLOCK_SPEED ( SPEED ) (((SPEED) > 0) && ((SPEED) <= 400000U))

Definition at line 565 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 557 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUTY_CYCLE ( CYCLE )
Value:
(((CYCLE) == I2C_DUTYCYCLE_2) || \
                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))

Definition at line 553 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                   ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 559 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 563 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 561 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)

Definition at line 566 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)

Definition at line 567 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)              || \
                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
                                                       ((REQUEST) == I2C_LAST_FRAME))

Definition at line 568 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), and HAL_I2C_Slave_Sequential_Transmit_IT().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Private Macros

Modules | Defines
I2C Private Macros
I2C

Modules

I2C Private macros to check input parameters

Defines

#define | I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
#define | I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
#define | I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
#define | I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
#define | I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)
#define | I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define | I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define | I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
#define | I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Define Documentation

#define I2C_10BIT_ADDRESS ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 543 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_10BIT_HEADER_READ ( __ADDRESS__ ) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))

Definition at line 545 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_MasterRequestRead().

#define I2C_10BIT_HEADER_WRITE ( __ADDRESS__ ) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))

Definition at line 544 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_7BIT_ADD_READ ( __ADDRESS__ ) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))

Definition at line 541 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_MasterRequestRead(), and I2C_RequestMemoryRead().

#define I2C_7BIT_ADD_WRITE ( __ADDRESS__ ) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))

Definition at line 540 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_FREQRANGE ( __PCLK__ ) ((__PCLK__)/1000000U)

Definition at line 532 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 548 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 547 of file stm32f4xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RISE_TIME | ( | __FREQRANGE__,
 |  | __SPEED__
 | ) | (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))

Definition at line 533 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define I2C_SPEED | ( | __PCLK__,
 |  | __SPEED__,
 |  | __DUTYCYCLE__
 | ) |
Value:
(((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))

Definition at line 536 of file stm32f4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define I2C_SPEED_FAST | ( | __PCLK__,
 |  | __SPEED__,
 |  | __DUTYCYCLE__
 | ) | (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))

Definition at line 535 of file stm32f4xx_hal_i2c.h.

#define I2C_SPEED_STANDARD | ( | __PCLK__,
 |  | __SPEED__
 | ) | (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))

Definition at line 534 of file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2C Private Functions

I2C Private Functions
I2C
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2CEx

I2CEx
STM32F4xx_HAL_Driver

I2C HAL module driver. More...

I2C HAL module driver.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Initialization and Configuration functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Sx peripheral in simplex mode:

      (+) User must Implement HAL_I2S_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2S_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Standard
        (++) Data Format
        (++) MCLK Output
        (++) Audio frequency
        (++) Polarity

      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
          of the selected I2Sx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2S_DeInit ( I2S_HandleTypeDef * hi2s )

DeInitializes the I2S peripheral.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 330 of file stm32f4xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspDeInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_RESET, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Init ( I2S_HandleTypeDef * hi2s )

Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 206 of file stm32f4xx_hal_i2s.c.

References assert_param, I2S_InitTypeDef::AudioFreq, I2S_InitTypeDef::ClockSource, I2S_InitTypeDef::CPOL, I2S_InitTypeDef::DataFormat, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_MspInit(), HAL_I2S_STATE_BUSY, HAL_I2S_STATE_READY, HAL_I2S_STATE_RESET, I2S_AUDIOFREQ_DEFAULT, I2S_DATAFORMAT_16B, I2S_GetInputClock(), I2S_MCLKOUTPUT_ENABLE, I2S_STANDARD_PCM_SHORT, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, IS_I2S_AUDIO_FREQ, IS_I2S_CLOCKSOURCE, IS_I2S_CPOL, IS_I2S_DATA_FORMAT, IS_I2S_MCLK_OUTPUT, IS_I2S_MODE, IS_I2S_STANDARD, I2S_HandleTypeDef::Lock, I2S_InitTypeDef::MCLKOutput, I2S_InitTypeDef::Mode, I2S_InitTypeDef::Standard, and I2S_HandleTypeDef::State.

void HAL_I2S_MspDeInit ( I2S_HandleTypeDef * hi2s )

I2S MSP DeInit.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 373 of file stm32f4xx_hal_i2s.c.

Referenced by HAL_I2S_DeInit().

void HAL_I2S_MspInit ( I2S_HandleTypeDef * hi2s )

I2S MSP Init.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 358 of file stm32f4xx_hal_i2s.c.

Referenced by HAL_I2S_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
I2S Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
__weak HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_Transmit()
        (++) HAL_I2S_Receive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_Transmit_IT()
        (++) HAL_I2S_Receive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_Transmit_DMA()
        (++) HAL_I2S_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2S_DMAPause ( I2S_HandleTypeDef * hi2s )

Pauses the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 901 of file stm32f4xx_hal_i2s.c.

References HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_BUSY_TX_RX, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_TX, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, I2S_InitTypeDef::Mode, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAResume ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 942 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_BUSY_TX_RX, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_TX, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, I2S_InitTypeDef::Mode, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_DMAStop ( I2S_HandleTypeDef * hi2s )

Resumes the audio stream playing from the Media.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 990 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_DISABLE, HAL_DMA_Abort(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmarx, I2S_HandleTypeDef::hdmatx, I2S_HandleTypeDef::Instance, and I2S_HandleTypeDef::State.

void HAL_I2S_ErrorCallback ( I2S_HandleTypeDef * hi2s )

I2S error callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1146 of file stm32f4xx_hal_i2s.c.

Referenced by HAL_I2S_IRQHandler(), and I2S_DMAError().

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1190 of file stm32f4xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1179 of file stm32f4xx_hal_i2s.c.

References I2S_HandleTypeDef::State.

void HAL_I2S_IRQHandler ( I2S_HandleTypeDef * hi2s )

This function handles I2S interrupt request.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1027 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_CLEAR_UDRFLAG, __HAL_I2S_GET_FLAG, __HAL_I2S_GET_IT_SOURCE, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_ERROR_OVR, HAL_I2S_ERROR_UDR, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_FLAG_OVR, I2S_FLAG_RXNE, I2S_FLAG_TXE, I2S_FLAG_UDR, I2S_IT_ERR, I2S_IT_RXNE, I2S_IT_TXE, I2S_Receive_IT(), I2S_Transmit_IT(), and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout,: Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate in continuous way and as the I2S is not disabled at the end of the I2S transaction.
Return values:
HAL status

Definition at line 525 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_RXNE, I2S_MODE_MASTER_RX, I2S_WaitFlagStateUntilTimeout(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, and I2S_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2S_Receive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Receive data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 819 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_ENABLE, I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmarx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMARxCplt(), I2S_DMARxHalfCplt(), I2S_MODE_MASTER_RX, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, I2S_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Receive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Receive data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
It is recommended to use DMA for the I2S receiver to avoid de-synchronisation between Master and Slave otherwise the I2S interrupt should be optimized.
Return values:
HAL status

Definition at line 672 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_RXNE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::RxXferSize, and I2S_HandleTypeDef::State.

void HAL_I2S_RxCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1131 of file stm32f4xx_hal_i2s.c.

Referenced by I2S_DMARxCplt(), and I2S_Receive_IT().

void HAL_I2S_RxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Rx Transfer half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1116 of file stm32f4xx_hal_i2s.c.

Referenced by I2S_DMARxHalfCplt().

HAL_StatusTypeDef HAL_I2S_Transmit | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
Parameters:
Timeout,: Timeout duration
Note:
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 442 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_FLAG_BSY, I2S_FLAG_TXE, I2S_MODE_SLAVE_RX, I2S_MODE_SLAVE_TX, I2S_WaitFlagStateUntilTimeout(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, and I2S_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_I2S_Transmit_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to the Transmit data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 736 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, I2S_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_HandleTypeDef::hdmatx, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_DMAError(), I2S_DMATxCplt(), I2S_DMATxHalfCplt(), I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, I2S_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_I2S_Transmit_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
pData,: a 16-bit pointer to data buffer.
Size,: number of data sample to be sent:
Note:
When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S configuration phase, the Size parameter means the number of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data frame is selected the Size parameter means the number of 16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization between Master and Slave(example: audio streaming).
Return values:
HAL status

Definition at line 606 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_ENABLE, __HAL_I2S_ENABLE_IT, I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_NONE, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, I2S_DATAFORMAT_24B, I2S_DATAFORMAT_32B, I2S_IT_ERR, I2S_IT_TXE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, I2S_HandleTypeDef::TxXferCount, and I2S_HandleTypeDef::TxXferSize.

void HAL_I2S_TxCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1101 of file stm32f4xx_hal_i2s.c.

Referenced by I2S_DMATxCplt(), and I2S_Transmit_IT().

void HAL_I2S_TxHalfCpltCallback ( I2S_HandleTypeDef * hi2s )

Tx Transfer Half completed callbacks.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
None

Definition at line 1086 of file stm32f4xx_hal_i2s.c.

Referenced by I2S_DMATxHalfCplt().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
I2S Exported Functions

Peripheral State functions. More...

Functions

HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2S_GetError ( I2S_HandleTypeDef * hi2s )

Return the I2S error code.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Error Code

Definition at line 1190 of file stm32f4xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode.

HAL_I2S_StateTypeDef HAL_I2S_GetState ( I2S_HandleTypeDef * hi2s )

Return the I2S state.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL state

Definition at line 1179 of file stm32f4xx_hal_i2s.c.

References I2S_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Exported Functions

Modules | Functions
I2S Exported Functions
I2S

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

Peripheral State functions.

Functions

void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
HAL_StatusTypeDef | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
This function handles I2S Communication Timeout.

Function Documentation

void I2S_DMAError ( DMA_HandleTypeDef * hdma )

DMA I2S communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1230 of file stm32f4xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma )

DMA I2S receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1217 of file stm32f4xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback().

Referenced by HAL_I2S_Receive_DMA().

void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma )

DMA I2S transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1204 of file stm32f4xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback().

Referenced by HAL_I2S_Transmit_DMA().

HAL_StatusTypeDef I2S_Receive_IT ( I2S_HandleTypeDef * hi2s )

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1293 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXNE, I2S_MODE_MASTER_RX, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_IRQHandler().

HAL_StatusTypeDef I2S_Transmit_IT ( I2S_HandleTypeDef * hi2s )

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1249 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_IRQHandler().

HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | uint32_t | Status,
 |  | uint32_t | Timeout
 | ) |  |

This function handles I2S Communication Timeout.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag,: Flag checked
Status,: Value of the flag expected
Timeout,: Duration of the timeout
Return values:
HAL status

Definition at line 1348 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Transmit().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Exported Types

Data Structures | Enumerations
I2S Exported Types
I2S

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | I2S_HandleTypeDef
I2S handle Structure definition. More...

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x12U,
HAL_I2S_STATE_BUSY_RX = 0x22U, HAL_I2S_STATE_BUSY_TX_RX = 0x32U, HAL_I2S_STATE_TIMEOUT = 0x03U, HAL_I2S_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_I2S_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_I2S_STATE_RESET

I2S not yet initialized or disabled

HAL_I2S_STATE_READY

I2S initialized and ready for use

HAL_I2S_STATE_BUSY

I2S internal process is ongoing

HAL_I2S_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2S_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2S_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_I2S_STATE_TIMEOUT

I2S timeout state

HAL_I2S_STATE_ERROR

I2S error state

Definition at line 96 of file stm32f4xx_hal_i2s.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_InitTypeDef Struct Reference
I2S Exported Types

I2S Init structure definition. More...

#include <stm32f4xx_hal_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | CPOL
uint32_t | ClockSource
uint32_t | FullDuplexMode

Detailed Description

I2S Init structure definition.

Definition at line 65 of file stm32f4xx_hal_i2s.h.

Field Documentation

uint32_t I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S Audio Frequency

Definition at line 79 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::ClockSource

Specifies the I2S Clock Source. This parameter can be a value of I2S Clock Source

Definition at line 85 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init(), and I2S_GetInputClock().

uint32_t I2S_InitTypeDef::CPOL

Specifies the idle state of the I2S clock. This parameter can be a value of I2S Clock Polarity

Definition at line 82 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of I2S Data Format

Definition at line 73 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::FullDuplexMode

Specifies the I2S FullDuplex mode. This parameter can be a value of I2S FullDuplex Mode

Definition at line 88 of file stm32f4xx_hal_i2s.h.

Referenced by I2S_DMARxCplt(), and I2S_DMATxCplt().

uint32_t I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S Mclk Output

Definition at line 76 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of I2S Mode

Definition at line 67 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), and HAL_I2S_Init().

uint32_t I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2S Standard

Definition at line 70 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_i2s.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2S_HandleTypeDef Struct Reference
I2S Exported Types

I2S handle Structure definition. More...

#include <stm32f4xx_hal_i2s.h>

Data Fields

SPI_TypeDef * | Instance
I2S_InitTypeDef Init
uint16_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint16_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
__IO HAL_LockTypeDef | Lock
__IO HAL_I2S_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

I2S handle Structure definition.

Definition at line 112 of file stm32f4xx_hal_i2s.h.

Field Documentation

__IO uint32_t I2S_HandleTypeDef::ErrorCode

Definition at line 138 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_GetError(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_DMAError().

DMA_HandleTypeDef* I2S_HandleTypeDef::hdmarx

Definition at line 132 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Receive_DMA().

DMA_HandleTypeDef* I2S_HandleTypeDef::hdmatx

Definition at line 130 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop(), and HAL_I2S_Transmit_DMA().

I2S_InitTypeDef I2S_HandleTypeDef::Init

Definition at line 116 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_Init(), I2S_DMARxCplt(), I2S_DMATxCplt(), and I2S_GetInputClock().

SPI_TypeDef* I2S_HandleTypeDef::Instance

Definition at line 114 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_Init(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), and I2S_Transmit_IT().

__IO HAL_LockTypeDef I2S_HandleTypeDef::Lock

Definition at line 134 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

uint16_t* I2S_HandleTypeDef::pRxBuffPtr

Definition at line 124 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

uint16_t* I2S_HandleTypeDef::pTxBuffPtr

Definition at line 118 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

__IO uint16_t I2S_HandleTypeDef::RxXferCount

Definition at line 128 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), and I2S_Receive_IT().

__IO uint16_t I2S_HandleTypeDef::RxXferSize

Definition at line 126 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and HAL_I2S_Receive_IT().

__IO HAL_I2S_StateTypeDef I2S_HandleTypeDef::State

Definition at line 136 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_DMAStop(), HAL_I2S_GetState(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), I2S_Receive_IT(), I2S_Transmit_IT(), and I2S_WaitFlagStateUntilTimeout().

__IO uint16_t I2S_HandleTypeDef::TxXferCount

Definition at line 122 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), HAL_I2S_Transmit_IT(), I2S_DMAError(), I2S_DMARxCplt(), I2S_DMATxCplt(), and I2S_Transmit_IT().

__IO uint16_t I2S_HandleTypeDef::TxXferSize

Definition at line 120 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_i2s.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Error Code

Defines
I2S Error Code
I2S Exported Constants

I2S Error Code. More...

Defines

#define | HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_I2S_ERROR_UDR ((uint32_t)0x00000001U)
#define | HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U)
#define | HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004U)
#define | HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008U)
#define | HAL_I2S_ERROR_FRE ((uint32_t)0x00000010U)
#define | HAL_I2S_ERROR_DMA ((uint32_t)0x00000020U)

Detailed Description

I2S Error Code.

Define Documentation

#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000020U)

DMA transfer error

Definition at line 160 of file stm32f4xx_hal_i2s.h.

Referenced by I2S_DMAError().

#define HAL_I2S_ERROR_FRE ((uint32_t)0x00000010U)

I2S Frame format error

Definition at line 159 of file stm32f4xx_hal_i2s.h.

#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 154 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DeInit(), HAL_I2S_Init(), HAL_I2S_IRQHandler(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U)

I2S Overrun error

Definition at line 156 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000001U)

I2S Underrun error

Definition at line 155 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008U)

I2S extended Overrun error

Definition at line 158 of file stm32f4xx_hal_i2s.h.

#define HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004U)

I2S extended Underrun error

Definition at line 157 of file stm32f4xx_hal_i2s.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Mode

Defines
I2S Mode
I2S Exported Constants

Defines

#define | I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
#define | I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
#define | I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
#define | I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)

Define Documentation

#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)

Definition at line 171 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and I2S_Receive_IT().

#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)

Definition at line 170 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), I2S_DMARxCplt(), and I2S_DMATxCplt().

#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)

Definition at line 169 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit().

#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)

Definition at line 168 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAPause(), HAL_I2S_DMAResume(), HAL_I2S_Transmit(), I2S_DMARxCplt(), and I2S_DMATxCplt().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Standard

Defines
I2S Standard
I2S Exported Constants

Defines

#define | I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
#define | I2S_STANDARD_MSB ((uint32_t)0x00000010U)
#define | I2S_STANDARD_LSB ((uint32_t)0x00000020U)
#define | I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
#define | I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)

Define Documentation

#define I2S_STANDARD_LSB ((uint32_t)0x00000020U)

Definition at line 181 of file stm32f4xx_hal_i2s.h.

#define I2S_STANDARD_MSB ((uint32_t)0x00000010U)

Definition at line 180 of file stm32f4xx_hal_i2s.h.

#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)

Definition at line 183 of file stm32f4xx_hal_i2s.h.

#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)

Definition at line 182 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)

Definition at line 179 of file stm32f4xx_hal_i2s.h.

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STM32F410Rx HAL User Manual: I2S Data Format

Defines
I2S Data Format
I2S Exported Constants

Defines

#define | I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
#define | I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
#define | I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)

Define Documentation

#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)

Definition at line 191 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)

Definition at line 192 of file stm32f4xx_hal_i2s.h.

#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)

Definition at line 193 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)

Definition at line 194 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Mclk Output

Defines
I2S Mclk Output
I2S Exported Constants

Defines

#define | I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)

Definition at line 203 of file stm32f4xx_hal_i2s.h.

#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)

Definition at line 202 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Audio Frequency

Defines
I2S Audio Frequency
I2S Exported Constants

Defines

#define | I2S_AUDIOFREQ_192K ((uint32_t)192000U)
#define | I2S_AUDIOFREQ_96K ((uint32_t)96000U)
#define | I2S_AUDIOFREQ_48K ((uint32_t)48000U)
#define | I2S_AUDIOFREQ_44K ((uint32_t)44100U)
#define | I2S_AUDIOFREQ_32K ((uint32_t)32000U)
#define | I2S_AUDIOFREQ_22K ((uint32_t)22050U)
#define | I2S_AUDIOFREQ_16K ((uint32_t)16000U)
#define | I2S_AUDIOFREQ_11K ((uint32_t)11025U)
#define | I2S_AUDIOFREQ_8K ((uint32_t)8000U)
#define | I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)

Define Documentation

#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)

Definition at line 218 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)

Definition at line 217 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)

Definition at line 211 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)

Definition at line 216 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)

Definition at line 215 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)

Definition at line 214 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)

Definition at line 213 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)

Definition at line 219 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)

Definition at line 212 of file stm32f4xx_hal_i2s.h.

#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)

Definition at line 220 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S FullDuplex Mode

Defines
I2S FullDuplex Mode
I2S Exported Constants

Defines

#define | I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000U)
#define | I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001U)

Define Documentation

#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000U)

Definition at line 228 of file stm32f4xx_hal_i2s.h.

#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001U)

Definition at line 229 of file stm32f4xx_hal_i2s.h.

Referenced by I2S_DMARxCplt(), and I2S_DMATxCplt().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Clock Polarity

Defines
I2S Clock Polarity
I2S Exported Constants

Defines

#define | I2S_CPOL_LOW ((uint32_t)0x00000000U)
#define | I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)

Define Documentation

#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)

Definition at line 238 of file stm32f4xx_hal_i2s.h.

#define I2S_CPOL_LOW ((uint32_t)0x00000000U)

Definition at line 237 of file stm32f4xx_hal_i2s.h.

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STM32F410Rx HAL User Manual: I2S Interrupts Definition

Defines
I2S Interrupts Definition
I2S Exported Constants

Defines

#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define I2S_IT_ERR SPI_CR2_ERRIE

Definition at line 248 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit_IT(), I2S_Receive_IT(), and I2S_Transmit_IT().

#define I2S_IT_RXNE SPI_CR2_RXNEIE

Definition at line 247 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive_IT(), and I2S_Receive_IT().

#define I2S_IT_TXE SPI_CR2_TXEIE

Definition at line 246 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Transmit_IT(), and I2S_Transmit_IT().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Flags Definition

Defines
I2S Flags Definition
I2S Exported Constants

Defines

#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY

Define Documentation

#define I2S_FLAG_BSY SPI_SR_BSY

Definition at line 264 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Transmit().

#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE

Definition at line 263 of file stm32f4xx_hal_i2s.h.

#define I2S_FLAG_FRE SPI_SR_FRE

Definition at line 261 of file stm32f4xx_hal_i2s.h.

#define I2S_FLAG_OVR SPI_SR_OVR

Definition at line 260 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define I2S_FLAG_RXNE SPI_SR_RXNE

Definition at line 257 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Receive().

#define I2S_FLAG_TXE SPI_SR_TXE

Definition at line 256 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and HAL_I2S_Transmit().

#define I2S_FLAG_UDR SPI_SR_UDR

Definition at line 259 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

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STM32F410Rx HAL User Manual: I2S Exported Macros

Defines
I2S Exported Macros
I2S

Defines

#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
Enable or disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.

Define Documentation

#define __HAL_I2S_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->DR;        \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    UNUSED(tmpreg);                             \
  } while(0)

Clears the I2S OVR pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 334 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), and I2S_Receive_IT().

#define __HAL_I2S_CLEAR_UDRFLAG ( __HANDLE__ )
Value:
do{                                           \
  __IO uint32_t tmpreg = 0x00U;                 \
  tmpreg = (__HANDLE__)->Instance->SR;          \
  UNUSED(tmpreg);                               \
  } while(0)

Clears the I2S UDR pending flag.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 346 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define __HAL_I2S_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)

Definition at line 289 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAStop().

#define __HAL_I2S_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))

Definition at line 301 of file stm32f4xx_hal_i2s.h.

Referenced by I2S_Receive_IT(), and I2S_Transmit_IT().

#define __HAL_I2S_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)

Enable or disable the specified SPI peripheral (in I2S mode).

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 288 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_DMAResume(), HAL_I2S_Receive(), HAL_I2S_Receive_DMA(), HAL_I2S_Receive_IT(), HAL_I2S_Transmit(), HAL_I2S_Transmit_DMA(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable or disable the specified I2S interrupts.

Parameters:
__HANDLE__,: specifies the I2S Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 300 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Receive_IT(), and HAL_I2S_Transmit_IT().

#define __HAL_I2S_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Checks whether the specified I2S flag is set or not.

Parameters:
__HANDLE__,: specifies the I2S Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • I2S_FLAG_RXNE: Receive buffer not empty flag
  • I2S_FLAG_TXE: Transmit buffer empty flag
  • I2S_FLAG_UDR: Underrun flag
  • I2S_FLAG_OVR: Overrun flag
  • I2S_FLAG_FRE: Frame error flag
  • I2S_FLAG_CHSIDE: Channel Side flag
  • I2S_FLAG_BSY: Busy flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 328 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler(), and I2S_WaitFlagStateUntilTimeout().

#define __HAL_I2S_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2S interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the I2S Handle. This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
__INTERRUPT__,: specifies the I2S interrupt source to check. This parameter can be one of the following values:
  • I2S_IT_TXE: Tx buffer empty interrupt enable
  • I2S_IT_RXNE: RX buffer not empty interrupt enable
  • I2S_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 313 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_IRQHandler().

#define __HAL_I2S_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)

Reset I2S handle state.

Parameters:
__HANDLE__,: specifies the I2S Handle.
Return values:
None

Definition at line 282 of file stm32f4xx_hal_i2s.h.

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STM32F410Rx HAL User Manual: I2S Private Constants

I2S Private Constants
I2S
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | IS_I2S_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_FULLDUPLEX_MODE(MODE)
#define | IS_I2S_CPOL(CPOL)

Define Documentation

#define IS_I2S_AUDIO_FREQ ( FREQ )
Value:
((((FREQ) >= I2S_AUDIOFREQ_8K) && \
                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))

Definition at line 449 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_CPOL ( CPOL )
Value:
(((CPOL) == I2S_CPOL_LOW) || \
                           ((CPOL) == I2S_CPOL_HIGH))

Definition at line 456 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_DATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == I2S_DATAFORMAT_16B)          || \
                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
                                    ((FORMAT) == I2S_DATAFORMAT_32B))

Definition at line 441 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_FULLDUPLEX_MODE ( MODE )
Value:
(((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
                                      ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))

Definition at line 453 of file stm32f4xx_hal_i2s.h.

#define IS_I2S_MCLK_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))

Definition at line 446 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_MODE ( MODE )
Value:
(((MODE) == I2S_MODE_SLAVE_TX)  || \
                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
                           ((MODE) == I2S_MODE_MASTER_TX) || \
                           ((MODE) == I2S_MODE_MASTER_RX))

Definition at line 430 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

#define IS_I2S_STANDARD ( STANDARD )
Value:
(((STANDARD) == I2S_STANDARD_PHILIPS)   || \
                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))

Definition at line 435 of file stm32f4xx_hal_i2s.h.

Referenced by HAL_I2S_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Private Functions

Functions
I2S Private Functions
I2S

Functions

void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.

Function Documentation

void I2S_DMAError ( DMA_HandleTypeDef * hdma )

DMA I2S communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1230 of file stm32f4xx_hal_i2s.c.

References I2S_HandleTypeDef::ErrorCode, HAL_I2S_ERROR_DMA, HAL_I2S_ErrorCallback(), HAL_I2S_STATE_READY, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA(), and HAL_I2S_Transmit_DMA().

void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma )

DMA I2S receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1251 of file stm32f4xx_hal_i2s_ex.c.

References I2S_InitTypeDef::FullDuplexMode, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, I2S_FULLDUPLEXMODE_ENABLE, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_TX, I2SxEXT, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA().

void I2S_DMARxHalfCplt ( DMA_HandleTypeDef * hdma )

DMA I2S receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1217 of file stm32f4xx_hal_i2s.c.

References HAL_I2S_RxHalfCpltCallback().

Referenced by HAL_I2S_Receive_DMA().

void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma )

DMA I2S transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1198 of file stm32f4xx_hal_i2s_ex.c.

References I2S_InitTypeDef::FullDuplexMode, HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_FULLDUPLEXMODE_ENABLE, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_TX, I2SxEXT, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

void I2S_DMATxHalfCplt ( DMA_HandleTypeDef * hdma )

DMA I2S transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1204 of file stm32f4xx_hal_i2s.c.

References HAL_I2S_TxHalfCpltCallback().

Referenced by HAL_I2S_Transmit_DMA().

HAL_StatusTypeDef I2S_Receive_IT ( I2S_HandleTypeDef * hi2s )

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1293 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_CLEAR_OVRFLAG, __HAL_I2S_DISABLE_IT, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_BUSY_RX, HAL_I2S_STATE_READY, I2S_IT_ERR, I2S_IT_RXNE, I2S_MODE_MASTER_RX, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pRxBuffPtr, I2S_HandleTypeDef::RxXferCount, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_IRQHandler().

HAL_StatusTypeDef I2S_Transmit_IT ( I2S_HandleTypeDef * hi2s )

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
HAL status

Definition at line 1249 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_DISABLE_IT, HAL_I2S_STATE_BUSY_TX, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_IT_ERR, I2S_IT_TXE, I2S_HandleTypeDef::Instance, I2S_HandleTypeDef::pTxBuffPtr, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_IRQHandler().

HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint32_t | Flag,
 |  | uint32_t | Status,
 |  | uint32_t | Timeout
 | ) |  |

This function handles I2S Communication Timeout.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Flag,: Flag checked
Status,: Value of the flag expected
Timeout,: Duration of the timeout
Return values:
HAL status

Definition at line 1348 of file stm32f4xx_hal_i2s.c.

References __HAL_I2S_GET_FLAG, HAL_GetTick(), HAL_I2S_STATE_READY, and I2S_HandleTypeDef::State.

Referenced by HAL_I2S_Receive(), and HAL_I2S_Transmit().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extension features functions

Functions
Extension features functions
I2S Exported Functions

Extension features functions. More...

Functions

void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
uint32_t | I2S_GetInputClock (I2S_HandleTypeDef *hi2s)
Get I2S clock Input based on Source clock selection in RCC.

Detailed Description

Extension features functions.

 ===============================================================================
                       ##### Extension features Functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2S data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2S_TransmitReceive()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2S_TransmitReceive_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2S_TransmitReceive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2S_TxCpltCallback()
        (++) HAL_I2S_RxCpltCallback()
        (++) HAL_I2S_ErrorCallback()

Function Documentation

void I2S_DMARxCplt ( DMA_HandleTypeDef * hdma )

DMA I2S receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1251 of file stm32f4xx_hal_i2s_ex.c.

References I2S_InitTypeDef::FullDuplexMode, HAL_I2S_RxCpltCallback(), HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, I2S_FULLDUPLEXMODE_ENABLE, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_TX, I2SxEXT, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Receive_DMA().

void I2S_DMATxCplt ( DMA_HandleTypeDef * hdma )

DMA I2S transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1198 of file stm32f4xx_hal_i2s_ex.c.

References I2S_InitTypeDef::FullDuplexMode, HAL_I2S_STATE_BUSY_TX_RX, HAL_I2S_STATE_READY, HAL_I2S_TxCpltCallback(), I2S_FULLDUPLEXMODE_ENABLE, I2S_MODE_MASTER_TX, I2S_MODE_SLAVE_TX, I2SxEXT, I2S_HandleTypeDef::Init, I2S_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, I2S_HandleTypeDef::RxXferCount, I2S_HandleTypeDef::State, and I2S_HandleTypeDef::TxXferCount.

Referenced by HAL_I2S_Transmit_DMA().

uint32_t I2S_GetInputClock ( I2S_HandleTypeDef * hi2s )

Get I2S clock Input based on Source clock selection in RCC.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Clock Input

Definition at line 1304 of file stm32f4xx_hal_i2s_ex.c.

References __HAL_RCC_I2S_CONFIG, I2S_InitTypeDef::ClockSource, EXTERNAL_CLOCK_VALUE, HSE_VALUE, HSI_VALUE, I2S_CLOCK_EXTERNAL, I2S_CLOCK_PLLR, I2S_CLOCK_PLLSRC, I2S_HandleTypeDef::Init, and RCC_PLLSOURCE_HSE.

Referenced by HAL_I2S_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2SEx_Exported_Functions_Group1

Functions
I2SEx_Exported_Functions_Group1
I2S Exported Functions

Functions

HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)

Function Documentation

HAL_StatusTypeDef HAL_I2SEx_TransmitReceive | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pTxData,
 |  | uint16_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pTxData,
 |  | uint16_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT | ( | I2S_HandleTypeDef * | hi2s,
 |  | uint16_t * | pTxData,
 |  | uint16_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Exported Types

I2S Exported Types
I2SEx
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Clock Source

Defines
I2S Clock Source
I2S Exported Constants

Defines

#define | I2S_CLOCK_PLLSRC ((uint32_t)0x00000000U)
#define | I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
#define | I2S_CLOCK_PLLR ((uint32_t)0x00000002U)

Define Documentation

#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)

Definition at line 92 of file stm32f4xx_hal_i2s_ex.h.

Referenced by I2S_GetInputClock().

#define I2S_CLOCK_PLLR ((uint32_t)0x00000002U)

Definition at line 93 of file stm32f4xx_hal_i2s_ex.h.

Referenced by I2S_GetInputClock().

#define I2S_CLOCK_PLLSRC ((uint32_t)0x00000000U)

Definition at line 91 of file stm32f4xx_hal_i2s_ex.h.

Referenced by I2S_GetInputClock().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Exported Macros

I2S Exported Macros
I2SEx
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Private Constants

I2S Private Constants
I2SEx
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2SEx

Defines

#define | IS_I2S_CLOCKSOURCE(CLOCK)
#define | I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))

Define Documentation

#define I2SxEXT ( __INSTANCE__ ) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))

Definition at line 175 of file stm32f4xx_hal_i2s_ex.h.

Referenced by I2S_DMARxCplt(), and I2S_DMATxCplt().

#define IS_I2S_CLOCKSOURCE ( CLOCK )
Value:
(((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
                                   ((CLOCK) == I2S_CLOCK_PLLSRC)     ||\
                                   ((CLOCK) == I2S_CLOCK_PLLR))

Definition at line 166 of file stm32f4xx_hal_i2s_ex.h.

Referenced by HAL_I2S_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: I2S Private Functions

Functions
I2S Private Functions
I2SEx

Functions

HAL_StatusTypeDef | I2SEx_TransmitReceive_IT (I2S_HandleTypeDef *hi2s)
uint32_t | I2S_GetInputClock (I2S_HandleTypeDef *hi2s)
Get I2S clock Input based on Source clock selection in RCC.

Function Documentation

uint32_t I2S_GetInputClock ( I2S_HandleTypeDef * hi2s )

Get I2S clock Input based on Source clock selection in RCC.

Parameters:
hi2s,: pointer to a I2S_HandleTypeDef structure that contains the configuration information for I2S module
Return values:
I2S Clock Input

Definition at line 1304 of file stm32f4xx_hal_i2s_ex.c.

References __HAL_RCC_I2S_CONFIG, I2S_InitTypeDef::ClockSource, EXTERNAL_CLOCK_VALUE, HSE_VALUE, HSI_VALUE, I2S_CLOCK_EXTERNAL, I2S_CLOCK_PLLR, I2S_CLOCK_PLLSRC, I2S_HandleTypeDef::Init, and RCC_PLLSOURCE_HSE.

Referenced by HAL_I2S_Init().

HAL_StatusTypeDef I2SEx_TransmitReceive_IT ( I2S_HandleTypeDef * hi2s )
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IrDA Initialization and de-initialization functions

Functions
IrDA Initialization and de-initialization functions
IrDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in IrDA mode.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) BaudRate
        (++) WordLength
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
             Depending on the frame length defined by the M bit (8-bits or 9-bits),
             please refer to Reference manual for possible IRDA frame formats.
        (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
             not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
             specification specifies a minimum of 10 ms delay between transmission and
             reception (IrDA is a half duplex protocol).
        (++) Mode: Receiver/transmitter modes
        (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
    [..]
    The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
    are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitializes the IRDA peripheral.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 273 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 212 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_SetConfig(), IRDA_InitTypeDef::IrDAMode, IS_IRDA_POWERMODE, IRDA_HandleTypeDef::Lock, IRDA_InitTypeDef::Prescaler, and IRDA_HandleTypeDef::RxState.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

IRDA MSP DeInit.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 324 of file stm32f4xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

IRDA MSP Init.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 309 of file stm32f4xx_hal_irda.c.

Referenced by HAL_IRDA_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
IrDA Exported Functions

IRDA Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.

Detailed Description

IRDA Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the IRDA data transfers.
    [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the HAL status.
           The end of the data processing will be indicated through the
           dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pauses the DMA Transfer.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 760 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resumes the DMA Transfer.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 788 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stops the DMA Transfer.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 818 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 993 of file stm32f4xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), and IRDA_DMAError().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

This function handles IRDA interrupt request.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 853 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FEFLAG, __HAL_IRDA_CLEAR_NEFLAG, __HAL_IRDA_CLEAR_OREFLAG, __HAL_IRDA_CLEAR_PEFLAG, __HAL_IRDA_GET_FLAG, __HAL_IRDA_GET_IT_SOURCE, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_READY, IRDA_EndTransmit_IT(), IRDA_FLAG_FE, IRDA_FLAG_NE, IRDA_FLAG_ORE, IRDA_FLAG_PE, IRDA_FLAG_RXNE, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_IT_TC, IRDA_IT_TXE, IRDA_Receive_IT(), IRDA_Transmit_IT(), and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 474 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Note:
When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 706 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 598 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer complete callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 963 of file stm32f4xx_hal_irda.c.

Referenced by IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 978 of file stm32f4xx_hal_irda.c.

Referenced by IRDA_DMAReceiveHalfCplt().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Sends an amount of data in blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 396 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 645 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_FLAG_TC, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 555 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_TXE, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer complete callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 933 of file stm32f4xx_hal_irda.c.

Referenced by IRDA_DMATransmitCplt(), and IRDA_EndTransmit_IT().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 948 of file stm32f4xx_hal_irda.c.

Referenced by IRDA_DMATransmitHalfCplt().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
IrDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IARDA error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
     (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IARDA error code.

Parameters:
hirda : pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA.
Return values:
IRDA Error Code

Definition at line 1044 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Returns the IRDA state.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 1029 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, and IRDA_HandleTypeDef::RxState.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IrDA Exported Functions

Modules | Functions
IrDA Exported Functions
IRDA

Modules

IrDA Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit/Receive functions.

Peripheral State and Errors functions

IRDA State and Errors functions.

Functions

static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles IRDA Communication Timeout.
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receives an amount of data in non blocking mode.
static void | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configures the IRDA peripheral.

Function Documentation

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1135 of file stm32f4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1098 of file stm32f4xx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1123 of file stm32f4xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback().

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1058 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, IRDA_IT_TC, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1086 of file stm32f4xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback().

Referenced by HAL_IRDA_Transmit_DMA().

static HAL_StatusTypeDef IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wraps up transmission in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1274 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), IRDA_IT_ERR, and IRDA_IT_TC.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receives an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1296 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configures the IRDA peripheral.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1361 of file stm32f4xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_BRR, IS_IRDA_BAUDRATE, IS_IRDA_MODE, IS_IRDA_PARITY, IS_IRDA_WORD_LENGTH, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static HAL_StatusTypeDef IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1226 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_IT_TC, IRDA_IT_TXE, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles IRDA Communication Timeout.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag,: specifies the IRDA flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1157 of file stm32f4xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, __HAL_IRDA_GET_FLAG, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_IT_TXE, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Transmit().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Exported Types

Data Structures | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...

Enumeration Type Documentation

enum HAL_IRDA_StateTypeDef

HAL IRDA State structures definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState.
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_IRDA_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_IRDA_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_IRDA_STATE_BUSY

An internal process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_IRDA_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_IRDA_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_IRDA_STATE_ERROR

Error Value is allowed for gState only

Definition at line 129 of file stm32f4xx_hal_irda.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32f4xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint32_t | IrDAMode

Detailed Description

IRDA Init Structure definition.

Definition at line 64 of file stm32f4xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5

Definition at line 66 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::IrDAMode

Specifies the IrDA mode This parameter can be a value of IRDA Low Power

Definition at line 86 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint32_t IRDA_InitTypeDef::Mode

Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 81 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 74 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler

Definition at line 84 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDA Word Length

Definition at line 71 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_irda.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32f4xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

IRDA handle Structure definition.

Definition at line 153 of file stm32f4xx_hal_irda.h.

Field Documentation

__IO uint32_t IRDA_HandleTypeDef::ErrorCode

Definition at line 184 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_GetError(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_DMAError().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::gState

Definition at line 177 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), IRDA_EndTransmit_IT(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmarx

Definition at line 173 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAStop(), and HAL_IRDA_Receive_DMA().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmatx

Definition at line 171 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAStop(), and HAL_IRDA_Transmit_DMA().

IRDA_InitTypeDef IRDA_HandleTypeDef::Init

Definition at line 157 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Init(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* IRDA_HandleTypeDef::Instance

Definition at line 155 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

HAL_LockTypeDef IRDA_HandleTypeDef::Lock

Definition at line 175 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint8_t* IRDA_HandleTypeDef::pRxBuffPtr

Definition at line 165 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pTxBuffPtr

Definition at line 159 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::RxState

Definition at line 181 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

uint16_t IRDA_HandleTypeDef::RxXferCount

Definition at line 169 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::RxXferSize

Definition at line 167 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::TxXferCount

Definition at line 163 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), IRDA_DMATransmitCplt(), and IRDA_Transmit_IT().

uint16_t IRDA_HandleTypeDef::TxXferSize

Definition at line 161 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_irda.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Error Code

Defines
IRDA Error Code
IRDA Exported constants

IRDA Error Code. More...

Defines

#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)

Detailed Description

IRDA Error Code.

Define Documentation

#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 204 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_DMAError().

#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)

Frame error

Definition at line 202 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 201 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 199 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 203 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 200 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Word Length

Defines
IRDA Word Length
IRDA Exported constants

Defines

#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)

Definition at line 212 of file stm32f4xx_hal_irda.h.

#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 213 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported constants

Defines

#define | IRDA_PARITY_NONE ((uint32_t)0x00000000U)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 222 of file stm32f4xx_hal_irda.h.

#define IRDA_PARITY_NONE ((uint32_t)0x00000000U)

Definition at line 221 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 223 of file stm32f4xx_hal_irda.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported constants

Defines

#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 231 of file stm32f4xx_hal_irda.h.

#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 232 of file stm32f4xx_hal_irda.h.

#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 233 of file stm32f4xx_hal_irda.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported constants

Defines

#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000U)

Define Documentation

#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

Definition at line 241 of file stm32f4xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000U)

Definition at line 242 of file stm32f4xx_hal_irda.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_TXE ((uint32_t)0x00000080U)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040U)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
#define | IRDA_FLAG_IDLE ((uint32_t)0x00000010U)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008U)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004U)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002U)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001U)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define IRDA_FLAG_FE ((uint32_t)0x00000002U)

Definition at line 258 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_FLAG_IDLE ((uint32_t)0x00000010U)

Definition at line 255 of file stm32f4xx_hal_irda.h.

#define IRDA_FLAG_NE ((uint32_t)0x00000004U)

Definition at line 257 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_FLAG_ORE ((uint32_t)0x00000008U)

Definition at line 256 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_FLAG_PE ((uint32_t)0x00000001U)

Definition at line 259 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_FLAG_RXNE ((uint32_t)0x00000020U)

Definition at line 254 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), and HAL_IRDA_Receive().

#define IRDA_FLAG_TC ((uint32_t)0x00000040U)

Definition at line 253 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Transmit(), and HAL_IRDA_Transmit_DMA().

#define IRDA_FLAG_TXE ((uint32_t)0x00000080U)

Definition at line 252 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), and HAL_IRDA_Transmit().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Interrupt Definitions

Defines
IRDA Interrupt Definitions
IRDA Exported constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask in the XX register
  • Y : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register

Define Documentation

#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))

Definition at line 281 of file stm32f4xx_hal_irda.h.

#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 282 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit_IT(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 277 of file stm32f4xx_hal_irda.h.

#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))

Definition at line 279 of file stm32f4xx_hal_irda.h.

#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 273 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 276 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 275 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_Transmit_IT().

#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 274 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Transmit_IT(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle gstate & RxState.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushs the IRDA DR register.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables or disables the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Macro to enable the IRDA's one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
Macro to disable the IRDA's one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 373 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified IRDA pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_FLAG_TC: Transmission Complete flag.
  • IRDA_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register.
TXE flag is cleared only by a write to the USART_DR register.
Return values:
None

Definition at line 352 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 397 of file stm32f4xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 381 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 389 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), and HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    UNUSED(tmpreg);                             \
  } while(0)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 360 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
Return values:
None

Definition at line 463 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))

Definition at line 416 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
Return values:
None

Definition at line 455 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))

Enables or disables the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__INTERRUPT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_PE: Parity Error interrupt
  • IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 413 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit_IT(), IRDA_DMATransmitCplt(), and IRDA_Transmit_IT().

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ ) ((__HANDLE__)->Instance->DR)

Flushs the IRDA DR register.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.

Definition at line 312 of file stm32f4xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_TXE: Transmit data register empty flag
  • IRDA_FLAG_TC: Transmission Complete flag
  • IRDA_FLAG_RXNE: Receive data register not empty flag
  • IRDA_FLAG_IDLE: Idle Line detection flag
  • IRDA_FLAG_ORE: OverRun Error flag
  • IRDA_FLAG_NE: Noise Error flag
  • IRDA_FLAG_FE: Framing Error flag
  • IRDA_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 330 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), and IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
(((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))

Checks whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • USART_IT_ERR: Error interrupt
  • IRDA_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 434 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))

Macro to disable the IRDA's one bit sample method.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 447 of file stm32f4xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Macro to enable the IRDA's one bit sample method.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 441 of file stm32f4xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                     } while(0)

Reset IRDA handle gstate & RxState.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 302 of file stm32f4xx_hal_irda.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_IT_MASK
IRDA interruptions flag mask.
#define | IRDA_CR1_REG_INDEX 1U
#define | IRDA_CR2_REG_INDEX 2U
#define | IRDA_CR3_REG_INDEX 3U

Define Documentation

#define IRDA_CR1_REG_INDEX 1U

Definition at line 536 of file stm32f4xx_hal_irda.h.

#define IRDA_CR2_REG_INDEX 2U

Definition at line 537 of file stm32f4xx_hal_irda.h.

#define IRDA_CR3_REG_INDEX 3U

Definition at line 538 of file stm32f4xx_hal_irda.h.

#define IRDA_IT_MASK
Value:
((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
                                  USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )

IRDA interruptions flag mask.

Definition at line 533 of file stm32f4xx_hal_irda.h.

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STM32F410Rx HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IS_IRDA_WORD_LENGTH(LENGTH)
#define | IS_IRDA_PARITY(PARITY)
#define | IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00000000U))
#define | IS_IRDA_POWERMODE(MODE)
#define | IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
#define | IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
#define | IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | IRDA_BRR(_PCLK_, _BAUD_)

Define Documentation

#define IRDA_BRR | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
                                             (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
                                             (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 562 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IRDA_DIV | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(4U*(_BAUD_)))

Definition at line 557 of file stm32f4xx_hal_irda.h.

#define IRDA_DIVFRAQ | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 559 of file stm32f4xx_hal_irda.h.

#define IRDA_DIVMANT | ( | _PCLK_,
 |  | _BAUD_
 | ) | (IRDA_DIV((_PCLK_), (_BAUD_))/100U)

Definition at line 558 of file stm32f4xx_hal_irda.h.

#define IS_IRDA_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 115201U)

Definition at line 555 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_MODE ( MODE ) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00000000U))

Definition at line 552 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PARITY ( PARITY )
Value:
(((PARITY) == IRDA_PARITY_NONE) || \
                                ((PARITY) == IRDA_PARITY_EVEN) || \
                                ((PARITY) == IRDA_PARITY_ODD))

Definition at line 549 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( MODE )
Value:
(((MODE) == IRDA_POWERMODE_LOWPOWER) || \
                                 ((MODE) == IRDA_POWERMODE_NORMAL))

Definition at line 553 of file stm32f4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define IS_IRDA_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == IRDA_WORDLENGTH_8B) || \
                                     ((LENGTH) == IRDA_WORDLENGTH_9B))

Definition at line 547 of file stm32f4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

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STM32F410Rx HAL User Manual: IRDA Private Functions

IRDA Private Functions
IRDA
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.
__weak void | HAL_IWDG_MspInit (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters
          in the IWDG_InitTypeDef and create the associated handle
      (+) Initialize the IWDG MSP
      (+) DeInitialize IWDG MSP

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 168 of file stm32f4xx_hal_iwdg.c.

References assert_param, HAL_IWDG_MspInit(), HAL_IWDG_STATE_BUSY, HAL_IWDG_STATE_READY, HAL_IWDG_STATE_RESET, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IWDG_ENABLE_WRITE_ACCESS, IWDG_HandleTypeDef::Lock, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_HandleTypeDef::State.

void HAL_IWDG_MspInit ( IWDG_HandleTypeDef * hiwdg )

Initializes the IWDG MSP.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
None

Definition at line 212 of file stm32f4xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

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STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_IWDG_Start (IWDG_HandleTypeDef *hiwdg)
Starts the IWDG.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refreshes the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the IWDG.
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refreshes the IWDG.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 276 of file stm32f4xx_hal_iwdg.c.

References __HAL_IWDG_GET_FLAG, __HAL_IWDG_RELOAD_COUNTER, HAL_GetTick(), HAL_IWDG_STATE_BUSY, HAL_IWDG_STATE_READY, HAL_IWDG_STATE_TIMEOUT, IWDG_FLAG_RVU, IWDG_TIMEOUT_FLAG, and IWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IWDG_Start ( IWDG_HandleTypeDef * hiwdg )

Starts the IWDG.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 246 of file stm32f4xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, HAL_IWDG_STATE_BUSY, HAL_IWDG_STATE_READY, and IWDG_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
IWDG Exported Functions

Peripheral State functions. More...

Functions

HAL_IWDG_StateTypeDef HAL_IWDG_GetState (IWDG_HandleTypeDef *hiwdg)
Returns the IWDG state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_IWDG_StateTypeDef HAL_IWDG_GetState ( IWDG_HandleTypeDef * hiwdg )

Returns the IWDG state.

Parameters:
hiwdg,: pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL state

Definition at line 341 of file stm32f4xx_hal_iwdg.c.

References IWDG_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: IWDG Exported Types

Data Structures | Enumerations
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Enumerations

enum HAL_IWDG_StateTypeDef {
HAL_IWDG_STATE_RESET = 0x00U, HAL_IWDG_STATE_READY = 0x01U, HAL_IWDG_STATE_BUSY = 0x02U, HAL_IWDG_STATE_TIMEOUT = 0x03U,
HAL_IWDG_STATE_ERROR = 0x04U
}
IWDG HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_IWDG_StateTypeDef

IWDG HAL State Structure definition.

Enumerator:
HAL_IWDG_STATE_RESET

IWDG not yet initialized or disabled

HAL_IWDG_STATE_READY

IWDG initialized and ready for use

HAL_IWDG_STATE_BUSY

IWDG internal process is ongoing

HAL_IWDG_STATE_TIMEOUT

IWDG timeout state

HAL_IWDG_STATE_ERROR

IWDG error state

Definition at line 65 of file stm32f4xx_hal_iwdg.h.

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STM32F410Rx HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32f4xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload

Detailed Description

IWDG Init structure definition.

Definition at line 77 of file stm32f4xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 79 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU

Definition at line 82 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_iwdg.h
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STM32F410Rx HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32f4xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * | Instance
IWDG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_IWDG_StateTypeDef | State

Detailed Description

IWDG Handle Structure definition.

Definition at line 89 of file stm32f4xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 93 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 91 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

HAL_LockTypeDef IWDG_HandleTypeDef::Lock

IWDG Locking object

Definition at line 95 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

__IO HAL_IWDG_StateTypeDef IWDG_HandleTypeDef::State

IWDG communication state

Definition at line 97 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_GetState(), HAL_IWDG_Init(), HAL_IWDG_Refresh(), and HAL_IWDG_Start().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_iwdg.h
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STM32F410Rx HAL User Manual: IWDG Registers BitMask

Defines
IWDG Registers BitMask
IWDG Exported Constants

IWDG registers bit mask. More...

Defines

#define | IWDG_KEY_RELOAD ((uint32_t)0xAAAAU)
#define | IWDG_KEY_ENABLE ((uint32_t)0xCCCCU)
#define | IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555U)
#define | IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000U)

Detailed Description

IWDG registers bit mask.

Define Documentation

#define IWDG_KEY_ENABLE ((uint32_t)0xCCCCU)

IWDG Peripheral Enable

Definition at line 116 of file stm32f4xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD ((uint32_t)0xAAAAU)

IWDG Reload Counter Enable

Definition at line 115 of file stm32f4xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000U)

IWDG KR Write Access Disable

Definition at line 118 of file stm32f4xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555U)

IWDG KR Write Access Enable

Definition at line 117 of file stm32f4xx_hal_iwdg.h.

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STM32F410Rx HAL User Manual: IWDG Flag definition

Defines
IWDG Flag definition
IWDG Exported Constants

Defines

#define | IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU)
#define | IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU)

Define Documentation

#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU)

Watchdog counter prescaler value update Flag

Definition at line 126 of file stm32f4xx_hal_iwdg.h.

#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU)

Watchdog counter reload value update Flag

Definition at line 127 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Refresh().

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STM32F410Rx HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 ((uint8_t)0x00U)
#define | IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0))
#define | IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1))
#define | IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2))
#define | IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))

Define Documentation

#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))

IWDG prescaler set to 128

Definition at line 140 of file stm32f4xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1))

IWDG prescaler set to 16

Definition at line 137 of file stm32f4xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))

IWDG prescaler set to 256

Definition at line 141 of file stm32f4xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))

IWDG prescaler set to 32

Definition at line 138 of file stm32f4xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 ((uint8_t)0x00U)

IWDG prescaler set to 4

Definition at line 135 of file stm32f4xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2))

IWDG prescaler set to 64

Definition at line 139 of file stm32f4xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0))

IWDG prescaler set to 8

Definition at line 136 of file stm32f4xx_hal_iwdg.h.

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STM32F410Rx HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
Reset IWDG handle state.
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enables the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
#define | __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected IWDG's flag status.

Define Documentation

#define __HAL_IWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Gets the selected IWDG's flag status.

Parameters:
__HANDLE__,: IWDG handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • IWDG_FLAG_PVU: Watchdog counter reload value update flag
  • IWDG_FLAG_RVU: Watchdog counter prescaler value flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 185 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Refresh().

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 174 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Refresh(), and HAL_IWDG_Start().

#define __HAL_IWDG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)

Reset IWDG handle state.

Parameters:
__HANDLE__,: IWDG handle.
Return values:
None

Definition at line 159 of file stm32f4xx_hal_iwdg.h.

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enables the IWDG peripheral.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 166 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Start().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enables write access to IWDG_PR and IWDG_RLR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disables write access to IWDG_PR and IWDG_RLR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU)

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                          ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                          ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                          ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                          ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                          ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                          ((__PRESCALER__) == IWDG_PRESCALER_256))

Definition at line 250 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= 0xFFFU)

Definition at line 259 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disables write access to IWDG_PR and IWDG_RLR registers.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 247 of file stm32f4xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enables write access to IWDG_PR and IWDG_RLR registers.

Parameters:
__HANDLE__,: IWDG handle
Return values:
None

Definition at line 240 of file stm32f4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define IWDG_TIMEOUT_FLAG ((uint32_t)1000U) /* 1 s */

Define Documentation

#define IWDG_TIMEOUT_FLAG ((uint32_t)1000U) /* 1 s */

Definition at line 131 of file stm32f4xx_hal_iwdg.c.

Referenced by HAL_IWDG_Refresh().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Private Types

LPTIM Private Types
LPTIM
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Private Defines

LPTIM Private Defines
LPTIM
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and creates the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 321 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 228 of file stm32f4xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

__weak void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 367 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

__weak void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 353 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1224 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1288 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1263 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1333 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 911 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 989 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 961 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1046 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 581 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 645 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 618 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 701 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 415 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 479 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 452 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 535 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 747 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 811 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 784 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 867 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1084 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function in interrupt mode.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1153 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1121 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1193 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

This function return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1394 of file stm32f4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

This function return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1407 of file stm32f4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

This function returns the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1381 of file stm32f4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM IRQ handler

Functions
LPTIM IRQ handler
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.

Detailed Description

LPTIM IRQ handler.

  ==============================================================================
                      ##### LPTIM IRQ handler  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler function.

Function Documentation

__weak void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1546 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1588 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1532 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1574 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1616 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1602 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

This function handles LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1439 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

__weak void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1560 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Returns the LPTIM state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1648 of file stm32f4xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Exported Functions

Modules | Functions
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1546 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1588 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1532 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1574 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1224 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1288 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1263 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1333 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 321 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1616 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1602 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 911 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Starts the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 989 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 961 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Encoder interface in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1046 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Returns the LPTIM state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1648 of file stm32f4xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 228 of file stm32f4xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

This function handles LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1439 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitializes LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 367 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initializes the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 353 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 581 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 645 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 618 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 701 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 415 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 479 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 452 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 535 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

This function return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1394 of file stm32f4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

This function return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1407 of file stm32f4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

This function returns the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1381 of file stm32f4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 747 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Starts the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 811 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 784 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 867 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1084 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Starts the Timeout function in interrupt mode.

The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1153 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1121 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stops the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1193 of file stm32f4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1560 of file stm32f4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM WAKEUP Timer EXTI Line

Defines
LPTIM WAKEUP Timer EXTI Line
LPTIM Exported Types

Defines

#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23)

Define Documentation

#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23)

External interrupt line 23 Connected to the LPTIM EXTI Line

Definition at line 67 of file stm32f4xx_hal_lptim.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Exported Types

Data Structures | Modules | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Modules

LPTIM WAKEUP Timer EXTI Line

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...

Typedef Documentation

typedef enum __HAL_LPTIM_StateTypeDef HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumeration Type Documentation

enum __HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 147 of file stm32f4xx_hal_lptim.h.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32f4xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 75 of file stm32f4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 80 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 77 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_lptim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32f4xx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 88 of file stm32f4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 90 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 97 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_lptim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32f4xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 106 of file stm32f4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 111 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 115 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 108 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_lptim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32f4xx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 123 of file stm32f4xx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 125 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 138 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 131 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 129 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 127 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autorelaod and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 134 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_lptim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32f4xx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State

Detailed Description

LPTIM handle Structure definition.

Definition at line 159 of file stm32f4xx_hal_lptim.h.

Field Documentation

LPTIM_InitTypeDef LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 163 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 161 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_LockTypeDef LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 167 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

__IO HAL_LPTIM_StateTypeDef LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 169 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_StatusTypeDef LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 165 of file stm32f4xx_hal_lptim.h.

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_lptim.h
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STM32F410Rx HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)

Definition at line 185 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 186 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

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STM32F410Rx HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Define Documentation

#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x00000000U)

Definition at line 194 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Definition at line 201 of file stm32f4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 198 of file stm32f4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 195 of file stm32f4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))

Definition at line 199 of file stm32f4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 196 of file stm32f4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))

Definition at line 200 of file stm32f4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))

Definition at line 197 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)

Definition at line 210 of file stm32f4xx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Definition at line 211 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 220 of file stm32f4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 221 of file stm32f4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 222 of file stm32f4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)

Definition at line 219 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 232 of file stm32f4xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)

Definition at line 231 of file stm32f4xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 233 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Define Documentation

#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)

Definition at line 242 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)

Definition at line 243 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 244 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 245 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 246 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 247 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)

Definition at line 241 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

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STM32F410Rx HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 256 of file stm32f4xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 255 of file stm32f4xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 257 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 266 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 267 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 268 of file stm32f4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)

Definition at line 265 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 278 of file stm32f4xx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)

Definition at line 277 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 288 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)

Definition at line 287 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Flag Definition

Defines
LPTIM Flag Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 302 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 299 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 303 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 300 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 297 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 301 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 298 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

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STM32F410Rx HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 317 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 314 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 318 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 315 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 312 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 316 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 313 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

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STM32F410Rx HAL User Manual: Register Definition

Defines
Register Definition
LPTIM Exported Constants

Defines

#define | LPTIM_OP_PAD_AF ((uint32_t)0x00000000U)
#define | LPTIM_OP_PAD_PA4 LPTIM_OR_OR_0
#define | LPTIM_OP_PAD_PB9 LPTIM_OR_OR_1
#define | LPTIM_OP_TIM_DAC LPTIM_OR_OR

Define Documentation

#define LPTIM_OP_PAD_AF ((uint32_t)0x00000000U)

Definition at line 326 of file stm32f4xx_hal_lptim.h.

#define LPTIM_OP_PAD_PA4 LPTIM_OR_OR_0

Definition at line 327 of file stm32f4xx_hal_lptim.h.

#define LPTIM_OP_PAD_PB9 LPTIM_OR_OR_1

Definition at line 328 of file stm32f4xx_hal_lptim.h.

#define LPTIM_OP_TIM_DAC LPTIM_OR_OR

Definition at line 329 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable/Disable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Starts the LPTIM peripheral in Continuous or in single mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Writes the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Writes the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Checks whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified LPTIM interrupt is set or not.
#define | __HAL_LPTIM_OPTR_CONFIG(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->OR = (__VALUE__))
LPTIM Option Register.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the LPTIM Wake-up Timer associated Exti line flag.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Writes the passed parameter in the Autoreload register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__ : Autoreload value
Return values:
None

Definition at line 373 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clears the specified LPTIM flag.

Parameters:
__HANDLE__,: LPTIM handle.
__FLAG__ : LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None.

Definition at line 413 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Writes the passed parameter in the Compare register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__ : Compare value
Return values:
None

Definition at line 381 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))

Definition at line 356 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.

Definition at line 445 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable/Disable the LPTIM peripheral.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 355 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.

Definition at line 429 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Checks whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__,: LPTIM handle
__FLAG__ : LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 397 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks whether the specified LPTIM interrupt is set or not.

Parameters:
__HANDLE__ : LPTIM handle.
__INTERRUPT__ : LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 462 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_OPTR_CONFIG | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->OR = (__VALUE__))

LPTIM Option Register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__,: This parameter can be a value of :
  • LPTIM_OP_PAD_AF
  • LPTIM_OP_PAD_PA4
  • LPTIM_OP_PAD_PB9
  • LPTIM_OP_TIM_DAC
Return values:
None

Definition at line 473 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)

Reset LPTIM handle state.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 348 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Starts the LPTIM peripheral in Continuous or in single mode.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 363 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Definition at line 364 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the LPTIM Wake-up Timer associated Exti line flag.

Return values:
None.

Definition at line 550 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 497 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 509 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the LPTIM Wake-up Timer associated Exti line.

Return values:
None

Definition at line 485 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 521 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
                                                                      __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
                                                                     }while(0)

Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 536 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 491 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 503 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the LPTIM Wake-up Timer associated Exti line.

Return values:
None

Definition at line 479 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 515 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
                                                                     __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
                                                                    }while(0)

Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 527 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 556 of file stm32f4xx_hal_lptim.h.

#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 544 of file stm32f4xx_hal_lptim.h.

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STM32F410Rx HAL User Manual: LPTIM Private Variables

LPTIM Private Variables
LPTIM
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Private Constants

LPTIM Private Constants
LPTIM
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
#define | IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
#define | IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)

Define Documentation

#define IS_LPTIM_AUTORELOAD ( __AUTORELOAD__ ) ((__AUTORELOAD__) <= 0x0000FFFFU)

Definition at line 727 of file stm32f4xx_hal_lptim.h.

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 700 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 682 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 690 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 695 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                     ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 679 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFFU)

Definition at line 729 of file stm32f4xx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                     ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 724 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLAR__ )
Value:
(((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 712 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                     ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 692 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( PERIOD ) ((PERIOD) <= 0x0000FFFFU)

Definition at line 731 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( PULSE ) ((PULSE) <= 0x0000FFFFU)

Definition at line 733 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_5))

Definition at line 704 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 716 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                     ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 721 of file stm32f4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

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STM32F410Rx HAL User Manual: LPTIM Private Functions

LPTIM Private Functions
LPTIM
Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LPTIM Private Functions Prototypes

LPTIM Private Functions Prototypes
LPTIM
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LTDC

LTDC
STM32F4xx_HAL_Driver

LTDC HAL module driver. More...

LTDC HAL module driver.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and Configuration functions

Initialization and Configuration functions
LTDC Extended Exported Functions

Initialization and Configuration functions. More...

Initialization and Configuration functions.

 ===============================================================================
                ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the LTDC
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STM32F410Rx HAL User Manual: NOR

NOR
STM32F4xx_HAL_Driver

NOR driver modules. More...

NOR driver modules.

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STM32F410Rx HAL User Manual: PCD

PCD
STM32F4xx_HAL_Driver

PCD HAL module driver. More...

PCD HAL module driver.

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PCDEx

PCDEx
STM32F4xx_HAL_Driver

PCD Extended HAL module driver. More...

PCD Extended HAL module driver.

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STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Initialization and de-initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      After reset, the backup domain (RTC registers, RTC backup data
      registers and backup SRAM) is protected against possible unwanted
      write accesses.
      To enable access to the RTC Domain and RTC registers, proceed as follows:
        (+) Enable the Power Controller (PWR) APB1 interface clock using the
            __HAL_RCC_PWR_CLK_ENABLE() macro.
        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitializes the HAL PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 110 of file stm32f4xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

void HAL_PWR_DisableBkUpAccess ( void )

Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 135 of file stm32f4xx_hal_pwr.c.

References CR_DBP_BB.

void HAL_PWR_EnableBkUpAccess ( void )

Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note:
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 123 of file stm32f4xx_hal_pwr.c.

References CR_DBP_BB.

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STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the Wake-up PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the Wake-up PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** Wake-up pin configuration ***
    ================================
    [..]
      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
          forced in input pull-down configuration and is active on rising edges.
      (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
         (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
         (++) For STM32F410xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01

    *** Low Power modes configuration ***
    =====================================
    [..]
      The devices feature 3 low-power modes:
      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
      (+) Stop mode: all clocks are stopped, regulator running, regulator
          in low power mode
      (+) Standby mode: 1.2V domain powered off.

   *** Sleep mode ***
   ==================
    [..]
      (+) Entry:
        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
              functions with
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      -@@- The Regulator parameter is not used for the STM32F4 family
              and is kept as parameter just to maintain compatibility with the
              lower power families (STM32L).
      (+) Exit:
        Any peripheral interrupt acknowledged by the nested vectored interrupt
              controller (NVIC) can wake up the device from Sleep mode.

   *** Stop mode ***
   =================
    [..]
      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
      and the HSE RC oscillators are disabled. Internal SRAM and register contents
      are preserved.
      The voltage regulator can be configured either in normal or low-power mode.
      To minimize the consumption In Stop mode, FLASH can be powered off before
      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
      It can be switched on again by software after exiting the Stop mode using
      the HAL_PWREx_DisableFlashPowerDown() function.

      (+) Entry:
         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
             function with:
          (++) Main regulator ON.
          (++) Low Power regulator ON.
      (+) Exit:
        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.

   *** Standby mode ***
   ====================
    [..]
    (+)
      The Standby mode allows to achieve the lowest power consumption. It is based
      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
      the HSE oscillator are also switched off. SRAM and register contents are lost
      except for the RTC registers, RTC backup registers, backup SRAM and Standby
      circuitry.

      The voltage regulator is OFF.

      (++) Entry:
        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
      (++) Exit:
        (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.

   *** Auto-wake-up (AWU) from low-power mode ***
   =============================================
    [..]

     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wake-up event, a tamper event or a time-stamp event, without depending on
      an external interrupt (Auto-wake-up mode).

      (+) RTC auto-wake-up (AWU) from the Stop and Standby modes

        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
             is necessary to configure the RTC to detect the tamper or time stamp event using the
                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.

        (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
              configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.

Function Documentation

void HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
sConfigPVD,: pointer to an PWR_PVDTypeDef structure that contains the configuration information for the PVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
Return values:
None

Definition at line 270 of file stm32f4xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 322 of file stm32f4xx_hal_pwr.c.

References CR_PVDE_BB.

void HAL_PWR_DisableSEVOnPend ( void )

Disables CORTEX M4 SEVONPEND bit.

Note:
Clears SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 554 of file stm32f4xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 530 of file stm32f4xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disables the Wake-up PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1
  • PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
  • PWR_WAKEUP_PIN3 available only on STM32F410xx devices
Return values:
None

Definition at line 354 of file stm32f4xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 313 of file stm32f4xx_hal_pwr.c.

References CR_PVDE_BB.

void HAL_PWR_EnableSEVOnPend ( void )

Enables CORTEX M4 SEVONPEND bit.

Note:
Sets SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 542 of file stm32f4xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 518 of file stm32f4xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinx )

Enables the Wake-up PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to enable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1
  • PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
  • PWR_WAKEUP_PIN3 available only on STM32F410xx devices
Return values:
None

Definition at line 336 of file stm32f4xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enters Sleep mode.

Note:
In Sleep mode, all I/O pins keep the same state as in Run mode.
In Sleep mode, the systick is stopped to avoid exit from this mode with systick interrupt when used as time base for Timeout
Parameters:
Regulator,: Specifies the regulator state in SLEEP mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
Note:
This parameter is not used for the STM32F4 family and is kept as parameter just to maintain compatibility with the lower power families.
Parameters:
SLEEPEntry,: Specifies if SLEEP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  • PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
Return values:
None

Definition at line 383 of file stm32f4xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enters Standby mode.

Note:
In Standby mode, all I/O pins are high impedance except for:
  • Reset pad (still available)
  • RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC Alarm out, or RTC clock calibration out.
  • RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
  • WKUP pin 1 (PA0) if enabled.
Return values:
None

Definition at line 465 of file stm32f4xx_hal_pwr.c.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enters Stop mode.

Note:
In Stop mode, all I/O pins keep the same state as in Run mode.
When exiting Stop mode by issuing an interrupt or a wake-up event, the HSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
Regulator,: Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
STOPEntry,: Specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
Return values:
None

Definition at line 426 of file stm32f4xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

void HAL_PWR_PVD_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_IRQHandler().
Return values:
None

Definition at line 486 of file stm32f4xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, and HAL_PWR_PVDCallback().

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 503 of file stm32f4xx_hal_pwr.c.

Referenced by HAL_PWR_PVD_IRQHandler().

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STM32F410Rx HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32f4xx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 66 of file stm32f4xx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD Mode

Definition at line 71 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of PWR PVD detection level

Definition at line 68 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_pwr.h
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STM32F410Rx HAL User Manual: PWR WakeUp Pins

Defines
PWR WakeUp Pins
PWR Exported Constants

Defines

#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100U)

Define Documentation

#define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100U)

Definition at line 87 of file stm32f4xx_hal_pwr.h.

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STM32F410Rx HAL User Manual: PWR PVD detection level

Defines
PWR PVD detection level
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define | PWR_PVDLEVEL_7

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0

Definition at line 95 of file stm32f4xx_hal_pwr.h.

#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1

Definition at line 96 of file stm32f4xx_hal_pwr.h.

#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2

Definition at line 97 of file stm32f4xx_hal_pwr.h.

#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3

Definition at line 98 of file stm32f4xx_hal_pwr.h.

#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4

Definition at line 99 of file stm32f4xx_hal_pwr.h.

#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5

Definition at line 100 of file stm32f4xx_hal_pwr.h.

#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6

Definition at line 101 of file stm32f4xx_hal_pwr.h.

#define PWR_PVDLEVEL_7
Value:
PWR_CR_PLS_LEV7/* External input analog voltage
                                                          (Compare internally to VREFINT) */

Definition at line 102 of file stm32f4xx_hal_pwr.h.

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STM32F410Rx HAL User Manual: PWR PVD Mode

Defines
PWR PVD Mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)

Event Mode with Falling edge trigger detection

Definition at line 115 of file stm32f4xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)

Event Mode with Rising edge trigger detection

Definition at line 114 of file stm32f4xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)

Event Mode with Rising/Falling edge trigger detection

Definition at line 116 of file stm32f4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U)

External Interrupt Mode with Falling edge trigger detection

Definition at line 112 of file stm32f4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U)

External Interrupt Mode with Rising edge trigger detection

Definition at line 111 of file stm32f4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 113 of file stm32f4xx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U)

basic mode is used

Definition at line 110 of file stm32f4xx_hal_pwr.h.

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STM32F410Rx HAL User Manual: PWR Regulator state in SLEEP/STOP mode

Defines
PWR Regulator state in SLEEP/STOP mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS

Definition at line 126 of file stm32f4xx_hal_pwr.h.

#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)

Definition at line 125 of file stm32f4xx_hal_pwr.h.

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STM32F410Rx HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)

Definition at line 135 of file stm32f4xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)

Definition at line 134 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

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STM32F410Rx HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02U)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)

Definition at line 144 of file stm32f4xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)

Definition at line 143 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

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STM32F410Rx HAL User Manual: PWR Flag

Defines
PWR Flag
PWR Exported Constants

Defines

#define | PWR_FLAG_WU PWR_CSR_WUF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_PVDO PWR_CSR_PVDO
#define | PWR_FLAG_BRR PWR_CSR_BRR
#define | PWR_FLAG_VOSRDY PWR_CSR_VOSRDY

Define Documentation

#define PWR_FLAG_BRR PWR_CSR_BRR

Definition at line 155 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define PWR_FLAG_PVDO PWR_CSR_PVDO

Definition at line 154 of file stm32f4xx_hal_pwr.h.

#define PWR_FLAG_SB PWR_CSR_SBF

Definition at line 153 of file stm32f4xx_hal_pwr.h.

#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY

Definition at line 156 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define PWR_FLAG_WU PWR_CSR_WUF

Definition at line 152 of file stm32f4xx_hal_pwr.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWR Exported Macro

Defines
PWR Exported Macro
PWR

Defines

#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
Clear the PWR's pending flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Enable the PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
checks whether the specified PVD Exti interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD Exti flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Generates a Software interrupt on PVD EXTI line.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ ) (PWR->CR |= (__FLAG__) << 2U)

Clear the PWR's pending flags.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag

Definition at line 199 of file stm32f4xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ ) ((PWR->CSR & (__FLAG__)) == (__FLAG__))

Check PWR flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
  • PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.
  • PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage scaling output selection is ready.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 191 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) (EXTI->PR = (PWR_EXTI_LINE_PVD))

Clear the PVD Exti flag.

Return values:
None.

Definition at line 278 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))

Disable event on PVD Exti Line 16.

Return values:
None.

Definition at line 223 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 248 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))

Disable the PVD EXTI Line 16.

Return values:
None.

Definition at line 211 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 235 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
                                                             __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
                                                            }while(0)

Disable the PVD Extended Interrupt Rising & Falling Trigger.

This parameter can be:

Return values:
None.

Definition at line 264 of file stm32f4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= (PWR_EXTI_LINE_PVD))

Enable event on PVD Exti Line 16.

Return values:
None.

Definition at line 217 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 241 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) (EXTI->IMR |= (PWR_EXTI_LINE_PVD))

Enable the PVD Exti Line 16.

Return values:
None.

Definition at line 205 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 229 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
                                                             __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
                                                            }while(0)

PVD EXTI line configuration: set rising & falling edge trigger.

Return values:
None.

Definition at line 255 of file stm32f4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))

Generates a Software interrupt on PVD EXTI line.

Return values:
None

Definition at line 284 of file stm32f4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) (EXTI->PR & (PWR_EXTI_LINE_PVD))

checks whether the specified PVD Exti interrupt flag is set or not.

Return values:
EXTI PVD Line Status.

Definition at line 272 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Constants

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000U)
#define | PVD_MODE_EVT ((uint32_t)0x00020000U)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002U)

Define Documentation

#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)

Definition at line 69 of file stm32f4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT ((uint32_t)0x00020000U)

Definition at line 67 of file stm32f4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT ((uint32_t)0x00010000U)

Definition at line 66 of file stm32f4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE ((uint32_t)0x00000001U)

Definition at line 68 of file stm32f4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

Generated on Fri Jan 29 2016 15:36:55 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWR PVD EXTI Line

Defines
PWR PVD EXTI Line
PWR Private Constants

Defines

#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)

Define Documentation

#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)

External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 355 of file stm32f4xx_hal_pwr.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWR Register alias address

Defines
PWR Register alias address
PWR Private Constants

Defines

#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define | PWR_CR_OFFSET 0x00U
#define | PWR_CSR_OFFSET 0x04U
#define | PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define | PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)

Define Documentation

#define PWR_CR_OFFSET 0x00U

Definition at line 365 of file stm32f4xx_hal_pwr.h.

#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)

Definition at line 367 of file stm32f4xx_hal_pwr.h.

#define PWR_CSR_OFFSET 0x04U

Definition at line 366 of file stm32f4xx_hal_pwr.h.

#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)

Definition at line 368 of file stm32f4xx_hal_pwr.h.

#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)

Definition at line 364 of file stm32f4xx_hal_pwr.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWR CR Register alias address

Defines
PWR CR Register alias address
PWR Private Constants

Defines

#define | DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
#define | CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
#define | PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
#define | CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
#define | PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
#define | CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))

Define Documentation

#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))

Definition at line 379 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_DisableBkUpAccess(), and HAL_PWR_EnableBkUpAccess().

#define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))

Definition at line 387 of file stm32f4xx_hal_pwr.h.

#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))

Definition at line 383 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_DisablePVD(), and HAL_PWR_EnablePVD().

#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)

Definition at line 378 of file stm32f4xx_hal_pwr.h.

#define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)

Definition at line 386 of file stm32f4xx_hal_pwr.h.

#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)

Definition at line 382 of file stm32f4xx_hal_pwr.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWR CSR Register alias address

Defines
PWR CSR Register alias address
PWR Private Constants

Defines

#define | EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
#define | CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))

Define Documentation

#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))

Definition at line 398 of file stm32f4xx_hal_pwr.h.

#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)

Definition at line 397 of file stm32f4xx_hal_pwr.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWR Private macros to check input parameters

Defines
PWR Private macros to check input parameters
PWR Private Macros

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 414 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_NORMAL))

Definition at line 418 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 422 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWR_EnterSTOPMode().

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 424 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 425 of file stm32f4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Extended features functions

Functions
Peripheral Extended features functions
PWREx Exported Functions

Peripheral Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enables the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disables the Backup Regulator.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enables the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disables the Flash Power Down in Stop mode.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configures the main internal regulator output voltage.
void | HAL_PWREx_EnableMainRegulatorLowVoltage (void)
Enables Main Regulator low voltage mode.
void | HAL_PWREx_DisableMainRegulatorLowVoltage (void)
Disables Main Regulator low voltage mode.
void | HAL_PWREx_EnableLowRegulatorLowVoltage (void)
Enables Low Power Regulator low voltage mode.
void | HAL_PWREx_DisableLowRegulatorLowVoltage (void)
Disables Low Power Regulator low voltage mode.

Detailed Description

Peripheral Extended features functions.

 ===============================================================================
                 ##### Peripheral extended features functions #####
 ===============================================================================

    *** Main and Backup Regulators configuration ***
    ================================================
    [..]
      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
          retained even in Standby or VBAT mode when the low power backup regulator
          is enabled. It can be considered as an internal EEPROM when VBAT is
          always present. You can use the HAL_PWREx_EnableBkUpReg() function to
          enable the low power backup regulator.

      (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
          the backup SRAM is powered from VDD which replaces the VBAT power supply to
          save battery life.

      (+) The backup SRAM is not mass erased by a tamper event. It is read
          protected to prevent confidential data, such as cryptographic private
          key, from being accessed. The backup SRAM can be erased only through
          the Flash interface when a protection level change from level 1 to
          level 0 is requested.
      -@- Refer to the description of Read protection (RDP) in the Flash
          programming manual.

      (+) The main internal regulator can be configured to have a tradeoff between
          performance and power consumption when the device does not operate at
          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
          macro which configure VOS bit in PWR_CR register

        Refer to the product datasheets for more details.

    *** FLASH Power Down configuration ****
    =======================================
    [..]
      (+) By setting the FPDS bit in the PWR_CR register by using the
          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
          down mode when the device enters Stop mode. When the Flash memory
          is in power down mode, an additional startup delay is incurred when
          waking up from Stop mode.

           (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
           is OFF and the HSI or HSE clock source is selected as system clock.
           The new value programmed is active only when the PLL is ON.
           When the PLL is OFF, the voltage scale 3 is automatically selected.
        Refer to the datasheets for more details.

    *** Over-Drive and Under-Drive configuration ****
    =================================================
    [..]
       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
           2 operating modes available:
        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
             voltage scaling (scale 1, scale 2 or scale 3)
        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
            higher frequency than the normal mode for a given voltage scaling (scale 1,
            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
            the sequence described in Reference manual.

       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
           and internal SRAM. 2 operating modes are available:
         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
              available when the main regulator or the low power regulator is used in Scale 3 or
              low voltage mode.
         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
              available when the main regulator or the low power regulator is in low voltage mode.

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configures the main internal regulator output voltage.

Parameters:
VoltageScaling,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, the maximum value of fHCLK is 168 MHz. It can be extended to 180 MHz by activating the over-drive mode.
  • PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, the maximum value of fHCLK is 144 MHz. It can be extended to, 168 MHz by activating the over-drive mode.
  • PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, the maximum value of fHCLK is 120 MHz.
Note:
To update the system clock frequency(SYSCLK):
  • Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
  • Call the HAL_RCC_OscConfig() to configure the PLL.
  • Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
  • Set the new system clock frequency using the HAL_RCC_ClockConfig().
The scale can be modified only when the HSI or HSE clock source is selected as system clock source, otherwise the API returns HAL_ERROR.
When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits value in the PWR_CR1 register are not taken in account.
This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
The new voltage scale is active only when the PLL is ON.
Return values:
HAL Status

Definition at line 307 of file stm32f4xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, __HAL_PWR_VOLTAGESCALING_CONFIG, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PWR_CLK_ENABLE, assert_param, HAL_GetTick(), IS_PWR_VOLTAGE_SCALING_RANGE, PLL_TIMEOUT_VALUE, PWR_FLAG_VOSRDY, PWR_VOSRDY_TIMEOUT_VALUE, and RCC_FLAG_PLLRDY.

HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg ( void )

Disables the Backup Regulator.

Return values:
HAL status

Definition at line 185 of file stm32f4xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, CSR_BRE_BB, HAL_GetTick(), PWR_BKPREG_TIMEOUT_VALUE, and PWR_FLAG_BRR.

void HAL_PWREx_DisableFlashPowerDown ( void )

Disables the Flash Power Down in Stop mode.

Return values:
None

Definition at line 218 of file stm32f4xx_hal_pwr_ex.c.

References CR_FPDS_BB.

void HAL_PWREx_DisableLowRegulatorLowVoltage ( void )

Disables Low Power Regulator low voltage mode.

Note:
This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
Return values:
None

Definition at line 426 of file stm32f4xx_hal_pwr_ex.c.

References CR_LPLVDS_BB.

void HAL_PWREx_DisableMainRegulatorLowVoltage ( void )

Disables Main Regulator low voltage mode.

Note:
This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
Return values:
None

Definition at line 406 of file stm32f4xx_hal_pwr_ex.c.

References CR_MRLVDS_BB.

HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg ( void )

Enables the Backup Regulator.

Return values:
HAL status

Definition at line 161 of file stm32f4xx_hal_pwr_ex.c.

References __HAL_PWR_GET_FLAG, CSR_BRE_BB, HAL_GetTick(), PWR_BKPREG_TIMEOUT_VALUE, and PWR_FLAG_BRR.

void HAL_PWREx_EnableFlashPowerDown ( void )

Enables the Flash Power Down in Stop mode.

Return values:
None

Definition at line 209 of file stm32f4xx_hal_pwr_ex.c.

References CR_FPDS_BB.

void HAL_PWREx_EnableLowRegulatorLowVoltage ( void )

Enables Low Power Regulator low voltage mode.

Note:
This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
Return values:
None

Definition at line 416 of file stm32f4xx_hal_pwr_ex.c.

References CR_LPLVDS_BB.

void HAL_PWREx_EnableMainRegulatorLowVoltage ( void )

Enables Main Regulator low voltage mode.

Note:
This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
Return values:
None

Definition at line 396 of file stm32f4xx_hal_pwr_ex.c.

References CR_MRLVDS_BB.

uint32_t HAL_PWREx_GetVoltageRange ( void )

Return Voltage Scaling Range.

Return values:
The configured scale for the regulator voltage(VOS bit field). The returned value can be one of the following:
    • PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
    • PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
    • PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode

Definition at line 231 of file stm32f4xx_hal_pwr_ex.c.

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STM32F410Rx HAL User Manual: PWREx Regulator Voltage Scale

Defines
PWREx Regulator Voltage Scale
PWREx Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1
#define | PWR_REGULATOR_VOLTAGE_SCALE2
#define | PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE1
Value:
PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
                                                                       180 MHz by activating the over-drive mode. */

Definition at line 92 of file stm32f4xx_hal_pwr_ex.h.

#define PWR_REGULATOR_VOLTAGE_SCALE2
Value:
PWR_CR_VOS_1           /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
                                                                       168 MHz by activating the over-drive mode. */

Definition at line 93 of file stm32f4xx_hal_pwr_ex.h.

#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */

Definition at line 94 of file stm32f4xx_hal_pwr_ex.h.

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STM32F410Rx HAL User Manual: PWREx WakeUp Pins

Defines
PWREx WakeUp Pins
PWREx Exported Constants

Defines

#define | PWR_WAKEUP_PIN2 ((uint32_t)0x00000080U)
#define | PWR_WAKEUP_PIN3 ((uint32_t)0x00000040U)

Define Documentation

#define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080U)

Definition at line 103 of file stm32f4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3 ((uint32_t)0x00000040U)

Definition at line 105 of file stm32f4xx_hal_pwr_ex.h.

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STM32F410Rx HAL User Manual: PWREx Exported Constants

Modules | Defines
PWREx Exported Constants
PWREx

Modules

PWREx Regulator Voltage Scale
PWREx WakeUp Pins

Defines

#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
macros configure the main internal regulator output voltage.

Define Documentation

#define __HAL_PWR_VOLTAGESCALING_CONFIG ( __REGULATOR__ )
Value:
do {                                                     \
                                                            __IO uint32_t tmpreg = 0x00U;                        \
                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
                                                            /* Delay after an RCC peripheral clock enabling */  \
                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
                                                            UNUSED(tmpreg);                                     \
                                                          } while(0)

macros configure the main internal regulator output voltage.

Parameters:
__REGULATOR__,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheets for more details). This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
  • PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
  • PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
Return values:
None

Definition at line 149 of file stm32f4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWREx Register alias address

Defines
PWREx Register alias address
PWREx Private Constants

Defines

#define | FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
#define | CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
#define | ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
#define | CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
#define | ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
#define | CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
#define | MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
#define | CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
#define | LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
#define | CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))

Define Documentation

#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))

Definition at line 265 of file stm32f4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableFlashPowerDown(), and HAL_PWREx_EnableFlashPowerDown().

#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))

Definition at line 281 of file stm32f4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableLowRegulatorLowVoltage(), and HAL_PWREx_EnableLowRegulatorLowVoltage().

#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))

Definition at line 277 of file stm32f4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableMainRegulatorLowVoltage(), and HAL_PWREx_EnableMainRegulatorLowVoltage().

#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))

Definition at line 269 of file stm32f4xx_hal_pwr_ex.h.

#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))

Definition at line 273 of file stm32f4xx_hal_pwr_ex.h.

#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)

Definition at line 264 of file stm32f4xx_hal_pwr_ex.h.

#define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)

Definition at line 280 of file stm32f4xx_hal_pwr_ex.h.

#define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)

Definition at line 276 of file stm32f4xx_hal_pwr_ex.h.

#define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)

Definition at line 268 of file stm32f4xx_hal_pwr_ex.h.

#define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)

Definition at line 272 of file stm32f4xx_hal_pwr_ex.h.

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STM32F410Rx HAL User Manual: PWRx CSR Register alias address

Defines
PWRx CSR Register alias address
PWREx Private Constants

Defines

#define | BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
#define | CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))

Define Documentation

#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)

Definition at line 292 of file stm32f4xx_hal_pwr_ex.h.

#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))

Definition at line 293 of file stm32f4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWREx Private Constants

Modules | Defines
PWREx Private Constants
PWREx

Modules

PWREx Register alias address
PWRx CSR Register alias address

Defines

#define | PWR_OVERDRIVE_TIMEOUT_VALUE 1000U
#define | PWR_UDERDRIVE_TIMEOUT_VALUE 1000U
#define | PWR_BKPREG_TIMEOUT_VALUE 1000U
#define | PWR_VOSRDY_TIMEOUT_VALUE 1000U

Define Documentation

#define PWR_BKPREG_TIMEOUT_VALUE 1000U

Definition at line 63 of file stm32f4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableBkUpReg(), and HAL_PWREx_EnableBkUpReg().

#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U

Definition at line 61 of file stm32f4xx_hal_pwr_ex.c.

#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U

Definition at line 62 of file stm32f4xx_hal_pwr_ex.c.

#define PWR_VOSRDY_TIMEOUT_VALUE 1000U

Definition at line 64 of file stm32f4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ControlVoltageScaling().

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STM32F410Rx HAL User Manual: PWREx Private macros to check input parameters

Defines
PWREx Private macros to check input parameters
PWREx Private Macros

Defines

#define | IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE)
#define | IS_PWR_WAKEUP_PIN(PIN)

Define Documentation

#define IS_PWR_VOLTAGE_SCALING_RANGE ( VOLTAGE )
Value:
(((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))

Definition at line 326 of file stm32f4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
                                ((PIN) == PWR_WAKEUP_PIN3))

Definition at line 334 of file stm32f4xx_hal_pwr_ex.h.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

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STM32F410Rx HAL User Manual: QSPI

QSPI
STM32F4xx_HAL_Driver

HAL QSPI module driver. More...

HAL QSPI module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC Private Variables

Variables
RCC Private Variables
RCC

Variables

const uint8_t APBAHBPrescTable [16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}

Variable Documentation

const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}

Definition at line 123 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_GetHCLKFreq(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

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STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

__weak void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
       and APB2).

    [..] Internal/external clock and PLL configuration
         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.

         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also as RTC clock source.

         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
           (++) The first output is used to generate the high speed system clock (up to 168 MHz)
           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).

         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
             and if a HSE clock failure occurs(HSE used directly or through PLL as System
             clock source), the System clocks automatically switched to HSI and an interrupt
             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
             (Non-Maskable Interrupt) exception vector.

         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
             clock (through a configurable prescaler) on PA8 pin.

         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
             clock (through a configurable prescaler) on PC9 pin.

    [..] System, AHB and APB busses clocks configuration
         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
             HSE and PLL.
             The AHB clock (HCLK) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
             from AHB clock through configurable prescalers and used to clock
             the peripherals mapped on these busses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

         (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
             the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
             PCLK2 84 MHz and PCLK1 42 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
             PCLK2 100 MHz and PCLK1 50 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency,: FLASH Latency, this parameter depend on device selected
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready.
Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 563 of file stm32f4xx_hal_rcc.c.

References __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_SYSCLK_CONFIG, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_PLLRDY, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_PLLCLK, RCC_SYSCLKSOURCE_PLLRCLK, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, RCC_SYSCLKSOURCE_STATUS_PLLCLK, RCC_SYSCLKSOURCE_STATUS_PLLRCLK, RCC_ClkInitTypeDef::SYSCLKSource, and TICK_INT_PRIORITY.

void HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE and PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 223 of file stm32f4xx_hal_rcc.c.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this API. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this API. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Return values:
HAL status

Definition at line 241 of file stm32f4xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PWR_CLK_ENABLE, assert_param, HAL_GetTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_CALIBRATION_VALUE, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_LSERDY, RCC_FLAG_LSIRDY, RCC_FLAG_PLLRDY, RCC_HSE_OFF, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_NONE, and RCC_PLL_ON.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
__weak uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
__weak void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.

Function Documentation

void HAL_RCC_CSSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
None

Definition at line 1083 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableCSS ( void )

Disables the Clock Security System.

Return values:
None

Definition at line 833 of file stm32f4xx_hal_rcc.c.

References RCC_CR_CSSON_BB.

void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
Return values:
None

Definition at line 824 of file stm32f4xx_hal_rcc.c.

References RCC_CR_CSSON_BB.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct,: pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency,: Pointer on the Flash Latency.
Return values:
None

Definition at line 1040 of file stm32f4xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 924 of file stm32f4xx_hal_rcc.c.

References APBAHBPrescTable, and HAL_RCC_GetSysClockFreq().

Referenced by HAL_InitTick(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 961 of file stm32f4xx_hal_rcc.c.

References RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 936 of file stm32f4xx_hal_rcc.c.

References APBAHBPrescTable, and HAL_RCC_GetHCLKFreq().

Referenced by HAL_I2C_Init(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK2 frequency

Definition at line 948 of file stm32f4xx_hal_rcc.c.

References APBAHBPrescTable, and HAL_RCC_GetHCLKFreq().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 868 of file stm32f4xx_hal_rcc.c.

References __HAL_RCC_GET_PLL_OSCSOURCE, HSE_VALUE, HSI_VALUE, and RCC_PLLSOURCE_HSI.

Referenced by HAL_RCC_GetHCLKFreq().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).

Note:
PA8/PC9 should be configured in alternate function mode.
Parameters:
RCC_MCOx,: specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1: Clock source to output on MCO1 pin(PA8).
  • RCC_MCO2: Clock source to output on MCO2 pin(PC9).
RCC_MCOSource,: specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
  • RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
RCC_MCODiv,: specifies the MCOx prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1: no division applied to MCOx clock
  • RCC_MCODIV_2: division by 2 applied to MCOx clock
  • RCC_MCODIV_3: division by 3 applied to MCOx clock
  • RCC_MCODIV_4: division by 4 applied to MCOx clock
  • RCC_MCODIV_5: division by 5 applied to MCOx clock
Note:
For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Return values:
None

Definition at line 758 of file stm32f4xx_hal_rcc.c.

References __HAL_RCC_MCO1_ENABLE, __HAL_RCC_MCO2_ENABLE, __MCO1_CLK_ENABLE, __MCO2_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCO2SOURCE, IS_RCC_MCODIV, MCO1_GPIO_PORT, MCO1_PIN, MCO2_GPIO_PORT, MCO2_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1066 of file stm32f4xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CSSCallback(), and RCC_IT_CSS.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...

#include <stm32f4xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.

Definition at line 69 of file stm32f4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of HSE Config

Definition at line 74 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 83 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of HSI Config

Definition at line 80 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of LSE Config

Definition at line 77 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of LSI Config

Definition at line 86 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of Oscillator Type

Definition at line 71 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

PLL structure parameters

Definition at line 89 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rcc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32f4xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 95 of file stm32f4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 103 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1/APB2 Clock Source

Definition at line 106 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1/APB2 Clock Source

Definition at line 109 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of System Clock Type

Definition at line 97 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source (SYSCLKS) used as system clock. This parameter can be a value of System Clock Source

Definition at line 100 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rcc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)

Define Documentation

#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)

Definition at line 127 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)

Definition at line 128 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)

Definition at line 129 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)

Definition at line 130 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)

Definition at line 126 of file stm32f4xx_hal_rcc.h.

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STM32F410Rx HAL User Manual: HSE Config

Defines
HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF ((uint8_t)0x00U)
#define | RCC_HSE_ON ((uint8_t)0x01U)
#define | RCC_HSE_BYPASS ((uint8_t)0x05U)

Define Documentation

#define RCC_HSE_BYPASS ((uint8_t)0x05U)

Definition at line 140 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF ((uint8_t)0x00U)

Definition at line 138 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON ((uint8_t)0x01U)

Definition at line 139 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F410Rx HAL User Manual: LSE Config

Defines
LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF ((uint8_t)0x00U)
#define | RCC_LSE_ON ((uint8_t)0x01U)
#define | RCC_LSE_BYPASS ((uint8_t)0x05U)

Define Documentation

#define RCC_LSE_BYPASS ((uint8_t)0x05U)

Definition at line 150 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF ((uint8_t)0x00U)

Definition at line 148 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON ((uint8_t)0x01U)

Definition at line 149 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F410Rx HAL User Manual: HSI Config

Defines
HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF ((uint8_t)0x00U)
#define | RCC_HSI_ON ((uint8_t)0x01U)
#define | RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */

Define Documentation

#define RCC_HSI_OFF ((uint8_t)0x00U)

Definition at line 158 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON ((uint8_t)0x01U)

Definition at line 159 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */

Definition at line 161 of file stm32f4xx_hal_rcc.h.

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STM32F410Rx HAL User Manual: LSI Config

Defines
LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF ((uint8_t)0x00U)
#define | RCC_LSI_ON ((uint8_t)0x01U)

Define Documentation

#define RCC_LSI_OFF ((uint8_t)0x00U)

Definition at line 169 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON ((uint8_t)0x01U)

Definition at line 170 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F410Rx HAL User Manual: PLL Config

Defines
PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE ((uint8_t)0x00U)
#define | RCC_PLL_OFF ((uint8_t)0x01U)
#define | RCC_PLL_ON ((uint8_t)0x02U)

Define Documentation

#define RCC_PLL_NONE ((uint8_t)0x00U)

Definition at line 178 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF ((uint8_t)0x01U)

Definition at line 179 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_PLL_ON ((uint8_t)0x02U)

Definition at line 180 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

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STM32F410Rx HAL User Manual: PLLP Clock Divider

Defines
PLLP Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
#define | RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
#define | RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
#define | RCC_PLLP_DIV8 ((uint32_t)0x00000008U)

Define Documentation

#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)

Definition at line 188 of file stm32f4xx_hal_rcc.h.

#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)

Definition at line 189 of file stm32f4xx_hal_rcc.h.

#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)

Definition at line 190 of file stm32f4xx_hal_rcc.h.

#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)

Definition at line 191 of file stm32f4xx_hal_rcc.h.

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STM32F410Rx HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Definition at line 200 of file stm32f4xx_hal_rcc.h.

Referenced by I2S_GetInputClock().

#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

Definition at line 199 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq().

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STM32F410Rx HAL User Manual: System Clock Type

Defines
System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)

Define Documentation

#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)

Definition at line 209 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)

Definition at line 210 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)

Definition at line 211 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)

Definition at line 208 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

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STM32F410Rx HAL User Manual: System Clock Source

Defines
System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
#define | RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))

Define Documentation

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

Definition at line 220 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

Definition at line 219 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

Definition at line 221 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))

Definition at line 222 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

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STM32F410Rx HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
#define | RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 231 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 230 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 232 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))

PLLR used as system clock

Definition at line 233 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB Clock Source

Defines
AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

Definition at line 241 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

Definition at line 247 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

Definition at line 245 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

Definition at line 242 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

Definition at line 248 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

Definition at line 243 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Definition at line 249 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

Definition at line 246 of file stm32f4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

Definition at line 244 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1/APB2 Clock Source

Defines
APB1/APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

Definition at line 257 of file stm32f4xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Definition at line 261 of file stm32f4xx_hal_rcc.h.

#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

Definition at line 258 of file stm32f4xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

Definition at line 259 of file stm32f4xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

Definition at line 260 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Clock Source

Defines
RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define | RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)

Definition at line 279 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)

Definition at line 280 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)

Definition at line 281 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)

Definition at line 282 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)

Definition at line 283 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)

Definition at line 284 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)

Definition at line 285 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)

Definition at line 286 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)

Definition at line 287 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)

Definition at line 288 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)

Definition at line 271 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)

Definition at line 289 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)

Definition at line 290 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)

Definition at line 291 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)

Definition at line 292 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)

Definition at line 293 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)

Definition at line 294 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)

Definition at line 295 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)

Definition at line 296 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)

Definition at line 297 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)

Definition at line 298 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)

Definition at line 272 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)

Definition at line 299 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)

Definition at line 300 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)

Definition at line 273 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)

Definition at line 274 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)

Definition at line 275 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)

Definition at line 276 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)

Definition at line 277 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)

Definition at line 278 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)

Definition at line 269 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)

Definition at line 270 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: MCO Index

Defines
MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 ((uint32_t)0x00000000U)
#define | RCC_MCO2 ((uint32_t)0x00000001U)

Define Documentation

#define RCC_MCO1 ((uint32_t)0x00000000U)

Definition at line 308 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO2 ((uint32_t)0x00000001U)

Definition at line 309 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: MCO1 Clock Source

Defines
MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1

Definition at line 319 of file stm32f4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)

Definition at line 317 of file stm32f4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0

Definition at line 318 of file stm32f4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1

Definition at line 320 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: MCOx Clock Prescaler

Defines
MCOx Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 ((uint32_t)0x00000000U)
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_5 RCC_CFGR_MCO1PRE

Define Documentation

#define RCC_MCODIV_1 ((uint32_t)0x00000000U)

Definition at line 328 of file stm32f4xx_hal_rcc.h.

#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2

Definition at line 329 of file stm32f4xx_hal_rcc.h.

#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

Definition at line 330 of file stm32f4xx_hal_rcc.h.

#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

Definition at line 331 of file stm32f4xx_hal_rcc.h.

#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE

Definition at line 332 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Interrupts

Defines
Interrupts
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY ((uint8_t)0x01U)
#define | RCC_IT_LSERDY ((uint8_t)0x02U)
#define | RCC_IT_HSIRDY ((uint8_t)0x04U)
#define | RCC_IT_HSERDY ((uint8_t)0x08U)
#define | RCC_IT_PLLRDY ((uint8_t)0x10U)
#define | RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
#define | RCC_IT_CSS ((uint8_t)0x80U)

Define Documentation

#define RCC_IT_CSS ((uint8_t)0x80U)

Definition at line 346 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY ((uint8_t)0x08U)

Definition at line 343 of file stm32f4xx_hal_rcc.h.

#define RCC_IT_HSIRDY ((uint8_t)0x04U)

Definition at line 342 of file stm32f4xx_hal_rcc.h.

#define RCC_IT_LSERDY ((uint8_t)0x02U)

Definition at line 341 of file stm32f4xx_hal_rcc.h.

#define RCC_IT_LSIRDY ((uint8_t)0x01U)

Definition at line 340 of file stm32f4xx_hal_rcc.h.

#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)

Definition at line 345 of file stm32f4xx_hal_rcc.h.

#define RCC_IT_PLLRDY ((uint8_t)0x10U)

Definition at line 344 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Flags

Defines
Flags
RCC Exported Constants

Elements values convention: 0XXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((uint8_t)0x21U)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31U)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39U)
#define | RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41U)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61U)
#define | RCC_FLAG_BORRST ((uint8_t)0x79U)
#define | RCC_FLAG_PINRST ((uint8_t)0x7AU)
#define | RCC_FLAG_PORRST ((uint8_t)0x7BU)
#define | RCC_FLAG_SFTRST ((uint8_t)0x7CU)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x7FU)

Detailed Description

Elements values convention: 0XXYYYYYb.

  • YYYYY : Flag position in the register
  • 0XX : Register index
    • 01: CR register
    • 10: BDCR register
    • 11: CSR register

Define Documentation

#define RCC_FLAG_BORRST ((uint8_t)0x79U)

Definition at line 371 of file stm32f4xx_hal_rcc.h.

#define RCC_FLAG_HSERDY ((uint8_t)0x31U)

Definition at line 362 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)

Definition at line 361 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)

Definition at line 375 of file stm32f4xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)

Definition at line 377 of file stm32f4xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)0x41U)

Definition at line 367 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)

Definition at line 370 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_PINRST ((uint8_t)0x7AU)

Definition at line 372 of file stm32f4xx_hal_rcc.h.

#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)

Definition at line 364 of file stm32f4xx_hal_rcc.h.

#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)

Definition at line 363 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_PORRST ((uint8_t)0x7BU)

Definition at line 373 of file stm32f4xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)

Definition at line 374 of file stm32f4xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)

Definition at line 376 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Peripheral Clock Enable Disable

Defines
AHB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))

Definition at line 445 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                         } while(0)

Definition at line 426 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Definition at line 446 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 433 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

Definition at line 441 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 398 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

Definition at line 442 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 405 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

Definition at line 443 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 412 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

Definition at line 444 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        UNUSED(tmpreg); \
                                         } while(0)

Definition at line 419 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Peripheral Clock Enable Disable Status

Defines
AHB1 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)

Definition at line 469 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)

Definition at line 462 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)

Definition at line 470 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)

Definition at line 463 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)

Definition at line 465 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)

Definition at line 458 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)

Definition at line 466 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)

Definition at line 459 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)

Definition at line 467 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)

Definition at line 460 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)

Definition at line 468 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)

Definition at line 461 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Peripheral Clock Enable Disable

Defines
APB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines

#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 536 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 510 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 537 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 517 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 538 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 524 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_FLASHEx_DisableFlashSleepMode(), HAL_FLASHEx_EnableFlashSleepMode(), HAL_FLASHEx_StartFlashInterfaceClk(), HAL_FLASHEx_StopFlashInterfaceClk(), HAL_PWREx_ControlVoltageScaling(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 534 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 496 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 532 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 482 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 535 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 503 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 533 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 489 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Peripheral Clock Enable Disable Status

Defines
APB1 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

Definition at line 562 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

Definition at line 554 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)

Definition at line 563 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)

Definition at line 555 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

Definition at line 564 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)

Definition at line 556 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)

Definition at line 560 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)

Definition at line 552 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)

Definition at line 558 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)

Definition at line 550 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

Definition at line 561 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

Definition at line 553 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)

Definition at line 559 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)

Definition at line 551 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Peripheral Clock Enable Disable

Defines
APB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM9_CLK_ENABLE()
#define | __HAL_RCC_TIM11_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define | __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
#define | __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 636 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 597 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 637 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 604 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 638 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 611 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_FMPI2CEx_DisableFastModePlus(), HAL_FMPI2CEx_EnableFastModePlus(), and HAL_GPIO_Init().

#define __HAL_RCC_TIM11_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 640 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 625 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 633 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 576 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 639 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 618 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 634 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 583 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 635 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        UNUSED(tmpreg); \
                                          } while(0)

Definition at line 590 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Peripheral Clock Enable Disable Status

Defines
APB2 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define | __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
#define | __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
#define | __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
#define | __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)

Detailed Description

Get the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)

Definition at line 664 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_ADC1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)

Definition at line 655 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)

Definition at line 665 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)

Definition at line 656 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)

Definition at line 666 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)

Definition at line 657 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM11_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)

Definition at line 668 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM11_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)

Definition at line 659 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)

Definition at line 661 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)

Definition at line 652 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)

Definition at line 667 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)

Definition at line 658 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

Definition at line 662 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)

Definition at line 653 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)

Definition at line 663 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)

Definition at line 654 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Force Release Reset

Defines
AHB1 Force Release Reset
RCC Exported Macros

Force or release AHB1 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))

Detailed Description

Force or release AHB1 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB1_FORCE_RESET ( ) (RCC->AHB1RSTR = 0xFFFFFFFFU)

Definition at line 677 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB1_RELEASE_RESET ( ) (RCC->AHB1RSTR = 0x00U)

Definition at line 685 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_DMA1_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))

Definition at line 682 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))

Definition at line 690 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))

Definition at line 683 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))

Definition at line 691 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))

Definition at line 678 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))

Definition at line 686 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))

Definition at line 679 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))

Definition at line 687 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))

Definition at line 680 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))

Definition at line 688 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))

Definition at line 681 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))

Definition at line 689 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Force Release Reset

Defines
APB1 Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( ) (RCC->APB1RSTR = 0xFFFFFFFFU)

Definition at line 700 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( ) (RCC->APB1RSTR = 0x00U)

Definition at line 709 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_I2C1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))

Definition at line 705 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))

Definition at line 714 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))

Definition at line 706 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))

Definition at line 715 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))

Definition at line 707 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_PWR_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

Definition at line 716 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_SPI2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))

Definition at line 703 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))

Definition at line 712 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))

Definition at line 701 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))

Definition at line 710 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))

Definition at line 704 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))

Definition at line 713 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))

Definition at line 702 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))

Definition at line 711 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Force Release Reset

Defines
APB2 Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))

Definition at line 729 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_ADC_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))

Definition at line 739 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_APB2_FORCE_RESET ( ) (RCC->APB2RSTR = 0xFFFFFFFFU)

Definition at line 725 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) (RCC->APB2RSTR = 0x00U)

Definition at line 735 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_SPI1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))

Definition at line 730 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))

Definition at line 740 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))

Definition at line 731 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))

Definition at line 741 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM11_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))

Definition at line 733 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM11_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))

Definition at line 743 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))

Definition at line 726 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))

Definition at line 736 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))

Definition at line 732 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))

Definition at line 742 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))

Definition at line 727 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

Definition at line 737 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))

Definition at line 728 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))

Definition at line 738 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Peripheral Low Power Enable Disable

Defines
AHB1 Peripheral Low Power Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))

Detailed Description

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wake-up from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))

Definition at line 767 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

Definition at line 760 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))

Definition at line 768 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

Definition at line 761 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))

Definition at line 763 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))

Definition at line 756 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))

Definition at line 764 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))

Definition at line 757 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))

Definition at line 765 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))

Definition at line 758 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))

Definition at line 766 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))

Definition at line 759 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Peripheral Low Power Enable Disable

Defines
APB1 Peripheral Low Power Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))

Detailed Description

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wake-up from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))

Definition at line 793 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))

Definition at line 785 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))

Definition at line 794 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))

Definition at line 786 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))

Definition at line 795 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))

Definition at line 787 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))

Definition at line 791 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))

Definition at line 783 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))

Definition at line 789 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))

Definition at line 781 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))

Definition at line 792 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))

Definition at line 784 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))

Definition at line 790 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))

Definition at line 782 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Peripheral Low Power Enable Disable

Defines
APB2 Peripheral Low Power Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))

Detailed Description

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wake-up from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))

Definition at line 820 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))

Definition at line 811 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))

Definition at line 821 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))

Definition at line 812 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))

Definition at line 822 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))

Definition at line 813 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))

Definition at line 824 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))

Definition at line 815 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))

Definition at line 817 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))

Definition at line 808 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))

Definition at line 823 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))

Definition at line 814 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))

Definition at line 818 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))

Definition at line 809 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))

Definition at line 819 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))

Definition at line 810 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: HSI Configuration

Defines
HSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Define Documentation

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICalibrationValue__ )
Value:
(MODIFY_REG(RCC->CR,\
        RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICalibrationValue__,: specifies the calibration trimming value. (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 0x1F.

Definition at line 858 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)

Definition at line 849 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)

Macros to enable or disable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 848 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LSI Configuration

Defines
LSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)

Define Documentation

#define __HAL_RCC_LSI_DISABLE ( ) (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)

Definition at line 877 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Definition at line 876 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: HSE Configuration

Defines
HSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Macro to configure the External High Speed oscillator (HSE).

Define Documentation

#define __HAL_RCC_HSE_CONFIG ( __STATE__ ) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))

Macro to configure the External High Speed oscillator (HSE).

Note:
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__,: specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON: turn ON the HSE oscillator.
  • RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.

Definition at line 907 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: LSE Configuration

Defines
LSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Macro to configure the External Low Speed oscillator (LSE).

Define Documentation

#define __HAL_RCC_LSE_CONFIG ( __STATE__ ) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__,: specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator.
  • RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.

Definition at line 934 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Clock Configuration

Defines
RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.

Definition at line 983 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)

Definition at line 984 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_CLKPRESCALER ( __RTCCLKSource__ )
Value:
(((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by a Power On Reset (POR).
Parameters:
__RTCCLKSource__,: specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected as RTC clock, where x:[2,31]
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wake-up source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Definition at line 971 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_RTC_CONFIG ( __RTCCLKSource__ )
Value:
do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
                                                   } while (0)

Definition at line 974 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_DISABLE ( ) (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)

Definition at line 948 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)

Macros to enable or disable the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 947 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PLL Configuration

Defines
PLL Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.

Define Documentation

#define __HAL_RCC_PLL_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)

Definition at line 1001 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Macros to enable or disable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 1000 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLM_CONFIG ( __PLLM__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))

Macro to configure the PLL multiplication factor.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLM__,: specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Definition at line 1022 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLL clock source.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Definition at line 1011 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Get Clock source

Defines
Get Clock source
RCC Exported Macros

Defines

#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.

Define Documentation

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

Definition at line 1057 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.

Definition at line 1049 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define __HAL_RCC_SYSCLK_CONFIG ( __RCC_SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__RCC_SYSCLKSOURCE__,: specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.

Definition at line 1039 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC Extended MCOx Clock Config

Defines
RCC Extended MCOx Clock Config
RCC Exported Macros

Defines

#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO1 clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
Macro to configure the MCO2 clock.

Define Documentation

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the MCO1 clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1: no division applied to MCOx clock
  • RCC_MCODIV_2: division by 2 applied to MCOx clock
  • RCC_MCODIV_3: division by 3 applied to MCOx clock
  • RCC_MCODIV_4: division by 4 applied to MCOx clock
  • RCC_MCODIV_5: division by 5 applied to MCOx clock

Definition at line 1081 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_MCO2_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));

Macro to configure the MCO2 clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
  • RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
  • RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1: no division applied to MCOx clock
  • RCC_MCODIV_2: division by 2 applied to MCOx clock
  • RCC_MCODIV_3: division by 3 applied to MCOx clock
  • RCC_MCODIV_4: division by 4 applied to MCOx clock
  • RCC_MCODIV_5: division by 5 applied to MCOx clock
Note:
For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).

Definition at line 1102 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
#define | RCC_FLAG_MASK ((uint8_t)0x1FU)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))

Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.

Parameters:
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
  • RCC_IT_CSS: Clock Security System interrupt

Definition at line 1151 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (RCC->CSR |= RCC_CSR_RMVF)

Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.

Definition at line 1170 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))

Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

Definition at line 1137 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))

Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

Definition at line 1124 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GET_FLAG ( __FLAG__ ) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

Definition at line 1191 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))

Check the RCC's interrupt has occurred or not.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt.
  • RCC_IT_LSERDY: LSE ready interrupt.
  • RCC_IT_HSIRDY: HSI ready interrupt.
  • RCC_IT_HSERDY: HSE ready interrupt.
  • RCC_IT_PLLRDY: Main PLL ready interrupt.
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 1165 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_FLAG_MASK ((uint8_t)0x1FU)

Check RCC flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready.
  • RCC_FLAG_HSERDY: HSE oscillator clock ready.
  • RCC_FLAG_PLLRDY: Main PLL clock ready.
  • RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
  • RCC_FLAG_LSERDY: LSE oscillator clock ready.
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready.
  • RCC_FLAG_BORRST: POR/PDR or BOR reset.
  • RCC_FLAG_PINRST: Pin reset.
  • RCC_FLAG_PORRST: POR/PDR reset.
  • RCC_FLAG_SFTRST: Software reset.
  • RCC_FLAG_IWDGRST: Independent Watchdog reset.
  • RCC_FLAG_WWDGRST: Window Watchdog reset.
  • RCC_FLAG_LPWRRST: Low Power reset.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1190 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC BitAddress AliasRegion

Defines
RCC BitAddress AliasRegion
RCC Private Constants

RCC registers bit address in the alias region. More...

Defines

#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
#define | RCC_HSION_BIT_NUMBER 0x00U
#define | RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
#define | RCC_CSSON_BIT_NUMBER 0x13U
#define | RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
#define | RCC_PLLON_BIT_NUMBER 0x18U
#define | RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
#define | RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
#define | RCC_RTCEN_BIT_NUMBER 0x0FU
#define | RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
#define | RCC_BDRST_BIT_NUMBER 0x10U
#define | RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
#define | RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
#define | RCC_LSION_BIT_NUMBER 0x00U
#define | RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
#define | RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
#define | LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */

Detailed Description

RCC registers bit address in the alias region.

Define Documentation

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 1299 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */

Definition at line 1300 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */

Definition at line 1301 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))

Definition at line 1276 of file stm32f4xx_hal_rcc.h.

#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)

Definition at line 1294 of file stm32f4xx_hal_rcc.h.

#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)

Definition at line 1271 of file stm32f4xx_hal_rcc.h.

#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))

Definition at line 1273 of file stm32f4xx_hal_rcc.h.

#define RCC_BDRST_BIT_NUMBER 0x10U

Definition at line 1275 of file stm32f4xx_hal_rcc.h.

#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))

Definition at line 1288 of file stm32f4xx_hal_rcc.h.

#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))

Definition at line 1291 of file stm32f4xx_hal_rcc.h.

#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)

Definition at line 1285 of file stm32f4xx_hal_rcc.h.

#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))

Definition at line 1264 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_DisableCSS(), and HAL_RCC_EnableCSS().

#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))

Definition at line 1261 of file stm32f4xx_hal_rcc.h.

#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)

Definition at line 1259 of file stm32f4xx_hal_rcc.h.

#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))

Definition at line 1267 of file stm32f4xx_hal_rcc.h.

#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))

Definition at line 1282 of file stm32f4xx_hal_rcc.h.

#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)

Definition at line 1280 of file stm32f4xx_hal_rcc.h.

#define RCC_CSSON_BIT_NUMBER 0x13U

Definition at line 1263 of file stm32f4xx_hal_rcc.h.

#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)

Definition at line 1296 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_HSION_BIT_NUMBER 0x00U

Definition at line 1260 of file stm32f4xx_hal_rcc.h.

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Definition at line 1297 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSION_BIT_NUMBER 0x00U

Definition at line 1281 of file stm32f4xx_hal_rcc.h.

#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)

Definition at line 1256 of file stm32f4xx_hal_rcc.h.

#define RCC_PLLON_BIT_NUMBER 0x18U

Definition at line 1266 of file stm32f4xx_hal_rcc.h.

#define RCC_RTCEN_BIT_NUMBER 0x0FU

Definition at line 1272 of file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC Private Constants

Modules | Defines
RCC Private Constants
RCC

Modules

RCC BitAddress AliasRegion

RCC registers bit address in the alias region.

Defines

#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Define Documentation

#define __MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 108 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define __MCO2_CLK_ENABLE ( ) __HAL_RCC_GPIOC_CLK_ENABLE()

Definition at line 112 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */

Definition at line 105 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 109 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 110 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_GPIO_PORT GPIOC

Definition at line 113 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_PIN GPIO_PIN_9

Definition at line 114 of file stm32f4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCC Private Macros

Defines

#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
#define | IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
#define | IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
#define | IS_RCC_PCLK(PCLK)
#define | IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)

Define Documentation

#define IS_RCC_CALIBRATION_VALUE ( VALUE ) ((VALUE) <= 0x1FU)

Definition at line 1367 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_CLOCKTYPE ( CLK ) ((1U <= (CLK)) && ((CLK) <= 15U))

Definition at line 1353 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLK ( HCLK )
Value:
(((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
                           ((HCLK) == RCC_SYSCLK_DIV512))

Definition at line 1347 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( HSE )
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_BYPASS))

Definition at line 1321 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( HSI ) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))

Definition at line 1327 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( LSE )
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_BYPASS))

Definition at line 1324 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSI ( LSI ) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

Definition at line 1329 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( MCOx ) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))

Definition at line 1359 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))

Definition at line 1361 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( DIV )
Value:
(((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
                             ((DIV) == RCC_MCODIV_5))

Definition at line 1364 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( OSCILLATOR ) ((OSCILLATOR) <= 15U)

Definition at line 1319 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK ( PCLK )
Value:
(((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
                           ((PCLK) == RCC_HCLK_DIV16))

Definition at line 1355 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( PLL ) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))

Definition at line 1331 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLM_VALUE ( VALUE ) ((VALUE) <= 63U)

Definition at line 1341 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLP_VALUE ( VALUE ) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))

Definition at line 1343 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLQ_VALUE ( VALUE ) ((4U <= (VALUE)) && ((VALUE) <= 15U))

Definition at line 1345 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_PLLSOURCE_HSI) || \
                                  ((SOURCE) == RCC_PLLSOURCE_HSE))

Definition at line 1333 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_SYSCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))

Definition at line 1336 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCCEx_SelectLSEMode (uint8_t Mode)
Select LSE mode.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) and RCC_BDCR register are set to their reset values.

Function Documentation

void HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE and PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 150 of file stm32f4xx_hal_rcc_ex.c.

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that will be configured.
Note:
This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
This function add the PLL/PLLR factor management
Return values:
None

Definition at line 2051 of file stm32f4xx_hal_rcc_ex.c.

References RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct,: pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
This function add the PLL/PLLR factor management during PLL configuration this feature is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices
Return values:
HAL status

Definition at line 1700 of file stm32f4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PWR_CLK_ENABLE, assert_param, HAL_GetTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_CALIBRATION_VALUE, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_LSERDY, RCC_FLAG_LSIRDY, RCC_FLAG_PLLRDY, RCC_HSE_OFF, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_NONE, and RCC_PLL_ON.

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit,: pointer to an RCC_PeriphCLKInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1239 of file stm32f4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_FMPI2C1_SOURCE, __HAL_RCC_GET_I2S_SOURCE, RCC_PeriphCLKInitTypeDef::Fmpi2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2SClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PERIPHCLK_FMPI2C1, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_TIM, RCC_TIMPRES_ACTIVATED, RCC_TIMPRES_DESACTIVATED, RCC_PeriphCLKInitTypeDef::RTCClockSelection, and RCC_PeriphCLKInitTypeDef::TIMPresSelection.

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit,: pointer to an RCC_PeriphCLKInitTypeDef structure that contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
Note:
A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
Return values:
HAL status

Definition at line 1133 of file stm32f4xx_hal_rcc_ex.c.

References __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_FMPI2C1_CONFIG, __HAL_RCC_GET_FLAG, __HAL_RCC_I2S_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_RTC_CONFIG, __HAL_RCC_TIMCLKPRESCALER, assert_param, RCC_PeriphCLKInitTypeDef::Fmpi2c1ClockSelection, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::I2SClockSelection, IS_RCC_FMPI2C1CLKSOURCE, IS_RCC_I2SAPBCLKSOURCE, IS_RCC_LPTIM1CLKSOURCE, IS_RCC_PERIPHCLOCK, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_LSERDY, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_FMPI2C1, RCC_PERIPHCLK_I2S, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_TIM, RCC_PeriphCLKInitTypeDef::RTCClockSelection, and RCC_PeriphCLKInitTypeDef::TIMPresSelection.

void HAL_RCCEx_SelectLSEMode ( uint8_t Mode )

Select LSE mode.

Note:
This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
Parameters:
Mode,: specifies the LSE mode. This parameter can be one of the following values:
  • RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
  • RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
Return values:
None

Definition at line 2136 of file stm32f4xx_hal_rcc_ex.c.

References assert_param, IS_RCC_LSE_MODE, and RCC_LSE_HIGHDRIVE_MODE.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCCEx Exported Types

RCC PLL configuration structure definition. More...

#include <stm32f4xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR

Detailed Description

RCC PLL configuration structure definition.

Definition at line 65 of file stm32f4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 0 and Max_Data = 63

Definition at line 73 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432 except for STM32F411xE devices where the Min_Data = 192

Definition at line 76 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: Division factor for main system clock (SYSCLK). This parameter must be a value of PLLP Clock Divider

Definition at line 80 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: Division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number between Min_Data = 4 and Max_Data = 15

Definition at line 83 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLR

PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx and STM32F479xx devices. This parameter must be a number between Min_Data = 2 and Max_Data = 7

Definition at line 87 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 70 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter can be a value of PLL Config

Definition at line 67 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rcc_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32f4xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
uint32_t | I2SClockSelection
uint32_t | RTCClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | Fmpi2c1ClockSelection
uint8_t | TIMPresSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 197 of file stm32f4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::Fmpi2c1ClockSelection

Specifies FMPI2C1 Clock Source Selection. This parameter can be a value of RCC FMPI2C1 Clock Source

Definition at line 211 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2SClockSelection

Specifies RTC Clock Source Selection. This parameter can be a value of RCC I2S APB Clock Source

Definition at line 202 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 Clock Source Selection. This parameter can be a value of RCC LPTIM1 Clock Source

Definition at line 208 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of RCC Periph Clock Selection

Definition at line 199 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC Clock Source Selection. This parameter can be a value of RTC Clock Source

Definition at line 205 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint8_t RCC_PeriphCLKInitTypeDef::TIMPresSelection

Specifies TIM Clock Source Selection. This parameter can be a value of RCC TIM PRescaler Selection

Definition at line 213 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rcc_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC Periph Clock Selection

Defines
RCC Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
#define | RCC_PERIPHCLK_TIM ((uint32_t)0x00000002U)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00000004U)
#define | RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008U)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010U)

Define Documentation

#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008U)

Definition at line 359 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)

Definition at line 356 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010U)

Definition at line 360 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004U)

Definition at line 358 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002U)

Definition at line 357 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC PLLSAI DIVR

RCC PLLSAI DIVR
RCCEx Exported Constants
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC PLLI2SP Clock Divider

RCC PLLI2SP Clock Divider
RCCEx Exported Constants
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC PLLSAIP Clock Divider

RCC PLLSAIP Clock Divider
RCCEx Exported Constants
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC I2S APB Clock Source

Defines
RCC I2S APB Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000U)
#define | RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
#define | RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)

Define Documentation

#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)

Definition at line 623 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000U)

Definition at line 622 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)

Definition at line 624 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC FMPI2C1 Clock Source

Defines
RCC FMPI2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
#define | RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
#define | RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)

Define Documentation

#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)

Definition at line 632 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)

Definition at line 634 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)

Definition at line 633 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC LPTIM1 Clock Source

Defines
RCC LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
#define | RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
#define | RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)

Define Documentation

#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)

Definition at line 643 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)

Definition at line 645 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)

Definition at line 644 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)

Definition at line 642 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC TIM PRescaler Selection

Defines
RCC TIM PRescaler Selection
RCCEx Exported Constants

Defines

#define | RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)
#define | RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)

Define Documentation

#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)

Definition at line 654 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)

Definition at line 653 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC LSE Dual Mode Selection

Defines
RCC LSE Dual Mode Selection
RCCEx Exported Constants

Defines

#define | RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00U)
#define | RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01U)

Define Documentation

#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01U)

Definition at line 680 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_SelectLSEMode().

#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00U)

Definition at line 679 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: MCO2 Clock Source

Defines
MCO2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
#define | RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2

Define Documentation

#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1

Definition at line 709 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0

Definition at line 708 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2

Definition at line 710 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)

Definition at line 707 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Peripheral Clock Enable Disable

Defines
AHB1 Peripheral Clock Enable Disable
RCCEx Exported Macros

Enables or disables the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))

Detailed Description

Enables or disables the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))

Definition at line 3050 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)

Definition at line 3036 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))

Definition at line 3051 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)

Definition at line 3043 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Peripheral Clock Enable Disable Status

Defines
AHB1 Peripheral Clock Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)

Definition at line 3063 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED ( ) ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)

Definition at line 3064 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Peripheral Clock Enable Disable

Defines
APB1 Peripheral Clock Enable Disable
RCCEx Exported Macros

Enable or disable the High Speed APB (APB1) peripheral clock. More...

Defines

#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_RTCAPB_CLK_ENABLE()
#define | __HAL_RCC_FMPI2C1_CLK_ENABLE()
#define | __HAL_RCC_DAC_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
#define | __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
#define | __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))

Detailed Description

Enable or disable the High Speed APB (APB1) peripheral clock.

Define Documentation

#define __HAL_RCC_DAC_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))

Definition at line 3113 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                      UNUSED(tmpreg); \
                                      } while(0)

Definition at line 3101 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))

Definition at line 3112 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
                                      UNUSED(tmpreg); \
                                      } while(0)

Definition at line 3094 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))

Definition at line 3111 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
                                      UNUSED(tmpreg); \
                                      } while(0)

Definition at line 3080 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RTCAPB_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))

Definition at line 3110 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RTCAPB_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
                                      UNUSED(tmpreg); \
                                      } while(0)

Definition at line 3087 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))

Definition at line 3109 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                      UNUSED(tmpreg); \
                                      } while(0)

Definition at line 3073 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Peripheral Clock Enable Disable Status

Defines
APB1 Peripheral Clock Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
#define | __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
#define | __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
#define | __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
#define | __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DAC_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)

Definition at line 3135 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)

Definition at line 3129 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)

Definition at line 3134 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)

Definition at line 3128 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)

Definition at line 3133 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)

Definition at line 3127 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)

Definition at line 3132 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)

Definition at line 3126 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)

Definition at line 3131 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)

Definition at line 3125 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Peripheral Clock Enable Disable

Defines
APB2 Peripheral Clock Enable Disable
RCCEx Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_EXTIT_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
#define | __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Define Documentation

#define __HAL_RCC_EXTIT_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))

Definition at line 3159 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_EXTIT_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
                                      UNUSED(tmpreg); \
                                      } while(0)

Definition at line 3151 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))

Definition at line 3158 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                      UNUSED(tmpreg); \
                                      } while(0)

Definition at line 3144 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Peripheral Clock Enable Disable Status

Defines
APB2 Peripheral Clock Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
#define | __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
#define | __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
#define | __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)

Detailed Description

Get the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_EXTIT_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)

Definition at line 3175 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_EXTIT_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)

Definition at line 3172 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)

Definition at line 3174 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)

Definition at line 3171 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Force Release Reset

Defines
AHB1 Force Release Reset
RCCEx Exported Macros

Force or release AHB1 peripheral reset. More...

Defines

#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))

Detailed Description

Force or release AHB1 peripheral reset.

Define Documentation

#define __HAL_RCC_CRC_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))

Definition at line 3184 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))

Definition at line 3186 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))

Definition at line 3185 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))

Definition at line 3187 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB2 Force Release Reset

Defines
AHB2 Force Release Reset
RCCEx Exported Macros

Force or release AHB2 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB2_FORCE_RESET()
#define | __HAL_RCC_AHB2_RELEASE_RESET()

Detailed Description

Force or release AHB2 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB2_FORCE_RESET ( )

Definition at line 3196 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_RELEASE_RESET ( )

Definition at line 3197 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB3 Force Release Reset

Defines
AHB3 Force Release Reset
RCCEx Exported Macros

Force or release AHB3 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB3_FORCE_RESET()
#define | __HAL_RCC_AHB3_RELEASE_RESET()

Detailed Description

Force or release AHB3 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB3_FORCE_RESET ( )

Definition at line 3206 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_RELEASE_RESET ( )

Definition at line 3207 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_DeInit().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Force Release Reset

Defines
APB1 Force Release Reset
RCCEx Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
#define | __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
#define | __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_DAC_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))

Definition at line 3219 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))

Definition at line 3224 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))

Definition at line 3218 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))

Definition at line 3223 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))

Definition at line 3217 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))

Definition at line 3222 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))

Definition at line 3216 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))

Definition at line 3221 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Force Release Reset

Defines
APB2 Force Release Reset
RCCEx Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_SPI5_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))

Definition at line 3233 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))

Definition at line 3234 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: AHB1 Peripheral Low Power Enable Disable

Defines
AHB1 Peripheral Low Power Enable Disable
RCCEx Exported Macros

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))

Detailed Description

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))

Definition at line 3253 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))

Definition at line 3248 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))

Definition at line 3254 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))

Definition at line 3249 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))

Definition at line 3252 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))

Definition at line 3247 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE ( ) (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))

Definition at line 3255 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))

Definition at line 3250 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB1 Peripheral Low Power Enable Disable

Defines
APB1 Peripheral Low Power Enable Disable
RCCEx Exported Macros

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
#define | __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
#define | __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))

Detailed Description

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Define Documentation

#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))

Definition at line 3274 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))

Definition at line 3268 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))

Definition at line 3273 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))

Definition at line 3267 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))

Definition at line 3271 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))

Definition at line 3265 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))

Definition at line 3272 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))

Definition at line 3266 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ( ) (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))

Definition at line 3270 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ( ) (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))

Definition at line 3264 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: APB2 Peripheral Low Power Enable Disable

Defines
APB2 Peripheral Low Power Enable Disable
RCCEx Exported Macros

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))

Detailed Description

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Define Documentation

#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))

Definition at line 3286 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))

Definition at line 3284 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE ( ) (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))

Definition at line 3285 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))

Definition at line 3283 of file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCCEx Exported Macros

Modules | Defines
RCCEx Exported Macros
RCCEx

Modules

AHB1 Peripheral Clock Enable Disable

Enables or disables the AHB1 peripheral clock.

AHB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB1 peripheral clock.

APB1 Peripheral Clock Enable Disable

Enable or disable the High Speed APB (APB1) peripheral clock.

APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock.

APB2 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB2 peripheral clock.

AHB1 Force Release Reset

Force or release AHB1 peripheral reset.

AHB2 Force Release Reset

Force or release AHB2 peripheral reset.

AHB3 Force Release Reset

Force or release AHB3 peripheral reset.

APB1 Force Release Reset

Force or release APB1 peripheral reset.

APB2 Force Release Reset

Force or release APB2 peripheral reset.

AHB1 Peripheral Low Power Enable Disable

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

APB1 Peripheral Low Power Enable Disable

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

APB2 Peripheral Low Power Enable Disable

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Defines

#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)
Macro to configure the PLLI2S clock multiplication and division factors .
#define | __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
Macro to configure I2S clock source selection.
#define | __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
Macro to Get I2S clock source selection.
#define | __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Macro to configure the FMPI2C1 clock.
#define | __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Macro to Get the FMPI2C1 clock.
#define | __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
Macro to configure the LPTIM1 clock.
#define | __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
Macro to Get the LPTIM1 clock.
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
Macro to configure the Timers clocks prescalers.
#define | __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
Macros to enable or disable the RCC MCO1 feature.
#define | __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
#define | __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
Macros to enable or disable the RCC MCO2 feature.
#define | __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)

Define Documentation

#define __HAL_RCC_FMPI2C1_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))

Macro to configure the FMPI2C1 clock.

Parameters:
__SOURCE__,: specifies the FMPI2C1 clock source. This parameter can be one of the following values:
  • RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
  • RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
  • RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock

Definition at line 5092 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_FMPI2C1_SOURCE ( ) (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))

Macro to Get the FMPI2C1 clock.

Return values:
The clock source can be one of the following values:
  • RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
  • RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
  • RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock

Definition at line 5100 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2S_SOURCE ( ) (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))

Macro to Get I2S clock source selection.

Return values:
The clock source can be one of the following values:
  • RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
  • RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
  • RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.

Definition at line 5083 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))

Macro to Get the LPTIM1 clock.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

Definition at line 5119 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_I2S_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))

Macro to configure I2S clock source selection.

Parameters:
__SOURCE__,: specifies the I2S clock source. This parameter can be one of the following values:
  • RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
  • RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
  • RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.

Definition at line 5075 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and I2S_GetInputClock().

#define __HAL_RCC_LPTIM1_CONFIG ( __SOURCE__ ) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))

Macro to configure the LPTIM1 clock.

Parameters:
__SOURCE__,: specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

Definition at line 5110 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_MCO1_DISABLE ( ) (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)

Definition at line 5175 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_MCO1_ENABLE ( ) (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)

Macros to enable or disable the RCC MCO1 feature.

Definition at line 5174 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define __HAL_RCC_MCO2_DISABLE ( ) (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)

Definition at line 5180 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_MCO2_ENABLE ( ) (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)

Macros to enable or disable the RCC MCO2 feature.

Definition at line 5179 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__,
 |  | __PLLQ__,
 |  | __PLLR__
 | ) |
Value:
(RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                      | \
                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))          | \
                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))                      | \
                            ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__RCC_PLLSource__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Note:
This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Parameters:
__PLLM__,: specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Parameters:
__PLLN__,: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.
Parameters:
__PLLP__,: specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLQ__,: specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Note:
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Parameters:
__PLLR__,: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Note:
This parameter is only available in STM32F446xx/STM32F469xx and STM32F479xx devices.

Definition at line 4518 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLI2S_CONFIG | ( | __PLLI2SN__,
 |  | __PLLI2SR__
 | ) |
Value:
(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))  |\
                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))

Macro to configure the PLLI2S clock multiplication and division factors .

Note:
This macro must be used only when the PLLI2S is disabled.
PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API).
Parameters:
__PLLI2SN__,: specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Note:
You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Parameters:
__PLLI2SR__,: specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Note:
You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Definition at line 4626 of file stm32f4xx_hal_rcc_ex.h.

#define __HAL_RCC_TIMCLKPRESCALER ( __PRESC__ ) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))

Macro to configure the Timers clocks prescalers.

Note:
This feature is only available with STM32F429x/439x Devices.
Parameters:
__PRESC__ : specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
  • RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.

Definition at line 5139 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC BitAddress AliasRegion

Defines
RCC BitAddress AliasRegion
RCCEx Private Constants

RCC registers bit address in the alias region. More...

Defines

#define | RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
#define | RCC_TIMPRE_BIT_NUMBER 0x18
#define | RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
#define | RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
#define | RCC_MCO1EN_BIT_NUMBER 0x8
#define | RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
#define | RCC_MCO2EN_BIT_NUMBER 0x9
#define | RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
#define | PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Detailed Description

RCC registers bit address in the alias region.

Define Documentation

#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */

Definition at line 5279 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_RCC_OscConfig().

#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))

Definition at line 5272 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))

Definition at line 5276 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)

Definition at line 5256 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)

Definition at line 5250 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))

Definition at line 5252 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_MCO1EN_BIT_NUMBER 0x8

Definition at line 5271 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_MCO2EN_BIT_NUMBER 0x9

Definition at line 5275 of file stm32f4xx_hal_rcc_ex.h.

#define RCC_TIMPRE_BIT_NUMBER 0x18

Definition at line 5251 of file stm32f4xx_hal_rcc_ex.h.

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STM32F410Rx HAL User Manual: RCC Private macros to check input parameters

Defines
RCC Private macros to check input parameters
RCCEx Private Macros

Defines

#define | IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
#define | IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
#define | IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
#define | IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
#define | IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
#define | IS_RCC_LSE_MODE(MODE)
#define | IS_RCC_FMPI2C1CLKSOURCE(SOURCE)
#define | IS_RCC_LPTIM1CLKSOURCE(SOURCE)
#define | IS_RCC_I2SAPBCLKSOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)

Define Documentation

#define IS_RCC_FMPI2C1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB)    ||\
                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))

Definition at line 5361 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2SAPBCLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR)    ||\
                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT)    ||\
                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))

Definition at line 5370 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLKSOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) ||\
                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))

Definition at line 5365 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LSE_MODE ( MODE )
Value:
(((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))

Definition at line 5358 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_SelectLSEMode().

#define IS_RCC_MCO2SOURCE ( SOURCE )
Value:
(((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))

Definition at line 5459 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_PERIPHCLOCK ( SELECTION ) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))

Definition at line 5315 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLI2SN_VALUE ( VALUE ) ((50U <= (VALUE)) && ((VALUE) <= 432U))

Definition at line 5302 of file stm32f4xx_hal_rcc_ex.h.

#define IS_RCC_PLLI2SR_VALUE ( VALUE ) ((2U <= (VALUE)) && ((VALUE) <= 7U))

Definition at line 5326 of file stm32f4xx_hal_rcc_ex.h.

#define IS_RCC_PLLN_VALUE ( VALUE ) ((50U <= (VALUE)) && ((VALUE) <= 432U))

Definition at line 5301 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLR_VALUE ( VALUE ) ((2U <= (VALUE)) && ((VALUE) <= 7U))

Definition at line 5356 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

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STM32F410Rx HAL User Manual: RNG State Structure definition

Enumerations
RNG State Structure definition
RNG Exported Types

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef
Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 72 of file stm32f4xx_hal_rng.h.

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STM32F410Rx HAL User Manual: RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_HandleTypeDef Struct Reference
RNG Handle Structure definition

#include <stm32f4xx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State
uint32_t | RandomNumber

Detailed Description

Definition at line 89 of file stm32f4xx_hal_rng.h.

Field Documentation

RNG_TypeDef* RNG_HandleTypeDef::Instance

Register base address

Definition at line 91 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GetRandomNumber_IT(), and HAL_RNG_IRQHandler().

HAL_LockTypeDef RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 93 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

uint32_t RNG_HandleTypeDef::RandomNumber

Last Generated RNG Data

Definition at line 97 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_GetRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

__IO HAL_RNG_StateTypeDef RNG_HandleTypeDef::State

RNG communication state

Definition at line 95 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rng.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Interrupt definition

Defines
RNG Interrupt definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 119 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 118 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 120 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

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STM32F410Rx HAL User Manual: RNG Flag definition

Defines
RNG Flag definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 129 of file stm32f4xx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 128 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 130 of file stm32f4xx_hal_rng.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clears the selected RNG flag status.

Parameters:
__HANDLE__,: RNG handle
__FLAG__,: RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 186 of file stm32f4xx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 226 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disables the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 164 of file stm32f4xx_hal_rng.h.

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disables the RNG interrupts.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 202 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enables the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 157 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enables the RNG interrupts.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 195 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT(), and HAL_RNG_GetRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check the selected RNG flag status.

Parameters:
__HANDLE__,: RNG Handle
__FLAG__,: RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 176 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 214 of file stm32f4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)

Reset RNG handle state.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 150 of file stm32f4xx_hal_rng.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP
      (+) DeInitialize RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG peripheral.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 161 of file stm32f4xx_hal_rng.c.

References HAL_RNG_MspDeInit(), HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Instance, and RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initializes the RNG peripheral and creates the associated handle.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 122 of file stm32f4xx_hal_rng.c.

References __HAL_RNG_ENABLE, HAL_RNG_MspInit(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Lock, and RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 208 of file stm32f4xx_hal_rng.c.

Referenced by HAL_RNG_DeInit().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initializes the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 193 of file stm32f4xx_hal_rng.c.

Referenced by HAL_RNG_Init().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callbacks.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 467 of file stm32f4xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generates a 32-bit random number.

Note:
Each time the random number data is read the RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit,: pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 247 of file stm32f4xx_hal_rng.c.

References __HAL_RNG_GET_FLAG, HAL_GetTick(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and RNG_HandleTypeDef::State.

Referenced by HAL_RNG_GetRandomNumber().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generates a 32-bit random number in interrupt mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 301 of file stm32f4xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and RNG_HandleTypeDef::State.

uint32_t HAL_RNG_GetRandomNumber ( RNG_HandleTypeDef * hrng )

Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
Random value

Definition at line 394 of file stm32f4xx_hal_rng.c.

References HAL_RNG_GenerateRandomNumber(), and RNG_HandleTypeDef::RandomNumber.

uint32_t HAL_RNG_GetRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
32-bit random number

Definition at line 413 of file stm32f4xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, HAL_RNG_STATE_BUSY, RNG_HandleTypeDef::Instance, and RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handles RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 352 of file stm32f4xx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __HAL_RNG_GET_IT, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 439 of file stm32f4xx_hal_rng.c.

References RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit,: generated random number.
Return values:
None

Definition at line 451 of file stm32f4xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_RNG_StateTypeDef HAL_RNG_GetState ( RNG_HandleTypeDef * hrng )

Returns the RNG state.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL state

Definition at line 501 of file stm32f4xx_hal_rng.c.

References RNG_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: RNG Private Types

RNG Private Types
RNG
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Private Defines

RNG Private Defines
RNG
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Private Variables

RNG Private Variables
RNG
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNG

Defines

#define RNG_TIMEOUT_VALUE 2U

Define Documentation

#define RNG_TIMEOUT_VALUE 2U

Definition at line 85 of file stm32f4xx_hal_rng.c.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)

Define Documentation

#define IS_RNG_FLAG ( FLAG )
Value:
(((FLAG) == RNG_FLAG_DRDY) || \
                           ((FLAG) == RNG_FLAG_CECS) || \
                           ((FLAG) == RNG_FLAG_SECS))

Definition at line 323 of file stm32f4xx_hal_rng.h.

#define IS_RNG_IT ( IT )
Value:
(((IT) == RNG_IT_CEI) || \
                       ((IT) == RNG_IT_SEI))

Definition at line 320 of file stm32f4xx_hal_rng.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Private Functions Prototypes

RNG Private Functions Prototypes
RNG
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Private Functions

RNG Private Functions
RNG
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wake-up from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC peripheral.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
This function doesn't reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 278 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initializes the RTC peripheral.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 203 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, RTC_InitTypeDef::HourFormat, RTC_HandleTypeDef::Init, RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, RTC_HandleTypeDef::Lock, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_HandleTypeDef::State, and RTC_InitTypeDef::SynchPrediv.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC MSP.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 393 of file stm32f4xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initializes the RTC MSP.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 378 of file stm32f4xx_hal_rtc.c.

Referenced by HAL_RTC_Init().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current date.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to Date structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Return values:
HAL status

Definition at line 720 of file stm32f4xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current time.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until current date is read.
Return values:
HAL status

Definition at line 563 of file stm32f4xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current date.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 608 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current time.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 431 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1340 of file stm32f4xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Alarm interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1299 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_IT, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1151 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Gets the RTC Alarm value and masks.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Date structure
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1248 of file stm32f4xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmA Polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1356 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 775 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm with Interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 961 of file stm32f4xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EXTI_LINE_ALARM_EVENT, RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wake-up from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1418 of file stm32f4xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Returns the RTC state.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL state

Definition at line 1464 of file stm32f4xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Exported Functions

Modules | Functions
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Converts from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted
Return values:
Converted word

Definition at line 1531 of file stm32f4xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Converts a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted
Return values:
Converted byte

Definition at line 1513 of file stm32f4xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1481 of file stm32f4xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCoarseCalib(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_SetCoarseCalib(), and HAL_RTCEx_SetRefClock().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Exported Types

Data Structures | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
RTC Handle Structure definition. More...

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 65 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32f4xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutPolarity
uint32_t | OutPutType

Detailed Description

RTC Configuration Structure definition.

Definition at line 77 of file stm32f4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 82 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 79 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTC Output Selection Definitions

Definition at line 88 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 91 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 94 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU

Definition at line 85 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rtc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32f4xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 101 of file stm32f4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

Specifies DayLight Save Operation. This parameter can be a value of RTC DayLight Saving Definitions

Definition at line 126 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 103 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 107 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 120 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 110 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

Specifies RTC_StoreOperation value to be written in the BCK bit in CR register to store the operation. This parameter can be a value of RTC Store Operation Definitions

Definition at line 129 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 116 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 113 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rtc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32f4xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 137 of file stm32f4xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 145 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 142 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 139 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 148 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rtc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32f4xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 156 of file stm32f4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 173 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 169 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC Alarm Date WeekDay Definitions

Definition at line 166 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC Alarm Mask Definitions

Definition at line 160 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 163 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 158 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rtc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_HandleTypeDef Struct Reference
RTC Exported Types

RTC Handle Structure definition. More...

#include <stm32f4xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State

Detailed Description

RTC Handle Structure definition.

Definition at line 180 of file stm32f4xx_hal_rtc.h.

Field Documentation

RTC_InitTypeDef RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 184 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* RTC_HandleTypeDef::Instance

Register base address

Definition at line 182 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateCoarseCalib(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetCoarseCalib(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), HAL_RTCEx_WakeUpTimerIRQHandler(), and RTC_EnterInitMode().

HAL_LockTypeDef RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 186 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

__IO HAL_RTCStateTypeDef RTC_HandleTypeDef::State

Time communication state

Definition at line 188 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateCoarseCalib(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetCoarseCalib(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rtc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040U)

Define Documentation

#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U)

Definition at line 205 of file stm32f4xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)

Definition at line 204 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Output Selection Definitions

Defines
RTC Output Selection Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U)

Define Documentation

#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U)

Definition at line 214 of file stm32f4xx_hal_rtc.h.

#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U)

Definition at line 215 of file stm32f4xx_hal_rtc.h.

#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)

Definition at line 213 of file stm32f4xx_hal_rtc.h.

#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U)

Definition at line 216 of file stm32f4xx_hal_rtc.h.

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STM32F410Rx HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U)

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)

Definition at line 224 of file stm32f4xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U)

Definition at line 225 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000U)

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)

Definition at line 233 of file stm32f4xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000U)

Definition at line 234 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40U)

Define Documentation

#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)

Definition at line 242 of file stm32f4xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)

Definition at line 243 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC DayLight Saving Definitions

Defines
RTC DayLight Saving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U)

Definition at line 252 of file stm32f4xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)

Definition at line 253 of file stm32f4xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U)

Definition at line 251 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Store Operation Definitions

Defines
RTC Store Operation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000U)

Define Documentation

#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)

Definition at line 261 of file stm32f4xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U)

Definition at line 262 of file stm32f4xx_hal_rtc.h.

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STM32F410Rx HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN ((uint32_t)0x00000000U)
#define | RTC_FORMAT_BCD ((uint32_t)0x00000001U)

Define Documentation

#define RTC_FORMAT_BCD ((uint32_t)0x00000001U)

Definition at line 271 of file stm32f4xx_hal_rtc.h.

#define RTC_FORMAT_BIN ((uint32_t)0x00000000U)

Definition at line 270 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04U)

Definition at line 283 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08U)

Definition at line 287 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Definition at line 291 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

Definition at line 281 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01U)

Definition at line 280 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07U)

Definition at line 286 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06U)

Definition at line 285 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03U)

Definition at line 282 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05U)

Definition at line 284 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

Definition at line 290 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)

Definition at line 289 of file stm32f4xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

Definition at line 288 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Definition at line 303 of file stm32f4xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Definition at line 299 of file stm32f4xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Definition at line 304 of file stm32f4xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Definition at line 305 of file stm32f4xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Definition at line 302 of file stm32f4xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Definition at line 300 of file stm32f4xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Definition at line 301 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Alarm Date WeekDay Definitions

Defines
RTC Alarm Date WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U)

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)

Definition at line 313 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U)

Definition at line 314 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Alarm Mask Definitions

Defines
RTC Alarm Mask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080U)

Define Documentation

#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U)

Definition at line 327 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 323 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 324 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 325 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)

Definition at line 322 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 326 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 335 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 336 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U)

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U)

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 344 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U)

SS[14:0] are compared and must match to activate alarm.

Definition at line 375 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U)

SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared

Definition at line 373 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U)

SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

Definition at line 347 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U)

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared

Definition at line 365 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U)

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared

Definition at line 367 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U)

SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared

Definition at line 369 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U)

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared

Definition at line 371 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U)

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared

Definition at line 349 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U)

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared

Definition at line 351 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U)

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared

Definition at line 353 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U)

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared

Definition at line 355 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U)

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared

Definition at line 357 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U)

SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared

Definition at line 359 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U)

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared

Definition at line 361 of file stm32f4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U)

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared

Definition at line 363 of file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS ((uint32_t)0x00008000U)
#define | RTC_IT_WUT ((uint32_t)0x00004000U)
#define | RTC_IT_ALRB ((uint32_t)0x00002000U)
#define | RTC_IT_ALRA ((uint32_t)0x00001000U)
#define | RTC_IT_TAMP ((uint32_t)0x00000004U) /* Used only to Enable the Tamper Interrupt */
#define | RTC_IT_TAMP1 ((uint32_t)0x00020000U)
#define | RTC_IT_TAMP2 ((uint32_t)0x00040000U)

Define Documentation

#define RTC_IT_ALRA ((uint32_t)0x00001000U)

Definition at line 387 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB ((uint32_t)0x00002000U)

Definition at line 386 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TAMP ((uint32_t)0x00000004U) /* Used only to Enable the Tamper Interrupt */

Definition at line 388 of file stm32f4xx_hal_rtc.h.

#define RTC_IT_TAMP1 ((uint32_t)0x00020000U)

Definition at line 389 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP2 ((uint32_t)0x00040000U)

Definition at line 390 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TS ((uint32_t)0x00008000U)

Definition at line 384 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_WUT ((uint32_t)0x00004000U)

Definition at line 385 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RECALPF ((uint32_t)0x00010000U)
#define | RTC_FLAG_TAMP2F ((uint32_t)0x00004000U)
#define | RTC_FLAG_TAMP1F ((uint32_t)0x00002000U)
#define | RTC_FLAG_TSOVF ((uint32_t)0x00001000U)
#define | RTC_FLAG_TSF ((uint32_t)0x00000800U)
#define | RTC_FLAG_WUTF ((uint32_t)0x00000400U)
#define | RTC_FLAG_ALRBF ((uint32_t)0x00000200U)
#define | RTC_FLAG_ALRAF ((uint32_t)0x00000100U)
#define | RTC_FLAG_INITF ((uint32_t)0x00000040U)
#define | RTC_FLAG_RSF ((uint32_t)0x00000020U)
#define | RTC_FLAG_INITS ((uint32_t)0x00000010U)
#define | RTC_FLAG_SHPF ((uint32_t)0x00000008U)
#define | RTC_FLAG_WUTWF ((uint32_t)0x00000004U)
#define | RTC_FLAG_ALRBWF ((uint32_t)0x00000002U)
#define | RTC_FLAG_ALRAWF ((uint32_t)0x00000001U)

Define Documentation

#define RTC_FLAG_ALRAF ((uint32_t)0x00000100U)

Definition at line 405 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001U)

Definition at line 412 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF ((uint32_t)0x00000200U)

Definition at line 404 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002U)

Definition at line 411 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF ((uint32_t)0x00000040U)

Definition at line 406 of file stm32f4xx_hal_rtc.h.

#define RTC_FLAG_INITS ((uint32_t)0x00000010U)

Definition at line 408 of file stm32f4xx_hal_rtc.h.

#define RTC_FLAG_RECALPF ((uint32_t)0x00010000U)

Definition at line 398 of file stm32f4xx_hal_rtc.h.

#define RTC_FLAG_RSF ((uint32_t)0x00000020U)

Definition at line 407 of file stm32f4xx_hal_rtc.h.

#define RTC_FLAG_SHPF ((uint32_t)0x00000008U)

Definition at line 409 of file stm32f4xx_hal_rtc.h.

#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000U)

Definition at line 400 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000U)

Definition at line 399 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSF ((uint32_t)0x00000800U)

Definition at line 402 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSOVF ((uint32_t)0x00001000U)

Definition at line 401 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_WUTF ((uint32_t)0x00000400U)

Definition at line 403 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF ((uint32_t)0x00000004U)

Definition at line 410 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 536 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 501 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 490 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)

Clear the RTC Alarm associated Exti line flag.

Return values:
None.

Definition at line 624 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 572 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 584 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 560 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 596 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
                                                                __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
                                                              } while(0)

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 610 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 566 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 578 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 554 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 590 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
                                                               __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
                                                             } while(0)

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 602 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on RTC Alarm associated Exti line.

Return values:
None.

Definition at line 630 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 618 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 525 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 512 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 548 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 465 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 458 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 479 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 472 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)

Reset RTC handle state.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 430 of file stm32f4xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xCAU;  \
                            (__HANDLE__)->Instance->WPR = 0x53U;  \
                          } while(0)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 437 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateCoarseCalib(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetCoarseCalib(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xFFU;  \
                          } while(0)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 448 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateCoarseCalib(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetCoarseCalib(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_FLAGS_MASK
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)

Define Documentation

#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU)

Definition at line 712 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 723 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define RTC_FLAGS_MASK
Value:
((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
                                            RTC_FLAG_RECALPF | RTC_FLAG_SHPF))

Definition at line 715 of file stm32f4xx_hal_rtc.h.

#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)

Definition at line 713 of file stm32f4xx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)

Definition at line 714 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000

Definition at line 721 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU)

Definition at line 711 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)
#define | IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFFU)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)

Define Documentation

#define IS_RTC_ALARM ( ALARM ) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))

Definition at line 781 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) >(uint32_t) 0U) && ((DATE) <= (uint32_t)31U))

Definition at line 770 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 778 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 771 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)

Definition at line 780 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))

Definition at line 784 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= (uint32_t)0x00007FFFU)

Definition at line 782 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7FU)

Definition at line 748 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))

Definition at line 762 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 754 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT ) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 759 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))

Definition at line 746 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= (uint32_t)23U)

Definition at line 747 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 736 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM ) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 753 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= (uint32_t)59U)

Definition at line 750 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))

Definition at line 761 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE) || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))

Definition at line 738 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 742 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 744 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= (uint32_t)59U)

Definition at line 751 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 757 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7FFFU)

Definition at line 749 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 763 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= (uint32_t)99U)

Definition at line 760 of file stm32f4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Converts from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted
Return values:
Converted word

Definition at line 1531 of file stm32f4xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Converts a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted
Return values:
Converted byte

Definition at line 1513 of file stm32f4xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1481 of file stm32f4xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCoarseCalib(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_SetCoarseCalib(), and HAL_RTCEx_SetRefClock().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC TimeStamp and Tamper functions

Functions
RTC TimeStamp and Tamper functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Gets the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper2 Polling.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivates Tamper.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Tamper,: Selected tamper pin. This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
Return values:
HAL status

Definition at line 477 of file stm32f4xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivates TimeStamp.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 272 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_IT_TS, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Gets the RTC TimeStamp value.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTimeStamp,: Pointer to Time structure
sTimeStampDate,: Pointer to Date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values: RTC_FORMAT_BIN: Binary data format RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 316 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper1 Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 647 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper2 Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 683 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles TimeStamp polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 604 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 368 of file stm32f4xx_hal_rtc_ex.c.

References assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_PIN, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::PinSelection, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to RTC Tamper.
Return values:
HAL status

Definition at line 418 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_PIN, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::PinSelection, RTC_TamperTypeDef::PrechargeDuration, RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Sets TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin. (PI8 for all STM32 devices except for STM32F446xx devices the PA0 is used)
  • RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
Return values:
HAL status

Definition at line 158 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Sets TimeStamp with Interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
  • RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices)
  • RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
Return values:
HAL status

Definition at line 218 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 573 of file stm32f4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 588 of file stm32f4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles TimeStamp interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 503 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_IT, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_TimeStampEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_TAMP1F, RTC_FLAG_TAMP2F, RTC_FLAG_TSF, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 558 of file stm32f4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Wake-up functions

Functions
RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivates wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Gets wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Wake-up feature

Function Documentation

uint32_t HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivates wake up timer counter.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 926 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Gets wake up timer counter.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
Counter value

Definition at line 981 of file stm32f4xx_hal_rtc_ex.c.

References RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Wake Up Timer Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1037 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Sets wake up timer.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 738 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Sets wake up timer with interrupt.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 829 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_EXTI_LINE_WAKEUPTIMER_EVENT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1021 of file stm32f4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Wake Up Timer interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 993 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_IT, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_HandleTypeDef::Instance, RTC_FLAG_WUTF, RTC_IT_WUT, and RTC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extension Peripheral Control functions

Functions
Extension Peripheral Control functions
RTCEx Exported Functions

Extension Peripheral Control functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetCoarseCalib (RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value)
Sets the Coarse calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCoarseCalib (RTC_HandleTypeDef *hrtc)
Deactivates the Coarse calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configures the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enables the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enables the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disables the Bypass Shadow feature.

Detailed Description

Extension Peripheral Control functions.

 ===============================================================================
              ##### Extension Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
Read value

Definition at line 1130 of file stm32f4xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 1107 of file stm32f4xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1488 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib ( RTC_HandleTypeDef * hrtc )

Deactivates the Coarse calibration parameters.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1219 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_COARSE_CALIB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1568 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disables the Bypass Shadow feature.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1653 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enables the Bypass Shadow feature.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1620 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
CalibOutput,: Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1449 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibSign,
 |  | uint32_t | Value
 | ) |  |

Sets the Coarse calibration parameters.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
CalibSign,: Specifies the sign of the coarse calibration value. This parameter can be one of the following values :
  • RTC_CALIBSIGN_POSITIVE: The value sign is positive
  • RTC_CALIBSIGN_NEGATIVE: The value sign is negative
Value,: value of coarse calibration expressed in ppm (coded on 5 bits).
Note:
This Calibration value should be between 0 and 63 when using negative sign with a 2-ppm step.
This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step.
Return values:
HAL status

Definition at line 1161 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_COARSE_CALIB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_CALIB_SIGN, IS_RTC_CALIB_VALUE, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enables the RTC reference clock detection.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1518 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmouthCalibMinusPulsesValue
 | ) |  |

Sets the Smooth calibration parameters.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
SmoothCalibPeriod,: Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses,: Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmouthCalibMinusPulsesValue,: Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmouthCalibMinusPulsesValue must be equal to 0.
Return values:
HAL status

Definition at line 1284 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configures the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
ShiftAdd1S,: Select to add or not 1 second to the time calendar. This parameter can be one of the following values :
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS,: Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 1354 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alarm B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1703 of file stm32f4xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmB Polling request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1719 of file stm32f4xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and RTC_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Exported Types

RTC Tamper structure definition. More...

#include <stm32f4xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | PinSelection
uint32_t | Trigger
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

RTC Tamper structure definition.

Definition at line 65 of file stm32f4xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the RTC Filter Tamper. This parameter can be a value of RTC Tamper Filter Definitions

Definition at line 76 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PinSelection

Specifies the Tamper Pin. This parameter can be a value of RTC tamper Pins Selection

Definition at line 70 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTC Tamper Pin Precharge Duration Definitions

Definition at line 82 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTC Tamper Sampling Frequencies Definitions

Definition at line 79 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTC Tamper Pins Definitions

Definition at line 67 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTC Tamper Pull Up Definitions

Definition at line 85 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTC Tamper TimeStamp On Tamper Detection Definitions

Definition at line 88 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTC Tamper Triggers Definitions

Definition at line 73 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_rtc_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Backup Registers Definitions

Defines
RTC Backup Registers Definitions
RTCEx Exported Constants

Defines

#define | RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004U)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005U)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006U)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007U)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008U)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009U)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000AU)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000BU)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000CU)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000DU)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000EU)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000FU)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010U)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011U)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012U)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013U)

Define Documentation

#define RTC_BKP_DR0 ((uint32_t)0x00000000U)

Definition at line 103 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 ((uint32_t)0x00000001U)

Definition at line 104 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 ((uint32_t)0x0000000AU)

Definition at line 113 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR11 ((uint32_t)0x0000000BU)

Definition at line 114 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR12 ((uint32_t)0x0000000CU)

Definition at line 115 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR13 ((uint32_t)0x0000000DU)

Definition at line 116 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR14 ((uint32_t)0x0000000EU)

Definition at line 117 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR15 ((uint32_t)0x0000000FU)

Definition at line 118 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR16 ((uint32_t)0x00000010U)

Definition at line 119 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR17 ((uint32_t)0x00000011U)

Definition at line 120 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR18 ((uint32_t)0x00000012U)

Definition at line 121 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR19 ((uint32_t)0x00000013U)

Definition at line 122 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 ((uint32_t)0x00000002U)

Definition at line 105 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 ((uint32_t)0x00000003U)

Definition at line 106 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 ((uint32_t)0x00000004U)

Definition at line 107 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 ((uint32_t)0x00000005U)

Definition at line 108 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 ((uint32_t)0x00000006U)

Definition at line 109 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 ((uint32_t)0x00000007U)

Definition at line 110 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 ((uint32_t)0x00000008U)

Definition at line 111 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 ((uint32_t)0x00000009U)

Definition at line 112 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC TimeStamp Edges Definitions

Defines
RTC TimeStamp Edges Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U)

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U)

Definition at line 131 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)

Definition at line 130 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper Pins Definitions

Defines
RTC Tamper Pins Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAFCR_TAMP2E

Define Documentation

#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E

Definition at line 139 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E

Definition at line 140 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC tamper Pins Selection

Defines
RTC tamper Pins Selection
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000U)
#define | RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000U)

Define Documentation

#define RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000U)

Definition at line 148 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000U)

Definition at line 149 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC TimeStamp Pins Selection

Defines
RTC TimeStamp Pins Selection
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)
#define | RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000U)

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)

Definition at line 157 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000U)

Definition at line 158 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper Triggers Definitions

Defines
RTC Tamper Triggers Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)

Definition at line 167 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Definition at line 169 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE

Definition at line 168 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)

Definition at line 166 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper Filter Definitions

Defines
RTC Tamper Filter Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800U)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000U)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800U)

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800U)

Tamper is activated after 2 consecutive samples at the active level

Definition at line 179 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000U)

Tamper is activated after 4 consecutive samples at the active level

Definition at line 181 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800U)

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 183 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U)

Tamper filter is disabled

Definition at line 177 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper Sampling Frequencies Definitions

Defines
RTC Tamper Sampling Frequencies Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700U)

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 202 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 194 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 200 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 206 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 192 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 198 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 204 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 196 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper Pin Precharge Duration Definitions

Defines
RTC Tamper Pin Precharge Duration Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 215 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 217 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 219 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 221 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper TimeStamp On Tamper Detection Definitions

Defines
RTC Tamper TimeStamp On Tamper Detection Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)

TimeStamp on Tamper Detection event is not saved

Definition at line 231 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS)

TimeStamp on Tamper Detection event saved

Definition at line 230 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper Pull Up Definitions

Defines
RTC Tamper Pull Up Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)

TimeStamp on Tamper Detection event is not saved

Definition at line 240 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U)

TimeStamp on Tamper Detection event saved

Definition at line 239 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Wake-up Timer Definitions

Defines
RTC Wake-up Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U)

Definition at line 252 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U)

Definition at line 253 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)

Definition at line 248 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U)

Definition at line 251 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U)

Definition at line 250 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U)

Definition at line 249 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Digital Calib Definitions

Defines
RTC Digital Calib Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000U)
#define | RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080U)

Define Documentation

#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080U)

Definition at line 262 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000U)

Definition at line 261 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Smooth Calib Period Definitions

Defines
RTC Smooth Calib Period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000U)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000U)

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000U)

If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds

Definition at line 272 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U)

If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds

Definition at line 270 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000U)

If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds

Definition at line 274 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Smooth Calib Plus Pulses Definitions

Defines
RTC Smooth Calib Plus Pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000U)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U)

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U)

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 286 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000U)

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 283 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Add 1 Second Parameter Definitions

Defines
RTC Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U)

Define Documentation

#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U)

Definition at line 295 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U)

Definition at line 296 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Calib Output Selection Definitions

Defines
RTC Calib Output Selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000U)

Define Documentation

#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000U)

Definition at line 306 of file stm32f4xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U)

Definition at line 305 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC WakeUp Timer

Defines
RTC WakeUp Timer
RTCEx Exported Macros

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC Wake-up Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC Wake-up Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.

Define Documentation

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Wake Up timer's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 398 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC Wake-up Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 337 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer A interrupt
Return values:
None

Definition at line 357 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 330 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer A interrupt
Return values:
None

Definition at line 347 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC Wake-up Timer associated Exti line flag.

Return values:
None.

Definition at line 475 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 422 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 434 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC Wake-up Timer associated Exti line.

Return values:
None

Definition at line 410 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 446 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
                                                                      __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
                                                                    } while(0)

Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 461 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 416 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 428 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC Wake-up Timer associated Exti line.

Return values:
None

Definition at line 404 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 440 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
                                                                     __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
                                                                   } while(0)

Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 452 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.

Return values:
None.

Definition at line 481 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 469 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC WakeUpTimer's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC WakeUpTimer Flag to check. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 388 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer A interrupt
Return values:
None

Definition at line 367 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 377 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Timestamp

Defines
RTC Timestamp
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.

Define Documentation

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Time Stamp's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_TSF
Return values:
None

Definition at line 565 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 504 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 524 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 497 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 514 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC TimeStamp's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC TimeStamp flag to check. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 555 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 534 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Time Stamp interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 544 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Tamper

Defines
RTC Tamper
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.

Define Documentation

#define __HAL_RTC_TAMPER1_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))

Disable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 588 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))

Enable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 581 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))

Disable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 602 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))

Enable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 595 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag to clear. This parameter can be:
  • RTC_FLAG_TAMP1F
  • RTC_FLAG_TAMP2F
Return values:
None

Definition at line 645 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_TAMP1F
  • RTC_FLAG_TAMP2F
Return values:
None

Definition at line 634 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_PollForTamper2Event().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)

Check whether the specified RTC Tamper interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMP1
  • RTC_IT_TAMP2
Return values:
None

Definition at line 613 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMP: Tamper interrupt
Return values:
None

Definition at line 623 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: EXTI RTC Tamper Timestamp EXTI

Defines
EXTI RTC Tamper Timestamp EXTI
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Define Documentation

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag.

Return values:
None.

Definition at line 730 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 677 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 689 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 665 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 701 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
                                                                           __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
                                                                         } while(0)

Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 716 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 671 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 683 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 659 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 695 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
                                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
                                                                        } while(0)

Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 707 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 736 of file stm32f4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG ( ) (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 724 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Calibration

Defines
RTC Calibration
RTCEx Exported Macros

Defines

#define | __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
Enable the Coarse calibration process.
#define | __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
Disable the Coarse calibration process.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC shift operation's flag status.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 772 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 765 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 786 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 779 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_COARSE_CALIB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))

Disable the Coarse calibration process.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 758 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCoarseCalib().

#define __HAL_RTC_COARSE_CALIB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))

Enable the Coarse calibration process.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 751 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCoarseCalib().

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC shift operation's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 796 of file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22)

Define Documentation

#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21)

External interrupt line 21 Connected to the RTC Tamper and Time Stamp events

Definition at line 890 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22)

External interrupt line 22 Connected to the RTC Wake-up event

Definition at line 891 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Private macros to check input parameters

Defines
Private macros to check input parameters
RTCEx Private Macros

Defines

#define | IS_RTC_BKP(BKP)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_PIN(PIN)
#define | IS_RTC_TIMESTAMP_PIN(PIN)
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
#define | IS_RTC_CALIB_SIGN(SIGN)
#define | IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Define Documentation

#define IS_RTC_BKP ( BKP )
Value:
(((BKP) == RTC_BKP_DR0)  || \
                                           ((BKP) == RTC_BKP_DR1)  || \
                                           ((BKP) == RTC_BKP_DR2)  || \
                                           ((BKP) == RTC_BKP_DR3)  || \
                                           ((BKP) == RTC_BKP_DR4)  || \
                                           ((BKP) == RTC_BKP_DR5)  || \
                                           ((BKP) == RTC_BKP_DR6)  || \
                                           ((BKP) == RTC_BKP_DR7)  || \
                                           ((BKP) == RTC_BKP_DR8)  || \
                                           ((BKP) == RTC_BKP_DR9)  || \
                                           ((BKP) == RTC_BKP_DR10) || \
                                           ((BKP) == RTC_BKP_DR11) || \
                                           ((BKP) == RTC_BKP_DR12) || \
                                           ((BKP) == RTC_BKP_DR13) || \
                                           ((BKP) == RTC_BKP_DR14) || \
                                           ((BKP) == RTC_BKP_DR15) || \
                                           ((BKP) == RTC_BKP_DR16) || \
                                           ((BKP) == RTC_BKP_DR17) || \
                                           ((BKP) == RTC_BKP_DR18) || \
                                           ((BKP) == RTC_BKP_DR19))

Definition at line 904 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 981 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_CALIB_SIGN ( SIGN )
Value:
(((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
                                 ((SIGN) == RTC_CALIBSIGN_NEGATIVE))

Definition at line 966 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCoarseCalib().

#define IS_RTC_CALIB_VALUE ( VALUE ) ((VALUE) < 0x20U)

Definition at line 969 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCoarseCalib().

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 978 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= 0x00007FFFU)

Definition at line 980 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= 0x000001FFU)

Definition at line 977 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 971 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 974 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( TAMPER ) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))

Definition at line 926 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( FILTER )
Value:
(((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 938 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PIN ( PIN )
Value:
(((PIN) == RTC_TAMPERPIN_DEFAULT) || \
                                ((PIN) == RTC_TAMPERPIN_POS1))

Definition at line 928 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( DURATION )
Value:
(((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 950 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 956 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( FREQ )
Value:
(((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 942 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 954 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 934 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN )
Value:
(((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
                                   ((PIN) == RTC_TIMESTAMPPIN_POS1))

Definition at line 931 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 958 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= 0xFFFFU)

Definition at line 965 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 924 of file stm32f4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SAI

SAI
STM32F4xx_HAL_Driver

SAI HAL module driver. More...

SAI HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SAIEx

SAIEx
STM32F4xx_HAL_Driver

SAI Extension HAL module driver. More...

SAI Extension HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SDRAM

SDRAM
STM32F4xx_HAL_Driver

SDRAM driver modules. More...

SDRAM driver modules.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SmartCard Initialization and de-initialization functions

Functions
SmartCard Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the USART SmartCard peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_ReInit (SMARTCARD_HandleTypeDef *hsc)

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USART
  in Smartcard mode.
  [..]
  The Smartcard interface is designed to support asynchronous protocol Smartcards as
  defined in the ISO 7816-3 standard.
  [..]
  The USART can provide a clock to the smartcard through the SCLK output.
  In smartcard mode, SCLK is not associated to the communication but is simply derived
  from the internal peripheral input clock through a 5-bit prescaler.
  [..]
  (+) For the Smartcard mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length => Should be 9 bits (8 bits + parity)
      (++) Stop Bit
      (++) Parity: => Should be enabled

      (+++) +-------------------------------------------------------------+
      (+++) |   M bit |  PCE bit  |        SMARTCARD frame                |
      (+++) |---------------------|---------------------------------------|
      (+++) |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
      (+++) +-------------------------------------------------------------+

      (++) USART polarity
      (++) USART phase
      (++) USART LastBit
      (++) Receiver/transmitter modes
      (++) Prescaler
      (++) GuardTime
      (++) NACKState: The Smartcard NACK state

     (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
        (++) Word Length = 9 Bits
        (++) 1.5 Stop Bit
        (++) Even parity
        (++) BaudRate = 12096 baud
        (++) Tx and Rx enabled
  [..]
  Please refer to the ISO 7816-3 specification for more details.

    -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
        to use 1.5 stop bits for both transmitting and receiving to avoid switching
        between the two configurations.
  [..]
    The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration
    procedure (details for the procedure are available in reference manual (RM0329)).

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsc )

DeInitializes the USART SmartCard peripheral.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 303 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE, assert_param, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsc )

Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 237 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE, __HAL_SMARTCARD_ENABLE_IT, assert_param, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, SMARTCARD_InitTypeDef::GuardTime, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_NACK_STATE, SMARTCARD_HandleTypeDef::Lock, SMARTCARD_InitTypeDef::NACKState, SMARTCARD_InitTypeDef::Prescaler, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, and SMARTCARD_SetConfig().

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD MSP DeInit.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 353 of file stm32f4xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD MSP Init.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 338 of file stm32f4xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init().

HAL_StatusTypeDef HAL_SMARTCARD_ReInit ( SMARTCARD_HandleTypeDef * hsc )
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
This function handles SMARTCARD interrupt request.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.

Detailed Description

SMARTCARD Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
    [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) Non Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the HAL status.
           The end of the data processing will be indicated through the
           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
           will be executed respectively at the end of the Transmit or Receive process
           The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_SMARTCARD_Transmit()
        (++) HAL_SMARTCARD_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_SMARTCARD_Transmit_IT()
        (++) HAL_SMARTCARD_Receive_IT()
        (++) HAL_SMARTCARD_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_SMARTCARD_Transmit_DMA()
        (++) HAL_SMARTCARD_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SMARTCARD_TxCpltCallback()
        (++) HAL_SMARTCARD_RxCpltCallback()
        (++) HAL_SMARTCARD_ErrorCallback()

Function Documentation

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD error callbacks.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 851 of file stm32f4xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsc )

This function handles SMARTCARD interrupt request.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 746 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FEFLAG, __HAL_SMARTCARD_CLEAR_NEFLAG, __HAL_SMARTCARD_CLEAR_OREFLAG, __HAL_SMARTCARD_CLEAR_PEFLAG, __HAL_SMARTCARD_GET_IT_SOURCE, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_EndTransmit_IT(), SMARTCARD_FLAG_FE, SMARTCARD_FLAG_NE, SMARTCARD_FLAG_ORE, SMARTCARD_FLAG_PE, SMARTCARD_FLAG_RXNE, SMARTCARD_FLAG_TC, SMARTCARD_FLAG_TXE, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, SMARTCARD_IT_RXNE, SMARTCARD_IT_TC, SMARTCARD_IT_TXE, SMARTCARD_Receive_IT(), and SMARTCARD_Transmit_IT().

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 484 of file stm32f4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be received
Note:
When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
Return values:
HAL status

Definition at line 694 of file stm32f4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 587 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, and SMARTCARD_IT_RXNE.

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

Rx Transfer completed callbacks.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 836 of file stm32f4xx_hal_smartcard.c.

Referenced by SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 425 of file stm32f4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FLAG_TC, SMARTCARD_FLAG_TXE, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 635 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_FLAG_TC, SMARTCARD_HandleTypeDef::TxXferCount, SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 539 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, SMARTCARD_IT_TXE, SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

Tx Transfer completed callbacks.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 821 of file stm32f4xx_hal_smartcard.c.

Referenced by SMARTCARD_EndTransmit_IT().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

SMARTCARD State and Errors functions.

 ===============================================================================
                ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SmartCard.
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
     (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsc )

Return the SMARTCARD error code.

Parameters:
hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD.
Return values:
SMARTCARD Error Code

Definition at line 900 of file stm32f4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsc )

return the SMARTCARD state

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL state

Definition at line 885 of file stm32f4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, and SMARTCARD_HandleTypeDef::RxState.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Exported Functions

Modules | Functions
SMARTCARD Exported Functions
SMARTCARD

Modules

SmartCard Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

Functions

static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles SMARTCARD Communication Timeout.
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc)
Receive an amount of data in non blocking mode.
static void | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD peripheral.

Function Documentation

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 957 of file stm32f4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 935 of file stm32f4xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 915 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_IT_TC, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wraps up transmission in non blocking mode.

Parameters:
hsmartcard,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1077 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), SMARTCARD_IT_ERR, and SMARTCARD_IT_TC.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_Receive_IT ( SMARTCARD_HandleTypeDef * hsc ) [static]

Receive an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 1099 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, and SMARTCARD_IT_RXNE.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsc ) [static]

Configure the SMARTCARD peripheral.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 1141 of file stm32f4xx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK_STATE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_WORD_LENGTH, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKState, SMARTCARD_InitTypeDef::Parity, SMARTCARD_BRR, SMARTCARD_InitTypeDef::StopBits, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_Transmit_IT ( SMARTCARD_HandleTypeDef * hsc ) [static]

Send an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 1043 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_IT_TC, SMARTCARD_IT_TXE, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles SMARTCARD Communication Timeout.

Parameters:
hsc,: SMARTCARD handle
Flag,: specifies the SMARTCARD flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 978 of file stm32f4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __HAL_SMARTCARD_GET_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_IT_RXNE, and SMARTCARD_IT_TXE.

Referenced by HAL_SMARTCARD_Receive(), and HAL_SMARTCARD_Transmit().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Exported Types

Data Structures | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...

Enumeration Type Documentation

enum HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State structures definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_SMARTCARD_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_SMARTCARD_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_SMARTCARD_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_SMARTCARD_STATE_ERROR

Error Value is allowed for gState only

Definition at line 148 of file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32f4xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | Prescaler
uint32_t | GuardTime
uint32_t | NACKState

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 65 of file stm32f4xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_InitTypeDef::BaudRate

This member configures the SmartCard communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5

Definition at line 67 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 94 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 91 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 88 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time value in terms of number of baud clocks

Definition at line 103 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint32_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Mode

Definition at line 85 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::NACKState

Specifies the SmartCard NACK Transmission state. This parameter can be a value of SMARTCARD NACK State

Definition at line 105 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 78 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler value used for dividing the system clock to provide the smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency. This parameter can be a value of SMARTCARD Prescaler

Definition at line 98 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of SMARTCARD Number of Stop Bits

Definition at line 75 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of SMARTCARD Word Length

Definition at line 72 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_smartcard.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32f4xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 172 of file stm32f4xx_hal_smartcard.h.

Field Documentation

__IO uint32_t SMARTCARD_HandleTypeDef::ErrorCode

Definition at line 203 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_DMAError().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::gState

Definition at line 196 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_EndTransmit_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmarx

Definition at line 192 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmatx

Definition at line 190 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA().

SMARTCARD_InitTypeDef SMARTCARD_HandleTypeDef::Init

Definition at line 176 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_SetConfig().

USART_TypeDef* SMARTCARD_HandleTypeDef::Instance

Definition at line 174 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_Receive_IT(), SMARTCARD_SetConfig(), and SMARTCARD_Transmit_IT().

HAL_LockTypeDef SMARTCARD_HandleTypeDef::Lock

Definition at line 194 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint8_t* SMARTCARD_HandleTypeDef::pRxBuffPtr

Definition at line 184 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

uint8_t* SMARTCARD_HandleTypeDef::pTxBuffPtr

Definition at line 178 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::RxState

Definition at line 200 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

uint16_t SMARTCARD_HandleTypeDef::RxXferCount

Definition at line 188 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::RxXferSize

Definition at line 186 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferCount

Definition at line 182 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferSize

Definition at line 180 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_smartcard.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Error Code

Defines
SMARTCARD Error Code
SMARTCARD Exported constants

SMARTCARD Error Code. More...

Defines

#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)

Detailed Description

SMARTCARD Error Code.

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 224 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)

Frame error

Definition at line 222 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 221 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 219 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 223 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 220 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

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STM32F410Rx HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported constants

Defines

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 232 of file stm32f4xx_hal_smartcard.h.

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STM32F410Rx HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported constants

Defines

#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

Definition at line 240 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Definition at line 241 of file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 249 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 250 of file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Mode

Defines
SMARTCARD Mode
SMARTCARD Exported constants

Defines

#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 258 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 259 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 260 of file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported constants

Defines

#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000U)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Definition at line 269 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000U)

Definition at line 268 of file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000U)

Definition at line 277 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Definition at line 278 of file stm32f4xx_hal_smartcard.h.

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STM32F410Rx HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000U)

Definition at line 286 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Definition at line 287 of file stm32f4xx_hal_smartcard.h.

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STM32F410Rx HAL User Manual: SMARTCARD NACK State

Defines
SMARTCARD NACK State
SMARTCARD Exported constants

Defines

#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000U)

Definition at line 296 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

Definition at line 295 of file stm32f4xx_hal_smartcard.h.

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STM32F410Rx HAL User Manual: SMARTCARD DMA requests

Defines
SMARTCARD DMA requests
SMARTCARD Exported constants

Defines

#define | SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define | SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)

Definition at line 305 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)

Definition at line 304 of file stm32f4xx_hal_smartcard.h.

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STM32F410Rx HAL User Manual: SMARTCARD Prescaler

Defines
SMARTCARD Prescaler
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000AU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000BU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000CU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000DU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000EU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000FU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001AU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001BU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001CU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001DU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001EU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001FU)

Define Documentation

#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005U)

SYSCLK divided by 10

Definition at line 317 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006U)

SYSCLK divided by 12

Definition at line 318 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007U)

SYSCLK divided by 14

Definition at line 319 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008U)

SYSCLK divided by 16

Definition at line 320 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009U)

SYSCLK divided by 18

Definition at line 321 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001U)

SYSCLK divided by 2

Definition at line 313 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000AU)

SYSCLK divided by 20

Definition at line 322 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000BU)

SYSCLK divided by 22

Definition at line 323 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000CU)

SYSCLK divided by 24

Definition at line 324 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000DU)

SYSCLK divided by 26

Definition at line 325 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000EU)

SYSCLK divided by 28

Definition at line 326 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000FU)

SYSCLK divided by 30

Definition at line 327 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010U)

SYSCLK divided by 32

Definition at line 328 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011U)

SYSCLK divided by 34

Definition at line 329 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012U)

SYSCLK divided by 36

Definition at line 330 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013U)

SYSCLK divided by 38

Definition at line 331 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002U)

SYSCLK divided by 4

Definition at line 314 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014U)

SYSCLK divided by 40

Definition at line 332 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015U)

SYSCLK divided by 42

Definition at line 333 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016U)

SYSCLK divided by 44

Definition at line 334 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017U)

SYSCLK divided by 46

Definition at line 335 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018U)

SYSCLK divided by 48

Definition at line 336 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019U)

SYSCLK divided by 50

Definition at line 337 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001AU)

SYSCLK divided by 52

Definition at line 338 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001BU)

SYSCLK divided by 54

Definition at line 339 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001CU)

SYSCLK divided by 56

Definition at line 340 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001DU)

SYSCLK divided by 58

Definition at line 341 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003U)

SYSCLK divided by 6

Definition at line 315 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001EU)

SYSCLK divided by 60

Definition at line 342 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001FU)

SYSCLK divided by 62

Definition at line 343 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004U)

SYSCLK divided by 8

Definition at line 316 of file stm32f4xx_hal_smartcard.h.

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STM32F410Rx HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U)
#define | SMARTCARD_FLAG_TC ((uint32_t)0x00000040U)
#define | SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U)
#define | SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U)
#define | SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U)
#define | SMARTCARD_FLAG_NE ((uint32_t)0x00000004U)
#define | SMARTCARD_FLAG_FE ((uint32_t)0x00000002U)
#define | SMARTCARD_FLAG_PE ((uint32_t)0x00000001U)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002U)

Definition at line 359 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U)

Definition at line 356 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004U)

Definition at line 358 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U)

Definition at line 357 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001U)

Definition at line 360 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U)

Definition at line 355 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), and HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040U)

Definition at line 354 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), and HAL_SMARTCARD_Transmit_DMA().

#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U)

Definition at line 353 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), and HAL_SMARTCARD_Transmit().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Exported constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask in the XX register
  • Y : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR3 register

Define Documentation

#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 378 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Receive_IT().

#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 377 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 373 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Receive_IT().

#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 376 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 375 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Transmit_IT().

#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 374 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle gstate & RxState.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushs the Smartcard DR register.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified Smartcard pending flags.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables or disables the specified SmartCard interrupts.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
Checks whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Macro to enable the SMARTCARD's one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
Macro to disable the SMARTCARD's one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
Macros to enable or disable the SmartCard DMA request.
#define | __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 459 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified Smartcard pending flags.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_FLAG_TC: Transmission Complete flag.
  • SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun error) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register.
TXE flag is cleared only by a write to the USART_DR register.

Definition at line 437 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 483 of file stm32f4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 467 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 475 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                                \
    __IO uint32_t tmpreg = 0x00U;                    \
    tmpreg = (__HANDLE__)->Instance->SR;             \
    tmpreg = (__HANDLE__)->Instance->DR;             \
    UNUSED(tmpreg);                                  \
  } while(0)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 445 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
Return values:
None

Definition at line 539 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit().

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
                                                                 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))

Definition at line 498 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE | ( | __HANDLE__,
 |  | __REQUEST__
 | ) | ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))

Definition at line 549 of file stm32f4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE | ( | __HANDLE__,
 |  | __REQUEST__
 | ) | ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))

Macros to enable or disable the SmartCard DMA request.

Parameters:
__HANDLE__,: specifies the SmartCard Handle.
__REQUEST__,: specifies the SmartCard DMA request. This parameter can be one of the following values:
  • SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
  • SMARTCARD_DMAREQ_RX: SmartCard DMA receive request

Definition at line 548 of file stm32f4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
Return values:
None

Definition at line 532 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
                                                                 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))

Enables or disables the specified SmartCard interrupts.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__INTERRUPT__,: specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_IDLE: Idle line detection interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
  • SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)

Definition at line 496 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ ) ((__HANDLE__)->Instance->DR)

Flushs the Smartcard DR register.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.

Definition at line 404 of file stm32f4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_TXE: Transmit data register empty flag
  • SMARTCARD_FLAG_TC: Transmission Complete flag
  • SMARTCARD_FLAG_RXNE: Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE: Idle Line detection flag
  • SMARTCARD_FLAG_ORE: Overrun Error flag
  • SMARTCARD_FLAG_NE: Noise Error flag
  • SMARTCARD_FLAG_FE: Framing Error flag
  • SMARTCARD_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 420 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) | (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))

Checks whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the SmartCard Handle.
__IT__,: specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_IDLE: Idle line detection interrupt
  • SMARTCARD_IT_ERR: Error interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 513 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))

Macro to disable the SMARTCARD's one bit sample method.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 525 of file stm32f4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Macro to enable the SMARTCARD's one bit sample method.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 519 of file stm32f4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                        \
                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
                                                          } while(0)

Reset SMARTCARD handle gstate & RxState.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 396 of file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_IT_MASK
SMARTCARD interruptions flag mask.
#define | SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
#define | SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | SMARTCARD_BRR(_PCLK_, _BAUD_)
#define | SMARTCARD_CR1_REG_INDEX 1U
#define | SMARTCARD_CR3_REG_INDEX 3U

Define Documentation

#define SMARTCARD_BRR | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
                                                  (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
                                                  (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 623 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_CR1_REG_INDEX 1U

Definition at line 627 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_CR3_REG_INDEX 3U

Definition at line 628 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_DIV | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(4U*(_BAUD_)))

Definition at line 618 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_DIVFRAQ | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 620 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_DIVMANT | ( | _PCLK_,
 |  | _BAUD_
 | ) | (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)

Definition at line 619 of file stm32f4xx_hal_smartcard.h.

#define SMARTCARD_IT_MASK
Value:
((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
                                        USART_CR1_IDLEIE | USART_CR3_EIE )

SMARTCARD interruptions flag mask.

Definition at line 615 of file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
#define | IS_SMARTCARD_STOPBITS(STOPBITS)
#define | IS_SMARTCARD_PARITY(PARITY)
#define | IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x000000U))
#define | IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
#define | IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
#define | IS_SMARTCARD_LASTBIT(LASTBIT)
#define | IS_SMARTCARD_NACK_STATE(NACK)
#define | IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)

Define Documentation

#define IS_SMARTCARD_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 10500001U)

Definition at line 649 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_LASTBIT ( LASTBIT )
Value:
(((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
                                       ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))

Definition at line 645 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( MODE ) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x000000U))

Definition at line 642 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK_STATE ( NACK )
Value:
(((NACK) == SMARTCARD_NACK_ENABLE) || \
                                       ((NACK) == SMARTCARD_NACK_DISABLE))

Definition at line 647 of file stm32f4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_PARITY ( PARITY )
Value:
(((PARITY) == SMARTCARD_PARITY_EVEN) || \
                                     ((PARITY) == SMARTCARD_PARITY_ODD))

Definition at line 640 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( CPHA ) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))

Definition at line 644 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( CPOL ) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))

Definition at line 643 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
                                         ((STOPBITS) == SMARTCARD_STOPBITS_1_5))

Definition at line 638 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( LENGTH ) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)

Definition at line 637 of file stm32f4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SMARTCARD Private Functions

SMARTCARD Private Functions
SMARTCARD
Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPDIFRX

SPDIFRX
STM32F4xx_HAL_Driver

SPDIFRX HAL module driver. More...

SPDIFRX HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 100U

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100U

Definition at line 172 of file stm32f4xx_hal_spi.c.

Referenced by SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De Initialize the SPI peripheral.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 341 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 259 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_ERROR_NONE, HAL_SPI_MspInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, SPI_InitTypeDef::NSS, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, SPI_TIMODE_DISABLE, __SPI_HandleTypeDef::State, and SPI_InitTypeDef::TIMode.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 391 of file stm32f4xx_hal_spi.c.

Referenced by HAL_SPI_DeInit().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 375 of file stm32f4xx_hal_spi.c.

Referenced by HAL_SPI_Init().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1529 of file stm32f4xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1549 of file stm32f4xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1569 of file stm32f4xx_hal_spi.c.

References HAL_DMA_Abort(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1754 of file stm32f4xx_hal_spi.c.

Referenced by HAL_SPI_IRQHandler(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 1600 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxISR.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 596 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CheckFlag_BSY(), SPI_CheckForDisablingSPI(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1332 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_ENABLE, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1072 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1679 of file stm32f4xx_hal_spi.c.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1724 of file stm32f4xx_hal_spi.c.

Referenced by SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 446 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CheckFlag_BSY(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_FLAG_TXE, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1245 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 982 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 799 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CheckFlag_BSY(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DIRECTION_2LINES, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1423 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Return values:
HAL status

Definition at line 1163 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1664 of file stm32f4xx_hal_spi.c.

Referenced by SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1709 of file stm32f4xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1694 of file stm32f4xx_hal_spi.c.

Referenced by SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1739 of file stm32f4xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitReceiveCplt().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 1803 of file stm32f4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 1791 of file stm32f4xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U
}
HAL SPI State structure definition. More...

Typedef Documentation

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

Definition at line 108 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32f4xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial

Detailed Description

SPI Configuration Structure definition.

Definition at line 65 of file stm32f4xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 86 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 79 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 76 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 98 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535

Definition at line 101 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 73 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), and HAL_SPI_TransmitReceive_IT().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 70 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CheckForDisablingSPI(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 92 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 67 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CheckForDisablingSPI(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 82 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 95 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_spi.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32f4xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SPI handle Structure definition.

Definition at line 122 of file stm32f4xx_hal_spi.h.

Field Documentation

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

Definition at line 152 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CheckFlag_BSY(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

Definition at line 146 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

Definition at line 144 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

Definition at line 126 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CheckForDisablingSPI(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

Definition at line 124 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Definition at line 148 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Definition at line 134 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Definition at line 128 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

Definition at line 140 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferCount

Definition at line 138 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

Definition at line 136 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

Definition at line 150 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

Definition at line 142 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

uint16_t __SPI_HandleTypeDef::TxXferCount

Definition at line 132 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

Definition at line 130 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_spi.h
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U)
#define | HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U)
#define | HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U)
#define | HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U)
#define | HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U)

Define Documentation

#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U)

CRC error

Definition at line 170 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 173 of file stm32f4xx_hal_spi.h.

Referenced by SPI_DMAError().

#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U)

Flag: RXNE,TXE, BSY

Definition at line 174 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CheckFlag_BSY(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U)

FRE error

Definition at line 172 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U)

MODF error

Definition at line 169 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 168 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U)

OVR error

Definition at line 171 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE ((uint32_t)0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 183 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CheckForDisablingSPI(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE ((uint32_t)0x00000000U)

Definition at line 182 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 193 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_CheckForDisablingSPI(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)

Definition at line 191 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 192 of file stm32f4xx_hal_spi.h.

Referenced by SPI_CheckForDisablingSPI(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_8BIT ((uint32_t)0x00000000U)
#define | SPI_DATASIZE_16BIT SPI_CR1_DFF

Define Documentation

#define SPI_DATASIZE_16BIT SPI_CR1_DFF

Definition at line 202 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U)

Definition at line 201 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW ((uint32_t)0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 211 of file stm32f4xx_hal_spi.h.

#define SPI_POLARITY_LOW ((uint32_t)0x00000000U)

Definition at line 210 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U)

Definition at line 219 of file stm32f4xx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 220 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)

Define Documentation

#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)

Definition at line 229 of file stm32f4xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)

Definition at line 230 of file stm32f4xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 228 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
#define | SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
#define | SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
#define | SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
#define | SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
#define | SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
#define | SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)

Definition at line 244 of file stm32f4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)

Definition at line 241 of file stm32f4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)

Definition at line 238 of file stm32f4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)

Definition at line 245 of file stm32f4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)

Definition at line 242 of file stm32f4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)

Definition at line 239 of file stm32f4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)

Definition at line 243 of file stm32f4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)

Definition at line 240 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 254 of file stm32f4xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)

Definition at line 253 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF

Define Documentation

#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)

Definition at line 262 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_TIMODE_ENABLE SPI_CR2_FRF

Definition at line 263 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)

Definition at line 271 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 272 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 282 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 281 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_CloseRx_ISR(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 280 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 292 of file stm32f4xx_hal_spi.h.

Referenced by SPI_CheckFlag_BSY().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 293 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 296 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 294 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 295 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 290 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 291 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 363 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ )
Value:
do{                                              \
  __IO uint32_t tmpreg = 0x00U;                    \
  tmpreg = (__HANDLE__)->Instance->SR;             \
  UNUSED(tmpreg);                                  \
  }while(0)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 396 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg = 0x00U;                  \
    tmpreg = (__HANDLE__)->Instance->SR;           \
    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
    UNUSED(tmpreg);                                \
  } while(0)

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 370 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg = 0x00U;                  \
    tmpreg = (__HANDLE__)->Instance->DR;           \
    tmpreg = (__HANDLE__)->Instance->SR;           \
    UNUSED(tmpreg);                                \
  } while(0)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 383 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))

Disable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 415 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Init(), SPI_CheckForDisablingSPI(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))

Definition at line 328 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 408 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable or disable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 327 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 356 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__,: specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 340 of file stm32f4xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)

Reset SPI handle state.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 315 of file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Definition at line 536 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
                           ((CPHA) == SPI_PHASE_2EDGE))

Definition at line 529 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
                           ((CPOL) == SPI_POLARITY_HIGH))

Definition at line 526 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( CALCULATION )
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

Definition at line 551 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))

Definition at line 554 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_8BIT))

Definition at line 523 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)        || \
                                ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
                                ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 514 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( MODE ) ((MODE) == SPI_DIRECTION_2LINES)

Definition at line 518 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)  || \
                                                ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 520 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                               ((BIT) == SPI_FIRSTBIT_LSB))

Definition at line 545 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_MODE_SLAVE) || \
                           ((MODE) == SPI_MODE_MASTER))

Definition at line 511 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT)       || \
                         ((NSS) == SPI_NSS_HARD_INPUT) || \
                         ((NSS) == SPI_NSS_HARD_OUTPUT))

Definition at line 532 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( MODE )
Value:
(((MODE) == SPI_TIMODE_DISABLE) || \
                             ((MODE) == SPI_TIMODE_ENABLE))

Definition at line 548 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))

Set the SPI receive-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 501 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 494 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)

Reset the CRC calculation of the SPI.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 508 of file stm32f4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_CheckForDisablingSPI (SPI_HandleTypeDef *hspi)
Handle to disable SPI in specific condition.
static HAL_StatusTypeDef | SPI_CheckFlag_BSY (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle to check BSY flag before start a new transaction.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2153 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2061 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2211 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2122 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static HAL_StatusTypeDef SPI_CheckFlag_BSY | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle to check BSY flag before start a new transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout,: Timeout duration
Tickstart,: tick start value
Return values:
HAL status

Definition at line 2472 of file stm32f4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

static HAL_StatusTypeDef SPI_CheckForDisablingSPI ( SPI_HandleTypeDef * hspi ) [static]

Handle to disable SPI in specific condition.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 2454 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, and SPI_MODE_MASTER.

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), and SPI_DMAReceiveCplt().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2546 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, SPI_CheckForDisablingSPI(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2489 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), SPI_CheckFlag_BSY(), SPI_DEFAULT_TIMEOUT, SPI_FLAG_CRCERR, SPI_IT_ERR, and __SPI_HandleTypeDef::State.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2588 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_CheckFlag_BSY(), SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_TXE, and __SPI_HandleTypeDef::State.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2043 of file stm32f4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2017 of file stm32f4xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback().

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2004 of file stm32f4xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback().

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2030 of file stm32f4xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback().

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1872 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CheckForDisablingSPI(), SPI_CRCCALCULATION_ENABLE, SPI_DEFAULT_TIMEOUT, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1828 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SPI_CheckFlag_BSY(), SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1938 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CheckFlag_BSY(), SPI_CRCCALCULATION_ENABLE, SPI_DEFAULT_TIMEOUT, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2321 of file stm32f4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), and SPI_CRCCALCULATION_ENABLE.

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2265 of file stm32f4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), and SPI_CRCCALCULATION_ENABLE.

Referenced by HAL_SPI_Receive_IT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2378 of file stm32f4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2354 of file stm32f4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag,: SPI flag to check
State,: flag state to check
Timeout,: Timeout duration
Tickstart,: tick start value
Return values:
HAL status

Definition at line 2408 of file stm32f4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CheckFlag_BSY(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SRAM

SRAM
STM32F4xx_HAL_Driver

SRAM driver modules. More...

SRAM driver modules.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Time Base functions

Functions
Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 247 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 208 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 290 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 275 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 305 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 396 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 353 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 329 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 441 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 374 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Time Output Compare functions

Functions
Time Output Compare functions
TIM Exported Functions

Time Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

Time Output Compare functions.

  ==============================================================================
                  ##### Time Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the Time Output Compare.
    (+) Stop the Time Output Compare.
    (+) Start the Time Output Compare and enable interrupt.
    (+) Stop the Time Output Compare and disable interrupt.
    (+) Start the Time Output Compare and enable DMA transfer.
    (+) Stop the Time Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 529 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 490 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 572 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 557 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 593 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 795 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 659 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 626 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 913 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 726 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Time PWM functions

Functions
Time PWM functions
TIM Exported Functions

Time PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

Time PWM functions.

  ==============================================================================
                          ##### Time PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM OPWM.
    (+) De-initialize the TIM PWM.
    (+) Start the Time PWM.
    (+) Stop the Time PWM.
    (+) Start the Time PWM and enable interrupt.
    (+) Stop the Time PWM and disable interrupt.
    (+) Start the Time PWM and enable DMA transfer.
    (+) Stop the Time PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1041 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1002 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1084 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1069 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1105 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1310 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1174 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1138 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1428 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1241 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Time Input Capture functions

Functions
Time Input Capture functions
TIM Exported Functions

Time Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.

Detailed Description

Time Input Capture functions.

  ==============================================================================
              ##### Time Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the Time Input Capture.
   (+) Stop the Time Input Capture.
   (+) Start the Time Input Capture and enable interrupt.
   (+) Stop the Time Input Capture and disable interrupt.
   (+) Start the Time Input Capture and enable DMA transfer.
   (+) Stop the Time Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1556 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 1517 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1599 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM INput Capture MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1584 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1620 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement on in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 1797 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1674 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1647 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement on in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1911 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1734 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Time One Pulse functions

Functions
Time One Pulse functions
TIM Exported Functions

Time One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

Time One Pulse functions.

  ==============================================================================
                        ##### Time One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the Time One Pulse.
    (+) Stop the Time One Pulse.
    (+) Start the Time One Pulse and enable interrupt.
    (+) Stop the Time One Pulse and disable interrupt.
    (+) Start the Time One Pulse and enable DMA transfer.
    (+) Stop the Time One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 2045 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OnePulseMode,: Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 1999 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2088 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2073 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2107 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2175 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be disable. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2141 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel : TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2215 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Time Encoder functions

Functions
Time Encoder functions
TIM Exported Functions

Time Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

Time Encoder functions.

  ==============================================================================
                          ##### Time Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the Time Encoder.
    (+) Stop the Time Encoder.
    (+) Start the Time Encoder and enable interrupt.
    (+) Stop the Time Encoder and disable interrupt.
    (+) Start the Time Encoder and enable DMA transfer.
    (+) Stop the Time Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 2364 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 2275 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_ENCODER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2407 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2392 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2427 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1,: The destination Buffer address for IC1.
pData2,: The destination Buffer address for IC2.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2618 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2514 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2470 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2736 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, and TIM_DMA_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2563 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 2799 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutationCallback(), TIM_HandleTypeDef::Instance, TIM_FLAG_BREAK, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, and TIM_IT_UPDATE.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIM Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
   (+) Configure External Clock source.
   (+) Configure Complementary channels, break features and dead time.
   (+) Configure Master and the Slave synchronization.
   (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sClockSourceConfig,: pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 3939 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sClearInputConfig,: pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel,: specifies the TIM Channel. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3836 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CLEARINPUTSOURCE_ETR, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
TI1_Selection,: Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4100 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data read. This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources. This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3592 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstRequestSrc,: TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 3725 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data write. This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources. This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3367 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
BurstRequestSrc,: TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 3499 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
EventSource,: specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
Note:
TIM6 and TIM7 can only generate an update event.
TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
Return values:
HAL status

Definition at line 3798 of file stm32f4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Input Capture configuration structure
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3032 of file stm32f4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Output Compare configuration structure
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2962 of file stm32f4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM One Pulse configuration structure
OutputChannel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 3230 of file stm32f4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM PWM configuration structure
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3129 of file stm32f4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channels to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 4207 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4133 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim,: TIM handle.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4168 of file stm32f4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) Timer Period elapsed callback
   (+) Timer Output Compare callback
   (+) Timer Input capture callback
   (+) Timer Trigger callback
   (+) Timer Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4369 of file stm32f4xx_hal_tim.c.

Referenced by TIM_DMAError().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4324 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMACaptureCplt().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4309 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4294 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMAPeriodElapsedCplt().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4339 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMADelayPulseCplt().

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 4354 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMATriggerCplt().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
TIM Exported Functions

Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4402 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4457 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4435 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM OC state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4413 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4446 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 4424 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Exported Functions

Modules | Functions
TIM Exported Functions
TIM

Modules

Time Base functions

Time Base functions.

Time Output Compare functions

Time Output Compare functions.

Time PWM functions

Time PWM functions.

Time Input Capture functions

Time Input Capture functions.

Time One Pulse functions

Time One Pulse functions.

Time Encoder functions

Time Encoder functions.

TIM IRQ handler management

IRQ handler management.

Peripheral Control functions

Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

Peripheral State functions

Peripheral State functions.

Functions

void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 4 configuration.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Time Output Compare 4 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
Selects the Input Trigger source.
static void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM peripheral
Structure,: pointer on TIM Time Base required parameters
Return values:
None

Definition at line 4471 of file stm32f4xx_hal_tim.c.

References TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 4729 of file stm32f4xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4688 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4639 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4673 of file stm32f4xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4752 of file stm32f4xx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4767 of file stm32f4xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  | [static]

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx to select the TIM peripheral
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5358 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | TIM_ITRx
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
TIM_ITRx,: The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 5327 of file stm32f4xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

static void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Output Compare 1 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4782 of file stm32f4xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4572 of file stm32f4xx_hal_tim.c.

References assert_param, IS_TIM_OCN_POLARITY, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Output Compare 3 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4847 of file stm32f4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Output Compare 4 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4915 of file stm32f4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Time Output Compare 4 configuration.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sSlaveConfig,: The slave configuration structure
Return values:
None

Definition at line 4973 of file stm32f4xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5110 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 4530 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5193 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 5153 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel4 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 5236 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel3 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 5284 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Exported Types

Data Structures | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 277 of file stm32f4xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 265 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 65 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 77 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 70 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF.

Definition at line 73 of file stm32f4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU

Definition at line 67 of file stm32f4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
    Note:
    This parameter is valid only for TIM1 and TIM8.

Definition at line 80 of file stm32f4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 94 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 109 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 114 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM modes

Definition at line 96 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare N Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 118 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Output CompareN Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 105 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 102 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU

Definition at line 99 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 126 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 155 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 149 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 152 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 141 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM modes

Definition at line 128 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare N Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 145 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Output CompareN Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 137 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 134 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU

Definition at line 131 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 164 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 175 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 166 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 172 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 169 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 183 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 185 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 197 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 188 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 194 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 191 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 209 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 200 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 206 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 203 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 216 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 224 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity. This parameter can be a value of TIM Clock Polarity

Definition at line 220 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler. This parameter can be a value of TIM Clock Prescaler

Definition at line 222 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources. This parameter can be a value of TIM Clock Source

Definition at line 218 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

Clear Input Configuration Handle Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

Clear Input Configuration Handle Structure definition.

Definition at line 231 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 241 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity. This parameter can be a value of TIM Clear Input Polarity

Definition at line 237 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler. This parameter can be a value of TIM Clear Input Prescaler

Definition at line 239 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources. This parameter can be a value of TIM Clear Input Source

Definition at line 235 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state. This parameter can be ENABLE or DISABLE

Definition at line 233 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 248 of file stm32f4xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 251 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave Mode

Definition at line 249 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 257 of file stm32f4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 253 of file stm32f4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 255 of file stm32f4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32f4xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 289 of file stm32f4xx_hal_tim.h.

Field Documentation

HAL_TIM_ActiveChannel TIM_HandleTypeDef::Channel

Active channel

Definition at line 293 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

DMA_HandleTypeDef* TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a DMA Handle index

Definition at line 294 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

TIM_Base_InitTypeDef TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 292 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* TIM_HandleTypeDef::Instance

Register base address

Definition at line 291 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef TIM_HandleTypeDef::Lock

Locking object

Definition at line 296 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), and HAL_TIM_PWM_Init().

__IO HAL_TIM_StateTypeDef TIM_HandleTypeDef::State

TIM operation state

Definition at line 297 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_RemapConfig(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), and TIMEx_DMACommutationCplt().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Input Channel Polarity

Defines
TIM Input Channel Polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 313 of file stm32f4xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)

Polarity for TIx source

Definition at line 312 of file stm32f4xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U)

Polarity for TIx source

Definition at line 311 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x00000000U)

Define Documentation

#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)

Polarity for ETR source

Definition at line 321 of file stm32f4xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x00000000U)

Polarity for ETR source

Definition at line 322 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

Define Documentation

#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x00000000U)

No prescaler is used

Definition at line 330 of file stm32f4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)

ETR input source is divided by 2

Definition at line 331 of file stm32f4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)

ETR input source is divided by 4

Definition at line 332 of file stm32f4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

ETR input source is divided by 8

Definition at line 333 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Definition at line 343 of file stm32f4xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Definition at line 344 of file stm32f4xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Definition at line 345 of file stm32f4xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Definition at line 342 of file stm32f4xx_hal_tim.h.

#define TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)

Definition at line 341 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)

Definition at line 353 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)

Definition at line 354 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Definition at line 355 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Output Compare and PWM modes

Defines
TIM Output Compare and PWM modes
TIM Exported Constants

Defines

#define | TIM_OCMODE_TIMING ((uint32_t)0x00000000U)
#define | TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)

Define Documentation

#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)

Definition at line 364 of file stm32f4xx_hal_tim.h.

#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Definition at line 369 of file stm32f4xx_hal_tim.h.

#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)

Definition at line 370 of file stm32f4xx_hal_tim.h.

#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)

Definition at line 365 of file stm32f4xx_hal_tim.h.

#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Definition at line 367 of file stm32f4xx_hal_tim.h.

#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)

Definition at line 368 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_TIMING ((uint32_t)0x00000000U)

Definition at line 363 of file stm32f4xx_hal_tim.h.

#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)

Definition at line 366 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE ((uint32_t)0x00000000U)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Define Documentation

#define TIM_OCFAST_DISABLE ((uint32_t)0x00000000U)

Definition at line 379 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Definition at line 380 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Define Documentation

#define TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)

Definition at line 388 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Definition at line 389 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Output CompareN Polarity

Defines
TIM Output CompareN Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Define Documentation

#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x00000000U)

Definition at line 397 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Definition at line 398 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x00000000U)

Define Documentation

#define TIM_OCIDLESTATE_RESET ((uint32_t)0x00000000U)

Definition at line 407 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)

Definition at line 406 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Output Compare N Idle State

Defines
TIM Output Compare N Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x00000000U)

Define Documentation

#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x00000000U)

Definition at line 416 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)

Definition at line 415 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Channel

Defines
TIM Channel
TIM Exported Constants

Defines

#define | TIM_CHANNEL_1 ((uint32_t)0x00000000U)
#define | TIM_CHANNEL_2 ((uint32_t)0x00000004U)
#define | TIM_CHANNEL_3 ((uint32_t)0x00000008U)
#define | TIM_CHANNEL_4 ((uint32_t)0x0000000CU)
#define | TIM_CHANNEL_ALL ((uint32_t)0x00000018U)

Define Documentation

#define TIM_CHANNEL_1 ((uint32_t)0x00000000U)

Definition at line 424 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_2 ((uint32_t)0x00000004U)

Definition at line 425 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_3 ((uint32_t)0x00000008U)

Definition at line 426 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_4 ((uint32_t)0x0000000CU)

Definition at line 427 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_ALL ((uint32_t)0x00000018U)

Definition at line 428 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

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STM32F410Rx HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Definition at line 439 of file stm32f4xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Definition at line 438 of file stm32f4xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Definition at line 437 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

Define Documentation

#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 447 of file stm32f4xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 449 of file stm32f4xx_hal_tim.h.

#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 451 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

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STM32F410Rx HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 ((uint32_t)0x00000000U)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Define Documentation

#define TIM_ICPSC_DIV1 ((uint32_t)0x00000000U)

Capture performed each time an edge is detected on the capture input

Definition at line 460 of file stm32f4xx_hal_tim.h.

#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)

Capture performed once every 2 events

Definition at line 461 of file stm32f4xx_hal_tim.h.

#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)

Capture performed once every 4 events

Definition at line 462 of file stm32f4xx_hal_tim.h.

#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Capture performed once every 8 events

Definition at line 463 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_OPMODE_REPETITIVE ((uint32_t)0x00000000U)

Definition at line 472 of file stm32f4xx_hal_tim.h.

#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)

Definition at line 471 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)

Definition at line 480 of file stm32f4xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Definition at line 482 of file stm32f4xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)

Definition at line 481 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Interrupt definition

Defines
TIM Interrupt definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)

Define Documentation

#define TIM_IT_BREAK (TIM_DIER_BIE)

Definition at line 498 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 (TIM_DIER_CC1IE)

Definition at line 492 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 (TIM_DIER_CC2IE)

Definition at line 493 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 (TIM_DIER_CC3IE)

Definition at line 494 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 (TIM_DIER_CC4IE)

Definition at line 495 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_COM (TIM_DIER_COMIE)

Definition at line 496 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define TIM_IT_TRIGGER (TIM_DIER_TIE)

Definition at line 497 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_IT_UPDATE (TIM_DIER_UIE)

Definition at line 491 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

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STM32F410Rx HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x00000000U)

Definition at line 507 of file stm32f4xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)

Definition at line 506 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM DMA sources

Defines
TIM DMA sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)

Define Documentation

#define TIM_DMA_CC1 (TIM_DIER_CC1DE)

Definition at line 516 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 (TIM_DIER_CC2DE)

Definition at line 517 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 (TIM_DIER_CC3DE)

Definition at line 518 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 (TIM_DIER_CC4DE)

Definition at line 519 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_COM (TIM_DIER_COMDE)

Definition at line 520 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_TRIGGER (TIM_DIER_TDE)

Definition at line 521 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_DMA_UPDATE (TIM_DIER_UDE)

Definition at line 515 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Event Source

Defines
TIM Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

Definition at line 536 of file stm32f4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

Definition at line 530 of file stm32f4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

Definition at line 531 of file stm32f4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

Definition at line 532 of file stm32f4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

Definition at line 533 of file stm32f4xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

Definition at line 534 of file stm32f4xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

Definition at line 535 of file stm32f4xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Definition at line 529 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Flag definition

Defines
TIM Flag definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Define Documentation

#define TIM_FLAG_BREAK (TIM_SR_BIF)

Definition at line 552 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 (TIM_SR_CC1IF)

Definition at line 546 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)

Definition at line 553 of file stm32f4xx_hal_tim.h.

#define TIM_FLAG_CC2 (TIM_SR_CC2IF)

Definition at line 547 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)

Definition at line 554 of file stm32f4xx_hal_tim.h.

#define TIM_FLAG_CC3 (TIM_SR_CC3IF)

Definition at line 548 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)

Definition at line 555 of file stm32f4xx_hal_tim.h.

#define TIM_FLAG_CC4 (TIM_SR_CC4IF)

Definition at line 549 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Definition at line 556 of file stm32f4xx_hal_tim.h.

#define TIM_FLAG_COM (TIM_SR_COMIF)

Definition at line 550 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_TRIGGER (TIM_SR_TIF)

Definition at line 551 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE (TIM_SR_UIF)

Definition at line 545 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

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STM32F410Rx HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x00000000U)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Definition at line 573 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)

Definition at line 564 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)

Definition at line 565 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x00000000U)

Definition at line 566 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)

Definition at line 567 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)

Definition at line 568 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Definition at line 569 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Definition at line 571 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)

Definition at line 570 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Definition at line 572 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

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STM32F410Rx HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 585 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 584 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 581 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 582 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 583 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 593 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 594 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 595 of file stm32f4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 596 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Clear Input Source

Defines
TIM Clear Input Source
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x00000001U)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x00000001U)

Definition at line 604 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x00000000U)

Definition at line 605 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 613 of file stm32f4xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 614 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 622 of file stm32f4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 623 of file stm32f4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 624 of file stm32f4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 625 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM OSSR OffState Selection for Run mode state

Defines
TIM OSSR OffState Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_OSSR_DISABLE ((uint32_t)0x00000000U)

Definition at line 634 of file stm32f4xx_hal_tim.h.

#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)

Definition at line 633 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM OSSI OffState Selection for Idle mode state

Defines
TIM OSSI OffState Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_OSSI_DISABLE ((uint32_t)0x00000000U)

Definition at line 643 of file stm32f4xx_hal_tim.h.

#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)

Definition at line 642 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Define Documentation

#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)

Definition at line 652 of file stm32f4xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)

Definition at line 653 of file stm32f4xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Definition at line 654 of file stm32f4xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)

Definition at line 651 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Break Input State

Defines
TIM Break Input State
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_BREAK_DISABLE ((uint32_t)0x00000000U)

Definition at line 662 of file stm32f4xx_hal_tim.h.

#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)

Definition at line 661 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Break Polarity

Defines
TIM Break Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x00000000U)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Define Documentation

#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Definition at line 671 of file stm32f4xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x00000000U)

Definition at line 670 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM AOE Bit State

Defines
TIM AOE Bit State
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U)

Definition at line 680 of file stm32f4xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)

Definition at line 679 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET ((uint32_t)0x00000000U)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Define Documentation

#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)

Definition at line 689 of file stm32f4xx_hal_tim.h.

#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 691 of file stm32f4xx_hal_tim.h.

#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)

Definition at line 692 of file stm32f4xx_hal_tim.h.

#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))

Definition at line 693 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))

Definition at line 694 of file stm32f4xx_hal_tim.h.

#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 695 of file stm32f4xx_hal_tim.h.

#define TIM_TRGO_RESET ((uint32_t)0x00000000U)

Definition at line 688 of file stm32f4xx_hal_tim.h.

#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)

Definition at line 690 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Slave Mode

Defines
TIM Slave Mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)
#define | TIM_SLAVEMODE_RESET ((uint32_t)0x00000004U)
#define | TIM_SLAVEMODE_GATED ((uint32_t)0x00000005U)
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)0x00000006U)
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x00000007U)

Define Documentation

#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)

Definition at line 703 of file stm32f4xx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x00000007U)

Definition at line 707 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED ((uint32_t)0x00000005U)

Definition at line 705 of file stm32f4xx_hal_tim.h.

#define TIM_SLAVEMODE_RESET ((uint32_t)0x00000004U)

Definition at line 704 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x00000006U)

Definition at line 706 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

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STM32F410Rx HAL User Manual: TIM Master Slave Mode

Defines
TIM Master Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x00000080U)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x00000000U)

Definition at line 716 of file stm32f4xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x00000080U)

Definition at line 715 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 ((uint32_t)0x00000000U)
#define | TIM_TS_ITR1 ((uint32_t)0x00000010U)
#define | TIM_TS_ITR2 ((uint32_t)0x00000020U)
#define | TIM_TS_ITR3 ((uint32_t)0x00000030U)
#define | TIM_TS_TI1F_ED ((uint32_t)0x00000040U)
#define | TIM_TS_TI1FP1 ((uint32_t)0x00000050U)
#define | TIM_TS_TI2FP2 ((uint32_t)0x00000060U)
#define | TIM_TS_ETRF ((uint32_t)0x00000070U)
#define | TIM_TS_NONE ((uint32_t)0x0000FFFFU)

Define Documentation

#define TIM_TS_ETRF ((uint32_t)0x00000070U)

Definition at line 731 of file stm32f4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 ((uint32_t)0x00000000U)

Definition at line 724 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 ((uint32_t)0x00000010U)

Definition at line 725 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 ((uint32_t)0x00000020U)

Definition at line 726 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 ((uint32_t)0x00000030U)

Definition at line 727 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE ((uint32_t)0x0000FFFFU)

Definition at line 732 of file stm32f4xx_hal_tim.h.

#define TIM_TS_TI1F_ED ((uint32_t)0x00000040U)

Definition at line 728 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 ((uint32_t)0x00000050U)

Definition at line 729 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 ((uint32_t)0x00000060U)

Definition at line 730 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 744 of file stm32f4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 743 of file stm32f4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 740 of file stm32f4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 741 of file stm32f4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 742 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 752 of file stm32f4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 753 of file stm32f4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 754 of file stm32f4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 755 of file stm32f4xx_hal_tim.h.

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STM32F410Rx HAL User Manual: TIM TI1 Selection

Defines
TIM TI1 Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x00000000U)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Define Documentation

#define TIM_TI1SELECTION_CH1 ((uint32_t)0x00000000U)

Definition at line 764 of file stm32f4xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Definition at line 765 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM DMA Base address

Defines
TIM DMA Base address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 (0x00000000U)
#define | TIM_DMABASE_CR2 (0x00000001U)
#define | TIM_DMABASE_SMCR (0x00000002U)
#define | TIM_DMABASE_DIER (0x00000003U)
#define | TIM_DMABASE_SR (0x00000004U)
#define | TIM_DMABASE_EGR (0x00000005U)
#define | TIM_DMABASE_CCMR1 (0x00000006U)
#define | TIM_DMABASE_CCMR2 (0x00000007U)
#define | TIM_DMABASE_CCER (0x00000008U)
#define | TIM_DMABASE_CNT (0x00000009U)
#define | TIM_DMABASE_PSC (0x0000000AU)
#define | TIM_DMABASE_ARR (0x0000000BU)
#define | TIM_DMABASE_RCR (0x0000000CU)
#define | TIM_DMABASE_CCR1 (0x0000000DU)
#define | TIM_DMABASE_CCR2 (0x0000000EU)
#define | TIM_DMABASE_CCR3 (0x0000000FU)
#define | TIM_DMABASE_CCR4 (0x00000010U)
#define | TIM_DMABASE_BDTR (0x00000011U)
#define | TIM_DMABASE_DCR (0x00000012U)
#define | TIM_DMABASE_OR (0x00000013U)

Define Documentation

#define TIM_DMABASE_ARR (0x0000000BU)

Definition at line 784 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_BDTR (0x00000011U)

Definition at line 790 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CCER (0x00000008U)

Definition at line 781 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CCMR1 (0x00000006U)

Definition at line 779 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CCMR2 (0x00000007U)

Definition at line 780 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CCR1 (0x0000000DU)

Definition at line 786 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CCR2 (0x0000000EU)

Definition at line 787 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CCR3 (0x0000000FU)

Definition at line 788 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CCR4 (0x00000010U)

Definition at line 789 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CNT (0x00000009U)

Definition at line 782 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CR1 (0x00000000U)

Definition at line 773 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_CR2 (0x00000001U)

Definition at line 774 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_DCR (0x00000012U)

Definition at line 791 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_DIER (0x00000003U)

Definition at line 776 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_EGR (0x00000005U)

Definition at line 778 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_OR (0x00000013U)

Definition at line 792 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_PSC (0x0000000AU)

Definition at line 783 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_RCR (0x0000000CU)

Definition at line 785 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_SMCR (0x00000002U)

Definition at line 775 of file stm32f4xx_hal_tim.h.

#define TIM_DMABASE_SR (0x00000004U)

Definition at line 777 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)

Definition at line 809 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)

Definition at line 810 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)

Definition at line 811 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)

Definition at line 812 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)

Definition at line 813 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)

Definition at line 814 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)

Definition at line 815 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)

Definition at line 816 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)

Definition at line 817 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)

Definition at line 800 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)

Definition at line 801 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)

Definition at line 802 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)

Definition at line 803 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)

Definition at line 804 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)

Definition at line 805 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)

Definition at line 806 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)

Definition at line 807 of file stm32f4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)

Definition at line 808 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMA Handle index

Defines
DMA Handle index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000U)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001U)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002U)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003U)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004U)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005U)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006U)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001U)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 826 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002U)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 827 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003U)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 828 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004U)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 829 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005U)

Index of the DMA handle used for Commutation DMA requests

Definition at line 830 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006U)

Index of the DMA handle used for Trigger DMA requests

Definition at line 831 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000U)

Index of the DMA handle used for Update DMA requests

Definition at line 825 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Channel CC State

Defines
Channel CC State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE ((uint32_t)0x00000001U)
#define | TIM_CCx_DISABLE ((uint32_t)0x00000000U)
#define | TIM_CCxN_ENABLE ((uint32_t)0x00000004U)
#define | TIM_CCxN_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define TIM_CCx_DISABLE ((uint32_t)0x00000000U)

Definition at line 840 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE ((uint32_t)0x00000001U)

Definition at line 839 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE ((uint32_t)0x00000000U)

Definition at line 842 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE ((uint32_t)0x00000004U)

Definition at line 841 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
Gets the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Definition at line 915 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Definition at line 918 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
                            { \
                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
                            } \
                          } \
                        } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 881 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Definition at line 913 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Definition at line 912 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 866 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Definition at line 911 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Definition at line 910 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Gets the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 1009 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Gets the TIM Clock Division value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 1033 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))

Gets the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
Return values:
None

Definition at line 974 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Gets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 990 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Definition at line 914 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

Gets the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
None

Definition at line 1070 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Definition at line 917 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Definition at line 920 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
                            { \
                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
                            } \
                          } \
                        } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 899 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 873 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

Reset TIM handle state.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 859 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                  \
                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
                          } while(0)

Sets the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__AUTORELOAD__,: specifies the Counter register new value.
Return values:
None

Definition at line 999 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                            \
                           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
                           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
                         }while(0)

Sets the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__,: Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Note:
The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
Return values:
None

Definition at line 1117 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                             \
                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
                          } while(0)

Sets the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__CKD__,: specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1
  • TIM_CLOCKDIVISION_DIV2
  • TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1022 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))

Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__COMPARE__,: specifies the Capture Compare register new value.
Return values:
None

Definition at line 960 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Sets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__COUNTER__,: specifies the Counter register new value.
Return values:
None

Definition at line 983 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
                          } while(0)

Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1053 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Definition at line 921 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): _ Counter overflow/underflow _ Setting the UG bit _ Update generation through the slave mode controller
Return values:
None

Definition at line 1098 of file stm32f4xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1084 of file stm32f4xx_hal_tim.h.

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))

Definition at line 941 of file stm32f4xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))

Definition at line 929 of file stm32f4xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))

Definition at line 935 of file stm32f4xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

Definition at line 923 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Private macros to check input parameters

Defines
TIM Private macros to check input parameters
TIM Private Macros

Defines

#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_CLOCKDIVISION_DIV(DIV)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_FAST_STATE(STATE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | IS_TIM_OCIDLE_STATE(STATE)
#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_CLOCKSOURCE(CLOCK)
#define | IS_TIM_CLOCKPOLARITY(POLARITY)
#define | IS_TIM_CLOCKPRESCALER(PRESCALER)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_CLEARINPUT_SOURCE(SOURCE)
#define | IS_TIM_CLEARINPUT_POLARITY(POLARITY)
#define | IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)
#define | IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_OSSR_STATE(STATE)
#define | IS_TIM_OSSI_STATE(STATE)
#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | IS_TIM_BREAK_STATE(STATE)
#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION)
#define | IS_TIM_TRIGGERPOLARITY(POLARITY)
#define | IS_TIM_TRIGGERPRESCALER(PRESCALER)
#define | IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_TI1SELECTION(TI1SELECTION)
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( STATE )
Value:
(((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1468 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1465 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( STATE )
Value:
(((STATE) == TIM_BREAK_ENABLE) || \
                                   ((STATE) == TIM_BREAK_DISABLE))

Definition at line 1462 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                  ((CHANNEL) == TIM_CHANNEL_2) || \
                                  ((CHANNEL) == TIM_CHANNEL_3) || \
                                  ((CHANNEL) == TIM_CHANNEL_4) || \
                                  ((CHANNEL) == TIM_CHANNEL_ALL))

Definition at line 1377 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( ICFILTER ) ((ICFILTER) <= 0x0FU)

Definition at line 1449 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                               ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1441 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1444 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
                                         ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))

Definition at line 1438 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( DIV )
Value:
(((DIV) == TIM_CLOCKDIVISION_DIV1) || \
                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1348 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( ICFILTER ) ((ICFILTER) <= 0x0FU)

Definition at line 1436 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1425 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1431 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( CLOCK )
Value:
(((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 1414 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                                ((CHANNEL) == TIM_CHANNEL_2) || \
                                                ((CHANNEL) == TIM_CHANNEL_3))

Definition at line 1386 of file stm32f4xx_hal_tim.h.

Referenced by TIM_CCxNChannelCmd().

#define IS_TIM_COUNTER_MODE ( MODE )
Value:
(((MODE) == TIM_COUNTERMODE_UP)              || \
                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1342 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DMA_BASE ( BASE )
Value:
(((BASE) == TIM_DMABASE_CR1) || \
                               ((BASE) == TIM_DMABASE_CR2) || \
                               ((BASE) == TIM_DMABASE_SMCR) || \
                               ((BASE) == TIM_DMABASE_DIER) || \
                               ((BASE) == TIM_DMABASE_SR) || \
                               ((BASE) == TIM_DMABASE_EGR) || \
                               ((BASE) == TIM_DMABASE_CCMR1) || \
                               ((BASE) == TIM_DMABASE_CCMR2) || \
                               ((BASE) == TIM_DMABASE_CCER) || \
                               ((BASE) == TIM_DMABASE_CNT) || \
                               ((BASE) == TIM_DMABASE_PSC) || \
                               ((BASE) == TIM_DMABASE_ARR) || \
                               ((BASE) == TIM_DMABASE_RCR) || \
                               ((BASE) == TIM_DMABASE_CCR1) || \
                               ((BASE) == TIM_DMABASE_CCR2) || \
                               ((BASE) == TIM_DMABASE_CCR3) || \
                               ((BASE) == TIM_DMABASE_CCR4) || \
                               ((BASE) == TIM_DMABASE_BDTR) || \
                               ((BASE) == TIM_DMABASE_DCR) || \
                               ((BASE) == TIM_DMABASE_OR))

Definition at line 1520 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_LENGTH ( LENGTH )
Value:
(((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1541 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_SOURCE ( SOURCE ) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))

Definition at line 1406 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( MODE )
Value:
(((MODE) == TIM_ENCODERMODE_TI1) || \
                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
                                   ((MODE) == TIM_ENCODERMODE_TI12))

Definition at line 1408 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( SOURCE ) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))

Definition at line 1412 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( STATE )
Value:
(((STATE) == TIM_OCFAST_DISABLE) || \
                                  ((STATE) == TIM_OCFAST_ENABLE))

Definition at line 1362 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_IC_FILTER ( ICFILTER ) ((ICFILTER) <= 0x0F)

Definition at line 1560 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_ICPOLARITY_RISING)   || \
                                      ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
                                      ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1390 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_ICPSC_DIV1) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV8))

Definition at line 1398 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
                                        ((SELECTION) == TIM_ICSELECTION_TRC))

Definition at line 1394 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                                           ((SELECTION) == TIM_TS_ITR1) || \
                                                           ((SELECTION) == TIM_TS_ITR2) || \
                                                           ((SELECTION) == TIM_TS_ITR3) || \
                                                           ((SELECTION) == TIM_TS_NONE))

Definition at line 1498 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define IS_TIM_LOCK_LEVEL ( LEVEL )
Value:
(((LEVEL) == TIM_LOCKLEVEL_OFF) || \
                                  ((LEVEL) == TIM_LOCKLEVEL_1) || \
                                  ((LEVEL) == TIM_LOCKLEVEL_2) || \
                                  ((LEVEL) == TIM_LOCKLEVEL_3))

Definition at line 1457 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( STATE )
Value:
(((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1486 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_TIMING)       || \
                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))

Definition at line 1355 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCPOLARITY_HIGH) || \
                                      ((POLARITY) == TIM_OCPOLARITY_LOW))

Definition at line 1365 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCIDLESTATE_SET) || \
                                    ((STATE) == TIM_OCIDLESTATE_RESET))

Definition at line 1371 of file stm32f4xx_hal_tim.h.

Referenced by TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))

Definition at line 1368 of file stm32f4xx_hal_tim.h.

Referenced by TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCNIDLESTATE_SET) || \
                                    ((STATE) == TIM_OCNIDLESTATE_RESET))

Definition at line 1374 of file stm32f4xx_hal_tim.h.

Referenced by TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                      ((CHANNEL) == TIM_CHANNEL_2))

Definition at line 1383 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( MODE )
Value:
(((MODE) == TIM_OPMODE_SINGLE) || \
                               ((MODE) == TIM_OPMODE_REPETITIVE))

Definition at line 1403 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( STATE )
Value:
(((STATE) == TIM_OSSI_ENABLE) || \
                                  ((STATE) == TIM_OSSI_DISABLE))

Definition at line 1454 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( STATE )
Value:
(((STATE) == TIM_OSSR_ENABLE) || \
                                  ((STATE) == TIM_OSSR_DISABLE))

Definition at line 1451 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PWM_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_PWM1) || \
                               ((MODE) == TIM_OCMODE_PWM2))

Definition at line 1352 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( MODE )
Value:
(((MODE) == TIM_SLAVEMODE_DISABLE) || \
                                 ((MODE) == TIM_SLAVEMODE_GATED) || \
                                 ((MODE) == TIM_SLAVEMODE_RESET) || \
                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))

Definition at line 1480 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TI1SELECTION ( TI1SELECTION )
Value:
(((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1517 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_TRGO_RESET) || \
                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
                                    ((SOURCE) == TIM_TRGO_OC1) || \
                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
                                    ((SOURCE) == TIM_TRGO_OC4REF))

Definition at line 1471 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                             ((SELECTION) == TIM_TS_ITR1) || \
                                             ((SELECTION) == TIM_TS_ITR2) || \
                                             ((SELECTION) == TIM_TS_ITR3) || \
                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
                                             ((SELECTION) == TIM_TS_TI1FP1) || \
                                             ((SELECTION) == TIM_TS_TI2FP2) || \
                                             ((SELECTION) == TIM_TS_ETRF))

Definition at line 1489 of file stm32f4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TRIGGERFILTER ( ICFILTER ) ((ICFILTER) <= 0x0FU)

Definition at line 1515 of file stm32f4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1504 of file stm32f4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1510 of file stm32f4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Mask Definition

Defines
TIM Mask Definition
TIM Private Macros

Defines

#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 1570 of file stm32f4xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 1571 of file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM peripheral
Structure,: pointer on TIM Time Base required parameters
Return values:
None

Definition at line 4471 of file stm32f4xx_hal_tim.c.

References TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 4729 of file stm32f4xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4688 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4639 of file stm32f4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 4673 of file stm32f4xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Output Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The output configuration structure
Return values:
None

Definition at line 4572 of file stm32f4xx_hal_tim.c.

References assert_param, IS_TIM_OCN_POLARITY, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 4530 of file stm32f4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Timer Hall Sensor functions

Functions
Timer Hall Sensor functions
TIM Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 232 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and create the associated handle.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sConfig,: TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 159 of file stm32f4xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIMEx_HallSensor_MspInit(), TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 275 of file stm32f4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 260 of file stm32f4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 290 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 386 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 334 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 312 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 434 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_DMA_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL status

Definition at line 359 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Timer Complementary Output Compare functions

Functions
Timer Complementary Output Compare functions
TIM Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 490 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 693 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 552 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 521 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 809 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 620 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Timer Complementary PWM functions

Functions
Timer Complementary PWM functions
TIM Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 909 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1111 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 970 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 939 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1227 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Channel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1038 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Timer Complementary One Pulse functions

Functions
Timer Complementary One Pulse functions
TIM Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1315 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be enabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1371 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1341 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
OutputChannel,: TIM Channel to be disabled. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1403 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIM Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
    (+) Configure External Clock source.
    (+) Configure Complementary channels, break features and dead time.
    (+) Configure Master and the Slave synchronization.
    (+) Configure the commutation event in case of use of the Hall sensor interface.
    (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sBreakDeadTimeConfig,: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
HAL status

Definition at line 1658 of file stm32f4xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
InputTrigger,: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource,: the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1472 of file stm32f4xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
: The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
InputTrigger,: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource,: the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1576 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_DMA, assert_param, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_DMAError(), TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
InputTrigger,: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource,: the Commutation Event source. This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1522 of file stm32f4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sMasterConfig,: pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1621 of file stm32f4xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterSlaveMode, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Remap,: specifies the TIM input remapping source. This parameter can be one of the following values:
  • TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
  • TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
  • TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
  • TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
  • TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
  • TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
  • TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
  • TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
  • TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
  • TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock (HSE divided by a programmable prescaler)
Return values:
HAL status

Definition at line 1713 of file stm32f4xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_REMAP, and TIM_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: Extension Callbacks functions

Functions
Extension Callbacks functions
TIM Exported Functions

Extension Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

Extension Callbacks functions.

  ==============================================================================
                    ##### Extension Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extension TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1772 of file stm32f4xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIMEx_CommutationCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non blocking mode.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 1757 of file stm32f4xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), and TIMEx_DMACommutationCplt().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1820 of file stm32f4xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Extension Peripheral State functions

Functions
Extension Peripheral State functions
TIM Exported Functions

Extension Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

Extension Peripheral State functions.

  ==============================================================================
                ##### Extension Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface state.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
HAL state

Definition at line 1805 of file stm32f4xx_hal_tim_ex.c.

References TIM_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: TIM Exported Functions

Modules | Functions
TIM Exported Functions
TIMEx

Modules

Timer Hall Sensor functions

Timer Hall Sensor functions.

Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Timer Complementary PWM functions

Timer Complementary PWM functions.

Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Peripheral Control functions

Peripheral Control functions.

Extension Callbacks functions

Extension Callbacks functions.

Extension Peripheral State functions

Extension Peripheral State functions.

Functions

void TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Function Documentation

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1820 of file stm32f4xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

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STM32F410Rx HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32f4xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 66 of file stm32f4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU

Definition at line 78 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 75 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 69 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 72 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim_ex.h
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STM32F410Rx HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32f4xx_hal_tim_ex.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Definition at line 85 of file stm32f4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection. This parameter can be a value of TIM Master Mode Selection

Definition at line 86 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection. This parameter can be a value of TIM Master Slave Mode

Definition at line 89 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break and Dead time configuration Structure definition. More...

#include <stm32f4xx_hal_tim_ex.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | AutomaticOutput

Detailed Description

TIM Break and Dead time configuration Structure definition.

Definition at line 96 of file stm32f4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state. This parameter can be a value of TIM AOE Bit State

Definition at line 110 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity. This parameter can be a value of TIM Break Polarity

Definition at line 108 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State. This parameter can be a value of TIM Break Input State

Definition at line 106 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 104 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level. This parameter can be a value of TIM Lock level

Definition at line 102 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode. This parameter can be a value of TIM OSSI OffState Selection for Idle mode state

Definition at line 100 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode. This parameter can be a value of TIM OSSR OffState Selection for Run mode state

Definition at line 98 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_tim_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Remap

Defines
TIM Remap
TIM Exported Constants

Defines

#define | TIM_TIM2_TIM8_TRGO (0x00000000U)
#define | TIM_TIM2_ETH_PTP (0x00000400U)
#define | TIM_TIM2_USBFS_SOF (0x00000800U)
#define | TIM_TIM2_USBHS_SOF (0x00000C00U)
#define | TIM_TIM5_GPIO (0x00000000U)
#define | TIM_TIM5_LSI (0x00000040U)
#define | TIM_TIM5_LSE (0x00000080U)
#define | TIM_TIM5_RTC (0x000000C0U)
#define | TIM_TIM11_GPIO (0x00000000U)
#define | TIM_TIM11_HSE (0x00000002U)

Define Documentation

#define TIM_TIM11_GPIO (0x00000000U)

Definition at line 133 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM11_HSE (0x00000002U)

Definition at line 134 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM2_ETH_PTP (0x00000400U)

Definition at line 126 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM2_TIM8_TRGO (0x00000000U)

Definition at line 125 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM2_USBFS_SOF (0x00000800U)

Definition at line 127 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM2_USBHS_SOF (0x00000C00U)

Definition at line 128 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM5_GPIO (0x00000000U)

Definition at line 129 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM5_LSE (0x00000080U)

Definition at line 131 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM5_LSI (0x00000040U)

Definition at line 130 of file stm32f4xx_hal_tim_ex.h.

#define TIM_TIM5_RTC (0x000000C0U)

Definition at line 132 of file stm32f4xx_hal_tim_ex.h.

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STM32F410Rx HAL User Manual: TIM System Break Input

Defines
TIM System Break Input
TIM Exported Constants

Defines

#define | TIM_SYSTEMBREAKINPUT_HARDFAULT ((uint32_t)0x00000001U) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
#define | TIM_SYSTEMBREAKINPUT_PVD ((uint32_t)0x00000004U) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
#define | TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005U) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */

Define Documentation

#define TIM_SYSTEMBREAKINPUT_HARDFAULT ((uint32_t)0x00000001U) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */

Definition at line 147 of file stm32f4xx_hal_tim_ex.h.

#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005U) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */

Definition at line 149 of file stm32f4xx_hal_tim_ex.h.

#define TIM_SYSTEMBREAKINPUT_PVD ((uint32_t)0x00000004U) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */

Definition at line 148 of file stm32f4xx_hal_tim_ex.h.

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STM32F410Rx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIMEx

Defines

#define | IS_TIM_REMAP(TIM_REMAP)
#define | IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT)
#define | IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)

Define Documentation

#define IS_TIM_DEADTIME ( DEADTIME ) ((DEADTIME) <= 0xFFU)

Definition at line 316 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_REMAP ( TIM_REMAP )
Value:
(((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
                                  ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
                                  ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
                                  ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
                                  ((TIM_REMAP) == TIM_TIM5_GPIO)||\
                                  ((TIM_REMAP) == TIM_TIM5_LSI)||\
                                  ((TIM_REMAP) == TIM_TIM5_LSE)||\
                                  ((TIM_REMAP) == TIM_TIM5_RTC)||\
                                  ((TIM_REMAP) == TIM_TIM11_GPIO)||\
                                  ((TIM_REMAP) == TIM_TIM11_HSE))

Definition at line 297 of file stm32f4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define IS_TIM_SYSTEMBREAKINPUT ( BREAKINPUT )
Value:
(((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\
                                               ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\
                                               ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD))

Definition at line 310 of file stm32f4xx_hal_tim_ex.h.

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STM32F410Rx HAL User Manual: TIM Private Functions

TIM Private Functions
TIMEx
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIMEx

Modules | Functions
TIMEx
STM32F4xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Exported Types
TIM Exported Constants
TIM Private Macros
TIM Private Functions

Functions

static void TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.

Detailed Description

TIM HAL module driver.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
ChannelNState,: specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 1844 of file stm32f4xx_hal_tim_ex.c.

References assert_param, and IS_TIM_COMPLEMENTARY_CHANNELS.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
             Depending on the frame length defined by the M bit (8-bits or 9-bits),
             please refer to Reference manual for possible UART frame formats.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
    configuration procedures (details for the procedures are available in reference manual (RM0329)).

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 301 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_OVERSAMPLING, IS_UART_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_SetConfig(), and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
BreakDetectLength,: Specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
Return values:
HAL status

Definition at line 361 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, IS_UART_LIN_OVERSAMPLING, IS_UART_LIN_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_SetConfig(), and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Address,: USART address
WakeUpMethod,: specifies the USART wake-up method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
Return values:
HAL status

Definition at line 427 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_ADDRESS, IS_UART_OVERSAMPLING, IS_UART_WAKEUPMETHOD, IS_UART_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_SetConfig(), and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitializes the UART peripheral.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 490 of file stm32f4xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 239 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_OVERSAMPLING, IS_UART_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_HWCONTROL_NONE, UART_SetConfig(), and UART_InitTypeDef::WordLength.

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

UART MSP DeInit.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 537 of file stm32f4xx_hal_uart.c.

Referenced by HAL_UART_DeInit().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

UART MSP Init.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 522 of file stm32f4xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.

Detailed Description

UART Transmit and Receive functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) Non blocking mode: The communication is performed using Interrupts
            or DMA, these APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or receive process.
            The HAL_UART_ErrorCallback() user callback will be executed when
            a communication error is detected.

    (#) Blocking mode APIs are:
        (++) HAL_UART_Transmit()
        (++) HAL_UART_Receive()

    (#) Non Blocking mode APIs with Interrupt are:
        (++) HAL_UART_Transmit_IT()
        (++) HAL_UART_Receive_IT()
        (++) HAL_UART_IRQHandler()

    (#) Non Blocking mode functions with DMA are:
        (++) HAL_UART_Transmit_DMA()
        (++) HAL_UART_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
        (++) HAL_UART_TxCpltCallback()
        (++) HAL_UART_RxCpltCallback()
        (++) HAL_UART_ErrorCallback()

    [..]
      (@) In the Half duplex communication, it is forbidden to run the transmit
          and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
          can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pauses the DMA Transfer.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 980 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resumes the DMA Transfer.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1008 of file stm32f4xx_hal_uart.c.

References __HAL_UART_CLEAR_OREFLAG, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stops the DMA Transfer.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1038 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1217 of file stm32f4xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), and UART_DMAError().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

This function handles UART interrupt request.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1073 of file stm32f4xx_hal_uart.c.

References __HAL_UART_CLEAR_FEFLAG, __HAL_UART_CLEAR_NEFLAG, __HAL_UART_CLEAR_OREFLAG, __HAL_UART_CLEAR_PEFLAG, __HAL_UART_GET_FLAG, __HAL_UART_GET_IT_SOURCE, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::RxState, UART_EndTransmit_IT(), UART_FLAG_FE, UART_FLAG_NE, UART_FLAG_ORE, UART_FLAG_PE, UART_FLAG_RXNE, UART_FLAG_TC, UART_FLAG_TXE, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, UART_IT_TC, UART_IT_TXE, UART_Receive_IT(), and UART_Transmit_IT().

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives an amount of data in blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 689 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Note:
When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 925 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 815 of file stm32f4xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_IT_ERR, UART_IT_PE, and UART_IT_RXNE.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1187 of file stm32f4xx_hal_uart.c.

Referenced by UART_DMAReceiveCplt(), and UART_Receive_IT().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1202 of file stm32f4xx_hal_uart.c.

Referenced by UART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Sends an amount of data in blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 611 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 863 of file stm32f4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), UART_FLAG_TC, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 773 of file stm32f4xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, and UART_IT_TXE.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1157 of file stm32f4xx_hal_uart.c.

Referenced by UART_DMATransmitCplt(), and UART_EndTransmit_IT().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1172 of file stm32f4xx_hal_uart.c.

Referenced by UART_DMATxHalfCplt().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enters the UART in mute mode.
HAL_StatusTypeDef | HAL_MultiProcessor_ExitMuteMode (UART_HandleTypeDef *huart)
Exits the UART mute mode: wake up software.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.

Detailed Description

UART control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the UART:
    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enables the UART receiver and disables the UART transmitter.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1369 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enables the UART transmitter and disables the UART receiver.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1334 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmits break characters.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1253 of file stm32f4xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enters the UART in mute mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1280 of file stm32f4xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode ( UART_HandleTypeDef * huart )

Exits the UART mute mode: wake up software.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1307 of file stm32f4xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
UART Exported Functions

UART State and Errors functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Returns the UART state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.

Detailed Description

UART State and Errors functions.

  ==============================================================================
                 ##### Peripheral State and Errors functions #####
  ==============================================================================
 [..]
   This subsection provides a set of functions allowing to return the State of
   UART communication process, return Peripheral Errors occurred during communication
   process
   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART error code.

Parameters:
huart : pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 1441 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

Returns the UART state.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL state

Definition at line 1426 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::gState, and UART_HandleTypeDef::RxState.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Exported Functions

Modules | Functions
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit and Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Errors functions

UART State and Errors functions.

Functions

static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles UART Communication Timeout.
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Sends an amount of data in non blocking mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receives an amount of data in non blocking mode.
static void | UART_SetConfig (UART_HandleTypeDef *huart)
Configures the UART peripheral.

Function Documentation

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1532 of file stm32f4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1496 of file stm32f4xx_hal_uart.c.

References HAL_UART_RxCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1520 of file stm32f4xx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback().

Referenced by HAL_UART_Receive_DMA().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1455 of file stm32f4xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, and UART_IT_TC.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1484 of file stm32f4xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback().

Referenced by HAL_UART_Transmit_DMA().

static HAL_StatusTypeDef UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wraps up transmission in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1669 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), and UART_IT_TC.

Referenced by HAL_UART_IRQHandler().

static HAL_StatusTypeDef UART_Receive_IT ( UART_HandleTypeDef * huart ) [static]

Receives an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1688 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

static void UART_SetConfig ( UART_HandleTypeDef * huart ) [static]

Configures the UART peripheral.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1752 of file stm32f4xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_BAUDRATE, IS_UART_MODE, IS_UART_PARITY, IS_UART_STOPBITS, UART_InitTypeDef::Mode, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, UART_InitTypeDef::StopBits, UART_BRR_SAMPLING16, UART_BRR_SAMPLING8, UART_OVERSAMPLING_8, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

static HAL_StatusTypeDef UART_Transmit_IT ( UART_HandleTypeDef * huart ) [static]

Sends an amount of data in non blocking mode.

Parameters:
huart,: Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1621 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, __HAL_UART_ENABLE_IT, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_IT_TC, UART_IT_TXE, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles UART Communication Timeout.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Flag,: specifies the UART flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1552 of file stm32f4xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, __HAL_UART_GET_FLAG, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_READY, UART_HandleTypeDef::RxState, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, and UART_IT_TXE.

Referenced by HAL_UART_Receive(), and HAL_UART_Transmit().

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STM32F410Rx HAL User Manual: UART Exported Types

Data Structures | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...

Enumeration Type Documentation

enum HAL_UART_StateTypeDef

HAL UART State structures definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState.
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_UART_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_UART_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_UART_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_UART_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_UART_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_UART_STATE_ERROR

Error Value is allowed for gState only

Definition at line 136 of file stm32f4xx_hal_uart.h.

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STM32F410Rx HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32f4xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling

Detailed Description

UART Init Structure definition.

Definition at line 65 of file stm32f4xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register.

Definition at line 67 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control

Definition at line 89 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode

Definition at line 86 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). This parameter can be a value of UART Over Sampling

Definition at line 93 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 79 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits

Definition at line 76 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UART Word Length

Definition at line 73 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_uart.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32f4xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 160 of file stm32f4xx_hal_uart.h.

Field Documentation

__IO uint32_t UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 191 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), HAL_UART_GetError(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_DMAError().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 184 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_MultiProcessor_ExitMuteMode(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_EndTransmit_IT(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 180 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_DMAStop(), and HAL_UART_Receive_DMA().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 178 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_DMAStop(), and HAL_UART_Transmit_DMA().

UART_InitTypeDef UART_HandleTypeDef::Init

UART communication parameters

Definition at line 164 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

USART_TypeDef* UART_HandleTypeDef::Instance

UART registers base address

Definition at line 162 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_MultiProcessor_ExitMuteMode(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

HAL_LockTypeDef UART_HandleTypeDef::Lock

Locking object

Definition at line 182 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

uint8_t* UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 172 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 166 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_Transmit_IT().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 188 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_DMAError(), UART_DMAReceiveCplt(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

uint16_t UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 176 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAError(), UART_DMAReceiveCplt(), and UART_Receive_IT().

uint16_t UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 174 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

uint16_t UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 170 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_DMATransmitCplt(), and UART_Transmit_IT().

uint16_t UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 168 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_uart.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Error Code

Defines
UART Error Code
UART Exported constants

UART Error Code. More...

Defines

#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)

Detailed Description

UART Error Code.

Define Documentation

#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 212 of file stm32f4xx_hal_uart.h.

Referenced by UART_DMAError().

#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U)

Frame error

Definition at line 210 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 209 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 207 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 211 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 208 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Word Length

Defines
UART Word Length
UART Exported constants

Defines

#define | UART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define UART_WORDLENGTH_8B ((uint32_t)0x00000000U)

Definition at line 220 of file stm32f4xx_hal_uart.h.

#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 221 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported constants

Defines

#define | UART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Define Documentation

#define UART_STOPBITS_1 ((uint32_t)0x00000000U)

Definition at line 229 of file stm32f4xx_hal_uart.h.

#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Definition at line 230 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Parity

Defines
UART Parity
UART Exported constants

Defines

#define | UART_PARITY_NONE ((uint32_t)0x00000000U)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 239 of file stm32f4xx_hal_uart.h.

#define UART_PARITY_NONE ((uint32_t)0x00000000U)

Definition at line 238 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 240 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported constants

Defines

#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Define Documentation

#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)

Definition at line 250 of file stm32f4xx_hal_uart.h.

#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U)

Definition at line 248 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)

Definition at line 249 of file stm32f4xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Definition at line 251 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported constants

Defines

#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define UART_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 259 of file stm32f4xx_hal_uart.h.

#define UART_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 260 of file stm32f4xx_hal_uart.h.

#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 261 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART State

Defines
UART State
UART Exported constants

Defines

#define | UART_STATE_DISABLE ((uint32_t)0x00000000U)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define UART_STATE_DISABLE ((uint32_t)0x00000000U)

Definition at line 269 of file stm32f4xx_hal_uart.h.

#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Definition at line 270 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported constants

Defines

#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)

Definition at line 278 of file stm32f4xx_hal_uart.h.

#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Definition at line 279 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART LIN Break Detection Length

Defines
UART LIN Break Detection Length
UART Exported constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020U)

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)

Definition at line 287 of file stm32f4xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020U)

Definition at line 288 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Wakeup Functions

Defines
UART Wakeup Functions
UART Exported constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800U)

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800U)

Definition at line 297 of file stm32f4xx_hal_uart.h.

#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)

Definition at line 296 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART FLags

Defines
UART FLags
UART Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
#define | UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define | UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | UART_FLAG_TC ((uint32_t)USART_SR_TC)
#define | UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | UART_FLAG_NE ((uint32_t)USART_SR_NE)
#define | UART_FLAG_FE ((uint32_t)USART_SR_FE)
#define | UART_FLAG_PE ((uint32_t)USART_SR_PE)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)

Definition at line 307 of file stm32f4xx_hal_uart.h.

#define UART_FLAG_FE ((uint32_t)USART_SR_FE)

Definition at line 315 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)

Definition at line 312 of file stm32f4xx_hal_uart.h.

#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)

Definition at line 308 of file stm32f4xx_hal_uart.h.

#define UART_FLAG_NE ((uint32_t)USART_SR_NE)

Definition at line 314 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)

Definition at line 313 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_FLAG_PE ((uint32_t)USART_SR_PE)

Definition at line 316 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)

Definition at line 311 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and HAL_UART_Receive().

#define UART_FLAG_TC ((uint32_t)USART_SR_TC)

Definition at line 310 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Transmit(), and HAL_UART_Transmit_DMA().

#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)

Definition at line 309 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and HAL_UART_Transmit().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Interrupt Definitions

Defines
UART Interrupt Definitions
UART Exported constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask (16 bits) in the Y register
  • Y : Interrupt source register (2bits)
    • 0001: CR1 register
    • 0010: CR2 register
    • 0011: CR3 register

Define Documentation

#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))

Definition at line 340 of file stm32f4xx_hal_uart.h.

#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 341 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 336 of file stm32f4xx_hal_uart.h.

#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))

Definition at line 338 of file stm32f4xx_hal_uart.h.

#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 332 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 335 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 334 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_Transmit_IT().

#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 333 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_Transmit_IT(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle gstate & RxState.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushes the UART DR register.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified UART flag is set or not.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART IDLE pending flag.
#define | UART_IT_MASK ((uint32_t)0x0000FFFFU)
Enable the specified UART interrupt.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
macros to enables the UART's one bit sample method
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
macros to disables the UART's one bit sample method
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clear the UART FE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 436 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified UART pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • UART_FLAG_LBD: LIN Break detection flag.
  • UART_FLAG_TC: Transmission Complete flag.
  • UART_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register.
TXE flag is cleared only by a write to the USART_DR register.
Return values:
None

Definition at line 414 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 460 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clear the UART NE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 444 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 452 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), and HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;                \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    tmpreg = (__HANDLE__)->Instance->DR;        \
    UNUSED(tmpreg);                             \
  } while(0)

Clear the UART PE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 422 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 618 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))

Disable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__INTERRUPT__,: specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 498 of file stm32f4xx_hal_uart.h.

Referenced by UART_EndTransmit_IT(), UART_Receive_IT(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 612 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))

Definition at line 479 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), UART_DMATransmitCplt(), and UART_Transmit_IT().

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ ) ((__HANDLE__)->Instance->DR)

Flushes the UART DR register.

Parameters:
__HANDLE__,: specifies the UART Handle.

Definition at line 369 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified UART flag is set or not.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
  • UART_FLAG_LBD: LIN Break detection flag
  • UART_FLAG_TXE: Transmit data register empty flag
  • UART_FLAG_TC: Transmission Complete flag
  • UART_FLAG_RXNE: Receive data register not empty flag
  • UART_FLAG_IDLE: Idle Line detection flag
  • UART_FLAG_ORE: Overrun Error flag
  • UART_FLAG_NE: Noise Error flag
  • UART_FLAG_FE: Framing Error flag
  • UART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 390 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
(((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))

Checks whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__IT__,: specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ERR: Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 517 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0)

Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 552 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0)

Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 533 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0)

Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 590 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0)

Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be USART1, USART2 or LPUART.
Return values:
None

Definition at line 571 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))

macros to disables the UART's one bit sample method

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 606 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

macros to enables the UART's one bit sample method

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 600 of file stm32f4xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                     } while(0)

Reset UART handle gstate & RxState.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Return values:
None

Definition at line 361 of file stm32f4xx_hal_uart.h.

#define UART_IT_MASK ((uint32_t)0x0000FFFFU)

Enable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
__INTERRUPT__,: specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 478 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | UART_CR1_REG_INDEX 1U
UART interruptions flag mask.
#define | UART_CR2_REG_INDEX 2U
#define | UART_CR3_REG_INDEX 3U

Define Documentation

#define UART_CR1_REG_INDEX 1U

UART interruptions flag mask.

Definition at line 701 of file stm32f4xx_hal_uart.h.

#define UART_CR2_REG_INDEX 2U

Definition at line 702 of file stm32f4xx_hal_uart.h.

#define UART_CR3_REG_INDEX 3U

Definition at line 703 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | IS_UART_WORD_LENGTH(LENGTH)
#define | IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define | IS_UART_STOPBITS(STOPBITS)
#define | IS_UART_PARITY(PARITY)
#define | IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00U))
#define | IS_UART_STATE(STATE)
#define | IS_UART_OVERSAMPLING(SAMPLING)
#define | IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_UART_WAKEUPMETHOD(WAKEUP)
#define | IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
#define | IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
#define | UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | UART_BRR_SAMPLING16(_PCLK_, _BAUD_)
#define | UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
#define | UART_BRR_SAMPLING8(_PCLK_, _BAUD_)

Define Documentation

#define IS_UART_ADDRESS ( ADDRESS ) ((ADDRESS) <= 0x0FU)

Definition at line 736 of file stm32f4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define IS_UART_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 10500001U)

Definition at line 735 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_HARDWARE_FLOW_CONTROL ( CONTROL )
Value:
(((CONTROL) == UART_HWCONTROL_NONE) || \
                               ((CONTROL) == UART_HWCONTROL_RTS) || \
                               ((CONTROL) == UART_HWCONTROL_CTS) || \
                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))

Definition at line 720 of file stm32f4xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( LENGTH )
Value:
(((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))

Definition at line 731 of file stm32f4xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_LIN_OVERSAMPLING ( SAMPLING ) (((SAMPLING) == UART_OVERSAMPLING_16))

Definition at line 730 of file stm32f4xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_LIN_WORD_LENGTH ( LENGTH ) (((LENGTH) == UART_WORDLENGTH_8B))

Definition at line 714 of file stm32f4xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( MODE ) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00U))

Definition at line 725 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERSAMPLING ( SAMPLING )
Value:
(((SAMPLING) == UART_OVERSAMPLING_16) || \
                                        ((SAMPLING) == UART_OVERSAMPLING_8))

Definition at line 728 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define IS_UART_PARITY ( PARITY )
Value:
(((PARITY) == UART_PARITY_NONE) || \
                                ((PARITY) == UART_PARITY_EVEN) || \
                                ((PARITY) == UART_PARITY_ODD))

Definition at line 717 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_STATE ( STATE )
Value:
(((STATE) == UART_STATE_DISABLE) || \
                              ((STATE) == UART_STATE_ENABLE))

Definition at line 726 of file stm32f4xx_hal_uart.h.

#define IS_UART_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == UART_STOPBITS_1) || \
                                    ((STOPBITS) == UART_STOPBITS_2))

Definition at line 715 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUPMETHOD ( WAKEUP )
Value:
(((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))

Definition at line 733 of file stm32f4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define IS_UART_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == UART_WORDLENGTH_8B) || \
                                     ((LENGTH) == UART_WORDLENGTH_9B))

Definition at line 712 of file stm32f4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define UART_BRR_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 743 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_BRR_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))

Definition at line 752 of file stm32f4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(4U*(_BAUD_)))

Definition at line 738 of file stm32f4xx_hal_uart.h.

#define UART_DIV_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(2U*(_BAUD_)))

Definition at line 747 of file stm32f4xx_hal_uart.h.

#define UART_DIVFRAQ_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 740 of file stm32f4xx_hal_uart.h.

#define UART_DIVFRAQ_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)

Definition at line 749 of file stm32f4xx_hal_uart.h.

#define UART_DIVMANT_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)

Definition at line 739 of file stm32f4xx_hal_uart.h.

#define UART_DIVMANT_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)

Definition at line 748 of file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Private Functions

UART Private Functions
UART
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Initialization and de-initialization functions

Functions
USART Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USART
  in asynchronous and in synchronous modes.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Stop Bit
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
           Depending on the frame length defined by the M bit (8-bits or 9-bits),
           please refer to Reference manual for possible USART frame formats.
      (++) USART polarity
      (++) USART phase
      (++) USART LastBit
      (++) Receiver/transmitter modes

  [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual (RM0329)).

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitializes the USART peripheral.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 268 of file stm32f4xx_hal_usart.c.

References __HAL_USART_DISABLE, assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 222 of file stm32f4xx_hal_usart.c.

References __HAL_USART_ENABLE, assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Lock, USART_HandleTypeDef::State, and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

USART MSP DeInit.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 317 of file stm32f4xx_hal_usart.c.

Referenced by HAL_USART_DeInit().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

USART MSP Init.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 302 of file stm32f4xx_hal_usart.c.

Referenced by HAL_USART_Init().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Simplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Full-Duplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.

Detailed Description

USART Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

  [..]
    The USART supports master mode only: it cannot receive or send data related to an input
    clock (SCLK is always an output).

    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, These API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
              user callbacks
             will be executed respectively at the end of the transmit or Receive process
             The HAL_USART_ErrorCallback() user callback will be executed when a communication
             error is detected

    (#) Blocking mode APIs are :
        (++) HAL_USART_Transmit() in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_USART_Transmit_IT()in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_USART_Transmit_DMA()in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceie_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pauses the DMA Transfer.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1052 of file stm32f4xx_hal_usart.c.

References USART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resumes the DMA Transfer.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1072 of file stm32f4xx_hal_usart.c.

References USART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stops the DMA Transfer.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1092 of file stm32f4xx_hal_usart.c.

References HAL_DMA_Abort(), HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1294 of file stm32f4xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), and USART_DMAError().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

This function handles USART interrupt request.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1126 of file stm32f4xx_hal_usart.c.

References __HAL_USART_CLEAR_FEFLAG, __HAL_USART_CLEAR_NEFLAG, __HAL_USART_CLEAR_OREFLAG, __HAL_USART_CLEAR_PEFLAG, __HAL_USART_GET_FLAG, __HAL_USART_GET_IT_SOURCE, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::State, USART_EndTransmit_IT(), USART_FLAG_FE, USART_FLAG_NE, USART_FLAG_ORE, USART_FLAG_PE, USART_FLAG_RXNE, USART_FLAG_TC, USART_FLAG_TXE, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, USART_IT_TC, USART_IT_TXE, USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Receive an amount of data in blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pRxData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 477 of file stm32f4xx_hal_usart.c.

References DUMMY_DATA, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_FLAG_RXNE, USART_FLAG_TXE, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pRxData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status
Note:
The USART DMA transmit stream must be configured in order to generate the clock for the slave.
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.

Definition at line 901 of file stm32f4xx_hal_usart.c.

References __HAL_USART_CLEAR_OREFLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Simplex Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pRxData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 738 of file stm32f4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, DUMMY_DATA, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, and USART_IT_RXNE.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1249 of file stm32f4xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_Receive_IT().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1264 of file stm32f4xx_hal_usart.c.

Referenced by USART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex Send an amount of data in blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 400 of file stm32f4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_TC, USART_FLAG_TXE, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Simplex Send an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 840 of file stm32f4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_FLAG_TC, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Simplex Send an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status
Note:
The USART errors are not managed to avoid the overrun error.

Definition at line 689 of file stm32f4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_IT_TXE.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data transmitted buffer
pRxData,: Pointer to data received buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 579 of file stm32f4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TXE, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data transmitted buffer
pRxData,: Pointer to data received buffer
Size,: Amount of data to be received
Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 974 of file stm32f4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_CLEAR_OREFLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_FLAG_TC, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data transmitted buffer
pRxData,: Pointer to data received buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 788 of file stm32f4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, and USART_IT_TXE.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1219 of file stm32f4xx_hal_usart.c.

Referenced by USART_DMATransmitCplt(), and USART_EndTransmit_IT().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1234 of file stm32f4xx_hal_usart.c.

Referenced by USART_DMATxHalfCplt().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1279 of file stm32f4xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_TransmitReceive_IT().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
USART Exported Functions

USART State and Errors functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Returns the USART state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of
    USART communication
    process, return Peripheral Errors occurred during communication process
     (+) HAL_USART_GetState() API can be helpful to check in run-time the state
         of the USART peripheral.
     (+) HAL_USART_GetError() check in run-time errors that could be occurred during
         communication.

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart : pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART Error Code

Definition at line 1343 of file stm32f4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

Returns the USART state.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL state

Definition at line 1332 of file stm32f4xx_hal_usart.c.

References USART_HandleTypeDef::State.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Exported Functions

Modules | Functions
USART Exported Functions
USART

Modules

USART Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Errors functions

USART State and Errors functions.

Functions

static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles USART Communication Timeout.
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
static void | USART_SetConfig (USART_HandleTypeDef *husart)
Configures the USART peripheral.

Function Documentation

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1464 of file stm32f4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, and USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1403 of file stm32f4xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1452 of file stm32f4xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback().

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1358 of file stm32f4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1391 of file stm32f4xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback().

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static HAL_StatusTypeDef USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1600 of file stm32f4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::State, USART_IT_ERR, and USART_IT_TC.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_Receive_IT ( USART_HandleTypeDef * husart ) [static]

Simplex Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1621 of file stm32f4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, DUMMY_DATA, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static void USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configures the USART peripheral.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1795 of file stm32f4xx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, USART_InitTypeDef::Mode, USART_InitTypeDef::Parity, USART_InitTypeDef::StopBits, USART_BRR, USART_CLOCK_ENABLE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static HAL_StatusTypeDef USART_Transmit_IT ( USART_HandleTypeDef * husart ) [static]

Simplex Send an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status
Note:
The USART errors are not managed to avoid the overrun error.

Definition at line 1554 of file stm32f4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_IT_TC, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_TransmitReceive_IT ( USART_HandleTypeDef * husart ) [static]

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1693 of file stm32f4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_FLAG_RXNE, USART_FLAG_TXE, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles USART Communication Timeout.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Flag,: specifies the USART flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1485 of file stm32f4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, and USART_IT_TXE.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Exported Types

Data Structures | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_USART_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not yet Initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 102 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32f4xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit

Detailed Description

USART Init Structure definition.

Definition at line 65 of file stm32f4xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5

Definition at line 67 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit

Definition at line 94 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase

Definition at line 91 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity

Definition at line 88 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode

Definition at line 85 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 78 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits

Definition at line 75 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USART Word Length

Definition at line 72 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_usart.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32f4xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

USART handle Structure definition.

Definition at line 117 of file stm32f4xx_hal_usart.h.

Field Documentation

__IO uint32_t USART_HandleTypeDef::ErrorCode

Definition at line 143 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_GetError(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), and USART_DMAError().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmarx

Definition at line 137 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmatx

Definition at line 135 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

USART_InitTypeDef USART_HandleTypeDef::Init

Definition at line 121 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

USART_TypeDef* USART_HandleTypeDef::Instance

Definition at line 119 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

HAL_LockTypeDef USART_HandleTypeDef::Lock

Definition at line 139 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint8_t* USART_HandleTypeDef::pRxBuffPtr

Definition at line 129 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pTxBuffPtr

Definition at line 123 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

__IO uint16_t USART_HandleTypeDef::RxXferCount

Definition at line 133 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAError(), USART_DMAReceiveCplt(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferSize

Definition at line 131 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

__IO HAL_USART_StateTypeDef USART_HandleTypeDef::State

Definition at line 141 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

__IO uint16_t USART_HandleTypeDef::TxXferCount

Definition at line 127 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAError(), USART_DMATransmitCplt(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::TxXferSize

Definition at line 125 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_usart.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Error Code

Defines
USART Error Code
USART Exported Constants

USART Error Code. More...

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)

Detailed Description

USART Error Code.

Define Documentation

#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 164 of file stm32f4xx_hal_usart.h.

Referenced by USART_DMAError().

#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U)

Frame error

Definition at line 162 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 161 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 159 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 163 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 160 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Word Length

Defines
USART Word Length
USART Exported Constants

Defines

#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U)

Definition at line 172 of file stm32f4xx_hal_usart.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 173 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

Definition at line 182 of file stm32f4xx_hal_usart.h.

#define USART_STOPBITS_1 ((uint32_t)0x00000000U)

Definition at line 181 of file stm32f4xx_hal_usart.h.

#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Definition at line 184 of file stm32f4xx_hal_usart.h.

#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Definition at line 183 of file stm32f4xx_hal_usart.h.

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STM32F410Rx HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE ((uint32_t)0x00000000U)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 193 of file stm32f4xx_hal_usart.h.

#define USART_PARITY_NONE ((uint32_t)0x00000000U)

Definition at line 192 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 194 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define USART_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 202 of file stm32f4xx_hal_usart.h.

#define USART_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 203 of file stm32f4xx_hal_usart.h.

#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 204 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE ((uint32_t)0x00000000U)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Define Documentation

#define USART_CLOCK_DISABLE ((uint32_t)0x00000000U)

Definition at line 212 of file stm32f4xx_hal_usart.h.

#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Definition at line 213 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW ((uint32_t)0x00000000U)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Definition at line 222 of file stm32f4xx_hal_usart.h.

#define USART_POLARITY_LOW ((uint32_t)0x00000000U)

Definition at line 221 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define USART_PHASE_1EDGE ((uint32_t)0x00000000U)

Definition at line 230 of file stm32f4xx_hal_usart.h.

#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Definition at line 231 of file stm32f4xx_hal_usart.h.

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STM32F410Rx HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)

Definition at line 239 of file stm32f4xx_hal_usart.h.

#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Definition at line 240 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART NACK State

Defines
USART NACK State
USART Exported Constants

Defines

#define | USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | USART_NACK_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define USART_NACK_DISABLE ((uint32_t)0x00000000U)

Definition at line 249 of file stm32f4xx_hal_usart.h.

#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

Definition at line 248 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_TXE ((uint32_t)0x00000080U)
#define | USART_FLAG_TC ((uint32_t)0x00000040U)
#define | USART_FLAG_RXNE ((uint32_t)0x00000020U)
#define | USART_FLAG_IDLE ((uint32_t)0x00000010U)
#define | USART_FLAG_ORE ((uint32_t)0x00000008U)
#define | USART_FLAG_NE ((uint32_t)0x00000004U)
#define | USART_FLAG_FE ((uint32_t)0x00000002U)
#define | USART_FLAG_PE ((uint32_t)0x00000001U)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define USART_FLAG_FE ((uint32_t)0x00000002U)

Definition at line 265 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_FLAG_IDLE ((uint32_t)0x00000010U)

Definition at line 262 of file stm32f4xx_hal_usart.h.

#define USART_FLAG_NE ((uint32_t)0x00000004U)

Definition at line 264 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_FLAG_ORE ((uint32_t)0x00000008U)

Definition at line 263 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_FLAG_PE ((uint32_t)0x00000001U)

Definition at line 266 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_FLAG_RXNE ((uint32_t)0x00000020U)

Definition at line 261 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

#define USART_FLAG_TC ((uint32_t)0x00000040U)

Definition at line 260 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define USART_FLAG_TXE ((uint32_t)0x00000080U)

Definition at line 259 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask in the XX register
  • Y : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register

Define Documentation

#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))

Definition at line 289 of file stm32f4xx_hal_usart.h.

#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 290 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 285 of file stm32f4xx_hal_usart.h.

#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))

Definition at line 287 of file stm32f4xx_hal_usart.h.

#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 281 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 284 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 283 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_Transmit_IT().

#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 282 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified Smartcard flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified Smartcard pending flags.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables or disables the specified USART interrupts.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Macro to enable the USART's one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
Macro to disable the USART's one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the USART FE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
Return values:
None

Definition at line 367 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified Smartcard pending flags.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register.
TXE flag is cleared only by a write to the USART_DR register.
Return values:
None

Definition at line 347 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
Return values:
None

Definition at line 388 of file stm32f4xx_hal_usart.h.

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the USART NE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
Return values:
None

Definition at line 374 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
Return values:
None

Definition at line 381 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;                \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    tmpreg = (__HANDLE__)->Instance->DR;        \
    UNUSED(tmpreg);                             \
  } while(0)

Clear the USART PE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
Return values:
None

Definition at line 354 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_DISABLE ( __HANDLE__ ) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
Return values:
None

Definition at line 451 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_DeInit().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
                                                            (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
                                                             ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))

Definition at line 407 of file stm32f4xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
Return values:
None

Definition at line 444 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
                                                            (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
                                                             ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))

Enables or disables the specified USART interrupts.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
__INTERRUPT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE: Parity Error interrupt
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 404 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_DMATransmitCplt(), and USART_Transmit_IT().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_TXE: Transmit data register empty flag
  • USART_FLAG_TC: Transmission Complete flag
  • USART_FLAG_RXNE: Receive data register not empty flag
  • USART_FLAG_IDLE: Idle Line detection flag
  • USART_FLAG_ORE: Overrun Error flag
  • USART_FLAG_NE: Noise Error flag
  • USART_FLAG_FE: Framing Error flag
  • USART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 326 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
(((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))

Checks whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ERR: Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 424 of file stm32f4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))

Macro to disable the USART's one bit sample method.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 437 of file stm32f4xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Macro to enable the USART's one bit sample method.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 431 of file stm32f4xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_USART_STATE_RESET)

Reset USART handle state.

Parameters:
__HANDLE__,: specifies the USART Handle. This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
Return values:
None

Definition at line 309 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | DUMMY_DATA 0xFFFFU
#define | USART_TIMEOUT_VALUE 22000U
#define | USART_IT_MASK
USART interruptions flag mask.
#define | USART_CR1_REG_INDEX 1U
#define | USART_CR2_REG_INDEX 2U
#define | USART_CR3_REG_INDEX 3U

Define Documentation

#define DUMMY_DATA 0xFFFFU

Definition at line 152 of file stm32f4xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), and USART_Receive_IT().

#define USART_CR1_REG_INDEX 1U

Definition at line 525 of file stm32f4xx_hal_usart.h.

#define USART_CR2_REG_INDEX 2U

Definition at line 526 of file stm32f4xx_hal_usart.h.

#define USART_CR3_REG_INDEX 3U

Definition at line 527 of file stm32f4xx_hal_usart.h.

#define USART_IT_MASK
Value:
((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
                                   USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )

USART interruptions flag mask.

Definition at line 522 of file stm32f4xx_hal_usart.h.

#define USART_TIMEOUT_VALUE 22000U

Definition at line 153 of file stm32f4xx_hal_usart.c.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_USART_NACK_STATE(NACK)
#define | IS_USART_LASTBIT(LASTBIT)
#define | IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
#define | IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
#define | IS_USART_CLOCK(CLOCK)
#define | IS_USART_WORD_LENGTH(LENGTH)
#define | IS_USART_STOPBITS(STOPBITS)
#define | IS_USART_PARITY(PARITY)
#define | IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00U) && ((MODE) != (uint32_t)0x00U))
#define | IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
#define | USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
#define | USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Define Documentation

#define IS_USART_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 10500001U)

Definition at line 554 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( CLOCK )
Value:
(((CLOCK) == USART_CLOCK_DISABLE) || \
                               ((CLOCK) == USART_CLOCK_ENABLE))

Definition at line 542 of file stm32f4xx_hal_usart.h.

#define IS_USART_LASTBIT ( LASTBIT )
Value:
(((LASTBIT) == USART_LASTBIT_DISABLE) || \
                                       ((LASTBIT) == USART_LASTBIT_ENABLE))

Definition at line 538 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( MODE ) ((((MODE) & (uint32_t)0xFFF3) == 0x00U) && ((MODE) != (uint32_t)0x00U))

Definition at line 553 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_NACK_STATE ( NACK )
Value:
(((NACK) == USART_NACK_ENABLE) || \
                                   ((NACK) == USART_NACK_DISABLE))

Definition at line 536 of file stm32f4xx_hal_usart.h.

#define IS_USART_PARITY ( PARITY )
Value:
(((PARITY) == USART_PARITY_NONE) || \
                                     ((PARITY) == USART_PARITY_EVEN) || \
                                     ((PARITY) == USART_PARITY_ODD))

Definition at line 550 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( CPHA ) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))

Definition at line 540 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( CPOL ) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))

Definition at line 541 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == USART_STOPBITS_1) || \
                                         ((STOPBITS) == USART_STOPBITS_0_5) || \
                                         ((STOPBITS) == USART_STOPBITS_1_5) || \
                                         ((STOPBITS) == USART_STOPBITS_2))

Definition at line 546 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == USART_WORDLENGTH_8B) || \
                                          ((LENGTH) == USART_WORDLENGTH_9B))

Definition at line 544 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_BRR | ( | _PCLK_,
 |  | _BAUD_
 | ) | ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 559 of file stm32f4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_DIV | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(2U*(_BAUD_)))

Definition at line 556 of file stm32f4xx_hal_usart.h.

#define USART_DIVFRAQ | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 558 of file stm32f4xx_hal_usart.h.

#define USART_DIVMANT | ( | _PCLK_,
 |  | _BAUD_
 | ) | (USART_DIV((_PCLK_), (_BAUD_))/100U)

Definition at line 557 of file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: USART Private Functions

USART Private Functions
USART
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_WWDG_DeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG peripheral.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG MSP.
__weak void | HAL_WWDG_MspDeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG MSP.
void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize the WWDG according to the specified parameters
        in the WWDG_InitTypeDef and create the associated handle
    (+) DeInitialize the WWDG peripheral
    (+) Initialize the WWDG MSP
    (+) DeInitialize the WWDG MSP

Function Documentation

HAL_StatusTypeDef HAL_WWDG_DeInit ( WWDG_HandleTypeDef * hwwdg )

DeInitializes the WWDG peripheral.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 193 of file stm32f4xx_hal_wwdg.c.

References assert_param, HAL_WWDG_MspDeInit(), HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_RESET, WWDG_HandleTypeDef::Instance, and WWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 150 of file stm32f4xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, HAL_WWDG_MspInit(), HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_READY, HAL_WWDG_STATE_RESET, WWDG_HandleTypeDef::Init, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, WWDG_HandleTypeDef::Lock, WWDG_InitTypeDef::Prescaler, WWDG_HandleTypeDef::State, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspDeInit ( WWDG_HandleTypeDef * hwwdg )

DeInitializes the WWDG MSP.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 250 of file stm32f4xx_hal_wwdg.c.

Referenced by HAL_WWDG_DeInit().

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initializes the WWDG MSP.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 235 of file stm32f4xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init().

void HAL_WWDG_WakeupCallback ( WWDG_HandleTypeDef * hwwdg )

Early Wakeup WWDG callback.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 404 of file stm32f4xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Start (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG.
HAL_StatusTypeDef | HAL_WWDG_Start_IT (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG with interrupt enabled.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
Refreshes the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handles WWDG interrupt request.
__weak void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.

Detailed Description

IO operation functions.

  ==============================================================================
                       ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the WWDG.
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request.

Function Documentation

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handles WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 375 of file stm32f4xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, HAL_WWDG_STATE_READY, HAL_WWDG_WakeupCallback(), WWDG_HandleTypeDef::State, WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | uint32_t | Counter
 | ) |  |

Refreshes the WWDG.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Counter,: value of counter to put in WWDG counter
Return values:
HAL status

Definition at line 338 of file stm32f4xx_hal_wwdg.c.

References assert_param, HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_READY, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, and WWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_WWDG_Start ( WWDG_HandleTypeDef * hwwdg )

Starts the WWDG.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 286 of file stm32f4xx_hal_wwdg.c.

References __HAL_WWDG_ENABLE, HAL_WWDG_STATE_BUSY, HAL_WWDG_STATE_READY, and WWDG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_WWDG_Start_IT ( WWDG_HandleTypeDef * hwwdg )

Starts the WWDG with interrupt enabled.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 313 of file stm32f4xx_hal_wwdg.c.

References __HAL_WWDG_ENABLE, __HAL_WWDG_ENABLE_IT, HAL_WWDG_STATE_BUSY, WWDG_HandleTypeDef::State, and WWDG_IT_EWI.

__weak void HAL_WWDG_WakeupCallback ( WWDG_HandleTypeDef * hwwdg )

Early Wakeup WWDG callback.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 404 of file stm32f4xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

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STM32F410Rx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
WWDG Exported Functions

Peripheral State functions. More...

Functions

HAL_WWDG_StateTypeDef HAL_WWDG_GetState (WWDG_HandleTypeDef *hwwdg)
Returns the WWDG state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_WWDG_StateTypeDef HAL_WWDG_GetState ( WWDG_HandleTypeDef * hwwdg )

Returns the WWDG state.

Parameters:
hwwdg,: pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL state

Definition at line 438 of file stm32f4xx_hal_wwdg.c.

References WWDG_HandleTypeDef::State.

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STM32F410Rx HAL User Manual: WWDG Exported Types

Data Structures | Enumerations
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Enumerations

enum HAL_WWDG_StateTypeDef {
HAL_WWDG_STATE_RESET = 0x00U, HAL_WWDG_STATE_READY = 0x01U, HAL_WWDG_STATE_BUSY = 0x02U, HAL_WWDG_STATE_TIMEOUT = 0x03U,
HAL_WWDG_STATE_ERROR = 0x04U
}
WWDG HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_WWDG_StateTypeDef

WWDG HAL State Structure definition.

Enumerator:
HAL_WWDG_STATE_RESET

WWDG not yet initialized or disabled

HAL_WWDG_STATE_READY

WWDG initialized and ready for use

HAL_WWDG_STATE_BUSY

WWDG internal process is ongoing

HAL_WWDG_STATE_TIMEOUT

WWDG timeout state

HAL_WWDG_STATE_ERROR

WWDG error state

Definition at line 65 of file stm32f4xx_hal_wwdg.h.

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STM32F410Rx HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32f4xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter

Detailed Description

WWDG Init structure definition.

Definition at line 77 of file stm32f4xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 85 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 79 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number lower than Max_Data = 0x80

Definition at line 82 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_wwdg.h
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STM32F410Rx HAL User Manual: WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32f4xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * | Instance
WWDG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_WWDG_StateTypeDef | State

Detailed Description

WWDG handle Structure definition.

Definition at line 93 of file stm32f4xx_hal_wwdg.h.

Field Documentation

WWDG_InitTypeDef WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 97 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

WWDG_TypeDef* WWDG_HandleTypeDef::Instance

Register base address

Definition at line 95 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_DeInit(), HAL_WWDG_Init(), and HAL_WWDG_Refresh().

HAL_LockTypeDef WWDG_HandleTypeDef::Lock

WWDG locking object

Definition at line 99 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

__IO HAL_WWDG_StateTypeDef WWDG_HandleTypeDef::State

WWDG communication state

Definition at line 101 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_DeInit(), HAL_WWDG_GetState(), HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), HAL_WWDG_Refresh(), HAL_WWDG_Start(), and HAL_WWDG_Start_IT().

The documentation for this struct was generated from the following file:
  • stm32f4xx_hal_wwdg.h
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STM32F410Rx HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 116 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler(), and HAL_WWDG_Start_IT().

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STM32F410Rx HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 125 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

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STM32F410Rx HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 ((uint32_t)0x00000000U)
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 ((uint32_t)0x00000000U)

WWDG counter clock = (PCLK1/4096)/1

Definition at line 133 of file stm32f4xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 134 of file stm32f4xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 135 of file stm32f4xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/8

Definition at line 136 of file stm32f4xx_hal_wwdg.h.

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STM32F410Rx HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
Reset WWDG handle state.
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enables the WWDG peripheral.
#define | __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
Disables the WWDG peripheral.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Gets the selected WWDG's it status.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
Disables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected WWDG's flag status.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clears the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified WWDG interrupt source is enabled or disabled.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__FLAG__))

Clears the WWDG's pending flags.

Parameters:
__HANDLE__,: WWDG handle
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 232 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 189 of file stm32f4xx_hal_wwdg.h.

#define __HAL_WWDG_DISABLE ( __HANDLE__ ) /* dummy macro */

Disables the WWDG peripheral.

Parameters:
__HANDLE__,: WWDG handle
Note:
WARNING: This is a dummy macro for HAL code alignment. Once enable, WWDG Peripheral cannot be disabled except by a system reset.
Return values:
None

Definition at line 170 of file stm32f4xx_hal_wwdg.h.

#define __HAL_WWDG_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | /* dummy macro */

Disables the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the interrupt to disable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
WARNING: This is a dummy macro for HAL code alignment. Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 212 of file stm32f4xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enables the WWDG peripheral.

Parameters:
__HANDLE__,: WWDG handle
Return values:
None

Definition at line 161 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Start(), and HAL_WWDG_Start_IT().

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enables the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 200 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Start_IT().

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Gets the selected WWDG's flag status.

Parameters:
__HANDLE__,: WWDG handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 222 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Gets the selected WWDG's it status.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 180 of file stm32f4xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified WWDG interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: WWDG Handle.
__INTERRUPT__,: specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 241 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)

Reset WWDG handle state.

Parameters:
__HANDLE__,: WWDG handle
Return values:
None

Definition at line 154 of file stm32f4xx_hal_wwdg.h.

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STM32F410Rx HAL User Manual: WWDG BitAddress

Defines
WWDG BitAddress
WWDG Private Constants

WWDG registers bit address in the alias region. More...

Defines

#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04U)

Detailed Description

WWDG registers bit address in the alias region.

Define Documentation

#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04U)

Definition at line 303 of file stm32f4xx_hal_wwdg.h.

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STM32F410Rx HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7FU)
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40U) && ((__COUNTER__) <= 0x7FU))

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= 0x40U) && ((__COUNTER__) <= 0x7FU))

Definition at line 322 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1) || \
                                          ((__PRESCALER__) == WWDG_PRESCALER_2) || \
                                          ((__PRESCALER__) == WWDG_PRESCALER_4) || \
                                          ((__PRESCALER__) == WWDG_PRESCALER_8))

Definition at line 317 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= 0x7FU)

Definition at line 321 of file stm32f4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

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STM32F410Rx HAL User Manual: WWDG Private Functions

WWDG Private Functions
WWDG
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STM32F410Rx HAL User Manual: DMA2D

DMA2D
STM32F4xx_HAL_Driver

DMA2D HAL module driver. More...

DMA2D HAL module driver.

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STM32F410Rx HAL User Manual: DSI

DSI
STM32F4xx_HAL_Driver
Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: NAND

NAND
STM32F4xx_HAL_Driver
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STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • AccessPermission : MPU_Region_InitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • Address : FLASH_ProcessTypeDef
  • AddressingMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • AddrEventCount : FMPI2C_HandleTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
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STM32F410Rx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • Bank : FLASH_ProcessTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BaudRate : USART_InitTypeDef , IRDA_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
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STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , TIM_HandleTypeDef , DMA_InitTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef
  • ClockPrescaler : ADC_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , I2S_InitTypeDef
  • ClockSpeed : I2C_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
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STM32F410Rx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataFormat : I2S_InitTypeDef
  • DataSize : SPI_InitTypeDef
  • Date : RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DMA_Handle : ADC_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DualAddressMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • DutyCycle : I2C_InitTypeDef
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STM32F410Rx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • Enable : MPU_Region_InitTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ErrorCode : ADC_HandleTypeDef , FMPI2C_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , I2C_HandleTypeDef , IRDA_HandleTypeDef , DAC_HandleTypeDef , I2S_HandleTypeDef , __DMA_HandleTypeDef , FLASH_ProcessTypeDef , SMARTCARD_HandleTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
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  • g
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FIFOMode : DMA_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef
  • Filter : RTC_TamperTypeDef
  • FirstBit : SPI_InitTypeDef
  • Fmpi2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • FullDuplexMode : I2S_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
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  • i
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  • r
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GeneralCallMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • gState : UART_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
  • c
  • d
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  • g
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • hdma : TIM_HandleTypeDef
  • hdmarx : FMPI2C_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , I2C_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • hdmatx : UART_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • r
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2SClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IFCR : DMA_Base_Registers
  • Init : TIM_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , ADC_HandleTypeDef , __DMA_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : IRDA_HandleTypeDef , __DMA_HandleTypeDef , CRC_HandleTypeDef , USART_HandleTypeDef , RTC_HandleTypeDef , TIM_HandleTypeDef , FMPI2C_HandleTypeDef , DAC_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , I2S_HandleTypeDef , ADC_HandleTypeDef , RNG_HandleTypeDef , I2C_HandleTypeDef , WWDG_HandleTypeDef
  • IrDAMode : IRDA_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • ISR : DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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  • g
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • Lock : ADC_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , I2S_HandleTypeDef , TIM_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , FLASH_ProcessTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , RTC_HandleTypeDef , RNG_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , DAC_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
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  • a
  • b
  • c
  • d
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MCLKOutput : I2S_InitTypeDef
  • MemBurst : DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef
  • Mode : SPI_InitTypeDef , I2S_InitTypeDef , I2C_HandleTypeDef , GPIO_InitTypeDef , FMPI2C_HandleTypeDef , DMA_InitTypeDef , ADC_MultiModeTypeDef , IRDA_InitTypeDef , USART_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef , PWR_PVDTypeDef
  • Month : RTC_DateTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
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  • a
  • b
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  • g
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKState : SMARTCARD_InitTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfCurrentConversionRank : ADC_HandleTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbSectors : FLASH_EraseInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • NoStretchMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • NSS : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OptionType : FLASH_AdvOBProgramInitTypeDef , FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OverSampling : UART_InitTypeDef
  • OwnAddress1 : I2C_InitTypeDef , FMPI2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , FMPI2C_InitTypeDef
  • OwnAddress2Masks : FMPI2C_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • Parent : __DMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • pBuffPtr : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • PCROPState : FLASH_AdvOBProgramInitTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphBurst : DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • Pin : GPIO_InitTypeDef
  • PinSelection : RTC_TamperTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : LPTIM_ULPClockConfigTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : WWDG_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef
  • PreviousState : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • Priority : DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • pRxBuffPtr : IRDA_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef
  • pTxBuffPtr : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef
  • Pull : GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef
  • Reserved0 : DMA_Base_Registers
  • Resolution : ADC_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • RxXferSize : UART_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , __SPI_HandleTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • a
  • b
  • c
  • d
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • Sectors : FLASH_AdvOBProgramInitTypeDef
  • Size : MPU_Region_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • Speed : GPIO_InitTypeDef
  • Standard : I2S_InitTypeDef
  • State : RTC_HandleTypeDef , ADC_HandleTypeDef , CRC_HandleTypeDef , DAC_HandleTypeDef , I2S_HandleTypeDef , __DMA_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef , TIM_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , RNG_HandleTypeDef , WWDG_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef
  • Status : LPTIM_HandleTypeDef
  • StopBits : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TimeFormat : RTC_TimeTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : FMPI2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • Trigger : LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxXferCount : UART_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef
  • TxXferSize : I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • b
  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • b
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : WWDG_InitTypeDef
  • WordLength : UART_InitTypeDef , USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferCount : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferOptions : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • XferSize : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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- a -

  • AccessPermission : MPU_Region_InitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • Address : FLASH_ProcessTypeDef
  • AddressingMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • AddrEventCount : FMPI2C_HandleTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AudioFreq : I2S_InitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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- b -

  • Bank : FLASH_ProcessTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • BaudRate : USART_InitTypeDef , IRDA_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BORLevel : FLASH_OBProgramInitTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , TIM_HandleTypeDef , DMA_InitTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef
  • ClockPrescaler : ADC_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , I2S_InitTypeDef
  • ClockSpeed : I2C_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPOL : I2S_InitTypeDef
  • CRCCalculation : SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- d -

  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataFormat : I2S_InitTypeDef
  • DataSize : SPI_InitTypeDef
  • Date : RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef
  • Direction : DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DMA_Handle : ADC_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DualAddressMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • DutyCycle : I2C_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- e -

  • Enable : MPU_Region_InitTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ErrorCode : ADC_HandleTypeDef , FMPI2C_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , I2C_HandleTypeDef , IRDA_HandleTypeDef , DAC_HandleTypeDef , I2S_HandleTypeDef , __DMA_HandleTypeDef , FLASH_ProcessTypeDef , SMARTCARD_HandleTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- f -

  • FIFOMode : DMA_InitTypeDef
  • FIFOThreshold : DMA_InitTypeDef
  • Filter : RTC_TamperTypeDef
  • FirstBit : SPI_InitTypeDef
  • Fmpi2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • FullDuplexMode : I2S_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- g -

  • GeneralCallMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • gState : UART_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- h -

  • hdma : TIM_HandleTypeDef
  • hdmarx : FMPI2C_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , I2C_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • hdmatx : UART_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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  • I2SClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IFCR : DMA_Base_Registers
  • Init : TIM_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , ADC_HandleTypeDef , __DMA_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : IRDA_HandleTypeDef , __DMA_HandleTypeDef , CRC_HandleTypeDef , USART_HandleTypeDef , RTC_HandleTypeDef , TIM_HandleTypeDef , FMPI2C_HandleTypeDef , DAC_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , I2S_HandleTypeDef , ADC_HandleTypeDef , RNG_HandleTypeDef , I2C_HandleTypeDef , WWDG_HandleTypeDef
  • IrDAMode : IRDA_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • ISR : DMA_Base_Registers
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- l -

  • Lock : ADC_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , I2S_HandleTypeDef , TIM_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , FLASH_ProcessTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , RTC_HandleTypeDef , RNG_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , DAC_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- m -

  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MCLKOutput : I2S_InitTypeDef
  • MemBurst : DMA_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef
  • Mode : SPI_InitTypeDef , I2S_InitTypeDef , I2C_HandleTypeDef , GPIO_InitTypeDef , FMPI2C_HandleTypeDef , DMA_InitTypeDef , ADC_MultiModeTypeDef , IRDA_InitTypeDef , USART_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef , PWR_PVDTypeDef
  • Month : RTC_DateTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • NACKState : SMARTCARD_InitTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfCurrentConversionRank : ADC_HandleTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbSectors : FLASH_EraseInitTypeDef
  • NbSectorsToErase : FLASH_ProcessTypeDef
  • NoStretchMode : FMPI2C_InitTypeDef , I2C_InitTypeDef
  • NSS : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OptionType : FLASH_AdvOBProgramInitTypeDef , FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OverSampling : UART_InitTypeDef
  • OwnAddress1 : I2C_InitTypeDef , FMPI2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , FMPI2C_InitTypeDef
  • OwnAddress2Masks : FMPI2C_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Parent : __DMA_HandleTypeDef
  • Parity : IRDA_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • pBuffPtr : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • PCROPState : FLASH_AdvOBProgramInitTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphBurst : DMA_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • Pin : GPIO_InitTypeDef
  • PinSelection : RTC_TamperTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : LPTIM_ULPClockConfigTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : WWDG_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef , LPTIM_ClockConfigTypeDef , SMARTCARD_InitTypeDef , TIM_Base_InitTypeDef
  • PreviousState : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • Priority : DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • pRxBuffPtr : IRDA_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef
  • pTxBuffPtr : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , __SPI_HandleTypeDef , I2S_HandleTypeDef , UART_HandleTypeDef
  • Pull : GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- r -

  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef
  • Reserved0 : DMA_Base_Registers
  • Resolution : ADC_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef , IRDA_HandleTypeDef
  • RxXferSize : UART_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , I2S_HandleTypeDef , __SPI_HandleTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
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  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef
  • Sector : FLASH_ProcessTypeDef , FLASH_EraseInitTypeDef
  • Sectors : FLASH_AdvOBProgramInitTypeDef
  • Size : MPU_Region_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • Speed : GPIO_InitTypeDef
  • Standard : I2S_InitTypeDef
  • State : RTC_HandleTypeDef , ADC_HandleTypeDef , CRC_HandleTypeDef , DAC_HandleTypeDef , I2S_HandleTypeDef , __DMA_HandleTypeDef , FMPI2C_HandleTypeDef , I2C_HandleTypeDef , TIM_HandleTypeDef , IWDG_HandleTypeDef , LPTIM_HandleTypeDef , RNG_HandleTypeDef , WWDG_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef
  • Status : LPTIM_HandleTypeDef
  • StopBits : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • StreamBaseAddress : __DMA_HandleTypeDef
  • StreamIndex : __DMA_HandleTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- t -

  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TimeFormat : RTC_TimeTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : FMPI2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TIMPresSelection : RCC_PeriphCLKInitTypeDef
  • Trigger : LPTIM_InitTypeDef , RTC_TamperTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxXferCount : UART_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , I2S_HandleTypeDef
  • TxXferSize : I2S_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- u -

  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- v -

  • VoltageForErase : FLASH_ProcessTypeDef
  • VoltageRange : FLASH_EraseInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- w -

  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : WWDG_InitTypeDef
  • WordLength : UART_InitTypeDef , USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • WRPSector : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- x -

  • XferCount : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferM1CpltCallback : __DMA_HandleTypeDef
  • XferOptions : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
  • XferSize : FMPI2C_HandleTypeDef , I2C_HandleTypeDef
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STM32F410Rx HAL User Manual: Data Fields - Variables

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- y -

  • Year : RTC_DateTypeDef
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STM32F410Rx HAL User Manual: stm32f4xx_hal_can.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
stm32f4xx_hal_can.c File Reference

This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Enable the CAN controller interface clock using
          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.

      (#) CAN pins configuration
        (++) Enable the clock for the CAN GPIOs using the following function:
             __GPIOx_CLK_ENABLE()
        (++) Connect and configure the involved CAN pins to AF9 using the
              following function HAL_GPIO_Init()

      (#) Initialize and configure the CAN using CAN_Init() function.

      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.

      (#) Receive a CAN frame using HAL_CAN_Receive() function.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the CAN peripheral transmission and wait the end of this operation
           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
           according to his end application
       (+) Start the CAN peripheral reception and wait the end of this operation
           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
           according to his end application

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_TxCpltCallback
       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_ErrorCallback

     *** CAN HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in CAN HAL driver.

      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status

     [..]
      (@) You can refer to the CAN HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_can.c.

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STM32F410Rx HAL User Manual: stm32f4xx_hal_can.h File Reference

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stm32f4xx_hal_can.h File Reference

Header file of CAN HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of CAN HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_can.h.

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STM32F410Rx HAL User Manual: stm32f4xx_hal_cec.c File Reference

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  • STM32F4xx_HAL_Driver
  • Src
stm32f4xx_hal_cec.c File Reference

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The CEC HAL driver can be used as follow:

    (#) Declare a CEC_HandleTypeDef handle structure.
    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
        (##) Enable the CEC interface clock.
        (##) CEC pins configuration:
            (+) Enable the clock for the CEC GPIOs.
            (+) Configure these CEC pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
             and HAL_CEC_Receive_IT() APIs):
            (+) Configure the CEC interrupt priority.
            (+) Enable the NVIC CEC IRQ handle.
            (@) The specific CEC interrupts (Transmission complete interrupt,
                RXNE interrupt and Error Interrupts) will be managed using the macros
                __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
                and receive process.

    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
        in case of Bit Rising Error, Error-Bit generation conditions, device logical
        address and Listen mode in the hcec Init structure.

    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.

    (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
        by calling the customed HAL_CEC_MspInit() API.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cec.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cec.h File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
  • Inc
stm32f4xx_hal_cec.h File Reference

Header file of CEC HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of CEC HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cec.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_conf.h File Reference

  • File List
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Defines
stm32f4xx_hal_conf.h File Reference
#include "stm32f4xx_hal_rcc.h"
#include "stm32f4xx_hal_gpio.h"
#include "stm32f4xx_hal_dma.h"
#include "stm32f4xx_hal_cortex.h"
#include "stm32f4xx_hal_adc.h"
#include "stm32f4xx_hal_can.h"
#include "stm32f4xx_hal_crc.h"
#include "stm32f4xx_hal_cryp.h"
#include "stm32f4xx_hal_dma2d.h"
#include "stm32f4xx_hal_dac.h"
#include "stm32f4xx_hal_dcmi.h"
#include "stm32f4xx_hal_eth.h"
#include "stm32f4xx_hal_flash.h"
#include "stm32f4xx_hal_sram.h"
#include "stm32f4xx_hal_nor.h"
#include "stm32f4xx_hal_nand.h"
#include "stm32f4xx_hal_pccard.h"
#include "stm32f4xx_hal_sdram.h"
#include "stm32f4xx_hal_hash.h"
#include "stm32f4xx_hal_i2c.h"
#include "stm32f4xx_hal_i2s.h"
#include "stm32f4xx_hal_iwdg.h"
#include "stm32f4xx_hal_ltdc.h"
#include "stm32f4xx_hal_pwr.h"
#include "stm32f4xx_hal_rng.h"
#include "stm32f4xx_hal_rtc.h"
#include "stm32f4xx_hal_sai.h"
#include "stm32f4xx_hal_sd.h"
#include "stm32f4xx_hal_spi.h"
#include "stm32f4xx_hal_tim.h"
#include "stm32f4xx_hal_uart.h"
#include "stm32f4xx_hal_usart.h"
#include "stm32f4xx_hal_irda.h"
#include "stm32f4xx_hal_smartcard.h"
#include "stm32f4xx_hal_wwdg.h"
#include "stm32f4xx_hal_pcd.h"
#include "stm32f4xx_hal_hcd.h"
#include "stm32f4xx_hal_dsi.h"
#include "stm32f4xx_hal_qspi.h"
#include "stm32f4xx_hal_cec.h"
#include "stm32f4xx_hal_fmpi2c.h"
#include "stm32f4xx_hal_spdifrx.h"
#include "stm32f4xx_hal_lptim.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CAN_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CEC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DCMI_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_DMA2D_MODULE_ENABLED
#define | HAL_ETH_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_PCCARD_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_SDRAM_MODULE_ENABLED
#define | HAL_HASH_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_LTDC_MODULE_ENABLED
#define | HAL_DSI_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_QSPI_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SAI_MODULE_ENABLED
#define | HAL_SD_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_HCD_MODULE_ENABLED
#define | HAL_FMPI2C_MODULE_ENABLED
#define | HAL_SPDIFRX_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HSE_VALUE ((uint32_t)25000000U)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT ((uint32_t)100U)
#define | HSI_VALUE ((uint32_t)16000000U)
Internal High Speed oscillator (HSI) value.
#define | LSI_VALUE ((uint32_t)32000U)
Internal Low Speed oscillator (LSI) value.
#define | LSE_VALUE ((uint32_t)32768U)
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT ((uint32_t)5000U)
#define | EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U)
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.
#define | VDD_VALUE ((uint32_t)3300U)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((uint32_t)0x0FU)
#define | USE_RTOS 0U
#define | PREFETCH_ENABLE 1U
#define | INSTRUCTION_CACHE_ENABLE 1U
#define | DATA_CACHE_ENABLE 1U
#define | MAC_ADDR0 2U
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.
#define | MAC_ADDR1 0U
#define | MAC_ADDR2 0U
#define | MAC_ADDR3 0U
#define | MAC_ADDR4 0U
#define | MAC_ADDR5 0U
#define | ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define | ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define | ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define | ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define | DP83848_PHY_ADDRESS 0x01U
#define | PHY_RESET_DELAY ((uint32_t)0x000000FFU)
#define | PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define | PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define | PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
#define | PHY_BCR ((uint16_t)0x0000U)
#define | PHY_BSR ((uint16_t)0x0001U)
#define | PHY_RESET ((uint16_t)0x8000U)
#define | PHY_LOOPBACK ((uint16_t)0x4000U)
#define | PHY_FULLDUPLEX_100M ((uint16_t)0x2100U)
#define | PHY_HALFDUPLEX_100M ((uint16_t)0x2000U)
#define | PHY_FULLDUPLEX_10M ((uint16_t)0x0100U)
#define | PHY_HALFDUPLEX_10M ((uint16_t)0x0000U)
#define | PHY_AUTONEGOTIATION ((uint16_t)0x1000U)
#define | PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U)
#define | PHY_POWERDOWN ((uint16_t)0x0800U)
#define | PHY_ISOLATE ((uint16_t)0x0400U)
#define | PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U)
#define | PHY_LINKED_STATUS ((uint16_t)0x0004U)
#define | PHY_JABBER_DETECTION ((uint16_t)0x0002U)
#define | PHY_SR ((uint16_t)0x0010U)
#define | PHY_MICR ((uint16_t)0x0011U)
#define | PHY_MISR ((uint16_t)0x0012U)
#define | PHY_LINK_STATUS ((uint16_t)0x0001U)
#define | PHY_SPEED_STATUS ((uint16_t)0x0002U)
#define | PHY_DUPLEX_STATUS ((uint16_t)0x0004U)
#define | PHY_MICR_INT_EN ((uint16_t)0x0002U)
#define | PHY_MICR_INT_OE ((uint16_t)0x0001U)
#define | PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U)
#define | PHY_LINK_INTERRUPT ((uint16_t)0x2000U)
#define | assert_param(expr) ((void)0)
Include module's header file.

Define Documentation

#define assert_param ( expr ) ((void)0)

Include module's header file.

Definition at line 429 of file stm32f4xx_hal_conf.h.

Referenced by ADC_Init(), FLASH_Erase_Sector(), FLASH_MassErase(), FLASH_OB_BOR_LevelConfig(), FLASH_OB_DisablePCROP(), FLASH_OB_DisableWRP(), FLASH_OB_EnablePCROP(), FLASH_OB_EnableWRP(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), FLASH_Program_Byte(), FLASH_Program_DoubleWord(), FLASH_Program_HalfWord(), FLASH_Program_Word(), FMPI2C_TransferConfig(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_TriangleWaveGenerate(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MultiBufferStart(), HAL_DMAEx_MultiBufferStart_IT(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_AdvOBProgram(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBProgram(), HAL_FMPI2C_DeInit(), HAL_FMPI2C_Init(), HAL_FMPI2C_Master_Sequential_Receive_IT(), HAL_FMPI2C_Master_Sequential_Transmit_IT(), HAL_FMPI2C_Mem_Read(), HAL_FMPI2C_Mem_Read_DMA(), HAL_FMPI2C_Mem_Read_IT(), HAL_FMPI2C_Mem_Write(), HAL_FMPI2C_Mem_Write_DMA(), HAL_FMPI2C_Mem_Write_IT(), HAL_FMPI2C_Slave_Sequential_Receive_IT(), HAL_FMPI2C_Slave_Sequential_Transmit_IT(), HAL_FMPI2CEx_ConfigAnalogFilter(), HAL_FMPI2CEx_ConfigDigitalFilter(), HAL_FMPI2CEx_DisableFastModePlus(), HAL_FMPI2CEx_DisableWakeUp(), HAL_FMPI2CEx_EnableFastModePlus(), HAL_FMPI2CEx_EnableWakeUp(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2S_Init(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_EnterMuteMode(), HAL_MultiProcessor_ExitMuteMode(), HAL_MultiProcessor_Init(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ControlVoltageScaling(), HAL_RCC_ClockConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RCCEx_SelectLSEMode(), HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetCoarseCalib(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WWDG_DeInit(), HAL_WWDG_Init(), HAL_WWDG_Refresh(), IRDA_SetConfig(), SMARTCARD_SetConfig(), TIM_CCxChannelCmd(), TIM_CCxNChannelCmd(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define DATA_CACHE_ENABLE 1U

Definition at line 163 of file stm32f4xx_hal_conf.h.

#define DP83848_PHY_ADDRESS 0x01U

Definition at line 193 of file stm32f4xx_hal_conf.h.

#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */

Definition at line 185 of file stm32f4xx_hal_conf.h.

#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */

Definition at line 187 of file stm32f4xx_hal_conf.h.

#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */

Definition at line 186 of file stm32f4xx_hal_conf.h.

#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */

Definition at line 188 of file stm32f4xx_hal_conf.h.

#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U)

External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S clock source frequency, this source is inserted directly through I2S_CKIN pad.

Value of the Internal oscillator in Hz

Definition at line 148 of file stm32f4xx_hal_conf.h.

Referenced by I2S_GetInputClock().

#define HAL_ADC_MODULE_ENABLED

Definition at line 56 of file stm32f4xx_hal_conf.h.

#define HAL_CAN_MODULE_ENABLED

Definition at line 57 of file stm32f4xx_hal_conf.h.

#define HAL_CEC_MODULE_ENABLED

Definition at line 59 of file stm32f4xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 93 of file stm32f4xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 58 of file stm32f4xx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 60 of file stm32f4xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 61 of file stm32f4xx_hal_conf.h.

#define HAL_DCMI_MODULE_ENABLED

Definition at line 62 of file stm32f4xx_hal_conf.h.

#define HAL_DMA2D_MODULE_ENABLED

Definition at line 64 of file stm32f4xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 63 of file stm32f4xx_hal_conf.h.

#define HAL_DSI_MODULE_ENABLED

Definition at line 78 of file stm32f4xx_hal_conf.h.

#define HAL_ETH_MODULE_ENABLED

Definition at line 65 of file stm32f4xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 66 of file stm32f4xx_hal_conf.h.

#define HAL_FMPI2C_MODULE_ENABLED

Definition at line 96 of file stm32f4xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 73 of file stm32f4xx_hal_conf.h.

#define HAL_HASH_MODULE_ENABLED

Definition at line 72 of file stm32f4xx_hal_conf.h.

#define HAL_HCD_MODULE_ENABLED

Definition at line 95 of file stm32f4xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 74 of file stm32f4xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 75 of file stm32f4xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 90 of file stm32f4xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 76 of file stm32f4xx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 98 of file stm32f4xx_hal_conf.h.

#define HAL_LTDC_MODULE_ENABLED

Definition at line 77 of file stm32f4xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 55 of file stm32f4xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 67 of file stm32f4xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 68 of file stm32f4xx_hal_conf.h.

#define HAL_PCCARD_MODULE_ENABLED

Definition at line 69 of file stm32f4xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 94 of file stm32f4xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 79 of file stm32f4xx_hal_conf.h.

#define HAL_QSPI_MODULE_ENABLED

Definition at line 80 of file stm32f4xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 81 of file stm32f4xx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 82 of file stm32f4xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 83 of file stm32f4xx_hal_conf.h.

#define HAL_SAI_MODULE_ENABLED

Definition at line 84 of file stm32f4xx_hal_conf.h.

#define HAL_SD_MODULE_ENABLED

Definition at line 85 of file stm32f4xx_hal_conf.h.

#define HAL_SDRAM_MODULE_ENABLED

Definition at line 71 of file stm32f4xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 91 of file stm32f4xx_hal_conf.h.

#define HAL_SPDIFRX_MODULE_ENABLED

Definition at line 97 of file stm32f4xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 86 of file stm32f4xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 70 of file stm32f4xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 87 of file stm32f4xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 88 of file stm32f4xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 89 of file stm32f4xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 92 of file stm32f4xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT ((uint32_t)100U)

Time out for HSE start up, in ms

Definition at line 111 of file stm32f4xx_hal_conf.h.

#define HSE_VALUE ((uint32_t)25000000U)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 107 of file stm32f4xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), and I2S_GetInputClock().

#define HSI_VALUE ((uint32_t)16000000U)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 120 of file stm32f4xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), and I2S_GetInputClock().

#define INSTRUCTION_CACHE_ENABLE 1U

Definition at line 162 of file stm32f4xx_hal_conf.h.

#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U)

Time out for LSE start up, in ms

Definition at line 139 of file stm32f4xx_hal_conf.h.

#define LSE_VALUE ((uint32_t)32768U)

External Low Speed oscillator (LSE) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. Value of the External Low Speed oscillator in Hz

Definition at line 135 of file stm32f4xx_hal_conf.h.

#define LSI_VALUE ((uint32_t)32000U)

Internal Low Speed oscillator (LSI) value.

LSI Typical Value in Hz

Definition at line 127 of file stm32f4xx_hal_conf.h.

#define MAC_ADDR0 2U

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Definition at line 177 of file stm32f4xx_hal_conf.h.

#define MAC_ADDR1 0U

Definition at line 178 of file stm32f4xx_hal_conf.h.

#define MAC_ADDR2 0U

Definition at line 179 of file stm32f4xx_hal_conf.h.

#define MAC_ADDR3 0U

Definition at line 180 of file stm32f4xx_hal_conf.h.

#define MAC_ADDR4 0U

Definition at line 181 of file stm32f4xx_hal_conf.h.

#define MAC_ADDR5 0U

Definition at line 182 of file stm32f4xx_hal_conf.h.

#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U)

Auto-Negotiation process completed

Definition at line 218 of file stm32f4xx_hal_conf.h.

#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U)

Enable auto-negotiation function

Definition at line 213 of file stm32f4xx_hal_conf.h.

#define PHY_BCR ((uint16_t)0x0000U)

Transceiver Basic Control Register

Definition at line 204 of file stm32f4xx_hal_conf.h.

#define PHY_BSR ((uint16_t)0x0001U)

Transceiver Basic Status Register

Definition at line 205 of file stm32f4xx_hal_conf.h.

#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)

Definition at line 197 of file stm32f4xx_hal_conf.h.

#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U)

PHY Duplex mask

Definition at line 230 of file stm32f4xx_hal_conf.h.

#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U)

Set the full-duplex mode at 100 Mb/s

Definition at line 209 of file stm32f4xx_hal_conf.h.

#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U)

Set the full-duplex mode at 10 Mb/s

Definition at line 211 of file stm32f4xx_hal_conf.h.

#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U)

Set the half-duplex mode at 100 Mb/s

Definition at line 210 of file stm32f4xx_hal_conf.h.

#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U)

Set the half-duplex mode at 10 Mb/s

Definition at line 212 of file stm32f4xx_hal_conf.h.

#define PHY_ISOLATE ((uint16_t)0x0400U)

Isolate PHY from MII

Definition at line 216 of file stm32f4xx_hal_conf.h.

#define PHY_JABBER_DETECTION ((uint16_t)0x0002U)

Jabber condition detected

Definition at line 220 of file stm32f4xx_hal_conf.h.

#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U)

PHY link status interrupt mask

Definition at line 236 of file stm32f4xx_hal_conf.h.

#define PHY_LINK_STATUS ((uint16_t)0x0001U)

PHY Link mask

Definition at line 228 of file stm32f4xx_hal_conf.h.

#define PHY_LINKED_STATUS ((uint16_t)0x0004U)

Valid link established

Definition at line 219 of file stm32f4xx_hal_conf.h.

#define PHY_LOOPBACK ((uint16_t)0x4000U)

Select loop-back mode

Definition at line 208 of file stm32f4xx_hal_conf.h.

#define PHY_MICR ((uint16_t)0x0011U)

MII Interrupt Control Register

Definition at line 225 of file stm32f4xx_hal_conf.h.

#define PHY_MICR_INT_EN ((uint16_t)0x0002U)

PHY Enable interrupts

Definition at line 232 of file stm32f4xx_hal_conf.h.

#define PHY_MICR_INT_OE ((uint16_t)0x0001U)

PHY Enable output interrupt events

Definition at line 233 of file stm32f4xx_hal_conf.h.

#define PHY_MISR ((uint16_t)0x0012U)

MII Interrupt Status and Misc. Control Register

Definition at line 226 of file stm32f4xx_hal_conf.h.

#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U)

Enable Interrupt on change of link status

Definition at line 235 of file stm32f4xx_hal_conf.h.

#define PHY_POWERDOWN ((uint16_t)0x0800U)

Select the power down mode

Definition at line 215 of file stm32f4xx_hal_conf.h.

#define PHY_READ_TO ((uint32_t)0x0000FFFFU)

Definition at line 199 of file stm32f4xx_hal_conf.h.

#define PHY_RESET ((uint16_t)0x8000U)

PHY Reset

Definition at line 207 of file stm32f4xx_hal_conf.h.

#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)

Definition at line 195 of file stm32f4xx_hal_conf.h.

#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U)

Restart auto-negotiation function

Definition at line 214 of file stm32f4xx_hal_conf.h.

#define PHY_SPEED_STATUS ((uint16_t)0x0002U)

PHY Speed mask

Definition at line 229 of file stm32f4xx_hal_conf.h.

#define PHY_SR ((uint16_t)0x0010U)

PHY status register Offset

Definition at line 224 of file stm32f4xx_hal_conf.h.

#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)

Definition at line 200 of file stm32f4xx_hal_conf.h.

#define PREFETCH_ENABLE 1U

Definition at line 161 of file stm32f4xx_hal_conf.h.

#define TICK_INT_PRIORITY ((uint32_t)0x0FU)

tick interrupt priority

Definition at line 159 of file stm32f4xx_hal_conf.h.

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

#define USE_RTOS 0U

Definition at line 160 of file stm32f4xx_hal_conf.h.

#define VDD_VALUE ((uint32_t)3300U)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 158 of file stm32f4xx_hal_conf.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
  • Src
stm32f4xx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams one for managing data transfer from
                 memory to peripheral (input stream) and another stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
         (##) The encryption/decryption key. It's size depends on the algorithm
              used for encryption/decryption
         (##) The initialization vector (counter). It is not used ECB mode.

      (#)Three processing (encryption/decryption) functions are available:
         (##) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished,
              e.g. HAL_CRYP_AESCBC_Encrypt()
         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt,
              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
         (##) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA,
              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()

      (#)When the processing function is called at first time after HAL_CRYP_Init()
         the CRYP peripheral is initialized and processes the buffer in input.
         At second call, the processing function performs an append of the already
         processed buffer.
         When a new data block is to be processed, call HAL_CRYP_Init() then the
         processing function.

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cryp.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp.h File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
  • Inc
stm32f4xx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cryp.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp_ex.c File Reference

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stm32f4xx_hal_cryp_ex.c File Reference

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The CRYP Extension HAL driver can be used as follows:
    (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
        (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
        (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
            (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
        (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++) Configure and enable two DMA streams one for managing data transfer from
                memory to peripheral (input stream) and another stream for managing data
                transfer from peripheral to memory (output stream)
            (+++) Associate the initialized DMA handle to the CRYP DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the two DMA Streams. The output stream should have higher
                priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
    (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
        (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
        (##) The encryption/decryption key. Its size depends on the algorithm
                used for encryption/decryption
        (##) The initialization vector (counter). It is not used ECB mode.
    (#)Three processing (encryption/decryption) functions are available:
        (##) Polling mode: encryption and decryption APIs are blocking functions
             i.e. they process the data and wait till the processing is finished
             e.g. HAL_CRYPEx_AESGCM_Encrypt()
        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
                i.e. they process the data under interrupt
                e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
        (##) DMA mode: encryption and decryption APIs are not blocking functions
                i.e. the data transfer is ensured by DMA
                e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
    (#)When the processing function is called at first time after HAL_CRYP_Init()
       the CRYP peripheral is initialized and processes the buffer in input.
       At second call, the processing function performs an append of the already
       processed buffer.
       When a new data block is to be processed, call HAL_CRYP_Init() then the
       processing function.
    (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
       which provide authentication messages.
       HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
       authentication messages.
       Call those functions after the processing ones (polling, interrupt or DMA).
       e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
            then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
     -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
     -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
           (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
    (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cryp_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp_ex.h File Reference

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stm32f4xx_hal_cryp_ex.h File Reference

Header file of CRYP HAL Extension module. More...

Go to the source code of this file.

Detailed Description

Header file of CRYP HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cryp_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi.c File Reference

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stm32f4xx_hal_dcmi.c File Reference

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
      The sequence below describes how to use this driver to capture image
      from a camera module connected to the DCMI Interface.
      This sequence does not take into account the configuration of the
      camera module, which should be made before to configure and enable
      the DCMI to capture images.

    (#) Program the required configuration through following parameters:
        horizontal and vertical polarity, pixel clock polarity, Capture Rate,
        Synchronization Mode, code of the frame delimiter and data width
        using HAL_DCMI_Init() function.

    (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
        register to the destination memory buffer.

    (#) Program the required configuration through following parameters:
        DCMI mode, destination memory Buffer address and the data length
        and enable capture using HAL_DCMI_Start_DMA() function.

    (#) Optionally, configure and Enable the CROP feature to select a rectangular
        window from the received image using HAL_DCMI_ConfigCrop()
        and HAL_DCMI_EnableCROP() functions

    (#) The capture can be stopped using HAL_DCMI_Stop() function.

    (#) To control DCMI state you can use the function HAL_DCMI_GetState().

     *** DCMI HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DCMI HAL driver.

      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.

     [..]
       (@) You can refer to the DCMI HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dcmi.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi.h File Reference

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stm32f4xx_hal_dcmi.h File Reference

Header file of DCMI HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DCMI HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dcmi.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi_ex.c File Reference

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stm32f4xx_hal_dcmi_ex.c File Reference

DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
               ##### DCMI peripheral extension features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the DCMI interface for STM32F446xx
       devices contains the following additional features :

       (+) Support of Black and White cameras

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to manage the Black and White feature
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dcmi_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi_ex.h File Reference

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stm32f4xx_hal_dcmi_ex.h File Reference

Header file of DCMI Extension HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DCMI Extension HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dcmi_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma2d.c File Reference

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stm32f4xx_hal_dma2d.c File Reference

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Program the required configuration through following parameters:
          the Transfer Mode, the output color mode and the output offset using
          HAL_DMA2D_Init() function.

      (#) Program the required configuration through following parameters:
          the input color mode, the input color, input alpha value, alpha mode
          and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
          or/and background layer.

     *** Polling mode IO operation ***
     =================================
    [..]
       (+) Configure the pdata, Destination and data length and Enable
           the transfer using HAL_DMA2D_Start()
       (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
           user can specify the value of timeout according to his end application.

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (#) Configure the pdata, Destination and data length and Enable
           the transfer using HAL_DMA2D_Start_IT()
       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
           add his own function by customization of function pointer XferCpltCallback and
           XferErrorCallback (i.e a member of DMA2D handle structure).

         -@-   In Register-to-Memory transfer mode, the pdata parameter is the register
               color, in Memory-to-memory or memory-to-memory with pixel format
               conversion the pdata is the source address.

         -@-   Configure the foreground source address, the background source address,
               the Destination and data length and Enable the transfer using
               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
               in interrupt mode.

         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
               are used if the memory to memory with blending transfer mode is selected.

      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
          HAL_DMA2D_EnableCLUT() functions.

      (#) Optionally, configure and enable LineInterrupt using the following function:
          HAL_DMA2D_ProgramLineEvent().

      (#) The transfer can be suspended, continued and aborted using the following
          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().

      (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()

     *** DMA2D HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA2D HAL driver :

      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
      (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA2D HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dma2d.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma2d.h File Reference

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stm32f4xx_hal_dma2d.h File Reference

Header file of DMA2D HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DMA2D HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dma2d.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dsi.c File Reference

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stm32f4xx_hal_dsi.c File Reference

DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dsi.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dsi.h File Reference

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stm32f4xx_hal_dsi.h File Reference

Header file of DSI HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DSI HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dsi.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_eth.c File Reference

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stm32f4xx_hal_eth.c File Reference

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      (#)Declare a ETH_HandleTypeDef handle structure, for example:
         ETH_HandleTypeDef  heth;

      (#)Fill parameters of Init structure in heth handle

      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)

      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
          (##) Enable the Ethernet interface clock using
               (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
               (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
               (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();

          (##) Initialize the related GPIO clocks
          (##) Configure Ethernet pin-out
          (##) Configure Ethernet NVIC interrupt (IT mode)

      (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
          (##) HAL_ETH_DMATxDescListInit(); for Transmission process
          (##) HAL_ETH_DMARxDescListInit(); for Reception process

      (#)Enable MAC and DMA transmission and reception:
          (##) HAL_ETH_Start();

      (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
         the frame to MAC TX FIFO:
         (##) HAL_ETH_TransmitFrame();

      (#)Poll for a received frame in ETH RX DMA Descriptors and get received
         frame parameters
         (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)

      (#) Get a received frame when an ETH RX interrupt occurs:
         (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)

      (#) Communicate with external PHY device:
         (##) Read a specific register from the PHY
              HAL_ETH_ReadPHYRegister();
         (##) Write data to a specific RHY register:
              HAL_ETH_WritePHYRegister();

      (#) Configure the Ethernet MAC after ETH peripheral initialization
          HAL_ETH_ConfigMAC(); all MAC parameters should be filled.

      (#) Configure the Ethernet DMA after ETH peripheral initialization
          HAL_ETH_ConfigDMA(); all DMA parameters should be filled.

      -@- The PTP protocol and the DMA descriptors ring mode are not supported
          in this driver
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_eth.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_eth.h File Reference

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stm32f4xx_hal_eth.h File Reference

Header file of ETH HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of ETH HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_eth.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash.c File Reference

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stm32f4xx_hal_hash.c File Reference

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The HASH HAL driver can be used as follows:
    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
        (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++) Configure and enable one DMA stream one for managing data transfer from
                memory to peripheral (input stream). Managing data transfer from
                peripheral to memory can be performed only using CPU
            (+++) Associate the initialized DMA handle to the HASH DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
        (##) For HMAC, the encryption key.
        (##) For HMAC, the key size used for encryption.
    (#)Three processing functions are available:
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished
             e.g. HAL_HASH_SHA1_Start()
        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
                i.e. they process the data under interrupt
                e.g. HAL_HASH_SHA1_Start_IT()
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA
                e.g. HAL_HASH_SHA1_Start_DMA()
    (#)When the processing function is called at first time after HAL_HASH_Init()
       the HASH peripheral is initialized and processes the buffer in input.
       After that, the digest computation is started.
       When processing multi-buffer use the accumulate function to write the
       data in the peripheral without starting the digest computation. In last
       buffer use the start function to input the last buffer ans start the digest
       computation.
       (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
       (##) write (n-1)th data buffer in the peripheral without starting the digest computation
       (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
       After that, call the finish function in order to get the digest value
       e.g. HAL_HASH_SHA1_Finish()
    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_hash.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash.h File Reference

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stm32f4xx_hal_hash.h File Reference

Header file of HASH HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of HASH HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_hash.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash_ex.c File Reference

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stm32f4xx_hal_hash_ex.c File Reference

HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The HASH HAL driver can be used as follows:
    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
        (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
            (+++) Configure and enable one DMA stream one for managing data transfer from
                memory to peripheral (input stream). Managing data transfer from
                peripheral to memory can be performed only using CPU
            (+++) Associate the initialized DMA handle to the HASH DMA handle
                using  __HAL_LINKDMA()
            (+++) Configure the priority and enable the NVIC for the transfer complete
                interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
        (##) For HMAC, the encryption key.
        (##) For HMAC, the key size used for encryption.
    (#)Three processing functions are available:
        (##) Polling mode: processing APIs are blocking functions
             i.e. they process the data and wait till the digest computation is finished
             e.g. HAL_HASHEx_SHA224_Start()
        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
                i.e. they process the data under interrupt
                e.g. HAL_HASHEx_SHA224_Start_IT()
        (##) DMA mode: processing APIs are not blocking functions and the CPU is
             not used for data transfer i.e. the data transfer is ensured by DMA
                e.g. HAL_HASHEx_SHA224_Start_DMA()
    (#)When the processing function is called at first time after HAL_HASH_Init()
       the HASH peripheral is initialized and processes the buffer in input.
       After that, the digest computation is started.
       When processing multi-buffer use the accumulate function to write the
       data in the peripheral without starting the digest computation. In last
       buffer use the start function to input the last buffer ans start the digest
       computation.
       (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
       (##)  write (n-1)th data buffer in the peripheral without starting the digest computation
       (##)  HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
       After that, call the finish function in order to get the digest value
       e.g. HAL_HASHEx_SHA224_Finish()
    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_hash_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash_ex.h File Reference

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stm32f4xx_hal_hash_ex.h File Reference

Header file of HASH HAL Extension module. More...

Go to the source code of this file.

Detailed Description

Header file of HASH HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_hash_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hcd.c File Reference

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stm32f4xx_hal_hcd.c File Reference

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
  [..]
    (#)Declare a HCD_HandleTypeDef handle structure, for example:
       HCD_HandleTypeDef  hhcd;

    (#)Fill parameters of Init structure in HCD handle

    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)

    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
        (##) Enable the HCD/USB Low Level interface clock using the following macros
             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)

        (##) Initialize the related GPIO clocks
        (##) Configure HCD pin-out
        (##) Configure HCD NVIC interrupt

    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
        (##) hhcd.pData = phost;

    (#)Enable HCD transmission and reception:
        (##) HAL_HCD_Start();
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_hcd.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hcd.h File Reference

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stm32f4xx_hal_hcd.h File Reference

Header file of HCD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of HCD HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_hcd.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c_ex.c File Reference

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stm32f4xx_hal_i2c_ex.c File Reference

I2C Extension HAL module driver. This file provides firmware functions to manage the following functionalities of I2C extension peripheral: + Extension features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

I2C Extension HAL module driver. This file provides firmware functions to manage the following functionalities of I2C extension peripheral: + Extension features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
               ##### I2C peripheral extension features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/
       429xx/439xx devices contains the following additional features :

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter
    (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config()
    (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2c_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c_ex.h File Reference

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stm32f4xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extension module. More...

Go to the source code of this file.

Detailed Description

Header file of I2C HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2c_ex.h.

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STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc.c File Reference

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stm32f4xx_hal_ltdc.c File Reference

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Program the required configuration through the following parameters:
         the LTDC timing, the horizontal and vertical polarity,
         the pixel clock polarity, Data Enable polarity and the LTDC background color value
         using HAL_LTDC_Init() function

     (#) Program the required configuration through the following parameters:
         the pixel format, the blending factors, input alpha value, the window size
         and the image size using HAL_LTDC_ConfigLayer() function for foreground
         or/and background layer.

     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
         HAL_LTDC_EnableCLUT functions.

     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().

     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
         and HAL_LTDC_EnableColorKeying functions.

     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
         function

     (#) If needed, reconfigure and change the pixel format value, the alpha value
         value, the window size, the window position and the layer start address
         for foreground or/and background layer using respectively the following
         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
         HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.

     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()

     *** LTDC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in LTDC HAL driver.

      (+) __HAL_LTDC_ENABLE: Enable the LTDC.
      (+) __HAL_LTDC_DISABLE: Disable the LTDC.
      (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.
      (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.
      (+) __HAL_LTDC_RELOAD_CONFIG: Reload  Layer Configuration.
      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.

     [..]
       (@) You can refer to the LTDC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_ltdc.c.

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STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc.h File Reference

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stm32f4xx_hal_ltdc.h File Reference

Header file of LTDC HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of LTDC HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_ltdc.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc_ex.c File Reference

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stm32f4xx_hal_ltdc_ex.c File Reference

LTDC Extension HAL module driver. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

LTDC Extension HAL module driver.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_ltdc_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc_ex.h File Reference

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stm32f4xx_hal_ltdc_ex.h File Reference

Header file of LTDC HAL Extension module. More...

Go to the source code of this file.

Detailed Description

Header file of LTDC HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_ltdc_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_nand.c File Reference

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stm32f4xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FMC/FSMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_nand.c.

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STM32F410Rx HAL User Manual: stm32f4xx_hal_nand.h File Reference

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stm32f4xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_nand.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_nor.c File Reference

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stm32f4xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FMC/FSMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE : NOR memory write data to specified address
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_nor.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_nor.h File Reference

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stm32f4xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_nor.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pccard.c File Reference

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stm32f4xx_hal_pccard.c File Reference

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
   [..]
     This driver is a generic layered driver which contains a set of APIs used to
     control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
     to interface with PCCARD devices. This driver is used for:

    (+) PCCARD/Compact Flash memory configuration sequence using the function
        HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
        both common and attribute spaces.

    (+) Read PCCARD/Compact Flash memory maker and device IDs using the function
        HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
        the CompactFlash_ID structure declared by the function caller.

    (+) Access PCCARD/Compact Flash memory by read/write operations using the functions
        HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
        HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.

    (+) Perform PCCARD/Compact Flash Reset chip operation using the function
        HAL_PCCARD_Reset()/HAL_CF_Reset.

    (+) Perform PCCARD/Compact Flash erase sector operation using the function
        HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.

    (+) Read the PCCARD/Compact Flash status operation using the function
        HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().

    (+) You can monitor the PCCARD/Compact Flash  device HAL state by calling
        the function HAL_PCCARD_GetState()/HAL_CF_GetState()

   [..]
     (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
         operations. If a PCCARD/Compact Flash device contains different operations
         and/or implementations, it should be implemented separately.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pccard.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pccard.h File Reference

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stm32f4xx_hal_pccard.h File Reference

Header file of PCCARD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of PCCARD HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pccard.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd.c File Reference

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stm32f4xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable PCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pcd.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd.h File Reference

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stm32f4xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pcd.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd_ex.c File Reference

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stm32f4xx_hal_pcd_ex.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pcd_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd_ex.h File Reference

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stm32f4xx_hal_pcd_ex.h File Reference

Header file of PCD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pcd_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_qspi.c File Reference

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stm32f4xx_hal_qspi.c File Reference

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
        (##) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
        (##) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
        (##) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (##) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
        (##) If interrupt mode is used, enable and configure QuadSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (##) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
          functions :
         (##) Instruction phase : the mode used and if present the instruction opcode.
         (##) Address phase : the mode used and if present the size and the address value.
         (##) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (##) Data phase : the mode used and if present the number of bytes.
         (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
      (#) If no data is required for the command, it is sent directly to the memory :
         (##) In polling mode, the output of the function is done when the transfer is complete.
         (##) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
          HAL_QSPI_Transmit_IT() after the command configuration :
         (##) In polling mode, the output of the function is done when the transfer is complete.
         (##) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
         (##) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
          HAL_QSPI_Receive_IT() after the command configuration :
         (##) In polling mode, the output of the function is done when the transfer is complete.
         (##) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
         (##) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence and the auto-polling functional mode using the
          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
         (##) Instruction phase : the mode used and if present the instruction opcode.
         (##) Address phase : the mode used and if present the size and the address value.
         (##) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (##) Data phase : the mode used.
         (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (##) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (##) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (##) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence and the memory-mapped functional mode using the
          HAL_QSPI_MemoryMapped() functions :
         (##) Instruction phase : the mode used and if present the instruction opcode.
         (##) Address phase : the mode used and the size.
         (##) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (##) Data phase : the mode used.
         (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (##) The timeout activation and the timeout period.
      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    ==================================================
    [..]
      (#) HAL_QSPI_GetError() function gives the error rised during the last operation.
      (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.

    *** Workarounds linked to Silicon Limitation ***
    ====================================================
    [..]
      (#) Workarounds Implemented inside HAL Driver
         (++) Extra data written in the FIFO at the end of a read transfer
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_qspi.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_qspi.h File Reference

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stm32f4xx_hal_qspi.h File Reference

Header file of QSPI HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of QSPI HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_qspi.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai.c File Reference

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stm32f4xx_hal_sai.c File Reference

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================

  [..]
    The SAI HAL driver can be used as follows:

    (#) Declare a SAI_HandleTypeDef handle structure.
    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
        (##) Enable the SAI interface clock.
        (##) SAI pins configuration:
            (+++) Enable the clock for the SAI GPIOs.
            (+++) Configure these SAI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
             and HAL_SAI_Receive_IT() APIs):
            (+++) Configure the SAI interrupt priority.
            (+++) Enable the NVIC SAI IRQ handle.

        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
             and HAL_SAI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

   (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_SAI_Init() function.

   -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
       will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
       inside the transmit and receive process.

  [..]
   (@) SAI Clock Source configuration is managed differently depending on the selected
       STM32F4 devices :
       (+@) For STM32F446xx devices, the configuration is managed through RCCEx_PeriphCLKConfig()
            function in the HAL RCC drivers
       (+@) For STM32F439xx/STM32F437xx/STM32F429xx/STM32F427xx devices, the configuration
            is managed within HAL SAI drivers through HAL_SAI_Init() function using
            ClockSource field of SAI_InitTypeDef structure.
  [..]
   (@) Make sure that either:
       (+@) I2S PLL is configured or
       (+@) SAI PLL is configured or
       (+@) External clock source is configured after setting correctly
            the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.

  [..]
    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
        for the external slaves even if there is no data in the FIFO, However FS signal
        generation is conditioned by the presence of data in the FIFO.

  [..]
    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
        and FS signal for the external slaves.

  [..]
    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
        (+@)  First bit Offset <= (SLOT size - Data size)
        (+@)  Data size <= SLOT size
        (+@)  Number of SLOT x SLOT size = Frame length
        (+@)  The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.

  [..]
     Three operation modes are available within this driver:

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT()
     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT()
     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_RxCpltCallback
     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SAI_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA()
     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA()
     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SAI_RxCpltCallback
     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SAI_ErrorCallback
     (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
     (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
     (+) Stop the DMA Transfer using HAL_SAI_DMAStop()

   *** SAI HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in USART HAL driver :

      (+) __HAL_SAI_ENABLE: Enable the SAI peripheral
      (+) __HAL_SAI_DISABLE: Disable the SAI peripheral
      (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts
      (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts
      (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is
          enabled or disabled
      (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sai.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai.h File Reference

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stm32f4xx_hal_sai.h File Reference

Header file of SAI HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of SAI HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sai.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai_ex.c File Reference

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stm32f4xx_hal_sai_ex.c File Reference

SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
               ##### SAI peripheral extension features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the SAI interface for STM32F446xx
       devices contains the following additional features :

       (+) Possibility to be clocked from PLLR

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to manage several sources to clock SAI
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sai_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai_ex.h File Reference

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stm32f4xx_hal_sai_ex.h File Reference

Header file of SAI Extension HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of SAI Extension HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sai_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sd.c File Reference

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stm32f4xx_hal_sd.c File Reference

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
    the user in HAL_SD_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDIO memories which uses the HAL
    SDIO driver functions to interface with SD and uSD cards devices.
    It is used as follows:

    (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
        (##) SDIO pins configuration for SD card
            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
             and HAL_SD_WriteBlocks_DMA() APIs).
            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
            (+++) Configure the SDIO and DMA interrupt priorities using functions
                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT()
                  and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
                  and __HAL_SD_SDIO_CLEAR_IT()
    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization

  *** SD Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes
    the SD Card and put it into Standby State (Ready for data transfer).
    This function provide the following operations:

    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
        type (Standard Capacity or High Capacity). You can change or adapt this
        frequency by adjusting the "ClockDiv" field.
        The SD Card frequency (SDIO_CK) is computed as follows:

           SDIO_CK = SDIOCLK / (ClockDiv + 2)

        In initialization mode and according to the SD Card standard,
        make sure that the SDIO_CK frequency doesn't exceed 400KHz.

    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
        structure. This structure provide also ready computed SD Card capacity
        and Block size.

        -@- These information are stored in SD handle structure in case of future use.

    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
        frequency is set to 24MHz. You can change or adapt this frequency by adjusting
        the "ClockDiv" field.
        In transfer mode and according to the SD Card standard, make sure that the
        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
        To be able to use a frequency higher than 24MHz, you should use the SDIO
        peripheral in bypass mode. Refer to the corresponding reference manual
        for more details.

    (#) Select the corresponding SD Card according to the address read with the step 2.

    (#) Configure the SD Card in wide bus mode: 4-bits data.

  *** SD Card Read operation ***
  ==============================
  [..]
    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
        that the read transfer is done correctly in both DMA and SD sides.

  *** SD Card Write operation ***
  ===============================
  [..]
    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 byte).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
        that the write transfer is done correctly in both DMA and SD sides.

  *** SD card status ***
  ======================
  [..]
    (+) At any time, you can check the SD Card status and get the SD card state
        by using the HAL_SD_GetStatus() function. This function checks first if the
        SD card is still connected and then get the internal SD Card transfer state.
    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
        function.

  *** SD HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in SD HAL driver.

    (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
    (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
    (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
    (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
    (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
    (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
    (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
    (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags

    (@) You can refer to the SD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sd.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sd.h File Reference

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stm32f4xx_hal_sd.h File Reference

Header file of SD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SD HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sd.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sdram.c File Reference

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stm32f4xx_hal_sdram.c File Reference

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                       ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SDRAM memories. It uses the FMC layer functions to interface
    with SDRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SDRAM memories:

   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
          SDRAM_HandleTypeDef  hdsram

       (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SDRAM device

   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
          FMC_SDRAM_TimingTypeDef  Timing;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
       (##) Control register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Init()
       (##) Timing register configuration using the FMC SDRAM interface function
            FMC_SDRAM_Timing_Init()
       (##) Program the SDRAM external device by applying its initialization sequence
            according to the device plugged in your hardware. This step is mandatory
            for accessing the SDRAM device.

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the SDRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
       structure.

   (#) You can continuously monitor the SDRAM device HAL state by calling the function
       HAL_SDRAM_GetState()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sdram.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sdram.h File Reference

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stm32f4xx_hal_sdram.h File Reference

Header file of SDRAM HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SDRAM HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sdram.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spdifrx.c File Reference

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stm32f4xx_hal_spdifrx.c File Reference

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The SPDIFRX HAL driver can be used as follow:

    (#) Declare SPDIFRX_HandleTypeDef handle structure.
    (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
        (##) Enable the SPDIFRX interface clock.
        (##) SPDIFRX pins configuration:
            (+++) Enable the clock for the SPDIFRX GPIOs.
            (+++) Configure these SPDIFRX pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
            (+++) Configure the SPDIFRX interrupt priority.
            (+++) Enable the NVIC SPDIFRX IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
            (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
                      (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
            (+++) Configure the DMA Channel.
            (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA CtrlRx/DataRx channel.

   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
       using HAL_SPDIFRX_Init() function.

   -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
       __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
   -@- Make sure that ck_spdif clock is configured.

   (#) Three operation modes are available within this driver :

   *** Polling mode for reception operation (for debug purpose) ***
   ================================================================
   [..]
     (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
         (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()

   *** Interrupt mode for reception operation ***
   =========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
         (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback

   *** DMA mode for reception operation ***
   ========================================
   [..]
     (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
         (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
     (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()

   *** SPDIFRX HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in SPDIFRX HAL driver.
      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
      (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
      (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
      (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.

    [..]
      (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_spdifrx.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spdifrx.h File Reference

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stm32f4xx_hal_spdifrx.h File Reference

Header file of SPDIFRX HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SPDIFRX HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_spdifrx.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sram.c File Reference

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stm32f4xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FMC/FSMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Init()
       (##) Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sram.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sram.h File Reference

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  • Drivers
  • STM32F4xx_HAL_Driver
  • Inc
stm32f4xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_sram.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __HAL_ADC_CLEAR_FLAG : stm32f4xx_hal_adc.h
  • __HAL_ADC_DISABLE : stm32f4xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32f4xx_hal_adc.h
  • __HAL_ADC_ENABLE : stm32f4xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32f4xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32f4xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f4xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f4xx_hal_adc.h
  • __HAL_CRC_DR_RESET : stm32f4xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f4xx_hal_crc.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f4xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f4xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32f4xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32f4xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32f4xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32f4xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32f4xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32f4xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32f4xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32f4xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_CAN2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM10 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM11 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM9 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM10 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM11 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM12 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM13 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM9 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f4xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32f4xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32f4xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f4xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f4xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f4xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32f4xx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32f4xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32f4xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32f4xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32f4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32f4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f4xx_hal_flash.h
  • __HAL_FMPI2C_CLEAR_FLAG : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_DISABLE : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_DISABLE_IT : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_ENABLE : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_ENABLE_IT : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_GET_FLAG : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_GET_IT_SOURCE : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_RESET_HANDLE_STATE : stm32f4xx_hal_fmpi2c.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f4xx_hal_gpio.h
  • __HAL_I2C_CLEAR_ADDRFLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_CLEAR_FLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_CLEAR_STOPFLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f4xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f4xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f4xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f4xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f4xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f4xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32f4xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32f4xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32f4xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32f4xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32f4xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32f4xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32f4xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32f4xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32f4xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f4xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32f4xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f4xx_hal_irda.h
  • __HAL_IWDG_GET_FLAG : stm32f4xx_hal_iwdg.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f4xx_hal_iwdg.h
  • __HAL_IWDG_RESET_HANDLE_STATE : stm32f4xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f4xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_OPTR_CONFIG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_StateTypeDef : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_PWR_CLEAR_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32f4xx_hal_pwr_ex.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_EXTIT_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GET_FMPI2C1_SOURCE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S_SOURCE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2S_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_MCO1_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_MCO1_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_MCO2_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_MCO2_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_MCO2_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32f4xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32f4xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32f4xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32f4xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32f4xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_COARSE_CALIB_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_COARSE_CALIB_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f4xx_hal_rtc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_DISABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_ENABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f4xx_hal_smartcard.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f4xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f4xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f4xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f4xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f4xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f4xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32f4xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32f4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32f4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32f4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32f4xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32f4xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f4xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f4xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f4xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f4xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f4xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f4xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f4xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f4xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f4xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f4xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f4xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f4xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f4xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f4xx_hal_usart.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_RESET_HANDLE_STATE : stm32f4xx_hal_wwdg.h
  • __MCO1_CLK_ENABLE : stm32f4xx_hal_rcc.c
  • __MCO2_CLK_ENABLE : stm32f4xx_hal_rcc.c
  • __STM32F4xx_HAL_VERSION : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_MAIN : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_RC : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_SUB1 : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_SUB2 : stm32f4xx_hal.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ACR_BYTE0_ADDRESS : stm32f4xx_hal_flash.h
  • ADC_ALL_CHANNELS : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f4xx_hal_adc.h
  • ADC_AWD_EVENT : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_0 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_1 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_11 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_12 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_13 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_14 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_15 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_16 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_17 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_18 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_2 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_3 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_4 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_5 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_6 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_7 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_8 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_9 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f4xx_hal_adc_ex.h
  • ADC_CHANNEL_VBAT : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32f4xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV6 : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV8 : stm32f4xx_hal_adc.h
  • ADC_CR1_DISCONTINUOUS : stm32f4xx_hal_adc.h
  • ADC_CR1_SCANCONV : stm32f4xx_hal_adc.h
  • ADC_CR2_CONTINUOUS : stm32f4xx_hal_adc.h
  • ADC_CR2_DMAContReq : stm32f4xx_hal_adc.h
  • ADC_CR2_EOCSelection : stm32f4xx_hal_adc.h
  • ADC_DATAALIGN_LEFT : stm32f4xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32f4xx_hal_adc.h
  • ADC_DMAACCESSMODE_1 : stm32f4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_2 : stm32f4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_3 : stm32f4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32f4xx_hal_adc_ex.h
  • ADC_DMAConvCplt() : stm32f4xx_hal_adc.c
  • ADC_DMAError() : stm32f4xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32f4xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32f4xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32f4xx_hal_adc.h
  • ADC_EOC_SINGLE_SEQ_CONV : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_Ext_IT11 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC2 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC3 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC3 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC4 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_TRGO : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T3_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T3_TRGO : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_CC2 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_CC3 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_TRGO : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGINJECCONV_EXT_IT15 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC2 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_CC1 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_CC2 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_CC3 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T5_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T5_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC2 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC3 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_FALLING : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_NONE : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISING : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING : stm32f4xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f4xx_hal_adc.h
  • ADC_FLAG_EOC : stm32f4xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32f4xx_hal_adc.h
  • ADC_FLAG_JSTRT : stm32f4xx_hal_adc.h
  • ADC_FLAG_OVR : stm32f4xx_hal_adc.h
  • ADC_FLAG_STRT : stm32f4xx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32f4xx_hal_adc.h
  • ADC_Init() : stm32f4xx_hal_adc.c
  • ADC_INJECTED_CHANNELS : stm32f4xx_hal_adc.h
  • ADC_INJECTED_RANK_1 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f4xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f4xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f4xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f4xx_hal_adc.h
  • ADC_IT_AWD : stm32f4xx_hal_adc.h
  • ADC_IT_EOC : stm32f4xx_hal_adc.h
  • ADC_IT_JEOC : stm32f4xx_hal_adc.h
  • ADC_IT_OVR : stm32f4xx_hal_adc.h
  • ADC_JSQR : stm32f4xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32f4xx_hal_adc_ex.h
  • ADC_MultiModeDMAConvCplt() : stm32f4xx_hal_adc_ex.c
  • ADC_MultiModeDMAError() : stm32f4xx_hal_adc_ex.c
  • ADC_MultiModeDMAHalfConvCplt() : stm32f4xx_hal_adc_ex.c
  • ADC_OVR_EVENT : stm32f4xx_hal_adc.h
  • ADC_REGULAR_CHANNELS : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_112CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_144CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_15CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_480CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_56CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_84CYCLES : stm32f4xx_hal_adc.h
  • ADC_SMPR1 : stm32f4xx_hal_adc.h
  • ADC_SMPR2 : stm32f4xx_hal_adc.h
  • ADC_SOFTWARE_START : stm32f4xx_hal_adc.h
  • ADC_SQR1 : stm32f4xx_hal_adc.h
  • ADC_SQR1_RK : stm32f4xx_hal_adc.h
  • ADC_SQR2_RK : stm32f4xx_hal_adc.h
  • ADC_SQR3_RK : stm32f4xx_hal_adc.h
  • ADC_STAB_DELAY_US : stm32f4xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32f4xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f4xx_hal_adc.h
  • ADC_TRIPLEMODE_ALTERTRIG : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INTERL : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_AlterTrig : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_13CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_14CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_15CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_16CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_17CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_18CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_19CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_20CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32f4xx_hal_adc.h
  • APBAHBPrescTable : stm32f4xx_hal_rcc.c
  • assert_param : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BRE_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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  • Globals
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f4xx_hal_rcc.c
  • CMP_PD_BIT_NUMBER : stm32f4xx_hal.c
  • CMPCR_CMP_PD_BB : stm32f4xx_hal.c
  • CMPCR_OFFSET : stm32f4xx_hal.c
  • CR_DBP_BB : stm32f4xx_hal_pwr.h
  • CR_FPDS_BB : stm32f4xx_hal_pwr_ex.h
  • CR_LPLVDS_BB : stm32f4xx_hal_pwr_ex.h
  • CR_MRLVDS_BB : stm32f4xx_hal_pwr_ex.h
  • CR_ODEN_BB : stm32f4xx_hal_pwr_ex.h
  • CR_ODSWEN_BB : stm32f4xx_hal_pwr_ex.h
  • CR_PMODE_BB : stm32f4xx_hal_pwr.h
  • CR_PSIZE_MASK : stm32f4xx_hal_flash.h
  • CR_PVDE_BB : stm32f4xx_hal_pwr.h
  • CSR_BRE_BB : stm32f4xx_hal_pwr_ex.h
  • CSR_EWUP_BB : stm32f4xx_hal_pwr.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_ALIGN_12B_L : stm32f4xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32f4xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32f4xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32f4xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32f4xx_hal_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32f4xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32f4xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32f4xx_hal_dac.h
  • DAC_DMAConvCpltCh1() : stm32f4xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • DAC_DMAErrorCh1() : stm32f4xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • DAC_DMAHalfConvCpltCh1() : stm32f4xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • DAC_FLAG_DMAUDR1 : stm32f4xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32f4xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32f4xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32f4xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32f4xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32f4xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32f4xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32f4xx_hal_dac.h
  • DATA_CACHE_ENABLE : stm32f4xx_hal_conf.h
  • DBP_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • DMA_CalcBaseAndBitshift() : stm32f4xx_hal_dma.c
  • DMA_CHANNEL_0 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_1 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_2 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_3 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_4 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_5 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_6 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_7 : stm32f4xx_hal_dma.h
  • DMA_CIRCULAR : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32f4xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32f4xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32f4xx_hal_dma.h
  • DMA_HandleTypeDef : stm32f4xx_hal_dma.h
  • DMA_IT_DME : stm32f4xx_hal_dma.h
  • DMA_IT_FE : stm32f4xx_hal_dma.h
  • DMA_IT_HT : stm32f4xx_hal_dma.h
  • DMA_IT_TC : stm32f4xx_hal_dma.h
  • DMA_IT_TE : stm32f4xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32f4xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32f4xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32f4xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32f4xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f4xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f4xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f4xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f4xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f4xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f4xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f4xx_hal_dma.h
  • DMA_MultiBufferSetConfig() : stm32f4xx_hal_dma_ex.c
  • DMA_NORMAL : stm32f4xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32f4xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32f4xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32f4xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32f4xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f4xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f4xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f4xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f4xx_hal_dma.h
  • DMA_PFCTRL : stm32f4xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f4xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f4xx_hal_dma.h
  • DMA_SetConfig() : stm32f4xx_hal_dma.c
  • DP83848_PHY_ADDRESS : stm32f4xx_hal_conf.h
  • DUMMY_DATA : stm32f4xx_hal_usart.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • ETH_RX_BUF_SIZE : stm32f4xx_hal_conf.h
  • ETH_RXBUFNB : stm32f4xx_hal_conf.h
  • ETH_TX_BUF_SIZE : stm32f4xx_hal_conf.h
  • ETH_TXBUFNB : stm32f4xx_hal_conf.h
  • EWUP_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • EXTERNAL_CLOCK_VALUE : stm32f4xx_hal_conf.h
  • EXTI_MODE : stm32f4xx_hal_gpio.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32f4xx_hal_gpio.c
  • FLASH_BANK_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_Erase_Sector() : stm32f4xx_hal_flash_ex.h , stm32f4xx_hal_flash_ex.c
  • FLASH_FLAG_BSY : stm32f4xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32f4xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_PGPERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32f4xx_hal_flash.h
  • FLASH_FlushCaches() : stm32f4xx_hal_flash_ex.c , stm32f4xx_hal_flash_ex.h
  • FLASH_IT_EOP : stm32f4xx_hal_flash.h
  • FLASH_IT_ERR : stm32f4xx_hal_flash.h
  • FLASH_KEY1 : stm32f4xx_hal_flash.h
  • FLASH_KEY2 : stm32f4xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32f4xx_hal_flash_ex.h
  • FLASH_MassErase() : stm32f4xx_hal_flash_ex.c
  • FLASH_MER_BIT : stm32f4xx_hal_flash_ex.h
  • FLASH_OB_BOR_LevelConfig() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_DisablePCROP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_EnablePCROP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f4xx_hal_flash_ex.c
  • FLASH_OPT_KEY1 : stm32f4xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32f4xx_hal_flash.h
  • FLASH_PROC_MASSERASE : stm32f4xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f4xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32f4xx_hal_flash.h
  • FLASH_PROC_SECTERASE : stm32f4xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32f4xx_hal_flash.h
  • FLASH_Program_Byte() : stm32f4xx_hal_flash.c
  • FLASH_Program_DoubleWord() : stm32f4xx_hal_flash.c
  • FLASH_Program_HalfWord() : stm32f4xx_hal_flash.c
  • FLASH_Program_Word() : stm32f4xx_hal_flash.c
  • FLASH_PSIZE_BYTE : stm32f4xx_hal_flash.h
  • FLASH_PSIZE_DOUBLE_WORD : stm32f4xx_hal_flash.h
  • FLASH_PSIZE_HALF_WORD : stm32f4xx_hal_flash.h
  • FLASH_PSIZE_WORD : stm32f4xx_hal_flash.h
  • FLASH_SECTOR_0 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_2 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_3 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_4 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_TOTAL : stm32f4xx_hal_flash_ex.h
  • FLASH_SetErrorCode() : stm32f4xx_hal_flash.c
  • FLASH_TIMEOUT_VALUE : stm32f4xx_hal_flash.c , stm32f4xx_hal_flash_ex.c
  • FLASH_TYPEERASE_MASSERASE : stm32f4xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32f4xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_BYTE : stm32f4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f4xx_hal_flash.h
  • FLASH_VOLTAGE_RANGE_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_2 : stm32f4xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_3 : stm32f4xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_4 : stm32f4xx_hal_flash_ex.h
  • FLASH_WaitForLastOperation() : stm32f4xx_hal_flash.c , stm32f4xx_hal_flash.h , stm32f4xx_hal_flash_ex.c
  • FMPI2C_ADDRESSINGMODE_10BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_ADDRESSINGMODE_7BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_ANALOGFILTER_DISABLE : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_ANALOGFILTER_ENABLE : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_AUTOEND_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_CHECK_FLAG : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_DIRECTION_RECEIVE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_DIRECTION_TRANSMIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_Disable_IRQ() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAError() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMasterReceiveCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMasterTransmitCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMemReceiveCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMemTransmitCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMASlaveReceiveCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMASlaveTransmitCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DUALADDRESS_DISABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_DUALADDRESS_ENABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_Enable_IRQ() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_FASTMODEPLUS_SCL : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_FASTMODEPLUS_SDA : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_FIRST_AND_LAST_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FIRST_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_ADDR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_AF : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_ALERT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_ARLO : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_BERR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_BUSY : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_DIR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_MASK : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_OVR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_PECERR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_RXNE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_STOPF : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TC : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TCR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TIMEOUT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TXE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TXIS : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERALCALL_DISABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERALCALL_ENABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_START : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_START_READ : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_START_WRITE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_STOP : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_ADDR_MATCH : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_DIR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_ISR_REG : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_OWN_ADDRESS1 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_OWN_ADDRESS2 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_STOP_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IsAcknowledgeFailed() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_IT_ADDR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_ADDRI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_ERRI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_NACKI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_RX : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_RXI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_STOPI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_TCI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_TX : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_TXI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_LAST_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_Master_ISR() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_MEM_ADD_LSB : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_MEM_ADD_MSB : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_MEMADD_SIZE_16BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_MEMADD_SIZE_8BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NEXT_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NO_OPTION_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NO_STARTSTOP : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NOSTRETCH_DISABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NOSTRETCH_ENABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK01 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK02 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK03 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK04 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK05 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK06 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK07 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_NOMASK : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_RELOAD_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_RequestMemoryRead() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_RequestMemoryWrite() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_RESET_CR2 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_Slave_ISR() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_SOFTEND_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_STATE_MASTER_BUSY_RX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MASTER_BUSY_TX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MEM_BUSY_RX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MEM_BUSY_TX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MSK : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_NONE : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_SLAVE_BUSY_RX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_SLAVE_BUSY_TX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_ADDR : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_BUSY : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_DIR : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_FLAG : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_RXNE : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_STOPF : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_TC : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_TCR : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_TXIS : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TransferConfig() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnRXNEFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnSTOPFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnTXISFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
  • FPDS_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_AF0_MCO : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_TAMPER : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM11 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM9 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF4_FMPI2C1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI5 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF8_USART6 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF9_FMPI2C1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF9_I2C2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32f4xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f4xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32f4xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f4xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f4xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f4xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f4xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f4xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f4xx_hal_gpio.h
  • GPIO_NOPULL : stm32f4xx_hal_gpio.h
  • GPIO_NUMBER : stm32f4xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f4xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_All : stm32f4xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f4xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32f4xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f4xx_hal_gpio.h
  • GPIO_PinState : stm32f4xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f4xx_hal_gpio.h
  • GPIO_PULLUP : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32f4xx_hal_gpio.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f4xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32f4xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f4xx_hal_adc.c
  • HAL_ADC_ERROR_DMA : stm32f4xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32f4xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32f4xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32f4xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f4xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f4xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f4xx_hal_adc.c
  • HAL_ADC_Init() : stm32f4xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32f4xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32f4xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f4xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f4xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32f4xx_hal_adc.c
  • HAL_ADC_Start() : stm32f4xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32f4xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32f4xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f4xx_hal_adc.h
  • HAL_ADC_Stop() : stm32f4xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32f4xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32f4xx_hal_adc.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32f4xx_hal_adc_ex.c
  • HAL_CAN_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CEC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32f4xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32f4xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32f4xx_hal_crc.c
  • HAL_CRC_GetState() : stm32f4xx_hal_crc.c
  • HAL_CRC_Init() : stm32f4xx_hal_crc.c
  • HAL_CRC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32f4xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32f4xx_hal_crc.c
  • HAL_CRC_STATE_BUSY : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f4xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32f4xx_hal_crc.h
  • HAL_CRYP_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DAC_ConfigChannel() : stm32f4xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_DeInit() : stm32f4xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_ERROR_DMA : stm32f4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32f4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32f4xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32f4xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_GetError() : stm32f4xx_hal_dac.c
  • HAL_DAC_GetState() : stm32f4xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32f4xx_hal_dac.c
  • HAL_DAC_Init() : stm32f4xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32f4xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32f4xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32f4xx_hal_dac.c
  • HAL_DAC_Start() : stm32f4xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32f4xx_hal_dac.c
  • HAL_DAC_STATE_BUSY : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32f4xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32f4xx_hal_dac.h
  • HAL_DAC_Stop() : stm32f4xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32f4xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_DualGetValue() : stm32f4xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32f4xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32f4xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32f4xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f4xx_hal.c
  • HAL_DCMI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DeInit() : stm32f4xx_hal.c
  • HAL_Delay() : stm32f4xx_hal.c
  • HAL_DisableCompensationCell() : stm32f4xx_hal.c
  • HAL_DMA2D_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DMA_Abort() : stm32f4xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32f4xx_hal_dma.c
  • HAL_DMA_ERROR_DME : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f4xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32f4xx_hal_dma.h
  • HAL_DMA_GetError() : stm32f4xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f4xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32f4xx_hal_dma.h
  • HAL_DMA_Init() : stm32f4xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f4xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32f4xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32f4xx_hal_dma_ex.h
  • HAL_DMA_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32f4xx_hal_dma.c
  • HAL_DMA_Start() : stm32f4xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f4xx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM0 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM1 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM0 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM1 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM0 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM1 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f4xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32f4xx_hal_dma.h
  • HAL_DMAEx_ChangeMemory() : stm32f4xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32f4xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32f4xx_hal_dma_ex.c
  • HAL_DSI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_EnableCompensationCell() : stm32f4xx_hal.c
  • HAL_ETH_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_FLASH_EndOfOperationCallback() : stm32f4xx_hal_flash.c
  • HAL_FLASH_ERROR_NONE : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_OPERATION : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGP : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f4xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32f4xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f4xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32f4xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f4xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f4xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f4xx_hal_flash.c
  • HAL_FLASHEx_AdvOBGetConfig() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_AdvOBProgram() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_DisableFlashSleepMode() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableFlashSleepMode() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_Erase() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OB_DeSelectPCROP() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OB_SelectPCROP() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_StartFlashInterfaceClk() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_StopFlashInterfaceClk() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FMPI2C_AddrCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_DeInit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_DisableListen_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_EnableListen_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_ER_IRQHandler() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_ERROR_AF : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_ARLO : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_BERR : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_DMA : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_NONE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_OVR : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_SIZE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_TIMEOUT : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ErrorCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_EV_IRQHandler() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_GetError() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_GetMode() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_GetState() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Init() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_IsDeviceReady() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_ListenCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Abort_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Receive() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Receive_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Sequential_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Sequential_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Transmit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Transmit_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MasterRxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MasterTxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Read() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Read_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Read_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Write() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Write_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Write_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MemRxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MemTxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MODE_MASTER : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODE_MEM : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODE_NONE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODE_SLAVE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ModeTypeDef : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_FMPI2C_MspDeInit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MspInit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Receive() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Receive_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Sequential_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Sequential_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Transmit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Transmit_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_SlaveRxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_SlaveTxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_STATE_BUSY : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_RX : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_RX_LISTEN : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_TX : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_TX_LISTEN : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_ERROR : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_LISTEN : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_READY : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_RESET : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_TIMEOUT : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_StateTypeDef : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2CEx_ConfigAnalogFilter() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_ConfigDigitalFilter() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_DisableFastModePlus() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_DisableWakeUp() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_EnableFastModePlus() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_EnableWakeUp() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_GetDEVID() : stm32f4xx_hal.c
  • HAL_GetHalVersion() : stm32f4xx_hal.c
  • HAL_GetREVID() : stm32f4xx_hal.c
  • HAL_GetTick() : stm32f4xx_hal.c
  • HAL_GPIO_DeInit() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f4xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f4xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f4xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f4xx_hal_uart.c
  • HAL_HASH_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_HCD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_I2C_AddrCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f4xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f4xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f4xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f4xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32f4xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f4xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f4xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32f4xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_STATE_BUSY : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f4xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32f4xx_hal_i2c.h
  • HAL_I2S_DeInit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32f4xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32f4xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32f4xx_hal_i2s.c
  • HAL_I2S_ERROR_DMA : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_FRE : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32f4xx_hal_i2s.h
  • HAL_I2S_ErrorCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • HAL_I2S_GetState() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • HAL_I2S_Init() : stm32f4xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32f4xx_hal_i2s.c
  • HAL_I2S_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_I2S_MspDeInit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32f4xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_STATE_BUSY : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32f4xx_hal_i2s.h
  • HAL_I2S_StateTypeDef : stm32f4xx_hal_i2s.h
  • HAL_I2S_Transmit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32f4xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2SEX_ERROR_OVR : stm32f4xx_hal_i2s.h
  • HAL_I2SEX_ERROR_UDR : stm32f4xx_hal_i2s.h
  • HAL_I2SEx_TransmitReceive() : stm32f4xx_hal_i2s_ex.h
  • HAL_I2SEx_TransmitReceive_DMA() : stm32f4xx_hal_i2s_ex.h
  • HAL_I2SEx_TransmitReceive_IT() : stm32f4xx_hal_i2s_ex.h
  • HAL_IncTick() : stm32f4xx_hal.c
  • HAL_Init() : stm32f4xx_hal.c
  • HAL_InitTick() : stm32f4xx_hal.c
  • HAL_IRDA_DeInit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f4xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f4xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f4xx_hal_irda.c
  • HAL_IRDA_ERROR_DMA : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f4xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f4xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f4xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f4xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f4xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32f4xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f4xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IWDG_GetState() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_IWDG_MspInit() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_Start() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_STATE_BUSY : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_ERROR : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_READY : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_RESET : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_TIMEOUT : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_StateTypeDef : stm32f4xx_hal_iwdg.h
  • HAL_LIN_Init() : stm32f4xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f4xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LTDC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32f4xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32f4xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32f4xx_hal_cortex.h
  • HAL_MspDeInit() : stm32f4xx_hal.c
  • HAL_MspInit() : stm32f4xx_hal.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f4xx_hal_uart.c
  • HAL_MultiProcessor_ExitMuteMode() : stm32f4xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f4xx_hal_uart.c
  • HAL_NAND_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_NVIC_ClearPendingIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f4xx_hal_cortex.c
  • HAL_PCCARD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_PCD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_PWR_ConfigPVD() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f4xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_PWR_PVD_IRQHandler() : stm32f4xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32f4xx_hal_pwr.c
  • HAL_PWREx_ControlVoltageScaling() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMainRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMainRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32f4xx_hal_pwr_ex.c
  • HAL_QSPI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_RCC_ClockConfig() : stm32f4xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f4xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f4xx_hal_rcc.c , stm32f4xx_hal_rcc_ex.c
  • HAL_RCC_DisableCSS() : stm32f4xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f4xx_hal_rcc.c , stm32f4xx_hal_rcc_ex.c
  • HAL_RCC_GetPCLK1Freq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f4xx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32f4xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f4xx_hal_rcc.c , stm32f4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f4xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f4xx_hal_rcc_ex.c
  • HAL_RCCEx_SelectLSEMode() : stm32f4xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32f4xx_hal.c
  • HAL_RNG_DeInit() : stm32f4xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32f4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32f4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32f4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber() : stm32f4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber_IT() : stm32f4xx_hal_rng.c
  • HAL_RNG_GetState() : stm32f4xx_hal_rng.c
  • HAL_RNG_Init() : stm32f4xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32f4xx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32f4xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32f4xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32f4xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32f4xx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32f4xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32f4xx_hal_rng.h
  • HAL_RTC_AlarmAEventCallback() : stm32f4xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32f4xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32f4xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32f4xx_hal_rtc.c
  • HAL_RTC_Init() : stm32f4xx_hal_rtc.c
  • HAL_RTC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32f4xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32f4xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32f4xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f4xx_hal_rtc.h
  • HAL_RTC_WaitForSynchro() : stm32f4xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCoarseCalib() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCoarseCalib() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32f4xx_hal_rtc.h
  • HAL_SAI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SDRAM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SMARTCARD_DeInit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_DMA : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_ReInit() : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f4xx_hal_smartcard.c
  • HAL_SPDIFRX_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SPI_DeInit() : stm32f4xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f4xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f4xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f4xx_hal_spi.c
  • HAL_SPI_ERROR_CRC : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f4xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f4xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f4xx_hal_spi.c
  • HAL_SPI_Init() : stm32f4xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f4xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32f4xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f4xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f4xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f4xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f4xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_STATE_BUSY : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f4xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32f4xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32f4xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f4xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f4xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SRAM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SuspendTick() : stm32f4xx_hal.c
  • HAL_SYSTICK_Callback() : stm32f4xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f4xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f4xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f4xx_hal_cortex.c
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f4xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32f4xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f4xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f4xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f4xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f4xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f4xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32f4xx_hal_tim.c
  • HAL_TIMEOUT_DMA_ABORT : stm32f4xx_hal_dma.c
  • HAL_TIMEx_BreakCallback() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32f4xx_hal_tim_ex.c
  • HAL_UART_DeInit() : stm32f4xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f4xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f4xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f4xx_hal_uart.c
  • HAL_UART_ERROR_DMA : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f4xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_GetError() : stm32f4xx_hal_uart.c
  • HAL_UART_GetState() : stm32f4xx_hal_uart.c
  • HAL_UART_Init() : stm32f4xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f4xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32f4xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f4xx_hal_uart.c
  • HAL_UART_Receive() : stm32f4xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f4xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f4xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f4xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32f4xx_hal_uart.h
  • HAL_UART_Transmit() : stm32f4xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f4xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f4xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_USART_DeInit() : stm32f4xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f4xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f4xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f4xx_hal_usart.c
  • HAL_USART_ERROR_DMA : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f4xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_GetError() : stm32f4xx_hal_usart.c
  • HAL_USART_GetState() : stm32f4xx_hal_usart.c
  • HAL_USART_Init() : stm32f4xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f4xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32f4xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f4xx_hal_usart.c
  • HAL_USART_Receive() : stm32f4xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f4xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f4xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f4xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32f4xx_hal_usart.h
  • HAL_USART_Transmit() : stm32f4xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f4xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f4xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f4xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f4xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f4xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_WWDG_DeInit() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_GetState() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_WWDG_MspDeInit() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Start() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Start_IT() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_STATE_BUSY : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_ERROR : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_READY : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_RESET : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_TIMEOUT : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_StateTypeDef : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_WakeupCallback() : stm32f4xx_hal_wwdg.h , stm32f4xx_hal_wwdg.c
  • HSE_STARTUP_TIMEOUT : stm32f4xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • HSE_VALUE : stm32f4xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • HSI_VALUE : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_10BIT_ADDRESS : stm32f4xx_hal_i2c.h
  • I2C_10BIT_HEADER_READ : stm32f4xx_hal_i2c.h
  • I2C_10BIT_HEADER_WRITE : stm32f4xx_hal_i2c.h
  • I2C_7BIT_ADD_READ : stm32f4xx_hal_i2c.h
  • I2C_7BIT_ADD_WRITE : stm32f4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_10BIT : stm32f4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f4xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32f4xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32f4xx_hal_i2c.h
  • I2C_DMAError() : stm32f4xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMAMemReceiveCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMAMemTransmitCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32f4xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32f4xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f4xx_hal_i2c.h
  • I2C_DUTYCYCLE_16_9 : stm32f4xx_hal_i2c.h
  • I2C_DUTYCYCLE_2 : stm32f4xx_hal_i2c.h
  • I2C_FIRST_AND_LAST_FRAME : stm32f4xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32f4xx_hal_i2c.h
  • I2C_FLAG_ADD10 : stm32f4xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f4xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_BTF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f4xx_hal_i2c.h
  • I2C_FLAG_DUALF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_GENCALL : stm32f4xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32f4xx_hal_i2c.h
  • I2C_FLAG_MSL : stm32f4xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SB : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SMBALERT : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SMBHOST : stm32f4xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f4xx_hal_i2c.h
  • I2C_FLAG_TRA : stm32f4xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f4xx_hal_i2c.h
  • I2C_FREQRANGE : stm32f4xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32f4xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f4xx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32f4xx_hal_i2c.c
  • I2C_IT_BUF : stm32f4xx_hal_i2c.h
  • I2C_IT_ERR : stm32f4xx_hal_i2c.h
  • I2C_IT_EVT : stm32f4xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32f4xx_hal_i2c.h
  • I2C_MasterReceive_BTF() : stm32f4xx_hal_i2c.c
  • I2C_MasterReceive_RXNE() : stm32f4xx_hal_i2c.c
  • I2C_MasterRequestRead() : stm32f4xx_hal_i2c.c
  • I2C_MasterRequestWrite() : stm32f4xx_hal_i2c.c
  • I2C_MasterTransmit_BTF() : stm32f4xx_hal_i2c.c
  • I2C_MasterTransmit_TXE() : stm32f4xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32f4xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f4xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32f4xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32f4xx_hal_i2c.c
  • I2C_NOSTRETCH_DISABLE : stm32f4xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f4xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32f4xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f4xx_hal_i2c.c
  • I2C_RISE_TIME : stm32f4xx_hal_i2c.h
  • I2C_Slave_ADDR() : stm32f4xx_hal_i2c.c
  • I2C_Slave_AF() : stm32f4xx_hal_i2c.c
  • I2C_Slave_STOPF() : stm32f4xx_hal_i2c.c
  • I2C_SlaveReceive_BTF() : stm32f4xx_hal_i2c.c
  • I2C_SlaveReceive_RXNE() : stm32f4xx_hal_i2c.c
  • I2C_SlaveTransmit_BTF() : stm32f4xx_hal_i2c.c
  • I2C_SlaveTransmit_TXE() : stm32f4xx_hal_i2c.c
  • I2C_SPEED : stm32f4xx_hal_i2c.h
  • I2C_SPEED_FAST : stm32f4xx_hal_i2c.h
  • I2C_SPEED_STANDARD : stm32f4xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32f4xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32f4xx_hal_i2c.c
  • I2C_STATE_MSK : stm32f4xx_hal_i2c.c
  • I2C_STATE_NONE : stm32f4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32f4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32f4xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR_SLAVE : stm32f4xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY_FLAG : stm32f4xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f4xx_hal_i2c.c
  • I2C_WaitOnBTFFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnMasterAddressFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnTXEFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32f4xx_hal_i2s.h
  • I2S_CLOCK_EXTERNAL : stm32f4xx_hal_i2s_ex.h
  • I2S_CLOCK_PLLR : stm32f4xx_hal_i2s_ex.h
  • I2S_CLOCK_PLLSRC : stm32f4xx_hal_i2s_ex.h
  • I2S_CPOL_HIGH : stm32f4xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32f4xx_hal_i2s.h
  • I2S_DMAError() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_DMARxCplt() : stm32f4xx_hal_i2s.h , stm32f4xx_hal_i2s_ex.c
  • I2S_DMARxHalfCplt() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_DMATxCplt() : stm32f4xx_hal_i2s.h , stm32f4xx_hal_i2s_ex.c
  • I2S_DMATxHalfCplt() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_FLAG_BSY : stm32f4xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32f4xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32f4xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_DISABLE : stm32f4xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_ENABLE : stm32f4xx_hal_i2s.h
  • I2S_GetInputClock() : stm32f4xx_hal_i2s_ex.c , stm32f4xx_hal_i2s_ex.h
  • I2S_IT_ERR : stm32f4xx_hal_i2s.h
  • I2S_IT_RXNE : stm32f4xx_hal_i2s.h
  • I2S_IT_TXE : stm32f4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32f4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32f4xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32f4xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32f4xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32f4xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32f4xx_hal_i2s.h
  • I2S_Receive_IT() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32f4xx_hal_i2s.h
  • I2S_Transmit_IT() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_WaitFlagStateUntilTimeout() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2SEx_TransmitReceive_IT() : stm32f4xx_hal_i2s_ex.h
  • I2SxEXT : stm32f4xx_hal_i2s_ex.h
  • IDCODE_DEVID_MASK : stm32f4xx_hal.c
  • INSTRUCTION_CACHE_ENABLE : stm32f4xx_hal_conf.h
  • IRDA_BRR : stm32f4xx_hal_irda.h
  • IRDA_CR1_REG_INDEX : stm32f4xx_hal_irda.h
  • IRDA_CR2_REG_INDEX : stm32f4xx_hal_irda.h
  • IRDA_CR3_REG_INDEX : stm32f4xx_hal_irda.h
  • IRDA_DIV : stm32f4xx_hal_irda.h
  • IRDA_DIVFRAQ : stm32f4xx_hal_irda.h
  • IRDA_DIVMANT : stm32f4xx_hal_irda.h
  • IRDA_DMAError() : stm32f4xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f4xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f4xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f4xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f4xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f4xx_hal_irda.c
  • IRDA_FLAG_FE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_IDLE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f4xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f4xx_hal_irda.h
  • IRDA_IT_CTS : stm32f4xx_hal_irda.h
  • IRDA_IT_ERR : stm32f4xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f4xx_hal_irda.h
  • IRDA_IT_LBD : stm32f4xx_hal_irda.h
  • IRDA_IT_MASK : stm32f4xx_hal_irda.h
  • IRDA_IT_PE : stm32f4xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f4xx_hal_irda.h
  • IRDA_IT_TC : stm32f4xx_hal_irda.h
  • IRDA_IT_TXE : stm32f4xx_hal_irda.h
  • IRDA_MODE_RX : stm32f4xx_hal_irda.h
  • IRDA_MODE_TX : stm32f4xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f4xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f4xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f4xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f4xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f4xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f4xx_hal_irda.h
  • IRDA_Receive_IT() : stm32f4xx_hal_irda.c
  • IRDA_SetConfig() : stm32f4xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32f4xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32f4xx_hal_irda.c
  • IRDA_WORDLENGTH_8B : stm32f4xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32f4xx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG : stm32f4xx_hal_adc.h
  • IS_ADC_CHANNEL : stm32f4xx_hal_adc_ex.h
  • IS_ADC_CHANNELS_TYPE : stm32f4xx_hal_adc.h
  • IS_ADC_CLOCKPRESCALER : stm32f4xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32f4xx_hal_adc.h
  • IS_ADC_DMA_ACCESS_MODE : stm32f4xx_hal_adc_ex.h
  • IS_ADC_EOCSelection : stm32f4xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32f4xx_hal_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32f4xx_hal_adc_ex.h
  • IS_ADC_EXT_INJEC_TRIG_EDGE : stm32f4xx_hal_adc_ex.h
  • IS_ADC_EXT_TRIG : stm32f4xx_hal_adc.h
  • IS_ADC_EXT_TRIG_EDGE : stm32f4xx_hal_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32f4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f4xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32f4xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f4xx_hal_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32f4xx_hal_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32f4xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32f4xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32f4xx_hal_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f4xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32f4xx_hal_adc.h
  • IS_ADC_THRESHOLD : stm32f4xx_hal_adc.h
  • IS_DAC_ALIGN : stm32f4xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32f4xx_hal_dac.h
  • IS_DAC_DATA : stm32f4xx_hal_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f4xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f4xx_hal_dac.h
  • IS_DAC_TRIGGER : stm32f4xx_hal_dac.h
  • IS_DMA_BUFFER_SIZE : stm32f4xx_hal_dma.h
  • IS_DMA_CHANNEL : stm32f4xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f4xx_hal_dma.h
  • IS_DMA_FIFO_MODE_STATE : stm32f4xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32f4xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32f4xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f4xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f4xx_hal_dma.h
  • IS_DMA_MODE : stm32f4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32f4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f4xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f4xx_hal_dma.h
  • IS_FLASH_ADDRESS : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_BANK : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_LATENCY : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_NBSECTORS : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_SECTOR : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f4xx_hal_flash.h
  • IS_FMPI2C_ADDRESSING_MODE : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_ANALOG_FILTER : stm32f4xx_hal_fmpi2c_ex.h
  • IS_FMPI2C_DIGITAL_FILTER : stm32f4xx_hal_fmpi2c_ex.h
  • IS_FMPI2C_DUAL_ADDRESS : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_FASTMODEPLUS : stm32f4xx_hal_fmpi2c_ex.h
  • IS_FMPI2C_GENERAL_CALL : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_MEMADD_SIZE : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_NO_STRETCH : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_OWN_ADDRESS1 : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_OWN_ADDRESS2 : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_OWN_ADDRESS2_MASK : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_TRANSFER_OPTIONS_REQUEST : stm32f4xx_hal_fmpi2c.h
  • IS_GPIO_AF : stm32f4xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32f4xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f4xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f4xx_hal_gpio.h
  • IS_GPIO_PULL : stm32f4xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f4xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32f4xx_hal_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32f4xx_hal_i2c.h
  • IS_I2C_DUAL_ADDRESS : stm32f4xx_hal_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32f4xx_hal_i2c.h
  • IS_I2C_GENERAL_CALL : stm32f4xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f4xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32f4xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f4xx_hal_i2s.h
  • IS_I2S_CLOCKSOURCE : stm32f4xx_hal_i2s_ex.h
  • IS_I2S_CPOL : stm32f4xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32f4xx_hal_i2s.h
  • IS_I2S_FULLDUPLEX_MODE : stm32f4xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32f4xx_hal_i2s.h
  • IS_I2S_MODE : stm32f4xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32f4xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32f4xx_hal_irda.h
  • IS_IRDA_MODE : stm32f4xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f4xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f4xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f4xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32f4xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f4xx_hal_iwdg.h
  • IS_LPTIM_AUTORELOAD : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32f4xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32f4xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32f4xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32f4xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32f4xx_hal_lptim.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32f4xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32f4xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32f4xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f4xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f4xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f4xx_hal_cortex.h
  • IS_OB_BOR_LEVEL : stm32f4xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f4xx_hal_flash_ex.h
  • IS_OB_PCROP : stm32f4xx_hal_flash_ex.h
  • IS_OB_PCROP_SELECT : stm32f4xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f4xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f4xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f4xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32f4xx_hal_flash_ex.h
  • IS_OBEX : stm32f4xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f4xx_hal_flash_ex.h
  • IS_PCROPSTATE : stm32f4xx_hal_flash_ex.h
  • IS_PWR_PVD_LEVEL : stm32f4xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32f4xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32f4xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32f4xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f4xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32f4xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32f4xx_hal_pwr_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_CLOCKTYPE : stm32f4xx_hal_rcc.h
  • IS_RCC_FMPI2C1CLKSOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32f4xx_hal_rcc.h
  • IS_RCC_HSE : stm32f4xx_hal_rcc.h
  • IS_RCC_HSI : stm32f4xx_hal_rcc.h
  • IS_RCC_I2SAPBCLKSOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLKSOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32f4xx_hal_rcc.h
  • IS_RCC_LSE_MODE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_LSI : stm32f4xx_hal_rcc.h
  • IS_RCC_MCO : stm32f4xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f4xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_MCODIV : stm32f4xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32f4xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f4xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLI2SN_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SR_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLM_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLP_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32f4xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32f4xx_hal_rcc.h
  • IS_RNG_FLAG : stm32f4xx_hal_rng.h
  • IS_RNG_IT : stm32f4xx_hal_rng.h
  • IS_RTC_ALARM : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32f4xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f4xx_hal_rtc.h
  • IS_RTC_BKP : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_SIGN : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_VALUE : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32f4xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32f4xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f4xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32f4xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f4xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32f4xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32f4xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f4xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f4xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32f4xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32f4xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32f4xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f4xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32f4xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32f4xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PIN : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32f4xx_hal_rtc.h
  • IS_RTC_YEAR : stm32f4xx_hal_rtc.h
  • IS_SMARTCARD_BAUDRATE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_NACK_STATE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f4xx_hal_smartcard.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f4xx_hal_spi.h
  • IS_SPI_CPHA : stm32f4xx_hal_spi.h
  • IS_SPI_CPOL : stm32f4xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f4xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f4xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f4xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f4xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f4xx_hal_spi.h
  • IS_SPI_MODE : stm32f4xx_hal_spi.h
  • IS_SPI_NSS : stm32f4xx_hal_spi.h
  • IS_SPI_TIMODE : stm32f4xx_hal_spi.h
  • IS_SYSTICK_CLK_SOURCE : stm32f4xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f4xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f4xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f4xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f4xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32f4xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f4xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f4xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f4xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_REMAP : stm32f4xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_SYSTEMBREAKINPUT : stm32f4xx_hal_tim_ex.h
  • IS_TIM_TI1SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f4xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32f4xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32f4xx_hal_fmpi2c.h
  • IS_TRANSFER_REQUEST : stm32f4xx_hal_fmpi2c.h
  • IS_UART_ADDRESS : stm32f4xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f4xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f4xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f4xx_hal_uart.h
  • IS_UART_LIN_OVERSAMPLING : stm32f4xx_hal_uart.h
  • IS_UART_LIN_WORD_LENGTH : stm32f4xx_hal_uart.h
  • IS_UART_MODE : stm32f4xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32f4xx_hal_uart.h
  • IS_UART_PARITY : stm32f4xx_hal_uart.h
  • IS_UART_STATE : stm32f4xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f4xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f4xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f4xx_hal_uart.h
  • IS_USART_BAUDRATE : stm32f4xx_hal_usart.h
  • IS_USART_CLOCK : stm32f4xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f4xx_hal_usart.h
  • IS_USART_MODE : stm32f4xx_hal_usart.h
  • IS_USART_NACK_STATE : stm32f4xx_hal_usart.h
  • IS_USART_PARITY : stm32f4xx_hal_usart.h
  • IS_USART_PHASE : stm32f4xx_hal_usart.h
  • IS_USART_POLARITY : stm32f4xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f4xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f4xx_hal_usart.h
  • IS_VOLTAGERANGE : stm32f4xx_hal_flash_ex.h
  • IS_WRPSTATE : stm32f4xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f4xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f4xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f4xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f4xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f4xx_hal_iwdg.h
  • IWDG_FLAG_PVU : stm32f4xx_hal_iwdg.h
  • IWDG_FLAG_RVU : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f4xx_hal_iwdg.h
  • IWDG_TIMEOUT_FLAG : stm32f4xx_hal_iwdg.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • s
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LPLVDS_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32f4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32f4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32f4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32f4xx_hal_lptim.h
  • LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32f4xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32f4xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32f4xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32f4xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32f4xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32f4xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32f4xx_hal_lptim.h
  • LPTIM_IT_UP : stm32f4xx_hal_lptim.h
  • LPTIM_OP_PAD_AF : stm32f4xx_hal_lptim.h
  • LPTIM_OP_PAD_PA4 : stm32f4xx_hal_lptim.h
  • LPTIM_OP_PAD_PB9 : stm32f4xx_hal_lptim.h
  • LPTIM_OP_TIM_DAC : stm32f4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32f4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32f4xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32f4xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32f4xx_hal_lptim.h
  • LSE_STARTUP_TIMEOUT : stm32f4xx_hal_conf.h
  • LSE_VALUE : stm32f4xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • LSI_VALUE : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
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  • i
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAC_ADDR0 : stm32f4xx_hal_conf.h
  • MAC_ADDR1 : stm32f4xx_hal_conf.h
  • MAC_ADDR2 : stm32f4xx_hal_conf.h
  • MAC_ADDR3 : stm32f4xx_hal_conf.h
  • MAC_ADDR4 : stm32f4xx_hal_conf.h
  • MAC_ADDR5 : stm32f4xx_hal_conf.h
  • MAX_NBYTE_SIZE : stm32f4xx_hal_fmpi2c.c
  • MCO1_GPIO_PORT : stm32f4xx_hal_rcc.c
  • MCO1_PIN : stm32f4xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32f4xx_hal_rcc.c
  • MCO2_PIN : stm32f4xx_hal_rcc.c
  • MEMORY0 : stm32f4xx_hal_dma_ex.h
  • MEMORY1 : stm32f4xx_hal_dma_ex.h
  • MEMRMP_OFFSET : stm32f4xx_hal.c
  • MPU_ACCESS_BUFFERABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32f4xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32f4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32f4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32f4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32f4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32f4xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32f4xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32f4xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32f4xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32f4xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32f4xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32f4xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32f4xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32f4xx_hal_cortex.h
  • MRLVDS_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • f
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NVIC_PRIORITYGROUP_0 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f4xx_hal_cortex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
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  • d
  • e
  • f
  • g
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BOR_LEVEL1 : stm32f4xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32f4xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32f4xx_hal_flash_ex.h
  • OB_BOR_OFF : stm32f4xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f4xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_DESELECTED : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_0 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_1 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_2 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_3 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_4 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_All : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SELECTED : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_STATE_DISABLE : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_STATE_ENABLE : stm32f4xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f4xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f4xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32f4xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f4xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f4xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f4xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_1 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_2 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_3 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_All : stm32f4xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f4xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f4xx_hal_flash_ex.h
  • ODEN_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
  • ODSWEN_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
  • OPTCR_BYTE0_ADDRESS : stm32f4xx_hal_flash.h
  • OPTCR_BYTE1_ADDRESS : stm32f4xx_hal_flash.h
  • OPTCR_BYTE2_ADDRESS : stm32f4xx_hal_flash.h
  • OPTCR_BYTE3_ADDRESS : stm32f4xx_hal_flash.h
  • OPTIONBYTE_BOR : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_PCROP : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f4xx_hal_flash_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • pFlash : stm32f4xx_hal_flash.c , stm32f4xx_hal_flash_ex.c
  • PHY_AUTONEGO_COMPLETE : stm32f4xx_hal_conf.h
  • PHY_AUTONEGOTIATION : stm32f4xx_hal_conf.h
  • PHY_BCR : stm32f4xx_hal_conf.h
  • PHY_BSR : stm32f4xx_hal_conf.h
  • PHY_CONFIG_DELAY : stm32f4xx_hal_conf.h
  • PHY_DUPLEX_STATUS : stm32f4xx_hal_conf.h
  • PHY_FULLDUPLEX_100M : stm32f4xx_hal_conf.h
  • PHY_FULLDUPLEX_10M : stm32f4xx_hal_conf.h
  • PHY_HALFDUPLEX_100M : stm32f4xx_hal_conf.h
  • PHY_HALFDUPLEX_10M : stm32f4xx_hal_conf.h
  • PHY_ISOLATE : stm32f4xx_hal_conf.h
  • PHY_JABBER_DETECTION : stm32f4xx_hal_conf.h
  • PHY_LINK_INTERRUPT : stm32f4xx_hal_conf.h
  • PHY_LINK_STATUS : stm32f4xx_hal_conf.h
  • PHY_LINKED_STATUS : stm32f4xx_hal_conf.h
  • PHY_LOOPBACK : stm32f4xx_hal_conf.h
  • PHY_MICR : stm32f4xx_hal_conf.h
  • PHY_MICR_INT_EN : stm32f4xx_hal_conf.h
  • PHY_MICR_INT_OE : stm32f4xx_hal_conf.h
  • PHY_MISR : stm32f4xx_hal_conf.h
  • PHY_MISR_LINK_INT_EN : stm32f4xx_hal_conf.h
  • PHY_POWERDOWN : stm32f4xx_hal_conf.h
  • PHY_READ_TO : stm32f4xx_hal_conf.h
  • PHY_RESET : stm32f4xx_hal_conf.h
  • PHY_RESET_DELAY : stm32f4xx_hal_conf.h
  • PHY_RESTART_AUTONEGOTIATION : stm32f4xx_hal_conf.h
  • PHY_SPEED_STATUS : stm32f4xx_hal_conf.h
  • PHY_SR : stm32f4xx_hal_conf.h
  • PHY_WRITE_TO : stm32f4xx_hal_conf.h
  • PLL_TIMEOUT_VALUE : stm32f4xx_hal_rcc_ex.h
  • PMODE_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • PREFETCH_ENABLE : stm32f4xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f4xx_hal_pwr.c
  • PVD_MODE_EVT : stm32f4xx_hal_pwr.c
  • PVD_MODE_IT : stm32f4xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32f4xx_hal_pwr.c
  • PVDE_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • PWR_BKPREG_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_CR_OFFSET : stm32f4xx_hal_pwr.h
  • PWR_CR_OFFSET_BB : stm32f4xx_hal_pwr.h
  • PWR_CSR_OFFSET : stm32f4xx_hal_pwr.h
  • PWR_CSR_OFFSET_BB : stm32f4xx_hal_pwr.h
  • PWR_EXTI_LINE_PVD : stm32f4xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32f4xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32f4xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f4xx_hal_pwr.h
  • PWR_FLAG_VOSRDY : stm32f4xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f4xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f4xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32f4xx_hal_pwr.h
  • PWR_OFFSET : stm32f4xx_hal_pwr.h
  • PWR_OVERDRIVE_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32f4xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32f4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32f4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32f4xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32f4xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f4xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f4xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f4xx_hal_pwr.h
  • PWR_UDERDRIVE_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_VOSRDY_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_WAKEUP_PIN1 : stm32f4xx_hal_pwr.h
  • PWR_WAKEUP_PIN2 : stm32f4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_BDCR_BDRST_BB : stm32f4xx_hal_rcc.h
  • RCC_BDCR_BYTE0_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_BDCR_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_BDCR_RTCEN_BB : stm32f4xx_hal_rcc.h
  • RCC_BDRST_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_CFGR_MCO1EN_BB : stm32f4xx_hal_rcc_ex.h
  • RCC_CFGR_MCO2EN_BB : stm32f4xx_hal_rcc_ex.h
  • RCC_CFGR_OFFSET : stm32f4xx_hal_rcc_ex.h
  • RCC_CIR_BYTE1_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f4xx_hal_rcc.h
  • RCC_CR_BYTE2_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_CR_CSSON_BB : stm32f4xx_hal_rcc.h
  • RCC_CR_HSION_BB : stm32f4xx_hal_rcc.h
  • RCC_CR_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_CR_PLLON_BB : stm32f4xx_hal_rcc.h
  • RCC_CSR_LSION_BB : stm32f4xx_hal_rcc.h
  • RCC_CSR_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_CSSON_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • RCC_DCKCFGR_OFFSET : stm32f4xx_hal_rcc_ex.h
  • RCC_DCKCFGR_TIMPRE_BB : stm32f4xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PLLI2SRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f4xx_hal_rcc.h
  • RCC_FMPI2C1CLKSOURCE_APB : stm32f4xx_hal_rcc_ex.h
  • RCC_FMPI2C1CLKSOURCE_HSI : stm32f4xx_hal_rcc_ex.h
  • RCC_FMPI2C1CLKSOURCE_SYSCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_HCLK_DIV1 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f4xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f4xx_hal_rcc.h
  • RCC_HSE_ON : stm32f4xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f4xx_hal_rcc.h
  • RCC_HSI_ON : stm32f4xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32f4xx_hal_rcc.h
  • RCC_HSION_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_I2SAPBCLKSOURCE_EXT : stm32f4xx_hal_rcc_ex.h
  • RCC_I2SAPBCLKSOURCE_PLLR : stm32f4xx_hal_rcc_ex.h
  • RCC_I2SAPBCLKSOURCE_PLLSRC : stm32f4xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32f4xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f4xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f4xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f4xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f4xx_hal_rcc.h
  • RCC_IT_PLLI2SRDY : stm32f4xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f4xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32f4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32f4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32f4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32f4xx_hal_rcc.h
  • RCC_LSE_HIGHDRIVE_MODE : stm32f4xx_hal_rcc_ex.h
  • RCC_LSE_LOWPOWER_MODE : stm32f4xx_hal_rcc_ex.h
  • RCC_LSE_OFF : stm32f4xx_hal_rcc.h
  • RCC_LSE_ON : stm32f4xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f4xx_hal_rcc.h
  • RCC_LSI_ON : stm32f4xx_hal_rcc.h
  • RCC_LSION_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_MCO1 : stm32f4xx_hal_rcc.h
  • RCC_MCO1EN_BIT_NUMBER : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_HSE : stm32f4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32f4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32f4xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32f4xx_hal_rcc.h
  • RCC_MCO2 : stm32f4xx_hal_rcc.h
  • RCC_MCO2EN_BIT_NUMBER : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_HSE : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_I2SCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_PLLCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_SYSCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_MCODIV_1 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32f4xx_hal_rcc.h
  • RCC_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f4xx_hal_rcc.h
  • RCC_PERIPHCLK_FMPI2C1 : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32f4xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32f4xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f4xx_hal_rcc.h
  • RCC_PLL_ON : stm32f4xx_hal_rcc.h
  • RCC_PLLON_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32f4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f4xx_hal_rcc.h
  • RCC_RTCEN_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLRCLK : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLRCLK : stm32f4xx_hal_rcc.h
  • RCC_TIMPRE_BIT_NUMBER : stm32f4xx_hal_rcc_ex.h
  • RCC_TIMPRES_ACTIVATED : stm32f4xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32f4xx_hal_rcc_ex.h
  • RDP_KEY : stm32f4xx_hal_flash.h
  • RISING_EDGE : stm32f4xx_hal_gpio.c
  • RNG_FLAG_CECS : stm32f4xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32f4xx_hal_rng.h
  • RNG_FLAG_SECS : stm32f4xx_hal_rng.h
  • RNG_IT_CEI : stm32f4xx_hal_rng.h
  • RNG_IT_DRDY : stm32f4xx_hal_rng.h
  • RNG_IT_SEI : stm32f4xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32f4xx_hal_rng.c
  • RTC_ALARM_A : stm32f4xx_hal_rtc.h
  • RTC_ALARM_B : stm32f4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32f4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32f4xx_hal_rtc.h
  • RTC_Bcd2ToByte() : stm32f4xx_hal_rtc.c , stm32f4xx_hal_rtc.h
  • RTC_BKP_DR0 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f4xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32f4xx_hal_rtc.c , stm32f4xx_hal_rtc.h
  • RTC_CALIBOUTPUT_1HZ : stm32f4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32f4xx_hal_rtc_ex.h
  • RTC_CALIBSIGN_NEGATIVE : stm32f4xx_hal_rtc_ex.h
  • RTC_CALIBSIGN_POSITIVE : stm32f4xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32f4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32f4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32f4xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32f4xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32f4xx_hal_rtc.h , stm32f4xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f4xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32f4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f4xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32f4xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32f4xx_hal_rtc.h
  • RTC_FLAGS_MASK : stm32f4xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f4xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32f4xx_hal_rtc.h
  • RTC_INIT_MASK : stm32f4xx_hal_rtc.h
  • RTC_IT_ALRA : stm32f4xx_hal_rtc.h
  • RTC_IT_ALRB : stm32f4xx_hal_rtc.h
  • RTC_IT_TAMP : stm32f4xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f4xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32f4xx_hal_rtc.h
  • RTC_IT_TS : stm32f4xx_hal_rtc.h
  • RTC_IT_WUT : stm32f4xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f4xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f4xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f4xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f4xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f4xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f4xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f4xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_ALARMA : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32f4xx_hal_rtc.h
  • RTC_RSF_MASK : stm32f4xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32f4xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32f4xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32f4xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32f4xx_hal_rtc.h
  • RTC_TAMPER_1 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPIN_DEFAULT : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPIN_POS1 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f4xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_POS1 : stm32f4xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32f4xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32f4xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f4xx_hal_rtc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SlaveAddr_MSK : stm32f4xx_hal_fmpi2c.c
  • SlaveAddr_SHIFT : stm32f4xx_hal_fmpi2c.c
  • SMARTCARD_BRR : stm32f4xx_hal_smartcard.h
  • SMARTCARD_CR1_REG_INDEX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_CR3_REG_INDEX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DIV : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DIVFRAQ : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DIVMANT : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DMAError() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_DMAREQ_RX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_TX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DMATransmitCplt() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_FLAG_FE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV10 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV12 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV14 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV16 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV18 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV2 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV20 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV22 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV24 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV26 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV28 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV30 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV32 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV34 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV36 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV38 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV4 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV40 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV42 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV44 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV46 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV48 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV50 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV52 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV54 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV56 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV58 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV6 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV60 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV62 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV8 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_Receive_IT() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_Transmit_IT() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32f4xx_hal_smartcard.h
  • SPI_1LINE_RX : stm32f4xx_hal_spi.h
  • SPI_1LINE_TX : stm32f4xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f4xx_hal_spi.h
  • SPI_CheckFlag_BSY() : stm32f4xx_hal_spi.c
  • SPI_CheckForDisablingSPI() : stm32f4xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32f4xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f4xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f4xx_hal_spi.c
  • SPI_CRCCALCULATION_DISABLE : stm32f4xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f4xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f4xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f4xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f4xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f4xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f4xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f4xx_hal_spi.h
  • SPI_DMAError() : stm32f4xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f4xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f4xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_FIRSTBIT_LSB : stm32f4xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f4xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f4xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f4xx_hal_spi.h
  • SPI_FLAG_FRE : stm32f4xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f4xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f4xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f4xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f4xx_hal_spi.h
  • SPI_HandleTypeDef : stm32f4xx_hal_spi.h
  • SPI_IT_ERR : stm32f4xx_hal_spi.h
  • SPI_IT_RXNE : stm32f4xx_hal_spi.h
  • SPI_IT_TXE : stm32f4xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f4xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f4xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f4xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f4xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f4xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f4xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f4xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f4xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f4xx_hal_spi.h
  • SPI_RESET_CRC : stm32f4xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32f4xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32f4xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32f4xx_hal_spi.c
  • SYSCFG_OFFSET : stm32f4xx_hal.c
  • SYSTICK_CLKSOURCE_HCLK : stm32f4xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f4xx_hal_cortex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
  • _
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TICK_INT_PRIORITY : stm32f4xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f4xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f4xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32f4xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f4xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f4xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f4xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32f4xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f4xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f4xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f4xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32f4xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f4xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32f4xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f4xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f4xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f4xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f4xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f4xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f4xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f4xx_hal_tim.h
  • TIM_DMA_COM : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f4xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f4xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32f4xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_OR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32f4xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_SR : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_DMADelayPulseCplt() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_DMAError() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_DMAPeriodElapsedCplt() : stm32f4xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f4xx_hal_tim.c
  • TIM_ENCODERMODE_TI1 : stm32f4xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f4xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f4xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_ETRPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32f4xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_COM : stm32f4xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f4xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f4xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f4xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f4xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_IT_BREAK : stm32f4xx_hal_tim.h
  • TIM_IT_CC1 : stm32f4xx_hal_tim.h
  • TIM_IT_CC2 : stm32f4xx_hal_tim.h
  • TIM_IT_CC3 : stm32f4xx_hal_tim.h
  • TIM_IT_CC4 : stm32f4xx_hal_tim.h
  • TIM_IT_COM : stm32f4xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f4xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32f4xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f4xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f4xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f4xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32f4xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f4xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f4xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f4xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32f4xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32f4xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32f4xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32f4xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32f4xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f4xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f4xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f4xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f4xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f4xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f4xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f4xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f4xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f4xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f4xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f4xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f4xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f4xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f4xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_SYSTEMBREAKINPUT_HARDFAULT : stm32f4xx_hal_tim_ex.h
  • TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD : stm32f4xx_hal_tim_ex.h
  • TIM_SYSTEMBREAKINPUT_PVD : stm32f4xx_hal_tim_ex.h
  • TIM_TI1_ConfigInputStage() : stm32f4xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f4xx_hal_tim.h , stm32f4xx_hal_tim.c
  • TIM_TI1SELECTION_CH1 : stm32f4xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f4xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32f4xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_TIM11_GPIO : stm32f4xx_hal_tim_ex.h
  • TIM_TIM11_HSE : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_ETH_PTP : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_TIM8_TRGO : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_USBFS_SOF : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_USBHS_SOF : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_GPIO : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_LSE : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_LSI : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_RTC : stm32f4xx_hal_tim_ex.h
  • TIM_TRGO_ENABLE : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f4xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_TS_ETRF : stm32f4xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f4xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f4xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f4xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f4xx_hal_tim.h
  • TIM_TS_NONE : stm32f4xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f4xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f4xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f4xx_hal_tim.h
  • TIMEx_DMACommutationCplt() : stm32f4xx_hal_tim_ex.c , stm32f4xx_hal_tim_ex.h
  • TIMING_CLEAR_MASK : stm32f4xx_hal_fmpi2c.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_BRR_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_BRR_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_CR1_REG_INDEX : stm32f4xx_hal_uart.h
  • UART_CR2_REG_INDEX : stm32f4xx_hal_uart.h
  • UART_CR3_REG_INDEX : stm32f4xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_DIVMANT_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_DIVMANT_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_DMAError() : stm32f4xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f4xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f4xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f4xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f4xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f4xx_hal_uart.c
  • UART_FLAG_CTS : stm32f4xx_hal_uart.h
  • UART_FLAG_FE : stm32f4xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f4xx_hal_uart.h
  • UART_FLAG_LBD : stm32f4xx_hal_uart.h
  • UART_FLAG_NE : stm32f4xx_hal_uart.h
  • UART_FLAG_ORE : stm32f4xx_hal_uart.h
  • UART_FLAG_PE : stm32f4xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f4xx_hal_uart.h
  • UART_FLAG_TC : stm32f4xx_hal_uart.h
  • UART_FLAG_TXE : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f4xx_hal_uart.h
  • UART_IT_CTS : stm32f4xx_hal_uart.h
  • UART_IT_ERR : stm32f4xx_hal_uart.h
  • UART_IT_IDLE : stm32f4xx_hal_uart.h
  • UART_IT_LBD : stm32f4xx_hal_uart.h
  • UART_IT_MASK : stm32f4xx_hal_uart.h
  • UART_IT_PE : stm32f4xx_hal_uart.h
  • UART_IT_RXNE : stm32f4xx_hal_uart.h
  • UART_IT_TC : stm32f4xx_hal_uart.h
  • UART_IT_TXE : stm32f4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f4xx_hal_uart.h
  • UART_MODE_RX : stm32f4xx_hal_uart.h
  • UART_MODE_TX : stm32f4xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f4xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f4xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32f4xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f4xx_hal_uart.h
  • UART_PARITY_NONE : stm32f4xx_hal_uart.h
  • UART_PARITY_ODD : stm32f4xx_hal_uart.h
  • UART_Receive_IT() : stm32f4xx_hal_uart.c
  • UART_SetConfig() : stm32f4xx_hal_uart.c
  • UART_STATE_DISABLE : stm32f4xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f4xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f4xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f4xx_hal_uart.h
  • UART_Transmit_IT() : stm32f4xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32f4xx_hal_uart.c
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f4xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f4xx_hal_uart.h
  • UART_WORDLENGTH_8B : stm32f4xx_hal_uart.h
  • UART_WORDLENGTH_9B : stm32f4xx_hal_uart.h
  • UFB_MODE_BB : stm32f4xx_hal.c
  • UFB_MODE_BIT_NUMBER : stm32f4xx_hal.c
  • USART_BRR : stm32f4xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f4xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f4xx_hal_usart.h
  • USART_CR1_REG_INDEX : stm32f4xx_hal_usart.h
  • USART_CR2_REG_INDEX : stm32f4xx_hal_usart.h
  • USART_CR3_REG_INDEX : stm32f4xx_hal_usart.h
  • USART_DIV : stm32f4xx_hal_usart.h
  • USART_DIVFRAQ : stm32f4xx_hal_usart.h
  • USART_DIVMANT : stm32f4xx_hal_usart.h
  • USART_DMAError() : stm32f4xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f4xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f4xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f4xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f4xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f4xx_hal_usart.c
  • USART_FLAG_FE : stm32f4xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f4xx_hal_usart.h
  • USART_FLAG_NE : stm32f4xx_hal_usart.h
  • USART_FLAG_ORE : stm32f4xx_hal_usart.h
  • USART_FLAG_PE : stm32f4xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f4xx_hal_usart.h
  • USART_FLAG_TC : stm32f4xx_hal_usart.h
  • USART_FLAG_TXE : stm32f4xx_hal_usart.h
  • USART_IT_CTS : stm32f4xx_hal_usart.h
  • USART_IT_ERR : stm32f4xx_hal_usart.h
  • USART_IT_IDLE : stm32f4xx_hal_usart.h
  • USART_IT_LBD : stm32f4xx_hal_usart.h
  • USART_IT_MASK : stm32f4xx_hal_usart.h
  • USART_IT_PE : stm32f4xx_hal_usart.h
  • USART_IT_RXNE : stm32f4xx_hal_usart.h
  • USART_IT_TC : stm32f4xx_hal_usart.h
  • USART_IT_TXE : stm32f4xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f4xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f4xx_hal_usart.h
  • USART_MODE_RX : stm32f4xx_hal_usart.h
  • USART_MODE_TX : stm32f4xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f4xx_hal_usart.h
  • USART_NACK_DISABLE : stm32f4xx_hal_usart.h
  • USART_NACK_ENABLE : stm32f4xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f4xx_hal_usart.h
  • USART_PARITY_NONE : stm32f4xx_hal_usart.h
  • USART_PARITY_ODD : stm32f4xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f4xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f4xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f4xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f4xx_hal_usart.h
  • USART_Receive_IT() : stm32f4xx_hal_usart.c
  • USART_SetConfig() : stm32f4xx_hal_usart.c
  • USART_STOPBITS_0_5 : stm32f4xx_hal_usart.h
  • USART_STOPBITS_1 : stm32f4xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f4xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f4xx_hal_usart.h
  • USART_TIMEOUT_VALUE : stm32f4xx_hal_usart.c
  • USART_Transmit_IT() : stm32f4xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f4xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32f4xx_hal_usart.c
  • USART_WORDLENGTH_8B : stm32f4xx_hal_usart.h
  • USART_WORDLENGTH_9B : stm32f4xx_hal_usart.h
  • USE_RTOS : stm32f4xx_hal_conf.h
  • uwTick : stm32f4xx_hal.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VDD_VALUE : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_CFR_BASE : stm32f4xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32f4xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f4xx_hal_wwdg.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
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  • i
  • r
  • s
  • t
  • u

- a -

  • ADC_DMAConvCplt() : stm32f4xx_hal_adc.c
  • ADC_DMAError() : stm32f4xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32f4xx_hal_adc.c
  • ADC_Init() : stm32f4xx_hal_adc.c
  • ADC_MultiModeDMAConvCplt() : stm32f4xx_hal_adc_ex.c
  • ADC_MultiModeDMAError() : stm32f4xx_hal_adc_ex.c
  • ADC_MultiModeDMAHalfConvCplt() : stm32f4xx_hal_adc_ex.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • d
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  • i
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  • t
  • u

- d -

  • DAC_DMAConvCpltCh1() : stm32f4xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • DAC_DMAErrorCh1() : stm32f4xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • DAC_DMAHalfConvCpltCh1() : stm32f4xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32f4xx_hal_dac_ex.h , stm32f4xx_hal_dac_ex.c
  • DMA_CalcBaseAndBitshift() : stm32f4xx_hal_dma.c
  • DMA_MultiBufferSetConfig() : stm32f4xx_hal_dma_ex.c
  • DMA_SetConfig() : stm32f4xx_hal_dma.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
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  • u

- f -

  • FLASH_Erase_Sector() : stm32f4xx_hal_flash_ex.c , stm32f4xx_hal_flash_ex.h
  • FLASH_FlushCaches() : stm32f4xx_hal_flash_ex.h , stm32f4xx_hal_flash_ex.c
  • FLASH_MassErase() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_BOR_LevelConfig() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_DisablePCROP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_EnablePCROP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetBOR() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f4xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f4xx_hal_flash_ex.c
  • FLASH_Program_Byte() : stm32f4xx_hal_flash.c
  • FLASH_Program_DoubleWord() : stm32f4xx_hal_flash.c
  • FLASH_Program_HalfWord() : stm32f4xx_hal_flash.c
  • FLASH_Program_Word() : stm32f4xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32f4xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32f4xx_hal_flash.c , stm32f4xx_hal_flash.h , stm32f4xx_hal_flash_ex.c
  • FMPI2C_Disable_IRQ() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAError() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMasterReceiveCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMasterTransmitCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMemReceiveCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMAMemTransmitCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMASlaveReceiveCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_DMASlaveTransmitCplt() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_Enable_IRQ() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_IsAcknowledgeFailed() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_Master_ISR() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_RequestMemoryRead() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_RequestMemoryWrite() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_Slave_ISR() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TransferConfig() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnRXNEFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnSTOPFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_WaitOnTXISFlagUntilTimeout() : stm32f4xx_hal_fmpi2c.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • d
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  • i
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  • s
  • t
  • u

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f4xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32f4xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f4xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f4xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f4xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f4xx_hal_adc.c
  • HAL_ADC_Init() : stm32f4xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32f4xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f4xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32f4xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f4xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f4xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32f4xx_hal_adc.c
  • HAL_ADC_Start() : stm32f4xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32f4xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32f4xx_hal_adc.c
  • HAL_ADC_Stop() : stm32f4xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32f4xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32f4xx_hal_adc.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32f4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32f4xx_hal_adc_ex.c
  • HAL_CRC_Accumulate() : stm32f4xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32f4xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32f4xx_hal_crc.c
  • HAL_CRC_GetState() : stm32f4xx_hal_crc.c
  • HAL_CRC_Init() : stm32f4xx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32f4xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32f4xx_hal_crc.c
  • HAL_DAC_ConfigChannel() : stm32f4xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_DeInit() : stm32f4xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_GetError() : stm32f4xx_hal_dac.c
  • HAL_DAC_GetState() : stm32f4xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32f4xx_hal_dac.c
  • HAL_DAC_Init() : stm32f4xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32f4xx_hal_dac.c , stm32f4xx_hal_dac.h
  • HAL_DAC_MspDeInit() : stm32f4xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32f4xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32f4xx_hal_dac.c
  • HAL_DAC_Start() : stm32f4xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32f4xx_hal_dac.c
  • HAL_DAC_Stop() : stm32f4xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32f4xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_DualGetValue() : stm32f4xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32f4xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32f4xx_hal_dac_ex.c , stm32f4xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32f4xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32f4xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f4xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f4xx_hal.c
  • HAL_DeInit() : stm32f4xx_hal.c
  • HAL_Delay() : stm32f4xx_hal.c
  • HAL_DisableCompensationCell() : stm32f4xx_hal.c
  • HAL_DMA_Abort() : stm32f4xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32f4xx_hal_dma.c
  • HAL_DMA_GetError() : stm32f4xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f4xx_hal_dma.c
  • HAL_DMA_Init() : stm32f4xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f4xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32f4xx_hal_dma.c
  • HAL_DMA_Start() : stm32f4xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f4xx_hal_dma.c
  • HAL_DMAEx_ChangeMemory() : stm32f4xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart() : stm32f4xx_hal_dma_ex.c
  • HAL_DMAEx_MultiBufferStart_IT() : stm32f4xx_hal_dma_ex.c
  • HAL_EnableCompensationCell() : stm32f4xx_hal.c
  • HAL_FLASH_EndOfOperationCallback() : stm32f4xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32f4xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f4xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32f4xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f4xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f4xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f4xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f4xx_hal_flash.c
  • HAL_FLASHEx_AdvOBGetConfig() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_AdvOBProgram() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_DisableFlashSleepMode() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableFlashSleepMode() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_Erase() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OB_DeSelectPCROP() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OB_SelectPCROP() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f4xx_hal_flash_ex.c
  • HAL_FLASHEx_StartFlashInterfaceClk() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_StopFlashInterfaceClk() : stm32f4xx_hal_flash_ramfunc.c
  • HAL_FMPI2C_AddrCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_DeInit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_DisableListen_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_EnableListen_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_ER_IRQHandler() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_ErrorCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_EV_IRQHandler() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_GetError() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_GetMode() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_GetState() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Init() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_IsDeviceReady() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_ListenCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Abort_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Receive() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Receive_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Sequential_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Sequential_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Transmit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Transmit_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Master_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MasterRxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MasterTxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Read() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Read_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Read_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Write() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Write_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Mem_Write_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MemRxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MemTxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MspDeInit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_MspInit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Receive() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Receive_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Sequential_Receive_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Sequential_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Transmit() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Transmit_DMA() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_Slave_Transmit_IT() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_SlaveRxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2C_SlaveTxCpltCallback() : stm32f4xx_hal_fmpi2c.c
  • HAL_FMPI2CEx_ConfigAnalogFilter() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_ConfigDigitalFilter() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_DisableFastModePlus() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_DisableWakeUp() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_EnableFastModePlus() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_FMPI2CEx_EnableWakeUp() : stm32f4xx_hal_fmpi2c_ex.c
  • HAL_GetDEVID() : stm32f4xx_hal.c
  • HAL_GetHalVersion() : stm32f4xx_hal.c
  • HAL_GetREVID() : stm32f4xx_hal.c
  • HAL_GetTick() : stm32f4xx_hal.c
  • HAL_GPIO_DeInit() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f4xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f4xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f4xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f4xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f4xx_hal_uart.c
  • HAL_I2C_AddrCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f4xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f4xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f4xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32f4xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f4xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f4xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f4xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f4xx_hal_i2c.c
  • HAL_I2S_DeInit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_DMAPause() : stm32f4xx_hal_i2s.c
  • HAL_I2S_DMAResume() : stm32f4xx_hal_i2s.c
  • HAL_I2S_DMAStop() : stm32f4xx_hal_i2s.c
  • HAL_I2S_ErrorCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_GetError() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • HAL_I2S_GetState() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • HAL_I2S_Init() : stm32f4xx_hal_i2s.c
  • HAL_I2S_IRQHandler() : stm32f4xx_hal_i2s.c
  • HAL_I2S_MspDeInit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_MspInit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Receive() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Receive_DMA() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Receive_IT() : stm32f4xx_hal_i2s.c
  • HAL_I2S_RxCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_RxHalfCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Transmit() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Transmit_DMA() : stm32f4xx_hal_i2s.c
  • HAL_I2S_Transmit_IT() : stm32f4xx_hal_i2s.c
  • HAL_I2S_TxCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2S_TxHalfCpltCallback() : stm32f4xx_hal_i2s.c
  • HAL_I2SEx_TransmitReceive() : stm32f4xx_hal_i2s_ex.h
  • HAL_I2SEx_TransmitReceive_DMA() : stm32f4xx_hal_i2s_ex.h
  • HAL_I2SEx_TransmitReceive_IT() : stm32f4xx_hal_i2s_ex.h
  • HAL_IncTick() : stm32f4xx_hal.c
  • HAL_Init() : stm32f4xx_hal.c
  • HAL_InitTick() : stm32f4xx_hal.c
  • HAL_IRDA_DeInit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f4xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f4xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f4xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f4xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f4xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f4xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f4xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f4xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f4xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f4xx_hal_irda.c
  • HAL_IWDG_GetState() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_MspInit() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32f4xx_hal_iwdg.c
  • HAL_IWDG_Start() : stm32f4xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32f4xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f4xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_MspDeInit() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32f4xx_hal_lptim.c , stm32f4xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32f4xx_hal_lptim.h , stm32f4xx_hal_lptim.c
  • HAL_MPU_ConfigRegion() : stm32f4xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32f4xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32f4xx_hal_cortex.h
  • HAL_MspDeInit() : stm32f4xx_hal.c
  • HAL_MspInit() : stm32f4xx_hal.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f4xx_hal_uart.c
  • HAL_MultiProcessor_ExitMuteMode() : stm32f4xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f4xx_hal_uart.c
  • HAL_NVIC_ClearPendingIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f4xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f4xx_hal_cortex.c
  • HAL_PWR_ConfigPVD() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f4xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f4xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f4xx_hal_pwr.c
  • HAL_PWR_PVD_IRQHandler() : stm32f4xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32f4xx_hal_pwr.c
  • HAL_PWREx_ControlVoltageScaling() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBkUpReg() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableMainRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBkUpReg() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableMainRegulatorLowVoltage() : stm32f4xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32f4xx_hal_pwr_ex.c
  • HAL_RCC_ClockConfig() : stm32f4xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f4xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f4xx_hal_rcc.c , stm32f4xx_hal_rcc_ex.c
  • HAL_RCC_DisableCSS() : stm32f4xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f4xx_hal_rcc_ex.c , stm32f4xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f4xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f4xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32f4xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f4xx_hal_rcc.c , stm32f4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f4xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f4xx_hal_rcc_ex.c
  • HAL_RCCEx_SelectLSEMode() : stm32f4xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32f4xx_hal.c
  • HAL_RNG_DeInit() : stm32f4xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32f4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32f4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32f4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber() : stm32f4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber_IT() : stm32f4xx_hal_rng.c
  • HAL_RNG_GetState() : stm32f4xx_hal_rng.c
  • HAL_RNG_Init() : stm32f4xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32f4xx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32f4xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32f4xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32f4xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32f4xx_hal_rng.c
  • HAL_RTC_AlarmAEventCallback() : stm32f4xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32f4xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32f4xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32f4xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32f4xx_hal_rtc.c
  • HAL_RTC_Init() : stm32f4xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32f4xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32f4xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32f4xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32f4xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32f4xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCoarseCalib() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCoarseCalib() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32f4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32f4xx_hal_rtc_ex.c
  • HAL_SMARTCARD_DeInit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_ReInit() : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f4xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f4xx_hal_smartcard.c
  • HAL_SPI_DeInit() : stm32f4xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f4xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f4xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f4xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f4xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f4xx_hal_spi.c
  • HAL_SPI_Init() : stm32f4xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f4xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32f4xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f4xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f4xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f4xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f4xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32f4xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f4xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f4xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f4xx_hal_spi.c
  • HAL_SuspendTick() : stm32f4xx_hal.c
  • HAL_SYSTICK_Callback() : stm32f4xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f4xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f4xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f4xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f4xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f4xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f4xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32f4xx_hal_tim.c
  • HAL_TIMEx_BreakCallback() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f4xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32f4xx_hal_tim_ex.c
  • HAL_UART_DeInit() : stm32f4xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f4xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f4xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f4xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_GetError() : stm32f4xx_hal_uart.c
  • HAL_UART_GetState() : stm32f4xx_hal_uart.c
  • HAL_UART_Init() : stm32f4xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f4xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32f4xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f4xx_hal_uart.c
  • HAL_UART_Receive() : stm32f4xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f4xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f4xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_Transmit() : stm32f4xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f4xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f4xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f4xx_hal_uart.c
  • HAL_USART_DeInit() : stm32f4xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f4xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f4xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f4xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_GetError() : stm32f4xx_hal_usart.c
  • HAL_USART_GetState() : stm32f4xx_hal_usart.c
  • HAL_USART_Init() : stm32f4xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f4xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32f4xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f4xx_hal_usart.c
  • HAL_USART_Receive() : stm32f4xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f4xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f4xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_Transmit() : stm32f4xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f4xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f4xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f4xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f4xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f4xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f4xx_hal_usart.c
  • HAL_WWDG_DeInit() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_GetState() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_MspDeInit() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Start() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_Start_IT() : stm32f4xx_hal_wwdg.c
  • HAL_WWDG_WakeupCallback() : stm32f4xx_hal_wwdg.c , stm32f4xx_hal_wwdg.h
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STM32F410Rx HAL User Manual: Globals

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- i -

  • I2C_DMAError() : stm32f4xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMAMemReceiveCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMAMemTransmitCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32f4xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32f4xx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32f4xx_hal_i2c.c
  • I2C_MasterReceive_BTF() : stm32f4xx_hal_i2c.c
  • I2C_MasterReceive_RXNE() : stm32f4xx_hal_i2c.c
  • I2C_MasterRequestRead() : stm32f4xx_hal_i2c.c
  • I2C_MasterRequestWrite() : stm32f4xx_hal_i2c.c
  • I2C_MasterTransmit_BTF() : stm32f4xx_hal_i2c.c
  • I2C_MasterTransmit_TXE() : stm32f4xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32f4xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f4xx_hal_i2c.c
  • I2C_Slave_ADDR() : stm32f4xx_hal_i2c.c
  • I2C_Slave_AF() : stm32f4xx_hal_i2c.c
  • I2C_Slave_STOPF() : stm32f4xx_hal_i2c.c
  • I2C_SlaveReceive_BTF() : stm32f4xx_hal_i2c.c
  • I2C_SlaveReceive_RXNE() : stm32f4xx_hal_i2c.c
  • I2C_SlaveTransmit_BTF() : stm32f4xx_hal_i2c.c
  • I2C_SlaveTransmit_TXE() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnBTFFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnMasterAddressFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2C_WaitOnTXEFlagUntilTimeout() : stm32f4xx_hal_i2c.c
  • I2S_DMAError() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_DMARxCplt() : stm32f4xx_hal_i2s.h , stm32f4xx_hal_i2s_ex.c
  • I2S_DMARxHalfCplt() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_DMATxCplt() : stm32f4xx_hal_i2s.h , stm32f4xx_hal_i2s_ex.c
  • I2S_DMATxHalfCplt() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_GetInputClock() : stm32f4xx_hal_i2s_ex.h , stm32f4xx_hal_i2s_ex.c
  • I2S_Receive_IT() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_Transmit_IT() : stm32f4xx_hal_i2s.c , stm32f4xx_hal_i2s.h
  • I2S_WaitFlagStateUntilTimeout() : stm32f4xx_hal_i2s.h , stm32f4xx_hal_i2s.c
  • I2SEx_TransmitReceive_IT() : stm32f4xx_hal_i2s_ex.h
  • IRDA_DMAError() : stm32f4xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f4xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f4xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f4xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f4xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f4xx_hal_irda.c
  • IRDA_Receive_IT() : stm32f4xx_hal_irda.c
  • IRDA_SetConfig() : stm32f4xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32f4xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32f4xx_hal_irda.c
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STM32F410Rx HAL User Manual: Globals

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  • u

- r -

  • RTC_Bcd2ToByte() : stm32f4xx_hal_rtc.c , stm32f4xx_hal_rtc.h
  • RTC_ByteToBcd2() : stm32f4xx_hal_rtc.h , stm32f4xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32f4xx_hal_rtc.h , stm32f4xx_hal_rtc.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- s -

  • SMARTCARD_DMAError() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_Receive_IT() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_Transmit_IT() : stm32f4xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f4xx_hal_smartcard.c
  • SPI_2linesRxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_CheckFlag_BSY() : stm32f4xx_hal_spi.c
  • SPI_CheckForDisablingSPI() : stm32f4xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32f4xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f4xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f4xx_hal_spi.c
  • SPI_DMAError() : stm32f4xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f4xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f4xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f4xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32f4xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f4xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32f4xx_hal_spi.c
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STM32F410Rx HAL User Manual: Globals

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- t -

  • TIM_Base_SetConfig() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32f4xx_hal_tim.h , stm32f4xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32f4xx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_DMADelayPulseCplt() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_DMAError() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_DMAPeriodElapsedCplt() : stm32f4xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f4xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_ITRx_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32f4xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f4xx_hal_tim.c , stm32f4xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32f4xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f4xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f4xx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32f4xx_hal_tim_ex.c , stm32f4xx_hal_tim_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- u -

  • UART_DMAError() : stm32f4xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f4xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f4xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f4xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f4xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f4xx_hal_uart.c
  • UART_Receive_IT() : stm32f4xx_hal_uart.c
  • UART_SetConfig() : stm32f4xx_hal_uart.c
  • UART_Transmit_IT() : stm32f4xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32f4xx_hal_uart.c
  • USART_DMAError() : stm32f4xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f4xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f4xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f4xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f4xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f4xx_hal_usart.c
  • USART_Receive_IT() : stm32f4xx_hal_usart.c
  • USART_SetConfig() : stm32f4xx_hal_usart.c
  • USART_Transmit_IT() : stm32f4xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f4xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32f4xx_hal_usart.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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  • APBAHBPrescTable : stm32f4xx_hal_rcc.c
  • pFlash : stm32f4xx_hal_flash.c , stm32f4xx_hal_flash_ex.c
  • uwTick : stm32f4xx_hal.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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  • DMA_HandleTypeDef : stm32f4xx_hal_dma.h
  • HAL_LPTIM_StateTypeDef : stm32f4xx_hal_lptim.h
  • SPI_HandleTypeDef : stm32f4xx_hal_spi.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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  • __HAL_LPTIM_StateTypeDef : stm32f4xx_hal_lptim.h
  • FLASH_ProcedureTypeDef : stm32f4xx_hal_flash.h
  • GPIO_PinState : stm32f4xx_hal_gpio.h
  • HAL_CRC_StateTypeDef : stm32f4xx_hal_crc.h
  • HAL_DAC_StateTypeDef : stm32f4xx_hal_dac.h
  • HAL_DMA_LevelCompleteTypeDef : stm32f4xx_hal_dma.h
  • HAL_DMA_MemoryTypeDef : stm32f4xx_hal_dma_ex.h
  • HAL_DMA_StateTypeDef : stm32f4xx_hal_dma.h
  • HAL_FMPI2C_ModeTypeDef : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_StateTypeDef : stm32f4xx_hal_fmpi2c.h
  • HAL_I2C_ModeTypeDef : stm32f4xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32f4xx_hal_i2c.h
  • HAL_I2S_StateTypeDef : stm32f4xx_hal_i2s.h
  • HAL_IRDA_StateTypeDef : stm32f4xx_hal_irda.h
  • HAL_IWDG_StateTypeDef : stm32f4xx_hal_iwdg.h
  • HAL_RNG_StateTypeDef : stm32f4xx_hal_rng.h
  • HAL_RTCStateTypeDef : stm32f4xx_hal_rtc.h
  • HAL_SMARTCARD_StateTypeDef : stm32f4xx_hal_smartcard.h
  • HAL_SPI_StateTypeDef : stm32f4xx_hal_spi.h
  • HAL_TIM_ActiveChannel : stm32f4xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f4xx_hal_tim.h
  • HAL_UART_StateTypeDef : stm32f4xx_hal_uart.h
  • HAL_USART_StateTypeDef : stm32f4xx_hal_usart.h
  • HAL_WWDG_StateTypeDef : stm32f4xx_hal_wwdg.h
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STM32F410Rx HAL User Manual: Globals

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  • f
  • g
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  • m

- f -

  • FLASH_PROC_MASSERASE : stm32f4xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f4xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32f4xx_hal_flash.h
  • FLASH_PROC_SECTERASE : stm32f4xx_hal_flash.h

- g -

  • GPIO_PIN_RESET : stm32f4xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f4xx_hal_gpio.h

- h -

  • HAL_CRC_STATE_BUSY : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f4xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f4xx_hal_crc.h
  • HAL_DAC_STATE_BUSY : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32f4xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32f4xx_hal_dac.h
  • HAL_DMA_FULL_TRANSFER : stm32f4xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM0 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_BUSY_MEM1 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_ERROR : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM0 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_HALF_MEM1 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM0 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_READY_MEM1 : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f4xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f4xx_hal_dma.h
  • HAL_FMPI2C_MODE_MASTER : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODE_MEM : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODE_NONE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODE_SLAVE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_RX : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_RX_LISTEN : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_TX : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_BUSY_TX_LISTEN : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_ERROR : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_LISTEN : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_READY : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_RESET : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_STATE_TIMEOUT : stm32f4xx_hal_fmpi2c.h
  • HAL_I2C_MODE_MASTER : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f4xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f4xx_hal_i2c.h
  • HAL_I2S_STATE_BUSY : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_RX : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_BUSY_TX_RX : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_ERROR : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_READY : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_RESET : stm32f4xx_hal_i2s.h
  • HAL_I2S_STATE_TIMEOUT : stm32f4xx_hal_i2s.h
  • HAL_IRDA_STATE_BUSY : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f4xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f4xx_hal_irda.h
  • HAL_IWDG_STATE_BUSY : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_ERROR : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_READY : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_RESET : stm32f4xx_hal_iwdg.h
  • HAL_IWDG_STATE_TIMEOUT : stm32f4xx_hal_iwdg.h
  • HAL_LPTIM_STATE_BUSY : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32f4xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32f4xx_hal_lptim.h
  • HAL_RNG_STATE_BUSY : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32f4xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32f4xx_hal_rng.h
  • HAL_RTC_STATE_BUSY : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f4xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f4xx_hal_rtc.h
  • HAL_SMARTCARD_STATE_BUSY : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f4xx_hal_smartcard.h
  • HAL_SPI_STATE_BUSY : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f4xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f4xx_hal_spi.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f4xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f4xx_hal_tim.h
  • HAL_UART_STATE_BUSY : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f4xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f4xx_hal_uart.h
  • HAL_USART_STATE_BUSY : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f4xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f4xx_hal_usart.h
  • HAL_WWDG_STATE_BUSY : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_ERROR : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_READY : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_RESET : stm32f4xx_hal_wwdg.h
  • HAL_WWDG_STATE_TIMEOUT : stm32f4xx_hal_wwdg.h

- m -

  • MEMORY0 : stm32f4xx_hal_dma_ex.h
  • MEMORY1 : stm32f4xx_hal_dma_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- _ -

  • __HAL_ADC_CLEAR_FLAG : stm32f4xx_hal_adc.h
  • __HAL_ADC_DISABLE : stm32f4xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32f4xx_hal_adc.h
  • __HAL_ADC_ENABLE : stm32f4xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32f4xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32f4xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f4xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f4xx_hal_adc.h
  • __HAL_CRC_DR_RESET : stm32f4xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f4xx_hal_crc.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f4xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f4xx_hal_crc.h
  • __HAL_DAC_CLEAR_FLAG : stm32f4xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32f4xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32f4xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32f4xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32f4xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32f4xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32f4xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32f4xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_CAN2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM10 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM11 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM12 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM13 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM14 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM9 : stm32f4xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM10 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM11 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM12 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM13 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM14 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM9 : stm32f4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f4xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32f4xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32f4xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f4xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f4xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_DME_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_FE_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_FS : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f4xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f4xx_hal_dma.h
  • __HAL_DMA_SET_COUNTER : stm32f4xx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32f4xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32f4xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32f4xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32f4xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32f4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32f4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f4xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f4xx_hal_flash.h
  • __HAL_FMPI2C_CLEAR_FLAG : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_DISABLE : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_DISABLE_IT : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_ENABLE : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_ENABLE_IT : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_GET_FLAG : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_GET_IT_SOURCE : stm32f4xx_hal_fmpi2c.h
  • __HAL_FMPI2C_RESET_HANDLE_STATE : stm32f4xx_hal_fmpi2c.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f4xx_hal_gpio.h
  • __HAL_I2C_CLEAR_ADDRFLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_CLEAR_FLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_CLEAR_STOPFLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f4xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f4xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f4xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f4xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f4xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f4xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f4xx_hal_i2c.h
  • __HAL_I2S_CLEAR_OVRFLAG : stm32f4xx_hal_i2s.h
  • __HAL_I2S_CLEAR_UDRFLAG : stm32f4xx_hal_i2s.h
  • __HAL_I2S_DISABLE : stm32f4xx_hal_i2s.h
  • __HAL_I2S_DISABLE_IT : stm32f4xx_hal_i2s.h
  • __HAL_I2S_ENABLE : stm32f4xx_hal_i2s.h
  • __HAL_I2S_ENABLE_IT : stm32f4xx_hal_i2s.h
  • __HAL_I2S_GET_FLAG : stm32f4xx_hal_i2s.h
  • __HAL_I2S_GET_IT_SOURCE : stm32f4xx_hal_i2s.h
  • __HAL_I2S_RESET_HANDLE_STATE : stm32f4xx_hal_i2s.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f4xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32f4xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f4xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f4xx_hal_irda.h
  • __HAL_IWDG_GET_FLAG : stm32f4xx_hal_iwdg.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f4xx_hal_iwdg.h
  • __HAL_IWDG_RESET_HANDLE_STATE : stm32f4xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f4xx_hal_iwdg.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_OPTR_CONFIG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f4xx_hal_lptim.h
  • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG : stm32f4xx_hal_lptim.h
  • __HAL_PWR_CLEAR_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f4xx_hal_pwr.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32f4xx_hal_pwr_ex.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DAC_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_EXTIT_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_EXTIT_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FLITF_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_FMPI2C1_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GET_FMPI2C1_SOURCE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2S_SOURCE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_I2S_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_MCO1_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_MCO1_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_MCO2_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_MCO2_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_MCO2_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_PLL_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PLLI2S_CONFIG : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTC_CLKPRESCALER : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SPI5_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SPI5_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM11_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_TIM9_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIM9_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_TIMCLKPRESCALER : stm32f4xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_USART6_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f4xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f4xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32f4xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32f4xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32f4xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32f4xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32f4xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32f4xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_COARSE_CALIB_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_COARSE_CALIB_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32f4xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f4xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f4xx_hal_rtc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_DISABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_ENABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f4xx_hal_smartcard.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f4xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f4xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f4xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f4xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f4xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f4xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f4xx_hal_spi.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32f4xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32f4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32f4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32f4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32f4xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32f4xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f4xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f4xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f4xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f4xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f4xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f4xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f4xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f4xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f4xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f4xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f4xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f4xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f4xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f4xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f4xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f4xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f4xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f4xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32f4xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f4xx_hal_usart.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_DISABLE_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f4xx_hal_wwdg.h
  • __HAL_WWDG_RESET_HANDLE_STATE : stm32f4xx_hal_wwdg.h
  • __MCO1_CLK_ENABLE : stm32f4xx_hal_rcc.c
  • __MCO2_CLK_ENABLE : stm32f4xx_hal_rcc.c
  • __STM32F4xx_HAL_VERSION : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_MAIN : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_RC : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_SUB1 : stm32f4xx_hal.c
  • __STM32F4xx_HAL_VERSION_SUB2 : stm32f4xx_hal.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- a -

  • ACR_BYTE0_ADDRESS : stm32f4xx_hal_flash.h
  • ADC_ALL_CHANNELS : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f4xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f4xx_hal_adc.h
  • ADC_AWD_EVENT : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_0 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_1 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_11 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_12 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_13 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_14 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_15 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_16 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_17 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_18 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_2 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_3 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_4 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_5 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_6 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_7 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_8 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_9 : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f4xx_hal_adc_ex.h
  • ADC_CHANNEL_VBAT : stm32f4xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32f4xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV6 : stm32f4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV8 : stm32f4xx_hal_adc.h
  • ADC_CR1_DISCONTINUOUS : stm32f4xx_hal_adc.h
  • ADC_CR1_SCANCONV : stm32f4xx_hal_adc.h
  • ADC_CR2_CONTINUOUS : stm32f4xx_hal_adc.h
  • ADC_CR2_DMAContReq : stm32f4xx_hal_adc.h
  • ADC_CR2_EOCSelection : stm32f4xx_hal_adc.h
  • ADC_DATAALIGN_LEFT : stm32f4xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32f4xx_hal_adc.h
  • ADC_DMAACCESSMODE_1 : stm32f4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_2 : stm32f4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_3 : stm32f4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_ALTERTRIG : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32f4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32f4xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32f4xx_hal_adc.h
  • ADC_EOC_SINGLE_SEQ_CONV : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_Ext_IT11 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC2 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T1_CC3 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC3 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_CC4 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T2_TRGO : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T3_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T3_TRGO : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_CC2 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T5_CC3 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_CC1 : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONV_T8_TRGO : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32f4xx_hal_adc.h
  • ADC_EXTERNALTRIGINJECCONV_EXT_IT15 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC2 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_CC1 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_CC2 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_CC3 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T5_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T5_TRGO : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC2 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC3 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T8_CC4 : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_FALLING : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_NONE : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISING : stm32f4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING : stm32f4xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f4xx_hal_adc.h
  • ADC_FLAG_EOC : stm32f4xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32f4xx_hal_adc.h
  • ADC_FLAG_JSTRT : stm32f4xx_hal_adc.h
  • ADC_FLAG_OVR : stm32f4xx_hal_adc.h
  • ADC_FLAG_STRT : stm32f4xx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32f4xx_hal_adc.h
  • ADC_INJECTED_CHANNELS : stm32f4xx_hal_adc.h
  • ADC_INJECTED_RANK_1 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f4xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f4xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f4xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f4xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f4xx_hal_adc.h
  • ADC_IT_AWD : stm32f4xx_hal_adc.h
  • ADC_IT_EOC : stm32f4xx_hal_adc.h
  • ADC_IT_JEOC : stm32f4xx_hal_adc.h
  • ADC_IT_OVR : stm32f4xx_hal_adc.h
  • ADC_JSQR : stm32f4xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32f4xx_hal_adc_ex.h
  • ADC_OVR_EVENT : stm32f4xx_hal_adc.h
  • ADC_REGULAR_CHANNELS : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32f4xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_112CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_144CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_15CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_3CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_480CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_56CYCLES : stm32f4xx_hal_adc.h
  • ADC_SAMPLETIME_84CYCLES : stm32f4xx_hal_adc.h
  • ADC_SMPR1 : stm32f4xx_hal_adc.h
  • ADC_SMPR2 : stm32f4xx_hal_adc.h
  • ADC_SOFTWARE_START : stm32f4xx_hal_adc.h
  • ADC_SQR1 : stm32f4xx_hal_adc.h
  • ADC_SQR1_RK : stm32f4xx_hal_adc.h
  • ADC_SQR2_RK : stm32f4xx_hal_adc.h
  • ADC_SQR3_RK : stm32f4xx_hal_adc.h
  • ADC_STAB_DELAY_US : stm32f4xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32f4xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f4xx_hal_adc.h
  • ADC_TRIPLEMODE_ALTERTRIG : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_INTERL : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_AlterTrig : stm32f4xx_hal_adc_ex.h
  • ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT : stm32f4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_13CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_14CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_15CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_16CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_17CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_18CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_19CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_20CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32f4xx_hal_adc.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32f4xx_hal_adc.h
  • assert_param : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- b -

  • BRE_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- c -

  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f4xx_hal_rcc.c
  • CMP_PD_BIT_NUMBER : stm32f4xx_hal.c
  • CMPCR_CMP_PD_BB : stm32f4xx_hal.c
  • CMPCR_OFFSET : stm32f4xx_hal.c
  • CR_DBP_BB : stm32f4xx_hal_pwr.h
  • CR_FPDS_BB : stm32f4xx_hal_pwr_ex.h
  • CR_LPLVDS_BB : stm32f4xx_hal_pwr_ex.h
  • CR_MRLVDS_BB : stm32f4xx_hal_pwr_ex.h
  • CR_ODEN_BB : stm32f4xx_hal_pwr_ex.h
  • CR_ODSWEN_BB : stm32f4xx_hal_pwr_ex.h
  • CR_PMODE_BB : stm32f4xx_hal_pwr.h
  • CR_PSIZE_MASK : stm32f4xx_hal_flash.h
  • CR_PVDE_BB : stm32f4xx_hal_pwr.h
  • CSR_BRE_BB : stm32f4xx_hal_pwr_ex.h
  • CSR_EWUP_BB : stm32f4xx_hal_pwr.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- d -

  • DAC_ALIGN_12B_L : stm32f4xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32f4xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32f4xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32f4xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32f4xx_hal_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32f4xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32f4xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32f4xx_hal_dac.h
  • DAC_FLAG_DMAUDR1 : stm32f4xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32f4xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32f4xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32f4xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32f4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32f4xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32f4xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32f4xx_hal_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32f4xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32f4xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32f4xx_hal_dac.h
  • DATA_CACHE_ENABLE : stm32f4xx_hal_conf.h
  • DBP_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • DMA_CHANNEL_0 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_1 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_2 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_3 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_4 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_5 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_6 : stm32f4xx_hal_dma.h
  • DMA_CHANNEL_7 : stm32f4xx_hal_dma.h
  • DMA_CIRCULAR : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_1QUARTERFULL : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_3QUARTERSFULL : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_FULL : stm32f4xx_hal_dma.h
  • DMA_FIFO_THRESHOLD_HALFFULL : stm32f4xx_hal_dma.h
  • DMA_FIFOMODE_DISABLE : stm32f4xx_hal_dma.h
  • DMA_FIFOMODE_ENABLE : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_DMEIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_FEIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_HTIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TCIF3_7 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF0_4 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF1_5 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF2_6 : stm32f4xx_hal_dma.h
  • DMA_FLAG_TEIF3_7 : stm32f4xx_hal_dma.h
  • DMA_IT_DME : stm32f4xx_hal_dma.h
  • DMA_IT_FE : stm32f4xx_hal_dma.h
  • DMA_IT_HT : stm32f4xx_hal_dma.h
  • DMA_IT_TC : stm32f4xx_hal_dma.h
  • DMA_IT_TE : stm32f4xx_hal_dma.h
  • DMA_MBURST_INC16 : stm32f4xx_hal_dma.h
  • DMA_MBURST_INC4 : stm32f4xx_hal_dma.h
  • DMA_MBURST_INC8 : stm32f4xx_hal_dma.h
  • DMA_MBURST_SINGLE : stm32f4xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f4xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f4xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f4xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f4xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f4xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f4xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f4xx_hal_dma.h
  • DMA_NORMAL : stm32f4xx_hal_dma.h
  • DMA_PBURST_INC16 : stm32f4xx_hal_dma.h
  • DMA_PBURST_INC4 : stm32f4xx_hal_dma.h
  • DMA_PBURST_INC8 : stm32f4xx_hal_dma.h
  • DMA_PBURST_SINGLE : stm32f4xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f4xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f4xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f4xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f4xx_hal_dma.h
  • DMA_PFCTRL : stm32f4xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f4xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f4xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f4xx_hal_dma.h
  • DP83848_PHY_ADDRESS : stm32f4xx_hal_conf.h
  • DUMMY_DATA : stm32f4xx_hal_usart.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- e -

  • ETH_RX_BUF_SIZE : stm32f4xx_hal_conf.h
  • ETH_RXBUFNB : stm32f4xx_hal_conf.h
  • ETH_TX_BUF_SIZE : stm32f4xx_hal_conf.h
  • ETH_TXBUFNB : stm32f4xx_hal_conf.h
  • EWUP_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • EXTERNAL_CLOCK_VALUE : stm32f4xx_hal_conf.h
  • EXTI_MODE : stm32f4xx_hal_gpio.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
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  • d
  • e
  • f
  • g
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  • i
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- f -

  • FALLING_EDGE : stm32f4xx_hal_gpio.c
  • FLASH_BANK_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_FLAG_BSY : stm32f4xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32f4xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_PGPERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32f4xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32f4xx_hal_flash.h
  • FLASH_IT_EOP : stm32f4xx_hal_flash.h
  • FLASH_IT_ERR : stm32f4xx_hal_flash.h
  • FLASH_KEY1 : stm32f4xx_hal_flash.h
  • FLASH_KEY2 : stm32f4xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_2 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_3 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_4 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_5 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_6 : stm32f4xx_hal_flash_ex.h
  • FLASH_LATENCY_7 : stm32f4xx_hal_flash_ex.h
  • FLASH_MER_BIT : stm32f4xx_hal_flash_ex.h
  • FLASH_OPT_KEY1 : stm32f4xx_hal_flash.h
  • FLASH_OPT_KEY2 : stm32f4xx_hal_flash.h
  • FLASH_PSIZE_BYTE : stm32f4xx_hal_flash.h
  • FLASH_PSIZE_DOUBLE_WORD : stm32f4xx_hal_flash.h
  • FLASH_PSIZE_HALF_WORD : stm32f4xx_hal_flash.h
  • FLASH_PSIZE_WORD : stm32f4xx_hal_flash.h
  • FLASH_SECTOR_0 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_2 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_3 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_4 : stm32f4xx_hal_flash_ex.h
  • FLASH_SECTOR_TOTAL : stm32f4xx_hal_flash_ex.h
  • FLASH_TIMEOUT_VALUE : stm32f4xx_hal_flash.c , stm32f4xx_hal_flash_ex.c
  • FLASH_TYPEERASE_MASSERASE : stm32f4xx_hal_flash_ex.h
  • FLASH_TYPEERASE_SECTORS : stm32f4xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_BYTE : stm32f4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f4xx_hal_flash.h
  • FLASH_VOLTAGE_RANGE_1 : stm32f4xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_2 : stm32f4xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_3 : stm32f4xx_hal_flash_ex.h
  • FLASH_VOLTAGE_RANGE_4 : stm32f4xx_hal_flash_ex.h
  • FMPI2C_ADDRESSINGMODE_10BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_ADDRESSINGMODE_7BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_ANALOGFILTER_DISABLE : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_ANALOGFILTER_ENABLE : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_AUTOEND_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_CHECK_FLAG : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_DIRECTION_RECEIVE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_DIRECTION_TRANSMIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_DUALADDRESS_DISABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_DUALADDRESS_ENABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FASTMODEPLUS_SCL : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_FASTMODEPLUS_SDA : stm32f4xx_hal_fmpi2c_ex.h
  • FMPI2C_FIRST_AND_LAST_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FIRST_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_ADDR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_AF : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_ALERT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_ARLO : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_BERR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_BUSY : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_DIR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_MASK : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_OVR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_PECERR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_RXNE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_STOPF : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TC : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TCR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TIMEOUT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TXE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_FLAG_TXIS : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERALCALL_DISABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERALCALL_ENABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_START : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_START_READ : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_START_WRITE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GENERATE_STOP : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_ADDR_MATCH : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_DIR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_ISR_REG : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_OWN_ADDRESS1 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_OWN_ADDRESS2 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_GET_STOP_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_ADDR : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_ADDRI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_ERRI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_NACKI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_RX : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_RXI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_STOPI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_TCI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_TX : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_IT_TXI : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_LAST_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_MEM_ADD_LSB : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_MEM_ADD_MSB : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_MEMADD_SIZE_16BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_MEMADD_SIZE_8BIT : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NEXT_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NO_OPTION_FRAME : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NO_STARTSTOP : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NOSTRETCH_DISABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_NOSTRETCH_ENABLE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK01 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK02 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK03 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK04 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK05 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK06 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_MASK07 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_OA2_NOMASK : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_RELOAD_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_RESET_CR2 : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_SOFTEND_MODE : stm32f4xx_hal_fmpi2c.h
  • FMPI2C_STATE_MASTER_BUSY_RX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MASTER_BUSY_TX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MEM_BUSY_RX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MEM_BUSY_TX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_MSK : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_NONE : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_SLAVE_BUSY_RX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_STATE_SLAVE_BUSY_TX : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_ADDR : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_BUSY : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_DIR : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_FLAG : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_RXNE : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_STOPF : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_TC : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_TCR : stm32f4xx_hal_fmpi2c.c
  • FMPI2C_TIMEOUT_TXIS : stm32f4xx_hal_fmpi2c.c
  • FPDS_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- g -

  • GPIO_AF0_MCO : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_TAMPER : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM11 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM9 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF4_FMPI2C1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI5 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF8_USART6 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF9_FMPI2C1 : stm32f4xx_hal_gpio_ex.h
  • GPIO_AF9_I2C2 : stm32f4xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32f4xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f4xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32f4xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f4xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f4xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f4xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f4xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f4xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f4xx_hal_gpio.h
  • GPIO_NOPULL : stm32f4xx_hal_gpio.h
  • GPIO_NUMBER : stm32f4xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f4xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f4xx_hal_gpio.h
  • GPIO_PIN_All : stm32f4xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f4xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f4xx_hal_gpio.h
  • GPIO_PULLUP : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32f4xx_hal_gpio.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- h -

  • HAL_ADC_ERROR_DMA : stm32f4xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32f4xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32f4xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32f4xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f4xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f4xx_hal_adc.h
  • HAL_CAN_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CEC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CRC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_CRYP_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DAC_ERROR_DMA : stm32f4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32f4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32f4xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32f4xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DCMI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DMA2D_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DMA_ERROR_DME : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_FE : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f4xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f4xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_DSI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_ETH_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_FLASH_ERROR_NONE : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_OPERATION : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGP : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32f4xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f4xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_FMPI2C_ERROR_AF : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_ARLO : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_BERR : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_DMA : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_NONE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_OVR : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_SIZE : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_ERROR_TIMEOUT : stm32f4xx_hal_fmpi2c.h
  • HAL_FMPI2C_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_HASH_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_HCD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f4xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f4xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_I2S_ERROR_DMA : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_FRE : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_NONE : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_OVR : stm32f4xx_hal_i2s.h
  • HAL_I2S_ERROR_UDR : stm32f4xx_hal_i2s.h
  • HAL_I2S_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_I2SEX_ERROR_OVR : stm32f4xx_hal_i2s.h
  • HAL_I2SEX_ERROR_UDR : stm32f4xx_hal_i2s.h
  • HAL_IRDA_ERROR_DMA : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f4xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f4xx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_IWDG_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_LTDC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_PCCARD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_PCD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_QSPI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_RNG_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SAI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SDRAM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f4xx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SPDIFRX_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SPI_ERROR_CRC : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f4xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f4xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_TIM_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_TIMEOUT_DMA_ABORT : stm32f4xx_hal_dma.c
  • HAL_UART_ERROR_DMA : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f4xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f4xx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_USART_ERROR_DMA : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f4xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f4xx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32f4xx_hal_conf.h
  • HSE_STARTUP_TIMEOUT : stm32f4xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • HSE_VALUE : stm32f4xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • HSI_VALUE : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- i -

  • I2C_10BIT_ADDRESS : stm32f4xx_hal_i2c.h
  • I2C_10BIT_HEADER_READ : stm32f4xx_hal_i2c.h
  • I2C_10BIT_HEADER_WRITE : stm32f4xx_hal_i2c.h
  • I2C_7BIT_ADD_READ : stm32f4xx_hal_i2c.h
  • I2C_7BIT_ADD_WRITE : stm32f4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_10BIT : stm32f4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f4xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32f4xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32f4xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32f4xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f4xx_hal_i2c.h
  • I2C_DUTYCYCLE_16_9 : stm32f4xx_hal_i2c.h
  • I2C_DUTYCYCLE_2 : stm32f4xx_hal_i2c.h
  • I2C_FIRST_AND_LAST_FRAME : stm32f4xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32f4xx_hal_i2c.h
  • I2C_FLAG_ADD10 : stm32f4xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f4xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_BTF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f4xx_hal_i2c.h
  • I2C_FLAG_DUALF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_GENCALL : stm32f4xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32f4xx_hal_i2c.h
  • I2C_FLAG_MSL : stm32f4xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f4xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SB : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SMBALERT : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32f4xx_hal_i2c.h
  • I2C_FLAG_SMBHOST : stm32f4xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f4xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f4xx_hal_i2c.h
  • I2C_FLAG_TRA : stm32f4xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f4xx_hal_i2c.h
  • I2C_FREQRANGE : stm32f4xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32f4xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f4xx_hal_i2c.h
  • I2C_IT_BUF : stm32f4xx_hal_i2c.h
  • I2C_IT_ERR : stm32f4xx_hal_i2c.h
  • I2C_IT_EVT : stm32f4xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32f4xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32f4xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f4xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32f4xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32f4xx_hal_i2c.c
  • I2C_NOSTRETCH_DISABLE : stm32f4xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f4xx_hal_i2c.h
  • I2C_RISE_TIME : stm32f4xx_hal_i2c.h
  • I2C_SPEED : stm32f4xx_hal_i2c.h
  • I2C_SPEED_FAST : stm32f4xx_hal_i2c.h
  • I2C_SPEED_STANDARD : stm32f4xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32f4xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32f4xx_hal_i2c.c
  • I2C_STATE_MSK : stm32f4xx_hal_i2c.c
  • I2C_STATE_NONE : stm32f4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32f4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32f4xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR_SLAVE : stm32f4xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY_FLAG : stm32f4xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f4xx_hal_i2c.c
  • I2S_AUDIOFREQ_11K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_16K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_192K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_22K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_32K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_44K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_48K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_8K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_96K : stm32f4xx_hal_i2s.h
  • I2S_AUDIOFREQ_DEFAULT : stm32f4xx_hal_i2s.h
  • I2S_CLOCK_EXTERNAL : stm32f4xx_hal_i2s_ex.h
  • I2S_CLOCK_PLLR : stm32f4xx_hal_i2s_ex.h
  • I2S_CLOCK_PLLSRC : stm32f4xx_hal_i2s_ex.h
  • I2S_CPOL_HIGH : stm32f4xx_hal_i2s.h
  • I2S_CPOL_LOW : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_16B_EXTENDED : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_24B : stm32f4xx_hal_i2s.h
  • I2S_DATAFORMAT_32B : stm32f4xx_hal_i2s.h
  • I2S_FLAG_BSY : stm32f4xx_hal_i2s.h
  • I2S_FLAG_CHSIDE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_FRE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_OVR : stm32f4xx_hal_i2s.h
  • I2S_FLAG_RXNE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_TXE : stm32f4xx_hal_i2s.h
  • I2S_FLAG_UDR : stm32f4xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_DISABLE : stm32f4xx_hal_i2s.h
  • I2S_FULLDUPLEXMODE_ENABLE : stm32f4xx_hal_i2s.h
  • I2S_IT_ERR : stm32f4xx_hal_i2s.h
  • I2S_IT_RXNE : stm32f4xx_hal_i2s.h
  • I2S_IT_TXE : stm32f4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_DISABLE : stm32f4xx_hal_i2s.h
  • I2S_MCLKOUTPUT_ENABLE : stm32f4xx_hal_i2s.h
  • I2S_MODE_MASTER_RX : stm32f4xx_hal_i2s.h
  • I2S_MODE_MASTER_TX : stm32f4xx_hal_i2s.h
  • I2S_MODE_SLAVE_RX : stm32f4xx_hal_i2s.h
  • I2S_MODE_SLAVE_TX : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_LSB : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_MSB : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_PCM_LONG : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_PCM_SHORT : stm32f4xx_hal_i2s.h
  • I2S_STANDARD_PHILIPS : stm32f4xx_hal_i2s.h
  • I2SxEXT : stm32f4xx_hal_i2s_ex.h
  • IDCODE_DEVID_MASK : stm32f4xx_hal.c
  • INSTRUCTION_CACHE_ENABLE : stm32f4xx_hal_conf.h
  • IRDA_BRR : stm32f4xx_hal_irda.h
  • IRDA_CR1_REG_INDEX : stm32f4xx_hal_irda.h
  • IRDA_CR2_REG_INDEX : stm32f4xx_hal_irda.h
  • IRDA_CR3_REG_INDEX : stm32f4xx_hal_irda.h
  • IRDA_DIV : stm32f4xx_hal_irda.h
  • IRDA_DIVFRAQ : stm32f4xx_hal_irda.h
  • IRDA_DIVMANT : stm32f4xx_hal_irda.h
  • IRDA_FLAG_FE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_IDLE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f4xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f4xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f4xx_hal_irda.h
  • IRDA_IT_CTS : stm32f4xx_hal_irda.h
  • IRDA_IT_ERR : stm32f4xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f4xx_hal_irda.h
  • IRDA_IT_LBD : stm32f4xx_hal_irda.h
  • IRDA_IT_MASK : stm32f4xx_hal_irda.h
  • IRDA_IT_PE : stm32f4xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f4xx_hal_irda.h
  • IRDA_IT_TC : stm32f4xx_hal_irda.h
  • IRDA_IT_TXE : stm32f4xx_hal_irda.h
  • IRDA_MODE_RX : stm32f4xx_hal_irda.h
  • IRDA_MODE_TX : stm32f4xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f4xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f4xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f4xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f4xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f4xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f4xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32f4xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32f4xx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG : stm32f4xx_hal_adc.h
  • IS_ADC_CHANNEL : stm32f4xx_hal_adc_ex.h
  • IS_ADC_CHANNELS_TYPE : stm32f4xx_hal_adc.h
  • IS_ADC_CLOCKPRESCALER : stm32f4xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32f4xx_hal_adc.h
  • IS_ADC_DMA_ACCESS_MODE : stm32f4xx_hal_adc_ex.h
  • IS_ADC_EOCSelection : stm32f4xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32f4xx_hal_adc.h
  • IS_ADC_EXT_INJEC_TRIG : stm32f4xx_hal_adc_ex.h
  • IS_ADC_EXT_INJEC_TRIG_EDGE : stm32f4xx_hal_adc_ex.h
  • IS_ADC_EXT_TRIG : stm32f4xx_hal_adc.h
  • IS_ADC_EXT_TRIG_EDGE : stm32f4xx_hal_adc.h
  • IS_ADC_INJECTED_LENGTH : stm32f4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f4xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32f4xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f4xx_hal_adc.h
  • IS_ADC_REGULAR_DISC_NUMBER : stm32f4xx_hal_adc.h
  • IS_ADC_REGULAR_LENGTH : stm32f4xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32f4xx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32f4xx_hal_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f4xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32f4xx_hal_adc.h
  • IS_ADC_THRESHOLD : stm32f4xx_hal_adc.h
  • IS_DAC_ALIGN : stm32f4xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32f4xx_hal_dac.h
  • IS_DAC_DATA : stm32f4xx_hal_dac.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32f4xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32f4xx_hal_dac.h
  • IS_DAC_TRIGGER : stm32f4xx_hal_dac.h
  • IS_DMA_BUFFER_SIZE : stm32f4xx_hal_dma.h
  • IS_DMA_CHANNEL : stm32f4xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f4xx_hal_dma.h
  • IS_DMA_FIFO_MODE_STATE : stm32f4xx_hal_dma.h
  • IS_DMA_FIFO_THRESHOLD : stm32f4xx_hal_dma.h
  • IS_DMA_MEMORY_BURST : stm32f4xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f4xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f4xx_hal_dma.h
  • IS_DMA_MODE : stm32f4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_BURST : stm32f4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f4xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f4xx_hal_dma.h
  • IS_FLASH_ADDRESS : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_BANK : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_LATENCY : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_NBSECTORS : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_SECTOR : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f4xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f4xx_hal_flash.h
  • IS_FMPI2C_ADDRESSING_MODE : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_ANALOG_FILTER : stm32f4xx_hal_fmpi2c_ex.h
  • IS_FMPI2C_DIGITAL_FILTER : stm32f4xx_hal_fmpi2c_ex.h
  • IS_FMPI2C_DUAL_ADDRESS : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_FASTMODEPLUS : stm32f4xx_hal_fmpi2c_ex.h
  • IS_FMPI2C_GENERAL_CALL : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_MEMADD_SIZE : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_NO_STRETCH : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_OWN_ADDRESS1 : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_OWN_ADDRESS2 : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_OWN_ADDRESS2_MASK : stm32f4xx_hal_fmpi2c.h
  • IS_FMPI2C_TRANSFER_OPTIONS_REQUEST : stm32f4xx_hal_fmpi2c.h
  • IS_GPIO_AF : stm32f4xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32f4xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f4xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f4xx_hal_gpio.h
  • IS_GPIO_PULL : stm32f4xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f4xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32f4xx_hal_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32f4xx_hal_i2c.h
  • IS_I2C_DUAL_ADDRESS : stm32f4xx_hal_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32f4xx_hal_i2c.h
  • IS_I2C_GENERAL_CALL : stm32f4xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f4xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32f4xx_hal_i2c.h
  • IS_I2S_AUDIO_FREQ : stm32f4xx_hal_i2s.h
  • IS_I2S_CLOCKSOURCE : stm32f4xx_hal_i2s_ex.h
  • IS_I2S_CPOL : stm32f4xx_hal_i2s.h
  • IS_I2S_DATA_FORMAT : stm32f4xx_hal_i2s.h
  • IS_I2S_FULLDUPLEX_MODE : stm32f4xx_hal_i2s.h
  • IS_I2S_MCLK_OUTPUT : stm32f4xx_hal_i2s.h
  • IS_I2S_MODE : stm32f4xx_hal_i2s.h
  • IS_I2S_STANDARD : stm32f4xx_hal_i2s.h
  • IS_IRDA_BAUDRATE : stm32f4xx_hal_irda.h
  • IS_IRDA_MODE : stm32f4xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f4xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f4xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f4xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32f4xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f4xx_hal_iwdg.h
  • IS_LPTIM_AUTORELOAD : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32f4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32f4xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32f4xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32f4xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32f4xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32f4xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32f4xx_hal_lptim.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32f4xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32f4xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32f4xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32f4xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32f4xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f4xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f4xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f4xx_hal_cortex.h
  • IS_OB_BOR_LEVEL : stm32f4xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f4xx_hal_flash_ex.h
  • IS_OB_PCROP : stm32f4xx_hal_flash_ex.h
  • IS_OB_PCROP_SELECT : stm32f4xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f4xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f4xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f4xx_hal_flash_ex.h
  • IS_OB_WRP_SECTOR : stm32f4xx_hal_flash_ex.h
  • IS_OBEX : stm32f4xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f4xx_hal_flash_ex.h
  • IS_PCROPSTATE : stm32f4xx_hal_flash_ex.h
  • IS_PWR_PVD_LEVEL : stm32f4xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32f4xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32f4xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32f4xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f4xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32f4xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32f4xx_hal_pwr_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_CLOCKTYPE : stm32f4xx_hal_rcc.h
  • IS_RCC_FMPI2C1CLKSOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32f4xx_hal_rcc.h
  • IS_RCC_HSE : stm32f4xx_hal_rcc.h
  • IS_RCC_HSI : stm32f4xx_hal_rcc.h
  • IS_RCC_I2SAPBCLKSOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLKSOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32f4xx_hal_rcc.h
  • IS_RCC_LSE_MODE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_LSI : stm32f4xx_hal_rcc.h
  • IS_RCC_MCO : stm32f4xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f4xx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_MCODIV : stm32f4xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32f4xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f4xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLI2SN_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLI2SR_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLM_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLP_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32f4xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32f4xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32f4xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32f4xx_hal_rcc.h
  • IS_RNG_FLAG : stm32f4xx_hal_rng.h
  • IS_RNG_IT : stm32f4xx_hal_rng.h
  • IS_RTC_ALARM : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32f4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32f4xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f4xx_hal_rtc.h
  • IS_RTC_BKP : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_SIGN : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_VALUE : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32f4xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32f4xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f4xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32f4xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f4xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32f4xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32f4xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f4xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f4xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32f4xx_hal_rtc.h
  • IS_RTC_OUTPUT_POL : stm32f4xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32f4xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f4xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32f4xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32f4xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PIN : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32f4xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32f4xx_hal_rtc.h
  • IS_RTC_YEAR : stm32f4xx_hal_rtc.h
  • IS_SMARTCARD_BAUDRATE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_NACK_STATE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f4xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f4xx_hal_smartcard.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f4xx_hal_spi.h
  • IS_SPI_CPHA : stm32f4xx_hal_spi.h
  • IS_SPI_CPOL : stm32f4xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f4xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f4xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f4xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f4xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f4xx_hal_spi.h
  • IS_SPI_MODE : stm32f4xx_hal_spi.h
  • IS_SPI_NSS : stm32f4xx_hal_spi.h
  • IS_SPI_TIMODE : stm32f4xx_hal_spi.h
  • IS_SYSTICK_CLK_SOURCE : stm32f4xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f4xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f4xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f4xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f4xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32f4xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f4xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f4xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f4xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f4xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_REMAP : stm32f4xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32f4xx_hal_tim.h
  • IS_TIM_SYSTEMBREAKINPUT : stm32f4xx_hal_tim_ex.h
  • IS_TIM_TI1SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f4xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f4xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32f4xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32f4xx_hal_fmpi2c.h
  • IS_TRANSFER_REQUEST : stm32f4xx_hal_fmpi2c.h
  • IS_UART_ADDRESS : stm32f4xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f4xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f4xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f4xx_hal_uart.h
  • IS_UART_LIN_OVERSAMPLING : stm32f4xx_hal_uart.h
  • IS_UART_LIN_WORD_LENGTH : stm32f4xx_hal_uart.h
  • IS_UART_MODE : stm32f4xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32f4xx_hal_uart.h
  • IS_UART_PARITY : stm32f4xx_hal_uart.h
  • IS_UART_STATE : stm32f4xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f4xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f4xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f4xx_hal_uart.h
  • IS_USART_BAUDRATE : stm32f4xx_hal_usart.h
  • IS_USART_CLOCK : stm32f4xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f4xx_hal_usart.h
  • IS_USART_MODE : stm32f4xx_hal_usart.h
  • IS_USART_NACK_STATE : stm32f4xx_hal_usart.h
  • IS_USART_PARITY : stm32f4xx_hal_usart.h
  • IS_USART_PHASE : stm32f4xx_hal_usart.h
  • IS_USART_POLARITY : stm32f4xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f4xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f4xx_hal_usart.h
  • IS_VOLTAGERANGE : stm32f4xx_hal_flash_ex.h
  • IS_WRPSTATE : stm32f4xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f4xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f4xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f4xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f4xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f4xx_hal_iwdg.h
  • IWDG_FLAG_PVU : stm32f4xx_hal_iwdg.h
  • IWDG_FLAG_RVU : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f4xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f4xx_hal_iwdg.h
  • IWDG_TIMEOUT_FLAG : stm32f4xx_hal_iwdg.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- l -

  • LPLVDS_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32f4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32f4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32f4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32f4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32f4xx_hal_lptim.h
  • LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32f4xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32f4xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32f4xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32f4xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32f4xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32f4xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32f4xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32f4xx_hal_lptim.h
  • LPTIM_IT_UP : stm32f4xx_hal_lptim.h
  • LPTIM_OP_PAD_AF : stm32f4xx_hal_lptim.h
  • LPTIM_OP_PAD_PA4 : stm32f4xx_hal_lptim.h
  • LPTIM_OP_PAD_PB9 : stm32f4xx_hal_lptim.h
  • LPTIM_OP_TIM_DAC : stm32f4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32f4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32f4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32f4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32f4xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32f4xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32f4xx_hal_lptim.h
  • LSE_STARTUP_TIMEOUT : stm32f4xx_hal_conf.h
  • LSE_VALUE : stm32f4xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • LSI_VALUE : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- m -

  • MAC_ADDR0 : stm32f4xx_hal_conf.h
  • MAC_ADDR1 : stm32f4xx_hal_conf.h
  • MAC_ADDR2 : stm32f4xx_hal_conf.h
  • MAC_ADDR3 : stm32f4xx_hal_conf.h
  • MAC_ADDR4 : stm32f4xx_hal_conf.h
  • MAC_ADDR5 : stm32f4xx_hal_conf.h
  • MAX_NBYTE_SIZE : stm32f4xx_hal_fmpi2c.c
  • MCO1_GPIO_PORT : stm32f4xx_hal_rcc.c
  • MCO1_PIN : stm32f4xx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32f4xx_hal_rcc.c
  • MCO2_PIN : stm32f4xx_hal_rcc.c
  • MEMRMP_OFFSET : stm32f4xx_hal.c
  • MPU_ACCESS_BUFFERABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32f4xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32f4xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32f4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32f4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32f4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32f4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32f4xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32f4xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32f4xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32f4xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32f4xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32f4xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32f4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32f4xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32f4xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32f4xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32f4xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32f4xx_hal_cortex.h
  • MRLVDS_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- n -

  • NVIC_PRIORITYGROUP_0 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f4xx_hal_cortex.h
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STM32F410Rx HAL User Manual: Globals

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- o -

  • OB_BOR_LEVEL1 : stm32f4xx_hal_flash_ex.h
  • OB_BOR_LEVEL2 : stm32f4xx_hal_flash_ex.h
  • OB_BOR_LEVEL3 : stm32f4xx_hal_flash_ex.h
  • OB_BOR_OFF : stm32f4xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f4xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_DESELECTED : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_0 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_1 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_2 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_3 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_4 : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SECTOR_All : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_SELECTED : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_STATE_DISABLE : stm32f4xx_hal_flash_ex.h
  • OB_PCROP_STATE_ENABLE : stm32f4xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f4xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f4xx_hal_flash_ex.h
  • OB_RDP_LEVEL_2 : stm32f4xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f4xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f4xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f4xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_0 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_1 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_2 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_3 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_4 : stm32f4xx_hal_flash_ex.h
  • OB_WRP_SECTOR_All : stm32f4xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f4xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f4xx_hal_flash_ex.h
  • ODEN_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
  • ODSWEN_BIT_NUMBER : stm32f4xx_hal_pwr_ex.h
  • OPTCR_BYTE0_ADDRESS : stm32f4xx_hal_flash.h
  • OPTCR_BYTE1_ADDRESS : stm32f4xx_hal_flash.h
  • OPTCR_BYTE2_ADDRESS : stm32f4xx_hal_flash.h
  • OPTCR_BYTE3_ADDRESS : stm32f4xx_hal_flash.h
  • OPTIONBYTE_BOR : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_PCROP : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f4xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f4xx_hal_flash_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- p -

  • PHY_AUTONEGO_COMPLETE : stm32f4xx_hal_conf.h
  • PHY_AUTONEGOTIATION : stm32f4xx_hal_conf.h
  • PHY_BCR : stm32f4xx_hal_conf.h
  • PHY_BSR : stm32f4xx_hal_conf.h
  • PHY_CONFIG_DELAY : stm32f4xx_hal_conf.h
  • PHY_DUPLEX_STATUS : stm32f4xx_hal_conf.h
  • PHY_FULLDUPLEX_100M : stm32f4xx_hal_conf.h
  • PHY_FULLDUPLEX_10M : stm32f4xx_hal_conf.h
  • PHY_HALFDUPLEX_100M : stm32f4xx_hal_conf.h
  • PHY_HALFDUPLEX_10M : stm32f4xx_hal_conf.h
  • PHY_ISOLATE : stm32f4xx_hal_conf.h
  • PHY_JABBER_DETECTION : stm32f4xx_hal_conf.h
  • PHY_LINK_INTERRUPT : stm32f4xx_hal_conf.h
  • PHY_LINK_STATUS : stm32f4xx_hal_conf.h
  • PHY_LINKED_STATUS : stm32f4xx_hal_conf.h
  • PHY_LOOPBACK : stm32f4xx_hal_conf.h
  • PHY_MICR : stm32f4xx_hal_conf.h
  • PHY_MICR_INT_EN : stm32f4xx_hal_conf.h
  • PHY_MICR_INT_OE : stm32f4xx_hal_conf.h
  • PHY_MISR : stm32f4xx_hal_conf.h
  • PHY_MISR_LINK_INT_EN : stm32f4xx_hal_conf.h
  • PHY_POWERDOWN : stm32f4xx_hal_conf.h
  • PHY_READ_TO : stm32f4xx_hal_conf.h
  • PHY_RESET : stm32f4xx_hal_conf.h
  • PHY_RESET_DELAY : stm32f4xx_hal_conf.h
  • PHY_RESTART_AUTONEGOTIATION : stm32f4xx_hal_conf.h
  • PHY_SPEED_STATUS : stm32f4xx_hal_conf.h
  • PHY_SR : stm32f4xx_hal_conf.h
  • PHY_WRITE_TO : stm32f4xx_hal_conf.h
  • PLL_TIMEOUT_VALUE : stm32f4xx_hal_rcc_ex.h
  • PMODE_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • PREFETCH_ENABLE : stm32f4xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f4xx_hal_pwr.c
  • PVD_MODE_EVT : stm32f4xx_hal_pwr.c
  • PVD_MODE_IT : stm32f4xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32f4xx_hal_pwr.c
  • PVDE_BIT_NUMBER : stm32f4xx_hal_pwr.h
  • PWR_BKPREG_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_CR_OFFSET : stm32f4xx_hal_pwr.h
  • PWR_CR_OFFSET_BB : stm32f4xx_hal_pwr.h
  • PWR_CSR_OFFSET : stm32f4xx_hal_pwr.h
  • PWR_CSR_OFFSET_BB : stm32f4xx_hal_pwr.h
  • PWR_EXTI_LINE_PVD : stm32f4xx_hal_pwr.h
  • PWR_FLAG_BRR : stm32f4xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32f4xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f4xx_hal_pwr.h
  • PWR_FLAG_VOSRDY : stm32f4xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f4xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f4xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32f4xx_hal_pwr.h
  • PWR_OFFSET : stm32f4xx_hal_pwr.h
  • PWR_OVERDRIVE_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f4xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32f4xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32f4xx_hal_pwr.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32f4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32f4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE3 : stm32f4xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32f4xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f4xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f4xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f4xx_hal_pwr.h
  • PWR_UDERDRIVE_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_VOSRDY_TIMEOUT_VALUE : stm32f4xx_hal_pwr_ex.c
  • PWR_WAKEUP_PIN1 : stm32f4xx_hal_pwr.h
  • PWR_WAKEUP_PIN2 : stm32f4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32f4xx_hal_pwr_ex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- r -

  • RCC_BDCR_BDRST_BB : stm32f4xx_hal_rcc.h
  • RCC_BDCR_BYTE0_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_BDCR_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_BDCR_RTCEN_BB : stm32f4xx_hal_rcc.h
  • RCC_BDRST_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_CFGR_MCO1EN_BB : stm32f4xx_hal_rcc_ex.h
  • RCC_CFGR_MCO2EN_BB : stm32f4xx_hal_rcc_ex.h
  • RCC_CFGR_OFFSET : stm32f4xx_hal_rcc_ex.h
  • RCC_CIR_BYTE1_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f4xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f4xx_hal_rcc.h
  • RCC_CR_BYTE2_ADDRESS : stm32f4xx_hal_rcc.h
  • RCC_CR_CSSON_BB : stm32f4xx_hal_rcc.h
  • RCC_CR_HSION_BB : stm32f4xx_hal_rcc.h
  • RCC_CR_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_CR_PLLON_BB : stm32f4xx_hal_rcc.h
  • RCC_CSR_LSION_BB : stm32f4xx_hal_rcc.h
  • RCC_CSR_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_CSSON_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • RCC_DCKCFGR_OFFSET : stm32f4xx_hal_rcc_ex.h
  • RCC_DCKCFGR_TIMPRE_BB : stm32f4xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PLLI2SRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f4xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f4xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f4xx_hal_rcc.h
  • RCC_FMPI2C1CLKSOURCE_APB : stm32f4xx_hal_rcc_ex.h
  • RCC_FMPI2C1CLKSOURCE_HSI : stm32f4xx_hal_rcc_ex.h
  • RCC_FMPI2C1CLKSOURCE_SYSCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_HCLK_DIV1 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f4xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f4xx_hal_rcc.h
  • RCC_HSE_ON : stm32f4xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f4xx_hal_rcc.h
  • RCC_HSI_ON : stm32f4xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32f4xx_hal_rcc.h
  • RCC_HSION_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_I2SAPBCLKSOURCE_EXT : stm32f4xx_hal_rcc_ex.h
  • RCC_I2SAPBCLKSOURCE_PLLR : stm32f4xx_hal_rcc_ex.h
  • RCC_I2SAPBCLKSOURCE_PLLSRC : stm32f4xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32f4xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f4xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f4xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f4xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f4xx_hal_rcc.h
  • RCC_IT_PLLI2SRDY : stm32f4xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f4xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32f4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32f4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32f4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32f4xx_hal_rcc.h
  • RCC_LSE_HIGHDRIVE_MODE : stm32f4xx_hal_rcc_ex.h
  • RCC_LSE_LOWPOWER_MODE : stm32f4xx_hal_rcc_ex.h
  • RCC_LSE_OFF : stm32f4xx_hal_rcc.h
  • RCC_LSE_ON : stm32f4xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f4xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f4xx_hal_rcc.h
  • RCC_LSI_ON : stm32f4xx_hal_rcc.h
  • RCC_LSION_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_MCO1 : stm32f4xx_hal_rcc.h
  • RCC_MCO1EN_BIT_NUMBER : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_HSE : stm32f4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32f4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32f4xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32f4xx_hal_rcc.h
  • RCC_MCO2 : stm32f4xx_hal_rcc.h
  • RCC_MCO2EN_BIT_NUMBER : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_HSE : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_I2SCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_PLLCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_MCO2SOURCE_SYSCLK : stm32f4xx_hal_rcc_ex.h
  • RCC_MCODIV_1 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_3 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32f4xx_hal_rcc.h
  • RCC_MCODIV_5 : stm32f4xx_hal_rcc.h
  • RCC_OFFSET : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f4xx_hal_rcc.h
  • RCC_PERIPHCLK_FMPI2C1 : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2S : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_TIM : stm32f4xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32f4xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f4xx_hal_rcc.h
  • RCC_PLL_ON : stm32f4xx_hal_rcc.h
  • RCC_PLLON_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32f4xx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32f4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV10 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV11 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV12 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV13 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV14 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV15 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV16 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV17 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV18 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV19 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV20 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV21 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV22 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV23 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV24 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV25 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV26 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV27 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV28 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV29 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV3 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV30 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV31 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV5 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV6 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV7 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV9 : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f4xx_hal_rcc.h
  • RCC_RTCEN_BIT_NUMBER : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLRCLK : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLRCLK : stm32f4xx_hal_rcc.h
  • RCC_TIMPRE_BIT_NUMBER : stm32f4xx_hal_rcc_ex.h
  • RCC_TIMPRES_ACTIVATED : stm32f4xx_hal_rcc_ex.h
  • RCC_TIMPRES_DESACTIVATED : stm32f4xx_hal_rcc_ex.h
  • RDP_KEY : stm32f4xx_hal_flash.h
  • RISING_EDGE : stm32f4xx_hal_gpio.c
  • RNG_FLAG_CECS : stm32f4xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32f4xx_hal_rng.h
  • RNG_FLAG_SECS : stm32f4xx_hal_rng.h
  • RNG_IT_CEI : stm32f4xx_hal_rng.h
  • RNG_IT_DRDY : stm32f4xx_hal_rng.h
  • RNG_IT_SEI : stm32f4xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32f4xx_hal_rng.c
  • RTC_ALARM_A : stm32f4xx_hal_rtc.h
  • RTC_ALARM_B : stm32f4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32f4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32f4xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32f4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32f4xx_hal_rtc.h
  • RTC_BKP_DR0 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f4xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32f4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32f4xx_hal_rtc_ex.h
  • RTC_CALIBSIGN_NEGATIVE : stm32f4xx_hal_rtc_ex.h
  • RTC_CALIBSIGN_POSITIVE : stm32f4xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32f4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32f4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32f4xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32f4xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f4xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32f4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32f4xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32f4xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32f4xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32f4xx_hal_rtc.h
  • RTC_FLAGS_MASK : stm32f4xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f4xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32f4xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32f4xx_hal_rtc.h
  • RTC_INIT_MASK : stm32f4xx_hal_rtc.h
  • RTC_IT_ALRA : stm32f4xx_hal_rtc.h
  • RTC_IT_ALRB : stm32f4xx_hal_rtc.h
  • RTC_IT_TAMP : stm32f4xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f4xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32f4xx_hal_rtc.h
  • RTC_IT_TS : stm32f4xx_hal_rtc.h
  • RTC_IT_WUT : stm32f4xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f4xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f4xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f4xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f4xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f4xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f4xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f4xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f4xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_ALARMA : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_ALARMB : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_DISABLE : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32f4xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32f4xx_hal_rtc.h
  • RTC_RSF_MASK : stm32f4xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32f4xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32f4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32f4xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32f4xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32f4xx_hal_rtc.h
  • RTC_TAMPER_1 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPIN_DEFAULT : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPIN_POS1 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f4xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32f4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_POS1 : stm32f4xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32f4xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32f4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32f4xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f4xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f4xx_hal_rtc.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- s -

  • SlaveAddr_MSK : stm32f4xx_hal_fmpi2c.c
  • SlaveAddr_SHIFT : stm32f4xx_hal_fmpi2c.c
  • SMARTCARD_BRR : stm32f4xx_hal_smartcard.h
  • SMARTCARD_CR1_REG_INDEX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_CR3_REG_INDEX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DIV : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DIVFRAQ : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DIVMANT : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_RX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_TX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_FE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f4xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f4xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f4xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV10 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV12 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV14 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV16 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV18 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV2 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV20 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV22 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV24 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV26 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV28 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV30 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV32 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV34 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV36 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV38 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV4 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV40 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV42 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV44 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV46 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV48 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV50 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV52 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV54 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV56 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV58 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV6 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV60 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV62 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV8 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_0_5 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32f4xx_hal_smartcard.h
  • SMARTCARD_WORDLENGTH_9B : stm32f4xx_hal_smartcard.h
  • SPI_1LINE_RX : stm32f4xx_hal_spi.h
  • SPI_1LINE_TX : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f4xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32f4xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f4xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f4xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f4xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f4xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f4xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f4xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f4xx_hal_spi.h
  • SPI_FIRSTBIT_LSB : stm32f4xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f4xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f4xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f4xx_hal_spi.h
  • SPI_FLAG_FRE : stm32f4xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f4xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f4xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f4xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f4xx_hal_spi.h
  • SPI_IT_ERR : stm32f4xx_hal_spi.h
  • SPI_IT_RXNE : stm32f4xx_hal_spi.h
  • SPI_IT_TXE : stm32f4xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f4xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f4xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f4xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f4xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f4xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f4xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f4xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f4xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f4xx_hal_spi.h
  • SPI_RESET_CRC : stm32f4xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32f4xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32f4xx_hal_spi.h
  • SYSCFG_OFFSET : stm32f4xx_hal.c
  • SYSTICK_CLKSOURCE_HCLK : stm32f4xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f4xx_hal_cortex.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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- t -

  • TICK_INT_PRIORITY : stm32f4xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f4xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f4xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32f4xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f4xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f4xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f4xx_hal_tim.h
  • TIM_CCER_CCxE_MASK : stm32f4xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f4xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f4xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f4xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32f4xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32f4xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f4xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f4xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f4xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f4xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f4xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f4xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f4xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f4xx_hal_tim.h
  • TIM_DMA_COM : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f4xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f4xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32f4xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32f4xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_OR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32f4xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32f4xx_hal_tim.h
  • TIM_DMABASE_SR : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f4xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32f4xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f4xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f4xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32f4xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f4xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f4xx_hal_tim.h
  • TIM_FLAG_COM : stm32f4xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f4xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f4xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f4xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f4xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f4xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_IT_BREAK : stm32f4xx_hal_tim.h
  • TIM_IT_CC1 : stm32f4xx_hal_tim.h
  • TIM_IT_CC2 : stm32f4xx_hal_tim.h
  • TIM_IT_CC3 : stm32f4xx_hal_tim.h
  • TIM_IT_CC4 : stm32f4xx_hal_tim.h
  • TIM_IT_COM : stm32f4xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f4xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32f4xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f4xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f4xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f4xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32f4xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f4xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f4xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f4xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32f4xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32f4xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32f4xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32f4xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32f4xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32f4xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f4xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f4xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f4xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f4xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f4xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f4xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f4xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f4xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f4xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f4xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f4xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f4xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f4xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f4xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32f4xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32f4xx_hal_tim.h
  • TIM_SYSTEMBREAKINPUT_HARDFAULT : stm32f4xx_hal_tim_ex.h
  • TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD : stm32f4xx_hal_tim_ex.h
  • TIM_SYSTEMBREAKINPUT_PVD : stm32f4xx_hal_tim_ex.h
  • TIM_TI1SELECTION_CH1 : stm32f4xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f4xx_hal_tim.h
  • TIM_TIM11_GPIO : stm32f4xx_hal_tim_ex.h
  • TIM_TIM11_HSE : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_ETH_PTP : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_TIM8_TRGO : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_USBFS_SOF : stm32f4xx_hal_tim_ex.h
  • TIM_TIM2_USBHS_SOF : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_GPIO : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_LSE : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_LSI : stm32f4xx_hal_tim_ex.h
  • TIM_TIM5_RTC : stm32f4xx_hal_tim_ex.h
  • TIM_TRGO_ENABLE : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f4xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f4xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f4xx_hal_tim.h
  • TIM_TS_ETRF : stm32f4xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f4xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f4xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f4xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f4xx_hal_tim.h
  • TIM_TS_NONE : stm32f4xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f4xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f4xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f4xx_hal_tim.h
  • TIMING_CLEAR_MASK : stm32f4xx_hal_fmpi2c.c
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- u -

  • UART_BRR_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_BRR_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_CR1_REG_INDEX : stm32f4xx_hal_uart.h
  • UART_CR2_REG_INDEX : stm32f4xx_hal_uart.h
  • UART_CR3_REG_INDEX : stm32f4xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_DIVMANT_SAMPLING16 : stm32f4xx_hal_uart.h
  • UART_DIVMANT_SAMPLING8 : stm32f4xx_hal_uart.h
  • UART_FLAG_CTS : stm32f4xx_hal_uart.h
  • UART_FLAG_FE : stm32f4xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f4xx_hal_uart.h
  • UART_FLAG_LBD : stm32f4xx_hal_uart.h
  • UART_FLAG_NE : stm32f4xx_hal_uart.h
  • UART_FLAG_ORE : stm32f4xx_hal_uart.h
  • UART_FLAG_PE : stm32f4xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f4xx_hal_uart.h
  • UART_FLAG_TC : stm32f4xx_hal_uart.h
  • UART_FLAG_TXE : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f4xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f4xx_hal_uart.h
  • UART_IT_CTS : stm32f4xx_hal_uart.h
  • UART_IT_ERR : stm32f4xx_hal_uart.h
  • UART_IT_IDLE : stm32f4xx_hal_uart.h
  • UART_IT_LBD : stm32f4xx_hal_uart.h
  • UART_IT_MASK : stm32f4xx_hal_uart.h
  • UART_IT_PE : stm32f4xx_hal_uart.h
  • UART_IT_RXNE : stm32f4xx_hal_uart.h
  • UART_IT_TC : stm32f4xx_hal_uart.h
  • UART_IT_TXE : stm32f4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f4xx_hal_uart.h
  • UART_MODE_RX : stm32f4xx_hal_uart.h
  • UART_MODE_TX : stm32f4xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f4xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f4xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32f4xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f4xx_hal_uart.h
  • UART_PARITY_NONE : stm32f4xx_hal_uart.h
  • UART_PARITY_ODD : stm32f4xx_hal_uart.h
  • UART_STATE_DISABLE : stm32f4xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f4xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f4xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f4xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f4xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f4xx_hal_uart.h
  • UART_WORDLENGTH_8B : stm32f4xx_hal_uart.h
  • UART_WORDLENGTH_9B : stm32f4xx_hal_uart.h
  • UFB_MODE_BB : stm32f4xx_hal.c
  • UFB_MODE_BIT_NUMBER : stm32f4xx_hal.c
  • USART_BRR : stm32f4xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f4xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f4xx_hal_usart.h
  • USART_CR1_REG_INDEX : stm32f4xx_hal_usart.h
  • USART_CR2_REG_INDEX : stm32f4xx_hal_usart.h
  • USART_CR3_REG_INDEX : stm32f4xx_hal_usart.h
  • USART_DIV : stm32f4xx_hal_usart.h
  • USART_DIVFRAQ : stm32f4xx_hal_usart.h
  • USART_DIVMANT : stm32f4xx_hal_usart.h
  • USART_FLAG_FE : stm32f4xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f4xx_hal_usart.h
  • USART_FLAG_NE : stm32f4xx_hal_usart.h
  • USART_FLAG_ORE : stm32f4xx_hal_usart.h
  • USART_FLAG_PE : stm32f4xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f4xx_hal_usart.h
  • USART_FLAG_TC : stm32f4xx_hal_usart.h
  • USART_FLAG_TXE : stm32f4xx_hal_usart.h
  • USART_IT_CTS : stm32f4xx_hal_usart.h
  • USART_IT_ERR : stm32f4xx_hal_usart.h
  • USART_IT_IDLE : stm32f4xx_hal_usart.h
  • USART_IT_LBD : stm32f4xx_hal_usart.h
  • USART_IT_MASK : stm32f4xx_hal_usart.h
  • USART_IT_PE : stm32f4xx_hal_usart.h
  • USART_IT_RXNE : stm32f4xx_hal_usart.h
  • USART_IT_TC : stm32f4xx_hal_usart.h
  • USART_IT_TXE : stm32f4xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f4xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f4xx_hal_usart.h
  • USART_MODE_RX : stm32f4xx_hal_usart.h
  • USART_MODE_TX : stm32f4xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f4xx_hal_usart.h
  • USART_NACK_DISABLE : stm32f4xx_hal_usart.h
  • USART_NACK_ENABLE : stm32f4xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f4xx_hal_usart.h
  • USART_PARITY_NONE : stm32f4xx_hal_usart.h
  • USART_PARITY_ODD : stm32f4xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f4xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f4xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f4xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f4xx_hal_usart.h
  • USART_STOPBITS_0_5 : stm32f4xx_hal_usart.h
  • USART_STOPBITS_1 : stm32f4xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f4xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f4xx_hal_usart.h
  • USART_TIMEOUT_VALUE : stm32f4xx_hal_usart.c
  • USART_WORDLENGTH_8B : stm32f4xx_hal_usart.h
  • USART_WORDLENGTH_9B : stm32f4xx_hal_usart.h
  • USE_RTOS : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- v -

  • VDD_VALUE : stm32f4xx_hal_conf.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Globals

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- w -

  • WWDG_CFR_BASE : stm32f4xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32f4xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f4xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f4xx_hal_wwdg.h
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal.h File Reference

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  • Drivers
  • STM32F4xx_HAL_Driver
  • Inc
Defines | Functions
stm32f4xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32f4xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define | __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define | __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define | __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
#define | __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM()
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK()
SYSCFG Break Lockup lock Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK()
SYSCFG Break PVD lock Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register.

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc.h File Reference

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Data Structures | Defines | Functions
stm32f4xx_hal_adc.h File Reference

Header file containing functions prototypes of ADC HAL library. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration multi-mode structure definition. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000U)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001U)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U)
#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00U)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02U)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04U)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
#define | ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
#define | ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
#define | ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define | ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define | ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
#define | ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define | ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define | ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
#define | ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
#define | ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#define | ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
#define | ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
#define | ADC_CHANNEL_0 ((uint32_t)0x00000000U)
#define | ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
#define | ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
#define | ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
#define | ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
#define | ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define | ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define | ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
#define | ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
#define | ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
#define | ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
#define | ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
#define | ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
#define | ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U)
#define | ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
#define | ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define | ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define | ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define | ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
#define | ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
#define | ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
#define | ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
#define | ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
#define | ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
#define | ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
#define | ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
#define | ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U)
#define | ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Check if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clear the ADC's pending flags.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | ADC_STAB_DELAY_US ((uint32_t) 3U)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
#define | IS_ADC_SAMPLING_DELAY(DELAY)
#define | IS_ADC_RESOLUTION(RESOLUTION)
#define | IS_ADC_EXT_TRIG_EDGE(EDGE)
#define | IS_ADC_EXT_TRIG(REGTRIG)
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_EOCSelection(EOCSelection)
#define | IS_ADC_EVENT_TYPE(EVENT)
#define | IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define | IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE)
#define | IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
#define | IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
#define | IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
#define | IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
#define | IS_ADC_RANGE(RESOLUTION, ADC_VALUE)
#define | ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
Set ADC Regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
Enable ADC scan mode.
#define | ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
Enable the ADC end of conversion selection.
#define | ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
Enable the ADC DMA continuous request.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
Return resolution bits in CR1 register.

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitializes the ADCx peripheral registers to their default reset values.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC and starts conversion of the regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Disables ADC and stop conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for regular conversion complete.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Disables the interrupt and stop ADC conversion of regular channels.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Gets the converted value from data register of regular channel.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion half DMA transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
Error ADC callback.
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

Header file containing functions prototypes of ADC HAL library.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_adc.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc_ex.h File Reference

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stm32f4xx_hal_adc_ex.h File Reference

Header file of ADC HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
struct | ADC_MultiModeTypeDef
ADC Configuration multi-mode structure definition. More...

Defines

#define | ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
#define | ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
#define | ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
#define | ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U)
#define | ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0)
#define | ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1)
#define | ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
#define | ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000U)
#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)
#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)
#define | ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
#define | IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
#define | IS_ADC_MODE(MODE)
#define | IS_ADC_DMA_ACCESS_MODE(MODE)
#define | IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE)
#define | IS_ADC_EXT_INJEC_TRIG(INJTRIG)
#define | IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
#define | IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
#define | ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
Set the selected injected Channel rank.

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables the selected ADC software start conversion of the injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for injected conversion complete.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Gets the converted value from data register of injected channel.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Configures the ADC multi-mode.

Detailed Description

Header file of ADC HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_adc_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cortex.h File Reference

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stm32f4xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U)
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
#define | MPU_REGION_ENABLE ((uint8_t)0x01U)
#define | MPU_REGION_DISABLE ((uint8_t)0x00U)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02U)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07U)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
__STATIC_INLINE void | HAL_MPU_Disable (void)
Disables the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enables the MPU.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cortex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_crc.h File Reference

  • File List
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stm32f4xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CRC_HandleTypeDef

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Resets CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Resets CRC Data Register.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Stores a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 8-bit data stored in the Independent Data(ID) register.

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Returns the CRC state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_crc.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac.h File Reference

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stm32f4xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U
#define | HAL_DAC_ERROR_DMA 0x04U
#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000U)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))
#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
#define | DAC_CHANNEL_1 ((uint32_t)0x00000000U)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010U)
#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified DAC interrupt source is enabled or disabled.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
Set DHR12RD alignment.

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00U, HAL_DAC_STATE_READY = 0x01U, HAL_DAC_STATE_BUSY = 0x02U, HAL_DAC_STATE_TIMEOUT = 0x03U,
HAL_DAC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitializes the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initializes the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitializes the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC state
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.
void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

Header file of DAC HAL module.

Header file of DAC HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dac.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac_ex.h File Reference

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stm32f4xx_hal_dac_ex.h File Reference
#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma.h File Reference

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stm32f4xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
#define | HAL_DMA_ERROR_FE ((uint32_t)0x00000002U)
#define | HAL_DMA_ERROR_DME ((uint32_t)0x00000004U)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
#define | DMA_CHANNEL_0 ((uint32_t)0x00000000U)
#define | DMA_CHANNEL_1 ((uint32_t)0x02000000U)
#define | DMA_CHANNEL_2 ((uint32_t)0x04000000U)
#define | DMA_CHANNEL_3 ((uint32_t)0x06000000U)
#define | DMA_CHANNEL_4 ((uint32_t)0x08000000U)
#define | DMA_CHANNEL_5 ((uint32_t)0x0A000000U)
#define | DMA_CHANNEL_6 ((uint32_t)0x0C000000U)
#define | DMA_CHANNEL_7 ((uint32_t)0x0E000000U)
#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000U)
#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
#define | DMA_NORMAL ((uint32_t)0x00000000U)
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define | DMA_IT_FE ((uint32_t)0x00000080U)
#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Return the current DMA Stream FIFO filled level.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
Enable the specified DMA Stream.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Disable the specified DMA Stream.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream transfer error flag.
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream FIFO error flag.
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)
Return the current DMA Stream direct mode error flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Stream pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Stream pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified DMA Stream interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified DMA Stream interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified DMA Stream interrupt is enabled or disabled.
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Writes the number of data units to be transferred on the DMA Stream.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Returns the number of remaining data units in the current DMAy Streamx transfer.
#define | IS_DMA_CHANNEL(CHANNEL)
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)
#define | IS_DMA_FIFO_MODE_STATE(STATE)
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD)
#define | IS_DMA_MEMORY_BURST(BURST)
#define | IS_DMA_PERIPHERAL_BURST(BURST)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_READY_MEM0 = 0x11U, HAL_DMA_STATE_READY_MEM1 = 0x21U,
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31U, HAL_DMA_STATE_READY_HALF_MEM1 = 0x41U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_BUSY_MEM0 = 0x12U,
HAL_DMA_STATE_BUSY_MEM1 = 0x22U, HAL_DMA_STATE_TIMEOUT = 0x03U, HAL_DMA_STATE_ERROR = 0x04U
}
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dma.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
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Enumerations | Functions
stm32f4xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | HAL_DMA_MemoryTypeDef { MEMORY0 = 0x00U, MEMORY1 = 0x01U }
HAL DMA Memory definition. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dma_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash.h File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f4xx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_flash_ex.h"
#include "stm32f4xx_hal_flash_ramfunc.h"

Go to the source code of this file.

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FLASH_ERROR_RD ((uint32_t)0x00000001U)
#define | HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U)
#define | HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U)
#define | HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U)
#define | HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U)
#define | FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U)
#define | FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U)
#define | FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U)
#define | FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U)
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_SOP
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_PGPERR FLASH_SR_PGPERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_RDERR ((uint32_t)0x00000100U)
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR ((uint32_t)0x02000000U)
#define | FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define | FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U)
#define | FLASH_PSIZE_WORD ((uint32_t)0x00000200U)
#define | FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U)
#define | CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)
#define | RDP_KEY ((uint16_t)0x00A5U)
#define | FLASH_KEY1 ((uint32_t)0x45670123U)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define | FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define | FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Resets the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Resets the FLASH data Cache.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))==(__FLAG__))
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
Clear the specified FLASH flag.
#define | ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00U)
ACR register byte 0 (Bits[7:0]) base address.
#define | OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14U)
OPTCR register byte 0 (Bits[7:0]) base address.
#define | OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15U)
OPTCR register byte 1 (Bits[15:8]) base address.
#define | OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16U)
OPTCR register byte 2 (Bits[23:16]) base address.
#define | OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17U)
OPTCR register byte 3 (Bits[31:24]) base address.
#define | IS_FLASH_TYPEPROGRAM(VALUE)

Enumerations

enum | FLASH_ProcedureTypeDef { FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM }
FLASH Procedure structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_flash.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ex.h File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f4xx_hal_flash_ex.h File Reference

Header file of FLASH HAL Extension module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_AdvOBProgramInitTypeDef
FLASH Advanced Option Bytes Program structure definition. More...

Defines

#define | FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U)
#define | FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U)
#define | FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U)
#define | FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U)
#define | FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U)
#define | OB_WRPSTATE_DISABLE ((uint32_t)0x00U)
#define | OB_WRPSTATE_ENABLE ((uint32_t)0x01U)
#define | OPTIONBYTE_WRP ((uint32_t)0x01U)
#define | OPTIONBYTE_RDP ((uint32_t)0x02U)
#define | OPTIONBYTE_USER ((uint32_t)0x04U)
#define | OPTIONBYTE_BOR ((uint32_t)0x08U)
#define | OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define | OB_RDP_LEVEL_1 ((uint8_t)0x55U)
#define | OB_RDP_LEVEL_2 ((uint8_t)0xCCU)
#define | OB_IWDG_SW ((uint8_t)0x20U)
#define | OB_IWDG_HW ((uint8_t)0x00U)
#define | OB_STOP_NO_RST ((uint8_t)0x40U)
#define | OB_STOP_RST ((uint8_t)0x00U)
#define | OB_STDBY_NO_RST ((uint8_t)0x80U)
#define | OB_STDBY_RST ((uint8_t)0x00U)
#define | OB_BOR_LEVEL3 ((uint8_t)0x00U)
#define | OB_BOR_LEVEL2 ((uint8_t)0x04U)
#define | OB_BOR_LEVEL1 ((uint8_t)0x08U)
#define | OB_BOR_OFF ((uint8_t)0x0CU)
#define | OB_PCROP_STATE_DISABLE ((uint32_t)0x00U)
#define | OB_PCROP_STATE_ENABLE ((uint32_t)0x01U)
#define | OPTIONBYTE_PCROP ((uint32_t)0x01U)
#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
#define | FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
#define | FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
#define | FLASH_BANK_1 ((uint32_t)1U)
#define | FLASH_MER_BIT (FLASH_CR_MER)
#define | FLASH_SECTOR_0 ((uint32_t)0U)
#define | FLASH_SECTOR_1 ((uint32_t)1U)
#define | FLASH_SECTOR_2 ((uint32_t)2U)
#define | FLASH_SECTOR_3 ((uint32_t)3U)
#define | FLASH_SECTOR_4 ((uint32_t)4U)
#define | OB_WRP_SECTOR_0 ((uint32_t)0x00000001U)
#define | OB_WRP_SECTOR_1 ((uint32_t)0x00000002U)
#define | OB_WRP_SECTOR_2 ((uint32_t)0x00000004U)
#define | OB_WRP_SECTOR_3 ((uint32_t)0x00000008U)
#define | OB_WRP_SECTOR_4 ((uint32_t)0x00000010U)
#define | OB_WRP_SECTOR_All ((uint32_t)0x00000FFFU)
#define | OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U)
#define | OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U)
#define | OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U)
#define | OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U)
#define | OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U)
#define | OB_PCROP_SECTOR_All ((uint32_t)0x00000FFFU)
#define | OB_PCROP_DESELECTED ((uint8_t)0x00U)
#define | OB_PCROP_SELECTED ((uint8_t)0x80U)
#define | FLASH_SECTOR_TOTAL 5U
#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_VOLTAGERANGE(RANGE)
#define | IS_WRPSTATE(VALUE)
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_OB_BOR_LEVEL(LEVEL)
#define | IS_PCROPSTATE(VALUE)
#define | IS_OBEX(VALUE) (((VALUE) == OPTIONBYTE_PCROP))
#define | IS_FLASH_LATENCY(LATENCY)
#define | IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#define | IS_FLASH_SECTOR(SECTOR)
#define | IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define | IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define | IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define | IS_OB_PCROP(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define | IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
Program option bytes.
void | HAL_FLASHEx_AdvOBGetConfig (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
Get the OBEX byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_OB_SelectPCROP (void)
Select the Protection Mode.
HAL_StatusTypeDef | HAL_FLASHEx_OB_DeSelectPCROP (void)
Deselect the Protection Mode.
void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.

Detailed Description

Header file of FLASH HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_flash_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ramfunc.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_flash_ramfunc.h File Reference

Header file of FLASH RAMFUNC driver. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Functions

__RAM_FUNC | HAL_FLASHEx_StopFlashInterfaceClk (void)
Stop the flash interface while System Run.
__RAM_FUNC | HAL_FLASHEx_StartFlashInterfaceClk (void)
Start the flash interface while System Run.
__RAM_FUNC | HAL_FLASHEx_EnableFlashSleepMode (void)
Enable the flash sleep while System Run.
__RAM_FUNC | HAL_FLASHEx_DisableFlashSleepMode (void)
Disable the flash sleep while System Run.

Detailed Description

Header file of FLASH RAMFUNC driver.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_flash_ramfunc.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c.h File Reference

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stm32f4xx_hal_fmpi2c.h File Reference

Header file of FMPI2C HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_fmpi2c_ex.h"

Go to the source code of this file.

Data Structures

struct | FMPI2C_InitTypeDef
struct | FMPI2C_HandleTypeDef

Defines

#define | HAL_FMPI2C_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_FMPI2C_ERROR_BERR ((uint32_t)0x00000001U)
#define | HAL_FMPI2C_ERROR_ARLO ((uint32_t)0x00000002U)
#define | HAL_FMPI2C_ERROR_AF ((uint32_t)0x00000004U)
#define | HAL_FMPI2C_ERROR_OVR ((uint32_t)0x00000008U)
#define | HAL_FMPI2C_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_FMPI2C_ERROR_TIMEOUT ((uint32_t)0x00000020U)
#define | HAL_FMPI2C_ERROR_SIZE ((uint32_t)0x00000040U)
#define | FMPI2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)
#define | FMPI2C_FIRST_FRAME ((uint32_t)FMPI2C_SOFTEND_MODE)
#define | FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
#define | FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
#define | FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
#define | FMPI2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U)
#define | FMPI2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U)
#define | FMPI2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define | FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
#define | FMPI2C_OA2_NOMASK ((uint8_t)0x00U)
#define | FMPI2C_OA2_MASK01 ((uint8_t)0x01U)
#define | FMPI2C_OA2_MASK02 ((uint8_t)0x02U)
#define | FMPI2C_OA2_MASK03 ((uint8_t)0x03U)
#define | FMPI2C_OA2_MASK04 ((uint8_t)0x04U)
#define | FMPI2C_OA2_MASK05 ((uint8_t)0x05U)
#define | FMPI2C_OA2_MASK06 ((uint8_t)0x06U)
#define | FMPI2C_OA2_MASK07 ((uint8_t)0x07U)
#define | FMPI2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define | FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
#define | FMPI2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define | FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
#define | FMPI2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define | FMPI2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U)
#define | FMPI2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
#define | FMPI2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
#define | FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD
#define | FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND
#define | FMPI2C_SOFTEND_MODE ((uint32_t)0x00000000U)
#define | FMPI2C_NO_STARTSTOP ((uint32_t)0x00000000U)
#define | FMPI2C_GENERATE_STOP FMPI2C_CR2_STOP
#define | FMPI2C_GENERATE_START_READ (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
#define | FMPI2C_GENERATE_START_WRITE FMPI2C_CR2_START
#define | FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE
#define | FMPI2C_IT_TCI FMPI2C_CR1_TCIE
#define | FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE
#define | FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE
#define | FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE
#define | FMPI2C_IT_RXI FMPI2C_CR1_RXIE
#define | FMPI2C_IT_TXI FMPI2C_CR1_TXIE
#define | FMPI2C_IT_TX (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI)
#define | FMPI2C_IT_RX (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI)
#define | FMPI2C_IT_ADDR (FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI)
#define | FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
#define | FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
#define | FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
#define | FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR
#define | FMPI2C_FLAG_AF FMPI2C_ISR_NACKF
#define | FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF
#define | FMPI2C_FLAG_TC FMPI2C_ISR_TC
#define | FMPI2C_FLAG_TCR FMPI2C_ISR_TCR
#define | FMPI2C_FLAG_BERR FMPI2C_ISR_BERR
#define | FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO
#define | FMPI2C_FLAG_OVR FMPI2C_ISR_OVR
#define | FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR
#define | FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
#define | FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT
#define | FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY
#define | FMPI2C_FLAG_DIR FMPI2C_ISR_DIR
#define | __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
Reset FMPI2C handle state.
#define | __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified FMPI2C interrupt.
#define | __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified FMPI2C interrupt.
#define | __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified FMPI2C interrupt source is enabled or not.
#define | FMPI2C_FLAG_MASK ((uint32_t)0x0001FFFFU)
Check whether the specified FMPI2C flag is set or not.
#define | __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
#define | __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
Enable the specified FMPI2C peripheral.
#define | __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
Disable the specified FMPI2C peripheral.
#define | IS_FMPI2C_ADDRESSING_MODE(MODE)
#define | IS_FMPI2C_DUAL_ADDRESS(ADDRESS)
#define | IS_FMPI2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_FMPI2C_GENERAL_CALL(CALL)
#define | IS_FMPI2C_NO_STRETCH(STRETCH)
#define | IS_FMPI2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
#define | FMPI2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U)
#define | FMPI2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
#define | FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
#define | FMPI2C_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
#define | FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
#define | FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
#define | IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FFU)
#define | IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | FMPI2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Enumerations

enum HAL_FMPI2C_StateTypeDef {
HAL_FMPI2C_STATE_RESET = 0x00U, HAL_FMPI2C_STATE_READY = 0x20U, HAL_FMPI2C_STATE_BUSY = 0x24U, HAL_FMPI2C_STATE_BUSY_TX = 0x21U,
HAL_FMPI2C_STATE_BUSY_RX = 0x22U, HAL_FMPI2C_STATE_LISTEN = 0x28U, HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, HAL_FMPI2C_STATE_ERROR = 0xE0U
}
enum | HAL_FMPI2C_ModeTypeDef { HAL_FMPI2C_MODE_NONE = 0x00U, HAL_FMPI2C_MODE_MASTER = 0x10U, HAL_FMPI2C_MODE_SLAVE = 0x20U, HAL_FMPI2C_MODE_MEM = 0x40U }
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_FMPI2C_Init (FMPI2C_HandleTypeDef *hfmpi2c)
Initializes the FMPI2C according to the specified parameters in the FMPI2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hfmpi2c)
DeInitialize the FMPI2C peripheral.
__weak void | HAL_FMPI2C_MspInit (FMPI2C_HandleTypeDef *hfmpi2c)
Initialize the FMPI2C MSP.
__weak void | HAL_FMPI2C_MspDeInit (FMPI2C_HandleTypeDef *hfmpi2c)
DeInitialize the FMPI2C MSP.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_IsDeviceReady (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Sequential_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Sequential_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Sequential_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Sequential_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_EnableListen_IT (FMPI2C_HandleTypeDef *hfmpi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_DisableListen_IT (FMPI2C_HandleTypeDef *hfmpi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Abort_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress)
Abort a master/host FMPI2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no blocking mode with DMA from a specific memory address.
void | HAL_FMPI2C_EV_IRQHandler (FMPI2C_HandleTypeDef *hfmpi2c)
This function handles FMPI2C event interrupt request.
void | HAL_FMPI2C_ER_IRQHandler (FMPI2C_HandleTypeDef *hfmpi2c)
This function handles FMPI2C error interrupt request.
__weak void | HAL_FMPI2C_MasterTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Master Tx Transfer completed callback.
__weak void | HAL_FMPI2C_MasterRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Master Rx Transfer completed callback.
__weak void | HAL_FMPI2C_SlaveTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_FMPI2C_SlaveRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_FMPI2C_AddrCallback (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_FMPI2C_ListenCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Listen Complete callback.
__weak void | HAL_FMPI2C_MemTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_FMPI2C_MemRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_FMPI2C_ErrorCallback (FMPI2C_HandleTypeDef *hfmpi2c)
FMPI2C error callback.
HAL_FMPI2C_StateTypeDef | HAL_FMPI2C_GetState (FMPI2C_HandleTypeDef *hfmpi2c)
Return the FMPI2C handle state.
HAL_FMPI2C_ModeTypeDef | HAL_FMPI2C_GetMode (FMPI2C_HandleTypeDef *hfmpi2c)
Returns the FMPI2C Master, Slave, Memory or no mode.
uint32_t | HAL_FMPI2C_GetError (FMPI2C_HandleTypeDef *hfmpi2c)
Return the FMPI2C error code.

Detailed Description

Header file of FMPI2C HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_fmpi2c.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c_ex.h File Reference

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Defines | Functions
stm32f4xx_hal_fmpi2c_ex.h File Reference

Header file of FMPI2C HAL Extended module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | FMPI2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define | FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
#define | FMPI2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL
#define | FMPI2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA
#define | IS_FMPI2C_ANALOG_FILTER(FILTER)
#define | IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_FMPI2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_FMPI2CEx_ConfigAnalogFilter (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter)
Configure FMPI2C Analog noise filter.
HAL_StatusTypeDef | HAL_FMPI2CEx_ConfigDigitalFilter (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
Configure FMPI2C Digital noise filter.
HAL_StatusTypeDef | HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
Enable FMPI2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
Disable FMPI2C wakeup from stop mode.
void | HAL_FMPI2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the FMPI2C fast mode plus driving capability.
void | HAL_FMPI2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the FMPI2C fast mode plus driving capability.

Detailed Description

Header file of FMPI2C HAL Extended module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_fmpi2c_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_gpio.h File Reference

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stm32f4xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT ((uint32_t)0x00000000U)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002U)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012U)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003U)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x10110000U)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U)
#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U)
#define | GPIO_NOPULL ((uint32_t)0x00000000U)
#define | GPIO_PULLUP ((uint32_t)0x00000001U)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002U)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_gpio.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_gpio_ex.h File Reference

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  • STM32F4xx_HAL_Driver
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Defines
stm32f4xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extension module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01U) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_FMPI2C1 ((uint8_t)0x04U) /* FMPI2C1 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
#define | GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_SPI2 ((uint8_t)0x06U) /* I2S2 Alternate Function mapping */
#define | GPIO_AF6_SPI5 ((uint8_t)0x06U) /* SPI5/I2S5 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
#define | GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF9_I2C2 ((uint8_t)0x09U) /* I2C2 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_FMPI2C1 ((uint8_t)0x09U) /* FMPI2C1 Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | GPIO_GET_INDEX(__GPIOx__)
#define | IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U))

Detailed Description

Header file of GPIO HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_gpio_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c.h File Reference

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stm32f4xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
I2C Configuration Structure definition. More...
struct | I2C_HandleTypeDef
I2C handle Structure definition. More...

Defines

#define | HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U)
#define | HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U)
#define | HAL_I2C_ERROR_AF ((uint32_t)0x00000004U)
#define | HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U)
#define | HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U)
#define | I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
#define | I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
#define | I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
#define | I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
#define | I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
#define | I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
#define | I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
#define | I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
#define | I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
#define | I2C_FIRST_FRAME ((uint32_t)0x00000001U)
#define | I2C_NEXT_FRAME ((uint32_t)0x00000002U)
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
#define | I2C_LAST_FRAME ((uint32_t)0x00000008U)
#define | I2C_IT_BUF I2C_CR2_ITBUFEN
#define | I2C_IT_EVT I2C_CR2_ITEVTEN
#define | I2C_IT_ERR I2C_CR2_ITERREN
#define | I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)
#define | I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)
#define | I2C_FLAG_PECERR ((uint32_t)0x00011000U)
#define | I2C_FLAG_OVR ((uint32_t)0x00010800U)
#define | I2C_FLAG_AF ((uint32_t)0x00010400U)
#define | I2C_FLAG_ARLO ((uint32_t)0x00010200U)
#define | I2C_FLAG_BERR ((uint32_t)0x00010100U)
#define | I2C_FLAG_TXE ((uint32_t)0x00010080U)
#define | I2C_FLAG_RXNE ((uint32_t)0x00010040U)
#define | I2C_FLAG_STOPF ((uint32_t)0x00010010U)
#define | I2C_FLAG_ADD10 ((uint32_t)0x00010008U)
#define | I2C_FLAG_BTF ((uint32_t)0x00010004U)
#define | I2C_FLAG_ADDR ((uint32_t)0x00010002U)
#define | I2C_FLAG_SB ((uint32_t)0x00010001U)
#define | I2C_FLAG_DUALF ((uint32_t)0x00100080U)
#define | I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)
#define | I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)
#define | I2C_FLAG_GENCALL ((uint32_t)0x00100010U)
#define | I2C_FLAG_TRA ((uint32_t)0x00100004U)
#define | I2C_FLAG_BUSY ((uint32_t)0x00100002U)
#define | I2C_FLAG_MSL ((uint32_t)0x00100001U)
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2C interrupts.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2C interrupt source is enabled or disabled.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
Checks whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
#define | __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)
Clears the I2C ADDR pending flag.
#define | __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)
Clears the I2C STOPF pending flag.
#define | __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
Enable the I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
Disable the I2C peripheral.
#define | I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
#define | I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
#define | I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
#define | I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
#define | I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
#define | I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)
#define | I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define | I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define | I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
#define | I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | IS_I2C_DUTY_CYCLE(CYCLE)
#define | IS_I2C_ADDRESSING_MODE(ADDRESS)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
HAL State structures definition. More...
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no-blocking mode with DMA from a specific memory address.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callbacks.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callbacks.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callbacks.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callbacks.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callbacks.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Returns the I2C state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2c.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s.h File Reference

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stm32f4xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_i2s_ex.h"

Go to the source code of this file.

Data Structures

struct | I2S_InitTypeDef
I2S Init structure definition. More...
struct | I2S_HandleTypeDef
I2S handle Structure definition. More...

Defines

#define | HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_I2S_ERROR_UDR ((uint32_t)0x00000001U)
#define | HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U)
#define | HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004U)
#define | HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008U)
#define | HAL_I2S_ERROR_FRE ((uint32_t)0x00000010U)
#define | HAL_I2S_ERROR_DMA ((uint32_t)0x00000020U)
#define | I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
#define | I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
#define | I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
#define | I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)
#define | I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
#define | I2S_STANDARD_MSB ((uint32_t)0x00000010U)
#define | I2S_STANDARD_LSB ((uint32_t)0x00000020U)
#define | I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
#define | I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)
#define | I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
#define | I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
#define | I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
#define | I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)
#define | I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define | I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
#define | I2S_AUDIOFREQ_192K ((uint32_t)192000U)
#define | I2S_AUDIOFREQ_96K ((uint32_t)96000U)
#define | I2S_AUDIOFREQ_48K ((uint32_t)48000U)
#define | I2S_AUDIOFREQ_44K ((uint32_t)44100U)
#define | I2S_AUDIOFREQ_32K ((uint32_t)32000U)
#define | I2S_AUDIOFREQ_22K ((uint32_t)22050U)
#define | I2S_AUDIOFREQ_16K ((uint32_t)16000U)
#define | I2S_AUDIOFREQ_11K ((uint32_t)11025U)
#define | I2S_AUDIOFREQ_8K ((uint32_t)8000U)
#define | I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
#define | I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000U)
#define | I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001U)
#define | I2S_CPOL_LOW ((uint32_t)0x00000000U)
#define | I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
#define | I2S_IT_TXE SPI_CR2_TXEIE
#define | I2S_IT_RXNE SPI_CR2_RXNEIE
#define | I2S_IT_ERR SPI_CR2_ERRIE
#define | I2S_FLAG_TXE SPI_SR_TXE
#define | I2S_FLAG_RXNE SPI_SR_RXNE
#define | I2S_FLAG_UDR SPI_SR_UDR
#define | I2S_FLAG_OVR SPI_SR_OVR
#define | I2S_FLAG_FRE SPI_SR_FRE
#define | I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define | I2S_FLAG_BSY SPI_SR_BSY
#define | __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
Reset I2S handle state.
#define | __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
Enable or disable the specified SPI peripheral (in I2S mode).
#define | __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
#define | __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2S interrupts.
#define | __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
#define | __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2S interrupt source is enabled or disabled.
#define | __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Checks whether the specified I2S flag is set or not.
#define | __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)
Clears the I2S OVR pending flag.
#define | __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)
Clears the I2S UDR pending flag.
#define | IS_I2S_MODE(MODE)
#define | IS_I2S_STANDARD(STANDARD)
#define | IS_I2S_DATA_FORMAT(FORMAT)
#define | IS_I2S_MCLK_OUTPUT(OUTPUT)
#define | IS_I2S_AUDIO_FREQ(FREQ)
#define | IS_I2S_FULLDUPLEX_MODE(MODE)
#define | IS_I2S_CPOL(CPOL)

Enumerations

enum HAL_I2S_StateTypeDef {
HAL_I2S_STATE_RESET = 0x00U, HAL_I2S_STATE_READY = 0x01U, HAL_I2S_STATE_BUSY = 0x02U, HAL_I2S_STATE_BUSY_TX = 0x12U,
HAL_I2S_STATE_BUSY_RX = 0x22U, HAL_I2S_STATE_BUSY_TX_RX = 0x32U, HAL_I2S_STATE_TIMEOUT = 0x03U, HAL_I2S_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

__weak HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
__weak void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
__weak HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
This function handles I2S Communication Timeout.
HAL_StatusTypeDef | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2s.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s_ex.h File Reference

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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_i2s_ex.h File Reference

Header file of I2S HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2S_CLOCK_PLLSRC ((uint32_t)0x00000000U)
#define | I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
#define | I2S_CLOCK_PLLR ((uint32_t)0x00000002U)
#define | IS_I2S_CLOCKSOURCE(CLOCK)
#define | I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))

Functions

HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
HAL_StatusTypeDef | HAL_I2SEx_TransmitReceive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
HAL_StatusTypeDef | I2SEx_TransmitReceive_IT (I2S_HandleTypeDef *hi2s)
uint32_t | I2S_GetInputClock (I2S_HandleTypeDef *hi2s)
Get I2S clock Input based on Source clock selection in RCC.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2s_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_irda.h File Reference

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stm32f4xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)
#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | IRDA_PARITY_NONE ((uint32_t)0x00000000U)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000U)
#define | IRDA_FLAG_TXE ((uint32_t)0x00000080U)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040U)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
#define | IRDA_FLAG_IDLE ((uint32_t)0x00000010U)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008U)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004U)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002U)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001U)
#define | IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle gstate & RxState.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushs the IRDA DR register.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables or disables the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Macro to enable the IRDA's one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
Macro to disable the IRDA's one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IRDA_IT_MASK
IRDA interruptions flag mask.
#define | IRDA_CR1_REG_INDEX 1U
#define | IRDA_CR2_REG_INDEX 2U
#define | IRDA_CR3_REG_INDEX 3U
#define | IS_IRDA_WORD_LENGTH(LENGTH)
#define | IS_IRDA_PARITY(PARITY)
#define | IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00000000U))
#define | IS_IRDA_POWERMODE(MODE)
#define | IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
#define | IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
#define | IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | IRDA_BRR(_PCLK_, _BAUD_)

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IARDA error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_irda.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_iwdg.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f4xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_KEY_RELOAD ((uint32_t)0xAAAAU)
#define | IWDG_KEY_ENABLE ((uint32_t)0xCCCCU)
#define | IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555U)
#define | IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000U)
#define | IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU)
#define | IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU)
#define | IWDG_PRESCALER_4 ((uint8_t)0x00U)
#define | IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0))
#define | IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1))
#define | IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2))
#define | IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))
#define | IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))
#define | __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
Reset IWDG handle state.
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enables the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).
#define | __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected IWDG's flag status.
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enables write access to IWDG_PR and IWDG_RLR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disables write access to IWDG_PR and IWDG_RLR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU)

Enumerations

enum HAL_IWDG_StateTypeDef {
HAL_IWDG_STATE_RESET = 0x00U, HAL_IWDG_STATE_READY = 0x01U, HAL_IWDG_STATE_BUSY = 0x02U, HAL_IWDG_STATE_TIMEOUT = 0x03U,
HAL_IWDG_STATE_ERROR = 0x04U
}
IWDG HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.
__weak void | HAL_IWDG_MspInit (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG MSP.
HAL_StatusTypeDef | HAL_IWDG_Start (IWDG_HandleTypeDef *hiwdg)
Starts the IWDG.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refreshes the IWDG.
HAL_IWDG_StateTypeDef | HAL_IWDG_GetState (IWDG_HandleTypeDef *hiwdg)
Returns the IWDG state.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_iwdg.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_lptim.h File Reference

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stm32f4xx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23)
#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | LPTIM_OP_PAD_AF ((uint32_t)0x00000000U)
#define | LPTIM_OP_PAD_PA4 LPTIM_OR_OR_0
#define | LPTIM_OP_PAD_PB9 LPTIM_OR_OR_1
#define | LPTIM_OP_TIM_DAC LPTIM_OR_OR
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable/Disable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Starts the LPTIM peripheral in Continuous or in single mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Writes the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Writes the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Checks whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clears the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified LPTIM interrupt is set or not.
#define | __HAL_LPTIM_OPTR_CONFIG(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->OR = (__VALUE__))
LPTIM Option Register.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the LPTIM Wake-up Timer associated Exti line flag.
#define | __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
#define | IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
#define | IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_lptim.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr.h File Reference

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stm32f4xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_pwr_ex.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_WAKEUP_PIN1 ((uint32_t)0x00000100U)
#define | PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define | PWR_PVDLEVEL_7
#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U)
#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02U)
#define | PWR_FLAG_WU PWR_CSR_WUF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_PVDO PWR_CSR_PVDO
#define | PWR_FLAG_BRR PWR_CSR_BRR
#define | PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
Clear the PWR's pending flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Enable the PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Disable the PVD EXTI Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
checks whether the specified PVD Exti interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD Exti flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Generates a Software interrupt on PVD EXTI line.
#define | PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16)
#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define | PWR_CR_OFFSET 0x00U
#define | PWR_CSR_OFFSET 0x04U
#define | PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define | PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
#define | DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
#define | CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
#define | PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
#define | CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
#define | PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
#define | CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))
#define | EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
#define | CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the Wake-up PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the Wake-up PINx functionality.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pwr.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr_ex.h File Reference

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stm32f4xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extension module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1
#define | PWR_REGULATOR_VOLTAGE_SCALE2
#define | PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
#define | PWR_WAKEUP_PIN2 ((uint32_t)0x00000080U)
#define | PWR_WAKEUP_PIN3 ((uint32_t)0x00000040U)
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
macros configure the main internal regulator output voltage.
#define | FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
#define | CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
#define | ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
#define | CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
#define | ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
#define | CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
#define | MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
#define | CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
#define | LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
#define | CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
#define | BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
#define | CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
#define | IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE)
#define | IS_PWR_WAKEUP_PIN(PIN)

Functions

void | HAL_PWREx_EnableFlashPowerDown (void)
Enables the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disables the Flash Power Down in Stop mode.
HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enables the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disables the Backup Regulator.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configures the main internal regulator output voltage.
void | HAL_PWREx_EnableMainRegulatorLowVoltage (void)
Enables Main Regulator low voltage mode.
void | HAL_PWREx_DisableMainRegulatorLowVoltage (void)
Disables Main Regulator low voltage mode.
void | HAL_PWREx_EnableLowRegulatorLowVoltage (void)
Enables Low Power Regulator low voltage mode.
void | HAL_PWREx_DisableLowRegulatorLowVoltage (void)
Disables Low Power Regulator low voltage mode.

Detailed Description

Header file of PWR HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pwr_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc.h File Reference

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stm32f4xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
#define | RCC_HSE_OFF ((uint8_t)0x00U)
#define | RCC_HSE_ON ((uint8_t)0x01U)
#define | RCC_HSE_BYPASS ((uint8_t)0x05U)
#define | RCC_LSE_OFF ((uint8_t)0x00U)
#define | RCC_LSE_ON ((uint8_t)0x01U)
#define | RCC_LSE_BYPASS ((uint8_t)0x05U)
#define | RCC_HSI_OFF ((uint8_t)0x00U)
#define | RCC_HSI_ON ((uint8_t)0x01U)
#define | RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
#define | RCC_LSI_OFF ((uint8_t)0x00U)
#define | RCC_LSI_ON ((uint8_t)0x01U)
#define | RCC_PLL_NONE ((uint8_t)0x00U)
#define | RCC_PLL_OFF ((uint8_t)0x01U)
#define | RCC_PLL_ON ((uint8_t)0x02U)
#define | RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
#define | RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
#define | RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
#define | RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
#define | RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
#define | RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
#define | RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define | RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
#define | RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
#define | RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
#define | RCC_MCO1 ((uint32_t)0x00000000U)
#define | RCC_MCO2 ((uint32_t)0x00000001U)
#define | RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
#define | RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define | RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
#define | RCC_MCODIV_1 ((uint32_t)0x00000000U)
#define | RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
#define | RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
#define | RCC_MCODIV_5 RCC_CFGR_MCO1PRE
#define | RCC_IT_LSIRDY ((uint8_t)0x01U)
#define | RCC_IT_LSERDY ((uint8_t)0x02U)
#define | RCC_IT_HSIRDY ((uint8_t)0x04U)
#define | RCC_IT_HSERDY ((uint8_t)0x08U)
#define | RCC_IT_PLLRDY ((uint8_t)0x10U)
#define | RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
#define | RCC_IT_CSS ((uint8_t)0x80U)
#define | RCC_FLAG_HSIRDY ((uint8_t)0x21U)
#define | RCC_FLAG_HSERDY ((uint8_t)0x31U)
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39U)
#define | RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
#define | RCC_FLAG_LSERDY ((uint8_t)0x41U)
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61U)
#define | RCC_FLAG_BORRST ((uint8_t)0x79U)
#define | RCC_FLAG_PINRST ((uint8_t)0x7AU)
#define | RCC_FLAG_PORRST ((uint8_t)0x7BU)
#define | RCC_FLAG_SFTRST ((uint8_t)0x7CU)
#define | RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
#define | RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
#define | RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
#define | __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
#define | __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_USART6_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_TIM9_CLK_ENABLE()
#define | __HAL_RCC_TIM11_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define | __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
#define | __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define | __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
#define | __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define | __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
#define | __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
#define | __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
#define | __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
#define | __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
#define | __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
#define | __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
#define | __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#define | __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
#define | __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
#define | __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
#define | __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
#define | __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
#define | __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
#define | __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
#define | __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
#define | __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
#define | __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define | __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
#define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.
#define | __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO1 clock.
#define | __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
Macro to configure the MCO2 clock.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
#define | RCC_FLAG_MASK ((uint8_t)0x1FU)
Check RCC flag is set or not.
#define | __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
#define | RCC_HSION_BIT_NUMBER 0x00U
#define | RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
#define | RCC_CSSON_BIT_NUMBER 0x13U
#define | RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
#define | RCC_PLLON_BIT_NUMBER 0x18U
#define | RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
#define | RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
#define | RCC_RTCEN_BIT_NUMBER 0x0FU
#define | RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
#define | RCC_BDRST_BIT_NUMBER 0x10U
#define | RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
#define | RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
#define | RCC_LSION_BIT_NUMBER 0x00U
#define | RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
#define | RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
#define | LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
#define | IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
#define | IS_RCC_HSE(HSE)
#define | IS_RCC_LSE(LSE)
#define | IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
#define | IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
#define | IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
#define | IS_RCC_PLLSOURCE(SOURCE)
#define | IS_RCC_SYSCLKSOURCE(SOURCE)
#define | IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
#define | IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
#define | IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
#define | IS_RCC_HCLK(HCLK)
#define | IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
#define | IS_RCC_PCLK(PCLK)
#define | IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
#define | IS_RCC_MCO1SOURCE(SOURCE)
#define | IS_RCC_MCODIV(DIV)
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)

Functions

__weak void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
__weak uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
__weak void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rcc.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f4xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extension module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...

Defines

#define | RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
#define | RCC_PERIPHCLK_TIM ((uint32_t)0x00000002U)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00000004U)
#define | RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008U)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010U)
#define | RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000U)
#define | RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
#define | RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
#define | RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
#define | RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
#define | RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
#define | RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
#define | RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
#define | RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
#define | RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)
#define | RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)
#define | RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00U)
#define | RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01U)
#define | RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
#define | RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
#define | RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define | RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
#define | __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_RTCAPB_CLK_ENABLE()
#define | __HAL_RCC_FMPI2C1_CLK_ENABLE()
#define | __HAL_RCC_DAC_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
#define | __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
#define | __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
#define | __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
#define | __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
#define | __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
#define | __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
#define | __HAL_RCC_SPI5_CLK_ENABLE()
#define | __HAL_RCC_EXTIT_CLK_ENABLE()
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
#define | __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
#define | __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
#define | __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
#define | __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
#define | __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
#define | __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
#define | __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
#define | __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
#define | __HAL_RCC_AHB2_FORCE_RESET()
#define | __HAL_RCC_AHB2_RELEASE_RESET()
#define | __HAL_RCC_AHB3_FORCE_RESET()
#define | __HAL_RCC_AHB3_RELEASE_RESET()
#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
#define | __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
#define | __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
#define | __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#define | __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
#define | __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
#define | __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
#define | __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
#define | __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
#define | __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
#define | __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
#define | __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
#define | __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)
Macro to configure the PLLI2S clock multiplication and division factors .
#define | __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
Macro to configure I2S clock source selection.
#define | __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
Macro to Get I2S clock source selection.
#define | __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Macro to configure the FMPI2C1 clock.
#define | __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Macro to Get the FMPI2C1 clock.
#define | __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
Macro to configure the LPTIM1 clock.
#define | __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
Macro to Get the LPTIM1 clock.
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
Macro to configure the Timers clocks prescalers.
#define | __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
Macros to enable or disable the RCC MCO1 feature.
#define | __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
#define | __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
Macros to enable or disable the RCC MCO2 feature.
#define | __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
#define | RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
#define | RCC_TIMPRE_BIT_NUMBER 0x18
#define | RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
#define | RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
#define | RCC_MCO1EN_BIT_NUMBER 0x8
#define | RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
#define | RCC_MCO2EN_BIT_NUMBER 0x9
#define | RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
#define | PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define | IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
#define | IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
#define | IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
#define | IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
#define | IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
#define | IS_RCC_LSE_MODE(MODE)
#define | IS_RCC_FMPI2C1CLKSOURCE(SOURCE)
#define | IS_RCC_LPTIM1CLKSOURCE(SOURCE)
#define | IS_RCC_I2SAPBCLKSOURCE(SOURCE)
#define | IS_RCC_MCO2SOURCE(SOURCE)

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCCEx_SelectLSEMode (uint8_t Mode)
Select LSE mode.

Detailed Description

Header file of RCC HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rcc_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rng.h File Reference

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stm32f4xx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_HandleTypeDef

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.
#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rng.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc.h File Reference

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stm32f4xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
RTC Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040U)
#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U)
#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U)
#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000U)
#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000U)
#define | RTC_FORMAT_BIN ((uint32_t)0x00000000U)
#define | RTC_FORMAT_BCD ((uint32_t)0x00000001U)
#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U)
#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080U)
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U)
#define | RTC_IT_TS ((uint32_t)0x00008000U)
#define | RTC_IT_WUT ((uint32_t)0x00004000U)
#define | RTC_IT_ALRB ((uint32_t)0x00002000U)
#define | RTC_IT_ALRA ((uint32_t)0x00001000U)
#define | RTC_IT_TAMP ((uint32_t)0x00000004U) /* Used only to Enable the Tamper Interrupt */
#define | RTC_IT_TAMP1 ((uint32_t)0x00020000U)
#define | RTC_IT_TAMP2 ((uint32_t)0x00040000U)
#define | RTC_FLAG_RECALPF ((uint32_t)0x00010000U)
#define | RTC_FLAG_TAMP2F ((uint32_t)0x00004000U)
#define | RTC_FLAG_TAMP1F ((uint32_t)0x00002000U)
#define | RTC_FLAG_TSOVF ((uint32_t)0x00001000U)
#define | RTC_FLAG_TSF ((uint32_t)0x00000800U)
#define | RTC_FLAG_WUTF ((uint32_t)0x00000400U)
#define | RTC_FLAG_ALRBF ((uint32_t)0x00000200U)
#define | RTC_FLAG_ALRAF ((uint32_t)0x00000100U)
#define | RTC_FLAG_INITF ((uint32_t)0x00000040U)
#define | RTC_FLAG_RSF ((uint32_t)0x00000020U)
#define | RTC_FLAG_INITS ((uint32_t)0x00000010U)
#define | RTC_FLAG_SHPF ((uint32_t)0x00000008U)
#define | RTC_FLAG_WUTWF ((uint32_t)0x00000004U)
#define | RTC_FLAG_ALRBWF ((uint32_t)0x00000002U)
#define | RTC_FLAG_ALRAWF ((uint32_t)0x00000001U)
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_FLAGS_MASK
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)
#define | IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFFU)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rtc.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f4xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extension module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
RTC Tamper structure definition. More...

Defines

#define | RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004U)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005U)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006U)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007U)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008U)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009U)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000AU)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000BU)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000CU)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000DU)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000EU)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000FU)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010U)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011U)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012U)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013U)
#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U)
#define | RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAFCR_TAMP2E
#define | RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000U)
#define | RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000U)
#define | RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)
#define | RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000U)
#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800U)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000U)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700U)
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U)
#define | RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000U)
#define | RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080U)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000U)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000U)
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000U)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U)
#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U)
#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000U)
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC Wake-up Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC Wake-up Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
Enable the Coarse calibration process.
#define | __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
Disable the Coarse calibration process.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22)
#define | IS_RTC_BKP(BKP)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_PIN(PIN)
#define | IS_RTC_TIMESTAMP_PIN(PIN)
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
#define | IS_RTC_CALIB_SIGN(SIGN)
#define | IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Gets the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles TimeStamp interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivates wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Gets wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetCoarseCalib (RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value)
Sets the Coarse calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCoarseCalib (RTC_HandleTypeDef *hrtc)
Deactivates the Coarse calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configures the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enables the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enables the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disables the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

Header file of RTC HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rtc_ex.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_smartcard.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f4xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)
#define | SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000U)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000U)
#define | SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define | SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000AU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000BU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000CU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000DU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000EU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000FU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019U)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001AU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001BU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001CU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001DU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001EU)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001FU)
#define | SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U)
#define | SMARTCARD_FLAG_TC ((uint32_t)0x00000040U)
#define | SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U)
#define | SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U)
#define | SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U)
#define | SMARTCARD_FLAG_NE ((uint32_t)0x00000004U)
#define | SMARTCARD_FLAG_FE ((uint32_t)0x00000002U)
#define | SMARTCARD_FLAG_PE ((uint32_t)0x00000001U)
#define | SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle gstate & RxState.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushs the Smartcard DR register.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified Smartcard pending flags.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables or disables the specified SmartCard interrupts.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
Checks whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Macro to enable the SMARTCARD's one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
Macro to disable the SMARTCARD's one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
Macros to enable or disable the SmartCard DMA request.
#define | __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
#define | SMARTCARD_IT_MASK
SMARTCARD interruptions flag mask.
#define | SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
#define | SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | SMARTCARD_BRR(_PCLK_, _BAUD_)
#define | SMARTCARD_CR1_REG_INDEX 1U
#define | SMARTCARD_CR3_REG_INDEX 3U
#define | IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
#define | IS_SMARTCARD_STOPBITS(STOPBITS)
#define | IS_SMARTCARD_PARITY(PARITY)
#define | IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x000000U))
#define | IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
#define | IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
#define | IS_SMARTCARD_LASTBIT(LASTBIT)
#define | IS_SMARTCARD_NACK_STATE(NACK)
#define | IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .
HAL_StatusTypeDef | HAL_SMARTCARD_ReInit (SMARTCARD_HandleTypeDef *hsc)
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the USART SmartCard peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
This function handles SMARTCARD interrupt request.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_smartcard.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spi.h File Reference

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stm32f4xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U)
#define | HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U)
#define | HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U)
#define | HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U)
#define | HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U)
#define | SPI_MODE_SLAVE ((uint32_t)0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_8BIT ((uint32_t)0x00000000U)
#define | SPI_DATASIZE_16BIT SPI_CR1_DFF
#define | SPI_POLARITY_LOW ((uint32_t)0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)
#define | SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
#define | SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
#define | SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
#define | SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
#define | SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
#define | SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
#define | SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)
#define | SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF
#define | SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U
}
HAL SPI State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_spi.h.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim.h File Reference

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stm32f4xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x00000000U)
#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)
#define | TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
#define | TIM_OCMODE_TIMING ((uint32_t)0x00000000U)
#define | TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
#define | TIM_OCFAST_DISABLE ((uint32_t)0x00000000U)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x00000000U)
#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x00000000U)
#define | TIM_CHANNEL_1 ((uint32_t)0x00000000U)
#define | TIM_CHANNEL_2 ((uint32_t)0x00000004U)
#define | TIM_CHANNEL_3 ((uint32_t)0x00000008U)
#define | TIM_CHANNEL_4 ((uint32_t)0x0000000CU)
#define | TIM_CHANNEL_ALL ((uint32_t)0x00000018U)
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)
#define | TIM_ICPSC_DIV1 ((uint32_t)0x00000000U)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)
#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x00000000U)
#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)
#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x00000000U)
#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)
#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x00000000U)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x00000001U)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x00000000U)
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x00000000U)
#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x00000000U)
#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x00000000U)
#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x00000000U)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U)
#define | TIM_TRGO_RESET ((uint32_t)0x00000000U)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)
#define | TIM_SLAVEMODE_RESET ((uint32_t)0x00000004U)
#define | TIM_SLAVEMODE_GATED ((uint32_t)0x00000005U)
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)0x00000006U)
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x00000007U)
#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x00000080U)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x00000000U)
#define | TIM_TS_ITR0 ((uint32_t)0x00000000U)
#define | TIM_TS_ITR1 ((uint32_t)0x00000010U)
#define | TIM_TS_ITR2 ((uint32_t)0x00000020U)
#define | TIM_TS_ITR3 ((uint32_t)0x00000030U)
#define | TIM_TS_TI1F_ED ((uint32_t)0x00000040U)
#define | TIM_TS_TI1FP1 ((uint32_t)0x00000050U)
#define | TIM_TS_TI2FP2 ((uint32_t)0x00000060U)
#define | TIM_TS_ETRF ((uint32_t)0x00000070U)
#define | TIM_TS_NONE ((uint32_t)0x0000FFFFU)
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x00000000U)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
#define | TIM_DMABASE_CR1 (0x00000000U)
#define | TIM_DMABASE_CR2 (0x00000001U)
#define | TIM_DMABASE_SMCR (0x00000002U)
#define | TIM_DMABASE_DIER (0x00000003U)
#define | TIM_DMABASE_SR (0x00000004U)
#define | TIM_DMABASE_EGR (0x00000005U)
#define | TIM_DMABASE_CCMR1 (0x00000006U)
#define | TIM_DMABASE_CCMR2 (0x00000007U)
#define | TIM_DMABASE_CCER (0x00000008U)
#define | TIM_DMABASE_CNT (0x00000009U)
#define | TIM_DMABASE_PSC (0x0000000AU)
#define | TIM_DMABASE_ARR (0x0000000BU)
#define | TIM_DMABASE_RCR (0x0000000CU)
#define | TIM_DMABASE_CCR1 (0x0000000DU)
#define | TIM_DMABASE_CCR2 (0x0000000EU)
#define | TIM_DMABASE_CCR3 (0x0000000FU)
#define | TIM_DMABASE_CCR4 (0x00000010U)
#define | TIM_DMABASE_BDTR (0x00000011U)
#define | TIM_DMABASE_DCR (0x00000012U)
#define | TIM_DMABASE_OR (0x00000013U)
#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000U)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001U)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002U)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003U)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004U)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005U)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006U)
#define | TIM_CCx_ENABLE ((uint32_t)0x00000001U)
#define | TIM_CCx_DISABLE ((uint32_t)0x00000000U)
#define | TIM_CCxN_ENABLE ((uint32_t)0x00000004U)
#define | TIM_CCxN_DISABLE ((uint32_t)0x00000000U)
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
Gets the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.
#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_CLOCKDIVISION_DIV(DIV)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_FAST_STATE(STATE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | IS_TIM_OCIDLE_STATE(STATE)
#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_CLOCKSOURCE(CLOCK)
#define | IS_TIM_CLOCKPOLARITY(POLARITY)
#define | IS_TIM_CLOCKPRESCALER(PRESCALER)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_CLEARINPUT_SOURCE(SOURCE)
#define | IS_TIM_CLEARINPUT_POLARITY(POLARITY)
#define | IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)
#define | IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_OSSR_STATE(STATE)
#define | IS_TIM_OSSI_STATE(STATE)
#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | IS_TIM_BREAK_STATE(STATE)
#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION)
#define | IS_TIM_TRIGGERPOLARITY(POLARITY)
#define | IS_TIM_TRIGGERPRESCALER(PRESCALER)
#define | IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_TI1SELECTION(TI1SELECTION)
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_tim.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim_ex.h File Reference

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Data Structures | Defines | Functions
stm32f4xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extension module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break and Dead time configuration Structure definition. More...

Defines

#define | TIM_TIM2_TIM8_TRGO (0x00000000U)
#define | TIM_TIM2_ETH_PTP (0x00000400U)
#define | TIM_TIM2_USBFS_SOF (0x00000800U)
#define | TIM_TIM2_USBHS_SOF (0x00000C00U)
#define | TIM_TIM5_GPIO (0x00000000U)
#define | TIM_TIM5_LSI (0x00000040U)
#define | TIM_TIM5_LSE (0x00000080U)
#define | TIM_TIM5_RTC (0x000000C0U)
#define | TIM_TIM11_GPIO (0x00000000U)
#define | TIM_TIM11_HSE (0x00000002U)
#define | TIM_SYSTEMBREAKINPUT_HARDFAULT ((uint32_t)0x00000001U) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
#define | TIM_SYSTEMBREAKINPUT_PVD ((uint32_t)0x00000004U) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
#define | TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005U) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
#define | IS_TIM_REMAP(TIM_REMAP)
#define | IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT)
#define | IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

Header file of TIM HAL Extension module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_tim_ex.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_uart.h File Reference

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stm32f4xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)
#define | UART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | UART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | UART_PARITY_NONE ((uint32_t)0x00000000U)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | UART_STATE_DISABLE ((uint32_t)0x00000000U)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020U)
#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800U)
#define | UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
#define | UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define | UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | UART_FLAG_TC ((uint32_t)USART_SR_TC)
#define | UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | UART_FLAG_NE ((uint32_t)USART_SR_NE)
#define | UART_FLAG_FE ((uint32_t)USART_SR_FE)
#define | UART_FLAG_PE ((uint32_t)USART_SR_PE)
#define | UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle gstate & RxState.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushes the UART DR register.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified UART flag is set or not.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART IDLE pending flag.
#define | UART_IT_MASK ((uint32_t)0x0000FFFFU)
Enable the specified UART interrupt.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
macros to enables the UART's one bit sample method
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
macros to disables the UART's one bit sample method
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | UART_CR1_REG_INDEX 1U
UART interruptions flag mask.
#define | UART_CR2_REG_INDEX 2U
#define | UART_CR3_REG_INDEX 3U
#define | IS_UART_WORD_LENGTH(LENGTH)
#define | IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define | IS_UART_STOPBITS(STOPBITS)
#define | IS_UART_PARITY(PARITY)
#define | IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00U))
#define | IS_UART_STATE(STATE)
#define | IS_UART_OVERSAMPLING(SAMPLING)
#define | IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_UART_WAKEUPMETHOD(WAKEUP)
#define | IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
#define | IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
#define | UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | UART_BRR_SAMPLING16(_PCLK_, _BAUD_)
#define | UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
#define | UART_BRR_SAMPLING8(_PCLK_, _BAUD_)

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enters the UART in mute mode.
HAL_StatusTypeDef | HAL_MultiProcessor_ExitMuteMode (UART_HandleTypeDef *huart)
Exits the UART mute mode: wake up software.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Returns the UART state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_uart.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_usart.h File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f4xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)
#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | USART_STOPBITS_1 ((uint32_t)0x00000000U)
#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | USART_PARITY_NONE ((uint32_t)0x00000000U)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | USART_CLOCK_DISABLE ((uint32_t)0x00000000U)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
#define | USART_POLARITY_LOW ((uint32_t)0x00000000U)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | USART_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | USART_NACK_DISABLE ((uint32_t)0x00000000U)
#define | USART_FLAG_TXE ((uint32_t)0x00000080U)
#define | USART_FLAG_TC ((uint32_t)0x00000040U)
#define | USART_FLAG_RXNE ((uint32_t)0x00000020U)
#define | USART_FLAG_IDLE ((uint32_t)0x00000010U)
#define | USART_FLAG_ORE ((uint32_t)0x00000008U)
#define | USART_FLAG_NE ((uint32_t)0x00000004U)
#define | USART_FLAG_FE ((uint32_t)0x00000002U)
#define | USART_FLAG_PE ((uint32_t)0x00000001U)
#define | USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified Smartcard flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified Smartcard pending flags.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the UART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enables or disables the specified USART interrupts.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Macro to enable the USART's one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
Macro to disable the USART's one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | USART_IT_MASK
USART interruptions flag mask.
#define | USART_CR1_REG_INDEX 1U
#define | USART_CR2_REG_INDEX 2U
#define | USART_CR3_REG_INDEX 3U
#define | IS_USART_NACK_STATE(NACK)
#define | IS_USART_LASTBIT(LASTBIT)
#define | IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
#define | IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
#define | IS_USART_CLOCK(CLOCK)
#define | IS_USART_WORD_LENGTH(LENGTH)
#define | IS_USART_STOPBITS(STOPBITS)
#define | IS_USART_PARITY(PARITY)
#define | IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00U) && ((MODE) != (uint32_t)0x00U))
#define | IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
#define | USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
#define | USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Simplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Full-Duplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Returns the USART state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_usart.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_wwdg.h File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32f4xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32f4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 ((uint32_t)0x00000000U)
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB
#define | __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
Reset WWDG handle state.
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enables the WWDG peripheral.
#define | __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
Disables the WWDG peripheral.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Gets the selected WWDG's it status.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
Disables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Gets the selected WWDG's flag status.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clears the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified WWDG interrupt source is enabled or disabled.
#define | WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04U)
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7FU)
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40U) && ((__COUNTER__) <= 0x7FU))

Enumerations

enum HAL_WWDG_StateTypeDef {
HAL_WWDG_STATE_RESET = 0x00U, HAL_WWDG_STATE_READY = 0x01U, HAL_WWDG_STATE_BUSY = 0x02U, HAL_WWDG_STATE_TIMEOUT = 0x03U,
HAL_WWDG_STATE_ERROR = 0x04U
}
WWDG HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_WWDG_DeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG peripheral.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG MSP.
__weak void | HAL_WWDG_MspDeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG MSP.
void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.
HAL_StatusTypeDef | HAL_WWDG_Start (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG.
HAL_StatusTypeDef | HAL_WWDG_Start_IT (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG with interrupt enabled.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
Refreshes the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handles WWDG interrupt request.
HAL_WWDG_StateTypeDef | HAL_WWDG_GetState (WWDG_HandleTypeDef *hwwdg)
Returns the WWDG state.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_wwdg.h.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
Defines | Functions | Variables
stm32f4xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32F4xx_HAL_VERSION_MAIN (0x01)
STM32F4xx HAL Driver version number V1.4.4.
#define | __STM32F4xx_HAL_VERSION_SUB1 (0x04)
#define | __STM32F4xx_HAL_VERSION_SUB2 (0x04)
#define | __STM32F4xx_HAL_VERSION_RC (0x00)
#define | __STM32F4xx_HAL_VERSION
#define | IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | MEMRMP_OFFSET SYSCFG_OFFSET
#define | UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
#define | UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))
#define | CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U)
#define | CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
#define | CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the systick.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_EnableCompensationCell (void)
Enables the I/O Compensation Cell.
void | HAL_DisableCompensationCell (void)
Power-down the I/O Compensation Cell.

Variables

__IO uint32_t | uwTick

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
Functions
stm32f4xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct without initializing the ADC MSP.
static void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitializes the ADCx peripheral registers to their default reset values.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC and starts conversion of the regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Disables ADC and stop conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for regular conversion complete.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of regular channels.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Disables the interrupt and stop ADC conversion of regular channels.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Gets the converted value from data register of regular channel.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Regular conversion half DMA transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
Error ADC callback.
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### ADC Peripheral features #####
  ==============================================================================
  [..]
  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
  (#) Interrupt generation at the end of conversion, end of injected conversion,
      and in case of analog watchdog or overrun events
  (#) Single and continuous conversion modes.
  (#) Scan mode for automatic conversion of channel 0 to channel x.
  (#) Data alignment with in-built data coherency.
  (#) Channel-wise programmable sampling time.
  (#) External trigger option with configurable polarity for both regular and
      injected conversion.
  (#) Dual/Triple mode (on devices with 2 ADCs or more).
  (#) Configurable DMA data storage in Dual/Triple ADC mode.
  (#) Configurable delay between conversions in Dual/Triple interleaved mode.
  (#) ADC conversion type (refer to the datasheets).
  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
      slower speed.
  (#) ADC input range: VREF(minus) = VIN = VREF(plus).
  (#) DMA request generation during regular channel conversion.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
       (##) ADC pins configuration
             (+++) Enable the clock for the ADC GPIOs using the following function:
                   __HAL_RCC_GPIOx_CLK_ENABLE()
             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream.

    *** Configuration of ADC, groups regular/injected, channels parameters ***
  ==============================================================================
  [..]
  (#) Configure the ADC parameters (resolution, data alignment, ...)
      and regular group parameters (conversion trigger, sequencer, ...)
      using function HAL_ADC_Init().

  (#) Configure the channels for regular group parameters (channel number,
      channel rank into sequencer, ..., into regular group)
      using function HAL_ADC_ConfigChannel().

  (#) Optionally, configure the injected group parameters (conversion trigger,
      sequencer, ..., of injected group)
      and the channels for injected group parameters (channel number,
      channel rank into sequencer, ..., into injected group)
      using function HAL_ADCEx_InjectedConfigChannel().

  (#) Optionally, configure the analog watchdog parameters (channels
      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().

  (#) Optionally, for devices with several ADC instances: configure the
      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().

                       *** Execution of ADC conversions ***
  ==============================================================================
  [..]
  (#) ADC driver can be used among three modes: polling, interruption,
      transfer by DMA.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the ADC peripheral using HAL_ADC_Start()
       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
           user can specify the value of timeout according to his end application
       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
       (+) Stop the ADC peripheral using HAL_ADC_Stop()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the ADC peripheral using HAL_ADC_Start_IT()
       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ErrorCallback
       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_ADC_ErrorCallback
       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()

     *** ADC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in ADC HAL driver.

      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register

     [..]
       (@) You can refer to the ADC HAL driver header file for more useful macros

                      *** Deinitialization of ADC ***
  ==============================================================================
  [..]
  (#) Disable the ADC interface
     (++) ADC clock can be hard reset and disabled at RCC top level.
     (++) Hard reset of ADC peripherals
          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
     (++) ADC clock disable using the equivalent macro/functions as configuration step.
               (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);

  (#) ADC pins configuration
     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()

  (#) Optionally, in case of usage of ADC with interruptions:
     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)

  (#) Optionally, in case of usage of DMA:
        (++) Deinitialize the DMA using function HAL_DMA_DeInit().
        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_adc.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc_ex.c File Reference

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Functions
stm32f4xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | ADC_MultiModeDMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
static void | ADC_MultiModeDMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | ADC_MultiModeDMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables the selected ADC software start conversion of the injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables the interrupt and starts ADC conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Poll for injected conversion complete.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Gets the converted value from data register of injected channel.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Disables ADC DMA (multi-ADC mode) and disables ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Configures the ADC multi-mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
       (##) ADC pins configuration
             (+++) Enable the clock for the ADC GPIOs using the following function:
                   __HAL_RCC_GPIOx_CLK_ENABLE()
             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the ADC DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream.
     (#) Configure the ADC Prescaler, conversion resolution and data alignment
         using the HAL_ADC_Init() function.

     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
         and HAL_ADC_ConfigChannel() functions.

     (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
           user can specify the value of timeout according to his end application
       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
       (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()

     *** Multi mode ADCs Regular channels configuration ***
     ======================================================
     [..]
       (+) Select the Multi mode ADC regular channels features (dual or triple mode)
          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_adc_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cortex.c File Reference

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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initializes and configures the Region and the memory to be protected.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M4 exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
        function according to the following table.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
    (#) please refer to programing manual for details in how to configure priority.

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest preemption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32f4xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_cortex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_crc.c File Reference

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stm32f4xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Returns the CRC state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRC HAL driver can be used as follows:

      (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();

      (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
          a 32-bit data buffer using combination of the previous CRC value
          and the new one.

      (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
          a new 32-bit data buffer. This function resets the CRC computation
          unit before starting the computation to avoid getting wrong CRC values.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_crc.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac.c File Reference

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Functions
stm32f4xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitializes the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initializes the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitializes the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    The device integrates two 12-bit Digital Analog Converters that can
    be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 (PA4) as output
      (#) DAC channel2 with DAC_OUT2 (PA5) as output

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_Pin9) must be configured in input mode.

      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)

      (#) Software using DAC_TRIGGER_SOFTWARE

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate
         (#) Noise wave
         (#) Triangle wave

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondence ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       DAC_OUTx = VREF+ * DOR / 4095
       with  DOR is the Data Output Register
          VEF+ is the input voltage reference (refer to the device datasheet)
        e.g. To set DAC_OUT1 to 0.7V, use
          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests  ***
       =====================
       [..]
       A DMA1 request can be generated when an external trigger (but not
       a software trigger) occurs if DMA1 requests are enabled using
       HAL_DAC_Start_DMA()
       [..]
       DMA1 requests are mapped as following:
         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
             already configured
         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
             already configured

    -@- For Dual mode and specific signal (Triangle and noise) generation please
        refer to Extension Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dac.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac_ex.c File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
Functions
stm32f4xx_hal_dac_ex.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enables or disables the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel2.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dac_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma.c File Reference

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Data Structures | Defines | Functions
stm32f4xx_hal_dma.c File Reference

DMA HAL module driver. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Data Structures

struct | DMA_Base_Registers

Defines

#define | HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static uint32_t | DMA_CalcBaseAndBitshift (DMA_HandleTypeDef *hdma)
Returns the DMA Stream base address depending on stream number.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initializes the DMA according to the specified parameters in the DMA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Returns the DMA state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016 This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Stream
       (except for internal SRAM/FLASH memories: no initialization is
       necessary) please refer to Reference manual for connection between peripherals
       and DMA requests .

   (#) For a given Stream, program the required configuration through the following parameters:
       Transfer Direction, Source and Destination data formats,
       Circular, Normal or peripheral flow control mode, Stream Priority level,
       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred. In this
              case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e a member of DMA handle structure).
    [..]
     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
         detection.

     (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.

     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
           Half-Word data size for the peripheral to access its data register and set Word data size
           for the Memory to gain in access time. Each two half words will be packed and written in
           a single access to a Word in the Memory).

     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
           and Destination. In this case the Peripheral Data Size will be applied to both Source
           and Destination.

     *** DMA HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DMA HAL driver.

      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dma.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma_ex.c File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_dma_ex.c File Reference

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_MultiBufferSetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Set the DMA Transfer parameter.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer.
HAL_StatusTypeDef | HAL_DMAEx_MultiBufferStart_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
Starts the multi_buffer DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMAEx_ChangeMemory (DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
Change the memory0 or memory1 address on the fly.

Detailed Description

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
  The DMA Extension HAL driver can be used as follows:
   (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.

     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
     -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_dma_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash.c File Reference

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  • STM32F4xx_HAL_Driver
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Defines | Functions | Variables
stm32f4xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program a double word (64-bit) at a specified address.
static void | FLASH_Program_Word (uint32_t Address, uint32_t Data)
Program word (32-bit) at a specified address.
static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_Program_Byte (uint32_t Address, uint8_t Data)
Program byte (8-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program byte, halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
       prefetch and cache lines.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Prefetch on I-Code
      (+) 64 cache lines of 128 bits on I-Code
      (+) 8 cache lines of 128 bits on D-Code

                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32F4xx devices.

      (#) FLASH Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: byte, half word, word and double word
           (++) There Two modes of programming :
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions :
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Wait for last FLASH operation according to its status
           (++) Get error flag status by calling HAL_SetErrorCode()

    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the prefetch buffer
       (+) Enable/Disable the Instruction cache and the Data cache
       (+) Reset the Instruction cache and the Data cache
       (+) Enable/Disable the FLASH interrupts
       (+) Monitor the FLASH flags status
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_flash.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ex.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Defines | Functions | Variables
stm32f4xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */

Functions

static void | FLASH_MassErase (uint8_t VoltageRange, uint32_t Banks)
Mass erase of FLASH memory.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WRPSector, uint32_t Banks)
Enable the write protection of the desired bank 1 sectors.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WRPSector, uint32_t Banks)
Disable the write protection of the desired bank 1 sectors.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t Level)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
static HAL_StatusTypeDef | FLASH_OB_BOR_LevelConfig (uint8_t Level)
Set the BOR Level.
static uint8_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static uint16_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint8_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint8_t | FLASH_OB_GetBOR (void)
Returns the FLASH BOR level.
static HAL_StatusTypeDef | FLASH_OB_EnablePCROP (uint32_t Sector)
Enable the read/write protection (PCROP) of the desired sectors.
static HAL_StatusTypeDef | FLASH_OB_DisablePCROP (uint32_t Sector)
Disable the read/write protection (PCROP) of the desired sectors.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
Program option bytes.
void | HAL_FLASHEx_AdvOBGetConfig (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
Get the OBEX byte configuration.
HAL_StatusTypeDef | HAL_FLASHEx_OB_SelectPCROP (void)
Select the Protection Mode.
HAL_StatusTypeDef | HAL_FLASHEx_OB_DeSelectPCROP (void)
Deselect the Protection Mode.
void | FLASH_Erase_Sector (uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                   ##### Flash Extension features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and
       STM32F429xx/439xx devices contains the following additional features

       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
           capability (RWW)
       (+) Dual bank memory organization
       (+) PCROP protection for all banks

                      ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
       devices. It includes
      (#) FLASH Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Erase sector, erase all sectors
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
           (++) Set/Reset the write protection
           (++) Set the Read protection Level
           (++) Set the BOR level
           (++) Program the user Option Bytes
      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
       (++) Extended space (bank 2) erase function
       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
       (++) Dual Boot activation
       (++) Write protection configuration for bank 2
       (++) PCROP protection configuration and control for both banks
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_flash_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ramfunc.c File Reference

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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_flash_ramfunc.c File Reference

FLASH RAMFUNC module driver. This file provides a FLASH firmware functions which should be executed from internal SRAM + Stop/Start the flash interface while System Run + Enable/Disable the flash sleep while System Run. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

__RAM_FUNC | HAL_FLASHEx_StopFlashInterfaceClk (void)
Stop the flash interface while System Run.
__RAM_FUNC | HAL_FLASHEx_StartFlashInterfaceClk (void)
Start the flash interface while System Run.
__RAM_FUNC | HAL_FLASHEx_EnableFlashSleepMode (void)
Enable the flash sleep while System Run.
__RAM_FUNC | HAL_FLASHEx_DisableFlashSleepMode (void)
Disable the flash sleep while System Run.

Detailed Description

FLASH RAMFUNC module driver. This file provides a FLASH firmware functions which should be executed from internal SRAM + Stop/Start the flash interface while System Run + Enable/Disable the flash sleep while System Run.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### APIs executed from Internal RAM #####
  ==============================================================================
  [..]
    *** ARM Compiler ***
    --------------------
    [..] RAM functions are defined using the toolchain options.
         Functions that are be executed in RAM should reside in a separate
         source module. Using the 'Options for File' dialog you can simply change
         the 'Code / Const' area of a module to a memory space in physical RAM.
         Available memory areas are declared in the 'Target' tab of the
         Options for Target' dialog.

    *** ICCARM Compiler ***
    -----------------------
    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".

    *** GNU Compiler ***
    --------------------
    [..] RAM functions are defined using a specific toolchain attribute
         "__attribute__((section(".RamFunc")))".
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_flash_ramfunc.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c.c File Reference

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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_fmpi2c.c File Reference

FMPI2C HAL module driver. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU)
#define | FMPI2C_TIMEOUT_ADDR ((uint32_t)10000U)
#define | FMPI2C_TIMEOUT_BUSY ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_DIR ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_RXNE ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_STOPF ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_TC ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_TCR ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_TXIS ((uint32_t)25U)
#define | FMPI2C_TIMEOUT_FLAG ((uint32_t)25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | FMPI2C_STATE_MSK ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~HAL_FMPI2C_STATE_READY)))
#define | FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE))
#define | FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))
#define | FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))
#define | FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))
#define | FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))
#define | FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))
#define | FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))

Functions

static void | FMPI2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C master transmit process complete callback.
static void | FMPI2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C master receive process complete callback.
static void | FMPI2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C slave transmit process complete callback.
static void | FMPI2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C slave receive process complete callback.
static void | FMPI2C_DMAMemTransmitCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C Memory Write process complete callback.
static void | FMPI2C_DMAMemReceiveCplt (DMA_HandleTypeDef *hdma)
DMA FMPI2C Memory Read process complete callback.
static void | FMPI2C_DMAError (DMA_HandleTypeDef *hdma)
DMA FMPI2C communication error callback.
static HAL_StatusTypeDef | FMPI2C_RequestMemoryWrite (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | FMPI2C_RequestMemoryRead (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | FMPI2C_WaitOnFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles FMPI2C Communication Timeout.
static HAL_StatusTypeDef | FMPI2C_WaitOnTXISFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles FMPI2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | FMPI2C_WaitOnRXNEFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | FMPI2C_WaitOnSTOPFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | FMPI2C_IsAcknowledgeFailed (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
This function handles Acknowledge failed detection during an FMPI2C Communication.
static HAL_StatusTypeDef | FMPI2C_Master_ISR (FMPI2C_HandleTypeDef *hfmpi2c)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | FMPI2C_Slave_ISR (FMPI2C_HandleTypeDef *hfmpi2c)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static HAL_StatusTypeDef | FMPI2C_Enable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | FMPI2C_Disable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | FMPI2C_TransferConfig (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_FMPI2C_Init (FMPI2C_HandleTypeDef *hfmpi2c)
Initializes the FMPI2C according to the specified parameters in the FMPI2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hfmpi2c)
DeInitialize the FMPI2C peripheral.
__weak void | HAL_FMPI2C_MspInit (FMPI2C_HandleTypeDef *hfmpi2c)
Initialize the FMPI2C MSP.
__weak void | HAL_FMPI2C_MspDeInit (FMPI2C_HandleTypeDef *hfmpi2c)
DeInitialize the FMPI2C MSP.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Transmit_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Receive_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Transmit_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Receive_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no blocking mode with DMA.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Write_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_Mem_Read_DMA (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_FMPI2C_IsDeviceReady (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Sequential_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Sequential_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Sequential_Transmit_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Slave_Sequential_Receive_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_EnableListen_IT (FMPI2C_HandleTypeDef *hfmpi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_DisableListen_IT (FMPI2C_HandleTypeDef *hfmpi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_FMPI2C_Master_Abort_IT (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress)
Abort a master/host FMPI2C process communication with Interrupt.
void | HAL_FMPI2C_EV_IRQHandler (FMPI2C_HandleTypeDef *hfmpi2c)
This function handles FMPI2C event interrupt request.
void | HAL_FMPI2C_ER_IRQHandler (FMPI2C_HandleTypeDef *hfmpi2c)
This function handles FMPI2C error interrupt request.
__weak void | HAL_FMPI2C_MasterTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Master Tx Transfer completed callback.
__weak void | HAL_FMPI2C_MasterRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Master Rx Transfer completed callback.
__weak void | HAL_FMPI2C_SlaveTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_FMPI2C_SlaveRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_FMPI2C_AddrCallback (FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_FMPI2C_ListenCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Listen Complete callback.
__weak void | HAL_FMPI2C_MemTxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_FMPI2C_MemRxCpltCallback (FMPI2C_HandleTypeDef *hfmpi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_FMPI2C_ErrorCallback (FMPI2C_HandleTypeDef *hfmpi2c)
FMPI2C error callback.
HAL_FMPI2C_StateTypeDef | HAL_FMPI2C_GetState (FMPI2C_HandleTypeDef *hfmpi2c)
Return the FMPI2C handle state.
HAL_FMPI2C_ModeTypeDef | HAL_FMPI2C_GetMode (FMPI2C_HandleTypeDef *hfmpi2c)
Returns the FMPI2C Master, Slave, Memory or no mode.
uint32_t | HAL_FMPI2C_GetError (FMPI2C_HandleTypeDef *hfmpi2c)
Return the FMPI2C error code.

Detailed Description

FMPI2C HAL module driver.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016 This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (FMPI2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The FMPI2C HAL driver can be used as follows:

    (#) Declare a FMPI2C_HandleTypeDef handle structure, for example:
        FMPI2C_HandleTypeDef  hfmpi2c;

    (#)Initialize the FMPI2C low level resources by implementing the HAL_FMPI2C_MspInit() API:
        (##) Enable the FMPI2Cx interface clock
        (##) FMPI2C pins configuration
            (+++) Enable the clock for the FMPI2C GPIOs
            (+++) Configure FMPI2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the FMPI2Cx interrupt priority
            (+++) Enable the NVIC FMPI2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hfmpi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.

    (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_FMPI2C_MspInit(&hfmpi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady()

    (#) For FMPI2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in no blocking mode using HAL_FMPI2C_Master_Transmit_IT()
      (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in no blocking mode using HAL_FMPI2C_Master_Receive_IT()
      (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in no blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in no blocking mode using HAL_FMPI2C_Slave_Receive_IT()
      (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()

    *** Interrupt mode IO sequential operation ***
    ==============================================
    [..]
      (+@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
      (+) A specific option manage the different steps of a sequential transfer
      (+) Different steps option FMPI2C_XferOptions_definition are listed below :
      (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
      (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a start condition with data to transfer without a final stop condition
      (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
             manage only the new data to transfer if no direction change and without a final stop condition in both cases
      (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
             manage only the new data to transfer if no direction change and with a final stop condition in both cases

      (+) Sequential transmit in master FMPI2C mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT()
      (++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
      (+) Sequential receive in master FMPI2C mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Sequential_Receive_IT()
      (++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
      (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean HAL_FMPI2C_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean HAL_FMPI2C_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave FMPI2C mode
           using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT()
      (++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback()
      (+) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Transmit_IT()
      (++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
      (+) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Receive_IT()
      (++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in no blocking mode with Interrupt to a specific memory address using
          HAL_FMPI2C_Mem_Write_IT()
      (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
      (+) Read an amount of data in no blocking mode with Interrupt from a specific memory address using
          HAL_FMPI2C_Mem_Read_IT()
      (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in no blocking mode (DMA) using
          HAL_FMPI2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in no blocking mode (DMA) using
          HAL_FMPI2C_Master_Receive_DMA()
      (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in no blocking mode (DMA) using
          HAL_FMPI2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in no blocking mode (DMA) using
          HAL_FMPI2C_Slave_Receive_DMA()
      (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in no blocking mode with DMA to a specific memory address using
          HAL_FMPI2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
      (+) Read an amount of data in no blocking mode with DMA from a specific memory address using
          HAL_FMPI2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()

     *** FMPI2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in FMPI2C HAL driver.

      (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
      (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
      (+) __HAL_FMPI2C_GET_FLAG : Checks whether the specified FMPI2C flag is set or not
      (+) __HAL_FMPI2C_CLEAR_FLAG : Clears the specified FMPI2C pending flag
      (+) __HAL_FMPI2C_ENABLE_IT: Enables the specified FMPI2C interrupt
      (+) __HAL_FMPI2C_DISABLE_IT: Disables the specified FMPI2C interrupt

     [..]
       (@) You can refer to the FMPI2C HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_fmpi2c.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c_ex.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_fmpi2c_ex.c File Reference

FMPI2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of FMPI2C Extended peripheral: + Extended features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_FMPI2CEx_ConfigAnalogFilter (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter)
Configure FMPI2C Analog noise filter.
HAL_StatusTypeDef | HAL_FMPI2CEx_ConfigDigitalFilter (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
Configure FMPI2C Digital noise filter.
HAL_StatusTypeDef | HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
Enable FMPI2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
Disable FMPI2C wakeup from stop mode.
void | HAL_FMPI2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the FMPI2C fast mode plus driving capability.
void | HAL_FMPI2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the FMPI2C fast mode plus driving capability.

Detailed Description

FMPI2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of FMPI2C Extended peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
               ##### FMPI2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the FMPI2C interface for STM32F4xx
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop mode

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure FMPI2C Analog noise filter using the function HAL_FMPI2CEx_ConfigAnalogFilter()
    (#) Configure FMPI2C Digital noise filter using the function HAL_FMPI2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of FMPI2C Wake Up Mode using the functions :
          (++) HAL_FMPI2CEx_EnableWakeUp()
          (++) HAL_FMPI2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_FMPI2CEx_EnableFastModePlus()
          (++) HAL_FMPI2CEx_DisbleFastModePlus()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_fmpi2c_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_gpio.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE ((uint32_t)0x00000003U)
#define | EXTI_MODE ((uint32_t)0x10000000U)
#define | GPIO_MODE_IT ((uint32_t)0x00010000U)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define | RISING_EDGE ((uint32_t)0x00100000U)
#define | FALLING_EDGE ((uint32_t)0x00200000U)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define | GPIO_NUMBER ((uint32_t)16U)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
  in several modes:
  (+) Input mode
  (+) Analog mode
  (+) Output mode
  (+) Alternate function mode
  (+) External interrupt/event lines

  [..]
  During and just after reset, the alternate functions and external interrupt
  lines are not active and the I/O ports are configured in input floating mode.

  [..]
  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
  activated or not.

  [..]
  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
  type and the IO speed can be selected depending on the VDD value.

  [..]
  All ports have external interrupt/event capability. To use external interrupt
  lines, the port must be configured in input mode. All available GPIO pins are
  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

  [..]
  The external interrupt/event controller consists of up to 23 edge detectors
  (16 lines are connected to GPIO) for generating event/interrupt requests (each
  input line can be independently configured to select the type (interrupt or event)
  and the corresponding trigger event (rising or falling or both). Each line can
  also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_gpio.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c.c File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
Defines | Functions
stm32f4xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | I2C_TIMEOUT_FLAG ((uint32_t)35U)
#define | I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000U)
#define | I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000U)
#define | I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAMemTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Write process complete callback.
static void | I2C_DMAMemReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C Memory Read process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static HAL_StatusTypeDef | I2C_MasterRequestWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
static HAL_StatusTypeDef | I2C_MasterRequestRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
Master sends target device address for read request.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnMasterAddressFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
This function handles I2C Communication Timeout for Master addressing phase.
static HAL_StatusTypeDef | I2C_WaitOnTXEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of TXE flag.
static HAL_StatusTypeDef | I2C_WaitOnBTFFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of BTF flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_MasterTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Master.
static HAL_StatusTypeDef | I2C_MasterTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master transmitter.
static HAL_StatusTypeDef | I2C_MasterReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Master.
static HAL_StatusTypeDef | I2C_MasterReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master receiver.
static HAL_StatusTypeDef | I2C_SlaveTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave transmitter.
static HAL_StatusTypeDef | I2C_SlaveReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave receiver.
static HAL_StatusTypeDef | I2C_Slave_ADDR (I2C_HandleTypeDef *hi2c)
Handle ADD flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_STOPF (I2C_HandleTypeDef *hi2c)
Handle STOPF flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_AF (I2C_HandleTypeDef *hi2c)
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in no-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in no-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in no-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in no-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callbacks.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callbacks.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callbacks.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callbacks.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callbacks.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callbacks.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Returns the I2C state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx Stream
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx Stream

    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** Interrupt mode IO sequential operation ***
    ==============================================
    [..]
      (+@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
      (+) A specific option manage the different steps of a sequential transfer
      (+) Differents steps option I2C_XferOptions_definition are listed below :
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a start condition with data to transfer without a final stop condition
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
             manage only the new data to transfer if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
             manage only the new data to transfer if no direction change and with a final stop condition in both cases

      (+) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
      (++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
      (++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave I2C mode
           using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
      (++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (+) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
      (++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
      (++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2c.c.

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STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s.c File Reference

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Functions
stm32f4xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

__weak HAL_StatusTypeDef | HAL_I2S_Init (I2S_HandleTypeDef *hi2s)
Initializes the I2S according to the specified parameters in the I2S_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s)
DeInitializes the I2S peripheral.
__weak void | HAL_I2S_MspInit (I2S_HandleTypeDef *hi2s)
I2S MSP Init.
__weak void | HAL_I2S_MspDeInit (I2S_HandleTypeDef *hi2s)
I2S MSP DeInit.
HAL_StatusTypeDef | HAL_I2S_Transmit (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Receive (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2S_Transmit_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Receive_IT (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2S_Transmit_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2S_Receive_DMA (I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
__weak HAL_StatusTypeDef | HAL_I2S_DMAPause (I2S_HandleTypeDef *hi2s)
Pauses the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAResume (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak HAL_StatusTypeDef | HAL_I2S_DMAStop (I2S_HandleTypeDef *hi2s)
Resumes the audio stream playing from the Media.
__weak void | HAL_I2S_IRQHandler (I2S_HandleTypeDef *hi2s)
This function handles I2S interrupt request.
__weak void | HAL_I2S_TxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer Half completed callbacks.
__weak void | HAL_I2S_TxCpltCallback (I2S_HandleTypeDef *hi2s)
Tx Transfer completed callbacks.
__weak void | HAL_I2S_RxHalfCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer half completed callbacks.
__weak void | HAL_I2S_RxCpltCallback (I2S_HandleTypeDef *hi2s)
Rx Transfer completed callbacks.
__weak void | HAL_I2S_ErrorCallback (I2S_HandleTypeDef *hi2s)
I2S error callbacks.
HAL_I2S_StateTypeDef | HAL_I2S_GetState (I2S_HandleTypeDef *hi2s)
Return the I2S state.
uint32_t | HAL_I2S_GetError (I2S_HandleTypeDef *hi2s)
Return the I2S error code.
void | I2S_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process half complete callback.
void | I2S_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process half complete callback.
void | I2S_DMAError (DMA_HandleTypeDef *hdma)
DMA I2S communication error callback.
HAL_StatusTypeDef | I2S_Transmit_IT (I2S_HandleTypeDef *hi2s)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | I2S_Receive_IT (I2S_HandleTypeDef *hi2s)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | I2S_WaitFlagStateUntilTimeout (I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
This function handles I2S Communication Timeout.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follow:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
   -@- Make sure that either:
        (+@) I2S PLL is configured or
        (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.

   (#) Three operation modes are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()

   *** I2S HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in USART HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2s.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s_ex.c File Reference

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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_i2s_ex.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

void | I2S_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA I2S transmit process complete callback.
void | I2S_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA I2S receive process complete callback.
uint32_t | I2S_GetInputClock (I2S_HandleTypeDef *hi2s)
Get I2S clock Input based on Source clock selection in RCC.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### I2S Extension features #####
  ==============================================================================
  [..]
     (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
         data simultaneously using two data lines. Each SPI peripheral has an extended block
         called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
     (#) The extension block is not a full SPI IP, it is used only as I2S slave to
         implement full duplex mode. The extension block uses the same clock sources
         as its master.

     (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.

     [..]
       (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
         I2Sx can be I2S2 or I2S3.

                  ##### How to use this driver #####
 ===============================================================================
 [..]
   Three operation modes are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_i2s_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_irda.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configures the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receives an amount of data in non blocking mode.
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles IRDA Communication Timeout.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IARDA error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure.
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) IRDA pins configuration:
            (+++) Enable the clock for the IRDA GPIOs.
            (+++) Configure these IRDA pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.

    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
        and Mode(Receiver/Transmitter) in the hirda Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
            by calling the customized HAL_IRDA_MspInit() API.
    -@@- The specific IRDA interrupts (Transmission complete interrupt,
        RXNE interrupt and Error Interrupts) will be managed using the macros
        __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
      (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_IRDA_ErrorCallback

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
      (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_IRDA_ErrorCallback

    *** IRDA HAL driver macros list ***
    ===================================
    [..]
      Below the list of most used macros in IRDA HAL driver.

     (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
     (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
     (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
     (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
     (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
     (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt

     (@) You can refer to the IRDA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_irda.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_iwdg.c File Reference

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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Configuration functions + IO operation functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | IWDG_TIMEOUT_FLAG ((uint32_t)1000U) /* 1 s */

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG according to the specified parameters in the IWDG_InitTypeDef and creates the associated handle.
__weak void | HAL_IWDG_MspInit (IWDG_HandleTypeDef *hiwdg)
Initializes the IWDG MSP.
HAL_StatusTypeDef | HAL_IWDG_Start (IWDG_HandleTypeDef *hiwdg)
Starts the IWDG.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refreshes the IWDG.
HAL_IWDG_StateTypeDef | HAL_IWDG_GetState (IWDG_HandleTypeDef *hiwdg)
Returns the IWDG state.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Configuration functions + IO operation functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                    ##### IWDG Specific features #####
  ==============================================================================
    [..]
    (+) The IWDG can be started by either software or hardware (configurable
         through option byte).

    (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
         thus stays active even if the main clock fails.
         Once the IWDG is started, the LSI is forced ON and cannot be disabled
         (LSI cannot be disabled too), and the counter starts counting down from
         the reset value of 0xFFF. When it reaches the end of count value (0x000)
         a system reset is generated.

    (+) The IWDG counter should be refreshed at regular intervals, otherwise the
         watchdog generates an MCU reset when the counter reaches 0.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
         reset occurs.

    (+) Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM5 CH4 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
    [..]
    If Window option is disabled
      (+) Use IWDG using HAL_IWDG_Init() function to :
         (++) Enable write access to IWDG_PR, IWDG_RLR.
         (++) Configure the IWDG prescaler, counter reload value.
              This reload value will be loaded in the IWDG counter each time the counter
              is reloaded, then the IWDG will start counting down from this value.
    [..]
      (+) Use IWDG using HAL_IWDG_Start() function to:
          (++) Reload IWDG counter with value defined in the IWDG_RLR register.
          (++) Start the IWDG, when the IWDG is used in software mode (no need
               to enable the LSI, it will be enabled by hardware).
      (+) Then the application program must refresh the IWDG counter at regular
          intervals during normal operation to prevent an MCU reset, using
          HAL_IWDG_Refresh() function.
    [..]
    if Window option is enabled:

      (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
      (+) Use IWDG using HAL_IWDG_Init() function to :
         (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
         (++) Configure the IWDG prescaler, reload value and window value.
      (+) Then the application program must refresh the IWDG counter at regular
          intervals during normal operation to prevent an MCU reset, using
          HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver.

      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
      (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_iwdg.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_lptim.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_lptim.c File Reference

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initializes the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitializes LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Starts the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Starts the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Starts the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stops the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
This function returns the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
This function return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
This function return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
This function handles LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Returns the LPTIM state.

Detailed Description

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
         (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (##) The instance: LPTIM1.
         (##) Clock: the counter clock.
             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE, LSI or MSI).
             (+++) Prescaler: select the clock divider.
         (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
             (+++) Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
             (+++) SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (##) Trigger: How the counter start.
             (+++) Source: trigger can be software or one of the hardware triggers.
             (+++) ActiveEdge : only for hardware trigger.
             (+++) SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (##) OutputPolarity : 2 opposite polarities are possibles.
         (##) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.

      (#)Six modes are available:

         (##) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (##) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (##) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (##) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode.

         (##) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (##) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

       (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_lptim.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr.c File Reference

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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000U)
#define | PVD_MODE_EVT ((uint32_t)0x00020000U)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002U)

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the Wake-up PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the Wake-up PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M4 SEVONPEND bit.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pwr.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr_ex.c File Reference

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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | PWR_OVERDRIVE_TIMEOUT_VALUE 1000U
#define | PWR_UDERDRIVE_TIMEOUT_VALUE 1000U
#define | PWR_BKPREG_TIMEOUT_VALUE 1000U
#define | PWR_VOSRDY_TIMEOUT_VALUE 1000U

Functions

HAL_StatusTypeDef | HAL_PWREx_EnableBkUpReg (void)
Enables the Backup Regulator.
HAL_StatusTypeDef | HAL_PWREx_DisableBkUpReg (void)
Disables the Backup Regulator.
void | HAL_PWREx_EnableFlashPowerDown (void)
Enables the Flash Power Down in Stop mode.
void | HAL_PWREx_DisableFlashPowerDown (void)
Disables the Flash Power Down in Stop mode.
uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configures the main internal regulator output voltage.
void | HAL_PWREx_EnableMainRegulatorLowVoltage (void)
Enables Main Regulator low voltage mode.
void | HAL_PWREx_DisableMainRegulatorLowVoltage (void)
Disables Main Regulator low voltage mode.
void | HAL_PWREx_EnableLowRegulatorLowVoltage (void)
Enables Low Power Regulator low voltage mode.
void | HAL_PWREx_DisableLowRegulatorLowVoltage (void)
Disables Low Power Regulator low voltage mode.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_pwr_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc.c File Reference

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Defines | Functions | Variables
stm32f4xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOC
#define | MCO2_PIN GPIO_PIN_9

Functions

__weak void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
__weak uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
__weak void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Variables

const uint8_t | APBAHBPrescTable [16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
      and I-Cache are disabled, and all peripherals are off except internal
      SRAM, Flash and JTAG.
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
          all peripherals mapped on these busses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in input floating state, except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB busses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals which clocks are not
          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
          after the clock enable bit is set on the hardware register
      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
          after the clock enable bit is set on the hardware register

    [..]
      Implemented Workaround:
      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rcc.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc_ex.c File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_rcc_ex.c File Reference

Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCCEx_SelectLSEMode (uint8_t Mode)
Select LSE mode.

Detailed Description

Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rcc_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rng.c File Reference

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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_TIMEOUT_VALUE 2U

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Returns generated random number in polling mode (Obsolete) Use HAL_RNG_GenerateRandomNumber() API instead.
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Returns a 32-bit random number with interrupt enabled (Obsolete), Use HAL_RNG_GenerateRandomNumber_IT() API instead.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32 bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rng.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc.c File Reference

  • File List
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  • Drivers
  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
              ##### Backup Domain Operating Condition #####
  ==============================================================================
  [..] The real-time clock (RTC), the RTC backup registers, and the backup
       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
       VDD supply is powered off.
       To retain the content of the RTC backup registers, backup SRAM, and supply
       the RTC when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
       off, the VBAT pin powers the following blocks:
    (#) The RTC
    (#) The LSE oscillator
    (#) The backup SRAM when the low power backup regulator is enabled
    (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)

  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
       the following pins are available:
    (#) PC14 and PC15 can be used as either GPIO or LSE pins
    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
    (#) PI8 can be used as a GPIO or as the RTC_AF2 pin

  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
       because VDD is not present), the following pins are available:
    (#) PC14 and PC15 can be used as LSE pins only
    (#) PC13 can be used as the RTC_AF1 pin
    (#) PI8 can be used as the RTC_AF2 pin

                   ##### Backup Domain Reset #####
  ==================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values. The BKPSRAM is not affected by this reset. The only
       way to reset the BKPSRAM is through the Flash interface by requesting
       a protection level change from 1 to 0.
  [..] A backup domain reset is generated when one of the following events occurs:
    (#) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (#) VDD or VBAT power on, if both supplies have previously been powered off.

                   ##### Backup Domain Access #####
  ==================================================================
  [..] After reset, the backup domain (RTC registers, RTC backup data
       registers and backup SRAM) is protected against possible unwanted write
       accesses.
  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (+) Enable the Power Controller (PWR) APB1 interface clock using the
        __HAL_RCC_PWR_CLK_ENABLE() function.
    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.

                  ##### How to use this driver #####
  ==================================================================
  [..]
    (+) Enable the RTC domain access (see description in the section above).
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
  ==================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wake-up mode), by using the RTC alarm
       or the RTC wake-up events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
       is LSE or LSI.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rtc.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc_ex.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_rtc_ex.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Sets TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivates TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Gets the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Sets wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivates wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Gets wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetCoarseCalib (RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value)
Sets the Coarse calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCoarseCalib (RTC_HandleTypeDef *hrtc)
Deactivates the Coarse calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configures the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enables the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enables the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disables the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmB Polling request.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wake-up configuration ***
  ================================
  [..]
    (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
        function. You can also configure the RTC Wake-up timer in interrupt mode
        using the HAL_RTC_SetWakeUpTimer_IT() function.
    (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
        HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
        interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
        function.
    (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
        or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in
        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
        or HAL_RTC_SetTimeStamp_IT() function.

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
        or Level according to the Tamper filter (if equal to 0 Edge else Level)
        value, sampling frequency, precharge or discharge and Pull-UP using the
        HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
        mode using HAL_RTC_SetTamper_IT() function.
    (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
        or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in
        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
        or HAL_RTC_SetTamper_IT() function.

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
        function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_rtc_ex.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_smartcard.c File Reference

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  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD peripheral.
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc)
Receive an amount of data in non blocking mode.
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles SMARTCARD Communication Timeout.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle .
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the USART SmartCard peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
This function handles SMARTCARD interrupt request.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) SMARTCARD pins configuration:
            (+++) Enable the clock for the SMARTCARD GPIOs.
            (+++) Configure these SMARTCARD pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.

    (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
        flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
    [..]
    (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
        RXNE interrupt and Error Interrupts) will be managed using the macros
        __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
      (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback

    *** SMARTCARD HAL driver macros list ***
    =============================================
    [..]
      Below the list of most used macros in SMARTCARD HAL driver.

      (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
      (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
      (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
      (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
      (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
      (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt

    [..]
      (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_smartcard.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spi.c File Reference

  • File List
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  • STM32F4xx_HAL_Driver
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Defines | Functions
stm32f4xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100U

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_CheckForDisablingSPI (SPI_HandleTypeDef *hspi)
Handle to disable SPI in specific condition.
static HAL_StatusTypeDef | SPI_CheckFlag_BSY (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle to check BSY flag before start a new transaction.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx stream
              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
     [..]
       Master Receive mode restriction:
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
          does not initiate a new transfer the following procedure has to be respected:
          (##) HAL_SPI_DeInit()
          (##) HAL_SPI_Init()
     [..]
       Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
       according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :

       DataSize = SPI_DATASIZE_8BIT:
       +----------------------------------------------------------------------------------------------+
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
       |==============================================================================================|
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
       |=========|================|==========|==========|===========|==========|===========|==========|
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
       |=========|================|==========|==========|===========|==========|===========|==========|
       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
       +----------------------------------------------------------------------------------------------+

       DataSize = SPI_DATASIZE_16BIT:
       +----------------------------------------------------------------------------------------------+
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
       |==============================================================================================|
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
       |=========|================|==========|==========|===========|==========|===========|==========|
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
       |=========|================|==========|==========|===========|==========|===========|==========|
       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
       +----------------------------------------------------------------------------------------------+
       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
       @note
            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_spi.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
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Functions
stm32f4xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 4 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Time Output Compare 4 configuration.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Output Compare 2 configuration.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output

                        ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
                 __GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
              Output Compare signal.
         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
              PWM signal.
         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
              external signal.
         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
              in One Pulse Mode.
         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_tim.c.

Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim_ex.c File Reference

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stm32f4xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extension features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Input Capture
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

                        ##### How to use this driver #####
  ==============================================================================
  [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
                 __GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

    (#) Configure the TIM in the desired functioning mode using one of the
        initialization function of this driver:
        (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
             Timer Hall Sensor Interface and the commutation event with the corresponding
             Interrupt and DMA request if needed (Note that One Timer is used to interface
             with the Hall sensor Interface and another Timer should be used to use
             the commutation event).

    (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_tim_ex.c.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_uart.c File Reference

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stm32f4xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

static void | UART_SetConfig (UART_HandleTypeDef *huart)
Configures the UART peripheral.
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Sends an amount of data in non blocking mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receives an amount of data in non blocking mode.
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles UART Communication Timeout.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enters the UART in mute mode.
HAL_StatusTypeDef | HAL_MultiProcessor_ExitMuteMode (UART_HandleTypeDef *huart)
Exits the UART mute mode: wake up software.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Returns the UART state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required
                  Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx Stream.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode(Receiver/Transmitter) in the Init structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.

    (#) For the Multi-Processor mode, initialize the UART registers by calling
        the HAL_MultiProcessor_Init() API.

     [..]
       (@) The specific UART interrupts (Transmission complete interrupt,
            RXNE interrupt and Error Interrupts) will be managed using the macros
            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
            and receive process.

     [..]
       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
            HAL_UART_MspInit() API.

     [..]
        Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback
       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
       (+) Stop the DMA Transfer using HAL_UART_DMAStop()

     *** UART HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in UART HAL driver.

      (+) __HAL_UART_ENABLE: Enable the UART peripheral
      (+) __HAL_UART_DISABLE: Disable the UART peripheral
      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not

     [..]
       (@) You can refer to the UART HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_uart.c.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_usart.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
Defines | Functions
stm32f4xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines

#define | DUMMY_DATA 0xFFFFU
#define | USART_TIMEOUT_VALUE 22000U

Functions

static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
static void | USART_SetConfig (USART_HandleTypeDef *husart)
Configures the USART peripheral.
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
This function handles USART Communication Timeout.
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Simplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Full-Duplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Returns the USART state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The USART HAL driver can be used as follows:

    (#) Declare a USART_HandleTypeDef handle structure.
    (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
        (##) Enable the USARTx interface clock.
        (##) USART pins configuration:
             (+++) Enable the clock for the USART GPIOs.
             (+++) Configure these USART pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
             (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx stream.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx Stream.
             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode(Receiver/Transmitter) in the husart Init structure.

    (#) Initialize the USART registers by calling the HAL_USART_Init() API:
        (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_USART_MspInit(&husart) API.

        -@@- The specific USART interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_USART_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
       (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_USART_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxCpltCallback
       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_USART_ErrorCallback
       (+) Pause the DMA Transfer using HAL_USART_DMAPause()
       (+) Resume the DMA Transfer using HAL_USART_DMAResume()
       (+) Stop the DMA Transfer using HAL_USART_DMAStop()

     *** USART HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in USART HAL driver.

       (+) __HAL_USART_ENABLE: Enable the USART peripheral
       (+) __HAL_USART_DISABLE: Disable the USART peripheral
       (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
       (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
       (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
       (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt

     [..]
       (@) You can refer to the USART HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_usart.c.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_wwdg.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
Functions
stm32f4xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG according to the specified parameters in the WWDG_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_WWDG_DeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG peripheral.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initializes the WWDG MSP.
__weak void | HAL_WWDG_MspDeInit (WWDG_HandleTypeDef *hwwdg)
DeInitializes the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Start (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG.
HAL_StatusTypeDef | HAL_WWDG_Start_IT (WWDG_HandleTypeDef *hwwdg)
Starts the WWDG with interrupt enabled.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
Refreshes the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handles WWDG interrupt request.
__weak void | HAL_WWDG_WakeupCallback (WWDG_HandleTypeDef *hwwdg)
Early Wakeup WWDG callback.
HAL_WWDG_StateTypeDef | HAL_WWDG_GetState (WWDG_HandleTypeDef *hwwdg)
Returns the WWDG state.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.4.4
Date:
22-January-2016
  ==============================================================================
                      ##### WWDG specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls over from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.
    (+) Once enabled the WWDG cannot be disabled except by a system reset.
    (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
        reset occurs.
    (+) The WWDG counter input clock is derived from the APB clock divided
        by a programmable prescaler.
    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
    (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
        (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock

    (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
    (+) Set the WWDG prescaler, refresh window and counter value
        using HAL_WWDG_Init() function.
    (+) Start the WWDG using HAL_WWDG_Start() function.
        When the WWDG is enabled the counter value should be configured to
        a value greater than 0x40 to prevent generating an immediate reset.
    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
        generated when the counter reaches 0x40, and then start the WWDG using
        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
        add his own code by customization of function pointer HAL_WWDG_WakeupCallback
        Once enabled, EWI interrupt cannot be disabled except by a system reset.
    (+) Then the application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the refresh window value already programmed.

     *** WWDG HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in WWDG HAL driver.

      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
      (+) __HAL_WWDG_ENABLE_IT:  Enables the WWDG early wake-up interrupt
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f4xx_hal_wwdg.c.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__DMA_HandleTypeDef | DMA handle Structure definition
__SPI_HandleTypeDef | SPI handle Structure definition
ADC_AnalogWDGConfTypeDef | ADC Configuration multi-mode structure definition
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_HandleTypeDef | ADC handle Structure definition
ADC_InitTypeDef | Structure definition of ADC and regular group initialization
ADC_InjectionConfTypeDef | ADC Configuration injected Channel structure definition
ADC_MultiModeTypeDef | ADC Configuration multi-mode structure definition
CRC_HandleTypeDef |
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DAC_HandleTypeDef | DAC handle Structure definition
DMA_Base_Registers |
DMA_InitTypeDef | DMA Configuration Structure definition
FLASH_AdvOBProgramInitTypeDef | FLASH Advanced Option Bytes Program structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
FMPI2C_HandleTypeDef |
FMPI2C_InitTypeDef |
GPIO_InitTypeDef | GPIO Init structure definition
I2C_HandleTypeDef | I2C handle Structure definition
I2C_InitTypeDef | I2C Configuration Structure definition
I2S_HandleTypeDef | I2S handle Structure definition
I2S_InitTypeDef | I2S Init structure definition
IRDA_HandleTypeDef | IRDA handle Structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_HandleTypeDef | LPTIM handle Structure definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
MPU_Region_InitTypeDef |
PWR_PVDTypeDef | PWR PVD configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RNG_HandleTypeDef |
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_HandleTypeDef | RTC Handle Structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_TamperTypeDef | RTC Tamper structure definition
RTC_TimeTypeDef | RTC Time structure definition
SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SPI_InitTypeDef | SPI Configuration Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_HandleTypeDef | TIM Time Base Handle Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
UART_HandleTypeDef | UART handle Structure definition
UART_InitTypeDef | UART Init Structure definition
USART_HandleTypeDef | USART handle Structure definition
USART_InitTypeDef | USART Init Structure definition
WWDG_HandleTypeDef | WWDG handle Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | F | G | I | L | M | P | R | S | T | U | W | _
A
FLASH_EraseInitTypeDef LPTIM_HandleTypeDef RTC_InitTypeDef TIM_OnePulse_InitTypeDef
FLASH_OBProgramInitTypeDef LPTIM_InitTypeDef RTC_TamperTypeDef TIM_SlaveConfigTypeDef
ADC_AnalogWDGConfTypeDef FLASH_ProcessTypeDef LPTIM_TriggerConfigTypeDef RTC_TimeTypeDef
U
ADC_ChannelConfTypeDef FMPI2C_HandleTypeDef LPTIM_ULPClockConfigTypeDef
S
ADC_HandleTypeDef FMPI2C_InitTypeDef
M
UART_HandleTypeDef
ADC_InitTypeDef
G
SMARTCARD_HandleTypeDef UART_InitTypeDef
ADC_InjectionConfTypeDef MPU_Region_InitTypeDef SMARTCARD_InitTypeDef USART_HandleTypeDef
ADC_MultiModeTypeDef GPIO_InitTypeDef
P
SPI_InitTypeDef USART_InitTypeDef
C
I
T
W
PWR_PVDTypeDef
CRC_HandleTypeDef I2C_HandleTypeDef
R
TIM_Base_InitTypeDef WWDG_HandleTypeDef
D
I2C_InitTypeDef TIM_BreakDeadTimeConfigTypeDef WWDG_InitTypeDef
I2S_HandleTypeDef RCC_ClkInitTypeDef TIM_ClearInputConfigTypeDef
_
DAC_ChannelConfTypeDef I2S_InitTypeDef RCC_OscInitTypeDef TIM_ClockConfigTypeDef
DAC_HandleTypeDef IRDA_HandleTypeDef RCC_PeriphCLKInitTypeDef TIM_Encoder_InitTypeDef __DMA_HandleTypeDef
DMA_Base_Registers IRDA_InitTypeDef RCC_PLLInitTypeDef TIM_HallSensor_InitTypeDef __SPI_HandleTypeDef
DMA_InitTypeDef IWDG_HandleTypeDef RNG_HandleTypeDef TIM_HandleTypeDef
F
IWDG_InitTypeDef RTC_AlarmTypeDef TIM_IC_InitTypeDef
L
RTC_DateTypeDef TIM_MasterConfigTypeDef
FLASH_AdvOBProgramInitTypeDef RTC_HandleTypeDef TIM_OC_InitTypeDef
LPTIM_ClockConfigTypeDef
A | C | D | F | G | I | L | M | P | R | S | T | U | W | _
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: C:/SVN/__HAL/STM32F4xx_HAL_Driver/branches/V1.4.4/Drivers/STM32F4xx_HAL_Driver/ Directory Reference

  • Drivers
  • STM32F4xx_HAL_Driver
STM32F4xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: C:/SVN/__HAL/STM32F4xx_HAL_Driver/branches/V1.4.4/Drivers/STM32F4xx_HAL_Driver/Inc/ Directory Reference

  • Drivers
  • STM32F4xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32f4xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32f4xx_hal_adc.h [code]

Header file containing functions prototypes of ADC HAL library.

file | stm32f4xx_hal_adc_ex.h [code]

Header file of ADC HAL module.

file | stm32f4xx_hal_can.h [code]

Header file of CAN HAL module.

file | stm32f4xx_hal_cec.h [code]

Header file of CEC HAL module.

file | stm32f4xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32f4xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32f4xx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32f4xx_hal_cryp_ex.h [code]

Header file of CRYP HAL Extension module.

file | stm32f4xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32f4xx_hal_dac_ex.h [code]
file | stm32f4xx_hal_dcmi.h [code]

Header file of DCMI HAL module.

file | stm32f4xx_hal_dcmi_ex.h [code]

Header file of DCMI Extension HAL module.

file | stm32f4xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32f4xx_hal_dma2d.h [code]

Header file of DMA2D HAL module.

file | stm32f4xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32f4xx_hal_dsi.h [code]

Header file of DSI HAL module.

file | stm32f4xx_hal_eth.h [code]

Header file of ETH HAL module.

file | stm32f4xx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32f4xx_hal_flash_ex.h [code]

Header file of FLASH HAL Extension module.

file | stm32f4xx_hal_flash_ramfunc.h [code]

Header file of FLASH RAMFUNC driver.

file | stm32f4xx_hal_fmpi2c.h [code]

Header file of FMPI2C HAL module.

file | stm32f4xx_hal_fmpi2c_ex.h [code]

Header file of FMPI2C HAL Extended module.

file | stm32f4xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32f4xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extension module.

file | stm32f4xx_hal_hash.h [code]

Header file of HASH HAL module.

file | stm32f4xx_hal_hash_ex.h [code]

Header file of HASH HAL Extension module.

file | stm32f4xx_hal_hcd.h [code]

Header file of HCD HAL module.

file | stm32f4xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32f4xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extension module.

file | stm32f4xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32f4xx_hal_i2s_ex.h [code]

Header file of I2S HAL module.

file | stm32f4xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32f4xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32f4xx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32f4xx_hal_ltdc.h [code]

Header file of LTDC HAL module.

file | stm32f4xx_hal_ltdc_ex.h [code]

Header file of LTDC HAL Extension module.

file | stm32f4xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32f4xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32f4xx_hal_pccard.h [code]

Header file of PCCARD HAL module.

file | stm32f4xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32f4xx_hal_pcd_ex.h [code]

Header file of PCD HAL module.

file | stm32f4xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32f4xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extension module.

file | stm32f4xx_hal_qspi.h [code]

Header file of QSPI HAL module.

file | stm32f4xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32f4xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extension module.

file | stm32f4xx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32f4xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32f4xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extension module.

file | stm32f4xx_hal_sai.h [code]

Header file of SAI HAL module.

file | stm32f4xx_hal_sai_ex.h [code]

Header file of SAI Extension HAL module.

file | stm32f4xx_hal_sd.h [code]

Header file of SD HAL module.

file | stm32f4xx_hal_sdram.h [code]

Header file of SDRAM HAL module.

file | stm32f4xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32f4xx_hal_spdifrx.h [code]

Header file of SPDIFRX HAL module.

file | stm32f4xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32f4xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32f4xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32f4xx_hal_tim_ex.h [code]

Header file of TIM HAL Extension module.

file | stm32f4xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32f4xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32f4xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: C:/SVN/__HAL/STM32F4xx_HAL_Driver/branches/V1.4.4/Drivers/ Directory Reference

  • Drivers
Drivers Directory Reference

Directories

directory STM32F4xx_HAL_Driver
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: C:/SVN/__HAL/STM32F4xx_HAL_Driver/branches/V1.4.4/Drivers/STM32F4xx_HAL_Driver/Src/ Directory Reference

  • Drivers
  • STM32F4xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32f4xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32f4xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions.

file | stm32f4xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions.

file | stm32f4xx_hal_can.c [code]

This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f4xx_hal_cec.c [code]

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32f4xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f4xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

file | stm32f4xx_hal_cryp_ex.c [code]

Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions.

file | stm32f4xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_dac_ex.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions.

file | stm32f4xx_hal_dcmi.c [code]

DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f4xx_hal_dcmi_ex.c [code]

DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions.

file | stm32f4xx_hal_dma.c [code]

DMA HAL module driver.

file | stm32f4xx_hal_dma2d.c [code]

DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_dma_ex.c [code]

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

file | stm32f4xx_hal_dsi.c [code]

DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_eth.c [code]

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32f4xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions.

file | stm32f4xx_hal_flash_ramfunc.c [code]

FLASH RAMFUNC module driver. This file provides a FLASH firmware functions which should be executed from internal SRAM + Stop/Start the flash interface while System Run + Enable/Disable the flash sleep while System Run.

file | stm32f4xx_hal_fmpi2c.c [code]

FMPI2C HAL module driver.

file | stm32f4xx_hal_fmpi2c_ex.c [code]

FMPI2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of FMPI2C Extended peripheral: + Extended features functions.

file | stm32f4xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32f4xx_hal_hash.c [code]

HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions.

file | stm32f4xx_hal_hash_ex.c [code]

HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm.

file | stm32f4xx_hal_hcd.c [code]

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_i2c_ex.c [code]

I2C Extension HAL module driver. This file provides firmware functions to manage the following functionalities of I2C extension peripheral: + Extension features functions.

file | stm32f4xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_i2s_ex.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions.

file | stm32f4xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods.

file | stm32f4xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Configuration functions + IO operation functions + Peripheral State functions.

file | stm32f4xx_hal_lptim.c [code]

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

file | stm32f4xx_hal_ltdc.c [code]

LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_ltdc_ex.c [code]

LTDC Extension HAL module driver.

file | stm32f4xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32f4xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32f4xx_hal_pccard.c [code]

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device.

file | stm32f4xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_pcd_ex.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32f4xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f4xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions.

file | stm32f4xx_hal_qspi.c [code]

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

file | stm32f4xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f4xx_hal_rcc_ex.c [code]

Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

file | stm32f4xx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_rtc_ex.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions.

file | stm32f4xx_hal_sai.c [code]

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_sai_ex.c [code]

SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions.

file | stm32f4xx_hal_sd.c [code]

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_sdram.c [code]

SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device.

file | stm32f4xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_spdifrx.c [code]

This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

file | stm32f4xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f4xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32f4xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

file | stm32f4xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration.

file | stm32f4xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f4xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32f4xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions.

Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Drivers
    • STM32F4xx_HAL_Driver
      • Inc
      • Src
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32f4xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32f4xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32f4xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions + IO operation functions + State and errors functions
stm32f4xx_hal_adc.h [code] | Header file containing functions prototypes of ADC HAL library
stm32f4xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the ADC extension peripheral: + Extended features functions
stm32f4xx_hal_adc_ex.h [code] | Header file of ADC HAL module
stm32f4xx_hal_can.c [code] | This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f4xx_hal_can.h [code] | Header file of CAN HAL module
stm32f4xx_hal_cec.c [code] | CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32f4xx_hal_cec.h [code] | Header file of CEC HAL module
stm32f4xx_hal_conf.h [code] |
stm32f4xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions
stm32f4xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32f4xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_crc.h [code] | Header file of CRC HAL module
stm32f4xx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + AES processing functions + DES processing functions + TDES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions
stm32f4xx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32f4xx_hal_cryp_ex.c [code] | Extended CRYP HAL module driver This file provides firmware functions to manage the following functionalities of CRYP extension peripheral: + Extended AES processing functions
stm32f4xx_hal_cryp_ex.h [code] | Header file of CRYP HAL Extension module
stm32f4xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f4xx_hal_dac.h [code] | Header file of DAC HAL module
stm32f4xx_hal_dac_ex.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions
stm32f4xx_hal_dac_ex.h [code] |
stm32f4xx_hal_dcmi.c [code] | DCMI HAL module driver This file provides firmware functions to manage the following functionalities of the Digital Camera Interface (DCMI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f4xx_hal_dcmi.h [code] | Header file of DCMI HAL module
stm32f4xx_hal_dcmi_ex.c [code] | DCMI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of DCMI extension peripheral: + Extension features functions
stm32f4xx_hal_dcmi_ex.h [code] | Header file of DCMI Extension HAL module
stm32f4xx_hal_dma.c [code] | DMA HAL module driver
stm32f4xx_hal_dma.h [code] | Header file of DMA HAL module
stm32f4xx_hal_dma2d.c [code] | DMA2D HAL module driver. This file provides firmware functions to manage the following functionalities of the DMA2D peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f4xx_hal_dma2d.h [code] | Header file of DMA2D HAL module
stm32f4xx_hal_dma_ex.c [code] | DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions
stm32f4xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32f4xx_hal_dsi.c [code] | DSI HAL module driver. This file provides firmware functions to manage the following functionalities of the DSI peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f4xx_hal_dsi.h [code] | Header file of DSI HAL module
stm32f4xx_hal_eth.c [code] | ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f4xx_hal_eth.h [code] | Header file of ETH HAL module
stm32f4xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32f4xx_hal_flash.h [code] | Header file of FLASH HAL module
stm32f4xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extension peripheral: + Extended programming operations functions
stm32f4xx_hal_flash_ex.h [code] | Header file of FLASH HAL Extension module
stm32f4xx_hal_flash_ramfunc.c [code] | FLASH RAMFUNC module driver. This file provides a FLASH firmware functions which should be executed from internal SRAM + Stop/Start the flash interface while System Run + Enable/Disable the flash sleep while System Run
stm32f4xx_hal_flash_ramfunc.h [code] | Header file of FLASH RAMFUNC driver
stm32f4xx_hal_fmpi2c.c [code] | FMPI2C HAL module driver
stm32f4xx_hal_fmpi2c.h [code] | Header file of FMPI2C HAL module
stm32f4xx_hal_fmpi2c_ex.c [code] | FMPI2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of FMPI2C Extended peripheral: + Extended features functions
stm32f4xx_hal_fmpi2c_ex.h [code] | Header file of FMPI2C HAL Extended module
stm32f4xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32f4xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32f4xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extension module
stm32f4xx_hal_hash.c [code] | HASH HAL module driver. This file provides firmware functions to manage the following functionalities of the HASH peripheral: + Initialization and de-initialization functions + HASH/HMAC Processing functions by algorithm using polling mode + HASH/HMAC functions by algorithm using interrupt mode + HASH/HMAC functions by algorithm using DMA mode + Peripheral State functions
stm32f4xx_hal_hash.h [code] | Header file of HASH HAL module
stm32f4xx_hal_hash_ex.c [code] | HASH HAL Extension module driver. This file provides firmware functions to manage the following functionalities of HASH peripheral: + Extended HASH processing functions based on SHA224 Algorithm + Extended HASH processing functions based on SHA256 Algorithm
stm32f4xx_hal_hash_ex.h [code] | Header file of HASH HAL Extension module
stm32f4xx_hal_hcd.c [code] | HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_hcd.h [code] | Header file of HCD HAL module
stm32f4xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32f4xx_hal_i2c_ex.c [code] | I2C Extension HAL module driver. This file provides firmware functions to manage the following functionalities of I2C extension peripheral: + Extension features functions
stm32f4xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extension module
stm32f4xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f4xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32f4xx_hal_i2s_ex.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of I2S extension peripheral: + Extension features Functions
stm32f4xx_hal_i2s_ex.h [code] | Header file of I2S HAL module
stm32f4xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization methods + IO operation methods + Peripheral Control methods
stm32f4xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32f4xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Configuration functions + IO operation functions + Peripheral State functions
stm32f4xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32f4xx_hal_lptim.c [code] | LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions
stm32f4xx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32f4xx_hal_ltdc.c [code] | LTDC HAL module driver. This file provides firmware functions to manage the following functionalities of the LTDC peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f4xx_hal_ltdc.h [code] | Header file of LTDC HAL module
stm32f4xx_hal_ltdc_ex.c [code] | LTDC Extension HAL module driver
stm32f4xx_hal_ltdc_ex.h [code] | Header file of LTDC HAL Extension module
stm32f4xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32f4xx_hal_nand.h [code] | Header file of NAND HAL module
stm32f4xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32f4xx_hal_nor.h [code] | Header file of NOR HAL module
stm32f4xx_hal_pccard.c [code] | PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device
stm32f4xx_hal_pccard.h [code] | Header file of PCCARD HAL module
stm32f4xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32f4xx_hal_pcd_ex.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32f4xx_hal_pcd_ex.h [code] | Header file of PCD HAL module
stm32f4xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32f4xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32f4xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of PWR extension peripheral: + Peripheral Extended features functions
stm32f4xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extension module
stm32f4xx_hal_qspi.c [code] | QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality
stm32f4xx_hal_qspi.h [code] | Header file of QSPI HAL module
stm32f4xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32f4xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32f4xx_hal_rcc_ex.c [code] | Extension RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions
stm32f4xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extension module
stm32f4xx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_rng.h [code] | Header file of RNG HAL module
stm32f4xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32f4xx_hal_rtc_ex.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extension Control functions + Extension RTC features functions
stm32f4xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extension module
stm32f4xx_hal_sai.c [code] | SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_sai.h [code] | Header file of SAI HAL module
stm32f4xx_hal_sai_ex.c [code] | SAI Extension HAL module driver. This file provides firmware functions to manage the following functionalities of SAI extension peripheral: + Extension features functions
stm32f4xx_hal_sai_ex.h [code] | Header file of SAI Extension HAL module
stm32f4xx_hal_sd.c [code] | SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_sd.h [code] | Header file of SD HAL module
stm32f4xx_hal_sdram.c [code] | SDRAM HAL module driver. This file provides a generic firmware to drive SDRAM memories mounted as external device
stm32f4xx_hal_sdram.h [code] | Header file of SDRAM HAL module
stm32f4xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f4xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32f4xx_hal_spdifrx.c [code] | This file provides firmware functions to manage the following functionalities of the SPDIFRX audio interface: + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management
stm32f4xx_hal_spdifrx.h [code] | Header file of SPDIFRX HAL module
stm32f4xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f4xx_hal_spi.h [code] | Header file of SPI HAL module
stm32f4xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32f4xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32f4xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration
stm32f4xx_hal_tim.h [code] | Header file of TIM HAL module
stm32f4xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer extension peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration
stm32f4xx_hal_tim_ex.h [code] | Header file of TIM HAL Extension module
stm32f4xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f4xx_hal_uart.h [code] | Header file of UART HAL module
stm32f4xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32f4xx_hal_usart.h [code] | Header file of USART HAL module
stm32f4xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions
stm32f4xx_hal_wwdg.h [code] | Header file of WWDG HAL module
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STM32F410Rx HAL User Manual: ADC

Modules
ADC
STM32F4xx_HAL_Driver

ADC driver modules. More...

Modules

ADC Exported Functions
ADC Exported Types
ADC Exported Constants
ADC Exported Macros
ADC Private Constants
ADC Private Macros
ADC Private Functions

Detailed Description

ADC driver modules.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC Clock Prescaler
ADC Delay Between 2 Sampling Phases
ADC Resolution
ADC External Trigger Edge Regular
ADC External Trigger Source Regular
ADC Data Align
ADC Common Channels
ADC Sampling Times
ADC EOC Selection
ADC Event Type
ADC Analog Watchdog Selection
ADC Interrupts Definition
ADC Flags Definition
ADC Channels Type
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STM32F410Rx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

ADC Peripheral State functions

ADC Peripheral State functions.

ADC Private Functions
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STM32F410Rx HAL User Manual: ADCEx

Modules
ADCEx
STM32F4xx_HAL_Driver

ADC Extended driver modules. More...

Modules

ADC Exported Functions
ADC Exported Types
ADC Exported Constants
ADC Exported Macros
ADC Private Constants
ADC Private Macros
ADC Private Functions

Detailed Description

ADC Extended driver modules.

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STM32F410Rx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADCEx

Modules

ADC Common Mode
ADC Direct Memory Access Mode For Multi Mode
ADC External Trigger Edge Injected
ADC External Trigger Source Injected
ADC Injected Rank
ADC Specific Channels
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STM32F410Rx HAL User Manual: ADC Exported Types

Data Structures
ADC Exported Types
ADCEx

Data Structures

struct | ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
struct | ADC_MultiModeTypeDef
ADC Configuration multi-mode structure definition. More...
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STM32F410Rx HAL User Manual: CORTEX

Modules
CORTEX
STM32F4xx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Functions
Cortex Exported Types
CORTEX Exported Constants
CORTEX Private Macros
CORTEX Private Functions

CORTEX private functions.

Detailed Description

CORTEX HAL module driver.

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STM32F410Rx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX _SysTick clock source
MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
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STM32F410Rx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

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STM32F410Rx HAL User Manual: Cortex Exported Types

Modules
Cortex Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

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STM32F410Rx HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
Cortex Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

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STM32F410Rx HAL User Manual: CRC

Modules
CRC
STM32F4xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Exported Types
CRC Exported Macros
CRC Exported Functions
CRC Private Types
CRC Private Defines
CRC Private Variables
CRC Private Constants
CRC Private Macros
CRC Private Functions Prototypes
CRC Private Functions

Detailed Description

CRC HAL module driver.

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STM32F410Rx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

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STM32F410Rx HAL User Manual: CRC Exported Types

Modules
CRC Exported Types
CRC

Modules

CRC State Structure definition
CRC Handle Structure definition
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STM32F410Rx HAL User Manual: CRC Handle Structure definition

Data Structures
CRC Handle Structure definition
CRC Exported Types

Data Structures

struct CRC_HandleTypeDef
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STM32F410Rx HAL User Manual: DAC

Modules
DAC
STM32F4xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Functions
DAC Exported Types
DAC Exported Constants
DAC Exported Macros
DAC Private Constants
DAC Private Macros
DAC Private Functions

Detailed Description

DAC driver modules.

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STM32F410Rx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC Trigger Selection
DAC Output Buffer
DAC Channel Selection
DAC Data Alignment
DAC Flags Definition
DAC IT Definition
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STM32F410Rx HAL User Manual: DACEx

Modules
DACEx
STM32F4xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Exported Functions
DAC Exported Constants
DAC Private Constants
DAC Private Macros
DAC Private Functions

Detailed Description

DAC driver modules.

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STM32F410Rx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DACEx

Modules

DAC LFS Run Mask Triangle Amplitude
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STM32F410Rx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

DMA Exported constants. More...

Modules

DMA Error Code

DMA Error Code.

DMA Channel selection

DMA channel selection.

DMA Data transfer direction

DMA data transfer direction.

DMA Peripheral incremented mode

DMA peripheral incremented mode.

DMA Memory incremented mode

DMA memory incremented mode.

DMA Peripheral data size

DMA peripheral data size.

DMA Memory data size

DMA memory data size.

DMA mode

DMA mode.

DMA Priority level

DMA priority levels.

DMA FIFO direct mode

DMA FIFO direct mode.

DMA FIFO threshold level

DMA FIFO level.

DMA Memory burst

DMA memory burst.

DMA Peripheral burst

DMA peripheral burst.

DMA interrupt enable definitions

DMA interrupts definition.

DMA flag definitions

DMA flag definitions.

Detailed Description

DMA Exported constants.

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STM32F410Rx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

DMA Exported functions. More...

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

I/O operation functions

I/O operation functions.

Peripheral State functions

Peripheral State functions.

Detailed Description

DMA Exported functions.

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STM32F410Rx HAL User Manual: DMAEx

Modules
DMAEx
STM32F4xx_HAL_Driver

DMA Extended HAL module driver. More...

Modules

DMAEx Exported Types

DMAEx Exported types.

DMAEx Exported Functions

DMAEx Exported functions.

DMAEx Private Functions

DMAEx Private functions.

Detailed Description

DMA Extended HAL module driver.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: DMAEx Exported Functions

Modules
DMAEx Exported Functions
DMAEx

DMAEx Exported functions. More...

Modules

Extended features functions

Extended features functions.

Detailed Description

DMAEx Exported functions.

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STM32F410Rx HAL User Manual: FLASH

Modules
FLASH
STM32F4xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros
FLASH Private Variables
FLASH Private Constants
FLASH Private Macros
FLASH Private Functions

Detailed Description

FLASH HAL module driver.

Generated on Fri Jan 29 2016 15:36:54 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error Code

FLASH Error Code.

FLASH Type Program
FLASH Flag definition

Flag definition.

FLASH Interrupt definition

FLASH Interrupt definition.

FLASH Program Parallelism
FLASH Keys
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STM32F410Rx HAL User Manual: FLASH Private Macros

Modules
FLASH Private Macros
FLASH

Modules

FLASH Private macros to check input parameters
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STM32F410Rx HAL User Manual: FLASH RAMFUNC

Modules
FLASH RAMFUNC
STM32F4xx_HAL_Driver

FLASH functions executed from RAM. More...

Modules

FLASH RAMFUNC Exported Functions

Detailed Description

FLASH functions executed from RAM.

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STM32F410Rx HAL User Manual: FLASH RAMFUNC Exported Functions

Modules
FLASH RAMFUNC Exported Functions
FLASH RAMFUNC

Modules

Peripheral features functions executed from internal RAM

Peripheral Extended features functions.

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STM32F410Rx HAL User Manual: FLASHEx

Modules
FLASHEx
STM32F4xx_HAL_Driver

FLASH HAL Extension module driver. More...

Modules

FLASHEx Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Private Constants
FLASH Private Macros
FLASH Private Functions
FLASHEx_Private_Variables

Detailed Description

FLASH HAL Extension module driver.

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STM32F410Rx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASHEx

Modules

FLASH Type Erase
FLASH Voltage Range
FLASH WRP State
FLASH Option Type
FLASH Option Bytes Read Protection
FLASH Option Bytes IWatchdog
FLASH Option Bytes nRST_STOP
FLASH Option Bytes nRST_STDBY
FLASH BOR Reset Level
FLASH PCROP State
FLASH Advanced Option Type
FLASH Latency
FLASH Banks
FLASH Mass Erase bit
FLASH Sectors
FLASH Option Bytes Write Protection
FLASH Option Bytes PC ReadWrite Protection
FLASH Dual Boot
FLASH Selection Protection Mode
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STM32F410Rx HAL User Manual: FLASH Exported Types

Data Structures
FLASH Exported Types
FLASHEx

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_AdvOBProgramInitTypeDef
FLASH Advanced Option Bytes Program structure definition. More...
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STM32F410Rx HAL User Manual: FLASH Private Macros

Modules
FLASH Private Macros
FLASHEx

Modules

FLASH Private macros to check input parameters
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STM32F410Rx HAL User Manual: FMPI2C

Modules
FMPI2C
STM32F4xx_HAL_Driver

FMPI2C HAL module driver. More...

Modules

FMPI2C Private Define
FMPI2C Private Functions
FMPI2C Exported Functions
FMPI2C Exported Types
FMPI2C Exported Constants
FMPI2C Exported Macros
FMPI2C Private Constants
FMPI2C Private Macros

Detailed Description

FMPI2C HAL module driver.

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STM32F410Rx HAL User Manual: FMPI2C Configuration Structure definition

Data Structures
FMPI2C Configuration Structure definition
FMPI2C Exported Types

FMPI2C Configuration Structure definition. More...

Data Structures

struct FMPI2C_InitTypeDef

Detailed Description

FMPI2C Configuration Structure definition.

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STM32F410Rx HAL User Manual: FMPI2C Exported Constants

Modules
FMPI2C Exported Constants
FMPI2C

Modules

FMPI2C addressing mode
FMPI2C dual addressing mode
FMPI2C own address2 masks
FMPI2C general call addressing mode
FMPI2C nostretch mode
FMPI2C Memory Address Size
FMPI2C XferDirection definition
FMPI2C ReloadEndMode definition
FMPI2C StartStopMode definition
FMPI2C Interrupt configuration definition

FMPI2C Interrupt definition Elements values convention: 0xXXXXXXXX.

FMPI2C Flag definition
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STM32F410Rx HAL User Manual: FMPI2C Exported Functions

Modules
FMPI2C Exported Functions
FMPI2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

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STM32F410Rx HAL User Manual: FMPI2C Exported Types

Modules
FMPI2C Exported Types
FMPI2C

Modules

FMPI2C Configuration Structure definition

FMPI2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

FMPI2C Error Code definition

FMPI2C Error Code definition.

FMPI2C XferOptions definition
FMPI2C handle Structure definition

FMPI2C handle Structure definition.

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STM32F410Rx HAL User Manual: FMPI2C handle Structure definition

Data Structures
FMPI2C handle Structure definition
FMPI2C Exported Types

FMPI2C handle Structure definition. More...

Data Structures

struct FMPI2C_HandleTypeDef

Detailed Description

FMPI2C handle Structure definition.

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STM32F410Rx HAL User Manual: FMPI2CEx

Modules
FMPI2CEx
STM32F4xx_HAL_Driver

FMPI2C Extended HAL module driver. More...

Modules

FMPI2C Extended Exported Functions
FMPI2C Extended Exported Constants

Detailed Description

FMPI2C Extended HAL module driver.

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STM32F410Rx HAL User Manual: FMPI2C Extended Exported Constants

Modules
FMPI2C Extended Exported Constants
FMPI2CEx

Modules

FMPI2C Extended Analog Filter
FMPI2C Extended Fast Mode Plus
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STM32F410Rx HAL User Manual: FMPI2C Extended Exported Functions

Modules
FMPI2C Extended Exported Functions
FMPI2CEx

Modules

Extended features functions

Extended features functions.

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STM32F410Rx HAL User Manual: GPIO

Modules
GPIO
STM32F4xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Exported Functions
GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions

Detailed Description

GPIO HAL module driver.

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STM32F410Rx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins define
GPIO mode define

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed define

GPIO Output Maximum frequency.

GPIO pull define

GPIO Pull-Up or Pull-Down Activation.

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STM32F410Rx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

GPIO Read and Write.

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STM32F410Rx HAL User Manual: GPIOEx

Modules
GPIOEx
STM32F4xx_HAL_Driver

Modules

GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions
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STM32F410Rx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIOEx

Modules

GPIO Alternate Function Selection
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STM32F410Rx HAL User Manual: GPIO Private Macros

Modules
GPIO Private Macros
GPIOEx

Modules

GPIO Get Port Index
GPIO Check Alternate Function
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STM32F410Rx HAL User Manual: HAL

Modules
HAL
STM32F4xx_HAL_Driver

HAL module driver. More...

Modules

HAL Exported Functions
HAL Exported Macros
HAL Private Variables
HAL Private Constants

Detailed Description

HAL module driver.

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STM32F410Rx HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

Initialization and de-initialization Functions

Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

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STM32F410Rx HAL User Manual: I2C

Modules
I2C
STM32F4xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros
I2C Private Functions

Detailed Description

I2C HAL module driver.

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STM32F410Rx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Error Code

I2C Error Code.

I2C duty cycle in fast mode
I2C addressing mode
I2C dual addressing mode
I2C general call addressing mode
I2C nostretch mode
I2C Memory Address Size
I2C XferDirection definition
I2C XferOptions definition
I2C Interrupt configuration definition
I2C Flag definition
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STM32F410Rx HAL User Manual: I2S

Modules
I2S
STM32F4xx_HAL_Driver

I2S HAL module driver. More...

Modules

I2S Exported Functions
I2S Exported Types
I2S Exported Constants
I2S Exported Macros
I2S Private Constants
I2S Private Macros
I2S Private Functions

Detailed Description

I2S HAL module driver.

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STM32F410Rx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

I2S Error Code

I2S Error Code.

I2S Mode
I2S Standard
I2S Data Format
I2S Mclk Output
I2S Audio Frequency
I2S FullDuplex Mode
I2S Clock Polarity
I2S Interrupts Definition
I2S Flags Definition
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STM32F410Rx HAL User Manual: I2SEx

Modules
I2SEx
STM32F4xx_HAL_Driver

I2S HAL module driver. More...

Modules

I2S Exported Functions
I2S Exported Types
I2S Exported Constants
I2S Exported Macros
I2S Private Constants
I2S Private Macros
I2S Private Functions

Detailed Description

I2S HAL module driver.

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STM32F410Rx HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2SEx

Modules

I2S Clock Source
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STM32F410Rx HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2SEx

Modules

Extension features functions

Extension features functions.

I2SEx_Exported_Functions_Group1
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STM32F410Rx HAL User Manual: IRDA

Modules
IRDA
STM32F4xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IrDA Exported Functions
IRDA Exported Types
IRDA Exported constants
IRDA Exported Macros
IRDA Private Constants
IRDA Private Macros
IRDA Private Functions

Detailed Description

HAL IRDA module driver.

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STM32F410Rx HAL User Manual: IRDA Exported constants

Modules
IRDA Exported constants
IRDA

Modules

IRDA Error Code

IRDA Error Code.

IRDA Word Length
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupt Definitions

Elements values convention: 0xY000XXXX.

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STM32F410Rx HAL User Manual: IWDG

Modules
IWDG
STM32F4xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Exported Functions
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Private Macros
IWDG Private Constants

Detailed Description

IWDG HAL module driver.

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STM32F410Rx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Registers BitMask

IWDG registers bit mask.

IWDG Flag definition
IWDG Prescaler
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STM32F410Rx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral State functions

Peripheral State functions.

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STM32F410Rx HAL User Manual: LPTIM

Modules
LPTIM
STM32F4xx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Private Types
LPTIM Private Defines
LPTIM Exported Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros
LPTIM Private Functions
LPTIM Private Functions Prototypes

Detailed Description

LPTIM HAL module driver.

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STM32F410Rx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Flag Definition
LPTIM Interrupts Definition
Register Definition
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STM32F410Rx HAL User Manual: LTDCEx

Modules
LTDCEx
STM32F4xx_HAL_Driver

LTDC HAL module driver. More...

Modules

LTDC Extended Exported Functions

Detailed Description

LTDC HAL module driver.

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STM32F410Rx HAL User Manual: LTDC Extended Exported Functions

Modules
LTDC Extended Exported Functions
LTDCEx

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

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STM32F410Rx HAL User Manual: PWR

Modules
PWR
STM32F4xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Exported Functions
PWR Exported Types
PWR Exported Constants
PWR Exported Macro
PWR Private Constants
PWR Private Macros

Detailed Description

PWR HAL module driver.

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STM32F410Rx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

PWR WakeUp Pins
PWR PVD detection level
PWR PVD Mode
PWR Regulator state in SLEEP/STOP mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR Flag
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STM32F410Rx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

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STM32F410Rx HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32F410Rx HAL User Manual: PWR Private Constants

Modules
PWR Private Constants
PWR

Modules

PWR PVD Mode Mask
PWR PVD EXTI Line
PWR Register alias address
PWR CR Register alias address
PWR CSR Register alias address
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STM32F410Rx HAL User Manual: PWR Private Macros

Modules
PWR Private Macros
PWR

Modules

PWR Private macros to check input parameters
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STM32F410Rx HAL User Manual: PWREx

Modules
PWREx
STM32F4xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWREx Exported Functions
PWREx Exported Constants
PWREx Private Constants
PWREx Private Macros

Detailed Description

PWR HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWREx Exported Functions

Modules
PWREx Exported Functions
PWREx

Modules

Peripheral Extended features functions

Peripheral Extended features functions.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: PWREx Private Macros

Modules
PWREx Private Macros
PWREx

Modules

PWREx Private macros to check input parameters
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STM32F410Rx HAL User Manual: RCC

Modules
RCC
STM32F4xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Variables
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Private Constants
RCC Private Macros

Detailed Description

RCC HAL module driver.

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STM32F410Rx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Type
HSE Config
LSE Config
HSI Config
LSI Config
PLL Config
PLLP Clock Divider
PLL Clock Source
System Clock Type
System Clock Source
System Clock Source Status
AHB Clock Source
APB1/APB2 Clock Source
RTC Clock Source
MCO Index
MCO1 Clock Source
MCOx Clock Prescaler
Interrupts
Flags

Elements values convention: 0XXYYYYYb.

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STM32F410Rx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

AHB1 Peripheral Clock Enable Disable

Enable or disable the AHB1 peripheral clock.

AHB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB1 peripheral clock.

APB1 Peripheral Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock.

APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock.

APB2 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB2 peripheral clock.

AHB1 Force Release Reset

Force or release AHB1 peripheral reset.

APB1 Force Release Reset

Force or release APB1 peripheral reset.

APB2 Force Release Reset

Force or release APB2 peripheral reset.

AHB1 Peripheral Low Power Enable Disable

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

APB1 Peripheral Low Power Enable Disable

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

APB2 Peripheral Low Power Enable Disable

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

HSI Configuration
LSI Configuration
HSE Configuration
LSE Configuration
RTC Clock Configuration
PLL Configuration
Get Clock source
RCC Extended MCOx Clock Config
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

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STM32F410Rx HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
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STM32F410Rx HAL User Manual: RCC Private Macros

Modules
RCC Private Macros
RCC

Modules

RCC Private macros to check input parameters
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STM32F410Rx HAL User Manual: RCCEx

Modules
RCCEx
STM32F4xx_HAL_Driver

RCCEx HAL module driver. More...

Modules

RCCEx Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros
RCCEx Private Constants
RCCEx Private Macros

Detailed Description

RCCEx HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

RCC Periph Clock Selection
RCC PLLSAI DIVR
RCC PLLI2SP Clock Divider
RCC PLLSAIP Clock Divider
RCC I2S APB Clock Source
RCC FMPI2C1 Clock Source
RCC LPTIM1 Clock Source
RCC TIM PRescaler Selection
RCC LSE Dual Mode Selection
MCO2 Clock Source
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STM32F410Rx HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
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STM32F410Rx HAL User Manual: RCCEx Private Constants

Modules
RCCEx Private Constants
RCCEx

Modules

RCC BitAddress AliasRegion

RCC registers bit address in the alias region.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RCCEx Private Macros

Modules
RCCEx Private Macros
RCCEx

Modules

RCC Private macros to check input parameters
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STM32F410Rx HAL User Manual: RNG

Modules
RNG
STM32F4xx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG Exported Types
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG Private Types
RNG Private Defines
RNG Private Variables
RNG Private Constants
RNG Private Macros
RNG Private Functions Prototypes
RNG Private Functions

Detailed Description

RNG HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

RNG Interrupt definition
RNG Flag definition
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STM32F410Rx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RNG Exported Types

Modules
RNG Exported Types
RNG

Modules

RNG State Structure definition
RNG Handle Structure definition
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STM32F410Rx HAL User Manual: RNG Handle Structure definition

Data Structures
RNG Handle Structure definition
RNG Exported Types

Data Structures

struct RNG_HandleTypeDef
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STM32F410Rx HAL User Manual: RTC

Modules
RTC
STM32F4xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Functions
RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Private Constants
RTC Private Macros
RTC Private Functions

Detailed Description

RTC HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTC Output Selection Definitions
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC AM PM Definitions
RTC DayLight Saving Definitions
RTC Store Operation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC Alarm Date WeekDay Definitions
RTC Alarm Mask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flags Definitions
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STM32F410Rx HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
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STM32F410Rx HAL User Manual: RTCEx

Modules
RTCEx
STM32F4xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTCEx Exported Functions
RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Private Constants
RTCEx Private Macros

Detailed Description

RTC HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTC Backup Registers Definitions
RTC TimeStamp Edges Definitions
RTC Tamper Pins Definitions
RTC tamper Pins Selection
RTC TimeStamp Pins Selection
RTC Tamper Triggers Definitions
RTC Tamper Filter Definitions
RTC Tamper Sampling Frequencies Definitions
RTC Tamper Pin Precharge Duration Definitions
RTC Tamper TimeStamp On Tamper Detection Definitions
RTC Tamper Pull Up Definitions
RTC Wake-up Timer Definitions
RTC Digital Calib Definitions
RTC Smooth Calib Period Definitions
RTC Smooth Calib Plus Pulses Definitions
RTC Add 1 Second Parameter Definitions
RTC Calib Output Selection Definitions
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STM32F410Rx HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

RTC TimeStamp and Tamper functions

RTC TimeStamp and Tamper functions.

RTC Wake-up functions

RTC Wake-up functions.

Extension Peripheral Control functions

Extension Peripheral Control functions.

Extended features functions

Extended features functions.

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STM32F410Rx HAL User Manual: RTCEx Exported Macros

Modules
RTCEx Exported Macros
RTCEx

Modules

RTC WakeUp Timer
RTC Timestamp
RTC Tamper
EXTI RTC Tamper Timestamp EXTI
RTC Calibration
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STM32F410Rx HAL User Manual: RTCEx Exported Types

Data Structures
RTCEx Exported Types
RTCEx

Data Structures

struct RTC_TamperTypeDef
RTC Tamper structure definition. More...
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STM32F410Rx HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
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STM32F410Rx HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32F4xx_HAL_Driver

HAL USART SMARTCARD module driver. More...

Modules

SMARTCARD Exported Functions
SMARTCARD Exported Types
SMARTCARD Exported constants
SMARTCARD Exported Macros
SMARTCARD Private Constants
SMARTCARD Private Macros
SMARTCARD Private Functions

Detailed Description

HAL USART SMARTCARD module driver.

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STM32F410Rx HAL User Manual: SMARTCARD Exported constants

Modules
SMARTCARD Exported constants
SMARTCARD

Modules

SMARTCARD Error Code

SMARTCARD Error Code.

SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD NACK State
SMARTCARD DMA requests
SMARTCARD Prescaler
SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 0xY000XXXX.

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STM32F410Rx HAL User Manual: SPI

Modules
SPI
STM32F4xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros
SPI Private Functions

Private functions.

Detailed Description

SPI HAL module driver.

Generated on Fri Jan 29 2016 15:36:56 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI Interrupt Definition
SPI Flags Definition
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STM32F410Rx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

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STM32F410Rx HAL User Manual: STM32F4xx_HAL_Driver

Modules
STM32F4xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC driver modules.

ADCEx

ADC Extended driver modules.

CAN

CAN driver modules.

CEC

HAL CEC module driver.

CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRYP

CRYP HAL module driver.

CRYPEx

CRYP Extension HAL module driver.

DAC

DAC driver modules.

DACEx

DAC driver modules.

DCMI

DCMI HAL module driver.

DCMIEx

DCMI Extended HAL module driver.

DMA

DMA HAL module driver.

DMAEx

DMA Extended HAL module driver.

ETH

ETH HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH HAL Extension module driver.

FLASH RAMFUNC

FLASH functions executed from RAM.

FMPI2C

FMPI2C HAL module driver.

FMPI2CEx

FMPI2C Extended HAL module driver.

GPIO

GPIO HAL module driver.

GPIOEx
HASH

HASH HAL module driver.

HASHEx

HASH Extension HAL module driver.

HCD

HCD HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C HAL module driver.

I2S

I2S HAL module driver.

I2SEx

I2S HAL module driver.

IRDA

HAL IRDA module driver.

IWDG

IWDG HAL module driver.

LPTIM

LPTIM HAL module driver.

LTDC

LTDC HAL module driver.

LTDCEx

LTDC HAL module driver.

NOR

NOR driver modules.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR HAL module driver.

QSPI

HAL QSPI module driver.

RCC

RCC HAL module driver.

RCCEx

RCCEx HAL module driver.

RNG

RNG HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC HAL module driver.

SAI

SAI HAL module driver.

SAIEx

SAI Extension HAL module driver.

SDRAM

SDRAM driver modules.

SMARTCARD

HAL USART SMARTCARD module driver.

SPDIFRX

SPDIFRX HAL module driver.

SPI

SPI HAL module driver.

SRAM

SRAM driver modules.

TIM

TIM HAL module driver.

TIMEx

TIM HAL module driver.

UART

HAL UART module driver.

USART

HAL USART Synchronous module driver.

WWDG

WWDG HAL module driver.

DMA2D

DMA2D HAL module driver.

DSI
NAND
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STM32F410Rx HAL User Manual: TIM

Modules
TIM
STM32F4xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Macros
TIM Private Functions

Detailed Description

TIM HAL module driver.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Input Channel Polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Clock Division
TIM Output Compare and PWM modes
TIM Output Fast State
TIM Output Compare Polarity
TIM Output CompareN Polarity
TIM Output Compare Idle State
TIM Output Compare N Idle State
TIM Channel
TIM Input Capture Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM Interrupt definition
TIM Commutation Source
TIM DMA sources
TIM Event Source
TIM Flag definition
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Source
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR OffState Selection for Run mode state
TIM OSSI OffState Selection for Idle mode state
TIM Lock level
TIM Break Input State
TIM Break Polarity
TIM AOE Bit State
TIM Master Mode Selection
TIM Slave Mode
TIM Master Slave Mode
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Selection
TIM DMA Base address
TIM DMA Burst Length
DMA Handle index
Channel CC State
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STM32F410Rx HAL User Manual: TIM Private Macros

Modules
TIM Private Macros
TIM

Modules

TIM Private macros to check input parameters
TIM Mask Definition
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STM32F410Rx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIMEx

Modules

TIM Remap
TIM System Break Input
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STM32F410Rx HAL User Manual: TIM Exported Types

Data Structures
TIM Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break and Dead time configuration Structure definition. More...
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STM32F410Rx HAL User Manual: UART

Modules
UART
STM32F4xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Exported Functions
UART Exported Types
UART Exported constants
UART Exported Macros
UART Private Constants
UART Private Macros
UART Private Functions

Detailed Description

HAL UART module driver.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: UART Exported constants

Modules
UART Exported constants
UART

Modules

UART Error Code

UART Error Code.

UART Word Length
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART LIN Break Detection Length
UART Wakeup Functions
UART FLags

Elements values convention: 0xXXXX.

UART Interrupt Definitions

Elements values convention: 0xY000XXXX.

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STM32F410Rx HAL User Manual: USART

Modules
USART
STM32F4xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Exported Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Constants
USART Private Macros
USART Private Functions

Detailed Description

HAL USART Synchronous module driver.

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STM32F410Rx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error Code

USART Error Code.

USART Word Length
USART Number of Stop Bits
USART Parity
USART Mode
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART NACK State
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0xY000XXXX.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: WWDG

Modules
WWDG
STM32F4xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Exported Macros
WWDG Private Constants
WWDG Private Macros
WWDG Private Functions

Detailed Description

WWDG HAL module driver.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
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STM32F410Rx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Jan 29 2016 15:36:57 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: WWDG Private Constants

Modules
WWDG Private Constants
WWDG

Modules

WWDG BitAddress

WWDG registers bit address in the alias region.

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STM32F410Rx HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32F4xx_HAL_Driver
    • HAL
      • HAL Exported Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
      • HAL Exported Macros
        • Cortex Lockup Enable
        • PVD Lock
      • HAL Private Variables
      • HAL Private Constants
    • ADC
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • ADC Peripheral State functions
        • ADC Private Functions
      • ADC Exported Types
      • ADC Exported Constants
        • ADC Error Code
        • ADC Clock Prescaler
        • ADC Delay Between 2 Sampling Phases
        • ADC Resolution
        • ADC External Trigger Edge Regular
        • ADC External Trigger Source Regular
        • ADC Data Align
        • ADC Common Channels
        • ADC Sampling Times
        • ADC EOC Selection
        • ADC Event Type
        • ADC Analog Watchdog Selection
        • ADC Interrupts Definition
        • ADC Flags Definition
        • ADC Channels Type
      • ADC Exported Macros
      • ADC Private Constants
      • ADC Private Macros
      • ADC Private Functions
    • ADCEx
      • ADC Exported Functions
        • Extended features functions
      • ADC Exported Types
      • ADC Exported Constants
        • ADC Common Mode
        • ADC Direct Memory Access Mode For Multi Mode
        • ADC External Trigger Edge Injected
        • ADC External Trigger Source Injected
        • ADC Injected Rank
        • ADC Specific Channels
      • ADC Exported Macros
      • ADC Private Constants
      • ADC Private Macros
      • ADC Private Functions
    • CAN
    • CEC
    • CORTEX
      • CORTEX Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • Cortex Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX _SysTick clock source
        • MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Private Macros
      • CORTEX Private Functions
    • CRC
      • CRC Exported Types
        • CRC State Structure definition
        • CRC Handle Structure definition
      • CRC Exported Macros
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Private Types
      • CRC Private Defines
      • CRC Private Variables
      • CRC Private Constants
      • CRC Private Macros
      • CRC Private Functions Prototypes
      • CRC Private Functions
    • CRYP
    • CRYPEx
    • DAC
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC Trigger Selection
        • DAC Output Buffer
        • DAC Channel Selection
        • DAC Data Alignment
        • DAC Flags Definition
        • DAC IT Definition
      • DAC Exported Macros
      • DAC Private Constants
      • DAC Private Macros
      • DAC Private Functions
    • DACEx
      • DAC Exported Functions
        • Extended features functions
      • DAC Exported Constants
        • DAC LFS Run Mask Triangle Amplitude
      • DAC Private Constants
      • DAC Private Macros
      • DAC Private Functions
    • DCMI
    • DCMIEx
    • DMA
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA Channel selection
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA FIFO direct mode
        • DMA FIFO threshold level
        • DMA Memory burst
        • DMA Peripheral burst
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • I/O operation functions
        • Peripheral State functions
      • DMA Private Constants
      • DMA Private Macros
      • DMA Private Functions
    • DMAEx
      • DMAEx Exported Types
      • DMAEx Exported Functions
        • Extended features functions
      • DMAEx Private Functions
    • ETH
    • FLASH
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error Code
        • FLASH Type Program
        • FLASH Flag definition
        • FLASH Interrupt definition
        • FLASH Program Parallelism
        • FLASH Keys
      • FLASH Exported Macros
      • FLASH Private Variables
      • FLASH Private Constants
      • FLASH Private Macros
        • FLASH Private macros to check input parameters
      • FLASH Private Functions
    • FLASHEx
      • FLASHEx Exported Functions
        • Extended IO operation functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Type Erase
        • FLASH Voltage Range
        • FLASH WRP State
        • FLASH Option Type
        • FLASH Option Bytes Read Protection
        • FLASH Option Bytes IWatchdog
        • FLASH Option Bytes nRST_STOP
        • FLASH Option Bytes nRST_STDBY
        • FLASH BOR Reset Level
        • FLASH PCROP State
        • FLASH Advanced Option Type
        • FLASH Latency
        • FLASH Banks
        • FLASH Mass Erase bit
        • FLASH Sectors
        • FLASH Option Bytes Write Protection
        • FLASH Option Bytes PC ReadWrite Protection
        • FLASH Dual Boot
        • FLASH Selection Protection Mode
      • FLASH Private Constants
      • FLASH Private Macros
        • FLASH Private macros to check input parameters
      • FLASH Private Functions
      • FLASHEx_Private_Variables
    • FLASH RAMFUNC
      • FLASH RAMFUNC Exported Functions
        • Peripheral features functions executed from internal RAM
    • FMPI2C
      • FMPI2C Private Define
      • FMPI2C Private Functions
      • FMPI2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
      • FMPI2C Exported Types
        • FMPI2C Configuration Structure definition
        • HAL state structure definition
        • FMPI2C Error Code definition
        • FMPI2C XferOptions definition
        • FMPI2C handle Structure definition
      • FMPI2C Exported Constants
        • FMPI2C addressing mode
        • FMPI2C dual addressing mode
        • FMPI2C own address2 masks
        • FMPI2C general call addressing mode
        • FMPI2C nostretch mode
        • FMPI2C Memory Address Size
        • FMPI2C XferDirection definition
        • FMPI2C ReloadEndMode definition
        • FMPI2C StartStopMode definition
        • FMPI2C Interrupt configuration definition
        • FMPI2C Flag definition
      • FMPI2C Exported Macros
      • FMPI2C Private Constants
      • FMPI2C Private Macros
    • FMPI2CEx
      • FMPI2C Extended Exported Functions
        • Extended features functions
          • FMPI2C Extended Private Constants
          • FMPI2C Extended Private Macros
          • FMPI2C Extended Private Functions
      • FMPI2C Extended Exported Constants
        • FMPI2C Extended Analog Filter
        • FMPI2C Extended Fast Mode Plus
    • GPIO
      • GPIO Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins define
        • GPIO mode define
        • GPIO speed define
        • GPIO pull define
      • GPIO Exported Macros
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Private Functions
    • GPIOEx
      • GPIO Exported Constants
        • GPIO Alternate Function Selection
      • GPIO Exported Macros
      • GPIO Exported Functions
      • GPIO Private Constants
      • GPIO Private Macros
        • GPIO Get Port Index
        • GPIO Check Alternate Function
      • GPIO Private Functions
    • HASH
    • HASHEx
    • HCD
    • I2C
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • I2C Exported Types
      • I2C Exported Constants
        • I2C Error Code
        • I2C duty cycle in fast mode
        • I2C addressing mode
        • I2C dual addressing mode
        • I2C general call addressing mode
        • I2C nostretch mode
        • I2C Memory Address Size
        • I2C XferDirection definition
        • I2C XferOptions definition
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
        • I2C Private macros to check input parameters
      • I2C Private Functions
    • I2CEx
    • I2S
      • I2S Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • I2S Exported Types
      • I2S Exported Constants
        • I2S Error Code
        • I2S Mode
        • I2S Standard
        • I2S Data Format
        • I2S Mclk Output
        • I2S Audio Frequency
        • I2S FullDuplex Mode
        • I2S Clock Polarity
        • I2S Interrupts Definition
        • I2S Flags Definition
      • I2S Exported Macros
      • I2S Private Constants
      • I2S Private Macros
      • I2S Private Functions
    • I2SEx
      • I2S Exported Functions
        • Extension features functions
        • I2SEx_Exported_Functions_Group1
      • I2S Exported Types
      • I2S Exported Constants
        • I2S Clock Source
      • I2S Exported Macros
      • I2S Private Constants
      • I2S Private Macros
      • I2S Private Functions
    • IRDA
      • IrDA Exported Functions
        • IrDA Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • IRDA Exported Types
      • IRDA Exported constants
        • IRDA Error Code
        • IRDA Word Length
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA Flags
        • IRDA Interrupt Definitions
      • IRDA Exported Macros
      • IRDA Private Constants
      • IRDA Private Macros
      • IRDA Private Functions
    • IWDG
      • IWDG Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Registers BitMask
        • IWDG Flag definition
        • IWDG Prescaler
      • IWDG Exported Macros
      • IWDG Private Macros
      • IWDG Private Constants
    • LPTIM
      • LPTIM Private Types
      • LPTIM Private Defines
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler
        • Peripheral State functions
      • LPTIM Exported Types
        • LPTIM WAKEUP Timer EXTI Line
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Flag Definition
        • LPTIM Interrupts Definition
        • Register Definition
      • LPTIM Exported Macros
      • LPTIM Private Variables
      • LPTIM Private Constants
      • LPTIM Private Macros
      • LPTIM Private Functions
      • LPTIM Private Functions Prototypes
    • LTDC
    • LTDCEx
      • LTDC Extended Exported Functions
        • Initialization and Configuration functions
    • NOR
    • PCD
    • PCDEx
    • PWR
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • PWR Exported Types
      • PWR Exported Constants
        • PWR WakeUp Pins
        • PWR PVD detection level
        • PWR PVD Mode
        • PWR Regulator state in SLEEP/STOP mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR Flag
      • PWR Exported Macro
      • PWR Private Constants
        • PWR PVD Mode Mask
        • PWR PVD EXTI Line
        • PWR Register alias address
        • PWR CR Register alias address
        • PWR CSR Register alias address
      • PWR Private Macros
        • PWR Private macros to check input parameters
    • PWREx
      • PWREx Exported Functions
        • Peripheral Extended features functions
      • PWREx Exported Constants
        • PWREx Regulator Voltage Scale
        • PWREx WakeUp Pins
      • PWREx Private Constants
        • PWREx Register alias address
        • PWRx CSR Register alias address
      • PWREx Private Macros
        • PWREx Private macros to check input parameters
    • QSPI
    • RCC
      • RCC Private Variables
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • Oscillator Type
        • HSE Config
        • LSE Config
        • HSI Config
        • LSI Config
        • PLL Config
        • PLLP Clock Divider
        • PLL Clock Source
        • System Clock Type
        • System Clock Source
        • System Clock Source Status
        • AHB Clock Source
        • APB1/APB2 Clock Source
        • RTC Clock Source
        • MCO Index
        • MCO1 Clock Source
        • MCOx Clock Prescaler
        • Interrupts
        • Flags
      • RCC Exported Macros
        • AHB1 Peripheral Clock Enable Disable
        • AHB1 Peripheral Clock Enable Disable Status
        • APB1 Peripheral Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable Status
        • APB2 Peripheral Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable Status
        • AHB1 Force Release Reset
        • APB1 Force Release Reset
        • APB2 Force Release Reset
        • AHB1 Peripheral Low Power Enable Disable
        • APB1 Peripheral Low Power Enable Disable
        • APB2 Peripheral Low Power Enable Disable
        • HSI Configuration
        • LSI Configuration
        • HSE Configuration
        • LSE Configuration
        • RTC Clock Configuration
        • PLL Configuration
        • Get Clock source
        • RCC Extended MCOx Clock Config
        • Flags Interrupts Management
      • RCC Private Constants
        • RCC BitAddress AliasRegion
      • RCC Private Macros
        • RCC Private macros to check input parameters
    • RCCEx
      • RCCEx Exported Functions
        • Extended Peripheral Control functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • RCC Periph Clock Selection
        • RCC PLLSAI DIVR
        • RCC PLLI2SP Clock Divider
        • RCC PLLSAIP Clock Divider
        • RCC I2S APB Clock Source
        • RCC FMPI2C1 Clock Source
        • RCC LPTIM1 Clock Source
        • RCC TIM PRescaler Selection
        • RCC LSE Dual Mode Selection
        • MCO2 Clock Source
      • RCCEx Exported Macros
        • AHB1 Peripheral Clock Enable Disable
        • AHB1 Peripheral Clock Enable Disable Status
        • APB1 Peripheral Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable Status
        • APB2 Peripheral Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable Status
        • AHB1 Force Release Reset
        • AHB2 Force Release Reset
        • AHB3 Force Release Reset
        • APB1 Force Release Reset
        • APB2 Force Release Reset
        • AHB1 Peripheral Low Power Enable Disable
        • APB1 Peripheral Low Power Enable Disable
        • APB2 Peripheral Low Power Enable Disable
      • RCCEx Private Constants
        • RCC BitAddress AliasRegion
      • RCCEx Private Macros
        • RCC Private macros to check input parameters
    • RNG
      • RNG Exported Types
        • RNG State Structure definition
        • RNG Handle Structure definition
      • RNG Exported Constants
        • RNG Interrupt definition
        • RNG Flag definition
      • RNG Exported Macros
      • RNG Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • RNG Private Types
      • RNG Private Defines
      • RNG Private Variables
      • RNG Private Constants
      • RNG Private Macros
      • RNG Private Functions Prototypes
      • RNG Private Functions
    • RTC
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTC Output Selection Definitions
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC AM PM Definitions
        • RTC DayLight Saving Definitions
        • RTC Store Operation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC Alarm Date WeekDay Definitions
        • RTC Alarm Mask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flags Definitions
      • RTC Exported Macros
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
      • RTC Private Functions
    • RTCEx
      • RTCEx Exported Functions
        • RTC TimeStamp and Tamper functions
        • RTC Wake-up functions
        • Extension Peripheral Control functions
        • Extended features functions
      • RTCEx Exported Types
      • RTCEx Exported Constants
        • RTC Backup Registers Definitions
        • RTC TimeStamp Edges Definitions
        • RTC Tamper Pins Definitions
        • RTC tamper Pins Selection
        • RTC TimeStamp Pins Selection
        • RTC Tamper Triggers Definitions
        • RTC Tamper Filter Definitions
        • RTC Tamper Sampling Frequencies Definitions
        • RTC Tamper Pin Precharge Duration Definitions
        • RTC Tamper TimeStamp On Tamper Detection Definitions
        • RTC Tamper Pull Up Definitions
        • RTC Wake-up Timer Definitions
        • RTC Digital Calib Definitions
        • RTC Smooth Calib Period Definitions
        • RTC Smooth Calib Plus Pulses Definitions
        • RTC Add 1 Second Parameter Definitions
        • RTC Calib Output Selection Definitions
      • RTCEx Exported Macros
        • RTC WakeUp Timer
        • RTC Timestamp
        • RTC Tamper
        • EXTI RTC Tamper Timestamp EXTI
        • RTC Calibration
      • RTCEx Private Constants
      • RTCEx Private Macros
        • Private macros to check input parameters
    • SAI
    • SAIEx
    • SDRAM
    • SMARTCARD
      • SMARTCARD Exported Functions
        • SmartCard Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported constants
        • SMARTCARD Error Code
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD NACK State
        • SMARTCARD DMA requests
        • SMARTCARD Prescaler
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
      • SMARTCARD Exported Macros
      • SMARTCARD Private Constants
      • SMARTCARD Private Macros
      • SMARTCARD Private Functions
    • SPDIFRX
    • SPI
      • SPI Private Constants
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI Interrupt Definition
        • SPI Flags Definition
      • SPI Exported Macros
      • SPI Private Macros
      • SPI Private Functions
    • SRAM
    • TIM
      • TIM Exported Functions
        • Time Base functions
        • Time Output Compare functions
        • Time PWM functions
        • Time Input Capture functions
        • Time One Pulse functions
        • Time Encoder functions
        • TIM IRQ handler management
        • Peripheral Control functions
        • TIM Callbacks functions
        • Peripheral State functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Input Channel Polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Clock Division
        • TIM Output Compare and PWM modes
        • TIM Output Fast State
        • TIM Output Compare Polarity
        • TIM Output CompareN Polarity
        • TIM Output Compare Idle State
        • TIM Output Compare N Idle State
        • TIM Channel
        • TIM Input Capture Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM Interrupt definition
        • TIM Commutation Source
        • TIM DMA sources
        • TIM Event Source
        • TIM Flag definition
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Source
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR OffState Selection for Run mode state
        • TIM OSSI OffState Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input State
        • TIM Break Polarity
        • TIM AOE Bit State
        • TIM Master Mode Selection
        • TIM Slave Mode
        • TIM Master Slave Mode
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Selection
        • TIM DMA Base address
        • TIM DMA Burst Length
        • DMA Handle index
        • Channel CC State
      • TIM Exported Macros
      • TIM Private Macros
        • TIM Private macros to check input parameters
        • TIM Mask Definition
      • TIM Private Functions
    • TIMEx
      • TIM Exported Functions
        • Timer Hall Sensor functions
        • Timer Complementary Output Compare functions
        • Timer Complementary PWM functions
        • Timer Complementary One Pulse functions
        • Peripheral Control functions
        • Extension Callbacks functions
        • Extension Peripheral State functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Remap
        • TIM System Break Input
      • TIM Private Macros
      • TIM Private Functions
    • UART
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • UART Exported Types
      • UART Exported constants
        • UART Error Code
        • UART Word Length
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART LIN Break Detection Length
        • UART Wakeup Functions
        • UART FLags
        • UART Interrupt Definitions
      • UART Exported Macros
      • UART Private Constants
      • UART Private Macros
      • UART Private Functions
    • USART
      • USART Exported Functions
        • USART Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error Code
        • USART Word Length
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART NACK State
        • USART Flags
        • USART Interrupts Definition
      • USART Exported Macros
      • USART Private Constants
      • USART Private Macros
      • USART Private Functions
    • WWDG
      • WWDG Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
      • WWDG Exported Macros
      • WWDG Private Constants
        • WWDG BitAddress
      • WWDG Private Macros
      • WWDG Private Functions
    • DMA2D
    • DSI
    • NAND
Generated on Fri Jan 29 2016 15:36:58 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal.c Source File

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stm32f4xx_hal.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   HAL module driver.
00008   *          This is the common part of the HAL initialization
00009   *
00010   @verbatim
00011   ==============================================================================
00012                      ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015     The common HAL driver contains a set of generic and common APIs that can be
00016     used by the PPP peripheral drivers and the user to start using the HAL.
00017     [..]
00018     The HAL contains two APIs' categories:
00019          (+) Common HAL APIs
00020          (+) Services HAL APIs
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32f4xx_hal.h"
00055
00056 /** @addtogroup STM32F4xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup HAL HAL
00061   * @brief HAL module driver.
00062   * @{
00063   */
00064
00065 /* Private typedef -----------------------------------------------------------*/
00066 /* Private define ------------------------------------------------------------*/
00067 /** @addtogroup HAL_Private_Constants
00068   * @{
00069   */
00070 /**
00071   * @brief STM32F4xx HAL Driver version number V1.4.4
00072   */
00073 #define __STM32F4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
00074 #define __STM32F4xx_HAL_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
00075 #define __STM32F4xx_HAL_VERSION_SUB2   (0x04) /*!< [15:8]  sub2 version */
00076 #define __STM32F4xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
00077 #define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
00078                                         |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
00079                                         |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
00080                                         |(__STM32F4xx_HAL_VERSION_RC))
00081
00082 #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFFU)
00083
00084 /* ------------ RCC registers bit address in the alias region ----------- */
00085 #define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
00086 /* ---  MEMRMP Register ---*/
00087 /* Alias word address of UFB_MODE bit */
00088 #define MEMRMP_OFFSET             SYSCFG_OFFSET
00089 #define UFB_MODE_BIT_NUMBER       POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
00090 #define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))
00091
00092 /* ---  CMPCR Register ---*/
00093 /* Alias word address of CMP_PD bit */
00094 #define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U)
00095 #define CMP_PD_BIT_NUMBER         POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
00096 #define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
00097 /**
00098   * @}
00099   */
00100
00101 /* Private macro -------------------------------------------------------------*/
00102 /* Private variables ---------------------------------------------------------*/
00103 /** @addtogroup HAL_Private_Variables
00104   * @{
00105   */
00106 __IO uint32_t uwTick;
00107 /**
00108   * @}
00109   */
00110 /* Private function prototypes -----------------------------------------------*/
00111 /* Private functions ---------------------------------------------------------*/
00112
00113 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00114   * @{
00115   */
00116
00117 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00118  *  @brief    Initialization and de-initialization functions
00119  *
00120 @verbatim
00121  ===============================================================================
00122               ##### Initialization and de-initialization functions #####
00123  ===============================================================================
00124     [..]  This section provides functions allowing to:
00125       (+) Initializes the Flash interface the NVIC allocation and initial clock
00126           configuration. It initializes the systick also when timeout is needed
00127           and the backup domain when enabled.
00128       (+) de-Initializes common part of the HAL
00129       (+) Configure The time base source to have 1ms time base with a dedicated
00130           Tick interrupt priority.
00131         (++) Systick timer is used by default as source of time base, but user
00132              can eventually implement his proper time base source (a general purpose
00133              timer for example or other time source), keeping in mind that Time base
00134              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00135              handled in milliseconds basis.
00136         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00137              at the beginning of the program after reset by HAL_Init() or at any time
00138              when clock is configured, by HAL_RCC_ClockConfig().
00139         (++) Source of time base is configured  to generate interrupts at regular
00140              time intervals. Care must be taken if HAL_Delay() is called from a
00141              peripheral ISR process, the Tick interrupt line must have higher priority
00142             (numerically lower) than the peripheral interrupt. Otherwise the caller
00143             ISR process will be blocked.
00144        (++) functions affecting time base configurations are declared as __weak
00145              to make  override possible  in case of other  implementations in user file.
00146 @endverbatim
00147   * @{
00148   */
00149
00150 /**
00151   * @brief  This function is used to initialize the HAL Library; it must be the first
00152   *         instruction to be executed in the main program (before to call any other
00153   *         HAL function), it performs the following:
00154   *           Configure the Flash prefetch, instruction and Data caches.
00155   *           Configures the SysTick to generate an interrupt each 1 millisecond,
00156   *           which is clocked by the HSI (at this stage, the clock is not yet
00157   *           configured and thus the system is running from the internal HSI at 16 MHz).
00158   *           Set NVIC Group Priority to 4.
00159   *           Calls the HAL_MspInit() callback function defined in user file
00160   *           "stm32f4xx_hal_msp.c" to do the global low level hardware initialization
00161   *
00162   * @note   SysTick is used as time base for the HAL_Delay() function, the application
00163   *         need to ensure that the SysTick time base is always set to 1 millisecond
00164   *         to have correct HAL operation.
00165   * @retval HAL status
00166   */
00167 HAL_StatusTypeDef HAL_Init(void)
00168 {
00169   /* Configure Flash prefetch, Instruction cache, Data cache */
00170 #if (INSTRUCTION_CACHE_ENABLE != 0U)
00171    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
00172 #endif /* INSTRUCTION_CACHE_ENABLE */
00173
00174 #if (DATA_CACHE_ENABLE != 0U)
00175    __HAL_FLASH_DATA_CACHE_ENABLE();
00176 #endif /* DATA_CACHE_ENABLE */
00177
00178 #if (PREFETCH_ENABLE != 0U)
00179   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
00180 #endif /* PREFETCH_ENABLE */
00181
00182   /* Set Interrupt Group Priority */
00183   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00184
00185   /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
00186   HAL_InitTick(TICK_INT_PRIORITY);
00187
00188   /* Init the low level hardware */
00189   HAL_MspInit();
00190
00191   /* Return function status */
00192   return HAL_OK;
00193 }
00194
00195 /**
00196   * @brief  This function de-Initializes common part of the HAL and stops the systick.
00197   *         This function is optional.
00198   * @retval HAL status
00199   */
00200 HAL_StatusTypeDef HAL_DeInit(void)
00201 {
00202   /* Reset of all peripherals */
00203   __HAL_RCC_APB1_FORCE_RESET();
00204   __HAL_RCC_APB1_RELEASE_RESET();
00205
00206   __HAL_RCC_APB2_FORCE_RESET();
00207   __HAL_RCC_APB2_RELEASE_RESET();
00208
00209   __HAL_RCC_AHB1_FORCE_RESET();
00210   __HAL_RCC_AHB1_RELEASE_RESET();
00211
00212   __HAL_RCC_AHB2_FORCE_RESET();
00213   __HAL_RCC_AHB2_RELEASE_RESET();
00214
00215   __HAL_RCC_AHB3_FORCE_RESET();
00216   __HAL_RCC_AHB3_RELEASE_RESET();
00217
00218   /* De-Init the low level hardware */
00219   HAL_MspDeInit();
00220
00221   /* Return function status */
00222   return HAL_OK;
00223 }
00224
00225 /**
00226   * @brief  Initializes the MSP.
00227   * @retval None
00228   */
00229 __weak void HAL_MspInit(void)
00230 {
00231   /* NOTE : This function Should not be modified, when the callback is needed,
00232             the HAL_MspInit could be implemented in the user file
00233    */
00234 }
00235
00236 /**
00237   * @brief  DeInitializes the MSP.
00238   * @retval None
00239   */
00240 __weak void HAL_MspDeInit(void)
00241 {
00242   /* NOTE : This function Should not be modified, when the callback is needed,
00243             the HAL_MspDeInit could be implemented in the user file
00244    */
00245 }
00246
00247 /**
00248   * @brief This function configures the source of the time base.
00249   *        The time source is configured  to have 1ms time base with a dedicated
00250   *        Tick interrupt priority.
00251   * @note This function is called  automatically at the beginning of program after
00252   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00253   * @note In the default implementation, SysTick timer is the source of time base.
00254   *       It is used to generate interrupts at regular time intervals.
00255   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00256   *       The the SysTick interrupt must have higher priority (numerically lower)
00257   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00258   *       The function is declared as __weak  to be overwritten  in case of other
00259   *       implementation  in user file.
00260   * @param TickPriority: Tick interrupt priority.
00261   * @retval HAL status
00262   */
00263 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00264 {
00265   /*Configure the SysTick to have interrupt in 1ms time basis*/
00266   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000U);
00267
00268   /*Configure the SysTick IRQ priority */
00269   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
00270
00271   /* Return function status */
00272   return HAL_OK;
00273 }
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00280  *  @brief    HAL Control functions
00281  *
00282 @verbatim
00283  ===============================================================================
00284                       ##### HAL Control functions #####
00285  ===============================================================================
00286     [..]  This section provides functions allowing to:
00287       (+) Provide a tick value in millisecond
00288       (+) Provide a blocking delay in millisecond
00289       (+) Suspend the time base source interrupt
00290       (+) Resume the time base source interrupt
00291       (+) Get the HAL API driver version
00292       (+) Get the device identifier
00293       (+) Get the device revision identifier
00294       (+) Enable/Disable Debug module during SLEEP mode
00295       (+) Enable/Disable Debug module during STOP mode
00296       (+) Enable/Disable Debug module during STANDBY mode
00297
00298 @endverbatim
00299   * @{
00300   */
00301
00302 /**
00303   * @brief This function is called to increment  a global variable "uwTick"
00304   *        used as application time base.
00305   * @note In the default implementation, this variable is incremented each 1ms
00306   *       in Systick ISR.
00307  * @note This function is declared as __weak to be overwritten in case of other
00308   *      implementations in user file.
00309   * @retval None
00310   */
00311 __weak void HAL_IncTick(void)
00312 {
00313   uwTick++;
00314 }
00315
00316 /**
00317   * @brief Provides a tick value in millisecond.
00318   * @note This function is declared as __weak to be overwritten in case of other
00319   *       implementations in user file.
00320   * @retval tick value
00321   */
00322 __weak uint32_t HAL_GetTick(void)
00323 {
00324   return uwTick;
00325 }
00326
00327 /**
00328   * @brief This function provides accurate delay (in milliseconds) based
00329   *        on variable incremented.
00330   * @note In the default implementation , SysTick timer is the source of time base.
00331   *       It is used to generate interrupts at regular time intervals where uwTick
00332   *       is incremented.
00333   * @note This function is declared as __weak to be overwritten in case of other
00334   *       implementations in user file.
00335   * @param Delay: specifies the delay time length, in milliseconds.
00336   * @retval None
00337   */
00338 __weak void HAL_Delay(__IO uint32_t Delay)
00339 {
00340   uint32_t tickstart = 0U;
00341   tickstart = HAL_GetTick();
00342   while((HAL_GetTick() - tickstart) < Delay)
00343   {
00344   }
00345 }
00346
00347 /**
00348   * @brief Suspend Tick increment.
00349   * @note In the default implementation , SysTick timer is the source of time base. It is
00350   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00351   *       is called, the SysTick interrupt will be disabled and so Tick increment
00352   *       is suspended.
00353   * @note This function is declared as __weak to be overwritten in case of other
00354   *       implementations in user file.
00355   * @retval None
00356   */
00357 __weak void HAL_SuspendTick(void)
00358 {
00359   /* Disable SysTick Interrupt */
00360   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
00361 }
00362
00363 /**
00364   * @brief Resume Tick increment.
00365   * @note In the default implementation , SysTick timer is the source of time base. It is
00366   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00367   *       is called, the SysTick interrupt will be enabled and so Tick increment
00368   *       is resumed.
00369   * @note This function is declared as __weak to be overwritten in case of other
00370   *       implementations in user file.
00371   * @retval None
00372   */
00373 __weak void HAL_ResumeTick(void)
00374 {
00375   /* Enable SysTick Interrupt */
00376   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
00377 }
00378
00379 /**
00380   * @brief  Returns the HAL revision
00381   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00382   */
00383 uint32_t HAL_GetHalVersion(void)
00384 {
00385  return __STM32F4xx_HAL_VERSION;
00386 }
00387
00388 /**
00389   * @brief  Returns the device revision identifier.
00390   * @retval Device revision identifier
00391   */
00392 uint32_t HAL_GetREVID(void)
00393 {
00394    return((DBGMCU->IDCODE) >> 16U);
00395 }
00396
00397 /**
00398   * @brief  Returns the device identifier.
00399   * @retval Device identifier
00400   */
00401 uint32_t HAL_GetDEVID(void)
00402 {
00403    return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
00404 }
00405
00406 /**
00407   * @brief  Enable the Debug Module during SLEEP mode
00408   * @retval None
00409   */
00410 void HAL_DBGMCU_EnableDBGSleepMode(void)
00411 {
00412   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00413 }
00414
00415 /**
00416   * @brief  Disable the Debug Module during SLEEP mode
00417   * @retval None
00418   */
00419 void HAL_DBGMCU_DisableDBGSleepMode(void)
00420 {
00421   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00422 }
00423
00424 /**
00425   * @brief  Enable the Debug Module during STOP mode
00426   * @retval None
00427   */
00428 void HAL_DBGMCU_EnableDBGStopMode(void)
00429 {
00430   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00431 }
00432
00433 /**
00434   * @brief  Disable the Debug Module during STOP mode
00435   * @retval None
00436   */
00437 void HAL_DBGMCU_DisableDBGStopMode(void)
00438 {
00439   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00440 }
00441
00442 /**
00443   * @brief  Enable the Debug Module during STANDBY mode
00444   * @retval None
00445   */
00446 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00447 {
00448   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00449 }
00450
00451 /**
00452   * @brief  Disable the Debug Module during STANDBY mode
00453   * @retval None
00454   */
00455 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00456 {
00457   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00458 }
00459
00460 /**
00461   * @brief  Enables the I/O Compensation Cell.
00462   * @note   The I/O compensation cell can be used only when the device supply
00463   *         voltage ranges from 2.4 to 3.6 V.
00464   * @retval None
00465   */
00466 void HAL_EnableCompensationCell(void)
00467 {
00468   *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
00469 }
00470
00471 /**
00472   * @brief  Power-down the I/O Compensation Cell.
00473   * @note   The I/O compensation cell can be used only when the device supply
00474   *         voltage ranges from 2.4 to 3.6 V.
00475   * @retval None
00476   */
00477 void HAL_DisableCompensationCell(void)
00478 {
00479   *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
00480 }
00481
00482 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00483     defined(STM32F469xx) || defined(STM32F479xx)
00484 /**
00485   * @brief  Enables the Internal FLASH Bank Swapping.
00486   *
00487   * @note   This function can be used only for STM32F42xxx/43xxx devices.
00488   *
00489   * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
00490   *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
00491   *
00492   * @retval None
00493   */
00494 void HAL_EnableMemorySwappingBank(void)
00495 {
00496   *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;
00497 }
00498
00499 /**
00500   * @brief  Disables the Internal FLASH Bank Swapping.
00501   *
00502   * @note   This function can be used only for STM32F42xxx/43xxx devices.
00503   *
00504   * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
00505   *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
00506   *
00507   * @retval None
00508   */
00509 void HAL_DisableMemorySwappingBank(void)
00510 {
00511
00512   *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
00513 }
00514 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00515
00516 /**
00517   * @}
00518   */
00519
00520 /**
00521   * @}
00522   */
00523
00524 /**
00525   * @}
00526   */
00527
00528 /**
00529   * @}
00530   */
00531
00532 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:50 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal.h Source File

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stm32f4xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   This file contains all the functions prototypes for the HAL
00008   *          module driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __STM32F4xx_HAL_H
00041 #define __STM32F4xx_HAL_H
00042
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_conf.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HAL
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /* Exported macro ------------------------------------------------------------*/
00061 /** @defgroup HAL_Exported_Macros HAL Exported Macros
00062   * @{
00063   */
00064
00065 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
00066   */
00067 #define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
00068 #define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
00069 #define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
00070 #define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
00071 #define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
00072 #define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
00073 #define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
00074 #define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
00075 #define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
00076 #define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
00077 #define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
00078 #define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
00079 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
00080 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
00081 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
00082 #define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
00083 #define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
00084 #define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
00085 #define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
00086 #define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
00087 #define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
00088 #define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
00089
00090 #define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
00091 #define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
00092 #define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
00093 #define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
00094 #define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
00095 #define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
00096 #define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
00097 #define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
00098 #define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
00099 #define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
00100 #define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
00101 #define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
00102 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
00103 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
00104 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
00105 #define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
00106 #define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
00107 #define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
00108 #define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
00109 #define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
00110 #define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
00111 #define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
00112
00113 /** @brief  Main Flash memory mapped at 0x00000000
00114   */
00115 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
00116
00117 /** @brief  System Flash memory mapped at 0x00000000
00118   */
00119 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
00120                                                          SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
00121                                                         }while(0);
00122
00123 /** @brief  Embedded SRAM mapped at 0x00000000
00124   */
00125 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
00126                                                   SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
00127                                                  }while(0);
00128
00129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
00130 /** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
00131   */
00132 #define __HAL_SYSCFG_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
00133                                                   SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
00134                                                  }while(0);
00135 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00136
00137 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00138     defined(STM32F469xx) || defined(STM32F479xx)
00139 /** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
00140   */
00141 #define __HAL_SYSCFG_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
00142                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
00143                                                 }while(0);
00144
00145 /** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
00146   */
00147 #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
00148                                                        SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
00149                                                       }while(0);
00150 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00151
00152 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00153 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
00154   * @{
00155   */
00156 /** @brief  SYSCFG Break Lockup lock
00157   *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
00158   * @note   The selected configuration is locked and can be unlocked by system reset
00159   */
00160 #define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
00161                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
00162                                               }while(0)
00163 /**
00164  * @}
00165  */
00166
00167 /** @defgroup PVD_Lock_Enable PVD Lock
00168   * @{
00169   */
00170 /** @brief  SYSCFG Break PVD lock
00171   *         Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
00172   * @note   The selected configuration is locked and can be unlocked by system reset
00173   */
00174 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
00175                                                  SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
00176                                                 }while(0)
00177 /**
00178  * @}
00179  */
00180 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00181 /**
00182   * @}
00183   */
00184
00185 /* Exported functions --------------------------------------------------------*/
00186 /** @addtogroup HAL_Exported_Functions
00187   * @{
00188   */
00189 /** @addtogroup HAL_Exported_Functions_Group1
00190   * @{
00191   */
00192 /* Initialization and de-initialization functions  ******************************/
00193 HAL_StatusTypeDef HAL_Init(void);
00194 HAL_StatusTypeDef HAL_DeInit(void);
00195 void HAL_MspInit(void);
00196 void HAL_MspDeInit(void);
00197 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00198 /**
00199   * @}
00200   */
00201
00202 /** @addtogroup HAL_Exported_Functions_Group2
00203   * @{
00204   */
00205 /* Peripheral Control functions  ************************************************/
00206 void HAL_IncTick(void);
00207 void HAL_Delay(__IO uint32_t Delay);
00208 uint32_t HAL_GetTick(void);
00209 void HAL_SuspendTick(void);
00210 void HAL_ResumeTick(void);
00211 uint32_t HAL_GetHalVersion(void);
00212 uint32_t HAL_GetREVID(void);
00213 uint32_t HAL_GetDEVID(void);
00214 void HAL_DBGMCU_EnableDBGSleepMode(void);
00215 void HAL_DBGMCU_DisableDBGSleepMode(void);
00216 void HAL_DBGMCU_EnableDBGStopMode(void);
00217 void HAL_DBGMCU_DisableDBGStopMode(void);
00218 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00219 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00220 void HAL_EnableCompensationCell(void);
00221 void HAL_DisableCompensationCell(void);
00222 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00223     defined(STM32F469xx) || defined(STM32F479xx)
00224 void HAL_EnableMemorySwappingBank(void);
00225 void HAL_DisableMemorySwappingBank(void);
00226 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00227 /**
00228   * @}
00229   */
00230
00231 /**
00232   * @}
00233   */
00234 /* Private types -------------------------------------------------------------*/
00235 /* Private variables ---------------------------------------------------------*/
00236 /** @defgroup HAL_Private_Variables HAL Private Variables
00237   * @{
00238   */
00239 /**
00240   * @}
00241   */
00242 /* Private constants ---------------------------------------------------------*/
00243 /** @defgroup HAL_Private_Constants HAL Private Constants
00244   * @{
00245   */
00246 /**
00247   * @}
00248   */
00249 /* Private macros ------------------------------------------------------------*/
00250 /* Private functions ---------------------------------------------------------*/
00251 /**
00252   * @}
00253   */
00254
00255 /**
00256   * @}
00257   */
00258
00259 #ifdef __cplusplus
00260 }
00261 #endif
00262
00263 #endif /* __STM32F4xx_HAL_H */
00264
00265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:50 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc.c Source File

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stm32f4xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + State and errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### ADC Peripheral features #####
00016   ==============================================================================
00017   [..]
00018   (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
00019   (#) Interrupt generation at the end of conversion, end of injected conversion,
00020       and in case of analog watchdog or overrun events
00021   (#) Single and continuous conversion modes.
00022   (#) Scan mode for automatic conversion of channel 0 to channel x.
00023   (#) Data alignment with in-built data coherency.
00024   (#) Channel-wise programmable sampling time.
00025   (#) External trigger option with configurable polarity for both regular and
00026       injected conversion.
00027   (#) Dual/Triple mode (on devices with 2 ADCs or more).
00028   (#) Configurable DMA data storage in Dual/Triple ADC mode.
00029   (#) Configurable delay between conversions in Dual/Triple interleaved mode.
00030   (#) ADC conversion type (refer to the datasheets).
00031   (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
00032       slower speed.
00033   (#) ADC input range: VREF(minus) = VIN = VREF(plus).
00034   (#) DMA request generation during regular channel conversion.
00035
00036
00037                      ##### How to use this driver #####
00038   ==============================================================================
00039   [..]
00040   (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
00041        (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
00042        (##) ADC pins configuration
00043              (+++) Enable the clock for the ADC GPIOs using the following function:
00044                    __HAL_RCC_GPIOx_CLK_ENABLE()
00045              (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
00046        (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
00047              (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
00048              (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
00049              (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
00050        (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
00051              (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
00052              (+++) Configure and enable two DMA streams stream for managing data
00053                  transfer from peripheral to memory (output stream)
00054              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00055                  using  __HAL_LINKDMA()
00056              (+++) Configure the priority and enable the NVIC for the transfer complete
00057                  interrupt on the two DMA Streams. The output stream should have higher
00058                  priority than the input stream.
00059
00060     *** Configuration of ADC, groups regular/injected, channels parameters ***
00061   ==============================================================================
00062   [..]
00063   (#) Configure the ADC parameters (resolution, data alignment, ...)
00064       and regular group parameters (conversion trigger, sequencer, ...)
00065       using function HAL_ADC_Init().
00066
00067   (#) Configure the channels for regular group parameters (channel number,
00068       channel rank into sequencer, ..., into regular group)
00069       using function HAL_ADC_ConfigChannel().
00070
00071   (#) Optionally, configure the injected group parameters (conversion trigger,
00072       sequencer, ..., of injected group)
00073       and the channels for injected group parameters (channel number,
00074       channel rank into sequencer, ..., into injected group)
00075       using function HAL_ADCEx_InjectedConfigChannel().
00076
00077   (#) Optionally, configure the analog watchdog parameters (channels
00078       monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
00079
00080   (#) Optionally, for devices with several ADC instances: configure the
00081       multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
00082
00083                        *** Execution of ADC conversions ***
00084   ==============================================================================
00085   [..]
00086   (#) ADC driver can be used among three modes: polling, interruption,
00087       transfer by DMA.
00088
00089      *** Polling mode IO operation ***
00090      =================================
00091      [..]
00092        (+) Start the ADC peripheral using HAL_ADC_Start()
00093        (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
00094            user can specify the value of timeout according to his end application
00095        (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
00096        (+) Stop the ADC peripheral using HAL_ADC_Stop()
00097
00098      *** Interrupt mode IO operation ***
00099      ===================================
00100      [..]
00101        (+) Start the ADC peripheral using HAL_ADC_Start_IT()
00102        (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
00103        (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
00104            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
00105        (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
00106            add his own code by customization of function pointer HAL_ADC_ErrorCallback
00107        (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
00108
00109      *** DMA mode IO operation ***
00110      ==============================
00111      [..]
00112        (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
00113            of data to be transferred at each end of conversion
00114        (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
00115            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
00116        (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
00117            add his own code by customization of function pointer HAL_ADC_ErrorCallback
00118        (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
00119
00120      *** ADC HAL driver macros list ***
00121      =============================================
00122      [..]
00123        Below the list of most used macros in ADC HAL driver.
00124
00125       (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
00126       (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
00127       (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
00128       (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
00129       (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
00130       (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
00131       (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
00132       (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
00133
00134      [..]
00135        (@) You can refer to the ADC HAL driver header file for more useful macros
00136
00137                       *** Deinitialization of ADC ***
00138   ==============================================================================
00139   [..]
00140   (#) Disable the ADC interface
00141      (++) ADC clock can be hard reset and disabled at RCC top level.
00142      (++) Hard reset of ADC peripherals
00143           using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
00144      (++) ADC clock disable using the equivalent macro/functions as configuration step.
00145                (+++) Example:
00146                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00147                    other device clock parameters configuration:
00148                (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
00149                (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
00150                (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
00151                (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
00152
00153   (#) ADC pins configuration
00154      (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00155
00156   (#) Optionally, in case of usage of ADC with interruptions:
00157      (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
00158
00159   (#) Optionally, in case of usage of DMA:
00160         (++) Deinitialize the DMA using function HAL_DMA_DeInit().
00161         (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
00162
00163     @endverbatim
00164   ******************************************************************************
00165   * @attention
00166   *
00167   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00168   *
00169   * Redistribution and use in source and binary forms, with or without modification,
00170   * are permitted provided that the following conditions are met:
00171   *   1. Redistributions of source code must retain the above copyright notice,
00172   *      this list of conditions and the following disclaimer.
00173   *   2. Redistributions in binary form must reproduce the above copyright notice,
00174   *      this list of conditions and the following disclaimer in the documentation
00175   *      and/or other materials provided with the distribution.
00176   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00177   *      may be used to endorse or promote products derived from this software
00178   *      without specific prior written permission.
00179   *
00180   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00181   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00182   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00183   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00184   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00185   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00186   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00187   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00188   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00189   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00190   *
00191   ******************************************************************************
00192   */
00193
00194 /* Includes ------------------------------------------------------------------*/
00195 #include "stm32f4xx_hal.h"
00196
00197 /** @addtogroup STM32F4xx_HAL_Driver
00198   * @{
00199   */
00200
00201 /** @defgroup ADC ADC
00202   * @brief ADC driver modules
00203   * @{
00204   */
00205
00206 #ifdef HAL_ADC_MODULE_ENABLED
00207
00208 /* Private typedef -----------------------------------------------------------*/
00209 /* Private define ------------------------------------------------------------*/
00210 /* Private macro -------------------------------------------------------------*/
00211 /* Private variables ---------------------------------------------------------*/
00212 /** @addtogroup ADC_Private_Functions
00213   * @{
00214   */
00215 /* Private function prototypes -----------------------------------------------*/
00216 static void ADC_Init(ADC_HandleTypeDef* hadc);
00217 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
00218 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
00219 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00220 /**
00221   * @}
00222   */
00223 /* Exported functions --------------------------------------------------------*/
00224 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00225   * @{
00226   */
00227
00228 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00229  *  @brief    Initialization and Configuration functions
00230  *
00231 @verbatim
00232  ===============================================================================
00233               ##### Initialization and de-initialization functions #####
00234  ===============================================================================
00235     [..]  This section provides functions allowing to:
00236       (+) Initialize and configure the ADC.
00237       (+) De-initialize the ADC.
00238
00239 @endverbatim
00240   * @{
00241   */
00242
00243 /**
00244   * @brief  Initializes the ADCx peripheral according to the specified parameters
00245   *         in the ADC_InitStruct and initializes the ADC MSP.
00246   *
00247   * @note   This function is used to configure the global features of the ADC (
00248   *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
00249   *         the rest of the configuration parameters are specific to the regular
00250   *         channels group (scan mode activation, continuous mode activation,
00251   *         External trigger source and edge, DMA continuous request after the
00252   *         last transfer and End of conversion selection).
00253   *
00254   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00255   *         the configuration information for the specified ADC.
00256   * @retval HAL status
00257   */
00258 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00259 {
00260   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00261
00262   /* Check ADC handle */
00263   if(hadc == NULL)
00264   {
00265     return HAL_ERROR;
00266   }
00267
00268   /* Check the parameters */
00269   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00270   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00271   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00272   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
00273   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00274   assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
00275   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00276   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
00277   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00278   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
00279   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00280
00281   if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00282   {
00283     assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00284   }
00285
00286   if(hadc->State == HAL_ADC_STATE_RESET)
00287   {
00288     /* Initialize ADC error code */
00289     ADC_CLEAR_ERRORCODE(hadc);
00290
00291     /* Allocate lock resource and initialize it */
00292     hadc->Lock = HAL_UNLOCKED;
00293
00294     /* Init the low level hardware */
00295     HAL_ADC_MspInit(hadc);
00296   }
00297
00298   /* Configuration of ADC parameters if previous preliminary actions are      */
00299   /* correctly completed.                                                     */
00300   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
00301   {
00302     /* Set ADC state */
00303     ADC_STATE_CLR_SET(hadc->State,
00304                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00305                       HAL_ADC_STATE_BUSY_INTERNAL);
00306
00307     /* Set ADC parameters */
00308     ADC_Init(hadc);
00309
00310     /* Set ADC error code to none */
00311     ADC_CLEAR_ERRORCODE(hadc);
00312
00313     /* Set the ADC state */
00314     ADC_STATE_CLR_SET(hadc->State,
00315                       HAL_ADC_STATE_BUSY_INTERNAL,
00316                       HAL_ADC_STATE_READY);
00317   }
00318   else
00319   {
00320     tmp_hal_status = HAL_ERROR;
00321   }
00322
00323   /* Release Lock */
00324   __HAL_UNLOCK(hadc);
00325
00326   /* Return function status */
00327   return tmp_hal_status;
00328 }
00329
00330 /**
00331   * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
00332   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00333   *         the configuration information for the specified ADC.
00334   * @retval HAL status
00335   */
00336 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00337 {
00338   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00339
00340   /* Check ADC handle */
00341   if(hadc == NULL)
00342   {
00343     return HAL_ERROR;
00344   }
00345
00346   /* Check the parameters */
00347   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00348
00349   /* Set ADC state */
00350   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00351
00352   /* Stop potential conversion on going, on regular and injected groups */
00353   /* Disable ADC peripheral */
00354   __HAL_ADC_DISABLE(hadc);
00355
00356   /* Configuration of ADC parameters if previous preliminary actions are      */
00357   /* correctly completed.                                                     */
00358   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00359   {
00360     /* DeInit the low level hardware */
00361     HAL_ADC_MspDeInit(hadc);
00362
00363     /* Set ADC error code to none */
00364     ADC_CLEAR_ERRORCODE(hadc);
00365
00366     /* Set ADC state */
00367     hadc->State = HAL_ADC_STATE_RESET;
00368   }
00369
00370   /* Process unlocked */
00371   __HAL_UNLOCK(hadc);
00372
00373   /* Return function status */
00374   return tmp_hal_status;
00375 }
00376
00377 /**
00378   * @brief  Initializes the ADC MSP.
00379   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00380   *         the configuration information for the specified ADC.
00381   * @retval None
00382   */
00383 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
00384 {
00385   /* Prevent unused argument(s) compilation warning */
00386   UNUSED(hadc);
00387   /* NOTE : This function Should not be modified, when the callback is needed,
00388             the HAL_ADC_MspInit could be implemented in the user file
00389    */
00390 }
00391
00392 /**
00393   * @brief  DeInitializes the ADC MSP.
00394   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00395   *         the configuration information for the specified ADC.
00396   * @retval None
00397   */
00398 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
00399 {
00400   /* Prevent unused argument(s) compilation warning */
00401   UNUSED(hadc);
00402   /* NOTE : This function Should not be modified, when the callback is needed,
00403             the HAL_ADC_MspDeInit could be implemented in the user file
00404    */
00405 }
00406
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
00412  *  @brief    IO operation functions
00413  *
00414 @verbatim
00415  ===============================================================================
00416              ##### IO operation functions #####
00417  ===============================================================================
00418     [..]  This section provides functions allowing to:
00419       (+) Start conversion of regular channel.
00420       (+) Stop conversion of regular channel.
00421       (+) Start conversion of regular channel and enable interrupt.
00422       (+) Stop conversion of regular channel and disable interrupt.
00423       (+) Start conversion of regular channel and enable DMA transfer.
00424       (+) Stop conversion of regular channel and disable DMA transfer.
00425       (+) Handle ADC interrupt request.
00426
00427 @endverbatim
00428   * @{
00429   */
00430
00431 /**
00432   * @brief  Enables ADC and starts conversion of the regular channels.
00433   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00434   *         the configuration information for the specified ADC.
00435   * @retval HAL status
00436   */
00437 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
00438 {
00439   __IO uint32_t counter = 0U;
00440
00441   /* Check the parameters */
00442   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00443   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00444
00445   /* Process locked */
00446   __HAL_LOCK(hadc);
00447
00448   /* Enable the ADC peripheral */
00449   /* Check if ADC peripheral is disabled in order to enable it and wait during
00450   Tstab time the ADC's stabilization */
00451   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00452   {
00453     /* Enable the Peripheral */
00454     __HAL_ADC_ENABLE(hadc);
00455
00456     /* Delay for ADC stabilization time */
00457     /* Compute number of CPU cycles to wait for */
00458     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
00459     while(counter != 0U)
00460     {
00461       counter--;
00462     }
00463   }
00464
00465   /* Start conversion if ADC is effectively enabled */
00466   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00467   {
00468     /* Set ADC state                                                          */
00469     /* - Clear state bitfield related to regular group conversion results     */
00470     /* - Set state bitfield related to regular group operation                */
00471     ADC_STATE_CLR_SET(hadc->State,
00472                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
00473                       HAL_ADC_STATE_REG_BUSY);
00474
00475     /* If conversions on group regular are also triggering group injected,    */
00476     /* update ADC state.                                                      */
00477     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00478     {
00479       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00480     }
00481
00482     /* State machine update: Check if an injected conversion is ongoing */
00483     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00484     {
00485       /* Reset ADC error code fields related to conversions on group regular */
00486       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
00487     }
00488     else
00489     {
00490       /* Reset ADC all error code fields */
00491       ADC_CLEAR_ERRORCODE(hadc);
00492     }
00493
00494     /* Process unlocked */
00495     /* Unlock before starting ADC conversions: in case of potential           */
00496     /* interruption, to let the process to ADC IRQ Handler.                   */
00497     __HAL_UNLOCK(hadc);
00498
00499     /* Clear regular group conversion flag and overrun flag */
00500     /* (To ensure of no unknown state from potential previous ADC operations) */
00501     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00502
00503     /* Check if Multimode enabled */
00504     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00505     {
00506       /* if no external trigger present enable software conversion of regular channels */
00507       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00508       {
00509         /* Enable the selected ADC software conversion for regular group */
00510         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00511       }
00512     }
00513     else
00514     {
00515       /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
00516       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
00517       {
00518         /* Enable the selected ADC software conversion for regular group */
00519           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00520       }
00521     }
00522   }
00523
00524   /* Return function status */
00525   return HAL_OK;
00526 }
00527
00528 /**
00529   * @brief  Disables ADC and stop conversion of regular channels.
00530   *
00531   * @note   Caution: This function will stop also injected channels.
00532   *
00533   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00534   *         the configuration information for the specified ADC.
00535   *
00536   * @retval HAL status.
00537   */
00538 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
00539 {
00540   /* Check the parameters */
00541   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00542
00543   /* Process locked */
00544   __HAL_LOCK(hadc);
00545
00546   /* Stop potential conversion on going, on regular and injected groups */
00547   /* Disable ADC peripheral */
00548   __HAL_ADC_DISABLE(hadc);
00549
00550   /* Check if ADC is effectively disabled */
00551   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00552   {
00553     /* Set ADC state */
00554     ADC_STATE_CLR_SET(hadc->State,
00555                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00556                       HAL_ADC_STATE_READY);
00557   }
00558
00559   /* Process unlocked */
00560   __HAL_UNLOCK(hadc);
00561
00562   /* Return function status */
00563   return HAL_OK;
00564 }
00565
00566 /**
00567   * @brief  Poll for regular conversion complete
00568   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
00569   *         conversion) are cleared by this function.
00570   * @note   This function cannot be used in a particular setup: ADC configured
00571   *         in DMA mode and polling for end of each conversion (ADC init
00572   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
00573   *         In this case, DMA resets the flag EOC and polling cannot be
00574   *         performed on each conversion. Nevertheless, polling can still
00575   *         be performed on the complete sequence.
00576   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00577   *         the configuration information for the specified ADC.
00578   * @param  Timeout: Timeout value in millisecond.
00579   * @retval HAL status
00580   */
00581 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00582 {
00583   uint32_t tickstart = 0U;
00584
00585   /* Verification that ADC configuration is compliant with polling for      */
00586   /* each conversion:                                                       */
00587   /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
00588   /* several ranks and polling for end of each conversion.                  */
00589   /* For code simplicity sake, this particular case is generalized to       */
00590   /* ADC configured in DMA mode and polling for end of each conversion.     */
00591   if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
00592       HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
00593   {
00594     /* Update ADC state machine to error */
00595     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00596
00597     /* Process unlocked */
00598     __HAL_UNLOCK(hadc);
00599
00600     return HAL_ERROR;
00601   }
00602
00603   /* Get tick */
00604   tickstart = HAL_GetTick();
00605
00606   /* Check End of conversion flag */
00607   while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
00608   {
00609     /* Check if timeout is disabled (set to infinite wait) */
00610     if(Timeout != HAL_MAX_DELAY)
00611     {
00612       if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
00613       {
00614         /* Update ADC state machine to timeout */
00615         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00616
00617         /* Process unlocked */
00618         __HAL_UNLOCK(hadc);
00619
00620         return HAL_TIMEOUT;
00621       }
00622     }
00623   }
00624
00625   /* Clear regular group conversion flag */
00626   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
00627
00628   /* Update ADC state machine */
00629   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
00630
00631   /* Determine whether any further conversion upcoming on group regular       */
00632   /* by external trigger, continuous mode or scan sequence on going.          */
00633   /* Note: On STM32F4, there is no independent flag of end of sequence.       */
00634   /*       The test of scan sequence on going is done either with scan        */
00635   /*       sequence disabled or with end of conversion flag set to            */
00636   /*       of end of sequence.                                                */
00637   if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
00638      (hadc->Init.ContinuousConvMode == DISABLE)            &&
00639      (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
00640       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
00641   {
00642     /* Set ADC state */
00643     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
00644
00645     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00646     {
00647       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00648     }
00649   }
00650
00651   /* Return ADC state */
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @brief  Poll for conversion event
00657   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00658   *         the configuration information for the specified ADC.
00659   * @param  EventType: the ADC event type.
00660   *          This parameter can be one of the following values:
00661   *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
00662   *            @arg ADC_OVR_EVENT: ADC Overrun event.
00663   * @param  Timeout: Timeout value in millisecond.
00664   * @retval HAL status
00665   */
00666 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
00667 {
00668   uint32_t tickstart = 0U;
00669
00670   /* Check the parameters */
00671   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00672   assert_param(IS_ADC_EVENT_TYPE(EventType));
00673
00674   /* Get tick */
00675   tickstart = HAL_GetTick();
00676
00677   /* Check selected event flag */
00678   while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
00679   {
00680     /* Check for the Timeout */
00681     if(Timeout != HAL_MAX_DELAY)
00682     {
00683       if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
00684       {
00685         /* Update ADC state machine to timeout */
00686         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00687
00688         /* Process unlocked */
00689         __HAL_UNLOCK(hadc);
00690
00691         return HAL_TIMEOUT;
00692       }
00693     }
00694   }
00695
00696   /* Analog watchdog (level out of window) event */
00697   if(EventType == ADC_AWD_EVENT)
00698   {
00699     /* Set ADC state */
00700     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
00701
00702     /* Clear ADC analog watchdog flag */
00703     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
00704   }
00705   /* Overrun event */
00706   else
00707   {
00708     /* Set ADC state */
00709     SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
00710     /* Set ADC error code to overrun */
00711     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
00712
00713     /* Clear ADC overrun flag */
00714     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
00715   }
00716
00717   /* Return ADC state */
00718   return HAL_OK;
00719 }
00720
00721
00722 /**
00723   * @brief  Enables the interrupt and starts ADC conversion of regular channels.
00724   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00725   *         the configuration information for the specified ADC.
00726   * @retval HAL status.
00727   */
00728 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
00729 {
00730   __IO uint32_t counter = 0U;
00731
00732   /* Check the parameters */
00733   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00734   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00735
00736   /* Process locked */
00737   __HAL_LOCK(hadc);
00738
00739   /* Enable the ADC peripheral */
00740   /* Check if ADC peripheral is disabled in order to enable it and wait during
00741   Tstab time the ADC's stabilization */
00742   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00743   {
00744     /* Enable the Peripheral */
00745     __HAL_ADC_ENABLE(hadc);
00746
00747     /* Delay for ADC stabilization time */
00748     /* Compute number of CPU cycles to wait for */
00749     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
00750     while(counter != 0U)
00751     {
00752       counter--;
00753     }
00754   }
00755
00756   /* Start conversion if ADC is effectively enabled */
00757   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00758   {
00759     /* Set ADC state                                                          */
00760     /* - Clear state bitfield related to regular group conversion results     */
00761     /* - Set state bitfield related to regular group operation                */
00762     ADC_STATE_CLR_SET(hadc->State,
00763                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
00764                       HAL_ADC_STATE_REG_BUSY);
00765
00766     /* If conversions on group regular are also triggering group injected,    */
00767     /* update ADC state.                                                      */
00768     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00769     {
00770       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00771     }
00772
00773     /* State machine update: Check if an injected conversion is ongoing */
00774     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00775     {
00776       /* Reset ADC error code fields related to conversions on group regular */
00777       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
00778     }
00779     else
00780     {
00781       /* Reset ADC all error code fields */
00782       ADC_CLEAR_ERRORCODE(hadc);
00783     }
00784
00785     /* Process unlocked */
00786     /* Unlock before starting ADC conversions: in case of potential           */
00787     /* interruption, to let the process to ADC IRQ Handler.                   */
00788     __HAL_UNLOCK(hadc);
00789
00790     /* Clear regular group conversion flag and overrun flag */
00791     /* (To ensure of no unknown state from potential previous ADC operations) */
00792     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00793
00794     /* Enable end of conversion interrupt for regular group */
00795     __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
00796
00797     /* Check if Multimode enabled */
00798     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00799     {
00800       /* if no external trigger present enable software conversion of regular channels */
00801       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00802       {
00803         /* Enable the selected ADC software conversion for regular group */
00804         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00805       }
00806     }
00807     else
00808     {
00809       /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
00810       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
00811       {
00812         /* Enable the selected ADC software conversion for regular group */
00813           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00814       }
00815     }
00816   }
00817
00818   /* Return function status */
00819   return HAL_OK;
00820 }
00821
00822 /**
00823   * @brief  Disables the interrupt and stop ADC conversion of regular channels.
00824   *
00825   * @note   Caution: This function will stop also injected channels.
00826   *
00827   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00828   *         the configuration information for the specified ADC.
00829   * @retval HAL status.
00830   */
00831 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
00832 {
00833   /* Check the parameters */
00834   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00835
00836   /* Process locked */
00837   __HAL_LOCK(hadc);
00838
00839   /* Stop potential conversion on going, on regular and injected groups */
00840   /* Disable ADC peripheral */
00841   __HAL_ADC_DISABLE(hadc);
00842
00843   /* Check if ADC is effectively disabled */
00844   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00845   {
00846         /* Disable ADC end of conversion interrupt for regular group */
00847     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
00848
00849     /* Set ADC state */
00850     ADC_STATE_CLR_SET(hadc->State,
00851                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00852                       HAL_ADC_STATE_READY);
00853   }
00854
00855   /* Process unlocked */
00856   __HAL_UNLOCK(hadc);
00857
00858   /* Return function status */
00859   return HAL_OK;
00860 }
00861
00862 /**
00863   * @brief  Handles ADC interrupt request
00864   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00865   *         the configuration information for the specified ADC.
00866   * @retval None
00867   */
00868 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
00869 {
00870   uint32_t tmp1 = 0U, tmp2 = 0U;
00871
00872   /* Check the parameters */
00873   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00874   assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
00875   assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
00876
00877   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
00878   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
00879   /* Check End of conversion flag for regular channels */
00880   if(tmp1 && tmp2)
00881   {
00882     /* Update state machine on conversion status if not in error state */
00883     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
00884     {
00885       /* Set ADC state */
00886       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
00887     }
00888
00889     /* Determine whether any further conversion upcoming on group regular   */
00890     /* by external trigger, continuous mode or scan sequence on going.      */
00891     /* Note: On STM32F4, there is no independent flag of end of sequence.   */
00892     /*       The test of scan sequence on going is done either with scan    */
00893     /*       sequence disabled or with end of conversion flag set to        */
00894     /*       of end of sequence.                                            */
00895     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
00896        (hadc->Init.ContinuousConvMode == DISABLE)            &&
00897        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
00898         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
00899     {
00900       /* Disable ADC end of single conversion interrupt on group regular */
00901       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
00902       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
00903       /* by overrun IRQ process below.                                      */
00904       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
00905
00906       /* Set ADC state */
00907       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
00908
00909       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00910       {
00911         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00912       }
00913     }
00914
00915     /* Conversion complete callback */
00916     HAL_ADC_ConvCpltCallback(hadc);
00917
00918     /* Clear regular group conversion flag */
00919     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
00920   }
00921
00922   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
00923   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
00924   /* Check End of conversion flag for injected channels */
00925   if(tmp1 && tmp2)
00926   {
00927     /* Update state machine on conversion status if not in error state */
00928     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
00929     {
00930       /* Set ADC state */
00931       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00932     }
00933
00934     /* Determine whether any further conversion upcoming on group injected  */
00935     /* by external trigger, scan sequence on going or by automatic injected */
00936     /* conversion from group regular (same conditions as group regular      */
00937     /* interruption disabling above).                                       */
00938     if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
00939        (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
00940         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
00941        (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
00942         (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
00943         (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
00944     {
00945       /* Disable ADC end of single conversion interrupt on group injected */
00946       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00947
00948       /* Set ADC state */
00949       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00950
00951       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00952       {
00953         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00954       }
00955     }
00956
00957     /* Conversion complete callback */
00958     HAL_ADCEx_InjectedConvCpltCallback(hadc);
00959
00960     /* Clear injected group conversion flag */
00961     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
00962   }
00963
00964   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
00965   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
00966   /* Check Analog watchdog flag */
00967   if(tmp1 && tmp2)
00968   {
00969     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
00970     {
00971       /* Set ADC state */
00972       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
00973
00974       /* Level out of window callback */
00975       HAL_ADC_LevelOutOfWindowCallback(hadc);
00976
00977       /* Clear the ADC analog watchdog flag */
00978       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
00979     }
00980   }
00981
00982   tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
00983   tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
00984   /* Check Overrun flag */
00985   if(tmp1 && tmp2)
00986   {
00987     /* Note: On STM32F4, ADC overrun can be set through other parameters    */
00988     /*       refer to description of parameter "EOCSelection" for more      */
00989     /*       details.                                                       */
00990
00991     /* Set ADC error code to overrun */
00992     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
00993
00994     /* Clear ADC overrun flag */
00995     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
00996
00997     /* Error callback */
00998     HAL_ADC_ErrorCallback(hadc);
00999
01000     /* Clear the Overrun flag */
01001     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01002   }
01003 }
01004
01005 /**
01006   * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
01007   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01008   *         the configuration information for the specified ADC.
01009   * @param  pData: The destination Buffer address.
01010   * @param  Length: The length of data to be transferred from ADC peripheral to memory.
01011   * @retval HAL status
01012   */
01013 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
01014 {
01015   __IO uint32_t counter = 0U;
01016
01017   /* Check the parameters */
01018   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
01019   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
01020
01021   /* Process locked */
01022   __HAL_LOCK(hadc);
01023
01024   /* Enable the ADC peripheral */
01025   /* Check if ADC peripheral is disabled in order to enable it and wait during
01026   Tstab time the ADC's stabilization */
01027   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
01028   {
01029     /* Enable the Peripheral */
01030     __HAL_ADC_ENABLE(hadc);
01031
01032     /* Delay for ADC stabilization time */
01033     /* Compute number of CPU cycles to wait for */
01034     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
01035     while(counter != 0U)
01036     {
01037       counter--;
01038     }
01039   }
01040
01041   /* Start conversion if ADC is effectively enabled */
01042   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
01043   {
01044     /* Set ADC state                                                          */
01045     /* - Clear state bitfield related to regular group conversion results     */
01046     /* - Set state bitfield related to regular group operation                */
01047     ADC_STATE_CLR_SET(hadc->State,
01048                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
01049                       HAL_ADC_STATE_REG_BUSY);
01050
01051     /* If conversions on group regular are also triggering group injected,    */
01052     /* update ADC state.                                                      */
01053     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
01054     {
01055       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01056     }
01057
01058     /* State machine update: Check if an injected conversion is ongoing */
01059     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01060     {
01061       /* Reset ADC error code fields related to conversions on group regular */
01062       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01063     }
01064     else
01065     {
01066       /* Reset ADC all error code fields */
01067       ADC_CLEAR_ERRORCODE(hadc);
01068     }
01069
01070     /* Process unlocked */
01071     /* Unlock before starting ADC conversions: in case of potential           */
01072     /* interruption, to let the process to ADC IRQ Handler.                   */
01073     __HAL_UNLOCK(hadc);
01074
01075     /* Set the DMA transfer complete callback */
01076     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01077
01078     /* Set the DMA half transfer complete callback */
01079     hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01080
01081     /* Set the DMA error callback */
01082     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01083
01084
01085     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
01086     /* start (in case of SW start):                                           */
01087
01088     /* Clear regular group conversion flag and overrun flag */
01089     /* (To ensure of no unknown state from potential previous ADC operations) */
01090     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01091
01092     /* Enable ADC overrun interrupt */
01093     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01094
01095     /* Enable ADC DMA mode */
01096     hadc->Instance->CR2 |= ADC_CR2_DMA;
01097
01098     /* Start the DMA channel */
01099     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01100
01101     /* Check if Multimode enabled */
01102     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
01103     {
01104       /* if no external trigger present enable software conversion of regular channels */
01105       if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
01106       {
01107         /* Enable the selected ADC software conversion for regular group */
01108         hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
01109       }
01110     }
01111     else
01112     {
01113       /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
01114       if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
01115       {
01116         /* Enable the selected ADC software conversion for regular group */
01117           hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
01118       }
01119     }
01120   }
01121
01122   /* Return function status */
01123   return HAL_OK;
01124 }
01125
01126 /**
01127   * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
01128   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01129   *         the configuration information for the specified ADC.
01130   * @retval HAL status
01131   */
01132 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
01133 {
01134   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01135
01136   /* Check the parameters */
01137   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01138
01139   /* Process locked */
01140   __HAL_LOCK(hadc);
01141
01142   /* Stop potential conversion on going, on regular and injected groups */
01143   /* Disable ADC peripheral */
01144   __HAL_ADC_DISABLE(hadc);
01145
01146   /* Check if ADC is effectively disabled */
01147   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
01148   {
01149     /* Disable the selected ADC DMA mode */
01150     hadc->Instance->CR2 &= ~ADC_CR2_DMA;
01151
01152     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01153     /* DMA transfer is on going)                                              */
01154     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01155
01156     /* Disable ADC overrun interrupt */
01157     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01158
01159     /* Set ADC state */
01160     ADC_STATE_CLR_SET(hadc->State,
01161                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01162                       HAL_ADC_STATE_READY);
01163   }
01164
01165   /* Process unlocked */
01166   __HAL_UNLOCK(hadc);
01167
01168   /* Return function status */
01169   return tmp_hal_status;
01170 }
01171
01172 /**
01173   * @brief  Gets the converted value from data register of regular channel.
01174   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01175   *         the configuration information for the specified ADC.
01176   * @retval Converted value
01177   */
01178 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
01179 {
01180   /* Return the selected ADC converted value */
01181   return hadc->Instance->DR;
01182 }
01183
01184 /**
01185   * @brief  Regular conversion complete callback in non blocking mode
01186   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01187   *         the configuration information for the specified ADC.
01188   * @retval None
01189   */
01190 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
01191 {
01192   /* Prevent unused argument(s) compilation warning */
01193   UNUSED(hadc);
01194   /* NOTE : This function Should not be modified, when the callback is needed,
01195             the HAL_ADC_ConvCpltCallback could be implemented in the user file
01196    */
01197 }
01198
01199 /**
01200   * @brief  Regular conversion half DMA transfer callback in non blocking mode
01201   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01202   *         the configuration information for the specified ADC.
01203   * @retval None
01204   */
01205 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
01206 {
01207   /* Prevent unused argument(s) compilation warning */
01208   UNUSED(hadc);
01209   /* NOTE : This function Should not be modified, when the callback is needed,
01210             the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
01211    */
01212 }
01213
01214 /**
01215   * @brief  Analog watchdog callback in non blocking mode
01216   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01217   *         the configuration information for the specified ADC.
01218   * @retval None
01219   */
01220 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
01221 {
01222   /* Prevent unused argument(s) compilation warning */
01223   UNUSED(hadc);
01224   /* NOTE : This function Should not be modified, when the callback is needed,
01225             the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
01226    */
01227 }
01228
01229 /**
01230   * @brief  Error ADC callback.
01231   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01232   *         the configuration information for the specified ADC.
01233   * @retval None
01234   */
01235 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
01236 {
01237   /* Prevent unused argument(s) compilation warning */
01238   UNUSED(hadc);
01239   /* NOTE : This function Should not be modified, when the callback is needed,
01240             the HAL_ADC_ErrorCallback could be implemented in the user file
01241    */
01242 }
01243
01244 /**
01245   * @}
01246   */
01247
01248 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
01249  *  @brief      Peripheral Control functions
01250  *
01251 @verbatim
01252  ===============================================================================
01253              ##### Peripheral Control functions #####
01254  ===============================================================================
01255     [..]  This section provides functions allowing to:
01256       (+) Configure regular channels.
01257       (+) Configure injected channels.
01258       (+) Configure multimode.
01259       (+) Configure the analog watch dog.
01260
01261 @endverbatim
01262   * @{
01263   */
01264
01265   /**
01266   * @brief  Configures for the selected ADC regular channel its corresponding
01267   *         rank in the sequencer and its sample time.
01268   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01269   *         the configuration information for the specified ADC.
01270   * @param  sConfig: ADC configuration structure.
01271   * @retval HAL status
01272   */
01273 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
01274 {
01275   __IO uint32_t counter = 0U;
01276
01277   /* Check the parameters */
01278   assert_param(IS_ADC_CHANNEL(sConfig->Channel));
01279   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
01280   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
01281
01282   /* Process locked */
01283   __HAL_LOCK(hadc);
01284
01285   /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
01286   if (sConfig->Channel > ADC_CHANNEL_9)
01287   {
01288     /* Clear the old sample time */
01289     hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
01290
01291     /* Set the new sample time */
01292     hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
01293   }
01294   else /* ADC_Channel include in ADC_Channel_[0..9] */
01295   {
01296     /* Clear the old sample time */
01297     hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
01298
01299     /* Set the new sample time */
01300     hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
01301   }
01302
01303   /* For Rank 1 to 6 */
01304   if (sConfig->Rank < 7U)
01305   {
01306     /* Clear the old SQx bits for the selected rank */
01307     hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
01308
01309     /* Set the SQx bits for the selected rank */
01310     hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
01311   }
01312   /* For Rank 7 to 12 */
01313   else if (sConfig->Rank < 13U)
01314   {
01315     /* Clear the old SQx bits for the selected rank */
01316     hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
01317
01318     /* Set the SQx bits for the selected rank */
01319     hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
01320   }
01321   /* For Rank 13 to 16 */
01322   else
01323   {
01324     /* Clear the old SQx bits for the selected rank */
01325     hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
01326
01327     /* Set the SQx bits for the selected rank */
01328     hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
01329   }
01330
01331   /* if ADC1 Channel_18 is selected enable VBAT Channel */
01332   if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
01333   {
01334     /* Enable the VBAT channel*/
01335     ADC->CCR |= ADC_CCR_VBATE;
01336   }
01337
01338   /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
01339   if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
01340   {
01341     /* Enable the TSVREFE channel*/
01342     ADC->CCR |= ADC_CCR_TSVREFE;
01343
01344     if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
01345     {
01346       /* Delay for temperature sensor stabilization time */
01347       /* Compute number of CPU cycles to wait for */
01348       counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
01349       while(counter != 0U)
01350       {
01351         counter--;
01352       }
01353     }
01354   }
01355
01356   /* Process unlocked */
01357   __HAL_UNLOCK(hadc);
01358
01359   /* Return function status */
01360   return HAL_OK;
01361 }
01362
01363 /**
01364   * @brief  Configures the analog watchdog.
01365   * @note Analog watchdog thresholds can be modified while ADC conversion
01366   * is on going.
01367   * In this case, some constraints must be taken into account:
01368   * The programmed threshold values are effective from the next
01369   * ADC EOC (end of unitary conversion).
01370   * Considering that registers write delay may happen due to
01371   * bus activity, this might cause an uncertainty on the
01372   * effective timing of the new programmed threshold values.
01373   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01374   *         the configuration information for the specified ADC.
01375   * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
01376   *         that contains the configuration information of ADC analog watchdog.
01377   * @retval HAL status
01378   */
01379 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
01380 {
01381 #ifdef USE_FULL_ASSERT
01382   uint32_t tmp = 0U;
01383 #endif /* USE_FULL_ASSERT  */
01384
01385   /* Check the parameters */
01386   assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
01387   assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
01388   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
01389
01390 #ifdef USE_FULL_ASSERT
01391   tmp = ADC_GET_RESOLUTION(hadc);
01392   assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
01393   assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
01394 #endif /* USE_FULL_ASSERT  */
01395
01396   /* Process locked */
01397   __HAL_LOCK(hadc);
01398
01399   if(AnalogWDGConfig->ITMode == ENABLE)
01400   {
01401     /* Enable the ADC Analog watchdog interrupt */
01402     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
01403   }
01404   else
01405   {
01406     /* Disable the ADC Analog watchdog interrupt */
01407     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
01408   }
01409
01410   /* Clear AWDEN, JAWDEN and AWDSGL bits */
01411   hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
01412
01413   /* Set the analog watchdog enable mode */
01414   hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
01415
01416   /* Set the high threshold */
01417   hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
01418
01419   /* Set the low threshold */
01420   hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
01421
01422   /* Clear the Analog watchdog channel select bits */
01423   hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
01424
01425   /* Set the Analog watchdog channel */
01426   hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
01427
01428   /* Process unlocked */
01429   __HAL_UNLOCK(hadc);
01430
01431   /* Return function status */
01432   return HAL_OK;
01433 }
01434
01435 /**
01436   * @}
01437   */
01438
01439 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
01440  *  @brief   ADC Peripheral State functions
01441  *
01442 @verbatim
01443  ===============================================================================
01444             ##### Peripheral State and errors functions #####
01445  ===============================================================================
01446     [..]
01447     This subsection provides functions allowing to
01448       (+) Check the ADC state
01449       (+) Check the ADC Error
01450
01451 @endverbatim
01452   * @{
01453   */
01454
01455 /**
01456   * @brief  return the ADC state
01457   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01458   *         the configuration information for the specified ADC.
01459   * @retval HAL state
01460   */
01461 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
01462 {
01463   /* Return ADC state */
01464   return hadc->State;
01465 }
01466
01467 /**
01468   * @brief  Return the ADC error code
01469   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01470   *         the configuration information for the specified ADC.
01471   * @retval ADC Error Code
01472   */
01473 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
01474 {
01475   return hadc->ErrorCode;
01476 }
01477
01478 /**
01479   * @}
01480   */
01481
01482 /** @addtogroup ADC_Private_Functions
01483   * @{
01484   */
01485
01486 /**
01487   * @brief  Initializes the ADCx peripheral according to the specified parameters
01488   *         in the ADC_InitStruct without initializing the ADC MSP.
01489   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
01490   *         the configuration information for the specified ADC.
01491   * @retval None
01492   */
01493 static void ADC_Init(ADC_HandleTypeDef* hadc)
01494 {
01495   /* Set ADC parameters */
01496   /* Set the ADC clock prescaler */
01497   ADC->CCR &= ~(ADC_CCR_ADCPRE);
01498   ADC->CCR |=  hadc->Init.ClockPrescaler;
01499
01500   /* Set ADC scan mode */
01501   hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
01502   hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
01503
01504   /* Set ADC resolution */
01505   hadc->Instance->CR1 &= ~(ADC_CR1_RES);
01506   hadc->Instance->CR1 |=  hadc->Init.Resolution;
01507
01508   /* Set ADC data alignment */
01509   hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
01510   hadc->Instance->CR2 |= hadc->Init.DataAlign;
01511
01512   /* Enable external trigger if trigger selection is different of software  */
01513   /* start.                                                                 */
01514   /* Note: This configuration keeps the hardware feature of parameter       */
01515   /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
01516   /*       software start.                                                  */
01517   if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
01518   {
01519     /* Select external trigger to start conversion */
01520     hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
01521     hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
01522
01523     /* Select external trigger polarity */
01524     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
01525     hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
01526   }
01527   else
01528   {
01529     /* Reset the external trigger */
01530     hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
01531     hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
01532   }
01533
01534   /* Enable or disable ADC continuous conversion mode */
01535   hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
01536   hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
01537
01538   if(hadc->Init.DiscontinuousConvMode != DISABLE)
01539   {
01540     assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
01541
01542     /* Enable the selected ADC regular discontinuous mode */
01543     hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
01544
01545     /* Set the number of channels to be converted in discontinuous mode */
01546     hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
01547     hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
01548   }
01549   else
01550   {
01551     /* Disable the selected ADC regular discontinuous mode */
01552     hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
01553   }
01554
01555   /* Set ADC number of conversion */
01556   hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
01557   hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);
01558
01559   /* Enable or disable ADC DMA continuous request */
01560   hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
01561   hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
01562
01563   /* Enable or disable ADC end of conversion selection */
01564   hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
01565   hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
01566 }
01567
01568 /**
01569   * @brief  DMA transfer complete callback.
01570   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01571   *                the configuration information for the specified DMA module.
01572   * @retval None
01573   */
01574 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
01575 {
01576   /* Retrieve ADC handle corresponding to current DMA handle */
01577   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01578
01579   /* Update state machine on conversion status if not in error state */
01580   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
01581   {
01582     /* Update ADC state machine */
01583     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01584
01585     /* Determine whether any further conversion upcoming on group regular   */
01586     /* by external trigger, continuous mode or scan sequence on going.      */
01587     /* Note: On STM32F4, there is no independent flag of end of sequence.   */
01588     /*       The test of scan sequence on going is done either with scan    */
01589     /*       sequence disabled or with end of conversion flag set to        */
01590     /*       of end of sequence.                                            */
01591     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
01592        (hadc->Init.ContinuousConvMode == DISABLE)            &&
01593        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
01594         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
01595     {
01596       /* Disable ADC end of single conversion interrupt on group regular */
01597       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
01598       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
01599       /* by overrun IRQ process below.                                      */
01600       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
01601
01602       /* Set ADC state */
01603       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01604
01605       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01606       {
01607         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01608       }
01609     }
01610
01611     /* Conversion complete callback */
01612     HAL_ADC_ConvCpltCallback(hadc);
01613   }
01614   else
01615   {
01616     /* Call DMA error callback */
01617     hadc->DMA_Handle->XferErrorCallback(hdma);
01618   }
01619 }
01620
01621 /**
01622   * @brief  DMA half transfer complete callback.
01623   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01624   *                the configuration information for the specified DMA module.
01625   * @retval None
01626   */
01627 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
01628 {
01629   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01630   /* Conversion complete callback */
01631   HAL_ADC_ConvHalfCpltCallback(hadc);
01632 }
01633
01634 /**
01635   * @brief  DMA error callback
01636   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01637   *                the configuration information for the specified DMA module.
01638   * @retval None
01639   */
01640 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
01641 {
01642   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01643   hadc->State= HAL_ADC_STATE_ERROR_DMA;
01644   /* Set ADC error code to DMA error */
01645   hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
01646   HAL_ADC_ErrorCallback(hadc);
01647 }
01648
01649 /**
01650   * @}
01651   */
01652
01653 /**
01654   * @}
01655   */
01656
01657 #endif /* HAL_ADC_MODULE_ENABLED */
01658 /**
01659   * @}
01660   */
01661
01662 /**
01663   * @}
01664   */
01665
01666 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:50 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc.h Source File

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stm32f4xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file containing functions prototypes of ADC HAL library.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_ADC_H
00040 #define __STM32F4xx_ADC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADC_Exported_Types ADC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  Structure definition of ADC and regular group initialization
00064   * @note   Parameters of this structure are shared within 2 scopes:
00065   *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
00066   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
00067   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
00068   *         ADC state can be either:
00069   *          - For all parameters: ADC disabled
00070   *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
00071   *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
00072   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00073   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00074   */
00075 typedef struct
00076 {
00077   uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for
00078                                        all the ADCs.
00079                                        This parameter can be a value of @ref ADC_ClockPrescaler */
00080   uint32_t Resolution;            /*!< Configures the ADC resolution.
00081                                        This parameter can be a value of @ref ADC_Resolution */
00082   uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
00083                                        or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
00084                                        This parameter can be a value of @ref ADC_Data_align */
00085   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
00086                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00087                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
00088                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00089                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
00090                                                     Scan direction is upward: from rank1 to rank 'n'.
00091                                        This parameter can be set to ENABLE or DISABLE */
00092   uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
00093                                        This parameter can be a value of @ref ADC_EOCSelection.
00094                                        Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
00095                                              Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
00096                                              or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
00097                                        Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
00098                                              If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
00099   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
00100                                        after the selected trigger occurred (software start or external trigger).
00101                                        This parameter can be set to ENABLE or DISABLE. */
00102   uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
00103                                        To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00104                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
00105   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00106                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00107                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00108                                        This parameter can be set to ENABLE or DISABLE. */
00109   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
00110                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00111                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00112   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
00113                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
00114                                        If set to external trigger source, triggering is on event rising edge by default.
00115                                        This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
00116   uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
00117                                        If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
00118                                        This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
00119   uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
00120                                        or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
00121                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
00122                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
00123                                        This parameter can be set to ENABLE or DISABLE. */
00124 }ADC_InitTypeDef;
00125
00126
00127
00128 /**
00129   * @brief  Structure definition of ADC channel for regular group
00130   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00131   *         ADC can be either disabled or enabled without conversion on going on regular group.
00132   */
00133 typedef struct
00134 {
00135   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
00136                                         This parameter can be a value of @ref ADC_channels */
00137   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
00138                                         This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00139   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00140                                         Unit: ADC clock cycles
00141                                         Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
00142                                         This parameter can be a value of @ref ADC_sampling_times
00143                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00144                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00145                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00146                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00147                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
00148   uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
00149 }ADC_ChannelConfTypeDef;
00150
00151 /**
00152   * @brief ADC Configuration multi-mode structure definition
00153   */
00154 typedef struct
00155 {
00156   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
00157                                    This parameter can be a value of @ref ADC_analog_watchdog_selection */
00158   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
00159                                    This parameter must be a 12-bit value. */
00160   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
00161                                    This parameter must be a 12-bit value. */
00162   uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog.
00163                                    This parameter has an effect only if watchdog mode is configured on single channel
00164                                    This parameter can be a value of @ref ADC_channels */
00165   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured
00166                                    is interrupt mode or in polling mode.
00167                                    This parameter can be set to ENABLE or DISABLE */
00168   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
00169 }ADC_AnalogWDGConfTypeDef;
00170
00171 /**
00172   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00173   */
00174 /* States of ADC global scope */
00175 #define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000U)    /*!< ADC not yet initialized or disabled */
00176 #define HAL_ADC_STATE_READY             ((uint32_t)0x00000001U)    /*!< ADC peripheral ready for use */
00177 #define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
00178 #define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004U)    /*!< TimeOut occurrence */
00179
00180 /* States of ADC errors */
00181 #define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010U)    /*!< Internal error occurrence */
00182 #define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020U)    /*!< Configuration error occurrence */
00183 #define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040U)    /*!< DMA error occurrence */
00184
00185 /* States of ADC group regular */
00186 #define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
00187                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00188 #define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200U)    /*!< Conversion data available on group regular */
00189 #define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400U)    /*!< Overrun occurrence */
00190
00191 /* States of ADC group injected */
00192 #define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
00193                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00194 #define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000U)    /*!< Conversion data available on group injected */
00195
00196 /* States of ADC analog watchdogs */
00197 #define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
00198 #define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000U)    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
00199 #define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000U)    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
00200
00201 /* States of ADC multi-mode */
00202 #define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000U)    /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
00203
00204
00205 /**
00206   * @brief  ADC handle Structure definition
00207   */
00208 typedef struct
00209 {
00210   ADC_TypeDef                   *Instance;                   /*!< Register base address */
00211
00212   ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
00213
00214   __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
00215
00216   DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
00217
00218   HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
00219
00220   __IO uint32_t                 State;                       /*!< ADC communication state */
00221
00222   __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
00223 }ADC_HandleTypeDef;
00224 /**
00225   * @}
00226   */
00227
00228 /* Exported constants --------------------------------------------------------*/
00229 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00230   * @{
00231   */
00232
00233 /** @defgroup ADC_Error_Code ADC Error Code
00234   * @{
00235   */
00236 #define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                              */
00237 #define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error: if problem of clocking,
00238                                                           enable/disable, erroneous state                       */
00239 #define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                                         */
00240 #define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                                    */
00241 /**
00242   * @}
00243   */
00244
00245
00246 /** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
00247   * @{
00248   */
00249 #define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000U)
00250 #define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
00251 #define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
00252 #define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
00258   * @{
00259   */
00260 #define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000U)
00261 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
00262 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
00263 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
00264 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
00265 #define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
00266 #define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
00267 #define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
00268 #define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
00269 #define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
00270 #define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
00271 #define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
00272 #define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
00273 #define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
00274 #define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
00275 #define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup ADC_Resolution ADC Resolution
00281   * @{
00282   */
00283 #define ADC_RESOLUTION_12B  ((uint32_t)0x00000000U)
00284 #define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
00285 #define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
00286 #define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
00292   * @{
00293   */
00294 #define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)
00295 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
00296 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
00297 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
00303   * @{
00304   */
00305 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
00306 /*       compatibility with other STM32 devices.                              */
00307 #define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000U)
00308 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
00309 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
00310 #define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00311 #define ADC_EXTERNALTRIGCONV_T2_CC3    ((uint32_t)ADC_CR2_EXTSEL_2)
00312 #define ADC_EXTERNALTRIGCONV_T2_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
00313 #define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
00314 #define ADC_EXTERNALTRIGCONV_T3_CC1    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00315 #define ADC_EXTERNALTRIGCONV_T3_TRGO   ((uint32_t)ADC_CR2_EXTSEL_3)
00316 #define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
00317 #define ADC_EXTERNALTRIGCONV_T5_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
00318 #define ADC_EXTERNALTRIGCONV_T5_CC2    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00319 #define ADC_EXTERNALTRIGCONV_T5_CC3    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
00320 #define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
00321 #define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
00322 #define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
00323 #define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1U)
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup ADC_Data_align ADC Data Align
00329   * @{
00330   */
00331 #define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)
00332 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup ADC_channels  ADC Common Channels
00338   * @{
00339   */
00340 #define ADC_CHANNEL_0           ((uint32_t)0x00000000U)
00341 #define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
00342 #define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
00343 #define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00344 #define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
00345 #define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
00346 #define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
00347 #define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00348 #define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
00349 #define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
00350 #define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
00351 #define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00352 #define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
00353 #define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
00354 #define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
00355 #define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
00356 #define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
00357 #define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
00358 #define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
00359
00360 #define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
00361 #define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup ADC_sampling_times  ADC Sampling Times
00367   * @{
00368   */
00369 #define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000U)
00370 #define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
00371 #define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
00372 #define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
00373 #define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
00374 #define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
00375 #define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
00376 #define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
00377 /**
00378   * @}
00379   */
00380
00381   /** @defgroup ADC_EOCSelection ADC EOC Selection
00382   * @{
00383   */
00384 #define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000U)
00385 #define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001U)
00386 #define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002U)  /*!< reserved for future use */
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup ADC_Event_type ADC Event Type
00392   * @{
00393   */
00394 #define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
00395 #define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
00401   * @{
00402   */
00403 #define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
00404 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
00405 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
00406 #define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
00407 #define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
00408 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
00409 #define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000U)
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
00415   * @{
00416   */
00417 #define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)
00418 #define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)
00419 #define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
00420 #define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup ADC_flags_definition ADC Flags Definition
00426   * @{
00427   */
00428 #define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
00429 #define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
00430 #define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
00431 #define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
00432 #define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
00433 #define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
00434 /**
00435   * @}
00436   */
00437
00438 /** @defgroup ADC_channels_type ADC Channels Type
00439   * @{
00440   */
00441 #define ADC_ALL_CHANNELS      ((uint32_t)0x00000001U)
00442 #define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002U) /*!< reserved for future use */
00443 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
00444 /**
00445   * @}
00446   */
00447
00448 /**
00449   * @}
00450   */
00451
00452 /* Exported macro ------------------------------------------------------------*/
00453 /** @defgroup ADC_Exported_Macros ADC Exported Macros
00454   * @{
00455   */
00456
00457 /** @brief Reset ADC handle state
00458   * @param  __HANDLE__: ADC handle
00459   * @retval None
00460   */
00461 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
00462
00463 /**
00464   * @brief  Enable the ADC peripheral.
00465   * @param  __HANDLE__: ADC handle
00466   * @retval None
00467   */
00468 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
00469
00470 /**
00471   * @brief  Disable the ADC peripheral.
00472   * @param  __HANDLE__: ADC handle
00473   * @retval None
00474   */
00475 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
00476
00477 /**
00478   * @brief  Enable the ADC end of conversion interrupt.
00479   * @param  __HANDLE__: specifies the ADC Handle.
00480   * @param  __INTERRUPT__: ADC Interrupt.
00481   * @retval None
00482   */
00483 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
00484
00485 /**
00486   * @brief  Disable the ADC end of conversion interrupt.
00487   * @param  __HANDLE__: specifies the ADC Handle.
00488   * @param  __INTERRUPT__: ADC interrupt.
00489   * @retval None
00490   */
00491 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
00492
00493 /** @brief  Check if the specified ADC interrupt source is enabled or disabled.
00494   * @param  __HANDLE__: specifies the ADC Handle.
00495   * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
00496   * @retval The new state of __IT__ (TRUE or FALSE).
00497   */
00498 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
00499
00500 /**
00501   * @brief  Clear the ADC's pending flags.
00502   * @param  __HANDLE__: specifies the ADC Handle.
00503   * @param  __FLAG__: ADC flag.
00504   * @retval None
00505   */
00506 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
00507
00508 /**
00509   * @brief  Get the selected ADC's flag status.
00510   * @param  __HANDLE__: specifies the ADC Handle.
00511   * @param  __FLAG__: ADC flag.
00512   * @retval None
00513   */
00514 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00515
00516 /**
00517   * @}
00518   */
00519
00520 /* Include ADC HAL Extension module */
00521 #include "stm32f4xx_hal_adc_ex.h"
00522
00523 /* Exported functions --------------------------------------------------------*/
00524 /** @addtogroup ADC_Exported_Functions
00525   * @{
00526   */
00527
00528 /** @addtogroup ADC_Exported_Functions_Group1
00529   * @{
00530   */
00531 /* Initialization/de-initialization functions ***********************************/
00532 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
00533 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
00534 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
00535 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
00536 /**
00537   * @}
00538   */
00539
00540 /** @addtogroup ADC_Exported_Functions_Group2
00541   * @{
00542   */
00543 /* I/O operation functions ******************************************************/
00544 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
00545 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
00546 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00547
00548 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
00549
00550 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
00551 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
00552
00553 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
00554
00555 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00556 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
00557
00558 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
00559
00560 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
00561 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
00562 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
00563 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
00564 /**
00565   * @}
00566   */
00567
00568 /** @addtogroup ADC_Exported_Functions_Group3
00569   * @{
00570   */
00571 /* Peripheral Control functions *************************************************/
00572 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
00573 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
00574 /**
00575   * @}
00576   */
00577
00578 /** @addtogroup ADC_Exported_Functions_Group4
00579   * @{
00580   */
00581 /* Peripheral State functions ***************************************************/
00582 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
00583 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
00584 /**
00585   * @}
00586   */
00587
00588 /**
00589   * @}
00590   */
00591 /* Private types -------------------------------------------------------------*/
00592 /* Private variables ---------------------------------------------------------*/
00593 /* Private constants ---------------------------------------------------------*/
00594 /** @defgroup ADC_Private_Constants ADC Private Constants
00595   * @{
00596   */
00597 /* Delay for ADC stabilization time.                                        */
00598 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
00599 /* Unit: us                                                                 */
00600 #define ADC_STAB_DELAY_US               ((uint32_t) 3U)
00601 /* Delay for temperature sensor stabilization time.                         */
00602 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
00603 /* Unit: us                                                                 */
00604 #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10U)
00605 /**
00606   * @}
00607   */
00608
00609 /* Private macro ------------------------------------------------------------*/
00610
00611 /** @defgroup ADC_Private_Macros ADC Private Macros
00612   * @{
00613   */
00614 /* Macro reserved for internal HAL driver usage, not intended to be used in
00615    code of final user */
00616
00617 /**
00618   * @brief Verification of ADC state: enabled or disabled
00619   * @param __HANDLE__: ADC handle
00620   * @retval SET (ADC enabled) or RESET (ADC disabled)
00621   */
00622 #define ADC_IS_ENABLE(__HANDLE__)                                              \
00623   ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
00624   ) ? SET : RESET)
00625
00626 /**
00627   * @brief Test if conversion trigger of regular group is software start
00628   *        or external trigger.
00629   * @param __HANDLE__: ADC handle
00630   * @retval SET (software start) or RESET (external trigger)
00631   */
00632 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
00633   (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00634
00635 /**
00636   * @brief Test if conversion trigger of injected group is software start
00637   *        or external trigger.
00638   * @param __HANDLE__: ADC handle
00639   * @retval SET (software start) or RESET (external trigger)
00640   */
00641 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
00642   (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
00643
00644 /**
00645   * @brief Simultaneously clears and sets specific bits of the handle State
00646   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00647   *        the first parameter is the ADC handle State, the second parameter is the
00648   *        bit field to clear, the third and last parameter is the bit field to set.
00649   * @retval None
00650   */
00651 #define ADC_STATE_CLR_SET MODIFY_REG
00652
00653 /**
00654   * @brief Clear ADC error code (set it to error code: "no error")
00655   * @param __HANDLE__: ADC handle
00656   * @retval None
00657   */
00658 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
00659   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00660
00661
00662 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK)     (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
00663                                               ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
00664                                               ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
00665                                               ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
00666 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
00667                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
00668                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
00669                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
00670                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
00671                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
00672                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
00673                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
00674                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
00675                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
00676                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
00677                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
00678                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
00679                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
00680                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
00681                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
00682 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
00683                                        ((RESOLUTION) == ADC_RESOLUTION_10B) || \
00684                                        ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
00685                                        ((RESOLUTION) == ADC_RESOLUTION_6B))
00686 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
00687                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
00688                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
00689                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
00690 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \
00691                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \
00692                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \
00693                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \
00694                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \
00695                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \
00696                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
00697                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \
00698                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
00699                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \
00700                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \
00701                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \
00702                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \
00703                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \
00704                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
00705                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
00706                                   ((REGTRIG) == ADC_SOFTWARE_START))
00707 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
00708                                   ((ALIGN) == ADC_DATAALIGN_LEFT))
00709 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES)   || \
00710                                   ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \
00711                                   ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \
00712                                   ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \
00713                                   ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \
00714                                   ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
00715                                   ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
00716                                   ((TIME) == ADC_SAMPLETIME_480CYCLES))
00717 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV)   || \
00718                                            ((EOCSelection) == ADC_EOC_SEQ_CONV)  || \
00719                                            ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
00720 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
00721                                   ((EVENT) == ADC_OVR_EVENT))
00722 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
00723                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
00724                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
00725                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
00726                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
00727                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
00728                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
00729 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
00730                                             ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
00731                                             ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
00732 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFFU))
00733
00734 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
00735 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)16U)))
00736 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1U)) && ((NUMBER) <= ((uint32_t)8U)))
00737 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
00738    ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
00739     (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
00740     (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
00741     (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
00742
00743 /**
00744   * @brief  Set ADC Regular channel sequence length.
00745   * @param  _NbrOfConversion_: Regular channel sequence length.
00746   * @retval None
00747   */
00748 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
00749
00750 /**
00751   * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
00752   * @param  _SAMPLETIME_: Sample time parameter.
00753   * @param  _CHANNELNB_: Channel number.
00754   * @retval None
00755   */
00756 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
00757
00758 /**
00759   * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
00760   * @param  _SAMPLETIME_: Sample time parameter.
00761   * @param  _CHANNELNB_: Channel number.
00762   * @retval None
00763   */
00764 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
00765
00766 /**
00767   * @brief  Set the selected regular channel rank for rank between 1 and 6.
00768   * @param  _CHANNELNB_: Channel number.
00769   * @param  _RANKNB_: Rank number.
00770   * @retval None
00771   */
00772 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
00773
00774 /**
00775   * @brief  Set the selected regular channel rank for rank between 7 and 12.
00776   * @param  _CHANNELNB_: Channel number.
00777   * @param  _RANKNB_: Rank number.
00778   * @retval None
00779   */
00780 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
00781
00782 /**
00783   * @brief  Set the selected regular channel rank for rank between 13 and 16.
00784   * @param  _CHANNELNB_: Channel number.
00785   * @param  _RANKNB_: Rank number.
00786   * @retval None
00787   */
00788 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
00789
00790 /**
00791   * @brief  Enable ADC continuous conversion mode.
00792   * @param  _CONTINUOUS_MODE_: Continuous mode.
00793   * @retval None
00794   */
00795 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
00796
00797 /**
00798   * @brief  Configures the number of discontinuous conversions for the regular group channels.
00799   * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
00800   * @retval None
00801   */
00802 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
00803
00804 /**
00805   * @brief  Enable ADC scan mode.
00806   * @param  _SCANCONV_MODE_: Scan conversion mode.
00807   * @retval None
00808   */
00809 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
00810
00811 /**
00812   * @brief  Enable the ADC end of conversion selection.
00813   * @param  _EOCSelection_MODE_: End of conversion selection mode.
00814   * @retval None
00815   */
00816 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
00817
00818 /**
00819   * @brief  Enable the ADC DMA continuous request.
00820   * @param  _DMAContReq_MODE_: DMA continuous request mode.
00821   * @retval None
00822   */
00823 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
00824
00825 /**
00826   * @brief Return resolution bits in CR1 register.
00827   * @param __HANDLE__: ADC handle
00828   * @retval None
00829   */
00830 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
00831
00832 /**
00833   * @}
00834   */
00835
00836 /* Private functions ---------------------------------------------------------*/
00837 /** @defgroup ADC_Private_Functions ADC Private Functions
00838   * @{
00839   */
00840
00841 /**
00842   * @}
00843   */
00844
00845 /**
00846   * @}
00847   */
00848
00849 /**
00850   * @}
00851   */
00852
00853 #ifdef __cplusplus
00854 }
00855 #endif
00856
00857 #endif /*__STM32F4xx_ADC_H */
00858
00859
00860 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:50 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc_ex.c Source File

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stm32f4xx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the ADC extension peripheral:
00009   *           + Extended features functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016     (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
00017        (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
00018        (##) ADC pins configuration
00019              (+++) Enable the clock for the ADC GPIOs using the following function:
00020                    __HAL_RCC_GPIOx_CLK_ENABLE()
00021              (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
00022        (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
00023              (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
00024              (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
00025              (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
00026       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
00027              (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
00028              (+++) Configure and enable two DMA streams stream for managing data
00029                  transfer from peripheral to memory (output stream)
00030              (+++) Associate the initialized DMA handle to the ADC DMA handle
00031                  using  __HAL_LINKDMA()
00032              (+++) Configure the priority and enable the NVIC for the transfer complete
00033                  interrupt on the two DMA Streams. The output stream should have higher
00034                  priority than the input stream.
00035      (#) Configure the ADC Prescaler, conversion resolution and data alignment
00036          using the HAL_ADC_Init() function.
00037
00038      (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
00039          and HAL_ADC_ConfigChannel() functions.
00040
00041      (#) Three operation modes are available within this driver :
00042
00043      *** Polling mode IO operation ***
00044      =================================
00045      [..]
00046        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
00047        (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
00048            user can specify the value of timeout according to his end application
00049        (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
00050        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
00051
00052      *** Interrupt mode IO operation ***
00053      ===================================
00054      [..]
00055        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
00056        (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
00057        (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
00058             add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
00059        (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
00060             add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
00061        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
00062
00063
00064      *** DMA mode IO operation ***
00065      ==============================
00066      [..]
00067        (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
00068            of data to be transferred at each end of conversion
00069        (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
00070             add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
00071        (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
00072             add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
00073         (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
00074
00075      *** Multi mode ADCs Regular channels configuration ***
00076      ======================================================
00077      [..]
00078        (+) Select the Multi mode ADC regular channels features (dual or triple mode)
00079           and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
00080        (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
00081            of data to be transferred at each end of conversion
00082        (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
00083
00084
00085     @endverbatim
00086   ******************************************************************************
00087   * @attention
00088   *
00089   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00090   *
00091   * Redistribution and use in source and binary forms, with or without modification,
00092   * are permitted provided that the following conditions are met:
00093   *   1. Redistributions of source code must retain the above copyright notice,
00094   *      this list of conditions and the following disclaimer.
00095   *   2. Redistributions in binary form must reproduce the above copyright notice,
00096   *      this list of conditions and the following disclaimer in the documentation
00097   *      and/or other materials provided with the distribution.
00098   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00099   *      may be used to endorse or promote products derived from this software
00100   *      without specific prior written permission.
00101   *
00102   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00103   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00104   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00105   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00106   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00107   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00108   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00109   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00110   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00111   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00112   *
00113   ******************************************************************************
00114   */
00115
00116 /* Includes ------------------------------------------------------------------*/
00117 #include "stm32f4xx_hal.h"
00118
00119 /** @addtogroup STM32F4xx_HAL_Driver
00120   * @{
00121   */
00122
00123 /** @defgroup ADCEx ADCEx
00124   * @brief ADC Extended driver modules
00125   * @{
00126   */
00127
00128 #ifdef HAL_ADC_MODULE_ENABLED
00129
00130 /* Private typedef -----------------------------------------------------------*/
00131 /* Private define ------------------------------------------------------------*/
00132 /* Private macro -------------------------------------------------------------*/
00133 /* Private variables ---------------------------------------------------------*/
00134 /** @addtogroup ADCEx_Private_Functions
00135   * @{
00136   */
00137 /* Private function prototypes -----------------------------------------------*/
00138 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
00139 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
00140 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported functions --------------------------------------------------------*/
00146 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions
00151   *  @brief    Extended features functions
00152   *
00153 @verbatim
00154  ===============================================================================
00155                  ##### Extended features functions #####
00156  ===============================================================================
00157     [..]  This section provides functions allowing to:
00158       (+) Start conversion of injected channel.
00159       (+) Stop conversion of injected channel.
00160       (+) Start multimode and enable DMA transfer.
00161       (+) Stop multimode and disable DMA transfer.
00162       (+) Get result of injected channel conversion.
00163       (+) Get result of multimode conversion.
00164       (+) Configure injected channels.
00165       (+) Configure multimode.
00166
00167 @endverbatim
00168   * @{
00169   */
00170
00171 /**
00172   * @brief  Enables the selected ADC software start conversion of the injected channels.
00173   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00174   *         the configuration information for the specified ADC.
00175   * @retval HAL status
00176   */
00177 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
00178 {
00179   __IO uint32_t counter = 0U;
00180   uint32_t tmp1 = 0U, tmp2 = 0U;
00181
00182   /* Process locked */
00183   __HAL_LOCK(hadc);
00184
00185   /* Enable the ADC peripheral */
00186
00187   /* Check if ADC peripheral is disabled in order to enable it and wait during
00188      Tstab time the ADC's stabilization */
00189   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00190   {
00191     /* Enable the Peripheral */
00192     __HAL_ADC_ENABLE(hadc);
00193
00194     /* Delay for ADC stabilization time */
00195     /* Compute number of CPU cycles to wait for */
00196     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
00197     while(counter != 0U)
00198     {
00199       counter--;
00200     }
00201   }
00202
00203   /* Start conversion if ADC is effectively enabled */
00204   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00205   {
00206     /* Set ADC state                                                          */
00207     /* - Clear state bitfield related to injected group conversion results    */
00208     /* - Set state bitfield related to injected operation                     */
00209     ADC_STATE_CLR_SET(hadc->State,
00210                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00211                       HAL_ADC_STATE_INJ_BUSY);
00212
00213     /* Check if a regular conversion is ongoing */
00214     /* Note: On this device, there is no ADC error code fields related to     */
00215     /*       conversions on group injected only. In case of conversion on     */
00216     /*       going on group regular, no error code is reset.                  */
00217     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00218     {
00219       /* Reset ADC all error code fields */
00220       ADC_CLEAR_ERRORCODE(hadc);
00221     }
00222
00223     /* Process unlocked */
00224     /* Unlock before starting ADC conversions: in case of potential           */
00225     /* interruption, to let the process to ADC IRQ Handler.                   */
00226     __HAL_UNLOCK(hadc);
00227
00228     /* Clear injected group conversion flag */
00229     /* (To ensure of no unknown state from potential previous ADC operations) */
00230     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00231
00232     /* Check if Multimode enabled */
00233     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00234     {
00235       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00236       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00237       if(tmp1 && tmp2)
00238       {
00239         /* Enable the selected ADC software conversion for injected group */
00240         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00241       }
00242     }
00243     else
00244     {
00245       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00246       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00247       if((hadc->Instance == ADC1) && tmp1 && tmp2)
00248       {
00249         /* Enable the selected ADC software conversion for injected group */
00250         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00251       }
00252     }
00253   }
00254
00255   /* Return function status */
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  Enables the interrupt and starts ADC conversion of injected channels.
00261   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00262   *         the configuration information for the specified ADC.
00263   *
00264   * @retval HAL status.
00265   */
00266 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
00267 {
00268   __IO uint32_t counter = 0U;
00269   uint32_t tmp1 = 0U, tmp2 = 0U;
00270
00271   /* Process locked */
00272   __HAL_LOCK(hadc);
00273
00274   /* Enable the ADC peripheral */
00275
00276   /* Check if ADC peripheral is disabled in order to enable it and wait during
00277      Tstab time the ADC's stabilization */
00278   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00279   {
00280     /* Enable the Peripheral */
00281     __HAL_ADC_ENABLE(hadc);
00282
00283     /* Delay for ADC stabilization time */
00284     /* Compute number of CPU cycles to wait for */
00285     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
00286     while(counter != 0U)
00287     {
00288       counter--;
00289     }
00290   }
00291
00292   /* Start conversion if ADC is effectively enabled */
00293   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00294   {
00295     /* Set ADC state                                                          */
00296     /* - Clear state bitfield related to injected group conversion results    */
00297     /* - Set state bitfield related to injected operation                     */
00298     ADC_STATE_CLR_SET(hadc->State,
00299                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00300                       HAL_ADC_STATE_INJ_BUSY);
00301
00302     /* Check if a regular conversion is ongoing */
00303     /* Note: On this device, there is no ADC error code fields related to     */
00304     /*       conversions on group injected only. In case of conversion on     */
00305     /*       going on group regular, no error code is reset.                  */
00306     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00307     {
00308       /* Reset ADC all error code fields */
00309       ADC_CLEAR_ERRORCODE(hadc);
00310     }
00311
00312     /* Process unlocked */
00313     /* Unlock before starting ADC conversions: in case of potential           */
00314     /* interruption, to let the process to ADC IRQ Handler.                   */
00315     __HAL_UNLOCK(hadc);
00316
00317     /* Clear injected group conversion flag */
00318     /* (To ensure of no unknown state from potential previous ADC operations) */
00319     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00320
00321     /* Enable end of conversion interrupt for injected channels */
00322     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00323
00324     /* Check if Multimode enabled */
00325     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
00326     {
00327       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00328       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00329       if(tmp1 && tmp2)
00330       {
00331         /* Enable the selected ADC software conversion for injected group */
00332         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00333       }
00334     }
00335     else
00336     {
00337       tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
00338       tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
00339       if((hadc->Instance == ADC1) && tmp1 && tmp2)
00340       {
00341         /* Enable the selected ADC software conversion for injected group */
00342         hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
00343       }
00344     }
00345   }
00346
00347   /* Return function status */
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
00353   *         no regular conversion is on going.
00354   * @note   If ADC must be disabled and if conversion is on going on
00355   *         regular group, function HAL_ADC_Stop must be used to stop both
00356   *         injected and regular groups, and disable the ADC.
00357   * @note   If injected group mode auto-injection is enabled,
00358   *         function HAL_ADC_Stop must be used.
00359   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
00360   * @param  hadc: ADC handle
00361   * @retval None
00362   */
00363 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
00364 {
00365   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00366
00367   /* Check the parameters */
00368   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00369
00370   /* Process locked */
00371   __HAL_LOCK(hadc);
00372
00373   /* Stop potential conversion and disable ADC peripheral                     */
00374   /* Conditioned to:                                                          */
00375   /* - No conversion on the other group (regular group) is intended to        */
00376   /*   continue (injected and regular groups stop conversion and ADC disable  */
00377   /*   are common)                                                            */
00378   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
00379   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
00380      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
00381   {
00382     /* Stop potential conversion on going, on regular and injected groups */
00383     /* Disable ADC peripheral */
00384     __HAL_ADC_DISABLE(hadc);
00385
00386     /* Check if ADC is effectively disabled */
00387     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00388     {
00389       /* Set ADC state */
00390       ADC_STATE_CLR_SET(hadc->State,
00391                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00392                         HAL_ADC_STATE_READY);
00393     }
00394   }
00395   else
00396   {
00397     /* Update ADC state machine to error */
00398     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00399
00400     tmp_hal_status = HAL_ERROR;
00401   }
00402
00403   /* Process unlocked */
00404   __HAL_UNLOCK(hadc);
00405
00406   /* Return function status */
00407   return tmp_hal_status;
00408 }
00409
00410 /**
00411   * @brief  Poll for injected conversion complete
00412   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00413   *         the configuration information for the specified ADC.
00414   * @param  Timeout: Timeout value in millisecond.
00415   * @retval HAL status
00416   */
00417 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00418 {
00419   uint32_t tickstart = 0U;
00420
00421   /* Get tick */
00422   tickstart = HAL_GetTick();
00423
00424   /* Check End of conversion flag */
00425   while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
00426   {
00427     /* Check for the Timeout */
00428     if(Timeout != HAL_MAX_DELAY)
00429     {
00430       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00431       {
00432         hadc->State= HAL_ADC_STATE_TIMEOUT;
00433         /* Process unlocked */
00434         __HAL_UNLOCK(hadc);
00435         return HAL_TIMEOUT;
00436       }
00437     }
00438   }
00439
00440   /* Clear injected group conversion flag */
00441   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
00442
00443   /* Update ADC state machine */
00444   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00445
00446   /* Determine whether any further conversion upcoming on group injected      */
00447   /* by external trigger, continuous mode or scan sequence on going.          */
00448   /* Note: On STM32F4, there is no independent flag of end of sequence.       */
00449   /*       The test of scan sequence on going is done either with scan        */
00450   /*       sequence disabled or with end of conversion flag set to            */
00451   /*       of end of sequence.                                                */
00452   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
00453      (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
00454       HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
00455      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
00456       (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
00457       (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
00458   {
00459     /* Set ADC state */
00460     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00461
00462     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00463     {
00464       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00465     }
00466   }
00467
00468   /* Return ADC state */
00469   return HAL_OK;
00470 }
00471
00472 /**
00473   * @brief  Stop conversion of injected channels, disable interruption of
00474   *         end-of-conversion. Disable ADC peripheral if no regular conversion
00475   *         is on going.
00476   * @note   If ADC must be disabled and if conversion is on going on
00477   *         regular group, function HAL_ADC_Stop must be used to stop both
00478   *         injected and regular groups, and disable the ADC.
00479   * @note   If injected group mode auto-injection is enabled,
00480   *         function HAL_ADC_Stop must be used.
00481   * @param  hadc: ADC handle
00482   * @retval None
00483   */
00484 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
00485 {
00486   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00487
00488   /* Check the parameters */
00489   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00490
00491   /* Process locked */
00492   __HAL_LOCK(hadc);
00493
00494   /* Stop potential conversion and disable ADC peripheral                     */
00495   /* Conditioned to:                                                          */
00496   /* - No conversion on the other group (regular group) is intended to        */
00497   /*   continue (injected and regular groups stop conversion and ADC disable  */
00498   /*   are common)                                                            */
00499   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
00500   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
00501      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
00502   {
00503     /* Stop potential conversion on going, on regular and injected groups */
00504     /* Disable ADC peripheral */
00505     __HAL_ADC_DISABLE(hadc);
00506
00507     /* Check if ADC is effectively disabled */
00508     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00509     {
00510       /* Disable ADC end of conversion interrupt for injected channels */
00511       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00512
00513       /* Set ADC state */
00514       ADC_STATE_CLR_SET(hadc->State,
00515                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00516                         HAL_ADC_STATE_READY);
00517     }
00518   }
00519   else
00520   {
00521     /* Update ADC state machine to error */
00522     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00523
00524     tmp_hal_status = HAL_ERROR;
00525   }
00526
00527   /* Process unlocked */
00528   __HAL_UNLOCK(hadc);
00529
00530   /* Return function status */
00531   return tmp_hal_status;
00532 }
00533
00534 /**
00535   * @brief  Gets the converted value from data register of injected channel.
00536   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00537   *         the configuration information for the specified ADC.
00538   * @param  InjectedRank: the ADC injected rank.
00539   *          This parameter can be one of the following values:
00540   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
00541   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
00542   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
00543   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
00544   * @retval None
00545   */
00546 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
00547 {
00548   __IO uint32_t tmp = 0U;
00549
00550   /* Check the parameters */
00551   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
00552
00553   /* Clear injected group conversion flag to have similar behaviour as        */
00554   /* regular group: reading data register also clears end of conversion flag. */
00555   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00556
00557   /* Return the selected ADC converted value */
00558   switch(InjectedRank)
00559   {
00560     case ADC_INJECTED_RANK_4:
00561     {
00562       tmp =  hadc->Instance->JDR4;
00563     }
00564     break;
00565     case ADC_INJECTED_RANK_3:
00566     {
00567       tmp =  hadc->Instance->JDR3;
00568     }
00569     break;
00570     case ADC_INJECTED_RANK_2:
00571     {
00572       tmp =  hadc->Instance->JDR2;
00573     }
00574     break;
00575     case ADC_INJECTED_RANK_1:
00576     {
00577       tmp =  hadc->Instance->JDR1;
00578     }
00579     break;
00580     default:
00581     break;
00582   }
00583   return tmp;
00584 }
00585
00586 /**
00587   * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
00588   *
00589   * @note   Caution: This function must be used only with the ADC master.
00590   *
00591   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00592   *         the configuration information for the specified ADC.
00593   * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
00594   * @param  Length:  The length of data to be transferred from ADC peripheral to memory.
00595   * @retval HAL status
00596   */
00597 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
00598 {
00599   __IO uint32_t counter = 0U;
00600
00601   /* Check the parameters */
00602   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00603   assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00604   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00605
00606   /* Process locked */
00607   __HAL_LOCK(hadc);
00608
00609   /* Check if ADC peripheral is disabled in order to enable it and wait during
00610      Tstab time the ADC's stabilization */
00611   if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
00612   {
00613     /* Enable the Peripheral */
00614     __HAL_ADC_ENABLE(hadc);
00615
00616     /* Delay for temperature sensor stabilization time */
00617     /* Compute number of CPU cycles to wait for */
00618     counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
00619     while(counter != 0U)
00620     {
00621       counter--;
00622     }
00623   }
00624
00625   /* Start conversion if ADC is effectively enabled */
00626   if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
00627   {
00628     /* Set ADC state                                                          */
00629     /* - Clear state bitfield related to regular group conversion results     */
00630     /* - Set state bitfield related to regular group operation                */
00631     ADC_STATE_CLR_SET(hadc->State,
00632                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
00633                       HAL_ADC_STATE_REG_BUSY);
00634
00635     /* If conversions on group regular are also triggering group injected,    */
00636     /* update ADC state.                                                      */
00637     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00638     {
00639       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00640     }
00641
00642     /* State machine update: Check if an injected conversion is ongoing */
00643     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00644     {
00645       /* Reset ADC error code fields related to conversions on group regular */
00646       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
00647     }
00648     else
00649     {
00650       /* Reset ADC all error code fields */
00651       ADC_CLEAR_ERRORCODE(hadc);
00652     }
00653
00654     /* Process unlocked */
00655     /* Unlock before starting ADC conversions: in case of potential           */
00656     /* interruption, to let the process to ADC IRQ Handler.                   */
00657     __HAL_UNLOCK(hadc);
00658
00659     /* Set the DMA transfer complete callback */
00660     hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
00661
00662     /* Set the DMA half transfer complete callback */
00663     hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
00664
00665     /* Set the DMA error callback */
00666     hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
00667
00668     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
00669     /* start (in case of SW start):                                           */
00670
00671     /* Clear regular group conversion flag and overrun flag */
00672     /* (To ensure of no unknown state from potential previous ADC operations) */
00673     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00674
00675     /* Enable ADC overrun interrupt */
00676     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
00677
00678     if (hadc->Init.DMAContinuousRequests != DISABLE)
00679     {
00680       /* Enable the selected ADC DMA request after last transfer */
00681       ADC->CCR |= ADC_CCR_DDS;
00682     }
00683     else
00684     {
00685       /* Disable the selected ADC EOC rising on each regular channel conversion */
00686       ADC->CCR &= ~ADC_CCR_DDS;
00687     }
00688
00689     /* Enable the DMA Stream */
00690     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
00691
00692     /* if no external trigger present enable software conversion of regular channels */
00693     if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
00694     {
00695       /* Enable the selected ADC software conversion for regular group */
00696       hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
00697     }
00698   }
00699
00700   /* Return function status */
00701   return HAL_OK;
00702 }
00703
00704 /**
00705   * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
00706   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00707   *         the configuration information for the specified ADC.
00708   * @retval HAL status
00709   */
00710 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
00711 {
00712   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00713
00714   /* Check the parameters */
00715   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00716
00717   /* Process locked */
00718   __HAL_LOCK(hadc);
00719
00720   /* Stop potential conversion on going, on regular and injected groups */
00721   /* Disable ADC peripheral */
00722   __HAL_ADC_DISABLE(hadc);
00723
00724   /* Check if ADC is effectively disabled */
00725   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
00726   {
00727     /* Disable the selected ADC DMA mode for multimode */
00728     ADC->CCR &= ~ADC_CCR_DDS;
00729
00730     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
00731     /* DMA transfer is on going)                                              */
00732     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
00733
00734     /* Disable ADC overrun interrupt */
00735     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
00736
00737     /* Set ADC state */
00738     ADC_STATE_CLR_SET(hadc->State,
00739                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00740                       HAL_ADC_STATE_READY);
00741   }
00742
00743   /* Process unlocked */
00744   __HAL_UNLOCK(hadc);
00745
00746   /* Return function status */
00747   return tmp_hal_status;
00748 }
00749
00750 /**
00751   * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results
00752   *         data in the selected multi mode.
00753   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00754   *         the configuration information for the specified ADC.
00755   * @retval The converted data value.
00756   */
00757 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
00758 {
00759   /* Return the multi mode conversion value */
00760   return ADC->CDR;
00761 }
00762
00763 /**
00764   * @brief  Injected conversion complete callback in non blocking mode
00765   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00766   *         the configuration information for the specified ADC.
00767   * @retval None
00768   */
00769 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
00770 {
00771   /* Prevent unused argument(s) compilation warning */
00772   UNUSED(hadc);
00773   /* NOTE : This function Should not be modified, when the callback is needed,
00774             the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
00775    */
00776 }
00777
00778 /**
00779   * @brief  Configures for the selected ADC injected channel its corresponding
00780   *         rank in the sequencer and its sample time.
00781   * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
00782   *         the configuration information for the specified ADC.
00783   * @param  sConfigInjected: ADC configuration structure for injected channel.
00784   * @retval None
00785   */
00786 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
00787 {
00788
00789 #ifdef USE_FULL_ASSERT
00790   uint32_t tmp = 0U;
00791 #endif /* USE_FULL_ASSERT  */
00792
00793   /* Check the parameters */
00794   assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
00795   assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
00796   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
00797   assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
00798   assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
00799   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
00800   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
00801
00802 #ifdef USE_FULL_ASSERT
00803   tmp = ADC_GET_RESOLUTION(hadc);
00804   assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
00805 #endif /* USE_FULL_ASSERT  */
00806
00807   if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
00808   {
00809     assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
00810   }
00811
00812   /* Process locked */
00813   __HAL_LOCK(hadc);
00814
00815   /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
00816   if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
00817   {
00818     /* Clear the old sample time */
00819     hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
00820
00821     /* Set the new sample time */
00822     hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
00823   }
00824   else /* ADC_Channel include in ADC_Channel_[0..9] */
00825   {
00826     /* Clear the old sample time */
00827     hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
00828
00829     /* Set the new sample time */
00830     hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
00831   }
00832
00833   /*---------------------------- ADCx JSQR Configuration -----------------*/
00834   hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
00835   hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
00836
00837   /* Rank configuration */
00838
00839   /* Clear the old SQx bits for the selected rank */
00840   hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
00841
00842   /* Set the SQx bits for the selected rank */
00843   hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
00844
00845   /* Enable external trigger if trigger selection is different of software  */
00846   /* start.                                                                 */
00847   /* Note: This configuration keeps the hardware feature of parameter       */
00848   /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
00849   /*       software start.                                                  */
00850   if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
00851   {
00852     /* Select external trigger to start conversion */
00853     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
00854     hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
00855
00856     /* Select external trigger polarity */
00857     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
00858     hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
00859   }
00860   else
00861   {
00862     /* Reset the external trigger */
00863     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
00864     hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
00865   }
00866
00867   if (sConfigInjected->AutoInjectedConv != DISABLE)
00868   {
00869     /* Enable the selected ADC automatic injected group conversion */
00870     hadc->Instance->CR1 |= ADC_CR1_JAUTO;
00871   }
00872   else
00873   {
00874     /* Disable the selected ADC automatic injected group conversion */
00875     hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
00876   }
00877
00878   if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
00879   {
00880     /* Enable the selected ADC injected discontinuous mode */
00881     hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
00882   }
00883   else
00884   {
00885     /* Disable the selected ADC injected discontinuous mode */
00886     hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
00887   }
00888
00889   switch(sConfigInjected->InjectedRank)
00890   {
00891     case 1U:
00892       /* Set injected channel 1 offset */
00893       hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
00894       hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
00895       break;
00896     case 2U:
00897       /* Set injected channel 2 offset */
00898       hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
00899       hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
00900       break;
00901     case 3U:
00902       /* Set injected channel 3 offset */
00903       hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
00904       hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
00905       break;
00906     default:
00907       /* Set injected channel 4 offset */
00908       hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
00909       hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
00910       break;
00911   }
00912
00913   /* if ADC1 Channel_18 is selected enable VBAT Channel */
00914   if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
00915   {
00916     /* Enable the VBAT channel*/
00917     ADC->CCR |= ADC_CCR_VBATE;
00918   }
00919
00920   /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
00921   if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
00922   {
00923     /* Enable the TSVREFE channel*/
00924     ADC->CCR |= ADC_CCR_TSVREFE;
00925   }
00926
00927   /* Process unlocked */
00928   __HAL_UNLOCK(hadc);
00929
00930   /* Return function status */
00931   return HAL_OK;
00932 }
00933
00934 /**
00935   * @brief  Configures the ADC multi-mode
00936   * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains
00937   *                     the configuration information for the specified ADC.
00938   * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains
00939   *                     the configuration information for  multimode.
00940   * @retval HAL status
00941   */
00942 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
00943 {
00944   /* Check the parameters */
00945   assert_param(IS_ADC_MODE(multimode->Mode));
00946   assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
00947   assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
00948
00949   /* Process locked */
00950   __HAL_LOCK(hadc);
00951
00952   /* Set ADC mode */
00953   ADC->CCR &= ~(ADC_CCR_MULTI);
00954   ADC->CCR |= multimode->Mode;
00955
00956   /* Set the ADC DMA access mode */
00957   ADC->CCR &= ~(ADC_CCR_DMA);
00958   ADC->CCR |= multimode->DMAAccessMode;
00959
00960   /* Set delay between two sampling phases */
00961   ADC->CCR &= ~(ADC_CCR_DELAY);
00962   ADC->CCR |= multimode->TwoSamplingDelay;
00963
00964   /* Process unlocked */
00965   __HAL_UNLOCK(hadc);
00966
00967   /* Return function status */
00968   return HAL_OK;
00969 }
00970
00971 /**
00972   * @}
00973   */
00974
00975 /**
00976   * @brief  DMA transfer complete callback.
00977   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00978   *                the configuration information for the specified DMA module.
00979   * @retval None
00980   */
00981 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
00982 {
00983   /* Retrieve ADC handle corresponding to current DMA handle */
00984   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00985
00986   /* Update state machine on conversion status if not in error state */
00987   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
00988   {
00989     /* Update ADC state machine */
00990     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
00991
00992     /* Determine whether any further conversion upcoming on group regular   */
00993     /* by external trigger, continuous mode or scan sequence on going.      */
00994     /* Note: On STM32F4, there is no independent flag of end of sequence.   */
00995     /*       The test of scan sequence on going is done either with scan    */
00996     /*       sequence disabled or with end of conversion flag set to        */
00997     /*       of end of sequence.                                            */
00998     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
00999        (hadc->Init.ContinuousConvMode == DISABLE)            &&
01000        (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
01001         HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
01002     {
01003       /* Disable ADC end of single conversion interrupt on group regular */
01004       /* Note: Overrun interrupt was enabled with EOC interrupt in          */
01005       /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
01006       /* by overrun IRQ process below.                                      */
01007       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
01008
01009       /* Set ADC state */
01010       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01011
01012       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01013       {
01014         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01015       }
01016     }
01017
01018     /* Conversion complete callback */
01019     HAL_ADC_ConvCpltCallback(hadc);
01020   }
01021   else
01022   {
01023     /* Call DMA error callback */
01024     hadc->DMA_Handle->XferErrorCallback(hdma);
01025   }
01026 }
01027
01028 /**
01029   * @brief  DMA half transfer complete callback.
01030   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01031   *                the configuration information for the specified DMA module.
01032   * @retval None
01033   */
01034 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
01035 {
01036     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01037     /* Conversion complete callback */
01038     HAL_ADC_ConvHalfCpltCallback(hadc);
01039 }
01040
01041 /**
01042   * @brief  DMA error callback
01043   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01044   *                the configuration information for the specified DMA module.
01045   * @retval None
01046   */
01047 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
01048 {
01049     ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01050     hadc->State= HAL_ADC_STATE_ERROR_DMA;
01051     /* Set ADC error code to DMA error */
01052     hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
01053     HAL_ADC_ErrorCallback(hadc);
01054 }
01055
01056 /**
01057   * @}
01058   */
01059
01060 #endif /* HAL_ADC_MODULE_ENABLED */
01061 /**
01062   * @}
01063   */
01064
01065 /**
01066   * @}
01067   */
01068
01069 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:50 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_adc_ex.h Source File

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stm32f4xx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of ADC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_ADC_EX_H
00040 #define __STM32F4xx_ADC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADCEx_Exported_Types ADC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  ADC Configuration injected Channel structure definition
00064   * @note   Parameters of this structure are shared within 2 scopes:
00065   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
00066   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00067   *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
00068   * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00069   *         ADC state can be either:
00070   *          - For all parameters: ADC disabled
00071   *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
00072   *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
00073   */
00074 typedef struct
00075 {
00076   uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
00077                                                This parameter can be a value of @ref ADC_channels
00078                                                Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
00079   uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
00080                                                This parameter must be a value of @ref ADCEx_injected_rank
00081                                                Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00082   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00083                                                Unit: ADC clock cycles
00084                                                Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
00085                                                This parameter can be a value of @ref ADC_sampling_times
00086                                                Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00087                                                         If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00088                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00089                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00090                                                      Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
00091   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
00092                                                Offset value must be a positive number.
00093                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits),
00094                                                this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
00095   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
00096                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00097                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00098                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00099                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00100   uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00101                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00102                                                Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00103                                                This parameter can be set to ENABLE or DISABLE.
00104                                                Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
00105                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00106                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00107   uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
00108                                                This parameter can be set to ENABLE or DISABLE.
00109                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00110                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
00111                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00112                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00113                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00114                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00115   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00116                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
00117                                                If set to external trigger source, triggering is on event rising edge.
00118                                                This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
00119                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00120                                                      If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
00121                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00122                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00123   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00124                                                This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
00125                                                If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
00126                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00127                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00128 }ADC_InjectionConfTypeDef;
00129
00130 /**
00131   * @brief ADC Configuration multi-mode structure definition
00132   */
00133 typedef struct
00134 {
00135   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode.
00136                                    This parameter can be a value of @ref ADCEx_Common_mode */
00137   uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.
00138                                    This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
00139   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
00140                                    This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
00141 }ADC_MultiModeTypeDef;
00142
00143 /**
00144   * @}
00145   */
00146
00147 /* Exported constants --------------------------------------------------------*/
00148 /** @defgroup ADCEx_Exported_Constants ADC Exported Constants
00149   * @{
00150   */
00151
00152 /** @defgroup ADCEx_Common_mode ADC Common Mode
00153   * @{
00154   */
00155 #define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000U)
00156 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
00157 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
00158 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
00159 #define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
00160 #define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
00161 #define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
00162 #define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
00163 #define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
00164 #define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
00165 #define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
00166 #define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
00167 #define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
00173   * @{
00174   */
00175 #define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000U)     /*!< DMA mode disabled */
00176 #define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
00177 #define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
00178 #define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
00184   * @{
00185   */
00186 #define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000U)
00187 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
00188 #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
00189 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
00195   * @{
00196   */
00197 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4           ((uint32_t)0x00000000U)
00198 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO          ((uint32_t)ADC_CR2_JEXTSEL_0)
00199 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1           ((uint32_t)ADC_CR2_JEXTSEL_1)
00200 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00201 #define ADC_EXTERNALTRIGINJECCONV_T3_CC2           ((uint32_t)ADC_CR2_JEXTSEL_2)
00202 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
00203 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
00204 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00205 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3           ((uint32_t)ADC_CR2_JEXTSEL_3)
00206 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
00207 #define ADC_EXTERNALTRIGINJECCONV_T5_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
00208 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00209 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
00210 #define ADC_EXTERNALTRIGINJECCONV_T8_CC3           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
00211 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
00212 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15         ((uint32_t)ADC_CR2_JEXTSEL)
00213 #define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1U)
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup ADCEx_injected_rank ADC Injected Rank
00219   * @{
00220   */
00221 #define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001U)
00222 #define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002U)
00223 #define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003U)
00224 #define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004U)
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup ADCEx_channels  ADC Specific Channels
00230   * @{
00231   */
00232 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00233     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
00234     defined(STM32F410Rx)
00235 #define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_16)
00236 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
00237
00238 #if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00239     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00240 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
00241 #define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
00242 #endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00243 /**
00244   * @}
00245   */
00246
00247
00248 /**
00249   * @}
00250   */
00251
00252 /* Exported macro ------------------------------------------------------------*/
00253 /** @defgroup ADC_Exported_Macros ADC Exported Macros
00254   * @{
00255   */
00256
00257 /**
00258   * @}
00259   */
00260
00261 /* Exported functions --------------------------------------------------------*/
00262 /** @addtogroup ADCEx_Exported_Functions
00263   * @{
00264   */
00265
00266 /** @addtogroup ADCEx_Exported_Functions_Group1
00267   * @{
00268   */
00269
00270 /* I/O operation functions ******************************************************/
00271 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
00272 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
00273 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00274 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
00275 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
00276 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
00277 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00278 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
00279 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
00280 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
00281
00282 /* Peripheral Control functions *************************************************/
00283 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
00284 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
00285
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293 /* Private types -------------------------------------------------------------*/
00294 /* Private variables ---------------------------------------------------------*/
00295 /* Private constants ---------------------------------------------------------*/
00296 /** @defgroup ADCEx_Private_Constants ADC Private Constants
00297   * @{
00298   */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /* Private macros ------------------------------------------------------------*/
00305 /** @defgroup ADCEx_Private_Macros ADC Private Macros
00306   * @{
00307   */
00308 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00309     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
00310     defined(STM32F410Rx) || defined(STM32F411xE)
00311 #define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
00312 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
00313
00314 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00315     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00316 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)  || \
00317                                  ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
00318 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00319
00320 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)                 || \
00321                            ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
00322                            ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
00323                            ((MODE) == ADC_DUALMODE_INJECSIMULT)             || \
00324                            ((MODE) == ADC_DUALMODE_REGSIMULT)               || \
00325                            ((MODE) == ADC_DUALMODE_INTERL)                  || \
00326                            ((MODE) == ADC_DUALMODE_ALTERTRIG)               || \
00327                            ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
00328                            ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
00329                            ((MODE) == ADC_TRIPLEMODE_INJECSIMULT)           || \
00330                            ((MODE) == ADC_TRIPLEMODE_REGSIMULT)             || \
00331                            ((MODE) == ADC_TRIPLEMODE_INTERL)                || \
00332                            ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
00333 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
00334                                       ((MODE) == ADC_DMAACCESSMODE_1)        || \
00335                                       ((MODE) == ADC_DMAACCESSMODE_2)        || \
00336                                       ((MODE) == ADC_DMAACCESSMODE_3))
00337 #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
00338                                           ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
00339                                           ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
00340                                           ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
00341 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)  || \
00342                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
00343                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)  || \
00344                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
00345                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2)  || \
00346                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)  || \
00347                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)  || \
00348                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)  || \
00349                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)  || \
00350                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
00351                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)  || \
00352                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
00353                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)  || \
00354                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3)  || \
00355                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)  || \
00356                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
00357                                         ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
00358 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
00359 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
00360
00361 /**
00362   * @brief  Set the selected injected Channel rank.
00363   * @param  _CHANNELNB_: Channel number.
00364   * @param  _RANKNB_: Rank number.
00365   * @param  _JSQR_JL_: Sequence length.
00366   * @retval None
00367   */
00368 #define   ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_)  (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
00369
00370 /**
00371   * @}
00372   */
00373
00374 /* Private functions ---------------------------------------------------------*/
00375 /** @defgroup ADCEx_Private_Functions ADC Private Functions
00376   * @{
00377   */
00378
00379 /**
00380   * @}
00381   */
00382
00383 /**
00384   * @}
00385   */
00386
00387 /**
00388   * @}
00389   */
00390
00391 #ifdef __cplusplus
00392 }
00393 #endif
00394
00395 #endif /*__STM32F4xx_ADC_EX_H */
00396
00397
00398 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:50 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_can.c Source File

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stm32f4xx_hal_can.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_can.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Controller Area Network (CAN) peripheral:
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State and Error functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       (#) Enable the CAN controller interface clock using
00020           __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
00021       -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
00022
00023       (#) CAN pins configuration
00024         (++) Enable the clock for the CAN GPIOs using the following function:
00025              __GPIOx_CLK_ENABLE()
00026         (++) Connect and configure the involved CAN pins to AF9 using the
00027               following function HAL_GPIO_Init()
00028
00029       (#) Initialize and configure the CAN using CAN_Init() function.
00030
00031       (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
00032
00033       (#) Receive a CAN frame using HAL_CAN_Receive() function.
00034
00035      *** Polling mode IO operation ***
00036      =================================
00037      [..]
00038        (+) Start the CAN peripheral transmission and wait the end of this operation
00039            using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
00040            according to his end application
00041        (+) Start the CAN peripheral reception and wait the end of this operation
00042            using HAL_CAN_Receive(), at this stage user can specify the value of timeout
00043            according to his end application
00044
00045      *** Interrupt mode IO operation ***
00046      ===================================
00047      [..]
00048        (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
00049        (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
00050        (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
00051        (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
00052             add his own code by customization of function pointer HAL_CAN_TxCpltCallback
00053        (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
00054             add his own code by customization of function pointer HAL_CAN_ErrorCallback
00055
00056      *** CAN HAL driver macros list ***
00057      =============================================
00058      [..]
00059        Below the list of most used macros in CAN HAL driver.
00060
00061       (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
00062       (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
00063       (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
00064       (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
00065       (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
00066
00067      [..]
00068       (@) You can refer to the CAN HAL driver header file for more useful macros
00069
00070   @endverbatim
00071
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32f4xx_hal.h"
00104
00105 /** @addtogroup STM32F4xx_HAL_Driver
00106   * @{
00107   */
00108
00109 /** @defgroup CAN CAN
00110   * @brief CAN driver modules
00111   * @{
00112   */
00113
00114 #ifdef HAL_CAN_MODULE_ENABLED
00115
00116 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00117     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00118     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00119
00120 /* Private typedef -----------------------------------------------------------*/
00121 /* Private define ------------------------------------------------------------*/
00122 /** @addtogroup CAN_Private_Constants
00123   * @{
00124   */
00125 #define CAN_TIMEOUT_VALUE  10U
00126 /**
00127   * @}
00128   */
00129 /* Private macro -------------------------------------------------------------*/
00130 /* Private variables ---------------------------------------------------------*/
00131 /* Private function prototypes -----------------------------------------------*/
00132 /** @addtogroup CAN_Private_Functions
00133   * @{
00134   */
00135 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
00136 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
00137 /**
00138   * @}
00139   */
00140
00141 /* Exported functions --------------------------------------------------------*/
00142 /** @defgroup CAN_Exported_Functions CAN Exported Functions
00143   * @{
00144   */
00145
00146 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
00147  *  @brief    Initialization and Configuration functions
00148  *
00149 @verbatim
00150   ==============================================================================
00151               ##### Initialization and de-initialization functions #####
00152   ==============================================================================
00153     [..]  This section provides functions allowing to:
00154       (+) Initialize and configure the CAN.
00155       (+) De-initialize the CAN.
00156
00157 @endverbatim
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Initializes the CAN peripheral according to the specified
00163   *         parameters in the CAN_InitStruct.
00164   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00165   *         the configuration information for the specified CAN.
00166   * @retval HAL status
00167   */
00168 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
00169 {
00170   uint32_t InitStatus = 3U;
00171   uint32_t tickstart = 0U;
00172
00173   /* Check CAN handle */
00174   if(hcan == NULL)
00175   {
00176      return HAL_ERROR;
00177   }
00178
00179   /* Check the parameters */
00180   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00181   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
00182   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
00183   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
00184   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
00185   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
00186   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
00187   assert_param(IS_CAN_MODE(hcan->Init.Mode));
00188   assert_param(IS_CAN_SJW(hcan->Init.SJW));
00189   assert_param(IS_CAN_BS1(hcan->Init.BS1));
00190   assert_param(IS_CAN_BS2(hcan->Init.BS2));
00191   assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
00192
00193
00194   if(hcan->State == HAL_CAN_STATE_RESET)
00195   {
00196     /* Allocate lock resource and initialize it */
00197     hcan->Lock = HAL_UNLOCKED;
00198     /* Init the low level hardware */
00199     HAL_CAN_MspInit(hcan);
00200   }
00201
00202   /* Initialize the CAN state*/
00203   hcan->State = HAL_CAN_STATE_BUSY;
00204
00205   /* Exit from sleep mode */
00206   hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
00207
00208   /* Request initialisation */
00209   hcan->Instance->MCR |= CAN_MCR_INRQ ;
00210
00211   /* Get tick */
00212   tickstart = HAL_GetTick();
00213
00214   /* Wait the acknowledge */
00215   while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00216   {
00217     if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
00218     {
00219       hcan->State= HAL_CAN_STATE_TIMEOUT;
00220       /* Process unlocked */
00221       __HAL_UNLOCK(hcan);
00222       return HAL_TIMEOUT;
00223     }
00224   }
00225
00226   /* Check acknowledge */
00227   if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00228   {
00229     InitStatus = CAN_INITSTATUS_FAILED;
00230   }
00231   else
00232   {
00233     /* Set the time triggered communication mode */
00234     if (hcan->Init.TTCM == ENABLE)
00235     {
00236       hcan->Instance->MCR |= CAN_MCR_TTCM;
00237     }
00238     else
00239     {
00240       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
00241     }
00242
00243     /* Set the automatic bus-off management */
00244     if (hcan->Init.ABOM == ENABLE)
00245     {
00246       hcan->Instance->MCR |= CAN_MCR_ABOM;
00247     }
00248     else
00249     {
00250       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
00251     }
00252
00253     /* Set the automatic wake-up mode */
00254     if (hcan->Init.AWUM == ENABLE)
00255     {
00256       hcan->Instance->MCR |= CAN_MCR_AWUM;
00257     }
00258     else
00259     {
00260       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
00261     }
00262
00263     /* Set the no automatic retransmission */
00264     if (hcan->Init.NART == ENABLE)
00265     {
00266       hcan->Instance->MCR |= CAN_MCR_NART;
00267     }
00268     else
00269     {
00270       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
00271     }
00272
00273     /* Set the receive FIFO locked mode */
00274     if (hcan->Init.RFLM == ENABLE)
00275     {
00276       hcan->Instance->MCR |= CAN_MCR_RFLM;
00277     }
00278     else
00279     {
00280       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
00281     }
00282
00283     /* Set the transmit FIFO priority */
00284     if (hcan->Init.TXFP == ENABLE)
00285     {
00286       hcan->Instance->MCR |= CAN_MCR_TXFP;
00287     }
00288     else
00289     {
00290       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
00291     }
00292
00293     /* Set the bit timing register */
00294     hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
00295                 ((uint32_t)hcan->Init.SJW) | \
00296                 ((uint32_t)hcan->Init.BS1) | \
00297                 ((uint32_t)hcan->Init.BS2) | \
00298                ((uint32_t)hcan->Init.Prescaler - 1U);
00299
00300     /* Request leave initialisation */
00301     hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
00302
00303   /* Get tick */
00304   tickstart = HAL_GetTick();
00305
00306    /* Wait the acknowledge */
00307    while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00308    {
00309     if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
00310      {
00311        hcan->State= HAL_CAN_STATE_TIMEOUT;
00312        /* Process unlocked */
00313        __HAL_UNLOCK(hcan);
00314        return HAL_TIMEOUT;
00315      }
00316    }
00317
00318     /* Check acknowledged */
00319     if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00320     {
00321       InitStatus = CAN_INITSTATUS_FAILED;
00322     }
00323     else
00324     {
00325       InitStatus = CAN_INITSTATUS_SUCCESS;
00326     }
00327   }
00328
00329   if(InitStatus == CAN_INITSTATUS_SUCCESS)
00330   {
00331     /* Set CAN error code to none */
00332     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00333
00334     /* Initialize the CAN state */
00335     hcan->State = HAL_CAN_STATE_READY;
00336
00337     /* Return function status */
00338     return HAL_OK;
00339   }
00340   else
00341   {
00342     /* Initialize the CAN state */
00343     hcan->State = HAL_CAN_STATE_ERROR;
00344
00345     /* Return function status */
00346     return HAL_ERROR;
00347   }
00348 }
00349
00350 /**
00351   * @brief  Configures the CAN reception filter according to the specified
00352   *         parameters in the CAN_FilterInitStruct.
00353   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00354   *         the configuration information for the specified CAN.
00355   * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
00356   *         contains the filter configuration information.
00357   * @retval None
00358   */
00359 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
00360 {
00361   uint32_t filternbrbitpos = 0U;
00362
00363   /* Check the parameters */
00364   assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
00365   assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
00366   assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
00367   assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
00368   assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
00369   assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
00370
00371   filternbrbitpos = ((uint32_t)1U) << sFilterConfig->FilterNumber;
00372
00373   /* Initialisation mode for the filter */
00374   CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
00375
00376   /* Select the start slave bank */
00377   CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
00378   CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
00379
00380   /* Filter Deactivation */
00381   CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
00382
00383   /* Filter Scale */
00384   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
00385   {
00386     /* 16-bit scale for the filter */
00387     CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
00388
00389     /* First 16-bit identifier and First 16-bit mask */
00390     /* Or First 16-bit identifier and Second 16-bit identifier */
00391     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00392        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
00393         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00394
00395     /* Second 16-bit identifier and Second 16-bit mask */
00396     /* Or Third 16-bit identifier and Fourth 16-bit identifier */
00397     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00398        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00399         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
00400   }
00401
00402   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
00403   {
00404     /* 32-bit scale for the filter */
00405     CAN1->FS1R |= filternbrbitpos;
00406     /* 32-bit identifier or First 32-bit identifier */
00407     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00408        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
00409         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00410     /* 32-bit mask or Second 32-bit identifier */
00411     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00412        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00413         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
00414   }
00415
00416   /* Filter Mode */
00417   if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
00418   {
00419     /*Id/Mask mode for the filter*/
00420     CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
00421   }
00422   else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
00423   {
00424     /*Identifier list mode for the filter*/
00425     CAN1->FM1R |= (uint32_t)filternbrbitpos;
00426   }
00427
00428   /* Filter FIFO assignment */
00429   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
00430   {
00431     /* FIFO 0 assignation for the filter */
00432     CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
00433   }
00434
00435   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
00436   {
00437     /* FIFO 1 assignation for the filter */
00438     CAN1->FFA1R |= (uint32_t)filternbrbitpos;
00439   }
00440
00441   /* Filter activation */
00442   if (sFilterConfig->FilterActivation == ENABLE)
00443   {
00444     CAN1->FA1R |= filternbrbitpos;
00445   }
00446
00447   /* Leave the initialisation mode for the filter */
00448   CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
00449
00450   /* Return function status */
00451   return HAL_OK;
00452 }
00453
00454 /**
00455   * @brief  Deinitializes the CANx peripheral registers to their default reset values.
00456   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00457   *         the configuration information for the specified CAN.
00458   * @retval HAL status
00459   */
00460 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
00461 {
00462   /* Check CAN handle */
00463   if(hcan == NULL)
00464   {
00465      return HAL_ERROR;
00466   }
00467
00468   /* Check the parameters */
00469   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00470
00471   /* Change CAN state */
00472   hcan->State = HAL_CAN_STATE_BUSY;
00473
00474   /* DeInit the low level hardware */
00475   HAL_CAN_MspDeInit(hcan);
00476
00477   /* Change CAN state */
00478   hcan->State = HAL_CAN_STATE_RESET;
00479
00480   /* Release Lock */
00481   __HAL_UNLOCK(hcan);
00482
00483   /* Return function status */
00484   return HAL_OK;
00485 }
00486
00487 /**
00488   * @brief  Initializes the CAN MSP.
00489   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00490   *         the configuration information for the specified CAN.
00491   * @retval None
00492   */
00493 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
00494 {
00495   /* Prevent unused argument(s) compilation warning */
00496   UNUSED(hcan);
00497   /* NOTE : This function Should not be modified, when the callback is needed,
00498             the HAL_CAN_MspInit could be implemented in the user file
00499    */
00500 }
00501
00502 /**
00503   * @brief  DeInitializes the CAN MSP.
00504   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00505   *         the configuration information for the specified CAN.
00506   * @retval None
00507   */
00508 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
00509 {
00510   /* Prevent unused argument(s) compilation warning */
00511   UNUSED(hcan);
00512   /* NOTE : This function Should not be modified, when the callback is needed,
00513             the HAL_CAN_MspDeInit could be implemented in the user file
00514    */
00515 }
00516
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup CAN_Exported_Functions_Group2 IO operation functions
00522  *  @brief    IO operation functions
00523  *
00524 @verbatim
00525   ==============================================================================
00526                       ##### IO operation functions #####
00527   ==============================================================================
00528     [..]  This section provides functions allowing to:
00529       (+) Transmit a CAN frame message.
00530       (+) Receive a CAN frame message.
00531       (+) Enter CAN peripheral in sleep mode.
00532       (+) Wake up the CAN peripheral from sleep mode.
00533
00534 @endverbatim
00535   * @{
00536   */
00537
00538 /**
00539   * @brief  Initiates and transmits a CAN frame message.
00540   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00541   *         the configuration information for the specified CAN.
00542   * @param  Timeout: Specify Timeout value
00543   * @retval HAL status
00544   */
00545 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
00546 {
00547   uint32_t  transmitmailbox = 5U;
00548   uint32_t tickstart = 0U;
00549
00550   /* Check the parameters */
00551   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00552   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00553   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00554
00555   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
00556      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
00557      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
00558   {
00559     /* Process locked */
00560     __HAL_LOCK(hcan);
00561
00562     if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00563     {
00564       /* Change CAN state */
00565       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00566     }
00567     else
00568     {
00569       /* Change CAN state */
00570       hcan->State = HAL_CAN_STATE_BUSY_TX;
00571     }
00572
00573     /* Select one empty transmit mailbox */
00574     if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
00575     {
00576       transmitmailbox = 0U;
00577     }
00578     else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
00579     {
00580       transmitmailbox = 1U;
00581     }
00582     else
00583     {
00584       transmitmailbox = 2U;
00585     }
00586
00587     /* Set up the Id */
00588     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00589     if (hcan->pTxMsg->IDE == CAN_ID_STD)
00590     {
00591       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00592       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
00593                                                   hcan->pTxMsg->RTR);
00594     }
00595     else
00596     {
00597       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00598       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
00599                                                   hcan->pTxMsg->IDE | \
00600                                                   hcan->pTxMsg->RTR);
00601     }
00602
00603     /* Set up the DLC */
00604     hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
00605     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
00606     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00607
00608     /* Set up the data field */
00609     hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
00610                                              ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
00611                                              ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
00612                                              ((uint32_t)hcan->pTxMsg->Data[0U]));
00613     hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
00614                                              ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
00615                                              ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
00616                                              ((uint32_t)hcan->pTxMsg->Data[4U]));
00617     /* Request transmission */
00618     hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00619
00620     /* Get tick */
00621     tickstart = HAL_GetTick();
00622
00623     /* Check End of transmission flag */
00624     while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
00625     {
00626       /* Check for the Timeout */
00627       if(Timeout != HAL_MAX_DELAY)
00628       {
00629        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00630        {
00631          hcan->State = HAL_CAN_STATE_TIMEOUT;
00632          /* Process unlocked */
00633          __HAL_UNLOCK(hcan);
00634          return HAL_TIMEOUT;
00635         }
00636       }
00637     }
00638     if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00639     {
00640       /* Change CAN state */
00641       hcan->State = HAL_CAN_STATE_BUSY_RX;
00642     }
00643     else
00644     {
00645       /* Change CAN state */
00646       hcan->State = HAL_CAN_STATE_READY;
00647     }
00648
00649     /* Process unlocked */
00650     __HAL_UNLOCK(hcan);
00651
00652     /* Return function status */
00653     return HAL_OK;
00654   }
00655   else
00656   {
00657     /* Change CAN state */
00658     hcan->State = HAL_CAN_STATE_ERROR;
00659
00660     /* Return function status */
00661     return HAL_ERROR;
00662   }
00663 }
00664
00665 /**
00666   * @brief  Initiates and transmits a CAN frame message.
00667   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00668   *         the configuration information for the specified CAN.
00669   * @retval HAL status
00670   */
00671 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
00672 {
00673   uint32_t  transmitmailbox = 5U;
00674
00675   /* Check the parameters */
00676   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00677   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00678   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00679
00680   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
00681      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
00682      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
00683   {
00684     /* Process Locked */
00685     __HAL_LOCK(hcan);
00686
00687     /* Select one empty transmit mailbox */
00688     if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
00689     {
00690       transmitmailbox = 0U;
00691     }
00692     else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
00693     {
00694       transmitmailbox = 1U;
00695     }
00696     else
00697     {
00698       transmitmailbox = 2U;
00699     }
00700
00701     /* Set up the Id */
00702     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00703     if(hcan->pTxMsg->IDE == CAN_ID_STD)
00704     {
00705       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00706       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
00707                                                 hcan->pTxMsg->RTR);
00708     }
00709     else
00710     {
00711       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00712       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
00713                                                 hcan->pTxMsg->IDE | \
00714                                                 hcan->pTxMsg->RTR);
00715     }
00716
00717     /* Set up the DLC */
00718     hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
00719     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
00720     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00721
00722     /* Set up the data field */
00723     hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
00724                                            ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
00725                                            ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
00726                                            ((uint32_t)hcan->pTxMsg->Data[0U]));
00727     hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
00728                                            ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
00729                                            ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
00730                                            ((uint32_t)hcan->pTxMsg->Data[4U]));
00731
00732     if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00733     {
00734       /* Change CAN state */
00735       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00736     }
00737     else
00738     {
00739       /* Change CAN state */
00740       hcan->State = HAL_CAN_STATE_BUSY_TX;
00741     }
00742
00743     /* Set CAN error code to none */
00744     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00745
00746     /* Process Unlocked */
00747     __HAL_UNLOCK(hcan);
00748
00749     /* Enable Error warning Interrupt */
00750     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
00751
00752     /* Enable Error passive Interrupt */
00753     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
00754
00755     /* Enable Bus-off Interrupt */
00756     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
00757
00758     /* Enable Last error code Interrupt */
00759     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
00760
00761     /* Enable Error Interrupt */
00762     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
00763
00764     /* Enable Transmit mailbox empty Interrupt */
00765     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
00766
00767     /* Request transmission */
00768     hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00769   }
00770   else
00771   {
00772     /* Change CAN state */
00773     hcan->State = HAL_CAN_STATE_ERROR;
00774
00775     /* Return function status */
00776     return HAL_ERROR;
00777   }
00778
00779   return HAL_OK;
00780 }
00781
00782 /**
00783   * @brief  Receives a correct CAN frame.
00784   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00785   *         the configuration information for the specified CAN.
00786   * @param  FIFONumber: FIFO Number value
00787   * @param  Timeout: Specify Timeout value
00788   * @retval HAL status
00789   */
00790 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
00791 {
00792   uint32_t tickstart = 0U;
00793
00794   /* Check the parameters */
00795   assert_param(IS_CAN_FIFO(FIFONumber));
00796
00797   /* Process locked */
00798   __HAL_LOCK(hcan);
00799
00800   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00801   {
00802     /* Change CAN state */
00803     hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00804   }
00805   else
00806   {
00807     /* Change CAN state */
00808     hcan->State = HAL_CAN_STATE_BUSY_RX;
00809   }
00810
00811   /* Get tick */
00812   tickstart = HAL_GetTick();
00813
00814   /* Check pending message */
00815   while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
00816   {
00817     /* Check for the Timeout */
00818     if(Timeout != HAL_MAX_DELAY)
00819     {
00820       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00821       {
00822         hcan->State = HAL_CAN_STATE_TIMEOUT;
00823         /* Process unlocked */
00824         __HAL_UNLOCK(hcan);
00825         return HAL_TIMEOUT;
00826       }
00827     }
00828   }
00829
00830   /* Get the Id */
00831   hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00832   if (hcan->pRxMsg->IDE == CAN_ID_STD)
00833   {
00834     hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
00835   }
00836   else
00837   {
00838     hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
00839   }
00840
00841   hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00842   /* Get the DLC */
00843   hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
00844   /* Get the FMI */
00845   hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
00846   /* Get the data field */
00847   hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
00848   hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
00849   hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
00850   hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
00851   hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
00852   hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
00853   hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
00854   hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
00855
00856   /* Release the FIFO */
00857   if(FIFONumber == CAN_FIFO0)
00858   {
00859     /* Release FIFO0 */
00860     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
00861   }
00862   else /* FIFONumber == CAN_FIFO1 */
00863   {
00864     /* Release FIFO1 */
00865     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
00866   }
00867
00868   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00869   {
00870     /* Change CAN state */
00871     hcan->State = HAL_CAN_STATE_BUSY_TX;
00872
00873     /* Process unlocked */
00874     __HAL_UNLOCK(hcan);
00875   }
00876   else
00877   {
00878     /* Change CAN state */
00879     hcan->State = HAL_CAN_STATE_READY;
00880
00881     /* Process unlocked */
00882     __HAL_UNLOCK(hcan);
00883   }
00884
00885   /* Return function status */
00886   return HAL_OK;
00887 }
00888
00889 /**
00890   * @brief  Receives a correct CAN frame.
00891   * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
00892   *         the configuration information for the specified CAN.
00893   * @param  FIFONumber: Specify the FIFO number
00894   * @retval HAL status
00895   */
00896 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
00897 {
00898   uint32_t tmp = 0U;
00899
00900   /* Check the parameters */
00901   assert_param(IS_CAN_FIFO(FIFONumber));
00902
00903   tmp = hcan->State;
00904   if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
00905   {
00906     /* Process locked */
00907     __HAL_LOCK(hcan);
00908
00909     if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00910     {
00911       /* Change CAN state */
00912       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00913     }
00914     else
00915     {
00916       /* Change CAN state */
00917       hcan->State = HAL_CAN_STATE_BUSY_RX;
00918     }
00919
00920     /* Set CAN error code to none */
00921     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00922
00923     /* Enable Error warning Interrupt */
00924     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
00925
00926     /* Enable Error passive Interrupt */
00927     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
00928
00929     /* Enable Bus-off Interrupt */
00930     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
00931
00932     /* Enable Last error code Interrupt */
00933     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
00934
00935     /* Enable Error Interrupt */
00936     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
00937
00938     /* Process unlocked */
00939     __HAL_UNLOCK(hcan);
00940
00941     if(FIFONumber == CAN_FIFO0)
00942     {
00943       /* Enable FIFO 0 message pending Interrupt */
00944       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
00945     }
00946     else
00947     {
00948       /* Enable FIFO 1 message pending Interrupt */
00949       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
00950     }
00951
00952   }
00953   else
00954   {
00955     return HAL_BUSY;
00956   }
00957
00958   /* Return function status */
00959   return HAL_OK;
00960 }
00961
00962 /**
00963   * @brief  Enters the Sleep (low power) mode.
00964   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00965   *         the configuration information for the specified CAN.
00966   * @retval HAL status.
00967   */
00968 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
00969 {
00970   uint32_t tickstart = 0U;
00971
00972   /* Process locked */
00973   __HAL_LOCK(hcan);
00974
00975   /* Change CAN state */
00976   hcan->State = HAL_CAN_STATE_BUSY;
00977
00978   /* Request Sleep mode */
00979    hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
00980
00981   /* Sleep mode status */
00982   if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
00983   {
00984     /* Process unlocked */
00985     __HAL_UNLOCK(hcan);
00986
00987     /* Return function status */
00988     return HAL_ERROR;
00989   }
00990
00991   /* Get tick */
00992   tickstart = HAL_GetTick();
00993
00994   /* Wait the acknowledge */
00995   while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
00996   {
00997     if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
00998     {
00999       hcan->State = HAL_CAN_STATE_TIMEOUT;
01000       /* Process unlocked */
01001       __HAL_UNLOCK(hcan);
01002       return HAL_TIMEOUT;
01003     }
01004   }
01005
01006   /* Change CAN state */
01007   hcan->State = HAL_CAN_STATE_READY;
01008
01009   /* Process unlocked */
01010   __HAL_UNLOCK(hcan);
01011
01012   /* Return function status */
01013   return HAL_OK;
01014 }
01015
01016 /**
01017   * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
01018   *         is in the normal mode.
01019   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01020   *         the configuration information for the specified CAN.
01021   * @retval HAL status.
01022   */
01023 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
01024 {
01025   uint32_t tickstart = 0U;
01026
01027   /* Process locked */
01028   __HAL_LOCK(hcan);
01029
01030   /* Change CAN state */
01031   hcan->State = HAL_CAN_STATE_BUSY;
01032
01033   /* Wake up request */
01034   hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
01035
01036   /* Get tick */
01037   tickstart = HAL_GetTick();
01038
01039   /* Sleep mode status */
01040   while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
01041   {
01042     if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
01043     {
01044       hcan->State= HAL_CAN_STATE_TIMEOUT;
01045       /* Process unlocked */
01046       __HAL_UNLOCK(hcan);
01047       return HAL_TIMEOUT;
01048     }
01049   }
01050   if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
01051   {
01052     /* Process unlocked */
01053     __HAL_UNLOCK(hcan);
01054
01055     /* Return function status */
01056     return HAL_ERROR;
01057   }
01058
01059   /* Change CAN state */
01060   hcan->State = HAL_CAN_STATE_READY;
01061
01062   /* Process unlocked */
01063   __HAL_UNLOCK(hcan);
01064
01065   /* Return function status */
01066   return HAL_OK;
01067 }
01068
01069 /**
01070   * @brief  Handles CAN interrupt request
01071   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01072   *         the configuration information for the specified CAN.
01073   * @retval None
01074   */
01075 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
01076 {
01077   uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
01078
01079   /* Check End of transmission flag */
01080   if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
01081   {
01082     tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
01083     tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
01084     tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
01085     if(tmp1 || tmp2 || tmp3)
01086     {
01087       /* Call transmit function */
01088       CAN_Transmit_IT(hcan);
01089     }
01090   }
01091
01092   tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
01093   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
01094   /* Check End of reception flag for FIFO0 */
01095   if((tmp1 != 0U) && tmp2)
01096   {
01097     /* Call receive function */
01098     CAN_Receive_IT(hcan, CAN_FIFO0);
01099   }
01100
01101   tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
01102   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
01103   /* Check End of reception flag for FIFO1 */
01104   if((tmp1 != 0U) && tmp2)
01105   {
01106     /* Call receive function */
01107     CAN_Receive_IT(hcan, CAN_FIFO1);
01108   }
01109
01110   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
01111   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
01112   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01113   /* Check Error Warning Flag */
01114   if(tmp1 && tmp2 && tmp3)
01115   {
01116     /* Set CAN error code to EWG error */
01117     hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
01118   }
01119
01120   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
01121   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
01122   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01123   /* Check Error Passive Flag */
01124   if(tmp1 && tmp2 && tmp3)
01125   {
01126     /* Set CAN error code to EPV error */
01127     hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
01128   }
01129
01130   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
01131   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
01132   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01133   /* Check Bus-Off Flag */
01134   if(tmp1 && tmp2 && tmp3)
01135   {
01136     /* Set CAN error code to BOF error */
01137     hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
01138   }
01139
01140   tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
01141   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
01142   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01143   /* Check Last error code Flag */
01144   if((!tmp1) && tmp2 && tmp3)
01145   {
01146     tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
01147     switch(tmp1)
01148     {
01149       case(CAN_ESR_LEC_0):
01150           /* Set CAN error code to STF error */
01151           hcan->ErrorCode |= HAL_CAN_ERROR_STF;
01152           break;
01153       case(CAN_ESR_LEC_1):
01154           /* Set CAN error code to FOR error */
01155           hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
01156           break;
01157       case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
01158           /* Set CAN error code to ACK error */
01159           hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
01160           break;
01161       case(CAN_ESR_LEC_2):
01162           /* Set CAN error code to BR error */
01163           hcan->ErrorCode |= HAL_CAN_ERROR_BR;
01164           break;
01165       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
01166           /* Set CAN error code to BD error */
01167           hcan->ErrorCode |= HAL_CAN_ERROR_BD;
01168           break;
01169       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
01170           /* Set CAN error code to CRC error */
01171           hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
01172           break;
01173       default:
01174           break;
01175     }
01176
01177     /* Clear Last error code Flag */
01178     hcan->Instance->ESR &= ~(CAN_ESR_LEC);
01179   }
01180
01181   /* Call the Error call Back in case of Errors */
01182   if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
01183   {
01184     /* Clear ERRI Flag */
01185     hcan->Instance->MSR = CAN_MSR_ERRI;
01186     /* Set the CAN state ready to be able to start again the process */
01187     hcan->State = HAL_CAN_STATE_READY;
01188     /* Call Error callback function */
01189     HAL_CAN_ErrorCallback(hcan);
01190   }
01191 }
01192
01193 /**
01194   * @brief  Transmission  complete callback in non blocking mode
01195   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01196   *         the configuration information for the specified CAN.
01197   * @retval None
01198   */
01199 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
01200 {
01201   /* Prevent unused argument(s) compilation warning */
01202   UNUSED(hcan);
01203   /* NOTE : This function Should not be modified, when the callback is needed,
01204             the HAL_CAN_TxCpltCallback could be implemented in the user file
01205    */
01206 }
01207
01208 /**
01209   * @brief  Transmission  complete callback in non blocking mode
01210   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01211   *         the configuration information for the specified CAN.
01212   * @retval None
01213   */
01214 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
01215 {
01216   /* Prevent unused argument(s) compilation warning */
01217   UNUSED(hcan);
01218   /* NOTE : This function Should not be modified, when the callback is needed,
01219             the HAL_CAN_RxCpltCallback could be implemented in the user file
01220    */
01221 }
01222
01223 /**
01224   * @brief  Error CAN callback.
01225   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01226   *         the configuration information for the specified CAN.
01227   * @retval None
01228   */
01229 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
01230 {
01231   /* Prevent unused argument(s) compilation warning */
01232   UNUSED(hcan);
01233   /* NOTE : This function Should not be modified, when the callback is needed,
01234             the HAL_CAN_ErrorCallback could be implemented in the user file
01235    */
01236 }
01237
01238 /**
01239   * @}
01240   */
01241
01242 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
01243  *  @brief   CAN Peripheral State functions
01244  *
01245 @verbatim
01246   ==============================================================================
01247             ##### Peripheral State and Error functions #####
01248   ==============================================================================
01249     [..]
01250     This subsection provides functions allowing to :
01251       (+) Check the CAN state.
01252       (+) Check CAN Errors detected during interrupt process
01253
01254 @endverbatim
01255   * @{
01256   */
01257
01258 /**
01259   * @brief  return the CAN state
01260   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01261   *         the configuration information for the specified CAN.
01262   * @retval HAL state
01263   */
01264 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
01265 {
01266   /* Return CAN state */
01267   return hcan->State;
01268 }
01269
01270 /**
01271   * @brief  Return the CAN error code
01272   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01273   *         the configuration information for the specified CAN.
01274   * @retval CAN Error Code
01275   */
01276 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
01277 {
01278   return hcan->ErrorCode;
01279 }
01280
01281 /**
01282   * @}
01283   */
01284 /**
01285   * @brief  Initiates and transmits a CAN frame message.
01286   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01287   *         the configuration information for the specified CAN.
01288   * @retval HAL status
01289   */
01290 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
01291 {
01292   /* Disable Transmit mailbox empty Interrupt */
01293   __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
01294
01295   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
01296   {
01297     /* Disable Error warning Interrupt */
01298     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
01299
01300     /* Disable Error passive Interrupt */
01301     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
01302
01303     /* Disable Bus-off Interrupt */
01304     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
01305
01306     /* Disable Last error code Interrupt */
01307     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
01308
01309     /* Disable Error Interrupt */
01310     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
01311   }
01312
01313   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01314   {
01315     /* Change CAN state */
01316     hcan->State = HAL_CAN_STATE_BUSY_RX;
01317   }
01318   else
01319   {
01320     /* Change CAN state */
01321     hcan->State = HAL_CAN_STATE_READY;
01322   }
01323
01324   /* Transmission complete callback */
01325   HAL_CAN_TxCpltCallback(hcan);
01326
01327   return HAL_OK;
01328 }
01329
01330 /**
01331   * @brief  Receives a correct CAN frame.
01332   * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
01333   *         the configuration information for the specified CAN.
01334   * @param  FIFONumber: Specify the FIFO number
01335   * @retval HAL status
01336   * @retval None
01337   */
01338 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
01339 {
01340   /* Get the Id */
01341   hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01342   if (hcan->pRxMsg->IDE == CAN_ID_STD)
01343   {
01344     hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
01345   }
01346   else
01347   {
01348     hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
01349   }
01350
01351   hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01352   /* Get the DLC */
01353   hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
01354   /* Get the FMI */
01355   hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
01356   /* Get the data field */
01357   hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
01358   hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
01359   hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
01360   hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
01361   hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
01362   hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
01363   hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
01364   hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
01365   /* Release the FIFO */
01366   /* Release FIFO0 */
01367   if (FIFONumber == CAN_FIFO0)
01368   {
01369     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
01370
01371     /* Disable FIFO 0 message pending Interrupt */
01372     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
01373   }
01374   /* Release FIFO1 */
01375   else /* FIFONumber == CAN_FIFO1 */
01376   {
01377     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
01378
01379     /* Disable FIFO 1 message pending Interrupt */
01380     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
01381   }
01382
01383   if(hcan->State == HAL_CAN_STATE_BUSY_RX)
01384   {
01385     /* Disable Error warning Interrupt */
01386     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
01387
01388     /* Disable Error passive Interrupt */
01389     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
01390
01391     /* Disable Bus-off Interrupt */
01392     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
01393
01394     /* Disable Last error code Interrupt */
01395     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
01396
01397     /* Disable Error Interrupt */
01398     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
01399   }
01400
01401   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01402   {
01403     /* Disable CAN state */
01404     hcan->State = HAL_CAN_STATE_BUSY_TX;
01405   }
01406   else
01407   {
01408     /* Change CAN state */
01409     hcan->State = HAL_CAN_STATE_READY;
01410   }
01411
01412   /* Receive complete callback */
01413   HAL_CAN_RxCpltCallback(hcan);
01414
01415   /* Return function status */
01416   return HAL_OK;
01417 }
01418
01419 /**
01420   * @}
01421   */
01422 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
01423           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
01424
01425 #endif /* HAL_CAN_MODULE_ENABLED */
01426 /**
01427   * @}
01428   */
01429
01430 /**
01431   * @}
01432   */
01433
01434 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_can.h Source File

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stm32f4xx_hal_can.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_can.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of CAN HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_CAN_H
00040 #define __STM32F4xx_HAL_CAN_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00047     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00048         defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_hal_def.h"
00051
00052 /** @addtogroup STM32F4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup CAN
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup CAN_Exported_Types CAN Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  HAL State structures definition
00067   */
00068 typedef enum
00069 {
00070   HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
00071   HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
00072   HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
00073   HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
00074   HAL_CAN_STATE_BUSY_RX           = 0x22U,  /*!< CAN process is ongoing              */
00075   HAL_CAN_STATE_BUSY_TX_RX        = 0x32U,  /*!< CAN process is ongoing              */
00076   HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< Timeout state                       */
00077   HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
00078
00079 }HAL_CAN_StateTypeDef;
00080
00081 /**
00082   * @brief  CAN init structure definition
00083   */
00084 typedef struct
00085 {
00086   uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
00087                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00088
00089   uint32_t Mode;       /*!< Specifies the CAN operating mode.
00090                             This parameter can be a value of @ref CAN_operating_mode */
00091
00092   uint32_t SJW;        /*!< Specifies the maximum number of time quanta
00093                             the CAN hardware is allowed to lengthen or
00094                             shorten a bit to perform resynchronization.
00095                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
00096
00097   uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
00098                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
00099
00100   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
00101                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
00102
00103   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
00104                             This parameter can be set to ENABLE or DISABLE. */
00105
00106   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
00107                             This parameter can be set to ENABLE or DISABLE */
00108
00109   uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
00110                             This parameter can be set to ENABLE or DISABLE */
00111
00112   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
00113                             This parameter can be set to ENABLE or DISABLE */
00114
00115   uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
00116                             This parameter can be set to ENABLE or DISABLE */
00117
00118   uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
00119                             This parameter can be set to ENABLE or DISABLE */
00120 }CAN_InitTypeDef;
00121
00122 /**
00123   * @brief  CAN filter configuration structure definition
00124   */
00125 typedef struct
00126 {
00127   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
00128                                        configuration, first one for a 16-bit configuration).
00129                                        This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00130
00131   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
00132                                        configuration, second one for a 16-bit configuration).
00133                                        This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00134
00135   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
00136                                        according to the mode (MSBs for a 32-bit configuration,
00137                                        first one for a 16-bit configuration).
00138                                        This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00139
00140   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
00141                                        according to the mode (LSBs for a 32-bit configuration,
00142                                        second one for a 16-bit configuration).
00143                                        This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00144
00145   uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
00146                                        This parameter can be a value of @ref CAN_filter_FIFO */
00147
00148   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
00149                                        This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
00150
00151   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
00152                                        This parameter can be a value of @ref CAN_filter_mode */
00153
00154   uint32_t FilterScale;           /*!< Specifies the filter scale.
00155                                        This parameter can be a value of @ref CAN_filter_scale */
00156
00157   uint32_t FilterActivation;      /*!< Enable or disable the filter.
00158                                        This parameter can be set to ENABLE or DISABLE. */
00159
00160   uint32_t BankNumber;            /*!< Select the start slave bank filter.
00161                                        This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
00162
00163 }CAN_FilterConfTypeDef;
00164
00165 /**
00166   * @brief  CAN Tx message structure definition
00167   */
00168 typedef struct
00169 {
00170   uint32_t StdId;    /*!< Specifies the standard identifier.
00171                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00172
00173   uint32_t ExtId;    /*!< Specifies the extended identifier.
00174                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
00175
00176   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
00177                           This parameter can be a value of @ref CAN_Identifier_Type */
00178
00179   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
00180                           This parameter can be a value of @ref CAN_remote_transmission_request */
00181
00182   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
00183                           This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00184
00185   uint8_t Data[8];   /*!< Contains the data to be transmitted.
00186                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00187
00188 }CanTxMsgTypeDef;
00189
00190 /**
00191   * @brief  CAN Rx message structure definition
00192   */
00193 typedef struct
00194 {
00195   uint32_t StdId;       /*!< Specifies the standard identifier.
00196                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00197
00198   uint32_t ExtId;       /*!< Specifies the extended identifier.
00199                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFFU */
00200
00201   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
00202                              This parameter can be a value of @ref CAN_Identifier_Type */
00203
00204   uint32_t RTR;         /*!< Specifies the type of frame for the received message.
00205                              This parameter can be a value of @ref CAN_remote_transmission_request */
00206
00207   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
00208                              This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00209
00210   uint8_t Data[8];      /*!< Contains the data to be received.
00211                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00212
00213   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
00214                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00215
00216   uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
00217                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
00218
00219 }CanRxMsgTypeDef;
00220
00221 /**
00222   * @brief  CAN handle Structure definition
00223   */
00224 typedef struct
00225 {
00226   CAN_TypeDef                 *Instance;  /*!< Register base address          */
00227
00228   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
00229
00230   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
00231
00232   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
00233
00234   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
00235
00236   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
00237
00238   __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
00239
00240 }CAN_HandleTypeDef;
00241
00242 /**
00243   * @}
00244   */
00245
00246 /* Exported constants --------------------------------------------------------*/
00247 /** @defgroup CAN_Exported_Constants CAN Exported Constants
00248   * @{
00249   */
00250
00251 /** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
00252   * @{
00253   */
00254 #define   HAL_CAN_ERROR_NONE      0x00U    /*!< No error             */
00255 #define   HAL_CAN_ERROR_EWG       0x01U    /*!< EWG error            */
00256 #define   HAL_CAN_ERROR_EPV       0x02U    /*!< EPV error            */
00257 #define   HAL_CAN_ERROR_BOF       0x04U    /*!< BOF error            */
00258 #define   HAL_CAN_ERROR_STF       0x08U    /*!< Stuff error          */
00259 #define   HAL_CAN_ERROR_FOR       0x10U    /*!< Form error           */
00260 #define   HAL_CAN_ERROR_ACK       0x20U    /*!< Acknowledgment error */
00261 #define   HAL_CAN_ERROR_BR        0x40U    /*!< Bit recessive        */
00262 #define   HAL_CAN_ERROR_BD        0x80U    /*!< LEC dominant         */
00263 #define   HAL_CAN_ERROR_CRC       0x100U   /*!< LEC transfer error   */
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup CAN_InitStatus CAN InitStatus
00269   * @{
00270   */
00271 #define CAN_INITSTATUS_FAILED       ((uint8_t)0x00U)  /*!< CAN initialization failed */
00272 #define CAN_INITSTATUS_SUCCESS      ((uint8_t)0x01U)  /*!< CAN initialization OK */
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup CAN_operating_mode CAN Operating Mode
00278   * @{
00279   */
00280 #define CAN_MODE_NORMAL             ((uint32_t)0x00000000U)                     /*!< Normal mode   */
00281 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
00282 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
00283 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
00289   * @{
00290   */
00291 #define CAN_SJW_1TQ                 ((uint32_t)0x00000000U)     /*!< 1 time quantum */
00292 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
00293 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
00294 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
00300   * @{
00301   */
00302 #define CAN_BS1_1TQ                 ((uint32_t)0x00000000U)                                       /*!< 1 time quantum  */
00303 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
00304 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
00305 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
00306 #define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
00307 #define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
00308 #define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
00309 #define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
00310 #define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
00311 #define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
00312 #define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
00313 #define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
00314 #define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
00315 #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
00316 #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
00317 #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
00323   * @{
00324   */
00325 #define CAN_BS2_1TQ                 ((uint32_t)0x00000000U)                       /*!< 1 time quantum */
00326 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
00327 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
00328 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
00329 #define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
00330 #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
00331 #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
00332 #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup CAN_filter_mode  CAN Filter Mode
00338   * @{
00339   */
00340 #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00U)  /*!< Identifier mask mode */
00341 #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01U)  /*!< Identifier list mode */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup CAN_filter_scale CAN Filter Scale
00347   * @{
00348   */
00349 #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00U)  /*!< Two 16-bit filters */
00350 #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01U)  /*!< One 32-bit filter  */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
00356   * @{
00357   */
00358 #define CAN_FILTER_FIFO0             ((uint8_t)0x00U)  /*!< Filter FIFO 0 assignment for filter x */
00359 #define CAN_FILTER_FIFO1             ((uint8_t)0x01U)  /*!< Filter FIFO 1 assignment for filter x */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup CAN_Identifier_Type CAN Identifier Type
00365   * @{
00366   */
00367 #define CAN_ID_STD             ((uint32_t)0x00000000U)  /*!< Standard Id */
00368 #define CAN_ID_EXT             ((uint32_t)0x00000004U)  /*!< Extended Id */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
00374   * @{
00375   */
00376 #define CAN_RTR_DATA                ((uint32_t)0x00000000U)  /*!< Data frame */
00377 #define CAN_RTR_REMOTE              ((uint32_t)0x00000002U)  /*!< Remote frame */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
00383   * @{
00384   */
00385 #define CAN_FIFO0                   ((uint8_t)0x00U)  /*!< CAN FIFO 0 used to receive */
00386 #define CAN_FIFO1                   ((uint8_t)0x01U)  /*!< CAN FIFO 1 used to receive */
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup CAN_flags CAN Flags
00392   * @{
00393   */
00394 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
00395    and CAN_ClearFlag() functions. */
00396 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
00397    CAN_GetFlagStatus() function.  */
00398
00399 /* Transmit Flags */
00400 #define CAN_FLAG_RQCP0             ((uint32_t)0x00000500U)  /*!< Request MailBox0 flag         */
00401 #define CAN_FLAG_RQCP1             ((uint32_t)0x00000508U)  /*!< Request MailBox1 flag         */
00402 #define CAN_FLAG_RQCP2             ((uint32_t)0x00000510U)  /*!< Request MailBox2 flag         */
00403 #define CAN_FLAG_TXOK0             ((uint32_t)0x00000501U)  /*!< Transmission OK MailBox0 flag */
00404 #define CAN_FLAG_TXOK1             ((uint32_t)0x00000509U)  /*!< Transmission OK MailBox1 flag */
00405 #define CAN_FLAG_TXOK2             ((uint32_t)0x00000511U)  /*!< Transmission OK MailBox2 flag */
00406 #define CAN_FLAG_TME0              ((uint32_t)0x0000051AU)  /*!< Transmit mailbox 0 empty flag */
00407 #define CAN_FLAG_TME1              ((uint32_t)0x0000051BU)  /*!< Transmit mailbox 0 empty flag */
00408 #define CAN_FLAG_TME2              ((uint32_t)0x0000051CU)  /*!< Transmit mailbox 0 empty flag */
00409
00410 /* Receive Flags */
00411 #define CAN_FLAG_FF0               ((uint32_t)0x00000203U)  /*!< FIFO 0 Full flag    */
00412 #define CAN_FLAG_FOV0              ((uint32_t)0x00000204U)  /*!< FIFO 0 Overrun flag */
00413
00414 #define CAN_FLAG_FF1               ((uint32_t)0x00000403U)  /*!< FIFO 1 Full flag    */
00415 #define CAN_FLAG_FOV1              ((uint32_t)0x00000404U)  /*!< FIFO 1 Overrun flag */
00416
00417 /* Operating Mode Flags */
00418 #define CAN_FLAG_INAK              ((uint32_t)0x00000100U)  /*!<  Initialization acknowledge flag */
00419 #define CAN_FLAG_SLAK              ((uint32_t)0x00000101U)  /*!< Sleep acknowledge flag */
00420 #define CAN_FLAG_ERRI              ((uint32_t)0x00000102U)  /*!<  Error flag */
00421 #define CAN_FLAG_WKU               ((uint32_t)0x00000103U)  /*!< Wake up flag           */
00422 #define CAN_FLAG_SLAKI             ((uint32_t)0x00000104U)  /*!< Sleep acknowledge flag */
00423
00424 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
00425          In this case the SLAK bit can be polled.*/
00426
00427 /* Error Flags */
00428 #define CAN_FLAG_EWG               ((uint32_t)0x00000300U)  /*!< Error warning flag   */
00429 #define CAN_FLAG_EPV               ((uint32_t)0x00000301U)  /*!< Error passive flag   */
00430 #define CAN_FLAG_BOF               ((uint32_t)0x00000302U)  /*!< Bus-Off flag         */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup CAN_Interrupts CAN Interrupts
00436   * @{
00437   */
00438 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
00439
00440 /* Receive Interrupts */
00441 #define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
00442 #define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
00443 #define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
00444 #define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
00445 #define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
00446 #define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
00447
00448 /* Operating Mode Interrupts */
00449 #define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
00450 #define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
00451
00452 /* Error Interrupts */
00453 #define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
00454 #define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
00455 #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
00456 #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
00457 #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
00463   * @{
00464   */
00465 #define CAN_TXMAILBOX_0   ((uint8_t)0x00U)
00466 #define CAN_TXMAILBOX_1   ((uint8_t)0x01U)
00467 #define CAN_TXMAILBOX_2   ((uint8_t)0x02U)
00468 /**
00469   * @}
00470   */
00471
00472 /**
00473   * @}
00474   */
00475
00476 /* Exported macro ------------------------------------------------------------*/
00477 /** @defgroup CAN_Exported_Macros CAN Exported Macros
00478   * @{
00479   */
00480
00481 /** @brief Reset CAN handle state
00482   * @param  __HANDLE__: specifies the CAN Handle.
00483   * @retval None
00484   */
00485 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
00486
00487 /**
00488   * @brief  Enable the specified CAN interrupts.
00489   * @param  __HANDLE__: CAN handle
00490   * @param  __INTERRUPT__: CAN Interrupt
00491   * @retval None
00492   */
00493 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
00494
00495 /**
00496   * @brief  Disable the specified CAN interrupts.
00497   * @param  __HANDLE__: CAN handle
00498   * @param  __INTERRUPT__: CAN Interrupt
00499   * @retval None
00500   */
00501 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
00502
00503 /**
00504   * @brief  Return the number of pending received messages.
00505   * @param  __HANDLE__: CAN handle
00506   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00507   * @retval The number of pending message.
00508   */
00509 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00510 ((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & (uint32_t)0x03U)))
00511
00512 /** @brief  Check whether the specified CAN flag is set or not.
00513   * @param  __HANDLE__: CAN Handle
00514   * @param  __FLAG__: specifies the flag to check.
00515   *         This parameter can be one of the following values:
00516   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00517   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00518   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00519   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00520   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00521   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00522   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00523   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00524   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00525   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00526   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00527   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00528   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00529   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00530   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00531   *            @arg CAN_FLAG_WKU: Wake up Flag
00532   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
00533   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00534   *            @arg CAN_FLAG_EWG: Error Warning Flag
00535   *            @arg CAN_FLAG_EPV: Error Passive Flag
00536   *            @arg CAN_FLAG_BOF: Bus-Off Flag
00537   * @retval The new state of __FLAG__ (TRUE or FALSE).
00538   */
00539 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
00540 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00541  (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00542  (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00543  (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00544  ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
00545
00546 /** @brief  Clear the specified CAN pending flag.
00547   * @param  __HANDLE__: CAN Handle.
00548   * @param  __FLAG__: specifies the flag to check.
00549   *         This parameter can be one of the following values:
00550   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00551   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00552   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00553   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00554   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00555   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00556   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00557   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00558   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00559   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00560   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00561   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00562   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00563   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00564   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00565   *            @arg CAN_FLAG_WKU: Wake up Flag
00566   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
00567   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00568   * @retval The new state of __FLAG__ (TRUE or FALSE).
00569   */
00570 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00571 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00572  (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00573  (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00574  (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
00575
00576 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
00577   * @param  __HANDLE__: CAN Handle
00578   * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
00579   *          This parameter can be one of the following values:
00580   *             @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
00581   *             @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
00582   *             @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
00583   * @retval The new state of __IT__ (TRUE or FALSE).
00584   */
00585 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00586
00587 /**
00588   * @brief  Check the transmission status of a CAN Frame.
00589   * @param  __HANDLE__: CAN Handle
00590   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00591   * @retval The new status of transmission  (TRUE or FALSE).
00592   */
00593 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
00594 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
00595  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
00596  ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
00597
00598 /**
00599   * @brief  Release the specified receive FIFO.
00600   * @param  __HANDLE__: CAN handle
00601   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00602   * @retval None
00603   */
00604 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00605 ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
00606
00607 /**
00608   * @brief  Cancel a transmit request.
00609   * @param  __HANDLE__: CAN Handle
00610   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00611   * @retval None
00612   */
00613 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
00614 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
00615  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
00616  ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
00617
00618 /**
00619   * @brief  Enable or disable the DBG Freeze for CAN.
00620   * @param  __HANDLE__: CAN Handle
00621   * @param  __NEWSTATE__: new state of the CAN peripheral.
00622   *          This parameter can be: ENABLE (CAN reception/transmission is frozen
00623   *          during debug. Reception FIFOs can still be accessed/controlled normally)
00624   *          or DISABLE (CAN is working during debug).
00625   * @retval None
00626   */
00627 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
00628 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
00629
00630 /**
00631   * @}
00632   */
00633
00634 /* Exported functions --------------------------------------------------------*/
00635 /** @addtogroup CAN_Exported_Functions
00636   * @{
00637   */
00638
00639 /** @addtogroup CAN_Exported_Functions_Group1
00640   * @{
00641   */
00642 /* Initialization/de-initialization functions ***********************************/
00643 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
00644 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
00645 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
00646 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
00647 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
00648 /**
00649   * @}
00650   */
00651
00652 /** @addtogroup CAN_Exported_Functions_Group2
00653   * @{
00654   */
00655 /* I/O operation functions ******************************************************/
00656 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
00657 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
00658 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
00659 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
00660 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
00661 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
00662 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
00663 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
00664 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
00665 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
00666 /**
00667   * @}
00668   */
00669
00670 /** @addtogroup CAN_Exported_Functions_Group3
00671   * @{
00672   */
00673 /* Peripheral State functions ***************************************************/
00674 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
00675 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683
00684 /* Private types -------------------------------------------------------------*/
00685 /** @defgroup CAN_Private_Types CAN Private Types
00686   * @{
00687   */
00688
00689 /**
00690   * @}
00691   */
00692
00693 /* Private variables ---------------------------------------------------------*/
00694 /** @defgroup CAN_Private_Variables CAN Private Variables
00695   * @{
00696   */
00697
00698 /**
00699   * @}
00700   */
00701
00702 /* Private constants ---------------------------------------------------------*/
00703 /** @defgroup CAN_Private_Constants CAN Private Constants
00704   * @{
00705   */
00706 #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04U)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
00707 #define CAN_FLAG_MASK  ((uint32_t)0x000000FFU)
00708 /**
00709   * @}
00710   */
00711
00712 /* Private macros ------------------------------------------------------------*/
00713 /** @defgroup CAN_Private_Macros CAN Private Macros
00714   * @{
00715   */
00716 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
00717                            ((MODE) == CAN_MODE_LOOPBACK)|| \
00718                            ((MODE) == CAN_MODE_SILENT) || \
00719                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
00720 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
00721                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
00722 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
00723 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
00724 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
00725 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
00726 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
00727                                   ((MODE) == CAN_FILTERMODE_IDLIST))
00728 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
00729                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
00730 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
00731                                   ((FIFO) == CAN_FILTER_FIFO1))
00732 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
00733
00734 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
00735 #define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FFU))
00736 #define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFFU))
00737 #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08U))
00738
00739 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
00740                                 ((IDTYPE) == CAN_ID_EXT))
00741 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
00742 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
00743
00744 /**
00745   * @}
00746   */
00747
00748 /* Private functions ---------------------------------------------------------*/
00749 /** @defgroup CAN_Private_Functions CAN Private Functions
00750   * @{
00751   */
00752
00753 /**
00754   * @}
00755   */
00756
00757 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00758           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00759
00760 /**
00761   * @}
00762   */
00763
00764 /**
00765   * @}
00766   */
00767
00768 #ifdef __cplusplus
00769 }
00770 #endif
00771
00772 #endif /* __STM32F4xx_CAN_H */
00773
00774
00775 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cec.c Source File

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stm32f4xx_hal_cec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cec.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   CEC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the High Definition Multimedia Interface
00010   *          Consumer Electronics Control Peripheral (CEC).
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral Control functions
00014   *
00015   *
00016   @verbatim
00017  ===============================================================================
00018                         ##### How to use this driver #####
00019  ===============================================================================
00020     [..]
00021     The CEC HAL driver can be used as follow:
00022
00023     (#) Declare a CEC_HandleTypeDef handle structure.
00024     (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
00025         (##) Enable the CEC interface clock.
00026         (##) CEC pins configuration:
00027             (+) Enable the clock for the CEC GPIOs.
00028             (+) Configure these CEC pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
00030              and HAL_CEC_Receive_IT() APIs):
00031             (+) Configure the CEC interrupt priority.
00032             (+) Enable the NVIC CEC IRQ handle.
00033             (@) The specific CEC interrupts (Transmission complete interrupt,
00034                 RXNE interrupt and Error Interrupts) will be managed using the macros
00035                 __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
00036                 and receive process.
00037
00038     (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
00039         in case of Bit Rising Error, Error-Bit generation conditions, device logical
00040         address and Listen mode in the hcec Init structure.
00041
00042     (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
00043
00044     (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00045         by calling the customed HAL_CEC_MspInit() API.
00046
00047   @endverbatim
00048   ******************************************************************************
00049   * @attention
00050   *
00051   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00052   *
00053   * Redistribution and use in source and binary forms, with or without modification,
00054   * are permitted provided that the following conditions are met:
00055   *   1. Redistributions of source code must retain the above copyright notice,
00056   *      this list of conditions and the following disclaimer.
00057   *   2. Redistributions in binary form must reproduce the above copyright notice,
00058   *      this list of conditions and the following disclaimer in the documentation
00059   *      and/or other materials provided with the distribution.
00060   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00061   *      may be used to endorse or promote products derived from this software
00062   *      without specific prior written permission.
00063   *
00064   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00065   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00066   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00067   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00068   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00069   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00070   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00071   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00072   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00073   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00074   *
00075   ******************************************************************************
00076   */
00077
00078 /* Includes ------------------------------------------------------------------*/
00079 #include "stm32f4xx_hal.h"
00080
00081 /** @addtogroup STM32F4xx_HAL_Driver
00082   * @{
00083   */
00084
00085 /** @defgroup CEC CEC
00086   * @brief HAL CEC module driver
00087   * @{
00088   */
00089 #ifdef HAL_CEC_MODULE_ENABLED
00090
00091 #if defined(STM32F446xx)
00092
00093 /* Private typedef -----------------------------------------------------------*/
00094 /* Private define ------------------------------------------------------------*/
00095 /** @defgroup CEC_Private_Constants CEC Private Constants
00096   * @{
00097   */
00098 #define CEC_CFGR_FIELDS     (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
00099                            | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
00100                            | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
00101 /**
00102   * @}
00103   */
00104
00105 /* Private macro -------------------------------------------------------------*/
00106 /* Private variables ---------------------------------------------------------*/
00107 /* Private function prototypes -----------------------------------------------*/
00108 /** @defgroup CEC_Private_Functions CEC Private Functions
00109   * @{
00110   */
00111 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
00112 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
00113 /**
00114   * @}
00115   */
00116
00117 /* Exported functions ---------------------------------------------------------*/
00118 /** @defgroup CEC_Exported_Functions CEC Exported Functions
00119   * @{
00120   */
00121
00122 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00123   *  @brief    Initialization and Configuration functions
00124   *
00125 @verbatim
00126 ===============================================================================
00127             ##### Initialization and Configuration functions #####
00128  ===============================================================================
00129     [..]
00130     This subsection provides a set of functions allowing to initialize the CEC
00131       (+) The following parameters need to be configured:
00132         (++) SignalFreeTime
00133         (++) Tolerance
00134         (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
00135         (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
00136         (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
00137         (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
00138         (++) SignalFreeTimeOption      (SFT Timer start definition)
00139         (++) OwnAddress                (CEC device address)
00140         (++) ListenMode
00141
00142 @endverbatim
00143   * @{
00144   */
00145
00146 /**
00147   * @brief Initializes the CEC mode according to the specified
00148   *         parameters in the CEC_InitTypeDef and creates the associated handle .
00149   * @param hcec: CEC handle
00150   * @retval HAL status
00151   */
00152 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
00153 {
00154   uint32_t tmpreg = 0x0U;
00155
00156   /* Check the CEC handle allocation */
00157   if(hcec == NULL)
00158   {
00159     return HAL_ERROR;
00160   }
00161
00162   /* Check the parameters */
00163   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00164   assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
00165   assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
00166   assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
00167   assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
00168   assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
00169   assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
00170   assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
00171   assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
00172   assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
00173   assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
00174
00175
00176   if(hcec->State == HAL_CEC_STATE_RESET)
00177   {
00178     /* Allocate lock resource and initialize it */
00179     hcec->Lock = HAL_UNLOCKED;
00180     /* Init the low level hardware : GPIO, CLOCK */
00181     HAL_CEC_MspInit(hcec);
00182   }
00183
00184   hcec->State = HAL_CEC_STATE_BUSY;
00185
00186   /* Disable the Peripheral */
00187   __HAL_CEC_DISABLE(hcec);
00188
00189   tmpreg = hcec->Init.SignalFreeTime;
00190   tmpreg |= hcec->Init.Tolerance;
00191   tmpreg |= hcec->Init.BRERxStop;
00192   tmpreg |= hcec->Init.BREErrorBitGen;
00193   tmpreg |= hcec->Init.LBPEErrorBitGen;
00194   tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
00195   tmpreg |= hcec->Init.SignalFreeTimeOption;
00196   tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
00197   tmpreg |= hcec->Init.ListenMode;
00198
00199   /* Write to CEC Control Register */
00200   MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
00201
00202   /* Enable the Peripheral */
00203   __HAL_CEC_ENABLE(hcec);
00204
00205   hcec->State = HAL_CEC_STATE_READY;
00206
00207   return HAL_OK;
00208 }
00209
00210 /**
00211   * @brief DeInitializes the CEC peripheral
00212   * @param hcec: CEC handle
00213   * @retval HAL status
00214   */
00215 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
00216 {
00217   /* Check the CEC handle allocation */
00218   if(hcec == NULL)
00219   {
00220     return HAL_ERROR;
00221   }
00222
00223   /* Check the parameters */
00224   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00225
00226   hcec->State = HAL_CEC_STATE_BUSY;
00227
00228   /* DeInit the low level hardware */
00229   HAL_CEC_MspDeInit(hcec);
00230   /* Disable the Peripheral */
00231   __HAL_CEC_DISABLE(hcec);
00232
00233   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00234   hcec->State = HAL_CEC_STATE_RESET;
00235
00236   /* Process Unlock */
00237   __HAL_UNLOCK(hcec);
00238
00239   return HAL_OK;
00240 }
00241
00242 /**
00243   * @brief CEC MSP Init
00244   * @param hcec: CEC handle
00245   * @retval None
00246   */
00247  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
00248 {
00249   /* Prevent unused argument(s) compilation warning */
00250   UNUSED(hcec);
00251   /* NOTE : This function should not be modified, when the callback is needed,
00252             the HAL_CEC_MspInit can be implemented in the user file
00253    */
00254 }
00255
00256 /**
00257   * @brief CEC MSP DeInit
00258   * @param hcec: CEC handle
00259   * @retval None
00260   */
00261  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
00262 {
00263   /* Prevent unused argument(s) compilation warning */
00264   UNUSED(hcec);
00265   /* NOTE : This function should not be modified, when the callback is needed,
00266             the HAL_CEC_MspDeInit can be implemented in the user file
00267    */
00268 }
00269
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
00275   *  @brief CEC Transmit/Receive functions
00276   *
00277 @verbatim
00278  ===============================================================================
00279                       ##### IO operation functions #####
00280  ===============================================================================
00281     This subsection provides a set of functions allowing to manage the CEC data transfers.
00282
00283     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
00284         logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
00285
00286     (#) There are two mode of transfer:
00287        (+) Blocking mode: The communication is performed in polling mode.
00288             The HAL status of all data processing is returned by the same function
00289             after finishing transfer.
00290        (+) No-Blocking mode: The communication is performed using Interrupts.
00291            These API's return the HAL status.
00292            The end of the data processing will be indicated through the
00293            dedicated CEC IRQ when using Interrupt mode.
00294            The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
00295            will be executed respectivelly at the end of the transmit or Receive process
00296            The HAL_CEC_ErrorCallback()user callback will be executed when a communication
00297            error is detected
00298
00299     (#) Blocking mode API's are :
00300         (+) HAL_CEC_Transmit()
00301         (+) HAL_CEC_Receive()
00302
00303     (#) Non-Blocking mode API's with Interrupt are :
00304         (+) HAL_CEC_Transmit_IT()
00305         (+) HAL_CEC_Receive_IT()
00306         (+) HAL_CEC_IRQHandler()
00307
00308     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00309         (+) HAL_CEC_TxCpltCallback()
00310         (+) HAL_CEC_RxCpltCallback()
00311         (+) HAL_CEC_ErrorCallback()
00312
00313 @endverbatim
00314   * @{
00315   */
00316
00317 /**
00318   * @brief Send data in blocking mode
00319   * @param hcec: CEC handle
00320   * @param DestinationAddress: destination logical address
00321   * @param pData: pointer to input byte data buffer
00322   * @param Size: amount of data to be sent in bytes (without counting the header).
00323   *              0 means only the header is sent (ping operation).
00324   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00325   * @param  Timeout: Timeout duration.
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
00329 {
00330  uint8_t  temp = 0U;
00331   uint32_t tempisr = 0U;
00332   uint32_t tickstart = 0U;
00333
00334   if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
00335   {
00336     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00337     if((pData == NULL ) && (Size > 0U))
00338     {
00339       hcec->State = HAL_CEC_STATE_ERROR;
00340       return  HAL_ERROR;
00341     }
00342
00343     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00344     assert_param(IS_CEC_MSGSIZE(Size));
00345
00346     /* Process Locked */
00347     __HAL_LOCK(hcec);
00348
00349     hcec->State = HAL_CEC_STATE_BUSY_TX;
00350
00351     hcec->TxXferCount = Size;
00352
00353     /* case no data to be sent, sender is only pinging the system */
00354     if (Size == 0U)
00355     {
00356       /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00357       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00358     }
00359
00360     /* send header block */
00361     temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
00362     hcec->Instance->TXDR = temp;
00363     /* Set TX Start of Message  (TXSOM) bit */
00364     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00365
00366     while (hcec->TxXferCount > 0U)
00367     {
00368       hcec->TxXferCount--;
00369
00370       tickstart = HAL_GetTick();
00371       while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
00372       {
00373         if(Timeout != HAL_MAX_DELAY)
00374         {
00375           if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
00376           {
00377             hcec->State = HAL_CEC_STATE_TIMEOUT;
00378             /* Process Unlocked */
00379             __HAL_UNLOCK(hcec);
00380             return HAL_TIMEOUT;
00381           }
00382         }
00383
00384         /* check whether error occured while waiting for TXBR to be set:
00385          * has Tx underrun occurred ?
00386          * has Tx error occurred ?
00387          * has Tx Missing Acknowledge error occurred ?
00388          * has Arbitration Loss error occurred ? */
00389         tempisr = hcec->Instance->ISR;
00390         if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0U)
00391         {
00392           /* copy ISR for error handling purposes */
00393           hcec->ErrorCode = tempisr;
00394          /* clear all error flags by default */
00395          __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
00396          hcec->State = HAL_CEC_STATE_ERROR;
00397          __HAL_UNLOCK(hcec);
00398          return  HAL_ERROR;
00399         }
00400       }
00401       /* TXBR to clear BEFORE writing TXDR register */
00402       __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
00403       if (hcec->TxXferCount == 0U)
00404       {
00405         /* if last byte transmission, set TX End of Message (TXEOM) bit */
00406         __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00407       }
00408       hcec->Instance->TXDR = *pData++;
00409
00410       /* error check after TX byte write up */
00411       tempisr = hcec->Instance->ISR;
00412       if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0U)
00413       {
00414         /* copy ISR for error handling purposes */
00415         hcec->ErrorCode = tempisr;
00416         /* clear all error flags by default */
00417         __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
00418         hcec->State = HAL_CEC_STATE_ERROR;
00419         __HAL_UNLOCK(hcec);
00420         return  HAL_ERROR;
00421       }
00422     } /* end while (while (hcec->TxXferCount > 0)) */
00423
00424     /* if no error up to this point, check that transmission is
00425      * complete, that is wait until TXEOM is reset */
00426     tickstart = HAL_GetTick();
00427
00428     while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
00429     {
00430       if(Timeout != HAL_MAX_DELAY)
00431       {
00432         if((HAL_GetTick() - tickstart) > Timeout)
00433         {
00434           hcec->State = HAL_CEC_STATE_ERROR;
00435           __HAL_UNLOCK(hcec);
00436           return HAL_TIMEOUT;
00437         }
00438       }
00439     }
00440
00441     /* Final error check once all bytes have been transmitted */
00442     tempisr = hcec->Instance->ISR;
00443     if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0U)
00444     {
00445       /* copy ISR for error handling purposes */
00446       hcec->ErrorCode = tempisr;
00447       /* clear all error flags by default */
00448       __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
00449       hcec->State = HAL_CEC_STATE_ERROR;
00450       __HAL_UNLOCK(hcec);
00451       return  HAL_ERROR;
00452     }
00453
00454     hcec->State = HAL_CEC_STATE_READY;
00455     __HAL_UNLOCK(hcec);
00456
00457     return HAL_OK;
00458   }
00459   else
00460   {
00461     return HAL_BUSY;
00462   }
00463 }
00464
00465 /**
00466   * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
00467   * @param hcec: CEC handle
00468   * @param pData: pointer to received data buffer.
00469   * @param Timeout: Timeout duration.
00470   *       Note that the received data size is not known beforehand, the latter is known
00471   *       when the reception is complete and is stored in hcec->RxXferSize.
00472   *       hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
00473   *       If only a header is received, hcec->RxXferSize = 0
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
00477 {
00478   uint32_t temp;
00479   uint32_t tickstart = 0U;
00480
00481   if (hcec->State == HAL_CEC_STATE_READY)
00482   {
00483     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00484     if (pData == NULL )
00485     {
00486       hcec->State = HAL_CEC_STATE_ERROR;
00487       return  HAL_ERROR;
00488     }
00489
00490     hcec->RxXferSize = 0U;
00491     /* Process Locked */
00492     __HAL_LOCK(hcec);
00493
00494     /* Rx loop until CEC_ISR_RXEND  is set */
00495     while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
00496     {
00497       tickstart = HAL_GetTick();
00498       /* Wait for next byte to be received */
00499       while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
00500       {
00501         if(Timeout != HAL_MAX_DELAY)
00502         {
00503           if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
00504           {
00505             hcec->State = HAL_CEC_STATE_TIMEOUT;
00506             __HAL_UNLOCK(hcec);
00507             return HAL_TIMEOUT;
00508           }
00509         }
00510         /* any error so far ?
00511          * has Rx Missing Acknowledge occurred ?
00512          * has Rx Long Bit Period error occurred ?
00513          * has Rx Short Bit Period error occurred ?
00514          * has Rx Bit Rising error occurred ?
00515          * has Rx Overrun error occurred ? */
00516         temp = (uint32_t) (hcec->Instance->ISR);
00517         if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0U)
00518         {
00519           /* copy ISR for error handling purposes */
00520           hcec->ErrorCode = temp;
00521           /* clear all error flags by default */
00522           __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
00523           hcec->State = HAL_CEC_STATE_ERROR;
00524           __HAL_UNLOCK(hcec);
00525           return  HAL_ERROR;
00526         }
00527       } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
00528
00529       /* read received data */
00530       *pData++ = hcec->Instance->RXDR;
00531       temp = (uint32_t) (hcec->Instance->ISR);
00532       /* end of message ? */
00533       if ((temp &  CEC_ISR_RXEND) != 0U)
00534       {
00535          assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
00536          __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
00537           hcec->State = HAL_CEC_STATE_READY;
00538          __HAL_UNLOCK(hcec);
00539          return HAL_OK;
00540       }
00541
00542       /* clear Rx-Byte Received flag */
00543       __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
00544       /* increment payload byte counter */
00545        hcec->RxXferSize++;
00546     } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
00547
00548     /* if the instructions below are executed, it means RXEND was set when RXBR was
00549      * set for the first time:
00550      * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
00551      * loop has not been executed and this means a single byte has been sent */
00552     *pData++ = hcec->Instance->RXDR;
00553      /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
00554      hcec->RxXferSize = 0U;
00555      __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
00556
00557     hcec->State = HAL_CEC_STATE_READY;
00558     __HAL_UNLOCK(hcec);
00559     return HAL_OK;
00560   }
00561   else
00562   {
00563     return HAL_BUSY;
00564   }
00565 }
00566
00567 /**
00568   * @brief Send data in interrupt mode
00569   * @param hcec: CEC handle
00570   * @param DestinationAddress: destination logical address
00571   * @param pData: pointer to input byte data buffer
00572   * @param Size: amount of data to be sent in bytes (without counting the header).
00573   *              0 means only the header is sent (ping operation).
00574   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00575   * @retval HAL status
00576   */
00577 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
00578 {
00579   uint8_t  temp = 0U;
00580   /* if the IP isn't already busy and if there is no previous transmission
00581      already pending due to arbitration lost */
00582   if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
00583   &&   (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
00584   {
00585     if((pData == NULL) && (Size > 0U))
00586     {
00587       hcec->State = HAL_CEC_STATE_ERROR;
00588       return  HAL_ERROR;
00589     }
00590
00591     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00592     assert_param(IS_CEC_MSGSIZE(Size));
00593
00594     /* Process Locked */
00595     __HAL_LOCK(hcec);
00596     hcec->pTxBuffPtr = pData;
00597     hcec->State = HAL_CEC_STATE_BUSY_TX;
00598     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00599
00600     /* Disable Peripheral to write CEC_IER register */
00601     __HAL_CEC_DISABLE(hcec);
00602
00603     /* Enable the following two CEC Transmission interrupts as
00604      * well as the following CEC Transmission Errors interrupts:
00605      * Tx Byte Request IT
00606      * End of Transmission IT
00607      * Tx Missing Acknowledge IT
00608      * Tx-Error IT
00609      * Tx-Buffer Underrun IT
00610      * Tx arbitration lost     */
00611     __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
00612
00613     /* Enable the Peripheral */
00614     __HAL_CEC_ENABLE(hcec);
00615
00616     /* initialize the number of bytes to send,
00617      * 0 means only one header is sent (ping operation) */
00618     hcec->TxXferCount = Size;
00619
00620     /* Process Unlocked */
00621     __HAL_UNLOCK(hcec);
00622
00623     /* in case of no payload (Size = 0), sender is only pinging the system;
00624      * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
00625     if (Size == 0U)
00626     {
00627       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00628     }
00629
00630     /* send header block */
00631     temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
00632     hcec->Instance->TXDR = temp;
00633     /* Set TX Start of Message  (TXSOM) bit */
00634     __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
00635
00636     return HAL_OK;
00637   }
00638     /* if the IP is already busy or if there is a previous transmission
00639      already pending due to arbitration loss */
00640   else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
00641   {
00642     __HAL_LOCK(hcec);
00643     /* set state to BUSY TX, in case it wasn't set already (case
00644      * of transmission new attempt after arbitration loss) */
00645     if (hcec->State != HAL_CEC_STATE_BUSY_TX)
00646     {
00647       hcec->State = HAL_CEC_STATE_BUSY_TX;
00648     }
00649
00650     /* if all data have been sent */
00651     if(hcec->TxXferCount == 0U)
00652     {
00653       /* Disable Peripheral to write CEC_IER register */
00654       __HAL_CEC_DISABLE(hcec);
00655
00656       /* Disable the CEC Transmission Interrupts */
00657       __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
00658       /* Disable the CEC Transmission Error Interrupts */
00659       __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
00660
00661       /* Enable the Peripheral */
00662       __HAL_CEC_ENABLE(hcec);
00663
00664       __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
00665
00666       hcec->State = HAL_CEC_STATE_READY;
00667       /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
00668       start again the Transmission under the Tx call back API */
00669       __HAL_UNLOCK(hcec);
00670
00671       HAL_CEC_TxCpltCallback(hcec);
00672
00673       return HAL_OK;
00674     }
00675     else
00676     {
00677       if (hcec->TxXferCount == 1U)
00678       {
00679         /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
00680         __HAL_CEC_LAST_BYTE_TX_SET(hcec);
00681       }
00682       /* clear Tx-Byte request flag */
00683        __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
00684        hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
00685       hcec->TxXferCount--;
00686
00687       /* Process Unlocked */
00688       __HAL_UNLOCK(hcec);
00689
00690       return HAL_OK;
00691     }
00692   }
00693   else
00694   {
00695     return HAL_BUSY;
00696   }
00697 }
00698
00699 /**
00700   * @brief Receive data in interrupt mode.
00701   * @param hcec: CEC handle
00702   * @param pData: pointer to received data buffer.
00703   * Note that the received data size is not known beforehand, the latter is known
00704   * when the reception is complete and is stored in hcec->RxXferSize.
00705   * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
00706   * If only a header is received, hcec->RxXferSize = 0
00707   * @retval HAL status
00708   */
00709 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
00710 {
00711   if(hcec->State == HAL_CEC_STATE_READY)
00712   {
00713     if(pData == NULL)
00714     {
00715       hcec->State = HAL_CEC_STATE_ERROR;
00716       return HAL_ERROR;
00717     }
00718
00719     /* Process Locked */
00720     __HAL_LOCK(hcec);
00721     hcec->RxXferSize = 0U;
00722     hcec->pRxBuffPtr = pData;
00723     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00724     /* the IP is moving to a ready to receive state */
00725     hcec->State = HAL_CEC_STATE_STANDBY_RX;
00726
00727     /* Disable Peripheral to write CEC_IER register */
00728     __HAL_CEC_DISABLE(hcec);
00729
00730     /* Enable the following CEC Reception Error Interrupts:
00731      * Rx overrun
00732      * Rx bit rising error
00733      * Rx short bit period error
00734      * Rx long bit period error
00735      * Rx missing acknowledge  */
00736     __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
00737
00738     /* Process Unlocked */
00739     __HAL_UNLOCK(hcec);
00740
00741     /* Enable the following two CEC Reception interrupts:
00742      * Rx Byte Received IT
00743      * End of Reception IT */
00744     __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
00745
00746     __HAL_CEC_ENABLE(hcec);
00747
00748     return HAL_OK;
00749   }
00750   else
00751   {
00752     return HAL_BUSY;
00753   }
00754 }
00755
00756 /**
00757   * @brief Get size of the received frame.
00758   * @param hcec: CEC handle
00759   * @retval Frame size
00760   */
00761 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
00762 {
00763   return hcec->RxXferSize;
00764 }
00765
00766 /**
00767   * @brief This function handles CEC interrupt requests.
00768   * @param hcec: CEC handle
00769   * @retval None
00770   */
00771 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
00772 {
00773   /* save interrupts register for further error or interrupts handling purposes */
00774   hcec->ErrorCode = hcec->Instance->ISR;
00775   /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
00776   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
00777   {
00778     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
00779     hcec->State = HAL_CEC_STATE_ERROR;
00780   }
00781
00782   /* CEC transmit error interrupt occured --------------------------------------*/
00783   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
00784   {
00785     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
00786     hcec->State = HAL_CEC_STATE_ERROR;
00787   }
00788
00789   /* CEC TX underrun error interrupt occured --------------------------------------*/
00790   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
00791   {
00792     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
00793     hcec->State = HAL_CEC_STATE_ERROR;
00794   }
00795
00796   /* CEC TX arbitration error interrupt occured --------------------------------------*/
00797   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
00798   {
00799     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
00800     hcec->State = HAL_CEC_STATE_ERROR;
00801   }
00802
00803   /* CEC RX overrun error interrupt occured --------------------------------------*/
00804   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
00805   {
00806     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
00807     hcec->State = HAL_CEC_STATE_ERROR;
00808   }
00809
00810   /* CEC RX bit rising error interrupt occured -------------------------------*/
00811   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
00812   {
00813     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
00814     hcec->State = HAL_CEC_STATE_ERROR;
00815   }
00816
00817   /* CEC RX short bit period error interrupt occured -------------------------*/
00818   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
00819   {
00820     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
00821     hcec->State = HAL_CEC_STATE_ERROR;
00822   }
00823
00824   /* CEC RX long bit period error interrupt occured --------------------------*/
00825   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
00826   {
00827     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
00828     hcec->State = HAL_CEC_STATE_ERROR;
00829   }
00830
00831   /* CEC RX missing acknowledge error interrupt occured ----------------------*/
00832   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
00833   {
00834     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
00835     hcec->State = HAL_CEC_STATE_ERROR;
00836   }
00837
00838   if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0U)
00839   {
00840     HAL_CEC_ErrorCallback(hcec);
00841   }
00842
00843   /* CEC RX byte received interrupt  -----------------------------------------*/
00844   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
00845   {
00846     /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
00847     CEC_Receive_IT(hcec);
00848   }
00849
00850   /* CEC RX end received interrupt  ------------------------------------------*/
00851   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
00852   {
00853     /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
00854     CEC_Receive_IT(hcec);
00855   }
00856
00857   /* CEC TX byte request interrupt -------------------------------------------*/
00858   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
00859   {
00860     /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
00861     CEC_Transmit_IT(hcec);
00862   }
00863
00864   /* CEC TX end interrupt ----------------------------------------------------*/
00865   if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
00866   {
00867    /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
00868     CEC_Transmit_IT(hcec);
00869   }
00870 }
00871
00872 /**
00873   * @brief Tx Transfer completed callback
00874   * @param hcec: CEC handle
00875   * @retval None
00876   */
00877  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
00878 {
00879   /* Prevent unused argument(s) compilation warning */
00880   UNUSED(hcec);
00881   /* NOTE : This function should not be modified, when the callback is needed,
00882             the HAL_CEC_TxCpltCallback can be implemented in the user file
00883    */
00884 }
00885
00886 /**
00887   * @brief Rx Transfer completed callback
00888   * @param hcec: CEC handle
00889   * @retval None
00890   */
00891 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
00892 {
00893   /* Prevent unused argument(s) compilation warning */
00894   UNUSED(hcec);
00895   /* NOTE : This function should not be modified, when the callback is needed,
00896             the HAL_CEC_TxCpltCallback can be implemented in the user file
00897    */
00898 }
00899
00900 /**
00901   * @brief CEC error callbacks
00902   * @param hcec: CEC handle
00903   * @retval None
00904   */
00905  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
00906 {
00907   /* Prevent unused argument(s) compilation warning */
00908   UNUSED(hcec);
00909   /* NOTE : This function should not be modified, when the callback is needed,
00910             the HAL_CEC_ErrorCallback can be implemented in the user file
00911    */
00912 }
00913 /**
00914   * @}
00915   */
00916
00917 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
00918   *  @brief   CEC control functions
00919   *
00920 @verbatim
00921  ===============================================================================
00922                       ##### Peripheral Control function #####
00923  ===============================================================================
00924     [..]
00925     This subsection provides a set of functions allowing to control the CEC.
00926      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
00927 @endverbatim
00928   * @{
00929   */
00930 /**
00931   * @brief return the CEC state
00932   * @param hcec: CEC handle
00933   * @retval HAL state
00934   */
00935 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
00936 {
00937   return hcec->State;
00938 }
00939
00940 /**
00941 * @brief  Return the CEC error code
00942 * @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
00943   *              the configuration information for the specified CEC.
00944 * @retval CEC Error Code
00945 */
00946 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
00947 {
00948   return hcec->ErrorCode;
00949 }
00950
00951 /**
00952   * @}
00953   */
00954
00955 /**
00956   * @brief Send data in interrupt mode
00957   * @param hcec: CEC handle.
00958   *         Function called under interruption only, once
00959   *         interruptions have been enabled by HAL_CEC_Transmit_IT()
00960   * @retval HAL status
00961   */
00962 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
00963 {
00964   /* if the IP is already busy or if there is a previous transmission
00965      already pending due to arbitration loss */
00966   if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
00967         || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
00968   {
00969     __HAL_LOCK(hcec);
00970     /* set state to BUSY TX, in case it wasn't set already (case
00971      * of transmission new attempt after arbitration loss) */
00972     if (hcec->State != HAL_CEC_STATE_BUSY_TX)
00973     {
00974       hcec->State = HAL_CEC_STATE_BUSY_TX;
00975     }
00976
00977     /* if all data have been sent */
00978     if(hcec->TxXferCount == 0U)
00979     {
00980       /* Disable Peripheral to write CEC_IER register */
00981       __HAL_CEC_DISABLE(hcec);
00982
00983       /* Disable the CEC Transmission Interrupts */
00984       __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
00985       /* Disable the CEC Transmission Error Interrupts */
00986       __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
00987
00988       /* Enable the Peripheral */
00989       __HAL_CEC_ENABLE(hcec);
00990
00991        __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
00992
00993       hcec->State = HAL_CEC_STATE_READY;
00994       /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
00995       start again the Transmission under the Tx call back API */
00996       __HAL_UNLOCK(hcec);
00997
00998       HAL_CEC_TxCpltCallback(hcec);
00999
01000       return HAL_OK;
01001     }
01002     else
01003     {
01004       if (hcec->TxXferCount == 1U)
01005       {
01006         /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
01007         __HAL_CEC_LAST_BYTE_TX_SET(hcec);
01008       }
01009       /* clear Tx-Byte request flag */
01010        __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
01011        hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
01012       hcec->TxXferCount--;
01013
01014       /* Process Unlocked */
01015       __HAL_UNLOCK(hcec);
01016
01017       return HAL_OK;
01018     }
01019   }
01020   else
01021   {
01022     return HAL_BUSY;
01023   }
01024 }
01025
01026
01027 /**
01028   * @brief Receive data in interrupt mode.
01029   * @param hcec: CEC handle.
01030   *         Function called under interruption only, once
01031   *         interruptions have been enabled by HAL_CEC_Receive_IT()
01032   * @retval HAL status
01033   */
01034 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
01035 {
01036   uint32_t tempisr;
01037
01038   /* Three different conditions are tested to carry out the RX IT processing:
01039    * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
01040    *   the reception of the first byte is starting
01041    * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
01042    *   and a new byte is being received
01043    * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
01044    *   but has been interrupted by a new message reception or discarded due to
01045    *   arbitration loss: the reception of the first or higher priority message
01046    *   (the arbitration winner) is starting */
01047   if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
01048   ||  (hcec->State == HAL_CEC_STATE_BUSY_RX)
01049   ||  (hcec->State == HAL_CEC_STATE_BUSY_TX))
01050   {
01051     /* reception is starting */
01052     hcec->State = HAL_CEC_STATE_BUSY_RX;
01053     tempisr =  (uint32_t) (hcec->Instance->ISR);
01054     if ((tempisr & CEC_FLAG_RXBR) != 0U)
01055     {
01056       /* Process Locked */
01057       __HAL_LOCK(hcec);
01058       /* read received byte */
01059       *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
01060       /* if last byte has been received */
01061       if ((tempisr & CEC_FLAG_RXEND) != 0U)
01062       {
01063         /* clear IT */
01064         __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND);
01065         /* RX interrupts are not disabled at this point.
01066          * Indeed, to disable the IT, the IP must be disabled first
01067          * which resets the TXSOM flag. In case of arbitration loss,
01068          * this leads to a transmission abort.
01069          * Therefore, RX interruptions disabling if so required,
01070          * is done in HAL_CEC_RxCpltCallback */
01071
01072         /* IP state is moved to READY.
01073          * If the IP must remain in standby mode to listen
01074          * any new message, it is up to HAL_CEC_RxCpltCallback
01075          * to move it again to HAL_CEC_STATE_STANDBY_RX */
01076         hcec->State = HAL_CEC_STATE_READY;
01077
01078         /* Call the Process Unlocked before calling the Rx call back API */
01079         __HAL_UNLOCK(hcec);
01080         HAL_CEC_RxCpltCallback(hcec);
01081
01082         return HAL_OK;
01083       }
01084       __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
01085
01086       hcec->RxXferSize++;
01087       /* Process Unlocked */
01088       __HAL_UNLOCK(hcec);
01089
01090       return HAL_OK;
01091     }
01092     else
01093     {
01094       return HAL_BUSY;
01095     }
01096   }
01097   else
01098   {
01099     return HAL_BUSY;
01100   }
01101 }
01102 /**
01103   * @}
01104   */
01105
01106 #endif /* STM32F446xx */
01107
01108 #endif /* HAL_CEC_MODULE_ENABLED */
01109 /**
01110   * @}
01111   */
01112
01113 /**
01114   * @}
01115   */
01116
01117 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cec.h Source File

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stm32f4xx_hal_cec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cec.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of CEC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_CEC_H
00040 #define __STM32F4xx_HAL_CEC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F446xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup CEC
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup CEC_Exported_Types CEC Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief CEC Init Structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
00069                                               It can be one of @ref CEC_Signal_Free_Time
00070                                               and belongs to the set {0,...,7} where
00071                                               0x0 is the default configuration
00072                                               else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
00073
00074   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
00075                                               it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
00076                                               or CEC_EXTENDED_TOLERANCE */
00077
00078   uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
00079                                               CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
00080                                               CEC_RX_STOP_ON_BRE:    reception is stopped. */
00081
00082   uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
00083                                               CEC line upon Bit Rising Error detection.
00084                                               CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
00085                                               CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */
00086
00087   uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
00088                                               CEC line upon Long Bit Period Error detection.
00089                                               CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.
00090                                               CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */
00091
00092   uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
00093                                               upon an error detected on a broadcast message.
00094
00095                                               It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
00096
00097                                               1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
00098                                                  a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
00099                                                     and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
00100                                                  b) LBPE detection: error-bit generation on the CEC line
00101                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
00102
00103                                               2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
00104                                                  no error-bit generation in case neither a) nor b) are satisfied. Additionally,
00105                                                  there is no error-bit generation in case of Short Bit Period Error detection in
00106                                                  a broadcast message while LSTN bit is set. */
00107
00108   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
00109                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
00110                                               CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
00111
00112   uint32_t OwnAddress;                   /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
00113
00114   uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
00115
00116                                               CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
00117                                                 own address (OAR). Messages addressed to different destination are ignored.
00118                                                 Broadcast messages are always received.
00119
00120                                               CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
00121                                                 address (OAR) with positive acknowledge. Messages addressed to different destination
00122                                                 are received, but without interfering with the CEC bus: no acknowledge sent.  */
00123
00124   uint8_t  InitiatorAddress;             /* Initiator address (source logical address, sent in each header) */
00125
00126 }CEC_InitTypeDef;
00127
00128 /**
00129   * @brief HAL CEC State structures definition
00130   */
00131 typedef enum
00132 {
00133   HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral Reset state                              */
00134   HAL_CEC_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use            */
00135   HAL_CEC_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                      */
00136   HAL_CEC_STATE_BUSY_TX           = 0x03U,    /*!< Data Transmission process is ongoing                */
00137   HAL_CEC_STATE_BUSY_RX           = 0x04U,    /*!< Data Reception process is ongoing                   */
00138   HAL_CEC_STATE_STANDBY_RX        = 0x05U,    /*!< IP ready to receive, doesn't prevent IP to transmit */
00139   HAL_CEC_STATE_TIMEOUT           = 0x06U,    /*!< Timeout state                                       */
00140   HAL_CEC_STATE_ERROR             = 0x07U     /*!< State Error                                         */
00141 }HAL_CEC_StateTypeDef;
00142
00143 /**
00144   * @brief  CEC handle Structure definition
00145   */
00146 typedef struct
00147 {
00148   CEC_TypeDef             *Instance;      /* CEC registers base address */
00149
00150   CEC_InitTypeDef         Init;           /* CEC communication parameters */
00151
00152   uint8_t                 *pTxBuffPtr;    /* Pointer to CEC Tx transfer Buffer */
00153
00154   uint16_t                TxXferCount;    /* CEC Tx Transfer Counter */
00155
00156   uint8_t                 *pRxBuffPtr;    /* Pointer to CEC Rx transfer Buffer */
00157
00158   uint16_t                RxXferSize;     /* CEC Rx Transfer size, 0: header received only */
00159
00160   uint32_t                ErrorCode;      /* For errors handling purposes, copy of ISR register
00161                                             in case error is reported */
00162
00163   HAL_LockTypeDef         Lock;           /* Locking object */
00164
00165   HAL_CEC_StateTypeDef    State;          /* CEC communication state */
00166
00167 }CEC_HandleTypeDef;
00168 /**
00169   * @}
00170   */
00171
00172 /* Exported constants --------------------------------------------------------*/
00173 /** @defgroup CEC_Exported_Constants CEC Exported Constants
00174   * @{
00175   */
00176
00177 /** @defgroup CEC_Error_Code CEC Error Code
00178   * @{
00179   */
00180 #define HAL_CEC_ERROR_NONE    ((uint32_t)0x00000000)  /*!< no error                      */
00181 #define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR           /*!< CEC Rx-Overrun                */
00182 #define HAL_CEC_ERROR_BRE     CEC_ISR_BRE             /*!< CEC Rx Bit Rising Error       */
00183 #define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE            /*!< CEC Rx Short Bit period Error */
00184 #define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE            /*!< CEC Rx Long Bit period Error  */
00185 #define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE          /*!< CEC Rx Missing Acknowledge    */
00186 #define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST          /*!< CEC Arbitration Lost          */
00187 #define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR           /*!< CEC Tx-Buffer Underrun        */
00188 #define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR           /*!< CEC Tx-Error                  */
00189 #define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE          /*!< CEC Tx Missing Acknowledge    */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter
00195   * @{
00196   */
00197 #define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000U)
00198 #define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001U)
00199 #define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002U)
00200 #define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003U)
00201 #define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004U)
00202 #define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005U)
00203 #define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006U)
00204 #define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007U)
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
00210   * @{
00211   */
00212 #define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000U)
00213 #define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
00219   * @{
00220   */
00221 #define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000U)
00222 #define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported
00228   * @{
00229   */
00230 #define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00231 #define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported
00237   * @{
00238   */
00239 #define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)
00240 #define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message
00246   * @{
00247   */
00248 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000U)
00249 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup CEC_SFT_Option     CEC Signal Free Time start option
00255   * @{
00256   */
00257 #define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000U)
00258 #define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup CEC_Listening_Mode    CEC Listening mode option
00264   * @{
00265   */
00266 #define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000U)
00267 #define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register
00273   * @{
00274   */
00275 #define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16U)
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header
00281   * @{
00282   */
00283 #define CEC_INITIATOR_LSB_POS           ((uint32_t) 4U)
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition
00289   * @{
00290   */
00291 #define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
00292 #define CEC_IT_TXERR                    CEC_IER_TXERRIE
00293 #define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
00294 #define CEC_IT_TXEND                    CEC_IER_TXENDIE
00295 #define CEC_IT_TXBR                     CEC_IER_TXBRIE
00296 #define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
00297 #define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
00298 #define CEC_IT_LBPE                     CEC_IER_LBPEIE
00299 #define CEC_IT_SBPE                     CEC_IER_SBPEIE
00300 #define CEC_IT_BRE                      CEC_IER_BREIE
00301 #define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
00302 #define CEC_IT_RXEND                    CEC_IER_RXENDIE
00303 #define CEC_IT_RXBR                     CEC_IER_RXBRIE
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup CEC_Flags_Definitions  CEC Flags definition
00309   * @{
00310   */
00311 #define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
00312 #define CEC_FLAG_TXERR                  CEC_ISR_TXERR
00313 #define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
00314 #define CEC_FLAG_TXEND                  CEC_ISR_TXEND
00315 #define CEC_FLAG_TXBR                   CEC_ISR_TXBR
00316 #define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
00317 #define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
00318 #define CEC_FLAG_LBPE                   CEC_ISR_LBPE
00319 #define CEC_FLAG_SBPE                   CEC_ISR_SBPE
00320 #define CEC_FLAG_BRE                    CEC_ISR_BRE
00321 #define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
00322 #define CEC_FLAG_RXEND                  CEC_ISR_RXEND
00323 #define CEC_FLAG_RXBR                   CEC_ISR_RXBR
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
00329   * @{
00330   */
00331 #define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
00332                                                   CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
00338   * @{
00339   */
00340 #define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
00346   * @{
00347   */
00348 #define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
00349 /**
00350   * @}
00351   */
00352
00353 /**
00354   * @}
00355   */
00356
00357 /* Exported macros -----------------------------------------------------------*/
00358 /** @defgroup CEC_Exported_Macros CEC Exported Macros
00359   * @{
00360   */
00361
00362 /** @brief  Reset CEC handle state
00363   * @param  __HANDLE__: CEC handle.
00364   * @retval None
00365   */
00366 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
00367
00368 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
00369   * @param  __HANDLE__: specifies the CEC Handle.
00370   * @param  __FLAG__: specifies the interrupt to check.
00371   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00372   *            @arg CEC_FLAG_TXERR: Tx Error.
00373   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00374   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00375   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00376   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00377   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00378   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00379   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00380   *            @arg CEC_FLAG_BRE: Rx Bit Rissing Error
00381   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00382   *            @arg CEC_FLAG_RXEND: End Of Reception.
00383   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00384   * @retval ITStatus
00385   */
00386 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__))
00387
00388 /** @brief  Clears the interrupt or status flag when raised (write at 1)
00389   * @param  __HANDLE__: specifies the CEC Handle.
00390   * @param  __FLAG__: specifies the interrupt/status flag to clear.
00391   *        This parameter can be one of the following values:
00392   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
00393   *            @arg CEC_FLAG_TXERR: Tx Error.
00394   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
00395   *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
00396   *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
00397   *            @arg CEC_FLAG_ARBLST: Arbitration Lost
00398   *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
00399   *            @arg CEC_FLAG_LBPE: Rx Long period Error
00400   *            @arg CEC_FLAG_SBPE: Rx Short period Error
00401   *            @arg CEC_FLAG_BRE: Rx Bit Rissing Error
00402   *            @arg CEC_FLAG_RXOVR: Rx Overrun.
00403   *            @arg CEC_FLAG_RXEND: End Of Reception.
00404   *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
00405   * @retval none
00406   */
00407 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__))
00408
00409 /** @brief  Enables the specified CEC interrupt.
00410   * @param  __HANDLE__: specifies the CEC Handle.
00411   * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
00412   *          This parameter can be one of the following values:
00413   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00414   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00415   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00416   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00417   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00418   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00419   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00420   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00421   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00422   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00423   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00424   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00425   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00426   * @retval none
00427   */
00428 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00429
00430 /** @brief  Disables the specified CEC interrupt.
00431   * @param  __HANDLE__: specifies the CEC Handle.
00432   * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
00433   *          This parameter can be one of the following values:
00434   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00435   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00436   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00437   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00438   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00439   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00440   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00441   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00442   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00443   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00444   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00445   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00446   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00447   * @retval none
00448   */
00449 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00450
00451 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
00452   * @param  __HANDLE__: specifies the CEC Handle.
00453   * @param  __INTERRUPT__: specifies the CEC interrupt to check.
00454   *          This parameter can be one of the following values:
00455   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
00456   *            @arg CEC_IT_TXERR: Tx Error IT Enable
00457   *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
00458   *            @arg CEC_IT_TXEND: End of transmission IT Enable
00459   *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
00460   *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
00461   *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
00462   *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable
00463   *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable
00464   *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
00465   *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable
00466   *            @arg CEC_IT_RXEND: End Of Reception IT Enable
00467   *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
00468   * @retval FlagStatus
00469   */
00470 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
00471
00472 /** @brief  Enables the CEC device
00473   * @param  __HANDLE__: specifies the CEC Handle.
00474   * @retval none
00475   */
00476 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
00477
00478 /** @brief  Disables the CEC device
00479   * @param  __HANDLE__: specifies the CEC Handle.
00480   * @retval none
00481   */
00482 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
00483
00484 /** @brief  Set Transmission Start flag
00485   * @param  __HANDLE__: specifies the CEC Handle.
00486   * @retval none
00487   */
00488 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
00489
00490 /** @brief  Set Transmission End flag
00491   * @param  __HANDLE__: specifies the CEC Handle.
00492   * @retval none
00493   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
00494   */
00495 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
00496
00497 /** @brief  Get Transmission Start flag
00498   * @param  __HANDLE__: specifies the CEC Handle.
00499   * @retval FlagStatus
00500   */
00501 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
00502
00503 /** @brief  Get Transmission End flag
00504   * @param  __HANDLE__: specifies the CEC Handle.
00505   * @retval FlagStatus
00506   */
00507 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
00508
00509 /** @brief  Clear OAR register
00510   * @param  __HANDLE__: specifies the CEC Handle.
00511   * @retval none
00512   */
00513 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
00514
00515 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
00516   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
00517   * @param  __HANDLE__: specifies the CEC Handle.
00518   * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
00519   * @retval none
00520   */
00521 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__) << CEC_CFGR_OAR_LSB_POS)
00522
00523 /**
00524   * @}
00525   */
00526
00527 /* Exported functions --------------------------------------------------------*/
00528 /** @addtogroup CEC_Exported_Functions
00529   * @{
00530   */
00531
00532 /** @addtogroup CEC_Exported_Functions_Group1
00533   * @{
00534   */
00535 /* Initialization and de-initialization functions  ****************************/
00536 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
00537 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
00538 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
00539 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
00540 /**
00541   * @}
00542   */
00543
00544 /** @addtogroup CEC_Exported_Functions_Group2
00545   * @{
00546   */
00547 /* I/O operation functions  ***************************************************/
00548 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
00549 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
00550 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
00551 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
00552 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
00553 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
00554 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
00555 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
00556 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
00557 /**
00558   * @}
00559   */
00560
00561 /** @addtogroup CEC_Exported_Functions_Group3
00562   * @{
00563   */
00564 /* Peripheral State functions  ************************************************/
00565 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
00566 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
00567 /**
00568   * @}
00569   */
00570
00571 /**
00572   * @}
00573   */
00574
00575 /* Private types -------------------------------------------------------------*/
00576 /** @defgroup CEC_Private_Types CEC Private Types
00577   * @{
00578   */
00579
00580 /**
00581   * @}
00582   */
00583
00584 /* Private variables ---------------------------------------------------------*/
00585 /** @defgroup CEC_Private_Variables CEC Private Variables
00586   * @{
00587   */
00588
00589 /**
00590   * @}
00591   */
00592
00593 /* Private constants ---------------------------------------------------------*/
00594 /** @defgroup CEC_Private_Constants CEC Private Constants
00595   * @{
00596   */
00597
00598 /**
00599   * @}
00600   */
00601
00602 /* Private macros ------------------------------------------------------------*/
00603 /** @defgroup CEC_Private_Macros CEC Private Macros
00604   * @{
00605   */
00606
00607 #define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)
00608
00609 #define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
00610                                             ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
00611
00612 #define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
00613                                            ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
00614
00615 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
00616                                                 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
00617
00618 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
00619                                                  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
00620
00621 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
00622                                                                        ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
00623
00624 #define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
00625                                           ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
00626
00627 #define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
00628                                              ((__MODE__) == CEC_FULL_LISTENING_MODE))
00629
00630 /** @brief Check CEC device Own Address Register (OAR) setting.
00631   *        OAR address is written in a 15-bit field within CEC_CFGR register.
00632   * @param  __ADDRESS__: CEC own address.
00633   * @retval Test result (TRUE or FALSE).
00634   */
00635 #define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFFU)
00636
00637 /** @brief Check CEC initiator or destination logical address setting.
00638   *        Initiator and destination addresses are coded over 4 bits.
00639   * @param  __ADDRESS__: CEC initiator or logical address.
00640   * @retval Test result (TRUE or FALSE).
00641   */
00642 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
00643
00644 /** @brief Check CEC message size.
00645   *       The message size is the payload size: without counting the header,
00646   *       it varies from 0 byte (ping operation, one header only, no payload) to
00647   *       15 bytes (1 opcode and up to 14 operands following the header).
00648   * @param  __SIZE__: CEC message size.
00649   * @retval Test result (TRUE or FALSE).
00650   */
00651 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xFU)
00652
00653 /**
00654   * @}
00655   */
00656
00657 /* Private functions ---------------------------------------------------------*/
00658 /** @defgroup CEC_Private_Functions CEC Private Functions
00659   * @{
00660   */
00661
00662 /**
00663   * @}
00664   */
00665
00666 /**
00667   * @}
00668   */
00669
00670 /**
00671   * @}
00672   */
00673 #endif /* STM32F446xx */
00674
00675 #ifdef __cplusplus
00676 }
00677 #endif
00678
00679 #endif /* __STM32F4xx_HAL_CEC_H */
00680
00681 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_conf.h Source File

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stm32f4xx_hal_conf.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_conf_template.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   HAL configuration template file.
00008   *          This file should be copied to the application folder and renamed
00009   *          to stm32f4xx_hal_conf.h.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Define to prevent recursive inclusion -------------------------------------*/
00041 #ifndef __STM32F4xx_HAL_CONF_H
00042 #define __STM32F4xx_HAL_CONF_H
00043
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047
00048 /* Exported types ------------------------------------------------------------*/
00049 /* Exported constants --------------------------------------------------------*/
00050
00051 /* ########################## Module Selection ############################## */
00052 /**
00053   * @brief This is the list of modules to be used in the HAL driver
00054   */
00055 #define HAL_MODULE_ENABLED
00056 #define HAL_ADC_MODULE_ENABLED
00057 #define HAL_CAN_MODULE_ENABLED
00058 #define HAL_CRC_MODULE_ENABLED
00059 #define HAL_CEC_MODULE_ENABLED
00060 #define HAL_CRYP_MODULE_ENABLED
00061 #define HAL_DAC_MODULE_ENABLED
00062 #define HAL_DCMI_MODULE_ENABLED
00063 #define HAL_DMA_MODULE_ENABLED
00064 #define HAL_DMA2D_MODULE_ENABLED
00065 #define HAL_ETH_MODULE_ENABLED
00066 #define HAL_FLASH_MODULE_ENABLED
00067 #define HAL_NAND_MODULE_ENABLED
00068 #define HAL_NOR_MODULE_ENABLED
00069 #define HAL_PCCARD_MODULE_ENABLED
00070 #define HAL_SRAM_MODULE_ENABLED
00071 #define HAL_SDRAM_MODULE_ENABLED
00072 #define HAL_HASH_MODULE_ENABLED
00073 #define HAL_GPIO_MODULE_ENABLED
00074 #define HAL_I2C_MODULE_ENABLED
00075 #define HAL_I2S_MODULE_ENABLED
00076 #define HAL_IWDG_MODULE_ENABLED
00077 #define HAL_LTDC_MODULE_ENABLED
00078 #define HAL_DSI_MODULE_ENABLED
00079 #define HAL_PWR_MODULE_ENABLED
00080 #define HAL_QSPI_MODULE_ENABLED
00081 #define HAL_RCC_MODULE_ENABLED
00082 #define HAL_RNG_MODULE_ENABLED
00083 #define HAL_RTC_MODULE_ENABLED
00084 #define HAL_SAI_MODULE_ENABLED
00085 #define HAL_SD_MODULE_ENABLED
00086 #define HAL_SPI_MODULE_ENABLED
00087 #define HAL_TIM_MODULE_ENABLED
00088 #define HAL_UART_MODULE_ENABLED
00089 #define HAL_USART_MODULE_ENABLED
00090 #define HAL_IRDA_MODULE_ENABLED
00091 #define HAL_SMARTCARD_MODULE_ENABLED
00092 #define HAL_WWDG_MODULE_ENABLED
00093 #define HAL_CORTEX_MODULE_ENABLED
00094 #define HAL_PCD_MODULE_ENABLED
00095 #define HAL_HCD_MODULE_ENABLED
00096 #define HAL_FMPI2C_MODULE_ENABLED
00097 #define HAL_SPDIFRX_MODULE_ENABLED
00098 #define HAL_LPTIM_MODULE_ENABLED
00099
00100 /* ########################## HSE/HSI Values adaptation ##################### */
00101 /**
00102   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00103   *        This value is used by the RCC HAL module to compute the system frequency
00104   *        (when HSE is used as system clock source, directly or through the PLL).
00105   */
00106 #if !defined  (HSE_VALUE)
00107   #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
00108 #endif /* HSE_VALUE */
00109
00110 #if !defined  (HSE_STARTUP_TIMEOUT)
00111   #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
00112 #endif /* HSE_STARTUP_TIMEOUT */
00113
00114 /**
00115   * @brief Internal High Speed oscillator (HSI) value.
00116   *        This value is used by the RCC HAL module to compute the system frequency
00117   *        (when HSI is used as system clock source, directly or through the PLL).
00118   */
00119 #if !defined  (HSI_VALUE)
00120   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
00121 #endif /* HSI_VALUE */
00122
00123 /**
00124   * @brief Internal Low Speed oscillator (LSI) value.
00125   */
00126 #if !defined  (LSI_VALUE)
00127  #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
00128 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00129                                              The real value may vary depending on the variations
00130                                              in voltage and temperature.*/
00131 /**
00132   * @brief External Low Speed oscillator (LSE) value.
00133   */
00134 #if !defined  (LSE_VALUE)
00135  #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
00136 #endif /* LSE_VALUE */
00137
00138 #if !defined  (LSE_STARTUP_TIMEOUT)
00139   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
00140 #endif /* LSE_STARTUP_TIMEOUT */
00141
00142 /**
00143   * @brief External clock source for I2S peripheral
00144   *        This value is used by the I2S HAL module to compute the I2S clock source
00145   *        frequency, this source is inserted directly through I2S_CKIN pad.
00146   */
00147 #if !defined  (EXTERNAL_CLOCK_VALUE)
00148   #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
00149 #endif /* EXTERNAL_CLOCK_VALUE */
00150
00151 /* Tip: To avoid modifying this file each time you need to use different HSE,
00152    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00153
00154 /* ########################### System Configuration ######################### */
00155 /**
00156   * @brief This is the HAL system configuration section
00157   */
00158 #define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
00159 #define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
00160 #define  USE_RTOS                     0U
00161 #define  PREFETCH_ENABLE              1U
00162 #define  INSTRUCTION_CACHE_ENABLE     1U
00163 #define  DATA_CACHE_ENABLE            1U
00164
00165 /* ########################## Assert Selection ############################## */
00166 /**
00167   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00168   *        HAL drivers code
00169   */
00170 /* #define USE_FULL_ASSERT    1U */
00171
00172 /* ################## Ethernet peripheral configuration ##################### */
00173
00174 /* Section 1 : Ethernet peripheral configuration */
00175
00176 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
00177 #define MAC_ADDR0   2U
00178 #define MAC_ADDR1   0U
00179 #define MAC_ADDR2   0U
00180 #define MAC_ADDR3   0U
00181 #define MAC_ADDR4   0U
00182 #define MAC_ADDR5   0U
00183
00184 /* Definition of the Ethernet driver buffers size and count */
00185 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
00186 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
00187 #define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
00188 #define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
00189
00190 /* Section 2: PHY configuration section */
00191
00192 /* DP83848 PHY Address*/
00193 #define DP83848_PHY_ADDRESS             0x01U
00194 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
00195 #define PHY_RESET_DELAY                 ((uint32_t)0x000000FFU)
00196 /* PHY Configuration delay */
00197 #define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
00198
00199 #define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
00200 #define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
00201
00202 /* Section 3: Common PHY Registers */
00203
00204 #define PHY_BCR                         ((uint16_t)0x0000U)  /*!< Transceiver Basic Control Register   */
00205 #define PHY_BSR                         ((uint16_t)0x0001U)  /*!< Transceiver Basic Status Register    */
00206
00207 #define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
00208 #define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
00209 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
00210 #define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
00211 #define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
00212 #define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
00213 #define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
00214 #define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
00215 #define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
00216 #define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
00217
00218 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
00219 #define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
00220 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
00221
00222 /* Section 4: Extended PHY Registers */
00223
00224 #define PHY_SR                          ((uint16_t)0x0010U)  /*!< PHY status register Offset                      */
00225 #define PHY_MICR                        ((uint16_t)0x0011U)  /*!< MII Interrupt Control Register                  */
00226 #define PHY_MISR                        ((uint16_t)0x0012U)  /*!< MII Interrupt Status and Misc. Control Register */
00227
00228 #define PHY_LINK_STATUS                 ((uint16_t)0x0001U)  /*!< PHY Link mask                                   */
00229 #define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
00230 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
00231
00232 #define PHY_MICR_INT_EN                 ((uint16_t)0x0002U)  /*!< PHY Enable interrupts                           */
00233 #define PHY_MICR_INT_OE                 ((uint16_t)0x0001U)  /*!< PHY Enable output interrupt events              */
00234
00235 #define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020U)  /*!< Enable Interrupt on change of link status       */
00236 #define PHY_LINK_INTERRUPT              ((uint16_t)0x2000U)  /*!< PHY link status interrupt mask                  */
00237
00238 /* Includes ------------------------------------------------------------------*/
00239 /**
00240   * @brief Include module's header file
00241   */
00242
00243 #ifdef HAL_RCC_MODULE_ENABLED
00244   #include "stm32f4xx_hal_rcc.h"
00245 #endif /* HAL_RCC_MODULE_ENABLED */
00246
00247 #ifdef HAL_GPIO_MODULE_ENABLED
00248   #include "stm32f4xx_hal_gpio.h"
00249 #endif /* HAL_GPIO_MODULE_ENABLED */
00250
00251 #ifdef HAL_DMA_MODULE_ENABLED
00252   #include "stm32f4xx_hal_dma.h"
00253 #endif /* HAL_DMA_MODULE_ENABLED */
00254
00255 #ifdef HAL_CORTEX_MODULE_ENABLED
00256   #include "stm32f4xx_hal_cortex.h"
00257 #endif /* HAL_CORTEX_MODULE_ENABLED */
00258
00259 #ifdef HAL_ADC_MODULE_ENABLED
00260   #include "stm32f4xx_hal_adc.h"
00261 #endif /* HAL_ADC_MODULE_ENABLED */
00262
00263 #ifdef HAL_CAN_MODULE_ENABLED
00264   #include "stm32f4xx_hal_can.h"
00265 #endif /* HAL_CAN_MODULE_ENABLED */
00266
00267 #ifdef HAL_CRC_MODULE_ENABLED
00268   #include "stm32f4xx_hal_crc.h"
00269 #endif /* HAL_CRC_MODULE_ENABLED */
00270
00271 #ifdef HAL_CRYP_MODULE_ENABLED
00272   #include "stm32f4xx_hal_cryp.h"
00273 #endif /* HAL_CRYP_MODULE_ENABLED */
00274
00275 #ifdef HAL_DMA2D_MODULE_ENABLED
00276   #include "stm32f4xx_hal_dma2d.h"
00277 #endif /* HAL_DMA2D_MODULE_ENABLED */
00278
00279 #ifdef HAL_DAC_MODULE_ENABLED
00280   #include "stm32f4xx_hal_dac.h"
00281 #endif /* HAL_DAC_MODULE_ENABLED */
00282
00283 #ifdef HAL_DCMI_MODULE_ENABLED
00284   #include "stm32f4xx_hal_dcmi.h"
00285 #endif /* HAL_DCMI_MODULE_ENABLED */
00286
00287 #ifdef HAL_ETH_MODULE_ENABLED
00288   #include "stm32f4xx_hal_eth.h"
00289 #endif /* HAL_ETH_MODULE_ENABLED */
00290
00291 #ifdef HAL_FLASH_MODULE_ENABLED
00292   #include "stm32f4xx_hal_flash.h"
00293 #endif /* HAL_FLASH_MODULE_ENABLED */
00294
00295 #ifdef HAL_SRAM_MODULE_ENABLED
00296   #include "stm32f4xx_hal_sram.h"
00297 #endif /* HAL_SRAM_MODULE_ENABLED */
00298
00299 #ifdef HAL_NOR_MODULE_ENABLED
00300   #include "stm32f4xx_hal_nor.h"
00301 #endif /* HAL_NOR_MODULE_ENABLED */
00302
00303 #ifdef HAL_NAND_MODULE_ENABLED
00304   #include "stm32f4xx_hal_nand.h"
00305 #endif /* HAL_NAND_MODULE_ENABLED */
00306
00307 #ifdef HAL_PCCARD_MODULE_ENABLED
00308   #include "stm32f4xx_hal_pccard.h"
00309 #endif /* HAL_PCCARD_MODULE_ENABLED */
00310
00311 #ifdef HAL_SDRAM_MODULE_ENABLED
00312   #include "stm32f4xx_hal_sdram.h"
00313 #endif /* HAL_SDRAM_MODULE_ENABLED */
00314
00315 #ifdef HAL_HASH_MODULE_ENABLED
00316  #include "stm32f4xx_hal_hash.h"
00317 #endif /* HAL_HASH_MODULE_ENABLED */
00318
00319 #ifdef HAL_I2C_MODULE_ENABLED
00320  #include "stm32f4xx_hal_i2c.h"
00321 #endif /* HAL_I2C_MODULE_ENABLED */
00322
00323 #ifdef HAL_I2S_MODULE_ENABLED
00324  #include "stm32f4xx_hal_i2s.h"
00325 #endif /* HAL_I2S_MODULE_ENABLED */
00326
00327 #ifdef HAL_IWDG_MODULE_ENABLED
00328  #include "stm32f4xx_hal_iwdg.h"
00329 #endif /* HAL_IWDG_MODULE_ENABLED */
00330
00331 #ifdef HAL_LTDC_MODULE_ENABLED
00332  #include "stm32f4xx_hal_ltdc.h"
00333 #endif /* HAL_LTDC_MODULE_ENABLED */
00334
00335 #ifdef HAL_PWR_MODULE_ENABLED
00336  #include "stm32f4xx_hal_pwr.h"
00337 #endif /* HAL_PWR_MODULE_ENABLED */
00338
00339 #ifdef HAL_RNG_MODULE_ENABLED
00340  #include "stm32f4xx_hal_rng.h"
00341 #endif /* HAL_RNG_MODULE_ENABLED */
00342
00343 #ifdef HAL_RTC_MODULE_ENABLED
00344  #include "stm32f4xx_hal_rtc.h"
00345 #endif /* HAL_RTC_MODULE_ENABLED */
00346
00347 #ifdef HAL_SAI_MODULE_ENABLED
00348  #include "stm32f4xx_hal_sai.h"
00349 #endif /* HAL_SAI_MODULE_ENABLED */
00350
00351 #ifdef HAL_SD_MODULE_ENABLED
00352  #include "stm32f4xx_hal_sd.h"
00353 #endif /* HAL_SD_MODULE_ENABLED */
00354
00355 #ifdef HAL_SPI_MODULE_ENABLED
00356  #include "stm32f4xx_hal_spi.h"
00357 #endif /* HAL_SPI_MODULE_ENABLED */
00358
00359 #ifdef HAL_TIM_MODULE_ENABLED
00360  #include "stm32f4xx_hal_tim.h"
00361 #endif /* HAL_TIM_MODULE_ENABLED */
00362
00363 #ifdef HAL_UART_MODULE_ENABLED
00364  #include "stm32f4xx_hal_uart.h"
00365 #endif /* HAL_UART_MODULE_ENABLED */
00366
00367 #ifdef HAL_USART_MODULE_ENABLED
00368  #include "stm32f4xx_hal_usart.h"
00369 #endif /* HAL_USART_MODULE_ENABLED */
00370
00371 #ifdef HAL_IRDA_MODULE_ENABLED
00372  #include "stm32f4xx_hal_irda.h"
00373 #endif /* HAL_IRDA_MODULE_ENABLED */
00374
00375 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00376  #include "stm32f4xx_hal_smartcard.h"
00377 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00378
00379 #ifdef HAL_WWDG_MODULE_ENABLED
00380  #include "stm32f4xx_hal_wwdg.h"
00381 #endif /* HAL_WWDG_MODULE_ENABLED */
00382
00383 #ifdef HAL_PCD_MODULE_ENABLED
00384  #include "stm32f4xx_hal_pcd.h"
00385 #endif /* HAL_PCD_MODULE_ENABLED */
00386
00387 #ifdef HAL_HCD_MODULE_ENABLED
00388  #include "stm32f4xx_hal_hcd.h"
00389 #endif /* HAL_HCD_MODULE_ENABLED */
00390
00391 #ifdef HAL_DSI_MODULE_ENABLED
00392  #include "stm32f4xx_hal_dsi.h"
00393 #endif /* HAL_DSI_MODULE_ENABLED */
00394
00395 #ifdef HAL_QSPI_MODULE_ENABLED
00396  #include "stm32f4xx_hal_qspi.h"
00397 #endif /* HAL_QSPI_MODULE_ENABLED */
00398
00399 #ifdef HAL_CEC_MODULE_ENABLED
00400  #include "stm32f4xx_hal_cec.h"
00401 #endif /* HAL_CEC_MODULE_ENABLED */
00402
00403 #ifdef HAL_FMPI2C_MODULE_ENABLED
00404  #include "stm32f4xx_hal_fmpi2c.h"
00405 #endif /* HAL_FMPI2C_MODULE_ENABLED */
00406
00407 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00408  #include "stm32f4xx_hal_spdifrx.h"
00409 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
00410
00411 #ifdef HAL_LPTIM_MODULE_ENABLED
00412  #include "stm32f4xx_hal_lptim.h"
00413 #endif /* HAL_LPTIM_MODULE_ENABLED */
00414
00415 /* Exported macro ------------------------------------------------------------*/
00416 #ifdef  USE_FULL_ASSERT
00417 /**
00418   * @brief  The assert_param macro is used for function's parameters check.
00419   * @param  expr: If expr is false, it calls assert_failed function
00420   *         which reports the name of the source file and the source
00421   *         line number of the call that failed.
00422   *         If expr is true, it returns no value.
00423   * @retval None
00424   */
00425   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
00426 /* Exported functions ------------------------------------------------------- */
00427   void assert_failed(uint8_t* file, uint32_t line);
00428 #else
00429   #define assert_param(expr) ((void)0)
00430 #endif /* USE_FULL_ASSERT */
00431
00432
00433 #ifdef __cplusplus
00434 }
00435 #endif
00436
00437 #endif /* __STM32F4xx_HAL_CONF_H */
00438
00439
00440 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cortex.c Source File

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stm32f4xx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   CORTEX HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the CORTEX:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017
00018     [..]
00019     *** How to configure Interrupts using CORTEX HAL driver ***
00020     ===========================================================
00021     [..]
00022     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00023     The Cortex-M4 exceptions are managed by CMSIS functions.
00024
00025     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
00026         function according to the following table.
00027     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
00028     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
00029     (#) please refer to programing manual for details in how to configure priority.
00030
00031      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
00032          The pending IRQ priority will be managed only by the sub priority.
00033
00034      -@- IRQ priority order (sorted by highest to lowest priority):
00035         (+@) Lowest preemption priority
00036         (+@) Lowest sub priority
00037         (+@) Lowest hardware priority (IRQ number)
00038
00039     [..]
00040     *** How to configure Systick using CORTEX HAL driver ***
00041     ========================================================
00042     [..]
00043     Setup SysTick Timer for time base.
00044
00045    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
00046        is a CMSIS function that:
00047         (++) Configures the SysTick Reload register with value passed as function parameter.
00048         (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
00049         (++) Resets the SysTick Counter register.
00050         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00051         (++) Enables the SysTick Interrupt.
00052         (++) Starts the SysTick Counter.
00053
00054    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00055        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00056        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00057        inside the stm32f4xx_hal_cortex.h file.
00058
00059    (+) You can change the SysTick IRQ priority by calling the
00060        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00061        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00062
00063    (+) To adjust the SysTick time base, use the following formula:
00064
00065        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00066        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00067        (++) Reload Value should not exceed 0xFFFFFF
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f4xx_hal.h"
00102
00103 /** @addtogroup STM32F4xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup CORTEX CORTEX
00108   * @brief CORTEX HAL module driver
00109   * @{
00110   */
00111
00112 #ifdef HAL_CORTEX_MODULE_ENABLED
00113
00114 /* Private types -------------------------------------------------------------*/
00115 /* Private variables ---------------------------------------------------------*/
00116 /* Private constants ---------------------------------------------------------*/
00117 /* Private macros ------------------------------------------------------------*/
00118 /* Private functions ---------------------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120
00121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00122   * @{
00123   */
00124
00125
00126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
00127  *  @brief    Initialization and Configuration functions
00128  *
00129 @verbatim
00130   ==============================================================================
00131               ##### Initialization and de-initialization functions #####
00132   ==============================================================================
00133     [..]
00134       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00135       Systick functionalities
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141
00142 /**
00143   * @brief  Sets the priority grouping field (preemption priority and subpriority)
00144   *         using the required unlock sequence.
00145   * @param  PriorityGroup: The priority grouping bits length.
00146   *         This parameter can be one of the following values:
00147   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00148   *                                    4 bits for subpriority
00149   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00150   *                                    3 bits for subpriority
00151   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00152   *                                    2 bits for subpriority
00153   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00154   *                                    1 bits for subpriority
00155   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00156   *                                    0 bits for subpriority
00157   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
00158   *         The pending IRQ priority will be managed only by the subpriority.
00159   * @retval None
00160   */
00161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00162 {
00163   /* Check the parameters */
00164   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00165
00166   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00167   NVIC_SetPriorityGrouping(PriorityGroup);
00168 }
00169
00170 /**
00171   * @brief  Sets the priority of an interrupt.
00172   * @param  IRQn: External interrupt number.
00173   *         This parameter can be an enumerator of IRQn_Type enumeration
00174   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00175   * @param  PreemptPriority: The preemption priority for the IRQn channel.
00176   *         This parameter can be a value between 0 and 15
00177   *         A lower priority value indicates a higher priority
00178   * @param  SubPriority: the subpriority level for the IRQ channel.
00179   *         This parameter can be a value between 0 and 15
00180   *         A lower priority value indicates a higher priority.
00181   * @retval None
00182   */
00183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00184 {
00185   uint32_t prioritygroup = 0x00U;
00186
00187   /* Check the parameters */
00188   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00189   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00190
00191   prioritygroup = NVIC_GetPriorityGrouping();
00192
00193   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00194 }
00195
00196 /**
00197   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
00198   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00199   *         function should be called before.
00200   * @param  IRQn External interrupt number.
00201   *         This parameter can be an enumerator of IRQn_Type enumeration
00202   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00203   * @retval None
00204   */
00205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00206 {
00207   /* Check the parameters */
00208   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00209
00210   /* Enable interrupt */
00211   NVIC_EnableIRQ(IRQn);
00212 }
00213
00214 /**
00215   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
00216   * @param  IRQn External interrupt number.
00217   *         This parameter can be an enumerator of IRQn_Type enumeration
00218   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00219   * @retval None
00220   */
00221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00222 {
00223   /* Check the parameters */
00224   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00225
00226   /* Disable interrupt */
00227   NVIC_DisableIRQ(IRQn);
00228 }
00229
00230 /**
00231   * @brief  Initiates a system reset request to reset the MCU.
00232   * @retval None
00233   */
00234 void HAL_NVIC_SystemReset(void)
00235 {
00236   /* System Reset */
00237   NVIC_SystemReset();
00238 }
00239
00240 /**
00241   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
00242   *         Counter is in free running mode to generate periodic interrupts.
00243   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
00244   * @retval status:  - 0  Function succeeded.
00245   *                  - 1  Function failed.
00246   */
00247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00248 {
00249    return SysTick_Config(TicksNumb);
00250 }
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00256  *  @brief   Cortex control functions
00257  *
00258 @verbatim
00259   ==============================================================================
00260                       ##### Peripheral Control functions #####
00261   ==============================================================================
00262     [..]
00263       This subsection provides a set of functions allowing to control the CORTEX
00264       (NVIC, SYSTICK, MPU) functionalities.
00265
00266
00267 @endverbatim
00268   * @{
00269   */
00270
00271 #if (__MPU_PRESENT == 1U)
00272 /**
00273   * @brief  Initializes and configures the Region and the memory to be protected.
00274   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
00275   *                the initialization and configuration information.
00276   * @retval None
00277   */
00278 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00279 {
00280   /* Check the parameters */
00281   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00282   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00283
00284   /* Set the Region number */
00285   MPU->RNR = MPU_Init->Number;
00286
00287   if ((MPU_Init->Enable) != RESET)
00288   {
00289     /* Check the parameters */
00290     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00291     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00292     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00293     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00294     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00295     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00296     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00297     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00298
00299     MPU->RBAR = MPU_Init->BaseAddress;
00300     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00301                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00302                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00303                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00304                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00305                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00306                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00307                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00308                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00309   }
00310   else
00311   {
00312     MPU->RBAR = 0x00U;
00313     MPU->RASR = 0x00U;
00314   }
00315 }
00316 #endif /* __MPU_PRESENT */
00317
00318 /**
00319   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
00320   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00321   */
00322 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00323 {
00324   /* Get the PRIGROUP[10:8] field value */
00325   return NVIC_GetPriorityGrouping();
00326 }
00327
00328 /**
00329   * @brief  Gets the priority of an interrupt.
00330   * @param  IRQn: External interrupt number.
00331   *         This parameter can be an enumerator of IRQn_Type enumeration
00332   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00333   * @param   PriorityGroup: the priority grouping bits length.
00334   *         This parameter can be one of the following values:
00335   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00336   *                                      4 bits for subpriority
00337   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00338   *                                      3 bits for subpriority
00339   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00340   *                                      2 bits for subpriority
00341   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00342   *                                      1 bits for subpriority
00343   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00344   *                                      0 bits for subpriority
00345   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
00346   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
00347   * @retval None
00348   */
00349 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00350 {
00351   /* Check the parameters */
00352   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00353  /* Get priority for Cortex-M system or device specific interrupts */
00354   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00355 }
00356
00357 /**
00358   * @brief  Sets Pending bit of an external interrupt.
00359   * @param  IRQn External interrupt number
00360   *         This parameter can be an enumerator of IRQn_Type enumeration
00361   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00362   * @retval None
00363   */
00364 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00365 {
00366   /* Check the parameters */
00367   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00368
00369   /* Set interrupt pending */
00370   NVIC_SetPendingIRQ(IRQn);
00371 }
00372
00373 /**
00374   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
00375   *         and returns the pending bit for the specified interrupt).
00376   * @param  IRQn External interrupt number.
00377   *          This parameter can be an enumerator of IRQn_Type enumeration
00378   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00379   * @retval status: - 0  Interrupt status is not pending.
00380   *                 - 1  Interrupt status is pending.
00381   */
00382 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00383 {
00384   /* Check the parameters */
00385   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00386
00387   /* Return 1 if pending else 0 */
00388   return NVIC_GetPendingIRQ(IRQn);
00389 }
00390
00391 /**
00392   * @brief  Clears the pending bit of an external interrupt.
00393   * @param  IRQn External interrupt number.
00394   *         This parameter can be an enumerator of IRQn_Type enumeration
00395   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00396   * @retval None
00397   */
00398 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00399 {
00400   /* Check the parameters */
00401   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00402
00403   /* Clear pending interrupt */
00404   NVIC_ClearPendingIRQ(IRQn);
00405 }
00406
00407 /**
00408   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
00409   * @param IRQn External interrupt number
00410   *         This parameter can be an enumerator of IRQn_Type enumeration
00411   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
00412   * @retval status: - 0  Interrupt status is not pending.
00413   *                 - 1  Interrupt status is pending.
00414   */
00415 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00416 {
00417   /* Check the parameters */
00418   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00419
00420   /* Return 1 if active else 0 */
00421   return NVIC_GetActive(IRQn);
00422 }
00423
00424 /**
00425   * @brief  Configures the SysTick clock source.
00426   * @param  CLKSource: specifies the SysTick clock source.
00427   *          This parameter can be one of the following values:
00428   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00429   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00430   * @retval None
00431   */
00432 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00433 {
00434   /* Check the parameters */
00435   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00436   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00437   {
00438     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00439   }
00440   else
00441   {
00442     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00443   }
00444 }
00445
00446 /**
00447   * @brief  This function handles SYSTICK interrupt request.
00448   * @retval None
00449   */
00450 void HAL_SYSTICK_IRQHandler(void)
00451 {
00452   HAL_SYSTICK_Callback();
00453 }
00454
00455 /**
00456   * @brief  SYSTICK callback.
00457   * @retval None
00458   */
00459 __weak void HAL_SYSTICK_Callback(void)
00460 {
00461   /* NOTE : This function Should not be modified, when the callback is needed,
00462             the HAL_SYSTICK_Callback could be implemented in the user file
00463    */
00464 }
00465
00466 /**
00467   * @}
00468   */
00469
00470 /**
00471   * @}
00472   */
00473
00474 #endif /* HAL_CORTEX_MODULE_ENABLED */
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cortex.h Source File

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stm32f4xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of CORTEX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_CORTEX_H
00040 #define __STM32F4xx_HAL_CORTEX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CORTEX
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
00058   * @{
00059   */
00060
00061 #if (__MPU_PRESENT == 1)
00062 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00063   * @brief  MPU Region initialization structure
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint8_t                Enable;                /*!< Specifies the status of the region.
00069                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00070   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00071                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00072   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00073   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00074                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00075   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00076                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00077   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00078                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00079   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00080                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00081   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00082                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00083   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00084                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00085   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00086                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00087   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00088                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00089 }MPU_Region_InitTypeDef;
00090 /**
00091   * @}
00092   */
00093 #endif /* __MPU_PRESENT */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100
00101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00106   * @{
00107   */
00108 #define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
00109                                                                  4 bits for subpriority */
00110 #define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
00111                                                                  3 bits for subpriority */
00112 #define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
00113                                                                  2 bits for subpriority */
00114 #define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
00115                                                                  1 bits for subpriority */
00116 #define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
00117                                                                  0 bits for subpriority */
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
00123   * @{
00124   */
00125 #define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000U)
00126 #define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004U)
00127
00128 /**
00129   * @}
00130   */
00131
00132 #if (__MPU_PRESENT == 1)
00133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
00134   * @{
00135   */
00136 #define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000U)
00137 #define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002U)
00138 #define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004U)
00139 #define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006U)
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00145   * @{
00146   */
00147 #define  MPU_REGION_ENABLE     ((uint8_t)0x01U)
00148 #define  MPU_REGION_DISABLE    ((uint8_t)0x00U)
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00154   * @{
00155   */
00156 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)
00157 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00163   * @{
00164   */
00165 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)
00166 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00172   * @{
00173   */
00174 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)
00175 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00181   * @{
00182   */
00183 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)
00184 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
00190   * @{
00191   */
00192 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)
00193 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)
00194 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00200   * @{
00201   */
00202 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
00203 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
00204 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
00205 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
00206 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
00207 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
00208 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
00209 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
00210 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
00211 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
00212 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
00213 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
00214 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
00215 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
00216 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
00217 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
00218 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
00219 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
00220 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
00221 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
00222 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
00223 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
00224 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
00225 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
00226 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
00227 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
00228 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
00229 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00235   * @{
00236   */
00237 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)
00238 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U)
00239 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)
00240 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)
00241 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U)
00242 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00248   * @{
00249   */
00250 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)
00251 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01U)
00252 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)
00253 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)
00254 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04U)
00255 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)
00256 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)
00257 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)
00258 /**
00259   * @}
00260   */
00261 #endif /* __MPU_PRESENT */
00262
00263 /**
00264   * @}
00265   */
00266
00267
00268 /* Exported Macros -----------------------------------------------------------*/
00269
00270 /* Exported functions --------------------------------------------------------*/
00271 /** @addtogroup CORTEX_Exported_Functions
00272   * @{
00273   */
00274
00275 /** @addtogroup CORTEX_Exported_Functions_Group1
00276  * @{
00277  */
00278 /* Initialization and de-initialization functions *****************************/
00279 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00280 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00281 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00282 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00283 void HAL_NVIC_SystemReset(void);
00284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00285 /**
00286   * @}
00287   */
00288
00289 /** @addtogroup CORTEX_Exported_Functions_Group2
00290  * @{
00291  */
00292 /* Peripheral Control functions ***********************************************/
00293 #if (__MPU_PRESENT == 1)
00294 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00295 #endif /* __MPU_PRESENT */
00296 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00297 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00298 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00299 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00300 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00301 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00302 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00303 void HAL_SYSTICK_IRQHandler(void);
00304 void HAL_SYSTICK_Callback(void);
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Private types -------------------------------------------------------------*/
00314 /* Private variables ---------------------------------------------------------*/
00315 /* Private constants ---------------------------------------------------------*/
00316 /* Private macros ------------------------------------------------------------*/
00317 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00318   * @{
00319   */
00320 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00321                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00322                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00323                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00324                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00325
00326 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
00327
00328 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
00329
00330 #define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
00331
00332 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00333                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00334
00335 #if (__MPU_PRESENT == 1U)
00336 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00337                                      ((STATE) == MPU_REGION_DISABLE))
00338
00339 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00340                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00341
00342 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00343                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00344
00345 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00346                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00347
00348 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00349                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00350
00351 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00352                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00353                                 ((TYPE) == MPU_TEX_LEVEL2))
00354
00355 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00356                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00357                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00358                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00359                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00360                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00361
00362 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00363                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00364                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00365                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00366                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00367                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00368                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00369                                          ((NUMBER) == MPU_REGION_NUMBER7))
00370
00371 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00372                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00373                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00374                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00375                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00376                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00377                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00378                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00379                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00380                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00381                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00382                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00383                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00384                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00385                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00386                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00387                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00388                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00389                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00390                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00391                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00392                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00393                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00394                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00395                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00396                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00397                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00398                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00399
00400 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
00401 #endif /* __MPU_PRESENT */
00402
00403 /**
00404   * @}
00405   */
00406
00407 /* Private functions ---------------------------------------------------------*/
00408 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
00409   * @brief    CORTEX private  functions
00410   * @{
00411   */
00412
00413 #if (__MPU_PRESENT == 1)
00414 /**
00415   * @brief  Disables the MPU
00416   * @retval None
00417   */
00418 __STATIC_INLINE void HAL_MPU_Disable(void)
00419 {
00420   /* Disable fault exceptions */
00421   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00422
00423   /* Disable the MPU */
00424   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00425 }
00426
00427 /**
00428   * @brief  Enables the MPU
00429   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
00430   *          NMI, FAULTMASK and privileged access to the default memory
00431   *          This parameter can be one of the following values:
00432   *            @arg MPU_HFNMI_PRIVDEF_NONE
00433   *            @arg MPU_HARDFAULT_NMI
00434   *            @arg MPU_PRIVILEGED_DEFAULT
00435   *            @arg MPU_HFNMI_PRIVDEF
00436   * @retval None
00437   */
00438 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
00439 {
00440   /* Enable the MPU */
00441   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
00442
00443   /* Enable fault exceptions */
00444   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00445 }
00446 #endif /* __MPU_PRESENT */
00447
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /**
00457   * @}
00458   */
00459
00460 #ifdef __cplusplus
00461 }
00462 #endif
00463
00464 #endif /* __STM32F4xx_HAL_CORTEX_H */
00465
00466
00467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_crc.c Source File

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stm32f4xx_hal_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   CRC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       The CRC HAL driver can be used as follows:
00020
00021       (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00022
00023       (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
00024           a 32-bit data buffer using combination of the previous CRC value
00025           and the new one.
00026
00027       (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
00028           a new 32-bit data buffer. This function resets the CRC computation
00029           unit before starting the computation to avoid getting wrong CRC values.
00030
00031   @endverbatim
00032   ******************************************************************************
00033   * @attention
00034   *
00035   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00036   *
00037   * Redistribution and use in source and binary forms, with or without modification,
00038   * are permitted provided that the following conditions are met:
00039   *   1. Redistributions of source code must retain the above copyright notice,
00040   *      this list of conditions and the following disclaimer.
00041   *   2. Redistributions in binary form must reproduce the above copyright notice,
00042   *      this list of conditions and the following disclaimer in the documentation
00043   *      and/or other materials provided with the distribution.
00044   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00045   *      may be used to endorse or promote products derived from this software
00046   *      without specific prior written permission.
00047   *
00048   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00049   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00050   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00051   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00052   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00053   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00054   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00055   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00056   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00057   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00058   *
00059   ******************************************************************************
00060   */
00061
00062 /* Includes ------------------------------------------------------------------*/
00063 #include "stm32f4xx_hal.h"
00064
00065 /** @addtogroup STM32F4xx_HAL_Driver
00066   * @{
00067   */
00068
00069 /** @addtogroup CRC
00070   * @{
00071   */
00072
00073 #ifdef HAL_CRC_MODULE_ENABLED
00074
00075 /* Private typedef -----------------------------------------------------------*/
00076 /* Private define ------------------------------------------------------------*/
00077 /* Private macro -------------------------------------------------------------*/
00078 /* Private variables ---------------------------------------------------------*/
00079 /* Private function prototypes -----------------------------------------------*/
00080 /* Private functions ---------------------------------------------------------*/
00081 /* Exported functions --------------------------------------------------------*/
00082
00083 /** @addtogroup CRC_Exported_Functions
00084   * @{
00085   */
00086
00087 /** @addtogroup CRC_Exported_Functions_Group1
00088  *  @brief   Initialization and de-initialization functions
00089  *
00090 @verbatim
00091   ==============================================================================
00092             ##### Initialization and de-initialization functions #####
00093   ==============================================================================
00094     [..]  This section provides functions allowing to:
00095       (+) Initialize the CRC according to the specified parameters
00096           in the CRC_InitTypeDef and create the associated handle
00097       (+) DeInitialize the CRC peripheral
00098       (+) Initialize the CRC MSP
00099       (+) DeInitialize CRC MSP
00100
00101 @endverbatim
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  Initializes the CRC according to the specified
00107   *         parameters in the CRC_InitTypeDef and creates the associated handle.
00108   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00109   *         the configuration information for CRC
00110   * @retval HAL status
00111   */
00112 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00113 {
00114   /* Check the CRC handle allocation */
00115   if(hcrc == NULL)
00116   {
00117     return HAL_ERROR;
00118   }
00119
00120   /* Check the parameters */
00121   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00122
00123   if(hcrc->State == HAL_CRC_STATE_RESET)
00124   {
00125     /* Allocate lock resource and initialize it */
00126     hcrc->Lock = HAL_UNLOCKED;
00127     /* Init the low level hardware */
00128     HAL_CRC_MspInit(hcrc);
00129   }
00130
00131   /* Change CRC peripheral state */
00132   hcrc->State = HAL_CRC_STATE_BUSY;
00133
00134   /* Change CRC peripheral state */
00135   hcrc->State = HAL_CRC_STATE_READY;
00136
00137   /* Return function status */
00138   return HAL_OK;
00139 }
00140
00141 /**
00142   * @brief  DeInitializes the CRC peripheral.
00143   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00144   *         the configuration information for CRC
00145   * @retval HAL status
00146   */
00147 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00148 {
00149   /* Check the CRC handle allocation */
00150   if(hcrc == NULL)
00151   {
00152     return HAL_ERROR;
00153   }
00154
00155   /* Check the parameters */
00156   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00157
00158   /* Change CRC peripheral state */
00159   hcrc->State = HAL_CRC_STATE_BUSY;
00160
00161   /* DeInit the low level hardware */
00162   HAL_CRC_MspDeInit(hcrc);
00163
00164   /* Change CRC peripheral state */
00165   hcrc->State = HAL_CRC_STATE_RESET;
00166
00167   /* Release Lock */
00168   __HAL_UNLOCK(hcrc);
00169
00170   /* Return function status */
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  Initializes the CRC MSP.
00176   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00177   *         the configuration information for CRC
00178   * @retval None
00179   */
00180 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00181 {
00182   /* Prevent unused argument(s) compilation warning */
00183   UNUSED(hcrc);
00184   /* NOTE : This function Should not be modified, when the callback is needed,
00185             the HAL_CRC_MspInit could be implemented in the user file
00186    */
00187 }
00188
00189 /**
00190   * @brief  DeInitializes the CRC MSP.
00191   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00192   *         the configuration information for CRC
00193   * @retval None
00194   */
00195 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00196 {
00197   /* Prevent unused argument(s) compilation warning */
00198   UNUSED(hcrc);
00199   /* NOTE : This function Should not be modified, when the callback is needed,
00200             the HAL_CRC_MspDeInit could be implemented in the user file
00201    */
00202 }
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @addtogroup CRC_Exported_Functions_Group2
00209  *  @brief   Peripheral Control functions
00210  *
00211 @verbatim
00212   ==============================================================================
00213                       ##### Peripheral Control functions #####
00214   ==============================================================================
00215     [..]  This section provides functions allowing to:
00216       (+) Compute the 32-bit CRC value of 32-bit data buffer,
00217           using combination of the previous CRC value and the new one.
00218       (+) Compute the 32-bit CRC value of 32-bit data buffer,
00219           independently of the previous CRC value.
00220
00221 @endverbatim
00222   * @{
00223   */
00224
00225 /**
00226   * @brief  Computes the 32-bit CRC of 32-bit data buffer using combination
00227   *         of the previous CRC value and the new one.
00228   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00229   *         the configuration information for CRC
00230   * @param  pBuffer: pointer to the buffer containing the data to be computed
00231   * @param  BufferLength: length of the buffer to be computed
00232   * @retval 32-bit CRC
00233   */
00234 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00235 {
00236   uint32_t index = 0U;
00237
00238   /* Process Locked */
00239   __HAL_LOCK(hcrc);
00240
00241   /* Change CRC peripheral state */
00242   hcrc->State = HAL_CRC_STATE_BUSY;
00243
00244   /* Enter Data to the CRC calculator */
00245   for(index = 0U; index < BufferLength; index++)
00246   {
00247     hcrc->Instance->DR = pBuffer[index];
00248   }
00249
00250   /* Change CRC peripheral state */
00251   hcrc->State = HAL_CRC_STATE_READY;
00252
00253   /* Process Unlocked */
00254   __HAL_UNLOCK(hcrc);
00255
00256   /* Return the CRC computed value */
00257   return hcrc->Instance->DR;
00258 }
00259
00260 /**
00261   * @brief  Computes the 32-bit CRC of 32-bit data buffer independently
00262   *         of the previous CRC value.
00263   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00264   *         the configuration information for CRC
00265   * @param  pBuffer: Pointer to the buffer containing the data to be computed
00266   * @param  BufferLength: Length of the buffer to be computed
00267   * @retval 32-bit CRC
00268   */
00269 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00270 {
00271   uint32_t index = 0U;
00272
00273   /* Process Locked */
00274   __HAL_LOCK(hcrc);
00275
00276   /* Change CRC peripheral state */
00277   hcrc->State = HAL_CRC_STATE_BUSY;
00278
00279   /* Reset CRC Calculation Unit */
00280   __HAL_CRC_DR_RESET(hcrc);
00281
00282   /* Enter Data to the CRC calculator */
00283   for(index = 0U; index < BufferLength; index++)
00284   {
00285     hcrc->Instance->DR = pBuffer[index];
00286   }
00287
00288   /* Change CRC peripheral state */
00289   hcrc->State = HAL_CRC_STATE_READY;
00290
00291   /* Process Unlocked */
00292   __HAL_UNLOCK(hcrc);
00293
00294   /* Return the CRC computed value */
00295   return hcrc->Instance->DR;
00296 }
00297
00298 /**
00299   * @}
00300   */
00301
00302
00303 /** @addtogroup CRC_Exported_Functions_Group3
00304  *  @brief   Peripheral State functions
00305  *
00306 @verbatim
00307   ==============================================================================
00308                       ##### Peripheral State functions #####
00309   ==============================================================================
00310     [..]
00311     This subsection permits to get in run-time the status of the peripheral
00312     and the data flow.
00313
00314 @endverbatim
00315   * @{
00316   */
00317
00318 /**
00319   * @brief  Returns the CRC state.
00320   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00321   *         the configuration information for CRC
00322   * @retval HAL state
00323   */
00324 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00325 {
00326   return hcrc->State;
00327 }
00328
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 #endif /* HAL_CRC_MODULE_ENABLED */
00338 /**
00339   * @}
00340   */
00341
00342 /**
00343   * @}
00344   */
00345
00346 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_crc.h Source File

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stm32f4xx_hal_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of CRC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_CRC_H
00040 #define __STM32F4xx_HAL_CRC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup CRC CRC
00054   * @brief CRC HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup CRC_Exported_Types CRC Exported Types
00060   * @{
00061   */
00062
00063 /** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
00064   * @{
00065   */
00066 typedef enum
00067 {
00068   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00069   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00070   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00071   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00072   HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
00073
00074 }HAL_CRC_StateTypeDef;
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition
00080   * @{
00081   */
00082 typedef struct
00083 {
00084   CRC_TypeDef                 *Instance;  /*!< Register base address   */
00085
00086   HAL_LockTypeDef             Lock;       /*!< CRC locking object      */
00087
00088   __IO HAL_CRC_StateTypeDef   State;      /*!< CRC communication state */
00089
00090 }CRC_HandleTypeDef;
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100 /* Exported macro ------------------------------------------------------------*/
00101 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00102   * @{
00103   */
00104
00105 /** @brief Resets CRC handle state
00106   * @param  __HANDLE__: CRC handle
00107   * @retval None
00108   */
00109 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00110
00111 /**
00112   * @brief  Resets CRC Data Register.
00113   * @param  __HANDLE__: CRC handle
00114   * @retval None
00115   */
00116 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00117
00118 /**
00119   * @brief Stores a 8-bit data in the Independent Data(ID) register.
00120   * @param __HANDLE__: CRC handle
00121   * @param __VALUE__: 8-bit value to be stored in the ID register
00122   * @retval None
00123   */
00124 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00125
00126 /**
00127   * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
00128   * @param __HANDLE__: CRC handle
00129   * @retval 8-bit value of the ID register
00130   */
00131 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported functions --------------------------------------------------------*/
00137 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00138   * @{
00139   */
00140
00141 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00142   * @{
00143   */
00144 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00145 HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
00146 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00147 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00153   * @{
00154   */
00155 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00156 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00162   * @{
00163   */
00164 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172 /* Private types -------------------------------------------------------------*/
00173 /** @defgroup CRC_Private_Types CRC Private Types
00174   * @{
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /* Private defines -----------------------------------------------------------*/
00182 /** @defgroup CRC_Private_Defines CRC Private Defines
00183   * @{
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Private variables ---------------------------------------------------------*/
00191 /** @defgroup CRC_Private_Variables CRC Private Variables
00192   * @{
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Private constants ---------------------------------------------------------*/
00200 /** @defgroup CRC_Private_Constants CRC Private Constants
00201   * @{
00202   */
00203
00204 /**
00205   * @}
00206   */
00207
00208 /* Private macros ------------------------------------------------------------*/
00209 /** @defgroup CRC_Private_Macros CRC Private Macros
00210   * @{
00211   */
00212
00213 /**
00214   * @}
00215   */
00216
00217 /* Private functions prototypes ----------------------------------------------*/
00218 /** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
00219   * @{
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /* Private functions ---------------------------------------------------------*/
00227 /** @defgroup CRC_Private_Functions CRC Private Functions
00228   * @{
00229   */
00230
00231 /**
00232   * @}
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 #ifdef __cplusplus
00244 }
00245 #endif
00246
00247 #endif /* __STM32F4xx_HAL_CRC_H */
00248
00249 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp.c Source File

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stm32f4xx_hal_cryp.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   CRYP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cryptography (CRYP) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + AES processing functions
00012   *           + DES processing functions
00013   *           + TDES processing functions
00014   *           + DMA callback functions
00015   *           + CRYP IRQ handler management
00016   *           + Peripheral State functions
00017   *
00018   @verbatim
00019   ==============================================================================
00020                      ##### How to use this driver #####
00021   ==============================================================================
00022     [..]
00023       The CRYP HAL driver can be used as follows:
00024
00025       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00026          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
00027          (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
00028              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00029              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00030              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00031          (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
00032              (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00033              (+++) Configure and enable two DMA streams one for managing data transfer from
00034                  memory to peripheral (input stream) and another stream for managing data
00035                  transfer from peripheral to memory (output stream)
00036              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00037                  using  __HAL_LINKDMA()
00038              (+++) Configure the priority and enable the NVIC for the transfer complete
00039                  interrupt on the two DMA Streams. The output stream should have higher
00040                  priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00041
00042       (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
00043          (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
00044          (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
00045          (##) The encryption/decryption key. It's size depends on the algorithm
00046               used for encryption/decryption
00047          (##) The initialization vector (counter). It is not used ECB mode.
00048
00049       (#)Three processing (encryption/decryption) functions are available:
00050          (##) Polling mode: encryption and decryption APIs are blocking functions
00051               i.e. they process the data and wait till the processing is finished,
00052               e.g. HAL_CRYP_AESCBC_Encrypt()
00053          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00054               i.e. they process the data under interrupt,
00055               e.g. HAL_CRYP_AESCBC_Encrypt_IT()
00056          (##) DMA mode: encryption and decryption APIs are not blocking functions
00057               i.e. the data transfer is ensured by DMA,
00058               e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
00059
00060       (#)When the processing function is called at first time after HAL_CRYP_Init()
00061          the CRYP peripheral is initialized and processes the buffer in input.
00062          At second call, the processing function performs an append of the already
00063          processed buffer.
00064          When a new data block is to be processed, call HAL_CRYP_Init() then the
00065          processing function.
00066
00067        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f4xx_hal.h"
00102
00103 /** @addtogroup STM32F4xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup CRYP CRYP
00108   * @brief CRYP HAL module driver.
00109   * @{
00110   */
00111
00112 #ifdef HAL_CRYP_MODULE_ENABLED
00113
00114 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /** @addtogroup CRYP_Private_define
00119   * @{
00120   */
00121 #define CRYP_TIMEOUT_VALUE  1U
00122 /**
00123   * @}
00124   */
00125
00126 /* Private macro -------------------------------------------------------------*/
00127 /* Private variables ---------------------------------------------------------*/
00128 /* Private function prototypes -----------------------------------------------*/
00129 /** @addtogroup CRYP_Private_Functions_prototypes
00130   * @{
00131   */
00132 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
00133 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
00134 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
00135 static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
00136 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00137 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00138 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00139 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00140 static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00141 static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00142 static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00143 static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
00144 /**
00145   * @}
00146   */
00147
00148
00149 /* Private functions ---------------------------------------------------------*/
00150
00151 /** @addtogroup CRYP_Private_Functions
00152   * @{
00153   */
00154
00155
00156 /**
00157   * @brief  DMA CRYP Input Data process complete callback.
00158   * @param  hdma: DMA handle
00159   * @retval None
00160   */
00161 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
00162 {
00163   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00164
00165   /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
00166      in the DMACR register */
00167   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
00168
00169   /* Call input data transfer complete callback */
00170   HAL_CRYP_InCpltCallback(hcryp);
00171 }
00172
00173 /**
00174   * @brief  DMA CRYP Output Data process complete callback.
00175   * @param  hdma: DMA handle
00176   * @retval None
00177   */
00178 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
00179 {
00180   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00181
00182   /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
00183      in the DMACR register */
00184   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
00185
00186   /* Disable CRYP */
00187   __HAL_CRYP_DISABLE(hcryp);
00188
00189   /* Change the CRYP state to ready */
00190   hcryp->State = HAL_CRYP_STATE_READY;
00191
00192   /* Call output data transfer complete callback */
00193   HAL_CRYP_OutCpltCallback(hcryp);
00194 }
00195
00196 /**
00197   * @brief  DMA CRYP communication error callback.
00198   * @param  hdma: DMA handle
00199   * @retval None
00200   */
00201 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
00202 {
00203   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
00204   hcryp->State= HAL_CRYP_STATE_READY;
00205   HAL_CRYP_ErrorCallback(hcryp);
00206 }
00207
00208 /**
00209   * @brief  Writes the Key in Key registers.
00210   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00211   *         the configuration information for CRYP module
00212   * @param  Key: Pointer to Key buffer
00213   * @param  KeySize: Size of Key
00214   * @retval None
00215   */
00216 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
00217 {
00218   uint32_t keyaddr = (uint32_t)Key;
00219
00220   switch(KeySize)
00221   {
00222   case CRYP_KEYSIZE_256B:
00223     /* Key Initialisation */
00224     hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
00225     keyaddr+=4U;
00226     hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
00227     keyaddr+=4U;
00228     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00229     keyaddr+=4U;
00230     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00231     keyaddr+=4U;
00232     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00233     keyaddr+=4U;
00234     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00235     keyaddr+=4U;
00236     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00237     keyaddr+=4U;
00238     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00239     break;
00240   case CRYP_KEYSIZE_192B:
00241     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00242     keyaddr+=4U;
00243     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00244     keyaddr+=4U;
00245     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00246     keyaddr+=4U;
00247     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00248     keyaddr+=4U;
00249     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00250     keyaddr+=4U;
00251     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00252     break;
00253   case CRYP_KEYSIZE_128B:
00254     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00255     keyaddr+=4U;
00256     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00257     keyaddr+=4U;
00258     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00259     keyaddr+=4U;
00260     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00261     break;
00262   default:
00263     break;
00264   }
00265 }
00266
00267 /**
00268   * @brief  Writes the InitVector/InitCounter in IV registers.
00269   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00270   *         the configuration information for CRYP module
00271   * @param  InitVector: Pointer to InitVector/InitCounter buffer
00272   * @param  IVSize: Size of the InitVector/InitCounter
00273   * @retval None
00274   */
00275 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
00276 {
00277   uint32_t ivaddr = (uint32_t)InitVector;
00278
00279   switch(IVSize)
00280   {
00281   case CRYP_KEYSIZE_128B:
00282     hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00283     ivaddr+=4U;
00284     hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00285     ivaddr+=4U;
00286     hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
00287     ivaddr+=4U;
00288     hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
00289     break;
00290     /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
00291   case CRYP_KEYSIZE_192B:
00292     hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00293     ivaddr+=4U;
00294     hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00295     break;
00296   case CRYP_KEYSIZE_256B:
00297     hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00298     ivaddr+=4U;
00299     hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00300     break;
00301   default:
00302     break;
00303   }
00304 }
00305
00306 /**
00307   * @brief  Process Data: Writes Input data in polling mode and read the output data
00308   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00309   *         the configuration information for CRYP module
00310   * @param  Input: Pointer to the Input buffer
00311   * @param  Ilength: Length of the Input buffer, must be a multiple of 16.
00312   * @param  Output: Pointer to the returned buffer
00313   * @param  Timeout: Timeout value
00314   * @retval None
00315   */
00316 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
00317 {
00318   uint32_t tickstart = 0U;
00319
00320   uint32_t i = 0U;
00321   uint32_t inputaddr  = (uint32_t)Input;
00322   uint32_t outputaddr = (uint32_t)Output;
00323
00324   for(i=0U; (i < Ilength); i+=16U)
00325   {
00326     /* Write the Input block in the IN FIFO */
00327     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00328     inputaddr+=4U;
00329     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00330     inputaddr+=4U;
00331     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
00332     inputaddr+=4U;
00333     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00334     inputaddr+=4U;
00335
00336     /* Get tick */
00337     tickstart = HAL_GetTick();
00338
00339     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00340     {
00341       /* Check for the Timeout */
00342       if(Timeout != HAL_MAX_DELAY)
00343       {
00344         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00345         {
00346           /* Change state */
00347           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00348
00349           /* Process Unlocked */
00350           __HAL_UNLOCK(hcryp);
00351
00352           return HAL_TIMEOUT;
00353         }
00354       }
00355     }
00356     /* Read the Output block from the Output FIFO */
00357     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00358     outputaddr+=4U;
00359     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00360     outputaddr+=4U;
00361     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00362     outputaddr+=4U;
00363     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00364     outputaddr+=4U;
00365   }
00366   /* Return function status */
00367   return HAL_OK;
00368 }
00369
00370 /**
00371   * @brief  Process Data: Write Input data in polling mode.
00372   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00373   *         the configuration information for CRYP module
00374   * @param  Input: Pointer to the Input buffer
00375   * @param  Ilength: Length of the Input buffer, must be a multiple of 8
00376   * @param  Output: Pointer to the returned buffer
00377   * @param  Timeout: Specify Timeout value
00378   * @retval None
00379   */
00380 static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
00381 {
00382   uint32_t tickstart = 0U;
00383
00384   uint32_t i = 0U;
00385   uint32_t inputaddr  = (uint32_t)Input;
00386   uint32_t outputaddr = (uint32_t)Output;
00387
00388   for(i=0U; (i < Ilength); i+=8U)
00389   {
00390     /* Write the Input block in the IN FIFO */
00391     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
00392     inputaddr+=4U;
00393     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00394     inputaddr+=4U;
00395
00396     /* Get tick */
00397     tickstart = HAL_GetTick();
00398
00399     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00400     {
00401       /* Check for the Timeout */
00402       if(Timeout != HAL_MAX_DELAY)
00403       {
00404         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00405         {
00406           /* Change state */
00407           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00408
00409           /* Process Unlocked */
00410           __HAL_UNLOCK(hcryp);
00411
00412           return HAL_TIMEOUT;
00413         }
00414       }
00415     }
00416     /* Read the Output block from the Output FIFO */
00417     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00418     outputaddr+=4U;
00419     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00420     outputaddr+=4U;
00421   }
00422   /* Return function status */
00423   return HAL_OK;
00424 }
00425
00426 /**
00427   * @brief  Set the DMA configuration and start the DMA transfer
00428   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00429   *         the configuration information for CRYP module
00430   * @param  inputaddr: address of the Input buffer
00431   * @param  Size: Size of the Input buffer, must be a multiple of 16.
00432   * @param  outputaddr: address of the Output buffer
00433   * @retval None
00434   */
00435 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
00436 {
00437   /* Set the CRYP DMA transfer complete callback */
00438   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
00439   /* Set the DMA error callback */
00440   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
00441
00442   /* Set the CRYP DMA transfer complete callback */
00443   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
00444   /* Set the DMA error callback */
00445   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
00446
00447   /* Enable CRYP */
00448   __HAL_CRYP_ENABLE(hcryp);
00449
00450   /* Enable the DMA In DMA Stream */
00451   HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4U);
00452
00453   /* Enable In DMA request */
00454   hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
00455
00456   /* Enable the DMA Out DMA Stream */
00457   HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4U);
00458
00459   /* Enable Out DMA request */
00460   hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
00461
00462 }
00463
00464 /**
00465   * @brief  Sets the CRYP peripheral in DES ECB mode.
00466   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00467   *         the configuration information for CRYP module
00468   * @param  Direction: Encryption or decryption
00469   * @retval None
00470   */
00471 static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00472 {
00473   /* Check if initialization phase has already been performed */
00474   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00475   {
00476     /* Set the CRYP peripheral in AES ECB mode */
00477     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
00478
00479     /* Set the key */
00480     hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
00481     hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4U));
00482
00483     /* Flush FIFO */
00484     __HAL_CRYP_FIFO_FLUSH(hcryp);
00485
00486     /* Set the phase */
00487     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00488   }
00489 }
00490
00491 /**
00492   * @brief  Sets the CRYP peripheral in DES CBC mode.
00493   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00494   *         the configuration information for CRYP module
00495   * @param  Direction: Encryption or decryption
00496   * @retval None
00497   */
00498 static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00499 {
00500   /* Check if initialization phase has already been performed */
00501   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00502   {
00503     /* Set the CRYP peripheral in AES ECB mode */
00504     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
00505
00506     /* Set the key */
00507     hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
00508     hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4U));
00509
00510     /* Set the Initialization Vector */
00511     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
00512
00513     /* Flush FIFO */
00514     __HAL_CRYP_FIFO_FLUSH(hcryp);
00515
00516     /* Set the phase */
00517     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00518   }
00519 }
00520
00521 /**
00522   * @brief  Sets the CRYP peripheral in TDES ECB mode.
00523   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00524   *         the configuration information for CRYP module
00525   * @param  Direction: Encryption or decryption
00526   * @retval None
00527   */
00528 static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00529 {
00530   /* Check if initialization phase has already been performed */
00531   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00532   {
00533     /* Set the CRYP peripheral in AES ECB mode */
00534     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
00535
00536     /* Set the key */
00537     CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
00538
00539     /* Flush FIFO */
00540     __HAL_CRYP_FIFO_FLUSH(hcryp);
00541
00542     /* Set the phase */
00543     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00544   }
00545 }
00546
00547 /**
00548   * @brief  Sets the CRYP peripheral in TDES CBC mode
00549   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00550   *         the configuration information for CRYP module
00551   * @param  Direction: Encryption or decryption
00552   * @retval None
00553   */
00554 static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
00555 {
00556   /* Check if initialization phase has already been performed */
00557   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00558   {
00559     /* Set the CRYP peripheral in AES CBC mode */
00560     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
00561
00562     /* Set the key */
00563     CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
00564
00565     /* Set the Initialization Vector */
00566     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
00567
00568     /* Flush FIFO */
00569     __HAL_CRYP_FIFO_FLUSH(hcryp);
00570
00571     /* Set the phase */
00572     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00573   }
00574 }
00575
00576 /**
00577   * @}
00578   */
00579
00580  /* Exported functions --------------------------------------------------------*/
00581 /** @addtogroup CRYP_Exported_Functions
00582   * @{
00583   */
00584
00585 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
00586  *  @brief    Initialization and Configuration functions.
00587  *
00588 @verbatim
00589   ==============================================================================
00590               ##### Initialization and de-initialization functions #####
00591   ==============================================================================
00592     [..]  This section provides functions allowing to:
00593       (+) Initialize the CRYP according to the specified parameters
00594           in the CRYP_InitTypeDef and creates the associated handle
00595       (+) DeInitialize the CRYP peripheral
00596       (+) Initialize the CRYP MSP
00597       (+) DeInitialize CRYP MSP
00598
00599 @endverbatim
00600   * @{
00601   */
00602
00603 /**
00604   * @brief  Initializes the CRYP according to the specified
00605   *         parameters in the CRYP_InitTypeDef and creates the associated handle.
00606   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00607   *         the configuration information for CRYP module
00608   * @retval HAL status
00609   */
00610 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00611 {
00612   /* Check the CRYP handle allocation */
00613   if(hcryp == NULL)
00614   {
00615     return HAL_ERROR;
00616   }
00617
00618   /* Check the parameters */
00619   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00620   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00621
00622   if(hcryp->State == HAL_CRYP_STATE_RESET)
00623   {
00624     /* Allocate lock resource and initialize it */
00625     hcryp->Lock = HAL_UNLOCKED;
00626     /* Init the low level hardware */
00627     HAL_CRYP_MspInit(hcryp);
00628   }
00629
00630   /* Change the CRYP state */
00631   hcryp->State = HAL_CRYP_STATE_BUSY;
00632
00633   /* Set the key size and data type*/
00634   CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
00635
00636   /* Reset CrypInCount and CrypOutCount */
00637   hcryp->CrypInCount = 0U;
00638   hcryp->CrypOutCount = 0U;
00639
00640   /* Change the CRYP state */
00641   hcryp->State = HAL_CRYP_STATE_READY;
00642
00643   /* Set the default CRYP phase */
00644   hcryp->Phase = HAL_CRYP_PHASE_READY;
00645
00646   /* Return function status */
00647   return HAL_OK;
00648 }
00649
00650 /**
00651   * @brief  DeInitializes the CRYP peripheral.
00652   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00653   *         the configuration information for CRYP module
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00657 {
00658   /* Check the CRYP handle allocation */
00659   if(hcryp == NULL)
00660   {
00661     return HAL_ERROR;
00662   }
00663
00664   /* Change the CRYP state */
00665   hcryp->State = HAL_CRYP_STATE_BUSY;
00666
00667   /* Set the default CRYP phase */
00668   hcryp->Phase = HAL_CRYP_PHASE_READY;
00669
00670   /* Reset CrypInCount and CrypOutCount */
00671   hcryp->CrypInCount = 0U;
00672   hcryp->CrypOutCount = 0U;
00673
00674   /* Disable the CRYP Peripheral Clock */
00675   __HAL_CRYP_DISABLE(hcryp);
00676
00677   /* DeInit the low level hardware: CLOCK, NVIC.*/
00678   HAL_CRYP_MspDeInit(hcryp);
00679
00680   /* Change the CRYP state */
00681   hcryp->State = HAL_CRYP_STATE_RESET;
00682
00683   /* Release Lock */
00684   __HAL_UNLOCK(hcryp);
00685
00686   /* Return function status */
00687   return HAL_OK;
00688 }
00689
00690 /**
00691   * @brief  Initializes the CRYP MSP.
00692   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00693   *         the configuration information for CRYP module
00694   * @retval None
00695   */
00696 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00697 {
00698   /* Prevent unused argument(s) compilation warning */
00699   UNUSED(hcryp);
00700   /* NOTE : This function Should not be modified, when the callback is needed,
00701             the HAL_CRYP_MspInit could be implemented in the user file
00702    */
00703 }
00704
00705 /**
00706   * @brief  DeInitializes CRYP MSP.
00707   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00708   *         the configuration information for CRYP module
00709   * @retval None
00710   */
00711 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00712 {
00713   /* Prevent unused argument(s) compilation warning */
00714   UNUSED(hcryp);
00715   /* NOTE : This function Should not be modified, when the callback is needed,
00716             the HAL_CRYP_MspDeInit could be implemented in the user file
00717    */
00718 }
00719
00720 /**
00721   * @}
00722   */
00723
00724 /** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
00725  *  @brief   processing functions.
00726  *
00727 @verbatim
00728   ==============================================================================
00729                       ##### AES processing functions #####
00730   ==============================================================================
00731     [..]  This section provides functions allowing to:
00732       (+) Encrypt plaintext using AES-128/192/256 using chaining modes
00733       (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
00734     [..]  Three processing functions are available:
00735       (+) Polling mode
00736       (+) Interrupt mode
00737       (+) DMA mode
00738
00739 @endverbatim
00740   * @{
00741   */
00742
00743 /**
00744   * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
00745   *         then encrypt pPlainData. The cypher data are available in pCypherData
00746   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00747   *         the configuration information for CRYP module
00748   * @param  pPlainData: Pointer to the plaintext buffer
00749   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00750   * @param  pCypherData: Pointer to the cyphertext buffer
00751   * @param  Timeout: Specify Timeout value
00752   * @retval HAL status
00753   */
00754 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00755 {
00756   /* Process Locked */
00757   __HAL_LOCK(hcryp);
00758
00759   /* Change the CRYP state */
00760   hcryp->State = HAL_CRYP_STATE_BUSY;
00761
00762   /* Check if initialization phase has already been performed */
00763   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00764   {
00765     /* Set the key */
00766     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00767
00768     /* Set the CRYP peripheral in AES ECB mode */
00769     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
00770
00771     /* Flush FIFO */
00772     __HAL_CRYP_FIFO_FLUSH(hcryp);
00773
00774     /* Enable CRYP */
00775     __HAL_CRYP_ENABLE(hcryp);
00776
00777     /* Set the phase */
00778     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00779   }
00780
00781     /* Write Plain Data and Get Cypher Data */
00782     if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00783     {
00784       return HAL_TIMEOUT;
00785     }
00786
00787   /* Change the CRYP state */
00788   hcryp->State = HAL_CRYP_STATE_READY;
00789
00790   /* Process Unlocked */
00791   __HAL_UNLOCK(hcryp);
00792
00793   /* Return function status */
00794   return HAL_OK;
00795 }
00796
00797 /**
00798   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
00799   *         then encrypt pPlainData. The cypher data are available in pCypherData
00800   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00801   *         the configuration information for CRYP module
00802   * @param  pPlainData: Pointer to the plaintext buffer
00803   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00804   * @param  pCypherData: Pointer to the cyphertext buffer
00805   * @param  Timeout: Specify Timeout value
00806   * @retval HAL status
00807   */
00808 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00809 {
00810   /* Process Locked */
00811   __HAL_LOCK(hcryp);
00812
00813   /* Change the CRYP state */
00814   hcryp->State = HAL_CRYP_STATE_BUSY;
00815
00816   /* Check if initialization phase has already been performed */
00817   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00818   {
00819     /* Set the key */
00820     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00821
00822     /* Set the CRYP peripheral in AES ECB mode */
00823     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
00824
00825     /* Set the Initialization Vector */
00826     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
00827
00828     /* Flush FIFO */
00829     __HAL_CRYP_FIFO_FLUSH(hcryp);
00830
00831     /* Enable CRYP */
00832     __HAL_CRYP_ENABLE(hcryp);
00833
00834     /* Set the phase */
00835     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00836   }
00837
00838     /* Write Plain Data and Get Cypher Data */
00839     if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00840     {
00841       return HAL_TIMEOUT;
00842     }
00843
00844   /* Change the CRYP state */
00845   hcryp->State = HAL_CRYP_STATE_READY;
00846
00847   /* Process Unlocked */
00848   __HAL_UNLOCK(hcryp);
00849
00850   /* Return function status */
00851   return HAL_OK;
00852 }
00853
00854 /**
00855   * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
00856   *         then encrypt pPlainData. The cypher data are available in pCypherData
00857   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00858   *         the configuration information for CRYP module
00859   * @param  pPlainData: Pointer to the plaintext buffer
00860   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00861   * @param  pCypherData: Pointer to the cyphertext buffer
00862   * @param  Timeout: Specify Timeout value
00863   * @retval HAL status
00864   */
00865 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00866 {
00867   /* Process Locked */
00868   __HAL_LOCK(hcryp);
00869
00870   /* Change the CRYP state */
00871   hcryp->State = HAL_CRYP_STATE_BUSY;
00872
00873   /* Check if initialization phase has already been performed */
00874   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00875   {
00876     /* Set the key */
00877     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00878
00879     /* Set the CRYP peripheral in AES ECB mode */
00880     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
00881
00882     /* Set the Initialization Vector */
00883     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
00884
00885     /* Flush FIFO */
00886     __HAL_CRYP_FIFO_FLUSH(hcryp);
00887
00888     /* Enable CRYP */
00889     __HAL_CRYP_ENABLE(hcryp);
00890
00891     /* Set the phase */
00892     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00893   }
00894
00895     /* Write Plain Data and Get Cypher Data */
00896     if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00897     {
00898       return HAL_TIMEOUT;
00899     }
00900
00901   /* Change the CRYP state */
00902   hcryp->State = HAL_CRYP_STATE_READY;
00903
00904   /* Process Unlocked */
00905   __HAL_UNLOCK(hcryp);
00906
00907   /* Return function status */
00908   return HAL_OK;
00909 }
00910
00911
00912
00913 /**
00914   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
00915   *         then decrypted pCypherData. The cypher data are available in pPlainData
00916   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00917   *         the configuration information for CRYP module
00918   * @param  pCypherData: Pointer to the cyphertext buffer
00919   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00920   * @param  pPlainData: Pointer to the plaintext buffer
00921   * @param  Timeout: Specify Timeout value
00922   * @retval HAL status
00923   */
00924 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
00925 {
00926    uint32_t tickstart = 0U;
00927
00928   /* Process Locked */
00929   __HAL_LOCK(hcryp);
00930
00931   /* Change the CRYP state */
00932   hcryp->State = HAL_CRYP_STATE_BUSY;
00933
00934   /* Check if initialization phase has already been performed */
00935   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00936   {
00937     /* Set the key */
00938     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00939
00940     /* Set the CRYP peripheral in AES Key mode */
00941     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
00942
00943     /* Enable CRYP */
00944     __HAL_CRYP_ENABLE(hcryp);
00945
00946     /* Get tick */
00947     tickstart = HAL_GetTick();
00948
00949     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
00950     {
00951       /* Check for the Timeout */
00952       if(Timeout != HAL_MAX_DELAY)
00953       {
00954         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00955         {
00956           /* Change state */
00957           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00958
00959           /* Process Unlocked */
00960           __HAL_UNLOCK(hcryp);
00961
00962           return HAL_TIMEOUT;
00963         }
00964       }
00965     }
00966
00967     /* Disable CRYP */
00968     __HAL_CRYP_DISABLE(hcryp);
00969
00970     /* Reset the ALGOMODE bits*/
00971     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
00972
00973     /* Set the CRYP peripheral in AES ECB decryption mode */
00974     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
00975     /* Flush FIFO */
00976     __HAL_CRYP_FIFO_FLUSH(hcryp);
00977
00978     /* Enable CRYP */
00979     __HAL_CRYP_ENABLE(hcryp);
00980
00981     /* Set the phase */
00982     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00983   }
00984
00985     /* Write Plain Data and Get Cypher Data */
00986     if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
00987     {
00988       return HAL_TIMEOUT;
00989     }
00990
00991   /* Change the CRYP state */
00992   hcryp->State = HAL_CRYP_STATE_READY;
00993
00994   /* Process Unlocked */
00995   __HAL_UNLOCK(hcryp);
00996
00997   /* Return function status */
00998   return HAL_OK;
00999 }
01000
01001 /**
01002   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
01003   *         then decrypted pCypherData. The cypher data are available in pPlainData
01004   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01005   *         the configuration information for CRYP module
01006   * @param  pCypherData: Pointer to the cyphertext buffer
01007   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01008   * @param  pPlainData: Pointer to the plaintext buffer
01009   * @param  Timeout: Specify Timeout value
01010   * @retval HAL status
01011   */
01012 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
01013 {
01014   uint32_t tickstart = 0U;
01015
01016   /* Process Locked */
01017   __HAL_LOCK(hcryp);
01018
01019   /* Change the CRYP state */
01020   hcryp->State = HAL_CRYP_STATE_BUSY;
01021
01022   /* Check if initialization phase has already been performed */
01023   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01024   {
01025     /* Set the key */
01026     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01027
01028     /* Set the CRYP peripheral in AES Key mode */
01029     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
01030
01031     /* Enable CRYP */
01032     __HAL_CRYP_ENABLE(hcryp);
01033
01034     /* Get tick */
01035     tickstart = HAL_GetTick();
01036
01037     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
01038     {
01039       /* Check for the Timeout */
01040       if(Timeout != HAL_MAX_DELAY)
01041       {
01042         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01043         {
01044           /* Change state */
01045           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01046
01047           /* Process Unlocked */
01048           __HAL_UNLOCK(hcryp);
01049
01050           return HAL_TIMEOUT;
01051         }
01052       }
01053     }
01054
01055     /* Reset the ALGOMODE bits*/
01056     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
01057
01058     /* Set the CRYP peripheral in AES CBC decryption mode */
01059     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
01060
01061     /* Set the Initialization Vector */
01062     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01063
01064     /* Flush FIFO */
01065     __HAL_CRYP_FIFO_FLUSH(hcryp);
01066
01067     /* Enable CRYP */
01068     __HAL_CRYP_ENABLE(hcryp);
01069
01070     /* Set the phase */
01071     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01072   }
01073
01074     /* Write Plain Data and Get Cypher Data */
01075     if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
01076     {
01077       return HAL_TIMEOUT;
01078     }
01079
01080   /* Change the CRYP state */
01081   hcryp->State = HAL_CRYP_STATE_READY;
01082
01083   /* Process Unlocked */
01084   __HAL_UNLOCK(hcryp);
01085
01086   /* Return function status */
01087   return HAL_OK;
01088 }
01089
01090 /**
01091   * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
01092   *         then decrypted pCypherData. The cypher data are available in pPlainData
01093   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01094   *         the configuration information for CRYP module
01095   * @param  pCypherData: Pointer to the cyphertext buffer
01096   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01097   * @param  pPlainData: Pointer to the plaintext buffer
01098   * @param  Timeout: Specify Timeout value
01099   * @retval HAL status
01100   */
01101 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
01102 {
01103   /* Process Locked */
01104   __HAL_LOCK(hcryp);
01105
01106   /* Check if initialization phase has already been performed */
01107   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01108   {
01109     /* Change the CRYP state */
01110     hcryp->State = HAL_CRYP_STATE_BUSY;
01111
01112     /* Set the key */
01113     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01114
01115     /* Set the CRYP peripheral in AES CTR mode */
01116     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
01117
01118     /* Set the Initialization Vector */
01119     CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01120
01121     /* Flush FIFO */
01122     __HAL_CRYP_FIFO_FLUSH(hcryp);
01123
01124     /* Enable CRYP */
01125     __HAL_CRYP_ENABLE(hcryp);
01126
01127     /* Set the phase */
01128     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01129   }
01130
01131     /* Write Plain Data and Get Cypher Data */
01132     if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
01133     {
01134       return HAL_TIMEOUT;
01135     }
01136
01137   /* Change the CRYP state */
01138   hcryp->State = HAL_CRYP_STATE_READY;
01139
01140   /* Process Unlocked */
01141   __HAL_UNLOCK(hcryp);
01142
01143   /* Return function status */
01144   return HAL_OK;
01145 }
01146
01147 /**
01148   * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
01149   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01150   *         the configuration information for CRYP module
01151   * @param  pPlainData: Pointer to the plaintext buffer
01152   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01153   * @param  pCypherData: Pointer to the cyphertext buffer
01154   * @retval HAL status
01155   */
01156 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01157 {
01158   uint32_t inputaddr;
01159   uint32_t outputaddr;
01160
01161   if(hcryp->State == HAL_CRYP_STATE_READY)
01162   {
01163     /* Process Locked */
01164     __HAL_LOCK(hcryp);
01165
01166     hcryp->CrypInCount = Size;
01167     hcryp->pCrypInBuffPtr = pPlainData;
01168     hcryp->pCrypOutBuffPtr = pCypherData;
01169     hcryp->CrypOutCount = Size;
01170
01171     /* Change the CRYP state */
01172     hcryp->State = HAL_CRYP_STATE_BUSY;
01173
01174     /* Check if initialization phase has already been performed */
01175     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01176     {
01177       /* Set the key */
01178       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01179
01180       /* Set the CRYP peripheral in AES ECB mode */
01181       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
01182
01183       /* Flush FIFO */
01184       __HAL_CRYP_FIFO_FLUSH(hcryp);
01185
01186      /* Set the phase */
01187      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01188     }
01189
01190     /* Enable Interrupts */
01191     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01192
01193     /* Enable CRYP */
01194     __HAL_CRYP_ENABLE(hcryp);
01195
01196     /* Return function status */
01197     return HAL_OK;
01198   }
01199   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01200   {
01201     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01202     /* Write the Input block in the IN FIFO */
01203     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01204     inputaddr+=4U;
01205     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01206     inputaddr+=4U;
01207     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01208     inputaddr+=4U;
01209     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01210     hcryp->pCrypInBuffPtr += 16U;
01211     hcryp->CrypInCount -= 16U;
01212     if(hcryp->CrypInCount == 0U)
01213     {
01214       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01215       /* Call the Input data transfer complete callback */
01216       HAL_CRYP_InCpltCallback(hcryp);
01217     }
01218   }
01219   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01220   {
01221     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01222     /* Read the Output block from the Output FIFO */
01223     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01224     outputaddr+=4U;
01225     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01226     outputaddr+=4U;
01227     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01228     outputaddr+=4U;
01229     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01230     hcryp->pCrypOutBuffPtr += 16U;
01231     hcryp->CrypOutCount -= 16U;
01232     if(hcryp->CrypOutCount == 0U)
01233     {
01234       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01235       /* Process Locked */
01236       __HAL_UNLOCK(hcryp);
01237       /* Change the CRYP state */
01238       hcryp->State = HAL_CRYP_STATE_READY;
01239       /* Call Input transfer complete callback */
01240       HAL_CRYP_OutCpltCallback(hcryp);
01241     }
01242   }
01243
01244   /* Return function status */
01245   return HAL_OK;
01246 }
01247
01248 /**
01249   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
01250   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01251   *         the configuration information for CRYP module
01252   * @param  pPlainData: Pointer to the plaintext buffer
01253   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01254   * @param  pCypherData: Pointer to the cyphertext buffer
01255   * @retval HAL status
01256   */
01257 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01258 {
01259   uint32_t inputaddr;
01260   uint32_t outputaddr;
01261
01262   if(hcryp->State == HAL_CRYP_STATE_READY)
01263   {
01264     /* Process Locked */
01265     __HAL_LOCK(hcryp);
01266
01267     hcryp->CrypInCount = Size;
01268     hcryp->pCrypInBuffPtr = pPlainData;
01269     hcryp->pCrypOutBuffPtr = pCypherData;
01270     hcryp->CrypOutCount = Size;
01271
01272     /* Change the CRYP state */
01273     hcryp->State = HAL_CRYP_STATE_BUSY;
01274
01275     /* Check if initialization phase has already been performed */
01276     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01277     {
01278       /* Set the key */
01279       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01280
01281       /* Set the CRYP peripheral in AES CBC mode */
01282       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
01283
01284       /* Set the Initialization Vector */
01285       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01286
01287       /* Flush FIFO */
01288       __HAL_CRYP_FIFO_FLUSH(hcryp);
01289
01290      /* Set the phase */
01291      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01292     }
01293     /* Enable Interrupts */
01294     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01295
01296     /* Enable CRYP */
01297     __HAL_CRYP_ENABLE(hcryp);
01298
01299     /* Return function status */
01300     return HAL_OK;
01301   }
01302   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01303   {
01304     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01305     /* Write the Input block in the IN FIFO */
01306     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01307     inputaddr+=4U;
01308     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01309     inputaddr+=4U;
01310     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01311     inputaddr+=4U;
01312     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01313     hcryp->pCrypInBuffPtr += 16U;
01314     hcryp->CrypInCount -= 16U;
01315     if(hcryp->CrypInCount == 0U)
01316     {
01317       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01318       /* Call the Input data transfer complete callback */
01319       HAL_CRYP_InCpltCallback(hcryp);
01320     }
01321   }
01322   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01323   {
01324     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01325     /* Read the Output block from the Output FIFO */
01326     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01327     outputaddr+=4U;
01328     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01329     outputaddr+=4U;
01330     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01331     outputaddr+=4U;
01332     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01333     hcryp->pCrypOutBuffPtr += 16U;
01334     hcryp->CrypOutCount -= 16U;
01335     if(hcryp->CrypOutCount == 0U)
01336     {
01337       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01338       /* Process Locked */
01339       __HAL_UNLOCK(hcryp);
01340       /* Change the CRYP state */
01341       hcryp->State = HAL_CRYP_STATE_READY;
01342       /* Call Input transfer complete callback */
01343       HAL_CRYP_OutCpltCallback(hcryp);
01344     }
01345   }
01346
01347   /* Return function status */
01348   return HAL_OK;
01349 }
01350
01351 /**
01352   * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
01353   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01354   *         the configuration information for CRYP module
01355   * @param  pPlainData: Pointer to the plaintext buffer
01356   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01357   * @param  pCypherData: Pointer to the cyphertext buffer
01358   * @retval HAL status
01359   */
01360 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01361 {
01362   uint32_t inputaddr;
01363   uint32_t outputaddr;
01364
01365   if(hcryp->State == HAL_CRYP_STATE_READY)
01366   {
01367     /* Process Locked */
01368     __HAL_LOCK(hcryp);
01369
01370     hcryp->CrypInCount = Size;
01371     hcryp->pCrypInBuffPtr = pPlainData;
01372     hcryp->pCrypOutBuffPtr = pCypherData;
01373     hcryp->CrypOutCount = Size;
01374
01375     /* Change the CRYP state */
01376     hcryp->State = HAL_CRYP_STATE_BUSY;
01377
01378     /* Check if initialization phase has already been performed */
01379     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01380     {
01381       /* Set the key */
01382       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01383
01384       /* Set the CRYP peripheral in AES CTR mode */
01385       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
01386
01387       /* Set the Initialization Vector */
01388       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01389
01390       /* Flush FIFO */
01391       __HAL_CRYP_FIFO_FLUSH(hcryp);
01392
01393      /* Set the phase */
01394      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01395     }
01396     /* Enable Interrupts */
01397     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01398
01399     /* Enable CRYP */
01400     __HAL_CRYP_ENABLE(hcryp);
01401
01402     /* Return function status */
01403     return HAL_OK;
01404   }
01405   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01406   {
01407     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01408     /* Write the Input block in the IN FIFO */
01409     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01410     inputaddr+=4U;
01411     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01412     inputaddr+=4U;
01413     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01414     inputaddr+=4U;
01415     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01416     hcryp->pCrypInBuffPtr += 16U;
01417     hcryp->CrypInCount -= 16U;
01418     if(hcryp->CrypInCount == 0U)
01419     {
01420       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01421       /* Call the Input data transfer complete callback */
01422       HAL_CRYP_InCpltCallback(hcryp);
01423     }
01424   }
01425   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01426   {
01427     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01428     /* Read the Output block from the Output FIFO */
01429     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01430     outputaddr+=4U;
01431     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01432     outputaddr+=4U;
01433     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01434     outputaddr+=4U;
01435     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01436     hcryp->pCrypOutBuffPtr += 16U;
01437     hcryp->CrypOutCount -= 16U;
01438     if(hcryp->CrypOutCount == 0U)
01439     {
01440       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01441       /* Process Unlocked */
01442       __HAL_UNLOCK(hcryp);
01443       /* Change the CRYP state */
01444       hcryp->State = HAL_CRYP_STATE_READY;
01445       /* Call Input transfer complete callback */
01446       HAL_CRYP_OutCpltCallback(hcryp);
01447     }
01448   }
01449
01450   /* Return function status */
01451   return HAL_OK;
01452 }
01453
01454
01455 /**
01456   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
01457   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01458   *         the configuration information for CRYP module
01459   * @param  pCypherData: Pointer to the cyphertext buffer
01460   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01461   * @param  pPlainData: Pointer to the plaintext buffer
01462   * @retval HAL status
01463   */
01464 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01465 {
01466   uint32_t tickstart = 0U;
01467
01468   uint32_t inputaddr;
01469   uint32_t outputaddr;
01470
01471   if(hcryp->State == HAL_CRYP_STATE_READY)
01472   {
01473     /* Process Locked */
01474     __HAL_LOCK(hcryp);
01475
01476     hcryp->CrypInCount = Size;
01477     hcryp->pCrypInBuffPtr = pCypherData;
01478     hcryp->pCrypOutBuffPtr = pPlainData;
01479     hcryp->CrypOutCount = Size;
01480
01481     /* Change the CRYP state */
01482     hcryp->State = HAL_CRYP_STATE_BUSY;
01483
01484   /* Check if initialization phase has already been performed */
01485   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01486   {
01487     /* Set the key */
01488     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01489
01490     /* Set the CRYP peripheral in AES Key mode */
01491     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
01492     /* Enable CRYP */
01493     __HAL_CRYP_ENABLE(hcryp);
01494
01495     /* Get tick */
01496     tickstart = HAL_GetTick();
01497
01498     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
01499     {
01500       /* Check for the Timeout */
01501       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
01502       {
01503         /* Change state */
01504         hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01505
01506         /* Process Unlocked */
01507         __HAL_UNLOCK(hcryp);
01508
01509         return HAL_TIMEOUT;
01510       }
01511     }
01512
01513     /* Reset the ALGOMODE bits*/
01514     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
01515
01516     /* Set the CRYP peripheral in AES ECB decryption mode */
01517     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
01518
01519     /* Flush FIFO */
01520     __HAL_CRYP_FIFO_FLUSH(hcryp);
01521
01522      /* Set the phase */
01523      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01524   }
01525
01526     /* Enable Interrupts */
01527     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01528
01529     /* Enable CRYP */
01530     __HAL_CRYP_ENABLE(hcryp);
01531
01532     /* Return function status */
01533     return HAL_OK;
01534   }
01535   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01536   {
01537     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01538     /* Write the Input block in the IN FIFO */
01539     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01540     inputaddr+=4U;
01541     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01542     inputaddr+=4U;
01543     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01544     inputaddr+=4U;
01545     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01546     hcryp->pCrypInBuffPtr += 16U;
01547     hcryp->CrypInCount -= 16U;
01548     if(hcryp->CrypInCount == 0U)
01549     {
01550       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01551       /* Call the Input data transfer complete callback */
01552       HAL_CRYP_InCpltCallback(hcryp);
01553     }
01554   }
01555   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01556   {
01557     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01558     /* Read the Output block from the Output FIFO */
01559     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01560     outputaddr+=4U;
01561     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01562     outputaddr+=4U;
01563     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01564     outputaddr+=4U;
01565     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01566     hcryp->pCrypOutBuffPtr += 16U;
01567     hcryp->CrypOutCount -= 16U;
01568     if(hcryp->CrypOutCount == 0U)
01569     {
01570       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01571       /* Process Unlocked */
01572       __HAL_UNLOCK(hcryp);
01573       /* Change the CRYP state */
01574       hcryp->State = HAL_CRYP_STATE_READY;
01575       /* Call Input transfer complete callback */
01576       HAL_CRYP_OutCpltCallback(hcryp);
01577     }
01578   }
01579
01580   /* Return function status */
01581   return HAL_OK;
01582 }
01583
01584 /**
01585   * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
01586   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01587   *         the configuration information for CRYP module
01588   * @param  pCypherData: Pointer to the cyphertext buffer
01589   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01590   * @param  pPlainData: Pointer to the plaintext buffer
01591   * @retval HAL status
01592   */
01593 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01594 {
01595
01596   uint32_t tickstart = 0U;
01597   uint32_t inputaddr;
01598   uint32_t outputaddr;
01599
01600   if(hcryp->State == HAL_CRYP_STATE_READY)
01601   {
01602     /* Process Locked */
01603     __HAL_LOCK(hcryp);
01604
01605     /* Get the buffer addresses and sizes */
01606     hcryp->CrypInCount = Size;
01607     hcryp->pCrypInBuffPtr = pCypherData;
01608     hcryp->pCrypOutBuffPtr = pPlainData;
01609     hcryp->CrypOutCount = Size;
01610
01611     /* Change the CRYP state */
01612     hcryp->State = HAL_CRYP_STATE_BUSY;
01613
01614     /* Check if initialization phase has already been performed */
01615     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01616     {
01617       /* Set the key */
01618       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01619
01620       /* Set the CRYP peripheral in AES Key mode */
01621       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
01622
01623       /* Enable CRYP */
01624       __HAL_CRYP_ENABLE(hcryp);
01625
01626     /* Get tick */
01627     tickstart = HAL_GetTick();
01628
01629     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
01630     {
01631       /* Check for the Timeout */
01632       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
01633       {
01634         /* Change state */
01635         hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01636
01637         /* Process Unlocked */
01638         __HAL_UNLOCK(hcryp);
01639
01640         return HAL_TIMEOUT;
01641       }
01642     }
01643
01644       /* Reset the ALGOMODE bits*/
01645       CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
01646
01647       /* Set the CRYP peripheral in AES CBC decryption mode */
01648       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
01649
01650       /* Set the Initialization Vector */
01651       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01652
01653       /* Flush FIFO */
01654       __HAL_CRYP_FIFO_FLUSH(hcryp);
01655
01656       /* Enable CRYP */
01657       __HAL_CRYP_ENABLE(hcryp);
01658
01659       /* Set the phase */
01660       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01661     }
01662
01663     /* Enable Interrupts */
01664     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01665
01666     /* Enable CRYP */
01667     __HAL_CRYP_ENABLE(hcryp);
01668
01669     /* Return function status */
01670     return HAL_OK;
01671   }
01672   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01673   {
01674     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01675     /* Write the Input block in the IN FIFO */
01676     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01677     inputaddr+=4U;
01678     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01679     inputaddr+=4U;
01680     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01681     inputaddr+=4U;
01682     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01683     hcryp->pCrypInBuffPtr += 16U;
01684     hcryp->CrypInCount -= 16U;
01685     if(hcryp->CrypInCount == 0U)
01686     {
01687       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01688       /* Call the Input data transfer complete callback */
01689       HAL_CRYP_InCpltCallback(hcryp);
01690     }
01691   }
01692   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01693   {
01694     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01695     /* Read the Output block from the Output FIFO */
01696     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01697     outputaddr+=4U;
01698     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01699     outputaddr+=4U;
01700     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01701     outputaddr+=4U;
01702     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01703     hcryp->pCrypOutBuffPtr += 16U;
01704     hcryp->CrypOutCount -= 16U;
01705     if(hcryp->CrypOutCount == 0U)
01706     {
01707       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01708       /* Process Unlocked */
01709       __HAL_UNLOCK(hcryp);
01710       /* Change the CRYP state */
01711       hcryp->State = HAL_CRYP_STATE_READY;
01712       /* Call Input transfer complete callback */
01713       HAL_CRYP_OutCpltCallback(hcryp);
01714     }
01715   }
01716
01717   /* Return function status */
01718   return HAL_OK;
01719 }
01720
01721 /**
01722   * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
01723   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01724   *         the configuration information for CRYP module
01725   * @param  pCypherData: Pointer to the cyphertext buffer
01726   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01727   * @param  pPlainData: Pointer to the plaintext buffer
01728   * @retval HAL status
01729   */
01730 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01731 {
01732   uint32_t inputaddr;
01733   uint32_t outputaddr;
01734
01735   if(hcryp->State == HAL_CRYP_STATE_READY)
01736   {
01737     /* Process Locked */
01738     __HAL_LOCK(hcryp);
01739
01740     /* Get the buffer addresses and sizes */
01741     hcryp->CrypInCount = Size;
01742     hcryp->pCrypInBuffPtr = pCypherData;
01743     hcryp->pCrypOutBuffPtr = pPlainData;
01744     hcryp->CrypOutCount = Size;
01745
01746     /* Change the CRYP state */
01747     hcryp->State = HAL_CRYP_STATE_BUSY;
01748
01749     /* Check if initialization phase has already been performed */
01750     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01751     {
01752       /* Set the key */
01753       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01754
01755       /* Set the CRYP peripheral in AES CTR mode */
01756       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
01757
01758       /* Set the Initialization Vector */
01759       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01760
01761       /* Flush FIFO */
01762       __HAL_CRYP_FIFO_FLUSH(hcryp);
01763
01764       /* Set the phase */
01765       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01766     }
01767
01768     /* Enable Interrupts */
01769     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01770
01771     /* Enable CRYP */
01772     __HAL_CRYP_ENABLE(hcryp);
01773
01774     /* Return function status */
01775     return HAL_OK;
01776   }
01777   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01778   {
01779     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01780     /* Write the Input block in the IN FIFO */
01781     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01782     inputaddr+=4U;
01783     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01784     inputaddr+=4U;
01785     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01786     inputaddr+=4U;
01787     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01788     hcryp->pCrypInBuffPtr += 16U;
01789     hcryp->CrypInCount -= 16U;
01790     if(hcryp->CrypInCount == 0U)
01791     {
01792       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01793       /* Call the Input data transfer complete callback */
01794       HAL_CRYP_InCpltCallback(hcryp);
01795     }
01796   }
01797   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01798   {
01799     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01800     /* Read the Output block from the Output FIFO */
01801     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01802     outputaddr+=4U;
01803     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01804     outputaddr+=4U;
01805     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01806     outputaddr+=4U;
01807     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01808     hcryp->pCrypOutBuffPtr += 16U;
01809     hcryp->CrypOutCount -= 16U;
01810     if(hcryp->CrypOutCount == 0U)
01811     {
01812       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01813       /* Process Unlocked */
01814       __HAL_UNLOCK(hcryp);
01815       /* Change the CRYP state */
01816       hcryp->State = HAL_CRYP_STATE_READY;
01817       /* Call Input transfer complete callback */
01818       HAL_CRYP_OutCpltCallback(hcryp);
01819     }
01820   }
01821
01822   /* Return function status */
01823   return HAL_OK;
01824 }
01825
01826 /**
01827   * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
01828   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01829   *         the configuration information for CRYP module
01830   * @param  pPlainData: Pointer to the plaintext buffer
01831   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
01832   * @param  pCypherData: Pointer to the cyphertext buffer
01833   * @retval HAL status
01834   */
01835 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01836 {
01837   uint32_t inputaddr;
01838   uint32_t outputaddr;
01839
01840   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
01841   {
01842     /* Process Locked */
01843     __HAL_LOCK(hcryp);
01844
01845     inputaddr  = (uint32_t)pPlainData;
01846     outputaddr = (uint32_t)pCypherData;
01847
01848     /* Change the CRYP state */
01849     hcryp->State = HAL_CRYP_STATE_BUSY;
01850
01851     /* Check if initialization phase has already been performed */
01852     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01853     {
01854       /* Set the key */
01855       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01856
01857       /* Set the CRYP peripheral in AES ECB mode */
01858       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
01859
01860       /* Flush FIFO */
01861       __HAL_CRYP_FIFO_FLUSH(hcryp);
01862
01863      /* Set the phase */
01864      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01865     }
01866     /* Set the input and output addresses and start DMA transfer */
01867     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
01868
01869     /* Process Unlocked */
01870     __HAL_UNLOCK(hcryp);
01871
01872     /* Return function status */
01873     return HAL_OK;
01874   }
01875   else
01876   {
01877     return HAL_ERROR;
01878   }
01879 }
01880
01881 /**
01882   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
01883   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01884   *         the configuration information for CRYP module
01885   * @param  pPlainData: Pointer to the plaintext buffer
01886   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01887   * @param  pCypherData: Pointer to the cyphertext buffer
01888   * @retval HAL status
01889   */
01890 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01891 {
01892   uint32_t inputaddr;
01893   uint32_t outputaddr;
01894
01895   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
01896   {
01897     /* Process Locked */
01898     __HAL_LOCK(hcryp);
01899
01900     inputaddr  = (uint32_t)pPlainData;
01901     outputaddr = (uint32_t)pCypherData;
01902
01903     /* Change the CRYP state */
01904     hcryp->State = HAL_CRYP_STATE_BUSY;
01905
01906     /* Check if initialization phase has already been performed */
01907     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01908     {
01909       /* Set the key */
01910       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01911
01912       /* Set the CRYP peripheral in AES ECB mode */
01913       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
01914
01915       /* Set the Initialization Vector */
01916       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01917
01918       /* Flush FIFO */
01919       __HAL_CRYP_FIFO_FLUSH(hcryp);
01920
01921        /* Set the phase */
01922        hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01923      }
01924      /* Set the input and output addresses and start DMA transfer */
01925      CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
01926
01927      /* Process Unlocked */
01928      __HAL_UNLOCK(hcryp);
01929
01930      /* Return function status */
01931      return HAL_OK;
01932   }
01933   else
01934   {
01935     return HAL_ERROR;
01936   }
01937 }
01938
01939 /**
01940   * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
01941   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01942   *         the configuration information for CRYP module
01943   * @param  pPlainData: Pointer to the plaintext buffer
01944   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
01945   * @param  pCypherData: Pointer to the cyphertext buffer
01946   * @retval HAL status
01947   */
01948 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01949 {
01950   uint32_t inputaddr;
01951   uint32_t outputaddr;
01952
01953   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
01954   {
01955     /* Process Locked */
01956     __HAL_LOCK(hcryp);
01957
01958     inputaddr  = (uint32_t)pPlainData;
01959     outputaddr = (uint32_t)pCypherData;
01960
01961   /* Change the CRYP state */
01962   hcryp->State = HAL_CRYP_STATE_BUSY;
01963
01964     /* Check if initialization phase has already been performed */
01965     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01966     {
01967       /* Set the key */
01968       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01969
01970       /* Set the CRYP peripheral in AES ECB mode */
01971       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
01972
01973       /* Set the Initialization Vector */
01974       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
01975
01976       /* Flush FIFO */
01977       __HAL_CRYP_FIFO_FLUSH(hcryp);
01978
01979        /* Set the phase */
01980        hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01981     }
01982
01983     /* Set the input and output addresses and start DMA transfer */
01984     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
01985
01986     /* Process Unlocked */
01987     __HAL_UNLOCK(hcryp);
01988
01989     /* Return function status */
01990     return HAL_OK;
01991   }
01992   else
01993   {
01994     return HAL_ERROR;
01995   }
01996 }
01997
01998 /**
01999   * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
02000   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02001   *         the configuration information for CRYP module
02002   * @param  pCypherData: Pointer to the cyphertext buffer
02003   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
02004   * @param  pPlainData: Pointer to the plaintext buffer
02005   * @retval HAL status
02006   */
02007 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02008 {
02009   uint32_t tickstart = 0U;
02010   uint32_t inputaddr;
02011   uint32_t outputaddr;
02012
02013   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02014   {
02015     /* Process Locked */
02016     __HAL_LOCK(hcryp);
02017
02018     inputaddr  = (uint32_t)pCypherData;
02019     outputaddr = (uint32_t)pPlainData;
02020
02021     /* Change the CRYP state */
02022     hcryp->State = HAL_CRYP_STATE_BUSY;
02023
02024     /* Check if initialization phase has already been performed */
02025     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02026     {
02027     /* Set the key */
02028     CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02029
02030     /* Set the CRYP peripheral in AES Key mode */
02031     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
02032
02033     /* Enable CRYP */
02034     __HAL_CRYP_ENABLE(hcryp);
02035
02036     /* Get tick */
02037     tickstart = HAL_GetTick();
02038
02039     while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
02040     {
02041       /* Check for the Timeout */
02042       if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
02043       {
02044         /* Change state */
02045         hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02046
02047         /* Process Unlocked */
02048         __HAL_UNLOCK(hcryp);
02049
02050         return HAL_TIMEOUT;
02051       }
02052     }
02053
02054     /* Reset the ALGOMODE bits*/
02055     CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
02056
02057     /* Set the CRYP peripheral in AES ECB decryption mode */
02058     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
02059
02060     /* Flush FIFO */
02061     __HAL_CRYP_FIFO_FLUSH(hcryp);
02062
02063      /* Set the phase */
02064      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02065     }
02066
02067     /* Set the input and output addresses and start DMA transfer */
02068     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02069
02070      /* Process Unlocked */
02071      __HAL_UNLOCK(hcryp);
02072
02073     /* Return function status */
02074     return HAL_OK;
02075   }
02076   else
02077   {
02078     return HAL_ERROR;
02079   }
02080 }
02081
02082 /**
02083   * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
02084   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02085   *         the configuration information for CRYP module
02086   * @param  pCypherData: Pointer to the cyphertext buffer
02087   * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
02088   * @param  pPlainData: Pointer to the plaintext buffer
02089   * @retval HAL status
02090   */
02091 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02092 {
02093   uint32_t tickstart = 0U;
02094   uint32_t inputaddr;
02095   uint32_t outputaddr;
02096
02097   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02098   {
02099     /* Process Locked */
02100     __HAL_LOCK(hcryp);
02101
02102     inputaddr  = (uint32_t)pCypherData;
02103     outputaddr = (uint32_t)pPlainData;
02104
02105     /* Change the CRYP state */
02106     hcryp->State = HAL_CRYP_STATE_BUSY;
02107
02108     /* Check if initialization phase has already been performed */
02109     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02110     {
02111       /* Set the key */
02112       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02113
02114       /* Set the CRYP peripheral in AES Key mode */
02115       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
02116
02117       /* Enable CRYP */
02118       __HAL_CRYP_ENABLE(hcryp);
02119
02120       /* Get tick */
02121       tickstart = HAL_GetTick();
02122
02123       while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
02124       {
02125         /* Check for the Timeout */
02126         if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
02127         {
02128           /* Change state */
02129           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02130
02131           /* Process Unlocked */
02132           __HAL_UNLOCK(hcryp);
02133
02134           return HAL_TIMEOUT;
02135         }
02136       }
02137
02138       /* Reset the ALGOMODE bits*/
02139       CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
02140
02141       /* Set the CRYP peripheral in AES CBC decryption mode */
02142       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
02143
02144       /* Set the Initialization Vector */
02145       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
02146
02147       /* Flush FIFO */
02148       __HAL_CRYP_FIFO_FLUSH(hcryp);
02149
02150       /* Set the phase */
02151       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02152     }
02153
02154     /* Set the input and output addresses and start DMA transfer */
02155     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02156
02157     /* Process Unlocked */
02158     __HAL_UNLOCK(hcryp);
02159
02160     /* Return function status */
02161     return HAL_OK;
02162   }
02163   else
02164   {
02165     return HAL_ERROR;
02166   }
02167 }
02168
02169 /**
02170   * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
02171   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02172   *         the configuration information for CRYP module
02173   * @param  pCypherData: Pointer to the cyphertext buffer
02174   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02175   * @param  pPlainData: Pointer to the plaintext buffer
02176   * @retval HAL status
02177   */
02178 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02179 {
02180   uint32_t inputaddr;
02181   uint32_t outputaddr;
02182
02183   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02184   {
02185     /* Process Locked */
02186     __HAL_LOCK(hcryp);
02187
02188     inputaddr  = (uint32_t)pCypherData;
02189     outputaddr = (uint32_t)pPlainData;
02190
02191     /* Change the CRYP state */
02192     hcryp->State = HAL_CRYP_STATE_BUSY;
02193
02194     /* Check if initialization phase has already been performed */
02195     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02196     {
02197       /* Set the key */
02198       CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02199
02200       /* Set the CRYP peripheral in AES CTR mode */
02201       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
02202
02203       /* Set the Initialization Vector */
02204       CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
02205
02206       /* Flush FIFO */
02207       __HAL_CRYP_FIFO_FLUSH(hcryp);
02208
02209       /* Set the phase */
02210       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02211     }
02212
02213     /* Set the input and output addresses and start DMA transfer */
02214     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02215
02216     /* Process Unlocked */
02217     __HAL_UNLOCK(hcryp);
02218
02219     /* Return function status */
02220     return HAL_OK;
02221   }
02222   else
02223   {
02224     return HAL_ERROR;
02225   }
02226 }
02227
02228
02229 /**
02230   * @}
02231   */
02232
02233 /** @defgroup CRYP_Exported_Functions_Group3 DES processing functions
02234  *  @brief   processing functions.
02235  *
02236 @verbatim
02237   ==============================================================================
02238                       ##### DES processing functions #####
02239   ==============================================================================
02240     [..]  This section provides functions allowing to:
02241       (+) Encrypt plaintext using DES using ECB or CBC chaining modes
02242       (+) Decrypt cyphertext using ECB or CBC chaining modes
02243     [..]  Three processing functions are available:
02244       (+) Polling mode
02245       (+) Interrupt mode
02246       (+) DMA mode
02247
02248 @endverbatim
02249   * @{
02250   */
02251
02252 /**
02253   * @brief  Initializes the CRYP peripheral in DES ECB encryption mode.
02254   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02255   *         the configuration information for CRYP module
02256   * @param  pPlainData: Pointer to the plaintext buffer
02257   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02258   * @param  pCypherData: Pointer to the cyphertext buffer
02259   * @param  Timeout: Specify Timeout value
02260   * @retval HAL status
02261   */
02262 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
02263 {
02264   /* Process Locked */
02265   __HAL_LOCK(hcryp);
02266
02267   /* Change the CRYP state */
02268   hcryp->State = HAL_CRYP_STATE_BUSY;
02269
02270   /* Set CRYP peripheral in DES ECB encryption mode */
02271   CRYP_SetDESECBMode(hcryp, 0U);
02272
02273   /* Enable CRYP */
02274   __HAL_CRYP_ENABLE(hcryp);
02275
02276   /* Write Plain Data and Get Cypher Data */
02277   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
02278   {
02279     return HAL_TIMEOUT;
02280   }
02281
02282   /* Change the CRYP state */
02283   hcryp->State = HAL_CRYP_STATE_READY;
02284
02285   /* Process Unlocked */
02286   __HAL_UNLOCK(hcryp);
02287
02288   /* Return function status */
02289   return HAL_OK;
02290 }
02291
02292 /**
02293   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
02294   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02295   *         the configuration information for CRYP module
02296   * @param  pCypherData: Pointer to the cyphertext buffer
02297   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02298   * @param  pPlainData: Pointer to the plaintext buffer
02299   * @param  Timeout: Specify Timeout value
02300   * @retval HAL status
02301   */
02302 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
02303 {
02304   /* Process Locked */
02305   __HAL_LOCK(hcryp);
02306
02307   /* Change the CRYP state */
02308   hcryp->State = HAL_CRYP_STATE_BUSY;
02309
02310   /* Set CRYP peripheral in DES ECB decryption mode */
02311   CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
02312
02313   /* Enable CRYP */
02314   __HAL_CRYP_ENABLE(hcryp);
02315
02316   /* Write Plain Data and Get Cypher Data */
02317   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
02318   {
02319     return HAL_TIMEOUT;
02320   }
02321
02322   /* Change the CRYP state */
02323   hcryp->State = HAL_CRYP_STATE_READY;
02324
02325   /* Process Unlocked */
02326   __HAL_UNLOCK(hcryp);
02327
02328   /* Return function status */
02329   return HAL_OK;
02330 }
02331
02332 /**
02333   * @brief  Initializes the CRYP peripheral in DES CBC encryption mode.
02334   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02335   *         the configuration information for CRYP module
02336   * @param  pPlainData: Pointer to the plaintext buffer
02337   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02338   * @param  pCypherData: Pointer to the cyphertext buffer
02339   * @param  Timeout: Specify Timeout value
02340   * @retval HAL status
02341   */
02342 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
02343 {
02344   /* Process Locked */
02345   __HAL_LOCK(hcryp);
02346
02347   /* Change the CRYP state */
02348   hcryp->State = HAL_CRYP_STATE_BUSY;
02349
02350   /* Set CRYP peripheral in DES CBC encryption mode */
02351   CRYP_SetDESCBCMode(hcryp, 0U);
02352
02353   /* Enable CRYP */
02354   __HAL_CRYP_ENABLE(hcryp);
02355
02356   /* Write Plain Data and Get Cypher Data */
02357   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
02358   {
02359     return HAL_TIMEOUT;
02360   }
02361
02362   /* Change the CRYP state */
02363   hcryp->State = HAL_CRYP_STATE_READY;
02364
02365   /* Process Unlocked */
02366   __HAL_UNLOCK(hcryp);
02367
02368   /* Return function status */
02369   return HAL_OK;
02370 }
02371
02372 /**
02373   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
02374   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02375   *         the configuration information for CRYP module
02376   * @param  pCypherData: Pointer to the cyphertext buffer
02377   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02378   * @param  pPlainData: Pointer to the plaintext buffer
02379   * @param  Timeout: Specify Timeout value
02380   * @retval HAL status
02381   */
02382 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
02383 {
02384   /* Process Locked */
02385   __HAL_LOCK(hcryp);
02386
02387   /* Change the CRYP state */
02388   hcryp->State = HAL_CRYP_STATE_BUSY;
02389
02390   /* Set CRYP peripheral in DES CBC decryption mode */
02391   CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
02392
02393   /* Enable CRYP */
02394   __HAL_CRYP_ENABLE(hcryp);
02395
02396   /* Write Plain Data and Get Cypher Data */
02397   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
02398   {
02399     return HAL_TIMEOUT;
02400   }
02401
02402   /* Change the CRYP state */
02403   hcryp->State = HAL_CRYP_STATE_READY;
02404
02405   /* Process Unlocked */
02406   __HAL_UNLOCK(hcryp);
02407
02408   /* Return function status */
02409   return HAL_OK;
02410 }
02411
02412 /**
02413   * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using IT.
02414   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02415   *         the configuration information for CRYP module
02416   * @param  pPlainData: Pointer to the plaintext buffer
02417   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02418   * @param  pCypherData: Pointer to the cyphertext buffer
02419   * @retval HAL status
02420   */
02421 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02422 {
02423   uint32_t inputaddr;
02424   uint32_t outputaddr;
02425
02426   if(hcryp->State == HAL_CRYP_STATE_READY)
02427   {
02428     /* Process Locked */
02429     __HAL_LOCK(hcryp);
02430
02431     hcryp->CrypInCount = Size;
02432     hcryp->pCrypInBuffPtr = pPlainData;
02433     hcryp->pCrypOutBuffPtr = pCypherData;
02434     hcryp->CrypOutCount = Size;
02435
02436     /* Change the CRYP state */
02437     hcryp->State = HAL_CRYP_STATE_BUSY;
02438
02439     /* Set CRYP peripheral in DES ECB encryption mode */
02440     CRYP_SetDESECBMode(hcryp, 0U);
02441
02442     /* Enable Interrupts */
02443     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02444
02445     /* Enable CRYP */
02446     __HAL_CRYP_ENABLE(hcryp);
02447
02448     /* Return function status */
02449     return HAL_OK;
02450   }
02451   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02452   {
02453     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02454     /* Write the Input block in the IN FIFO */
02455     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02456     inputaddr+=4U;
02457     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02458
02459     hcryp->pCrypInBuffPtr += 8U;
02460     hcryp->CrypInCount -= 8U;
02461     if(hcryp->CrypInCount == 0U)
02462     {
02463       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02464       /* Call the Input data transfer complete callback */
02465       HAL_CRYP_InCpltCallback(hcryp);
02466     }
02467   }
02468   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02469   {
02470     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02471     /* Read the Output block from the Output FIFO */
02472     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02473     outputaddr+=4U;
02474     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02475
02476     hcryp->pCrypOutBuffPtr += 8U;
02477     hcryp->CrypOutCount -= 8U;
02478     if(hcryp->CrypOutCount == 0U)
02479     {
02480       /* Disable IT */
02481       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02482       /* Disable CRYP */
02483       __HAL_CRYP_DISABLE(hcryp);
02484       /* Process Unlocked */
02485       __HAL_UNLOCK(hcryp);
02486       /* Change the CRYP state */
02487       hcryp->State = HAL_CRYP_STATE_READY;
02488       /* Call Input transfer complete callback */
02489       HAL_CRYP_OutCpltCallback(hcryp);
02490     }
02491   }
02492
02493   /* Return function status */
02494   return HAL_OK;
02495 }
02496
02497 /**
02498   * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
02499   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02500   *         the configuration information for CRYP module
02501   * @param  pPlainData: Pointer to the plaintext buffer
02502   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02503   * @param  pCypherData: Pointer to the cyphertext buffer
02504   * @retval HAL status
02505   */
02506 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02507 {
02508   uint32_t inputaddr;
02509   uint32_t outputaddr;
02510
02511   if(hcryp->State == HAL_CRYP_STATE_READY)
02512   {
02513     /* Process Locked */
02514     __HAL_LOCK(hcryp);
02515
02516     hcryp->CrypInCount = Size;
02517     hcryp->pCrypInBuffPtr = pPlainData;
02518     hcryp->pCrypOutBuffPtr = pCypherData;
02519     hcryp->CrypOutCount = Size;
02520
02521     /* Change the CRYP state */
02522     hcryp->State = HAL_CRYP_STATE_BUSY;
02523
02524     /* Set CRYP peripheral in DES CBC encryption mode */
02525     CRYP_SetDESCBCMode(hcryp, 0U);
02526
02527     /* Enable Interrupts */
02528     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02529
02530     /* Enable CRYP */
02531     __HAL_CRYP_ENABLE(hcryp);
02532
02533     /* Return function status */
02534     return HAL_OK;
02535   }
02536
02537   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02538   {
02539     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02540     /* Write the Input block in the IN FIFO */
02541     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02542     inputaddr+=4U;
02543     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02544
02545     hcryp->pCrypInBuffPtr += 8U;
02546     hcryp->CrypInCount -= 8U;
02547     if(hcryp->CrypInCount == 0U)
02548     {
02549       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02550       /* Call the Input data transfer complete callback */
02551       HAL_CRYP_InCpltCallback(hcryp);
02552     }
02553   }
02554   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02555   {
02556     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02557     /* Read the Output block from the Output FIFO */
02558     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02559     outputaddr+=4U;
02560     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02561
02562     hcryp->pCrypOutBuffPtr += 8U;
02563     hcryp->CrypOutCount -= 8U;
02564     if(hcryp->CrypOutCount == 0U)
02565     {
02566       /* Disable IT */
02567       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02568       /* Disable CRYP */
02569       __HAL_CRYP_DISABLE(hcryp);
02570       /* Process Unlocked */
02571       __HAL_UNLOCK(hcryp);
02572       /* Change the CRYP state */
02573       hcryp->State = HAL_CRYP_STATE_READY;
02574       /* Call Input transfer complete callback */
02575       HAL_CRYP_OutCpltCallback(hcryp);
02576     }
02577   }
02578
02579   /* Return function status */
02580   return HAL_OK;
02581 }
02582
02583 /**
02584   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using IT.
02585   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02586   *         the configuration information for CRYP module
02587   * @param  pPlainData: Pointer to the plaintext buffer
02588   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02589   * @param  pCypherData: Pointer to the cyphertext buffer
02590   * @retval HAL status
02591   */
02592 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02593 {
02594   uint32_t inputaddr;
02595   uint32_t outputaddr;
02596
02597   if(hcryp->State == HAL_CRYP_STATE_READY)
02598   {
02599     /* Process Locked */
02600     __HAL_LOCK(hcryp);
02601
02602     hcryp->CrypInCount = Size;
02603     hcryp->pCrypInBuffPtr = pCypherData;
02604     hcryp->pCrypOutBuffPtr = pPlainData;
02605     hcryp->CrypOutCount = Size;
02606
02607     /* Change the CRYP state */
02608     hcryp->State = HAL_CRYP_STATE_BUSY;
02609
02610     /* Set CRYP peripheral in DES ECB decryption mode */
02611     CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
02612
02613     /* Enable Interrupts */
02614     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02615
02616     /* Enable CRYP */
02617     __HAL_CRYP_ENABLE(hcryp);
02618
02619     /* Return function status */
02620     return HAL_OK;
02621   }
02622   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02623   {
02624     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02625     /* Write the Input block in the IN FIFO */
02626     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02627     inputaddr+=4U;
02628     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02629
02630     hcryp->pCrypInBuffPtr += 8U;
02631     hcryp->CrypInCount -= 8U;
02632     if(hcryp->CrypInCount == 0U)
02633     {
02634       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02635       /* Call the Input data transfer complete callback */
02636       HAL_CRYP_InCpltCallback(hcryp);
02637     }
02638   }
02639   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02640   {
02641     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02642     /* Read the Output block from the Output FIFO */
02643     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02644     outputaddr+=4U;
02645     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02646
02647     hcryp->pCrypOutBuffPtr += 8U;
02648     hcryp->CrypOutCount -= 8U;
02649     if(hcryp->CrypOutCount == 0U)
02650     {
02651       /* Disable IT */
02652       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02653       /* Disable CRYP */
02654       __HAL_CRYP_DISABLE(hcryp);
02655       /* Process Unlocked */
02656       __HAL_UNLOCK(hcryp);
02657       /* Change the CRYP state */
02658       hcryp->State = HAL_CRYP_STATE_READY;
02659       /* Call Input transfer complete callback */
02660       HAL_CRYP_OutCpltCallback(hcryp);
02661     }
02662   }
02663
02664   /* Return function status */
02665   return HAL_OK;
02666 }
02667
02668 /**
02669   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
02670   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02671   *         the configuration information for CRYP module
02672   * @param  pPlainData: Pointer to the plaintext buffer
02673   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02674   * @param  pCypherData: Pointer to the cyphertext buffer
02675   * @retval HAL status
02676   */
02677 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02678 {
02679   uint32_t inputaddr;
02680   uint32_t outputaddr;
02681
02682   if(hcryp->State == HAL_CRYP_STATE_READY)
02683   {
02684     /* Process Locked */
02685     __HAL_LOCK(hcryp);
02686
02687     hcryp->CrypInCount = Size;
02688     hcryp->pCrypInBuffPtr = pCypherData;
02689     hcryp->pCrypOutBuffPtr = pPlainData;
02690     hcryp->CrypOutCount = Size;
02691
02692     /* Change the CRYP state */
02693     hcryp->State = HAL_CRYP_STATE_BUSY;
02694
02695     /* Set CRYP peripheral in DES CBC decryption mode */
02696     CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
02697
02698     /* Enable Interrupts */
02699     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02700
02701     /* Enable CRYP */
02702     __HAL_CRYP_ENABLE(hcryp);
02703
02704     /* Return function status */
02705     return HAL_OK;
02706   }
02707   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02708   {
02709     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02710     /* Write the Input block in the IN FIFO */
02711     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02712     inputaddr+=4U;
02713     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02714
02715     hcryp->pCrypInBuffPtr += 8U;
02716     hcryp->CrypInCount -= 8U;
02717     if(hcryp->CrypInCount == 0U)
02718     {
02719       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02720       /* Call the Input data transfer complete callback */
02721       HAL_CRYP_InCpltCallback(hcryp);
02722     }
02723   }
02724   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02725   {
02726     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02727     /* Read the Output block from the Output FIFO */
02728     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02729     outputaddr+=4U;
02730     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02731
02732     hcryp->pCrypOutBuffPtr += 8U;
02733     hcryp->CrypOutCount -= 8U;
02734     if(hcryp->CrypOutCount == 0U)
02735     {
02736       /* Disable IT */
02737       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02738       /* Disable CRYP */
02739       __HAL_CRYP_DISABLE(hcryp);
02740       /* Process Unlocked */
02741       __HAL_UNLOCK(hcryp);
02742       /* Change the CRYP state */
02743       hcryp->State = HAL_CRYP_STATE_READY;
02744       /* Call Input transfer complete callback */
02745       HAL_CRYP_OutCpltCallback(hcryp);
02746     }
02747   }
02748
02749   /* Return function status */
02750   return HAL_OK;
02751 }
02752
02753 /**
02754   * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
02755   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02756   *         the configuration information for CRYP module
02757   * @param  pPlainData: Pointer to the plaintext buffer
02758   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02759   * @param  pCypherData: Pointer to the cyphertext buffer
02760   * @retval HAL status
02761   */
02762 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02763 {
02764   uint32_t inputaddr;
02765   uint32_t outputaddr;
02766
02767   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02768   {
02769     /* Process Locked */
02770     __HAL_LOCK(hcryp);
02771
02772     inputaddr  = (uint32_t)pPlainData;
02773     outputaddr = (uint32_t)pCypherData;
02774
02775     /* Change the CRYP state */
02776     hcryp->State = HAL_CRYP_STATE_BUSY;
02777
02778     /* Set CRYP peripheral in DES ECB encryption mode */
02779     CRYP_SetDESECBMode(hcryp, 0U);
02780
02781     /* Set the input and output addresses and start DMA transfer */
02782     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02783
02784     /* Process Unlocked */
02785     __HAL_UNLOCK(hcryp);
02786
02787     /* Return function status */
02788     return HAL_OK;
02789   }
02790   else
02791   {
02792     return HAL_ERROR;
02793   }
02794 }
02795
02796 /**
02797   * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
02798   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02799   *         the configuration information for CRYP module
02800   * @param  pPlainData: Pointer to the plaintext buffer
02801   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02802   * @param  pCypherData: Pointer to the cyphertext buffer
02803   * @retval HAL status
02804   */
02805 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02806 {
02807   uint32_t inputaddr;
02808   uint32_t outputaddr;
02809
02810   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02811   {
02812     /* Process Locked */
02813     __HAL_LOCK(hcryp);
02814
02815     inputaddr  = (uint32_t)pPlainData;
02816     outputaddr = (uint32_t)pCypherData;
02817
02818     /* Change the CRYP state */
02819     hcryp->State = HAL_CRYP_STATE_BUSY;
02820
02821     /* Set CRYP peripheral in DES CBC encryption mode */
02822     CRYP_SetDESCBCMode(hcryp, 0U);
02823
02824     /* Set the input and output addresses and start DMA transfer */
02825     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02826
02827     /* Process Unlocked */
02828     __HAL_UNLOCK(hcryp);
02829
02830     /* Return function status */
02831     return HAL_OK;
02832   }
02833   else
02834   {
02835     return HAL_ERROR;
02836   }
02837 }
02838
02839 /**
02840   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
02841   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02842   *         the configuration information for CRYP module
02843   * @param  pPlainData: Pointer to the plaintext buffer
02844   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02845   * @param  pCypherData: Pointer to the cyphertext buffer
02846   * @retval HAL status
02847   */
02848 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02849 {
02850   uint32_t inputaddr;
02851   uint32_t outputaddr;
02852
02853   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02854   {
02855     /* Process Locked */
02856     __HAL_LOCK(hcryp);
02857
02858     inputaddr  = (uint32_t)pCypherData;
02859     outputaddr = (uint32_t)pPlainData;
02860
02861     /* Change the CRYP state */
02862     hcryp->State = HAL_CRYP_STATE_BUSY;
02863
02864     /* Set CRYP peripheral in DES ECB decryption mode */
02865     CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
02866
02867     /* Set the input and output addresses and start DMA transfer */
02868     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02869
02870     /* Process Unlocked */
02871     __HAL_UNLOCK(hcryp);
02872
02873     /* Return function status */
02874     return HAL_OK;
02875   }
02876   else
02877   {
02878     return HAL_ERROR;
02879   }
02880 }
02881
02882 /**
02883   * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
02884   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02885   *         the configuration information for CRYP module
02886   * @param  pPlainData: Pointer to the plaintext buffer
02887   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02888   * @param  pCypherData: Pointer to the cyphertext buffer
02889   * @retval HAL status
02890   */
02891 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02892 {
02893   uint32_t inputaddr;
02894   uint32_t outputaddr;
02895
02896   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02897   {
02898     /* Process Locked */
02899     __HAL_LOCK(hcryp);
02900
02901     inputaddr  = (uint32_t)pCypherData;
02902     outputaddr = (uint32_t)pPlainData;
02903
02904     /* Change the CRYP state */
02905     hcryp->State = HAL_CRYP_STATE_BUSY;
02906
02907     /* Set CRYP peripheral in DES CBC decryption mode */
02908     CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
02909
02910     /* Set the input and output addresses and start DMA transfer */
02911     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02912
02913     /* Process Unlocked */
02914     __HAL_UNLOCK(hcryp);
02915
02916     /* Return function status */
02917     return HAL_OK;
02918   }
02919   else
02920   {
02921     return HAL_ERROR;
02922   }
02923 }
02924
02925 /**
02926   * @}
02927   */
02928
02929 /** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions
02930  *  @brief   processing functions.
02931  *
02932 @verbatim
02933   ==============================================================================
02934                       ##### TDES processing functions #####
02935   ==============================================================================
02936     [..]  This section provides functions allowing to:
02937       (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
02938       (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
02939     [..]  Three processing functions are available:
02940       (+) Polling mode
02941       (+) Interrupt mode
02942       (+) DMA mode
02943
02944 @endverbatim
02945   * @{
02946   */
02947
02948 /**
02949   * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode
02950   *         then encrypt pPlainData. The cypher data are available in pCypherData
02951   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02952   *         the configuration information for CRYP module
02953   * @param  pPlainData: Pointer to the plaintext buffer
02954   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02955   * @param  pCypherData: Pointer to the cyphertext buffer
02956   * @param  Timeout: Specify Timeout value
02957   * @retval HAL status
02958   */
02959 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
02960 {
02961   /* Process Locked */
02962   __HAL_LOCK(hcryp);
02963
02964   /* Change the CRYP state */
02965   hcryp->State = HAL_CRYP_STATE_BUSY;
02966
02967   /* Set CRYP peripheral in TDES ECB encryption mode */
02968   CRYP_SetTDESECBMode(hcryp, 0U);
02969
02970   /* Enable CRYP */
02971   __HAL_CRYP_ENABLE(hcryp);
02972
02973   /* Write Plain Data and Get Cypher Data */
02974   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
02975   {
02976     return HAL_TIMEOUT;
02977   }
02978
02979   /* Change the CRYP state */
02980   hcryp->State = HAL_CRYP_STATE_READY;
02981
02982   /* Process Unlocked */
02983   __HAL_UNLOCK(hcryp);
02984
02985   /* Return function status */
02986   return HAL_OK;
02987 }
02988
02989 /**
02990   * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode
02991   *         then decrypted pCypherData. The cypher data are available in pPlainData
02992   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02993   *         the configuration information for CRYP module
02994   * @param  pPlainData: Pointer to the plaintext buffer
02995   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
02996   * @param  pCypherData: Pointer to the cyphertext buffer
02997   * @param  Timeout: Specify Timeout value
02998   * @retval HAL status
02999   */
03000 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
03001 {
03002   /* Process Locked */
03003   __HAL_LOCK(hcryp);
03004
03005   /* Change the CRYP state */
03006   hcryp->State = HAL_CRYP_STATE_BUSY;
03007
03008   /* Set CRYP peripheral in TDES ECB decryption mode */
03009   CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
03010
03011   /* Enable CRYP */
03012   __HAL_CRYP_ENABLE(hcryp);
03013
03014   /* Write Cypher Data and Get Plain Data */
03015   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
03016   {
03017     return HAL_TIMEOUT;
03018   }
03019
03020   /* Change the CRYP state */
03021   hcryp->State = HAL_CRYP_STATE_READY;
03022
03023   /* Process Unlocked */
03024   __HAL_UNLOCK(hcryp);
03025
03026   /* Return function status */
03027   return HAL_OK;
03028 }
03029
03030 /**
03031   * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode
03032   *         then encrypt pPlainData. The cypher data are available in pCypherData
03033   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03034   *         the configuration information for CRYP module
03035   * @param  pPlainData: Pointer to the plaintext buffer
03036   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03037   * @param  pCypherData: Pointer to the cyphertext buffer
03038   * @param  Timeout: Specify Timeout value
03039   * @retval HAL status
03040   */
03041 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
03042 {
03043   /* Process Locked */
03044   __HAL_LOCK(hcryp);
03045
03046   /* Change the CRYP state */
03047   hcryp->State = HAL_CRYP_STATE_BUSY;
03048
03049   /* Set CRYP peripheral in TDES CBC encryption mode */
03050   CRYP_SetTDESCBCMode(hcryp, 0U);
03051
03052   /* Enable CRYP */
03053   __HAL_CRYP_ENABLE(hcryp);
03054
03055   /* Write Plain Data and Get Cypher Data */
03056   if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
03057   {
03058     return HAL_TIMEOUT;
03059   }
03060
03061   /* Change the CRYP state */
03062   hcryp->State = HAL_CRYP_STATE_READY;
03063
03064   /* Process Unlocked */
03065   __HAL_UNLOCK(hcryp);
03066
03067   /* Return function status */
03068   return HAL_OK;
03069 }
03070
03071 /**
03072   * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode
03073   *         then decrypted pCypherData. The cypher data are available in pPlainData
03074   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03075   *         the configuration information for CRYP module
03076   * @param  pCypherData: Pointer to the cyphertext buffer
03077   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03078   * @param  pPlainData: Pointer to the plaintext buffer
03079   * @param  Timeout: Specify Timeout value
03080   * @retval HAL status
03081   */
03082 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
03083 {
03084   /* Process Locked */
03085   __HAL_LOCK(hcryp);
03086
03087   /* Change the CRYP state */
03088   hcryp->State = HAL_CRYP_STATE_BUSY;
03089
03090   /* Set CRYP peripheral in TDES CBC decryption mode */
03091   CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
03092
03093   /* Enable CRYP */
03094   __HAL_CRYP_ENABLE(hcryp);
03095
03096   /* Write Cypher Data and Get Plain Data */
03097   if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
03098   {
03099     return HAL_TIMEOUT;
03100   }
03101
03102   /* Change the CRYP state */
03103   hcryp->State = HAL_CRYP_STATE_READY;
03104
03105   /* Process Unlocked */
03106   __HAL_UNLOCK(hcryp);
03107
03108   /* Return function status */
03109   return HAL_OK;
03110 }
03111
03112 /**
03113   * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
03114   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03115   *         the configuration information for CRYP module
03116   * @param  pPlainData: Pointer to the plaintext buffer
03117   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03118   * @param  pCypherData: Pointer to the cyphertext buffer
03119   * @retval HAL status
03120   */
03121 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03122 {
03123   uint32_t inputaddr;
03124   uint32_t outputaddr;
03125
03126   if(hcryp->State == HAL_CRYP_STATE_READY)
03127   {
03128     /* Process Locked */
03129     __HAL_LOCK(hcryp);
03130
03131     hcryp->CrypInCount = Size;
03132     hcryp->pCrypInBuffPtr = pPlainData;
03133     hcryp->pCrypOutBuffPtr = pCypherData;
03134     hcryp->CrypOutCount = Size;
03135
03136     /* Change the CRYP state */
03137     hcryp->State = HAL_CRYP_STATE_BUSY;
03138
03139     /* Set CRYP peripheral in TDES ECB encryption mode */
03140     CRYP_SetTDESECBMode(hcryp, 0U);
03141
03142     /* Enable Interrupts */
03143     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03144
03145     /* Enable CRYP */
03146     __HAL_CRYP_ENABLE(hcryp);
03147
03148     /* Return function status */
03149     return HAL_OK;
03150   }
03151   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03152   {
03153     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03154     /* Write the Input block in the IN FIFO */
03155     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03156     inputaddr+=4U;
03157     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03158
03159     hcryp->pCrypInBuffPtr += 8U;
03160     hcryp->CrypInCount -= 8U;
03161     if(hcryp->CrypInCount == 0U)
03162     {
03163       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03164       /* Call the Input data transfer complete callback */
03165       HAL_CRYP_InCpltCallback(hcryp);
03166     }
03167   }
03168   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03169   {
03170     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03171     /* Read the Output block from the Output FIFO */
03172     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03173     outputaddr+=4U;
03174     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03175
03176     hcryp->pCrypOutBuffPtr += 8U;
03177     hcryp->CrypOutCount -= 8U;
03178     if(hcryp->CrypOutCount == 0U)
03179     {
03180       /* Disable IT */
03181       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03182       /* Disable CRYP */
03183       __HAL_CRYP_DISABLE(hcryp);
03184       /* Process Unlocked */
03185       __HAL_UNLOCK(hcryp);
03186       /* Change the CRYP state */
03187       hcryp->State = HAL_CRYP_STATE_READY;
03188       /* Call the Output data transfer complete callback */
03189       HAL_CRYP_OutCpltCallback(hcryp);
03190     }
03191   }
03192
03193   /* Return function status */
03194   return HAL_OK;
03195 }
03196
03197 /**
03198   * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode.
03199   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03200   *         the configuration information for CRYP module
03201   * @param  pPlainData: Pointer to the plaintext buffer
03202   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03203   * @param  pCypherData: Pointer to the cyphertext buffer
03204   * @retval HAL status
03205   */
03206 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03207 {
03208   uint32_t inputaddr;
03209   uint32_t outputaddr;
03210
03211   if(hcryp->State == HAL_CRYP_STATE_READY)
03212   {
03213     /* Process Locked */
03214     __HAL_LOCK(hcryp);
03215
03216     hcryp->CrypInCount = Size;
03217     hcryp->pCrypInBuffPtr = pPlainData;
03218     hcryp->pCrypOutBuffPtr = pCypherData;
03219     hcryp->CrypOutCount = Size;
03220
03221     /* Change the CRYP state */
03222     hcryp->State = HAL_CRYP_STATE_BUSY;
03223
03224     /* Set CRYP peripheral in TDES CBC encryption mode */
03225     CRYP_SetTDESCBCMode(hcryp, 0U);
03226
03227     /* Enable Interrupts */
03228     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03229
03230     /* Enable CRYP */
03231     __HAL_CRYP_ENABLE(hcryp);
03232
03233     /* Return function status */
03234     return HAL_OK;
03235   }
03236   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03237   {
03238     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03239     /* Write the Input block in the IN FIFO */
03240     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03241     inputaddr+=4U;
03242     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03243
03244     hcryp->pCrypInBuffPtr += 8U;
03245     hcryp->CrypInCount -= 8U;
03246     if(hcryp->CrypInCount == 0U)
03247     {
03248       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03249       /* Call the Input data transfer complete callback */
03250       HAL_CRYP_InCpltCallback(hcryp);
03251     }
03252   }
03253   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03254   {
03255     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03256     /* Read the Output block from the Output FIFO */
03257     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03258     outputaddr+=4U;
03259     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03260
03261     hcryp->pCrypOutBuffPtr += 8U;
03262     hcryp->CrypOutCount -= 8U;
03263     if(hcryp->CrypOutCount == 0U)
03264     {
03265       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03266       /* Disable CRYP */
03267       __HAL_CRYP_DISABLE(hcryp);
03268       /* Process Unlocked */
03269       __HAL_UNLOCK(hcryp);
03270       /* Change the CRYP state */
03271       hcryp->State = HAL_CRYP_STATE_READY;
03272       /* Call Input transfer complete callback */
03273       HAL_CRYP_OutCpltCallback(hcryp);
03274     }
03275   }
03276
03277   /* Return function status */
03278   return HAL_OK;
03279 }
03280
03281 /**
03282   * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode.
03283   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03284   *         the configuration information for CRYP module
03285   * @param  pPlainData: Pointer to the plaintext buffer
03286   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03287   * @param  pCypherData: Pointer to the cyphertext buffer
03288   * @retval HAL status
03289   */
03290 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03291 {
03292   uint32_t inputaddr;
03293   uint32_t outputaddr;
03294
03295   if(hcryp->State == HAL_CRYP_STATE_READY)
03296   {
03297     /* Process Locked */
03298     __HAL_LOCK(hcryp);
03299
03300     hcryp->CrypInCount = Size;
03301     hcryp->pCrypInBuffPtr = pCypherData;
03302     hcryp->pCrypOutBuffPtr = pPlainData;
03303     hcryp->CrypOutCount = Size;
03304
03305     /* Change the CRYP state */
03306     hcryp->State = HAL_CRYP_STATE_BUSY;
03307
03308     /* Set CRYP peripheral in TDES ECB decryption mode */
03309     CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
03310
03311     /* Enable Interrupts */
03312     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03313
03314     /* Enable CRYP */
03315     __HAL_CRYP_ENABLE(hcryp);
03316
03317     /* Return function status */
03318     return HAL_OK;
03319   }
03320   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03321   {
03322     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03323     /* Write the Input block in the IN FIFO */
03324     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03325     inputaddr+=4U;
03326     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03327
03328     hcryp->pCrypInBuffPtr += 8U;
03329     hcryp->CrypInCount -= 8U;
03330     if(hcryp->CrypInCount == 0U)
03331     {
03332       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03333       /* Call the Input data transfer complete callback */
03334       HAL_CRYP_InCpltCallback(hcryp);
03335     }
03336   }
03337   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03338   {
03339     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03340     /* Read the Output block from the Output FIFO */
03341     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03342     outputaddr+=4U;
03343     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03344
03345     hcryp->pCrypOutBuffPtr += 8U;
03346     hcryp->CrypOutCount -= 8U;
03347     if(hcryp->CrypOutCount == 0U)
03348     {
03349       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03350       /* Disable CRYP */
03351       __HAL_CRYP_DISABLE(hcryp);
03352       /* Process Unlocked */
03353       __HAL_UNLOCK(hcryp);
03354       /* Change the CRYP state */
03355       hcryp->State = HAL_CRYP_STATE_READY;
03356       /* Call Input transfer complete callback */
03357       HAL_CRYP_OutCpltCallback(hcryp);
03358     }
03359   }
03360
03361   /* Return function status */
03362   return HAL_OK;
03363 }
03364
03365 /**
03366   * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode.
03367   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03368   *         the configuration information for CRYP module
03369   * @param  pCypherData: Pointer to the cyphertext buffer
03370   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03371   * @param  pPlainData: Pointer to the plaintext buffer
03372   * @retval HAL status
03373   */
03374 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03375 {
03376   uint32_t inputaddr;
03377   uint32_t outputaddr;
03378
03379   if(hcryp->State == HAL_CRYP_STATE_READY)
03380   {
03381     /* Process Locked */
03382     __HAL_LOCK(hcryp);
03383
03384     hcryp->CrypInCount = Size;
03385     hcryp->pCrypInBuffPtr = pCypherData;
03386     hcryp->pCrypOutBuffPtr = pPlainData;
03387     hcryp->CrypOutCount = Size;
03388
03389     /* Change the CRYP state */
03390     hcryp->State = HAL_CRYP_STATE_BUSY;
03391
03392     /* Set CRYP peripheral in TDES CBC decryption mode */
03393     CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
03394
03395     /* Enable Interrupts */
03396     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
03397
03398     /* Enable CRYP */
03399     __HAL_CRYP_ENABLE(hcryp);
03400
03401     /* Return function status */
03402     return HAL_OK;
03403   }
03404   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
03405   {
03406     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
03407     /* Write the Input block in the IN FIFO */
03408     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03409     inputaddr+=4U;
03410     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
03411
03412     hcryp->pCrypInBuffPtr += 8U;
03413     hcryp->CrypInCount -= 8U;
03414     if(hcryp->CrypInCount == 0U)
03415     {
03416       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
03417       /* Call the Input data transfer complete callback */
03418       HAL_CRYP_InCpltCallback(hcryp);
03419     }
03420   }
03421   else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
03422   {
03423     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
03424     /* Read the Output block from the Output FIFO */
03425     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03426     outputaddr+=4U;
03427     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
03428
03429     hcryp->pCrypOutBuffPtr += 8U;
03430     hcryp->CrypOutCount -= 8U;
03431     if(hcryp->CrypOutCount == 0U)
03432     {
03433       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
03434       /* Disable CRYP */
03435       __HAL_CRYP_DISABLE(hcryp);
03436       /* Process Unlocked */
03437       __HAL_UNLOCK(hcryp);
03438       /* Change the CRYP state */
03439       hcryp->State = HAL_CRYP_STATE_READY;
03440       /* Call Input transfer complete callback */
03441       HAL_CRYP_OutCpltCallback(hcryp);
03442     }
03443   }
03444
03445   /* Return function status */
03446   return HAL_OK;
03447 }
03448
03449 /**
03450   * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
03451   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03452   *         the configuration information for CRYP module
03453   * @param  pPlainData: Pointer to the plaintext buffer
03454   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03455   * @param  pCypherData: Pointer to the cyphertext buffer
03456   * @retval HAL status
03457   */
03458 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03459 {
03460   uint32_t inputaddr;
03461   uint32_t outputaddr;
03462
03463   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03464   {
03465     /* Process Locked */
03466     __HAL_LOCK(hcryp);
03467
03468     inputaddr  = (uint32_t)pPlainData;
03469     outputaddr = (uint32_t)pCypherData;
03470
03471     /* Change the CRYP state */
03472     hcryp->State = HAL_CRYP_STATE_BUSY;
03473
03474     /* Set CRYP peripheral in TDES ECB encryption mode */
03475     CRYP_SetTDESECBMode(hcryp, 0U);
03476
03477     /* Set the input and output addresses and start DMA transfer */
03478     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03479
03480     /* Process Unlocked */
03481     __HAL_UNLOCK(hcryp);
03482
03483     /* Return function status */
03484     return HAL_OK;
03485   }
03486   else
03487   {
03488     return HAL_ERROR;
03489   }
03490 }
03491
03492 /**
03493   * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
03494   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03495   *         the configuration information for CRYP module
03496   * @param  pPlainData: Pointer to the plaintext buffer
03497   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03498   * @param  pCypherData: Pointer to the cyphertext buffer
03499   * @retval HAL status
03500   */
03501 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
03502 {
03503   uint32_t inputaddr;
03504   uint32_t outputaddr;
03505
03506   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03507   {
03508     /* Process Locked */
03509     __HAL_LOCK(hcryp);
03510
03511     inputaddr  = (uint32_t)pPlainData;
03512     outputaddr = (uint32_t)pCypherData;
03513
03514     /* Change the CRYP state */
03515     hcryp->State = HAL_CRYP_STATE_BUSY;
03516
03517     /* Set CRYP peripheral in TDES CBC encryption mode */
03518     CRYP_SetTDESCBCMode(hcryp, 0U);
03519
03520     /* Set the input and output addresses and start DMA transfer */
03521     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03522
03523     /* Process Unlocked */
03524     __HAL_UNLOCK(hcryp);
03525
03526     /* Return function status */
03527     return HAL_OK;
03528   }
03529   else
03530   {
03531     return HAL_ERROR;
03532   }
03533 }
03534
03535 /**
03536   * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
03537   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03538   *         the configuration information for CRYP module
03539   * @param  pPlainData: Pointer to the plaintext buffer
03540   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03541   * @param  pCypherData: Pointer to the cyphertext buffer
03542   * @retval HAL status
03543   */
03544 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03545 {
03546   uint32_t inputaddr;
03547   uint32_t outputaddr;
03548
03549   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03550   {
03551     /* Process Locked */
03552     __HAL_LOCK(hcryp);
03553
03554     inputaddr  = (uint32_t)pCypherData;
03555     outputaddr = (uint32_t)pPlainData;
03556
03557     /* Change the CRYP state */
03558     hcryp->State = HAL_CRYP_STATE_BUSY;
03559
03560     /* Set CRYP peripheral in TDES ECB decryption mode */
03561     CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
03562
03563     /* Set the input and output addresses and start DMA transfer */
03564     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03565
03566     /* Process Unlocked */
03567     __HAL_UNLOCK(hcryp);
03568
03569     /* Return function status */
03570     return HAL_OK;
03571   }
03572   else
03573   {
03574     return HAL_ERROR;
03575   }
03576 }
03577
03578 /**
03579   * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
03580   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03581   *         the configuration information for CRYP module
03582   * @param  pCypherData: Pointer to the cyphertext buffer
03583   * @param  Size: Length of the plaintext buffer, must be a multiple of 8
03584   * @param  pPlainData: Pointer to the plaintext buffer
03585   * @retval HAL status
03586   */
03587 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
03588 {
03589   uint32_t inputaddr;
03590   uint32_t outputaddr;
03591
03592   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
03593   {
03594     /* Process Locked */
03595     __HAL_LOCK(hcryp);
03596
03597     inputaddr  = (uint32_t)pCypherData;
03598     outputaddr = (uint32_t)pPlainData;
03599
03600     /* Change the CRYP state */
03601     hcryp->State = HAL_CRYP_STATE_BUSY;
03602
03603     /* Set CRYP peripheral in TDES CBC decryption mode */
03604     CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
03605
03606     /* Set the input and output addresses and start DMA transfer */
03607     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
03608
03609     /* Process Unlocked */
03610     __HAL_UNLOCK(hcryp);
03611
03612     /* Return function status */
03613     return HAL_OK;
03614   }
03615   else
03616   {
03617     return HAL_ERROR;
03618   }
03619 }
03620
03621 /**
03622   * @}
03623   */
03624
03625 /** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions
03626  *  @brief   DMA callback functions.
03627  *
03628 @verbatim
03629   ==============================================================================
03630                       ##### DMA callback functions  #####
03631   ==============================================================================
03632     [..]  This section provides DMA callback functions:
03633       (+) DMA Input data transfer complete
03634       (+) DMA Output data transfer complete
03635       (+) DMA error
03636
03637 @endverbatim
03638   * @{
03639   */
03640
03641 /**
03642   * @brief  Input FIFO transfer completed callbacks.
03643   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03644   *         the configuration information for CRYP module
03645   * @retval None
03646   */
03647 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
03648 {
03649   /* Prevent unused argument(s) compilation warning */
03650   UNUSED(hcryp);
03651   /* NOTE : This function Should not be modified, when the callback is needed,
03652             the HAL_CRYP_InCpltCallback could be implemented in the user file
03653    */
03654 }
03655
03656 /**
03657   * @brief  Output FIFO transfer completed callbacks.
03658   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03659   *         the configuration information for CRYP module
03660   * @retval None
03661   */
03662 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
03663 {
03664   /* Prevent unused argument(s) compilation warning */
03665   UNUSED(hcryp);
03666   /* NOTE : This function Should not be modified, when the callback is needed,
03667             the HAL_CRYP_OutCpltCallback could be implemented in the user file
03668    */
03669 }
03670
03671 /**
03672   * @brief  CRYP error callbacks.
03673   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03674   *         the configuration information for CRYP module
03675   * @retval None
03676   */
03677  __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
03678 {
03679   /* Prevent unused argument(s) compilation warning */
03680   UNUSED(hcryp);
03681   /* NOTE : This function Should not be modified, when the callback is needed,
03682             the HAL_CRYP_ErrorCallback could be implemented in the user file
03683    */
03684 }
03685
03686 /**
03687   * @}
03688   */
03689
03690 /** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management
03691  *  @brief   CRYP IRQ handler.
03692  *
03693 @verbatim
03694   ==============================================================================
03695                 ##### CRYP IRQ handler management #####
03696   ==============================================================================
03697 [..]  This section provides CRYP IRQ handler function.
03698
03699 @endverbatim
03700   * @{
03701   */
03702
03703 /**
03704   * @brief  This function handles CRYP interrupt request.
03705   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03706   *         the configuration information for CRYP module
03707   * @retval None
03708   */
03709 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
03710 {
03711   switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
03712   {
03713   case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
03714     HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
03715     break;
03716
03717   case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
03718     HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
03719     break;
03720
03721   case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
03722     HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
03723     break;
03724
03725   case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
03726     HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
03727     break;
03728
03729   case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
03730     HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
03731     break;
03732
03733   case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
03734     HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
03735     break;
03736
03737   case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
03738     HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
03739     break;
03740
03741   case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
03742     HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
03743     break;
03744
03745   case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
03746     HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
03747     break;
03748
03749   case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
03750     HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
03751     break;
03752
03753   case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
03754     HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
03755     break;
03756
03757   case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
03758     HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
03759     break;
03760
03761   case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
03762     HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0U, NULL);
03763     break;
03764
03765   case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
03766     HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0U, NULL);
03767     break;
03768
03769   default:
03770     break;
03771   }
03772 }
03773
03774 /**
03775   * @}
03776   */
03777
03778 /** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions
03779  *  @brief   Peripheral State functions.
03780  *
03781 @verbatim
03782   ==============================================================================
03783                       ##### Peripheral State functions #####
03784   ==============================================================================
03785     [..]
03786     This subsection permits to get in run-time the status of the peripheral.
03787
03788 @endverbatim
03789   * @{
03790   */
03791
03792 /**
03793   * @brief  Returns the CRYP state.
03794   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
03795   *         the configuration information for CRYP module
03796   * @retval HAL state
03797   */
03798 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
03799 {
03800   return hcryp->State;
03801 }
03802
03803 /**
03804   * @}
03805   */
03806
03807
03808 /**
03809   * @}
03810   */
03811
03812 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
03813
03814 #endif /* HAL_CRYP_MODULE_ENABLED */
03815 /**
03816   * @}
03817   */
03818
03819 /**
03820   * @}
03821   */
03822
03823 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp.h Source File

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stm32f4xx_hal_cryp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of CRYP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_CRYP_H
00040 #define __STM32F4xx_HAL_CRYP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup CRYP
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
00065   * @{
00066   */
00067
00068 typedef struct
00069 {
00070   uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00071                              This parameter can be a value of @ref CRYP_Data_Type */
00072
00073   uint32_t KeySize;     /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
00074                              This parameter can be a value of @ref CRYP_Key_Size */
00075
00076   uint8_t* pKey;        /*!< The key used for encryption/decryption */
00077
00078   uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
00079                              counter in CTR mode */
00080
00081   uint8_t IVSize;       /*!< The size of initialization vector.
00082                              This parameter (called nonce size in CCM) is used only
00083                              in AES-128/192/256 encryption/decryption CCM mode */
00084
00085   uint8_t TagSize;      /*!< The size of returned authentication TAG.
00086                              This parameter is used only in AES-128/192/256
00087                              encryption/decryption CCM mode */
00088
00089   uint8_t* Header;      /*!< The header used in GCM and CCM modes */
00090
00091   uint32_t HeaderSize;  /*!< The size of header buffer in bytes */
00092
00093   uint8_t* pScratch;    /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
00094                              This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
00095 }CRYP_InitTypeDef;
00096
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
00102   * @{
00103   */
00104
00105
00106 typedef enum
00107 {
00108   HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
00109   HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
00110   HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP internal processing is ongoing   */
00111   HAL_CRYP_STATE_TIMEOUT           = 0x03U,  /*!< CRYP timeout state                    */
00112   HAL_CRYP_STATE_ERROR             = 0x04U   /*!< CRYP error state                      */
00113 }HAL_CRYP_STATETypeDef;
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
00120   * @{
00121   */
00122
00123
00124 typedef enum
00125 {
00126   HAL_CRYP_PHASE_READY             = 0x01U,    /*!< CRYP peripheral is ready for initialization. */
00127   HAL_CRYP_PHASE_PROCESS           = 0x02U,    /*!< CRYP peripheral is in processing phase */
00128   HAL_CRYP_PHASE_FINAL             = 0x03U     /*!< CRYP peripheral is in final phase
00129                                                    This is relevant only with CCM and GCM modes */
00130 }HAL_PhaseTypeDef;
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
00137   * @{
00138   */
00139
00140 typedef struct
00141 {
00142       CRYP_TypeDef             *Instance;        /*!< CRYP registers base address */
00143
00144       CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */
00145
00146       uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00147
00148       uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00149
00150       __IO uint16_t            CrypInCount;      /*!< Counter of inputed data */
00151
00152       __IO uint16_t            CrypOutCount;     /*!< Counter of output data */
00153
00154       HAL_StatusTypeDef        Status;           /*!< CRYP peripheral status */
00155
00156       HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral phase */
00157
00158       DMA_HandleTypeDef        *hdmain;          /*!< CRYP In DMA handle parameters */
00159
00160       DMA_HandleTypeDef        *hdmaout;         /*!< CRYP Out DMA handle parameters */
00161
00162       HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
00163
00164    __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
00165 }CRYP_HandleTypeDef;
00166
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported constants --------------------------------------------------------*/
00176 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00177   * @{
00178   */
00179
00180 /** @defgroup CRYP_Key_Size CRYP Key Size
00181   * @{
00182   */
00183 #define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000U)
00184 #define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
00185 #define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup CRYP_Data_Type CRYP Data Type
00191   * @{
00192   */
00193 #define CRYP_DATATYPE_32B         ((uint32_t)0x00000000U)
00194 #define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
00195 #define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
00196 #define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
00202   * @{
00203   */
00204 #define CRYP_CR_ALGOMODE_DIRECTION         ((uint32_t)0x0008003CU)
00205 #define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT  ((uint32_t)0x00000000U)
00206 #define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT  ((uint32_t)0x00000004U)
00207 #define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT  ((uint32_t)0x00000008U)
00208 #define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT  ((uint32_t)0x0000000CU)
00209 #define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT   ((uint32_t)0x00000010U)
00210 #define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT   ((uint32_t)0x00000014U)
00211 #define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT   ((uint32_t)0x00000018U)
00212 #define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT   ((uint32_t)0x0000001CU)
00213 #define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT   ((uint32_t)0x00000020U)
00214 #define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT   ((uint32_t)0x00000024U)
00215 #define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT   ((uint32_t)0x00000028U)
00216 #define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT   ((uint32_t)0x0000002CU)
00217 #define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT   ((uint32_t)0x00000030U)
00218 #define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT   ((uint32_t)0x00000034U)
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
00224   * @{
00225   */
00226 #define CRYP_IT_INI               ((uint32_t)CRYP_IMSCR_INIM)   /*!< Input FIFO Interrupt */
00227 #define CRYP_IT_OUTI              ((uint32_t)CRYP_IMSCR_OUTIM)  /*!< Output FIFO Interrupt */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
00233   * @{
00234   */
00235 #define CRYP_FLAG_BUSY   ((uint32_t)0x00000010U)  /*!< The CRYP core is currently
00236                                                      processing a block of data
00237                                                      or a key preparation (for
00238                                                      AES decryption). */
00239 #define CRYP_FLAG_IFEM   ((uint32_t)0x00000001U)  /*!< Input FIFO is empty */
00240 #define CRYP_FLAG_IFNF   ((uint32_t)0x00000002U)  /*!< Input FIFO is not Full */
00241 #define CRYP_FLAG_OFNE   ((uint32_t)0x00000004U)  /*!< Output FIFO is not empty */
00242 #define CRYP_FLAG_OFFU   ((uint32_t)0x00000008U)  /*!< Output FIFO is Full */
00243 #define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U)  /*!< Output FIFO service raw
00244                                                       interrupt status */
00245 #define CRYP_FLAG_INRIS  ((uint32_t)0x01000001U)  /*!< Input FIFO service raw
00246                                                       interrupt status */
00247 /**
00248   * @}
00249   */
00250
00251 /**
00252   * @}
00253   */
00254
00255 /* Exported macro ------------------------------------------------------------*/
00256 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00257   * @{
00258   */
00259
00260 /** @brief Reset CRYP handle state
00261   * @param  __HANDLE__: specifies the CRYP handle.
00262   * @retval None
00263   */
00264 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
00265
00266 /**
00267   * @brief  Enable/Disable the CRYP peripheral.
00268   * @param  __HANDLE__: specifies the CRYP handle.
00269   * @retval None
00270   */
00271 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)
00272 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)
00273
00274 /**
00275   * @brief  Flush the data FIFO.
00276   * @param  __HANDLE__: specifies the CRYP handle.
00277   * @retval None
00278   */
00279 #define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
00280
00281 /**
00282   * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
00283   * @param  __HANDLE__: specifies the CRYP handle.
00284   * @param  MODE: The algorithm mode.
00285   * @retval None
00286   */
00287 #define __HAL_CRYP_SET_MODE(__HANDLE__, MODE)  ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
00288
00289 /** @brief  Check whether the specified CRYP flag is set or not.
00290   * @param  __HANDLE__: specifies the CRYP handle.
00291   * @param  __FLAG__: specifies the flag to check.
00292   *         This parameter can be one of the following values:
00293   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
00294   *                                 or a key preparation (for AES decryption).
00295   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
00296   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
00297   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
00298   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
00299   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
00300   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
00301   * @retval The new state of __FLAG__ (TRUE or FALSE).
00302   */
00303
00304 #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24U)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
00305                                                  ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
00306
00307 /** @brief  Check whether the specified CRYP interrupt is set or not.
00308   * @param  __HANDLE__: specifies the CRYP handle.
00309   * @param  __INTERRUPT__: specifies the interrupt to check.
00310   *         This parameter can be one of the following values:
00311   *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
00312   *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
00313   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00314   */
00315 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
00316
00317 /**
00318   * @brief  Enable the CRYP interrupt.
00319   * @param  __HANDLE__: specifies the CRYP handle.
00320   * @param  __INTERRUPT__: CRYP Interrupt.
00321   * @retval None
00322   */
00323 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
00324
00325 /**
00326   * @brief  Disable the CRYP interrupt.
00327   * @param  __HANDLE__: specifies the CRYP handle.
00328   * @param  __INTERRUPT__: CRYP interrupt.
00329   * @retval None
00330   */
00331 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
00332
00333 /**
00334   * @}
00335   */
00336
00337 /* Include CRYP HAL Extension module */
00338 #include "stm32f4xx_hal_cryp_ex.h"
00339
00340 /* Exported functions --------------------------------------------------------*/
00341 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00342   * @{
00343   */
00344
00345 /** @addtogroup CRYP_Exported_Functions_Group1
00346   * @{
00347   */
00348 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00349 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00350 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00351 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00352 /**
00353   * @}
00354   */
00355
00356 /** @addtogroup CRYP_Exported_Functions_Group2
00357   * @{
00358   */
00359 /* AES encryption/decryption using polling  ***********************************/
00360 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00361 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00362 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00363 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00364 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00365 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00366
00367 /* AES encryption/decryption using interrupt  *********************************/
00368 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00369 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00370 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00371 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00372 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00373 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00374
00375 /* AES encryption/decryption using DMA  ***************************************/
00376 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00377 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00378 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00379 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00380 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00381 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00382 /**
00383   * @}
00384   */
00385
00386 /** @addtogroup CRYP_Exported_Functions_Group3
00387   * @{
00388   */
00389 /* DES encryption/decryption using polling  ***********************************/
00390 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00391 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00392 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00393 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00394
00395 /* DES encryption/decryption using interrupt  *********************************/
00396 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00397 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00398 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00399 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00400
00401 /* DES encryption/decryption using DMA  ***************************************/
00402 HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00403 HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00404 HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00405 HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00406 /**
00407   * @}
00408   */
00409
00410 /** @addtogroup CRYP_Exported_Functions_Group4
00411   * @{
00412   */
00413 /* TDES encryption/decryption using polling  **********************************/
00414 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00415 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00416 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00417 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00418
00419 /* TDES encryption/decryption using interrupt  ********************************/
00420 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00421 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00422 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00423 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00424
00425 /* TDES encryption/decryption using DMA  **************************************/
00426 HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00427 HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00428 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00429 HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00430 /**
00431   * @}
00432   */
00433
00434 /** @addtogroup CRYP_Exported_Functions_Group5
00435   * @{
00436   */
00437 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00438 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00439 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00440 /**
00441   * @}
00442   */
00443
00444 /** @addtogroup CRYP_Exported_Functions_Group6
00445   * @{
00446   */
00447 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00448 /**
00449   * @}
00450   */
00451
00452 /** @addtogroup CRYP_Exported_Functions_Group7
00453   * @{
00454   */
00455 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00456 /**
00457   * @}
00458   */
00459
00460 /**
00461   * @}
00462   */
00463
00464 /* Private types -------------------------------------------------------------*/
00465 /** @defgroup CRYP_Private_Types CRYP Private Types
00466   * @{
00467   */
00468
00469 /**
00470   * @}
00471   */
00472
00473 /* Private variables ---------------------------------------------------------*/
00474 /** @defgroup CRYP_Private_Variables CRYP Private Variables
00475   * @{
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /* Private constants ---------------------------------------------------------*/
00483 /** @defgroup CRYP_Private_Constants CRYP Private Constants
00484   * @{
00485   */
00486 #define CRYP_FLAG_MASK  ((uint32_t)0x0000001FU)
00487 /**
00488   * @}
00489   */
00490
00491 /* Private macros ------------------------------------------------------------*/
00492 /** @defgroup CRYP_Private_Macros CRYP Private Macros
00493   * @{
00494   */
00495
00496 #define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
00497                                        ((__KEYSIZE__) == CRYP_KEYSIZE_192B)  || \
00498                                        ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
00499
00500
00501 #define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
00502                                         ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
00503                                         ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
00504                                         ((__DATATYPE__) == CRYP_DATATYPE_1B))
00505
00506
00507  /**
00508   * @}
00509   */
00510
00511 /* Private functions ---------------------------------------------------------*/
00512 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00513   * @{
00514   */
00515
00516 /**
00517   * @}
00518   */
00519
00520 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
00521
00522 /**
00523   * @}
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 #ifdef __cplusplus
00531 }
00532 #endif
00533
00534 #endif /* __STM32F4xx_HAL_CRYP_H */
00535
00536 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp_ex.c Source File

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stm32f4xx_hal_cryp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Extended CRYP HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of CRYP extension peripheral:
00010   *           + Extended AES processing functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                      ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The CRYP Extension HAL driver can be used as follows:
00018     (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00019         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
00020         (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
00021             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00022             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00023             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00024         (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
00025             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00026             (+++) Configure and enable two DMA streams one for managing data transfer from
00027                 memory to peripheral (input stream) and another stream for managing data
00028                 transfer from peripheral to memory (output stream)
00029             (+++) Associate the initialized DMA handle to the CRYP DMA handle
00030                 using  __HAL_LINKDMA()
00031             (+++) Configure the priority and enable the NVIC for the transfer complete
00032                 interrupt on the two DMA Streams. The output stream should have higher
00033                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00034     (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
00035         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
00036         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
00037         (##) The encryption/decryption key. Its size depends on the algorithm
00038                 used for encryption/decryption
00039         (##) The initialization vector (counter). It is not used ECB mode.
00040     (#)Three processing (encryption/decryption) functions are available:
00041         (##) Polling mode: encryption and decryption APIs are blocking functions
00042              i.e. they process the data and wait till the processing is finished
00043              e.g. HAL_CRYPEx_AESGCM_Encrypt()
00044         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00045                 i.e. they process the data under interrupt
00046                 e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
00047         (##) DMA mode: encryption and decryption APIs are not blocking functions
00048                 i.e. the data transfer is ensured by DMA
00049                 e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
00050     (#)When the processing function is called at first time after HAL_CRYP_Init()
00051        the CRYP peripheral is initialized and processes the buffer in input.
00052        At second call, the processing function performs an append of the already
00053        processed buffer.
00054        When a new data block is to be processed, call HAL_CRYP_Init() then the
00055        processing function.
00056     (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
00057        which provide authentication messages.
00058        HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
00059        authentication messages.
00060        Call those functions after the processing ones (polling, interrupt or DMA).
00061        e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
00062             then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
00063      -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
00064      -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
00065            (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
00066     (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097   */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f4xx_hal.h"
00101
00102 /** @addtogroup STM32F4xx_HAL_Driver
00103   * @{
00104   */
00105
00106 /** @defgroup CRYPEx CRYPEx
00107   * @brief CRYP Extension HAL module driver.
00108   * @{
00109   */
00110
00111 #ifdef HAL_CRYP_MODULE_ENABLED
00112
00113 #if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00114
00115 /* Private typedef -----------------------------------------------------------*/
00116 /* Private define ------------------------------------------------------------*/
00117 /** @addtogroup CRYPEx_Private_define
00118   * @{
00119   */
00120 #define CRYPEx_TIMEOUT_VALUE  1U
00121 /**
00122   * @}
00123   */
00124
00125 /* Private macro -------------------------------------------------------------*/
00126 /* Private variables ---------------------------------------------------------*/
00127 /* Private function prototypes -----------------------------------------------*/
00128 /** @defgroup CRYPEx_Private_Functions_prototypes  CRYP Private Functions Prototypes
00129   * @{
00130   */
00131 static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
00132 static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
00133 static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
00134 static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
00135 static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
00136 static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
00137 static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
00138 static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00139 /**
00140   * @}
00141   */
00142
00143 /* Private functions ---------------------------------------------------------*/
00144 /** @addtogroup CRYPEx_Private_Functions
00145   * @{
00146   */
00147
00148 /**
00149   * @brief  DMA CRYP Input Data process complete callback.
00150   * @param  hdma: DMA handle
00151   * @retval None
00152   */
00153 static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
00154 {
00155   CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00156
00157   /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
00158      in the DMACR register */
00159   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
00160
00161   /* Call input data transfer complete callback */
00162   HAL_CRYP_InCpltCallback(hcryp);
00163 }
00164
00165 /**
00166   * @brief  DMA CRYP Output Data process complete callback.
00167   * @param  hdma: DMA handle
00168   * @retval None
00169   */
00170 static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
00171 {
00172   CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00173
00174   /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
00175      in the DMACR register */
00176   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
00177
00178   /* Enable the CRYP peripheral */
00179   __HAL_CRYP_DISABLE(hcryp);
00180
00181   /* Change the CRYP peripheral state */
00182   hcryp->State = HAL_CRYP_STATE_READY;
00183
00184   /* Call output data transfer complete callback */
00185   HAL_CRYP_OutCpltCallback(hcryp);
00186 }
00187
00188 /**
00189   * @brief  DMA CRYP communication error callback.
00190   * @param  hdma: DMA handle
00191   * @retval None
00192   */
00193 static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
00194 {
00195   CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00196   hcryp->State= HAL_CRYP_STATE_READY;
00197   HAL_CRYP_ErrorCallback(hcryp);
00198 }
00199
00200 /**
00201   * @brief  Writes the Key in Key registers.
00202   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00203   *         the configuration information for CRYP module
00204   * @param  Key: Pointer to Key buffer
00205   * @param  KeySize: Size of Key
00206   * @retval None
00207   */
00208 static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
00209 {
00210   uint32_t keyaddr = (uint32_t)Key;
00211
00212   switch(KeySize)
00213   {
00214   case CRYP_KEYSIZE_256B:
00215     /* Key Initialisation */
00216     hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
00217     keyaddr+=4U;
00218     hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
00219     keyaddr+=4U;
00220     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00221     keyaddr+=4U;
00222     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00223     keyaddr+=4U;
00224     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00225     keyaddr+=4U;
00226     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00227     keyaddr+=4U;
00228     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00229     keyaddr+=4U;
00230     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00231     break;
00232   case CRYP_KEYSIZE_192B:
00233     hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
00234     keyaddr+=4U;
00235     hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
00236     keyaddr+=4U;
00237     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00238     keyaddr+=4U;
00239     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00240     keyaddr+=4U;
00241     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00242     keyaddr+=4U;
00243     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00244     break;
00245   case CRYP_KEYSIZE_128B:
00246     hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
00247     keyaddr+=4U;
00248     hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
00249     keyaddr+=4U;
00250     hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
00251     keyaddr+=4U;
00252     hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
00253     break;
00254   default:
00255     break;
00256   }
00257 }
00258
00259 /**
00260   * @brief  Writes the InitVector/InitCounter in IV registers.
00261   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00262   *         the configuration information for CRYP module
00263   * @param  InitVector: Pointer to InitVector/InitCounter buffer
00264   * @retval None
00265   */
00266 static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
00267 {
00268   uint32_t ivaddr = (uint32_t)InitVector;
00269
00270   hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
00271   ivaddr+=4U;
00272   hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
00273   ivaddr+=4U;
00274   hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
00275   ivaddr+=4U;
00276   hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
00277 }
00278
00279 /**
00280   * @brief  Process Data: Writes Input data in polling mode and read the Output data.
00281   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00282   *         the configuration information for CRYP module
00283   * @param  Input: Pointer to the Input buffer.
00284   * @param  Ilength: Length of the Input buffer, must be a multiple of 16
00285   * @param  Output: Pointer to the returned buffer
00286   * @param  Timeout: Timeout value
00287   * @retval None
00288   */
00289 static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
00290 {
00291   uint32_t tickstart = 0U;
00292   uint32_t i = 0U;
00293   uint32_t inputaddr  = (uint32_t)Input;
00294   uint32_t outputaddr = (uint32_t)Output;
00295
00296   for(i=0U; (i < Ilength); i+=16U)
00297   {
00298     /* Write the Input block in the IN FIFO */
00299     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00300     inputaddr+=4U;
00301     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00302     inputaddr+=4U;
00303     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
00304     inputaddr+=4U;
00305     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
00306     inputaddr+=4U;
00307
00308     /* Get tick */
00309     tickstart = HAL_GetTick();
00310
00311     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
00312     {
00313       /* Check for the Timeout */
00314       if(Timeout != HAL_MAX_DELAY)
00315       {
00316         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
00317         {
00318           /* Change state */
00319           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00320
00321           /* Process Unlocked */
00322           __HAL_UNLOCK(hcryp);
00323
00324           return HAL_TIMEOUT;
00325         }
00326       }
00327     }
00328     /* Read the Output block from the OUT FIFO */
00329     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00330     outputaddr+=4U;
00331     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00332     outputaddr+=4U;
00333     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00334     outputaddr+=4U;
00335     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
00336     outputaddr+=4U;
00337   }
00338   /* Return function status */
00339   return HAL_OK;
00340 }
00341
00342 /**
00343   * @brief  Sets the header phase
00344   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00345   *         the configuration information for CRYP module
00346   * @param  Input: Pointer to the Input buffer.
00347   * @param  Ilength: Length of the Input buffer, must be a multiple of 16
00348   * @param  Timeout: Timeout value
00349   * @retval None
00350   */
00351 static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
00352 {
00353   uint32_t tickstart = 0U;
00354   uint32_t loopcounter = 0U;
00355   uint32_t headeraddr = (uint32_t)Input;
00356
00357   /***************************** Header phase *********************************/
00358   if(hcryp->Init.HeaderSize != 0U)
00359   {
00360     /* Select header phase */
00361     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
00362     /* Enable the CRYP peripheral */
00363     __HAL_CRYP_ENABLE(hcryp);
00364
00365     for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16U)
00366     {
00367       /* Get tick */
00368       tickstart = HAL_GetTick();
00369
00370       while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
00371       {
00372         /* Check for the Timeout */
00373         if(Timeout != HAL_MAX_DELAY)
00374         {
00375           if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00376           {
00377             /* Change state */
00378             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00379
00380             /* Process Unlocked */
00381             __HAL_UNLOCK(hcryp);
00382
00383             return HAL_TIMEOUT;
00384           }
00385         }
00386       }
00387       /* Write the Input block in the IN FIFO */
00388       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00389       headeraddr+=4U;
00390       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00391       headeraddr+=4U;
00392       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00393       headeraddr+=4U;
00394       hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00395       headeraddr+=4U;
00396     }
00397
00398     /* Wait until the complete message has been processed */
00399
00400     /* Get tick */
00401     tickstart = HAL_GetTick();
00402
00403     while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
00404     {
00405       /* Check for the Timeout */
00406       if(Timeout != HAL_MAX_DELAY)
00407       {
00408         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00409         {
00410           /* Change state */
00411           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00412
00413           /* Process Unlocked */
00414           __HAL_UNLOCK(hcryp);
00415
00416           return HAL_TIMEOUT;
00417         }
00418       }
00419     }
00420   }
00421   /* Return function status */
00422   return HAL_OK;
00423 }
00424
00425 /**
00426   * @brief  Sets the DMA configuration and start the DMA transfer.
00427   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00428   *         the configuration information for CRYP module
00429   * @param  inputaddr: Address of the Input buffer
00430   * @param  Size: Size of the Input buffer, must be a multiple of 16
00431   * @param  outputaddr: Address of the Output buffer
00432   * @retval None
00433   */
00434 static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
00435 {
00436   /* Set the CRYP DMA transfer complete callback */
00437   hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
00438   /* Set the DMA error callback */
00439   hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
00440
00441   /* Set the CRYP DMA transfer complete callback */
00442   hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
00443   /* Set the DMA error callback */
00444   hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
00445
00446   /* Enable the CRYP peripheral */
00447   __HAL_CRYP_ENABLE(hcryp);
00448
00449   /* Enable the DMA In DMA Stream */
00450   HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4U);
00451
00452   /* Enable In DMA request */
00453   hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
00454
00455   /* Enable the DMA Out DMA Stream */
00456   HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4U);
00457
00458   /* Enable Out DMA request */
00459   hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
00460 }
00461
00462 /**
00463   * @}
00464   */
00465
00466 /* Exported functions---------------------------------------------------------*/
00467 /** @addtogroup CRYPEx_Exported_Functions
00468   * @{
00469   */
00470
00471 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
00472  *  @brief   Extended processing functions.
00473  *
00474 @verbatim
00475   ==============================================================================
00476               ##### Extended AES processing functions #####
00477   ==============================================================================
00478     [..]  This section provides functions allowing to:
00479       (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
00480       (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
00481       (+) Finish the processing. This function is available only for GCM and CCM
00482     [..]  Three processing methods are available:
00483       (+) Polling mode
00484       (+) Interrupt mode
00485       (+) DMA mode
00486
00487 @endverbatim
00488   * @{
00489   */
00490
00491
00492 /**
00493   * @brief  Initializes the CRYP peripheral in AES CCM encryption mode then
00494   *         encrypt pPlainData. The cypher data are available in pCypherData.
00495   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00496   *         the configuration information for CRYP module
00497   * @param  pPlainData: Pointer to the plaintext buffer
00498   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
00499   * @param  pCypherData: Pointer to the cyphertext buffer
00500   * @param  Timeout: Timeout duration
00501   * @retval HAL status
00502   */
00503 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00504 {
00505   uint32_t tickstart = 0U;
00506   uint32_t headersize = hcryp->Init.HeaderSize;
00507   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
00508   uint32_t loopcounter = 0U;
00509   uint32_t bufferidx = 0U;
00510   uint8_t blockb0[16U] = {0U};/* Block B0 */
00511   uint8_t ctr[16U] = {0U}; /* Counter */
00512   uint32_t b0addr = (uint32_t)blockb0;
00513
00514   /* Process Locked */
00515   __HAL_LOCK(hcryp);
00516
00517   /* Change the CRYP peripheral state */
00518   hcryp->State = HAL_CRYP_STATE_BUSY;
00519
00520   /* Check if initialization phase has already been performed */
00521   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00522   {
00523     /************************ Formatting the header block *********************/
00524     if(headersize != 0U)
00525     {
00526       /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
00527       if(headersize < 65280U)
00528       {
00529         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8U) & 0xFFU);
00530         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
00531         headersize += 2U;
00532       }
00533       else
00534       {
00535         /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
00536         hcryp->Init.pScratch[bufferidx++] = 0xFFU;
00537         hcryp->Init.pScratch[bufferidx++] = 0xFEU;
00538         hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
00539         hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
00540         hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
00541         hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
00542         headersize += 6U;
00543       }
00544       /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
00545       for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
00546       {
00547         hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
00548       }
00549       /* Check if the header size is modulo 16 */
00550       if ((headersize % 16U) != 0U)
00551       {
00552         /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
00553         for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
00554         {
00555           hcryp->Init.pScratch[loopcounter] = 0U;
00556         }
00557         /* Set the header size to modulo 16 */
00558         headersize = ((headersize/16U) + 1U) * 16U;
00559       }
00560       /* Set the pointer headeraddr to hcryp->Init.pScratch */
00561       headeraddr = (uint32_t)hcryp->Init.pScratch;
00562     }
00563     /*********************** Formatting the block B0 **************************/
00564     if(headersize != 0U)
00565     {
00566       blockb0[0U] = 0x40U;
00567     }
00568     /* Flags byte */
00569     /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
00570     blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
00571     blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
00572
00573     for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
00574     {
00575       blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
00576     }
00577     for ( ; loopcounter < 13U; loopcounter++)
00578     {
00579       blockb0[loopcounter+1U] = 0U;
00580     }
00581
00582     blockb0[14U] = (Size >> 8U);
00583     blockb0[15U] = (Size & 0xFFU);
00584
00585     /************************* Formatting the initial counter *****************/
00586     /* Byte 0:
00587        Bits 7 and 6 are reserved and shall be set to 0
00588        Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
00589        are distinct from B0
00590        Bits 0, 1, and 2 contain the same encoding of q as in B0
00591     */
00592     ctr[0U] = blockb0[0U] & 0x07U;
00593     /* byte 1 to NonceSize is the IV (Nonce) */
00594     for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
00595     {
00596       ctr[loopcounter] = blockb0[loopcounter];
00597     }
00598     /* Set the LSB to 1 */
00599     ctr[15U] |= 0x01U;
00600
00601     /* Set the key */
00602     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00603
00604     /* Set the CRYP peripheral in AES CCM mode */
00605     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
00606
00607     /* Set the Initialization Vector */
00608     CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
00609
00610     /* Select init phase */
00611     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
00612
00613     b0addr = (uint32_t)blockb0;
00614     /* Write the blockb0 block in the IN FIFO */
00615     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00616     b0addr+=4U;
00617     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00618     b0addr+=4U;
00619     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00620     b0addr+=4U;
00621     hcryp->Instance->DR = *(uint32_t*)(b0addr);
00622
00623     /* Enable the CRYP peripheral */
00624     __HAL_CRYP_ENABLE(hcryp);
00625
00626     /* Get tick */
00627     tickstart = HAL_GetTick();
00628
00629     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
00630     {
00631       /* Check for the Timeout */
00632       if(Timeout != HAL_MAX_DELAY)
00633       {
00634         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00635         {
00636           /* Change state */
00637           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00638
00639           /* Process Unlocked */
00640           __HAL_UNLOCK(hcryp);
00641
00642           return HAL_TIMEOUT;
00643         }
00644       }
00645     }
00646     /***************************** Header phase *******************************/
00647     if(headersize != 0U)
00648     {
00649       /* Select header phase */
00650       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
00651
00652       /* Enable the CRYP peripheral */
00653       __HAL_CRYP_ENABLE(hcryp);
00654
00655       for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
00656       {
00657         /* Get tick */
00658         tickstart = HAL_GetTick();
00659
00660         while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
00661         {
00662           {
00663             /* Check for the Timeout */
00664             if(Timeout != HAL_MAX_DELAY)
00665             {
00666               if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00667               {
00668                 /* Change state */
00669                 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00670
00671                 /* Process Unlocked */
00672                 __HAL_UNLOCK(hcryp);
00673
00674                 return HAL_TIMEOUT;
00675               }
00676             }
00677           }
00678         }
00679         /* Write the header block in the IN FIFO */
00680         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00681         headeraddr+=4U;
00682         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00683         headeraddr+=4U;
00684         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00685         headeraddr+=4U;
00686         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
00687         headeraddr+=4U;
00688       }
00689
00690       /* Get tick */
00691       tickstart = HAL_GetTick();
00692
00693       while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
00694       {
00695         /* Check for the Timeout */
00696         if(Timeout != HAL_MAX_DELAY)
00697         {
00698           if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00699           {
00700             /* Change state */
00701             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00702
00703             /* Process Unlocked */
00704             __HAL_UNLOCK(hcryp);
00705
00706             return HAL_TIMEOUT;
00707           }
00708         }
00709       }
00710     }
00711     /* Save formatted counter into the scratch buffer pScratch */
00712     for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
00713     {
00714       hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
00715     }
00716     /* Reset bit 0 */
00717     hcryp->Init.pScratch[15U] &= 0xFEU;
00718
00719     /* Select payload phase once the header phase is performed */
00720     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
00721
00722     /* Flush FIFO */
00723     __HAL_CRYP_FIFO_FLUSH(hcryp);
00724
00725     /* Enable the CRYP peripheral */
00726     __HAL_CRYP_ENABLE(hcryp);
00727
00728     /* Set the phase */
00729     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00730   }
00731
00732   /* Write Plain Data and Get Cypher Data */
00733   if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00734   {
00735     return HAL_TIMEOUT;
00736   }
00737
00738   /* Change the CRYP peripheral state */
00739   hcryp->State = HAL_CRYP_STATE_READY;
00740
00741   /* Process Unlocked */
00742   __HAL_UNLOCK(hcryp);
00743
00744   /* Return function status */
00745   return HAL_OK;
00746 }
00747
00748 /**
00749   * @brief  Initializes the CRYP peripheral in AES GCM encryption mode then
00750   *         encrypt pPlainData. The cypher data are available in pCypherData.
00751   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00752   *         the configuration information for CRYP module
00753   * @param  pPlainData: Pointer to the plaintext buffer
00754   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
00755   * @param  pCypherData: Pointer to the cyphertext buffer
00756   * @param  Timeout: Timeout duration
00757   * @retval HAL status
00758   */
00759 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00760 {
00761   uint32_t tickstart = 0U;
00762
00763   /* Process Locked */
00764   __HAL_LOCK(hcryp);
00765
00766   /* Change the CRYP peripheral state */
00767   hcryp->State = HAL_CRYP_STATE_BUSY;
00768
00769   /* Check if initialization phase has already been performed */
00770   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00771   {
00772     /* Set the key */
00773     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00774
00775     /* Set the CRYP peripheral in AES GCM mode */
00776     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
00777
00778     /* Set the Initialization Vector */
00779     CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
00780
00781     /* Flush FIFO */
00782     __HAL_CRYP_FIFO_FLUSH(hcryp);
00783
00784     /* Enable the CRYP peripheral */
00785     __HAL_CRYP_ENABLE(hcryp);
00786
00787     /* Get tick */
00788     tickstart = HAL_GetTick();
00789
00790     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
00791     {
00792       /* Check for the Timeout */
00793       if(Timeout != HAL_MAX_DELAY)
00794       {
00795         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00796         {
00797           /* Change state */
00798           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00799
00800           /* Process Unlocked */
00801           __HAL_UNLOCK(hcryp);
00802
00803           return HAL_TIMEOUT;
00804         }
00805       }
00806     }
00807
00808     /* Set the header phase */
00809     if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
00810     {
00811       return HAL_TIMEOUT;
00812     }
00813
00814     /* Disable the CRYP peripheral */
00815     __HAL_CRYP_DISABLE(hcryp);
00816
00817     /* Select payload phase once the header phase is performed */
00818     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
00819
00820     /* Flush FIFO */
00821     __HAL_CRYP_FIFO_FLUSH(hcryp);
00822
00823     /* Enable the CRYP peripheral */
00824     __HAL_CRYP_ENABLE(hcryp);
00825
00826     /* Set the phase */
00827     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00828   }
00829
00830   /* Write Plain Data and Get Cypher Data */
00831   if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
00832   {
00833     return HAL_TIMEOUT;
00834   }
00835
00836   /* Change the CRYP peripheral state */
00837   hcryp->State = HAL_CRYP_STATE_READY;
00838
00839   /* Process Unlocked */
00840   __HAL_UNLOCK(hcryp);
00841
00842   /* Return function status */
00843   return HAL_OK;
00844 }
00845
00846 /**
00847   * @brief  Initializes the CRYP peripheral in AES GCM decryption mode then
00848   *         decrypted pCypherData. The cypher data are available in pPlainData.
00849   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00850   *         the configuration information for CRYP module
00851   * @param  pCypherData: Pointer to the cyphertext buffer
00852   * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
00853   * @param  pPlainData: Pointer to the plaintext buffer
00854   * @param  Timeout: Timeout duration
00855   * @retval HAL status
00856   */
00857 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
00858 {
00859   uint32_t tickstart = 0U;
00860
00861   /* Process Locked */
00862   __HAL_LOCK(hcryp);
00863
00864   /* Change the CRYP peripheral state */
00865   hcryp->State = HAL_CRYP_STATE_BUSY;
00866
00867   /* Check if initialization phase has already been performed */
00868   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
00869   {
00870     /* Set the key */
00871     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
00872
00873     /* Set the CRYP peripheral in AES GCM decryption mode */
00874     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
00875
00876     /* Set the Initialization Vector */
00877     CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
00878
00879     /* Flush FIFO */
00880     __HAL_CRYP_FIFO_FLUSH(hcryp);
00881
00882     /* Enable the CRYP peripheral */
00883     __HAL_CRYP_ENABLE(hcryp);
00884
00885     /* Get tick */
00886     tickstart = HAL_GetTick();
00887
00888     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
00889     {
00890       /* Check for the Timeout */
00891       if(Timeout != HAL_MAX_DELAY)
00892       {
00893         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00894         {
00895           /* Change state */
00896           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
00897
00898           /* Process Unlocked */
00899           __HAL_UNLOCK(hcryp);
00900
00901           return HAL_TIMEOUT;
00902         }
00903       }
00904     }
00905
00906     /* Set the header phase */
00907     if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
00908     {
00909       return HAL_TIMEOUT;
00910     }
00911     /* Disable the CRYP peripheral */
00912     __HAL_CRYP_DISABLE(hcryp);
00913
00914     /* Select payload phase once the header phase is performed */
00915     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
00916
00917     /* Enable the CRYP peripheral */
00918     __HAL_CRYP_ENABLE(hcryp);
00919
00920     /* Set the phase */
00921     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
00922   }
00923
00924   /* Write Plain Data and Get Cypher Data */
00925   if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
00926   {
00927     return HAL_TIMEOUT;
00928   }
00929
00930   /* Change the CRYP peripheral state */
00931   hcryp->State = HAL_CRYP_STATE_READY;
00932
00933   /* Process Unlocked */
00934   __HAL_UNLOCK(hcryp);
00935
00936   /* Return function status */
00937   return HAL_OK;
00938 }
00939
00940 /**
00941   * @brief  Computes the authentication TAG.
00942   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00943   *         the configuration information for CRYP module
00944   * @param  Size: Total length of the plain/cyphertext buffer
00945   * @param  AuthTag: Pointer to the authentication buffer
00946   * @param  Timeout: Timeout duration
00947   * @retval HAL status
00948   */
00949 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)
00950 {
00951   uint32_t tickstart = 0U;
00952   uint64_t headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
00953   uint64_t inputlength = Size * 8U; /* input length in bits */
00954   uint32_t tagaddr = (uint32_t)AuthTag;
00955
00956   /* Process Locked */
00957   __HAL_LOCK(hcryp);
00958
00959   /* Change the CRYP peripheral state */
00960   hcryp->State = HAL_CRYP_STATE_BUSY;
00961
00962   /* Check if initialization phase has already been performed */
00963   if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
00964   {
00965     /* Change the CRYP phase */
00966     hcryp->Phase = HAL_CRYP_PHASE_FINAL;
00967
00968     /* Disable CRYP to start the final phase */
00969     __HAL_CRYP_DISABLE(hcryp);
00970
00971     /* Select final phase */
00972     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
00973
00974     /* Enable the CRYP peripheral */
00975     __HAL_CRYP_ENABLE(hcryp);
00976
00977     /* Write the number of bits in header (64 bits) followed by the number of bits
00978        in the payload */
00979     if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
00980     {
00981       hcryp->Instance->DR = __RBIT(headerlength >> 32U);
00982       hcryp->Instance->DR = __RBIT(headerlength);
00983       hcryp->Instance->DR = __RBIT(inputlength >> 32U);
00984       hcryp->Instance->DR = __RBIT(inputlength);
00985     }
00986     else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
00987     {
00988       hcryp->Instance->DR = __REV(headerlength >> 32U);
00989       hcryp->Instance->DR = __REV(headerlength);
00990       hcryp->Instance->DR = __REV(inputlength >> 32U);
00991       hcryp->Instance->DR = __REV(inputlength);
00992     }
00993     else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
00994     {
00995       hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32U), 16U);
00996       hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16U);
00997       hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32U), 16U);
00998       hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16U);
00999     }
01000     else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
01001     {
01002       hcryp->Instance->DR = (uint32_t)(headerlength >> 32U);
01003       hcryp->Instance->DR = (uint32_t)(headerlength);
01004       hcryp->Instance->DR = (uint32_t)(inputlength >> 32U);
01005       hcryp->Instance->DR = (uint32_t)(inputlength);
01006     }
01007     /* Get tick */
01008     tickstart = HAL_GetTick();
01009
01010     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
01011     {
01012       /* Check for the Timeout */
01013       if(Timeout != HAL_MAX_DELAY)
01014       {
01015         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01016         {
01017           /* Change state */
01018           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01019
01020           /* Process Unlocked */
01021           __HAL_UNLOCK(hcryp);
01022
01023           return HAL_TIMEOUT;
01024         }
01025       }
01026     }
01027
01028     /* Read the Auth TAG in the IN FIFO */
01029     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01030     tagaddr+=4U;
01031     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01032     tagaddr+=4U;
01033     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01034     tagaddr+=4U;
01035     *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
01036   }
01037
01038   /* Change the CRYP peripheral state */
01039   hcryp->State = HAL_CRYP_STATE_READY;
01040
01041   /* Process Unlocked */
01042   __HAL_UNLOCK(hcryp);
01043
01044   /* Return function status */
01045   return HAL_OK;
01046 }
01047
01048 /**
01049   * @brief  Computes the authentication TAG for AES CCM mode.
01050   * @note   This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
01051   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01052   *         the configuration information for CRYP module
01053   * @param  AuthTag: Pointer to the authentication buffer
01054   * @param  Timeout: Timeout duration
01055   * @retval HAL status
01056   */
01057 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)
01058 {
01059   uint32_t tickstart = 0U;
01060   uint32_t tagaddr = (uint32_t)AuthTag;
01061   uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
01062   uint32_t temptag[4U] = {0U}; /* Temporary TAG (MAC) */
01063   uint32_t loopcounter;
01064
01065   /* Process Locked */
01066   __HAL_LOCK(hcryp);
01067
01068   /* Change the CRYP peripheral state */
01069   hcryp->State = HAL_CRYP_STATE_BUSY;
01070
01071   /* Check if initialization phase has already been performed */
01072   if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
01073   {
01074     /* Change the CRYP phase */
01075     hcryp->Phase = HAL_CRYP_PHASE_FINAL;
01076
01077     /* Disable CRYP to start the final phase */
01078     __HAL_CRYP_DISABLE(hcryp);
01079
01080     /* Select final phase */
01081     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
01082
01083     /* Enable the CRYP peripheral */
01084     __HAL_CRYP_ENABLE(hcryp);
01085
01086     /* Write the counter block in the IN FIFO */
01087     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01088     ctraddr+=4U;
01089     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01090     ctraddr+=4U;
01091     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01092     ctraddr+=4U;
01093     hcryp->Instance->DR = *(uint32_t*)ctraddr;
01094
01095     /* Get tick */
01096     tickstart = HAL_GetTick();
01097
01098     while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
01099     {
01100       /* Check for the Timeout */
01101       if(Timeout != HAL_MAX_DELAY)
01102       {
01103         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01104         {
01105           /* Change state */
01106           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01107
01108           /* Process Unlocked */
01109           __HAL_UNLOCK(hcryp);
01110
01111           return HAL_TIMEOUT;
01112         }
01113       }
01114     }
01115
01116     /* Read the Auth TAG in the IN FIFO */
01117     temptag[0U] = hcryp->Instance->DOUT;
01118     temptag[1U] = hcryp->Instance->DOUT;
01119     temptag[2U] = hcryp->Instance->DOUT;
01120     temptag[3U] = hcryp->Instance->DOUT;
01121   }
01122
01123   /* Copy temporary authentication TAG in user TAG buffer */
01124   for(loopcounter = 0U; loopcounter < hcryp->Init.TagSize ; loopcounter++)
01125   {
01126     /* Set the authentication TAG buffer */
01127     *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
01128   }
01129
01130   /* Change the CRYP peripheral state */
01131   hcryp->State = HAL_CRYP_STATE_READY;
01132
01133   /* Process Unlocked */
01134   __HAL_UNLOCK(hcryp);
01135
01136   /* Return function status */
01137   return HAL_OK;
01138 }
01139
01140 /**
01141   * @brief  Initializes the CRYP peripheral in AES CCM decryption mode then
01142   *         decrypted pCypherData. The cypher data are available in pPlainData.
01143   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01144   *         the configuration information for CRYP module
01145   * @param  pPlainData: Pointer to the plaintext buffer
01146   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01147   * @param  pCypherData: Pointer to the cyphertext buffer
01148   * @param  Timeout: Timeout duration
01149   * @retval HAL status
01150   */
01151 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
01152 {
01153   uint32_t tickstart = 0U;
01154   uint32_t headersize = hcryp->Init.HeaderSize;
01155   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
01156   uint32_t loopcounter = 0U;
01157   uint32_t bufferidx = 0U;
01158   uint8_t blockb0[16U] = {0U};/* Block B0 */
01159   uint8_t ctr[16U] = {0U}; /* Counter */
01160   uint32_t b0addr = (uint32_t)blockb0;
01161
01162   /* Process Locked */
01163   __HAL_LOCK(hcryp);
01164
01165   /* Change the CRYP peripheral state */
01166   hcryp->State = HAL_CRYP_STATE_BUSY;
01167
01168   /* Check if initialization phase has already been performed */
01169   if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01170   {
01171     /************************ Formatting the header block *********************/
01172     if(headersize != 0U)
01173     {
01174       /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
01175       if(headersize < 65280U)
01176       {
01177         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8U) & 0xFFU);
01178         hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
01179         headersize += 2U;
01180       }
01181       else
01182       {
01183         /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
01184         hcryp->Init.pScratch[bufferidx++] = 0xFFU;
01185         hcryp->Init.pScratch[bufferidx++] = 0xFEU;
01186         hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
01187         hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
01188         hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
01189         hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
01190         headersize += 6U;
01191       }
01192       /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
01193       for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
01194       {
01195         hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
01196       }
01197       /* Check if the header size is modulo 16 */
01198       if ((headersize % 16U) != 0U)
01199       {
01200         /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
01201         for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
01202         {
01203           hcryp->Init.pScratch[loopcounter] = 0U;
01204         }
01205         /* Set the header size to modulo 16 */
01206         headersize = ((headersize/16U) + 1U) * 16U;
01207       }
01208       /* Set the pointer headeraddr to hcryp->Init.pScratch */
01209       headeraddr = (uint32_t)hcryp->Init.pScratch;
01210     }
01211     /*********************** Formatting the block B0 **************************/
01212     if(headersize != 0U)
01213     {
01214       blockb0[0U] = 0x40U;
01215     }
01216     /* Flags byte */
01217     /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
01218     blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
01219     blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
01220
01221     for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
01222     {
01223       blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
01224     }
01225     for ( ; loopcounter < 13U; loopcounter++)
01226     {
01227       blockb0[loopcounter+1U] = 0U;
01228     }
01229
01230     blockb0[14U] = (Size >> 8U);
01231     blockb0[15U] = (Size & 0xFFU);
01232
01233     /************************* Formatting the initial counter *****************/
01234     /* Byte 0:
01235        Bits 7 and 6 are reserved and shall be set to 0
01236        Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
01237        blocks are distinct from B0
01238        Bits 0, 1, and 2 contain the same encoding of q as in B0
01239     */
01240     ctr[0U] = blockb0[0U] & 0x07U;
01241     /* byte 1 to NonceSize is the IV (Nonce) */
01242     for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
01243     {
01244       ctr[loopcounter] = blockb0[loopcounter];
01245     }
01246     /* Set the LSB to 1 */
01247     ctr[15U] |= 0x01U;
01248
01249     /* Set the key */
01250     CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01251
01252     /* Set the CRYP peripheral in AES CCM mode */
01253     __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
01254
01255     /* Set the Initialization Vector */
01256     CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
01257
01258     /* Select init phase */
01259     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
01260
01261     b0addr = (uint32_t)blockb0;
01262     /* Write the blockb0 block in the IN FIFO */
01263     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01264     b0addr+=4U;
01265     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01266     b0addr+=4U;
01267     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01268     b0addr+=4U;
01269     hcryp->Instance->DR = *(uint32_t*)(b0addr);
01270
01271     /* Enable the CRYP peripheral */
01272     __HAL_CRYP_ENABLE(hcryp);
01273
01274     /* Get tick */
01275     tickstart = HAL_GetTick();
01276
01277     while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01278     {
01279       /* Check for the Timeout */
01280       if(Timeout != HAL_MAX_DELAY)
01281       {
01282         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01283         {
01284           /* Change state */
01285           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01286
01287           /* Process Unlocked */
01288           __HAL_UNLOCK(hcryp);
01289
01290           return HAL_TIMEOUT;
01291         }
01292       }
01293     }
01294     /***************************** Header phase *******************************/
01295     if(headersize != 0U)
01296     {
01297       /* Select header phase */
01298       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
01299
01300       /* Enable Crypto processor */
01301       __HAL_CRYP_ENABLE(hcryp);
01302
01303       for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
01304       {
01305         /* Get tick */
01306         tickstart = HAL_GetTick();
01307
01308         while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
01309         {
01310           /* Check for the Timeout */
01311           if(Timeout != HAL_MAX_DELAY)
01312           {
01313             if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01314             {
01315               /* Change state */
01316               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01317
01318               /* Process Unlocked */
01319               __HAL_UNLOCK(hcryp);
01320
01321               return HAL_TIMEOUT;
01322             }
01323           }
01324         }
01325         /* Write the header block in the IN FIFO */
01326         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01327         headeraddr+=4U;
01328         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01329         headeraddr+=4U;
01330         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01331         headeraddr+=4U;
01332         hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01333         headeraddr+=4U;
01334       }
01335
01336       /* Get tick */
01337       tickstart = HAL_GetTick();
01338
01339       while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
01340       {
01341       /* Check for the Timeout */
01342         if(Timeout != HAL_MAX_DELAY)
01343         {
01344           if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01345           {
01346             /* Change state */
01347             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01348
01349             /* Process Unlocked */
01350             __HAL_UNLOCK(hcryp);
01351
01352             return HAL_TIMEOUT;
01353           }
01354         }
01355       }
01356     }
01357     /* Save formatted counter into the scratch buffer pScratch */
01358     for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
01359     {
01360       hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
01361     }
01362     /* Reset bit 0 */
01363     hcryp->Init.pScratch[15U] &= 0xFEU;
01364     /* Select payload phase once the header phase is performed */
01365     __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01366
01367     /* Flush FIFO */
01368     __HAL_CRYP_FIFO_FLUSH(hcryp);
01369
01370     /* Enable the CRYP peripheral */
01371     __HAL_CRYP_ENABLE(hcryp);
01372
01373     /* Set the phase */
01374     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01375   }
01376
01377   /* Write Plain Data and Get Cypher Data */
01378   if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
01379   {
01380     return HAL_TIMEOUT;
01381   }
01382
01383   /* Change the CRYP peripheral state */
01384   hcryp->State = HAL_CRYP_STATE_READY;
01385
01386   /* Process Unlocked */
01387   __HAL_UNLOCK(hcryp);
01388
01389   /* Return function status */
01390   return HAL_OK;
01391 }
01392
01393 /**
01394   * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using IT.
01395   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01396   *         the configuration information for CRYP module
01397   * @param  pPlainData: Pointer to the plaintext buffer
01398   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01399   * @param  pCypherData: Pointer to the cyphertext buffer
01400   * @retval HAL status
01401   */
01402 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01403 {
01404   uint32_t tickstart = 0U;
01405   uint32_t inputaddr;
01406   uint32_t outputaddr;
01407
01408   if(hcryp->State == HAL_CRYP_STATE_READY)
01409   {
01410     /* Process Locked */
01411     __HAL_LOCK(hcryp);
01412
01413     /* Get the buffer addresses and sizes */
01414     hcryp->CrypInCount = Size;
01415     hcryp->pCrypInBuffPtr = pPlainData;
01416     hcryp->pCrypOutBuffPtr = pCypherData;
01417     hcryp->CrypOutCount = Size;
01418
01419     /* Change the CRYP peripheral state */
01420     hcryp->State = HAL_CRYP_STATE_BUSY;
01421
01422     /* Check if initialization phase has already been performed */
01423     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01424     {
01425       /* Set the key */
01426       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01427
01428       /* Set the CRYP peripheral in AES GCM mode */
01429       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
01430
01431       /* Set the Initialization Vector */
01432       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
01433
01434       /* Flush FIFO */
01435       __HAL_CRYP_FIFO_FLUSH(hcryp);
01436
01437       /* Enable CRYP to start the init phase */
01438       __HAL_CRYP_ENABLE(hcryp);
01439
01440      /* Get tick */
01441      tickstart = HAL_GetTick();
01442
01443       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01444       {
01445         /* Check for the Timeout */
01446
01447         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01448         {
01449           /* Change state */
01450           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01451
01452           /* Process Unlocked */
01453           __HAL_UNLOCK(hcryp);
01454
01455           return HAL_TIMEOUT;
01456
01457         }
01458       }
01459
01460       /* Set the header phase */
01461       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
01462       {
01463         return HAL_TIMEOUT;
01464       }
01465       /* Disable the CRYP peripheral */
01466       __HAL_CRYP_DISABLE(hcryp);
01467
01468       /* Select payload phase once the header phase is performed */
01469       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01470
01471       /* Flush FIFO */
01472       __HAL_CRYP_FIFO_FLUSH(hcryp);
01473
01474       /* Set the phase */
01475       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01476     }
01477
01478     if(Size != 0U)
01479     {
01480       /* Enable Interrupts */
01481       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01482       /* Enable the CRYP peripheral */
01483       __HAL_CRYP_ENABLE(hcryp);
01484     }
01485     else
01486     {
01487       /* Process Locked */
01488       __HAL_UNLOCK(hcryp);
01489       /* Change the CRYP state and phase */
01490       hcryp->State = HAL_CRYP_STATE_READY;
01491     }
01492     /* Return function status */
01493     return HAL_OK;
01494   }
01495   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01496   {
01497     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01498     /* Write the Input block in the IN FIFO */
01499     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01500     inputaddr+=4U;
01501     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01502     inputaddr+=4U;
01503     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01504     inputaddr+=4U;
01505     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01506     hcryp->pCrypInBuffPtr += 16U;
01507     hcryp->CrypInCount -= 16U;
01508     if(hcryp->CrypInCount == 0U)
01509     {
01510       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01511       /* Call the Input data transfer complete callback */
01512       HAL_CRYP_InCpltCallback(hcryp);
01513     }
01514   }
01515   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01516   {
01517     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01518     /* Read the Output block from the Output FIFO */
01519     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01520     outputaddr+=4U;
01521     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01522     outputaddr+=4U;
01523     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01524     outputaddr+=4U;
01525     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01526     hcryp->pCrypOutBuffPtr += 16U;
01527     hcryp->CrypOutCount -= 16U;
01528     if(hcryp->CrypOutCount == 0U)
01529     {
01530       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01531       /* Process Unlocked */
01532       __HAL_UNLOCK(hcryp);
01533       /* Change the CRYP peripheral state */
01534       hcryp->State = HAL_CRYP_STATE_READY;
01535       /* Call Input transfer complete callback */
01536       HAL_CRYP_OutCpltCallback(hcryp);
01537     }
01538   }
01539
01540   /* Return function status */
01541   return HAL_OK;
01542 }
01543
01544 /**
01545   * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
01546   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01547   *         the configuration information for CRYP module
01548   * @param  pPlainData: Pointer to the plaintext buffer
01549   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01550   * @param  pCypherData: Pointer to the cyphertext buffer
01551   * @retval HAL status
01552   */
01553 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
01554 {
01555   uint32_t tickstart = 0U;
01556   uint32_t inputaddr;
01557   uint32_t outputaddr;
01558
01559   uint32_t headersize = hcryp->Init.HeaderSize;
01560   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
01561   uint32_t loopcounter = 0U;
01562   uint32_t bufferidx = 0U;
01563   uint8_t blockb0[16U] = {0U};/* Block B0 */
01564   uint8_t ctr[16U] = {0U}; /* Counter */
01565   uint32_t b0addr = (uint32_t)blockb0;
01566
01567   if(hcryp->State == HAL_CRYP_STATE_READY)
01568   {
01569     /* Process Locked */
01570     __HAL_LOCK(hcryp);
01571
01572     hcryp->CrypInCount = Size;
01573     hcryp->pCrypInBuffPtr = pPlainData;
01574     hcryp->pCrypOutBuffPtr = pCypherData;
01575     hcryp->CrypOutCount = Size;
01576
01577     /* Change the CRYP peripheral state */
01578     hcryp->State = HAL_CRYP_STATE_BUSY;
01579
01580     /* Check if initialization phase has already been performed */
01581     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01582     {
01583       /************************ Formatting the header block *******************/
01584       if(headersize != 0U)
01585       {
01586         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
01587         if(headersize < 65280U)
01588         {
01589           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8U) & 0xFFU);
01590           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
01591           headersize += 2U;
01592         }
01593         else
01594         {
01595           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
01596           hcryp->Init.pScratch[bufferidx++] = 0xFFU;
01597           hcryp->Init.pScratch[bufferidx++] = 0xFEU;
01598           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
01599           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
01600           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
01601           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
01602           headersize += 6U;
01603         }
01604         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
01605         for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
01606         {
01607           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
01608         }
01609         /* Check if the header size is modulo 16 */
01610         if ((headersize % 16U) != 0U)
01611         {
01612           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
01613           for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
01614           {
01615             hcryp->Init.pScratch[loopcounter] = 0U;
01616           }
01617           /* Set the header size to modulo 16 */
01618           headersize = ((headersize/16U) + 1U) * 16U;
01619         }
01620         /* Set the pointer headeraddr to hcryp->Init.pScratch */
01621         headeraddr = (uint32_t)hcryp->Init.pScratch;
01622       }
01623       /*********************** Formatting the block B0 ************************/
01624       if(headersize != 0U)
01625       {
01626         blockb0[0U] = 0x40U;
01627       }
01628       /* Flags byte */
01629       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
01630       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
01631       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
01632
01633       for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
01634       {
01635         blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
01636       }
01637       for ( ; loopcounter < 13U; loopcounter++)
01638       {
01639         blockb0[loopcounter+1U] = 0U;
01640       }
01641
01642       blockb0[14U] = (Size >> 8U);
01643       blockb0[15U] = (Size & 0xFFU);
01644
01645       /************************* Formatting the initial counter ***************/
01646       /* Byte 0:
01647          Bits 7 and 6 are reserved and shall be set to 0
01648          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
01649          blocks are distinct from B0
01650          Bits 0, 1, and 2 contain the same encoding of q as in B0
01651       */
01652       ctr[0U] = blockb0[0U] & 0x07U;
01653       /* byte 1 to NonceSize is the IV (Nonce) */
01654       for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
01655       {
01656         ctr[loopcounter] = blockb0[loopcounter];
01657       }
01658       /* Set the LSB to 1 */
01659       ctr[15U] |= 0x01U;
01660
01661       /* Set the key */
01662       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01663
01664       /* Set the CRYP peripheral in AES CCM mode */
01665       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
01666
01667       /* Set the Initialization Vector */
01668       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
01669
01670       /* Select init phase */
01671       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
01672
01673       b0addr = (uint32_t)blockb0;
01674       /* Write the blockb0 block in the IN FIFO */
01675       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01676       b0addr+=4U;
01677       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01678       b0addr+=4U;
01679       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01680       b0addr+=4U;
01681       hcryp->Instance->DR = *(uint32_t*)(b0addr);
01682
01683       /* Enable the CRYP peripheral */
01684       __HAL_CRYP_ENABLE(hcryp);
01685
01686      /* Get tick */
01687      tickstart = HAL_GetTick();
01688
01689       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01690       {
01691         /* Check for the Timeout */
01692         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01693         {
01694           /* Change state */
01695           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01696
01697           /* Process Unlocked */
01698           __HAL_UNLOCK(hcryp);
01699
01700           return HAL_TIMEOUT;
01701         }
01702       }
01703       /***************************** Header phase *****************************/
01704       if(headersize != 0U)
01705       {
01706         /* Select header phase */
01707         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
01708
01709         /* Enable Crypto processor */
01710         __HAL_CRYP_ENABLE(hcryp);
01711
01712         for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
01713         {
01714          /* Get tick */
01715          tickstart = HAL_GetTick();
01716
01717           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
01718           {
01719             /* Check for the Timeout */
01720             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01721             {
01722               /* Change state */
01723               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01724
01725               /* Process Unlocked */
01726               __HAL_UNLOCK(hcryp);
01727
01728               return HAL_TIMEOUT;
01729             }
01730           }
01731           /* Write the header block in the IN FIFO */
01732           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01733           headeraddr+=4U;
01734           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01735           headeraddr+=4U;
01736           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01737           headeraddr+=4U;
01738           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
01739           headeraddr+=4U;
01740         }
01741
01742         /* Get tick */
01743         tickstart = HAL_GetTick();
01744
01745         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
01746         {
01747           /* Check for the Timeout */
01748           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01749           {
01750             /* Change state */
01751             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01752
01753             /* Process Unlocked */
01754             __HAL_UNLOCK(hcryp);
01755
01756             return HAL_TIMEOUT;
01757           }
01758         }
01759       }
01760       /* Save formatted counter into the scratch buffer pScratch */
01761       for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
01762       {
01763         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
01764       }
01765       /* Reset bit 0 */
01766       hcryp->Init.pScratch[15U] &= 0xFEU;
01767
01768       /* Select payload phase once the header phase is performed */
01769       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01770
01771       /* Flush FIFO */
01772       __HAL_CRYP_FIFO_FLUSH(hcryp);
01773
01774       /* Set the phase */
01775       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01776     }
01777
01778     if(Size != 0U)
01779     {
01780       /* Enable Interrupts */
01781       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01782       /* Enable the CRYP peripheral */
01783       __HAL_CRYP_ENABLE(hcryp);
01784     }
01785     else
01786     {
01787       /* Change the CRYP state and phase */
01788       hcryp->State = HAL_CRYP_STATE_READY;
01789     }
01790
01791     /* Return function status */
01792     return HAL_OK;
01793   }
01794   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01795   {
01796     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01797     /* Write the Input block in the IN FIFO */
01798     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01799     inputaddr+=4U;
01800     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01801     inputaddr+=4U;
01802     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01803     inputaddr+=4U;
01804     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01805     hcryp->pCrypInBuffPtr += 16U;
01806     hcryp->CrypInCount -= 16U;
01807     if(hcryp->CrypInCount == 0U)
01808     {
01809       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01810       /* Call Input transfer complete callback */
01811       HAL_CRYP_InCpltCallback(hcryp);
01812     }
01813   }
01814   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01815   {
01816     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01817     /* Read the Output block from the Output FIFO */
01818     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01819     outputaddr+=4U;
01820     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01821     outputaddr+=4U;
01822     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01823     outputaddr+=4U;
01824     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01825     hcryp->pCrypOutBuffPtr += 16U;
01826     hcryp->CrypOutCount -= 16U;
01827     if(hcryp->CrypOutCount == 0U)
01828     {
01829       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01830       /* Process Unlocked */
01831       __HAL_UNLOCK(hcryp);
01832       /* Change the CRYP peripheral state */
01833       hcryp->State = HAL_CRYP_STATE_READY;
01834       /* Call Input transfer complete callback */
01835       HAL_CRYP_OutCpltCallback(hcryp);
01836     }
01837   }
01838
01839   /* Return function status */
01840   return HAL_OK;
01841 }
01842
01843 /**
01844   * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using IT.
01845   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01846   *         the configuration information for CRYP module
01847   * @param  pCypherData: Pointer to the cyphertext buffer
01848   * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
01849   * @param  pPlainData: Pointer to the plaintext buffer
01850   * @retval HAL status
01851   */
01852 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
01853 {
01854   uint32_t tickstart = 0U;
01855   uint32_t inputaddr;
01856   uint32_t outputaddr;
01857
01858   if(hcryp->State == HAL_CRYP_STATE_READY)
01859   {
01860     /* Process Locked */
01861     __HAL_LOCK(hcryp);
01862
01863     /* Get the buffer addresses and sizes */
01864     hcryp->CrypInCount = Size;
01865     hcryp->pCrypInBuffPtr = pCypherData;
01866     hcryp->pCrypOutBuffPtr = pPlainData;
01867     hcryp->CrypOutCount = Size;
01868
01869     /* Change the CRYP peripheral state */
01870     hcryp->State = HAL_CRYP_STATE_BUSY;
01871
01872     /* Check if initialization phase has already been performed */
01873     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
01874     {
01875       /* Set the key */
01876       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
01877
01878       /* Set the CRYP peripheral in AES GCM decryption mode */
01879       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
01880
01881       /* Set the Initialization Vector */
01882       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
01883
01884       /* Flush FIFO */
01885       __HAL_CRYP_FIFO_FLUSH(hcryp);
01886
01887       /* Enable CRYP to start the init phase */
01888       __HAL_CRYP_ENABLE(hcryp);
01889
01890         /* Get tick */
01891         tickstart = HAL_GetTick();
01892
01893       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
01894       {
01895         /* Check for the Timeout */
01896         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
01897         {
01898           /* Change state */
01899           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
01900
01901           /* Process Unlocked */
01902           __HAL_UNLOCK(hcryp);
01903
01904           return HAL_TIMEOUT;
01905         }
01906       }
01907
01908       /* Set the header phase */
01909       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
01910       {
01911         return HAL_TIMEOUT;
01912       }
01913       /* Disable the CRYP peripheral */
01914       __HAL_CRYP_DISABLE(hcryp);
01915
01916       /* Select payload phase once the header phase is performed */
01917       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
01918
01919       /* Set the phase */
01920       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
01921     }
01922
01923     if(Size != 0U)
01924     {
01925       /* Enable Interrupts */
01926       __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
01927       /* Enable the CRYP peripheral */
01928       __HAL_CRYP_ENABLE(hcryp);
01929     }
01930     else
01931     {
01932       /* Process Locked */
01933       __HAL_UNLOCK(hcryp);
01934       /* Change the CRYP state and phase */
01935       hcryp->State = HAL_CRYP_STATE_READY;
01936     }
01937
01938     /* Return function status */
01939     return HAL_OK;
01940   }
01941   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
01942   {
01943     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01944     /* Write the Input block in the IN FIFO */
01945     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01946     inputaddr+=4U;
01947     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01948     inputaddr+=4U;
01949     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
01950     inputaddr+=4U;
01951     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
01952     hcryp->pCrypInBuffPtr += 16U;
01953     hcryp->CrypInCount -= 16U;
01954     if(hcryp->CrypInCount == 0U)
01955     {
01956       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
01957       /* Call the Input data transfer complete callback */
01958       HAL_CRYP_InCpltCallback(hcryp);
01959     }
01960   }
01961   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
01962   {
01963     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01964     /* Read the Output block from the Output FIFO */
01965     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01966     outputaddr+=4U;
01967     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01968     outputaddr+=4U;
01969     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01970     outputaddr+=4U;
01971     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
01972     hcryp->pCrypOutBuffPtr += 16U;
01973     hcryp->CrypOutCount -= 16U;
01974     if(hcryp->CrypOutCount == 0U)
01975     {
01976       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
01977       /* Process Unlocked */
01978       __HAL_UNLOCK(hcryp);
01979       /* Change the CRYP peripheral state */
01980       hcryp->State = HAL_CRYP_STATE_READY;
01981       /* Call Input transfer complete callback */
01982       HAL_CRYP_OutCpltCallback(hcryp);
01983     }
01984   }
01985
01986   /* Return function status */
01987   return HAL_OK;
01988 }
01989
01990 /**
01991   * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
01992   *         then decrypted pCypherData. The cypher data are available in pPlainData.
01993   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01994   *         the configuration information for CRYP module
01995   * @param  pCypherData: Pointer to the cyphertext buffer
01996   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
01997   * @param  pPlainData: Pointer to the plaintext buffer
01998   * @retval HAL status
01999   */
02000 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02001 {
02002   uint32_t inputaddr;
02003   uint32_t outputaddr;
02004   uint32_t tickstart = 0U;
02005   uint32_t headersize = hcryp->Init.HeaderSize;
02006   uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
02007   uint32_t loopcounter = 0U;
02008   uint32_t bufferidx = 0U;
02009   uint8_t blockb0[16U] = {0U};/* Block B0 */
02010   uint8_t ctr[16U] = {0U}; /* Counter */
02011   uint32_t b0addr = (uint32_t)blockb0;
02012
02013   if(hcryp->State == HAL_CRYP_STATE_READY)
02014   {
02015     /* Process Locked */
02016     __HAL_LOCK(hcryp);
02017
02018     hcryp->CrypInCount = Size;
02019     hcryp->pCrypInBuffPtr = pCypherData;
02020     hcryp->pCrypOutBuffPtr = pPlainData;
02021     hcryp->CrypOutCount = Size;
02022
02023     /* Change the CRYP peripheral state */
02024     hcryp->State = HAL_CRYP_STATE_BUSY;
02025
02026     /* Check if initialization phase has already been performed */
02027     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02028     {
02029       /************************ Formatting the header block *******************/
02030       if(headersize != 0U)
02031       {
02032         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
02033         if(headersize < 65280U)
02034         {
02035           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8U) & 0xFFU);
02036           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
02037           headersize += 2U;
02038         }
02039         else
02040         {
02041           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
02042           hcryp->Init.pScratch[bufferidx++] = 0xFFU;
02043           hcryp->Init.pScratch[bufferidx++] = 0xFEU;
02044           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
02045           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
02046           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
02047           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
02048           headersize += 6U;
02049         }
02050         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
02051         for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
02052         {
02053           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
02054         }
02055         /* Check if the header size is modulo 16 */
02056         if ((headersize % 16U) != 0U)
02057         {
02058           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
02059           for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
02060           {
02061             hcryp->Init.pScratch[loopcounter] = 0U;
02062           }
02063           /* Set the header size to modulo 16 */
02064           headersize = ((headersize/16U) + 1U) * 16U;
02065         }
02066         /* Set the pointer headeraddr to hcryp->Init.pScratch */
02067         headeraddr = (uint32_t)hcryp->Init.pScratch;
02068       }
02069       /*********************** Formatting the block B0 ************************/
02070       if(headersize != 0U)
02071       {
02072         blockb0[0U] = 0x40U;
02073       }
02074       /* Flags byte */
02075       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
02076       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
02077       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
02078
02079       for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
02080       {
02081         blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
02082       }
02083       for ( ; loopcounter < 13U; loopcounter++)
02084       {
02085         blockb0[loopcounter+1U] = 0U;
02086       }
02087
02088       blockb0[14U] = (Size >> 8U);
02089       blockb0[15U] = (Size & 0xFFU);
02090
02091       /************************* Formatting the initial counter ***************/
02092       /* Byte 0:
02093          Bits 7 and 6 are reserved and shall be set to 0
02094          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
02095          blocks are distinct from B0
02096          Bits 0, 1, and 2 contain the same encoding of q as in B0
02097       */
02098       ctr[0U] = blockb0[0U] & 0x07U;
02099       /* byte 1 to NonceSize is the IV (Nonce) */
02100       for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
02101       {
02102         ctr[loopcounter] = blockb0[loopcounter];
02103       }
02104       /* Set the LSB to 1 */
02105       ctr[15U] |= 0x01U;
02106
02107       /* Set the key */
02108       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02109
02110       /* Set the CRYP peripheral in AES CCM mode */
02111       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
02112
02113       /* Set the Initialization Vector */
02114       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
02115
02116       /* Select init phase */
02117       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02118
02119       b0addr = (uint32_t)blockb0;
02120       /* Write the blockb0 block in the IN FIFO */
02121       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02122       b0addr+=4U;
02123       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02124       b0addr+=4U;
02125       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02126       b0addr+=4U;
02127       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02128
02129       /* Enable the CRYP peripheral */
02130       __HAL_CRYP_ENABLE(hcryp);
02131
02132       /* Get tick */
02133       tickstart = HAL_GetTick();
02134
02135       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02136       {
02137         /* Check for the Timeout */
02138         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02139         {
02140           /* Change state */
02141           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02142
02143           /* Process Unlocked */
02144           __HAL_UNLOCK(hcryp);
02145
02146           return HAL_TIMEOUT;
02147         }
02148       }
02149       /***************************** Header phase *****************************/
02150       if(headersize != 0U)
02151       {
02152         /* Select header phase */
02153         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02154
02155         /* Enable Crypto processor */
02156         __HAL_CRYP_ENABLE(hcryp);
02157
02158         for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
02159         {
02160          /* Get tick */
02161          tickstart = HAL_GetTick();
02162
02163           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
02164           {
02165             /* Check for the Timeout */
02166             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02167             {
02168               /* Change state */
02169               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02170
02171               /* Process Unlocked */
02172               __HAL_UNLOCK(hcryp);
02173
02174               return HAL_TIMEOUT;
02175             }
02176           }
02177           /* Write the header block in the IN FIFO */
02178           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02179           headeraddr+=4U;
02180           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02181           headeraddr+=4U;
02182           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02183           headeraddr+=4U;
02184           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02185           headeraddr+=4U;
02186         }
02187
02188         /* Get tick */
02189         tickstart = HAL_GetTick();
02190
02191         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
02192         {
02193           /* Check for the Timeout */
02194           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02195           {
02196             /* Change state */
02197             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02198
02199             /* Process Unlocked */
02200             __HAL_UNLOCK(hcryp);
02201
02202             return HAL_TIMEOUT;
02203           }
02204         }
02205       }
02206       /* Save formatted counter into the scratch buffer pScratch */
02207       for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
02208       {
02209         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
02210       }
02211       /* Reset bit 0 */
02212       hcryp->Init.pScratch[15U] &= 0xFEU;
02213       /* Select payload phase once the header phase is performed */
02214       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02215
02216       /* Flush FIFO */
02217       __HAL_CRYP_FIFO_FLUSH(hcryp);
02218
02219       /* Set the phase */
02220       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02221     }
02222
02223     /* Enable Interrupts */
02224     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
02225
02226     /* Enable the CRYP peripheral */
02227     __HAL_CRYP_ENABLE(hcryp);
02228
02229     /* Return function status */
02230     return HAL_OK;
02231   }
02232   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
02233   {
02234     inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02235     /* Write the Input block in the IN FIFO */
02236     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02237     inputaddr+=4U;
02238     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02239     inputaddr+=4U;
02240     hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
02241     inputaddr+=4U;
02242     hcryp->Instance->DR = *(uint32_t*)(inputaddr);
02243     hcryp->pCrypInBuffPtr += 16U;
02244     hcryp->CrypInCount -= 16U;
02245     if(hcryp->CrypInCount == 0U)
02246     {
02247       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
02248       /* Call the Input data transfer complete callback */
02249       HAL_CRYP_InCpltCallback(hcryp);
02250     }
02251   }
02252   else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
02253   {
02254     outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02255     /* Read the Output block from the Output FIFO */
02256     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02257     outputaddr+=4U;
02258     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02259     outputaddr+=4U;
02260     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02261     outputaddr+=4U;
02262     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
02263     hcryp->pCrypOutBuffPtr += 16U;
02264     hcryp->CrypOutCount -= 16U;
02265     if(hcryp->CrypOutCount == 0U)
02266     {
02267       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
02268       /* Process Unlocked */
02269       __HAL_UNLOCK(hcryp);
02270       /* Change the CRYP peripheral state */
02271       hcryp->State = HAL_CRYP_STATE_READY;
02272       /* Call Input transfer complete callback */
02273       HAL_CRYP_OutCpltCallback(hcryp);
02274     }
02275   }
02276
02277   /* Return function status */
02278   return HAL_OK;
02279 }
02280
02281 /**
02282   * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
02283   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02284   *         the configuration information for CRYP module
02285   * @param  pPlainData: Pointer to the plaintext buffer
02286   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02287   * @param  pCypherData: Pointer to the cyphertext buffer
02288   * @retval HAL status
02289   */
02290 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02291 {
02292   uint32_t tickstart = 0U;
02293   uint32_t inputaddr;
02294   uint32_t outputaddr;
02295
02296   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02297   {
02298     /* Process Locked */
02299     __HAL_LOCK(hcryp);
02300
02301     inputaddr  = (uint32_t)pPlainData;
02302     outputaddr = (uint32_t)pCypherData;
02303
02304     /* Change the CRYP peripheral state */
02305     hcryp->State = HAL_CRYP_STATE_BUSY;
02306
02307     /* Check if initialization phase has already been performed */
02308     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02309     {
02310       /* Set the key */
02311       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02312
02313       /* Set the CRYP peripheral in AES GCM mode */
02314       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
02315
02316       /* Set the Initialization Vector */
02317       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
02318
02319       /* Flush FIFO */
02320       __HAL_CRYP_FIFO_FLUSH(hcryp);
02321
02322       /* Enable CRYP to start the init phase */
02323       __HAL_CRYP_ENABLE(hcryp);
02324
02325       /* Get tick */
02326       tickstart = HAL_GetTick();
02327
02328       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02329       {
02330         /* Check for the Timeout */
02331         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02332         {
02333           /* Change state */
02334           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02335
02336           /* Process Unlocked */
02337           __HAL_UNLOCK(hcryp);
02338
02339           return HAL_TIMEOUT;
02340         }
02341       }
02342       /* Flush FIFO */
02343       __HAL_CRYP_FIFO_FLUSH(hcryp);
02344
02345       /* Set the header phase */
02346       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
02347       {
02348         return HAL_TIMEOUT;
02349       }
02350       /* Disable the CRYP peripheral */
02351       __HAL_CRYP_DISABLE(hcryp);
02352
02353       /* Select payload phase once the header phase is performed */
02354       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02355
02356       /* Flush FIFO */
02357       __HAL_CRYP_FIFO_FLUSH(hcryp);
02358
02359       /* Set the phase */
02360       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02361     }
02362
02363     /* Set the input and output addresses and start DMA transfer */
02364     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02365
02366     /* Unlock process */
02367     __HAL_UNLOCK(hcryp);
02368
02369     /* Return function status */
02370     return HAL_OK;
02371   }
02372   else
02373   {
02374     return HAL_ERROR;
02375   }
02376 }
02377
02378 /**
02379   * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
02380   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02381   *         the configuration information for CRYP module
02382   * @param  pPlainData: Pointer to the plaintext buffer
02383   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02384   * @param  pCypherData: Pointer to the cyphertext buffer
02385   * @retval HAL status
02386   */
02387 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
02388 {
02389   uint32_t tickstart = 0U;
02390   uint32_t inputaddr;
02391   uint32_t outputaddr;
02392   uint32_t headersize;
02393   uint32_t headeraddr;
02394   uint32_t loopcounter = 0U;
02395   uint32_t bufferidx = 0U;
02396   uint8_t blockb0[16U] = {0U};/* Block B0 */
02397   uint8_t ctr[16U] = {0U}; /* Counter */
02398   uint32_t b0addr = (uint32_t)blockb0;
02399
02400   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02401   {
02402     /* Process Locked */
02403     __HAL_LOCK(hcryp);
02404
02405     inputaddr  = (uint32_t)pPlainData;
02406     outputaddr = (uint32_t)pCypherData;
02407
02408     headersize = hcryp->Init.HeaderSize;
02409     headeraddr = (uint32_t)hcryp->Init.Header;
02410
02411     hcryp->CrypInCount = Size;
02412     hcryp->pCrypInBuffPtr = pPlainData;
02413     hcryp->pCrypOutBuffPtr = pCypherData;
02414     hcryp->CrypOutCount = Size;
02415
02416     /* Change the CRYP peripheral state */
02417     hcryp->State = HAL_CRYP_STATE_BUSY;
02418
02419     /* Check if initialization phase has already been performed */
02420     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02421     {
02422       /************************ Formatting the header block *******************/
02423       if(headersize != 0U)
02424       {
02425         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
02426         if(headersize < 65280U)
02427         {
02428           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8U) & 0xFFU);
02429           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
02430           headersize += 2U;
02431         }
02432         else
02433         {
02434           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
02435           hcryp->Init.pScratch[bufferidx++] = 0xFFU;
02436           hcryp->Init.pScratch[bufferidx++] = 0xFEU;
02437           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
02438           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
02439           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
02440           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
02441           headersize += 6U;
02442         }
02443         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
02444         for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
02445         {
02446           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
02447         }
02448         /* Check if the header size is modulo 16 */
02449         if ((headersize % 16U) != 0U)
02450         {
02451           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
02452           for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
02453           {
02454             hcryp->Init.pScratch[loopcounter] = 0U;
02455           }
02456           /* Set the header size to modulo 16 */
02457           headersize = ((headersize/16U) + 1U) * 16U;
02458         }
02459         /* Set the pointer headeraddr to hcryp->Init.pScratch */
02460         headeraddr = (uint32_t)hcryp->Init.pScratch;
02461       }
02462       /*********************** Formatting the block B0 ************************/
02463       if(headersize != 0U)
02464       {
02465         blockb0[0U] = 0x40U;
02466       }
02467       /* Flags byte */
02468       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
02469       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
02470       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
02471
02472       for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
02473       {
02474         blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
02475       }
02476       for ( ; loopcounter < 13U; loopcounter++)
02477       {
02478         blockb0[loopcounter+1U] = 0U;
02479       }
02480
02481       blockb0[14U] = (Size >> 8U);
02482       blockb0[15U] = (Size & 0xFFU);
02483
02484       /************************* Formatting the initial counter ***************/
02485       /* Byte 0:
02486          Bits 7 and 6 are reserved and shall be set to 0
02487          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
02488          blocks are distinct from B0
02489          Bits 0, 1, and 2 contain the same encoding of q as in B0
02490       */
02491       ctr[0U] = blockb0[0U] & 0x07U;
02492       /* byte 1 to NonceSize is the IV (Nonce) */
02493       for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
02494       {
02495         ctr[loopcounter] = blockb0[loopcounter];
02496       }
02497       /* Set the LSB to 1 */
02498       ctr[15U] |= 0x01U;
02499
02500       /* Set the key */
02501       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02502
02503       /* Set the CRYP peripheral in AES CCM mode */
02504       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
02505
02506       /* Set the Initialization Vector */
02507       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
02508
02509       /* Select init phase */
02510       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02511
02512       b0addr = (uint32_t)blockb0;
02513       /* Write the blockb0 block in the IN FIFO */
02514       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02515       b0addr+=4U;
02516       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02517       b0addr+=4U;
02518       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02519       b0addr+=4U;
02520       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02521
02522       /* Enable the CRYP peripheral */
02523       __HAL_CRYP_ENABLE(hcryp);
02524
02525       /* Get tick */
02526       tickstart = HAL_GetTick();
02527
02528       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02529       {
02530         /* Check for the Timeout */
02531         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02532         {
02533           /* Change state */
02534           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02535
02536           /* Process Unlocked */
02537           __HAL_UNLOCK(hcryp);
02538
02539           return HAL_TIMEOUT;
02540         }
02541       }
02542       /***************************** Header phase *****************************/
02543       if(headersize != 0U)
02544       {
02545         /* Select header phase */
02546         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02547
02548         /* Enable Crypto processor */
02549         __HAL_CRYP_ENABLE(hcryp);
02550
02551         for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
02552         {
02553          /* Get tick */
02554          tickstart = HAL_GetTick();
02555
02556           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
02557           {
02558             /* Check for the Timeout */
02559             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02560             {
02561               /* Change state */
02562               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02563
02564               /* Process Unlocked */
02565               __HAL_UNLOCK(hcryp);
02566
02567               return HAL_TIMEOUT;
02568             }
02569           }
02570           /* Write the header block in the IN FIFO */
02571           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02572           headeraddr+=4U;
02573           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02574           headeraddr+=4U;
02575           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02576           headeraddr+=4U;
02577           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02578           headeraddr+=4U;
02579         }
02580
02581         /* Get tick */
02582         tickstart = HAL_GetTick();
02583
02584         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
02585         {
02586           /* Check for the Timeout */
02587           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02588           {
02589             /* Change state */
02590             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02591
02592             /* Process Unlocked */
02593             __HAL_UNLOCK(hcryp);
02594
02595             return HAL_TIMEOUT;
02596           }
02597         }
02598       }
02599       /* Save formatted counter into the scratch buffer pScratch */
02600       for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
02601       {
02602         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
02603       }
02604       /* Reset bit 0 */
02605       hcryp->Init.pScratch[15U] &= 0xFEU;
02606
02607       /* Select payload phase once the header phase is performed */
02608       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02609
02610       /* Flush FIFO */
02611       __HAL_CRYP_FIFO_FLUSH(hcryp);
02612
02613       /* Set the phase */
02614       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02615     }
02616
02617     /* Set the input and output addresses and start DMA transfer */
02618     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02619
02620     /* Unlock process */
02621     __HAL_UNLOCK(hcryp);
02622
02623     /* Return function status */
02624     return HAL_OK;
02625   }
02626   else
02627   {
02628     return HAL_ERROR;
02629   }
02630 }
02631
02632 /**
02633   * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
02634   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02635   *         the configuration information for CRYP module
02636   * @param  pCypherData: Pointer to the cyphertext buffer.
02637   * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
02638   * @param  pPlainData: Pointer to the plaintext buffer
02639   * @retval HAL status
02640   */
02641 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02642 {
02643   uint32_t tickstart = 0U;
02644   uint32_t inputaddr;
02645   uint32_t outputaddr;
02646
02647   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02648   {
02649     /* Process Locked */
02650     __HAL_LOCK(hcryp);
02651
02652     inputaddr  = (uint32_t)pCypherData;
02653     outputaddr = (uint32_t)pPlainData;
02654
02655     /* Change the CRYP peripheral state */
02656     hcryp->State = HAL_CRYP_STATE_BUSY;
02657
02658     /* Check if initialization phase has already been performed */
02659     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02660     {
02661       /* Set the key */
02662       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02663
02664       /* Set the CRYP peripheral in AES GCM decryption mode */
02665       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
02666
02667       /* Set the Initialization Vector */
02668       CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
02669
02670       /* Enable CRYP to start the init phase */
02671       __HAL_CRYP_ENABLE(hcryp);
02672
02673       /* Get tick */
02674       tickstart = HAL_GetTick();
02675
02676       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02677       {
02678         /* Check for the Timeout */
02679         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02680         {
02681           /* Change state */
02682           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02683
02684           /* Process Unlocked */
02685           __HAL_UNLOCK(hcryp);
02686
02687           return HAL_TIMEOUT;
02688         }
02689       }
02690
02691       /* Set the header phase */
02692       if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
02693       {
02694         return HAL_TIMEOUT;
02695       }
02696       /* Disable the CRYP peripheral */
02697       __HAL_CRYP_DISABLE(hcryp);
02698
02699       /* Select payload phase once the header phase is performed */
02700       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02701
02702       /* Set the phase */
02703       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02704     }
02705
02706     /* Set the input and output addresses and start DMA transfer */
02707     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02708
02709     /* Unlock process */
02710     __HAL_UNLOCK(hcryp);
02711
02712     /* Return function status */
02713     return HAL_OK;
02714   }
02715   else
02716   {
02717     return HAL_ERROR;
02718   }
02719 }
02720
02721 /**
02722   * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using DMA
02723   *         then decrypted pCypherData. The cypher data are available in pPlainData.
02724   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02725   *         the configuration information for CRYP module
02726   * @param  pCypherData: Pointer to the cyphertext buffer
02727   * @param  Size: Length of the plaintext buffer, must be a multiple of 16
02728   * @param  pPlainData: Pointer to the plaintext buffer
02729   * @retval HAL status
02730   */
02731 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
02732 {
02733   uint32_t tickstart = 0U;
02734   uint32_t inputaddr;
02735   uint32_t outputaddr;
02736   uint32_t headersize;
02737   uint32_t headeraddr;
02738   uint32_t loopcounter = 0U;
02739   uint32_t bufferidx = 0U;
02740   uint8_t blockb0[16U] = {0U};/* Block B0 */
02741   uint8_t ctr[16U] = {0U}; /* Counter */
02742   uint32_t b0addr = (uint32_t)blockb0;
02743
02744   if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
02745   {
02746     /* Process Locked */
02747     __HAL_LOCK(hcryp);
02748
02749     inputaddr  = (uint32_t)pCypherData;
02750     outputaddr = (uint32_t)pPlainData;
02751
02752     headersize = hcryp->Init.HeaderSize;
02753     headeraddr = (uint32_t)hcryp->Init.Header;
02754
02755     hcryp->CrypInCount = Size;
02756     hcryp->pCrypInBuffPtr = pCypherData;
02757     hcryp->pCrypOutBuffPtr = pPlainData;
02758     hcryp->CrypOutCount = Size;
02759
02760     /* Change the CRYP peripheral state */
02761     hcryp->State = HAL_CRYP_STATE_BUSY;
02762
02763     /* Check if initialization phase has already been performed */
02764     if(hcryp->Phase == HAL_CRYP_PHASE_READY)
02765     {
02766       /************************ Formatting the header block *******************/
02767       if(headersize != 0U)
02768       {
02769         /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
02770         if(headersize < 65280U)
02771         {
02772           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8U) & 0xFFU);
02773           hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
02774           headersize += 2U;
02775         }
02776         else
02777         {
02778           /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
02779           hcryp->Init.pScratch[bufferidx++] = 0xFFU;
02780           hcryp->Init.pScratch[bufferidx++] = 0xFEU;
02781           hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
02782           hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
02783           hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
02784           hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
02785           headersize += 6U;
02786         }
02787         /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
02788         for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
02789         {
02790           hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
02791         }
02792         /* Check if the header size is modulo 16 */
02793         if ((headersize % 16U) != 0U)
02794         {
02795           /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
02796           for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
02797           {
02798             hcryp->Init.pScratch[loopcounter] = 0U;
02799           }
02800           /* Set the header size to modulo 16 */
02801           headersize = ((headersize/16U) + 1U) * 16U;
02802         }
02803         /* Set the pointer headeraddr to hcryp->Init.pScratch */
02804         headeraddr = (uint32_t)hcryp->Init.pScratch;
02805       }
02806       /*********************** Formatting the block B0 ************************/
02807       if(headersize != 0U)
02808       {
02809         blockb0[0U] = 0x40U;
02810       }
02811       /* Flags byte */
02812       /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
02813       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
02814       blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
02815
02816       for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
02817       {
02818         blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
02819       }
02820       for ( ; loopcounter < 13U; loopcounter++)
02821       {
02822         blockb0[loopcounter+1U] = 0U;
02823       }
02824
02825       blockb0[14U] = (Size >> 8U);
02826       blockb0[15U] = (Size & 0xFFU);
02827
02828       /************************* Formatting the initial counter ***************/
02829       /* Byte 0:
02830          Bits 7 and 6 are reserved and shall be set to 0
02831          Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
02832          blocks are distinct from B0
02833          Bits 0, 1, and 2 contain the same encoding of q as in B0
02834       */
02835       ctr[0U] = blockb0[0U] & 0x07U;
02836       /* byte 1 to NonceSize is the IV (Nonce) */
02837       for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
02838       {
02839         ctr[loopcounter] = blockb0[loopcounter];
02840       }
02841       /* Set the LSB to 1 */
02842       ctr[15U] |= 0x01U;
02843
02844       /* Set the key */
02845       CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
02846
02847       /* Set the CRYP peripheral in AES CCM mode */
02848       __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
02849
02850       /* Set the Initialization Vector */
02851       CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
02852
02853       /* Select init phase */
02854       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
02855
02856       b0addr = (uint32_t)blockb0;
02857       /* Write the blockb0 block in the IN FIFO */
02858       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02859       b0addr+=4U;
02860       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02861       b0addr+=4U;
02862       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02863       b0addr+=4U;
02864       hcryp->Instance->DR = *(uint32_t*)(b0addr);
02865
02866       /* Enable the CRYP peripheral */
02867       __HAL_CRYP_ENABLE(hcryp);
02868
02869       /* Get tick */
02870       tickstart = HAL_GetTick();
02871
02872       while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
02873       {
02874         /* Check for the Timeout */
02875
02876         if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02877         {
02878           /* Change state */
02879           hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02880
02881           /* Process Unlocked */
02882           __HAL_UNLOCK(hcryp);
02883
02884           return HAL_TIMEOUT;
02885
02886         }
02887       }
02888       /***************************** Header phase *****************************/
02889       if(headersize != 0U)
02890       {
02891         /* Select header phase */
02892         __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
02893
02894         /* Enable Crypto processor */
02895         __HAL_CRYP_ENABLE(hcryp);
02896
02897         for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
02898         {
02899          /* Get tick */
02900          tickstart = HAL_GetTick();
02901
02902           while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
02903           {
02904             /* Check for the Timeout */
02905             if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02906             {
02907               /* Change state */
02908               hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02909
02910               /* Process Unlocked */
02911               __HAL_UNLOCK(hcryp);
02912
02913               return HAL_TIMEOUT;
02914             }
02915           }
02916           /* Write the header block in the IN FIFO */
02917           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02918           headeraddr+=4U;
02919           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02920           headeraddr+=4U;
02921           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02922           headeraddr+=4U;
02923           hcryp->Instance->DR = *(uint32_t*)(headeraddr);
02924           headeraddr+=4U;
02925         }
02926
02927         /* Get tick */
02928         tickstart = HAL_GetTick();
02929
02930         while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
02931         {
02932           /* Check for the Timeout */
02933           if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
02934           {
02935             /* Change state */
02936             hcryp->State = HAL_CRYP_STATE_TIMEOUT;
02937
02938             /* Process Unlocked */
02939             __HAL_UNLOCK(hcryp);
02940
02941             return HAL_TIMEOUT;
02942           }
02943         }
02944       }
02945       /* Save formatted counter into the scratch buffer pScratch */
02946       for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
02947       {
02948         hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
02949       }
02950       /* Reset bit 0 */
02951       hcryp->Init.pScratch[15U] &= 0xFEU;
02952       /* Select payload phase once the header phase is performed */
02953       __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
02954
02955       /* Flush FIFO */
02956       __HAL_CRYP_FIFO_FLUSH(hcryp);
02957
02958       /* Set the phase */
02959       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
02960     }
02961     /* Set the input and output addresses and start DMA transfer */
02962     CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
02963
02964     /* Unlock process */
02965     __HAL_UNLOCK(hcryp);
02966
02967     /* Return function status */
02968     return HAL_OK;
02969   }
02970   else
02971   {
02972     return HAL_ERROR;
02973   }
02974 }
02975
02976 /**
02977   * @}
02978   */
02979
02980 /** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management
02981  *  @brief   CRYPEx IRQ handler.
02982  *
02983 @verbatim
02984   ==============================================================================
02985                 ##### CRYPEx IRQ handler management #####
02986   ==============================================================================
02987 [..]  This section provides CRYPEx IRQ handler function.
02988
02989 @endverbatim
02990   * @{
02991   */
02992
02993 /**
02994   * @brief  This function handles CRYPEx interrupt request.
02995   * @param  hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains
02996   *         the configuration information for CRYP module
02997   * @retval None
02998   */
02999
03000 void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
03001 {
03002   switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
03003   {
03004   case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
03005     HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0U, NULL);
03006     break;
03007
03008   case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
03009     HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0U, NULL);
03010     break;
03011
03012   case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
03013     HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0U, NULL);
03014     break;
03015
03016   case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
03017     HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0U, NULL);
03018     break;
03019
03020   default:
03021     break;
03022   }
03023 }
03024
03025 /**
03026   * @}
03027   */
03028
03029 /**
03030   * @}
03031   */
03032 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
03033
03034 #endif /* HAL_CRYP_MODULE_ENABLED */
03035 /**
03036   * @}
03037   */
03038
03039 /**
03040   * @}
03041   */
03042
03043 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_cryp_ex.h Source File

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stm32f4xx_hal_cryp_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of CRYP HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_CRYP_EX_H
00040 #define __STM32F4xx_HAL_CRYP_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup CRYPEx
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060
00061 /** @defgroup CRYPEx_Exported_Constants   CRYPEx Exported Constants
00062   * @{
00063   */
00064
00065 /** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
00066   * @{
00067   */
00068 #define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT   ((uint32_t)0x00080000U)
00069 #define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT   ((uint32_t)0x00080004U)
00070 #define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT   ((uint32_t)0x00080008U)
00071 #define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT   ((uint32_t)0x0008000CU)
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig
00078   * @brief    The phases are relevant only to AES-GCM and AES-CCM
00079   * @{
00080   */
00081 #define CRYP_PHASE_INIT           ((uint32_t)0x00000000U)
00082 #define CRYP_PHASE_HEADER         CRYP_CR_GCM_CCMPH_0
00083 #define CRYP_PHASE_PAYLOAD        CRYP_CR_GCM_CCMPH_1
00084 #define CRYP_PHASE_FINAL          CRYP_CR_GCM_CCMPH
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported macro ------------------------------------------------------------*/
00094 /** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  Set the phase: Init, header, payload, final.
00100   *         This is relevant only for GCM and CCM modes.
00101   * @param  __HANDLE__: specifies the CRYP handle.
00102   * @param  __PHASE__: The phase.
00103   * @retval None
00104   */
00105 #define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
00106                                                         (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
00107                                                        }while(0)
00108
00109 /**
00110   * @}
00111   */
00112
00113 /* Exported functions --------------------------------------------------------*/
00114 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00115   * @{
00116   */
00117
00118 /** @addtogroup CRYPEx_Exported_Functions_Group1
00119   * @{
00120   */
00121
00122 /* AES encryption/decryption using polling  ***********************************/
00123 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00124 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00125 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);
00126 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00127 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00128 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
00129
00130 /* AES encryption/decryption using interrupt  *********************************/
00131 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00132 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00133 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00134 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00135
00136 /* AES encryption/decryption using DMA  ***************************************/
00137 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00138 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00139 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00140 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00141
00142 /**
00143   * @}
00144   */
00145
00146 /** @addtogroup CRYPEx_Exported_Functions_Group2
00147   * @{
00148   */
00149
00150 void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
00151
00152 /**
00153   * @}
00154   */
00155
00156  /**
00157   * @}
00158   */
00159
00160
00161  /* Private types -------------------------------------------------------------*/
00162 /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
00163   * @{
00164   */
00165
00166 /**
00167   * @}
00168   */
00169
00170 /* Private variables ---------------------------------------------------------*/
00171 /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
00172   * @{
00173   */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /* Private constants ---------------------------------------------------------*/
00180 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00181   * @{
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /* Private macros ------------------------------------------------------------*/
00189 /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
00190   * @{
00191   */
00192
00193  /**
00194   * @}
00195   */
00196
00197 /* Private functions ---------------------------------------------------------*/
00198 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00199   * @{
00200   */
00201
00202 /**
00203   * @}
00204   */
00205
00206 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
00207 /**
00208   * @}
00209   */
00210
00211 /**
00212   * @}
00213   */
00214
00215 #ifdef __cplusplus
00216 }
00217 #endif
00218
00219 #endif /* __STM32F4xx_HAL_CRYP_EX_H */
00220
00221 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac.c Source File

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stm32f4xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   *
00016   @verbatim
00017   ==============================================================================
00018                       ##### DAC Peripheral features #####
00019   ==============================================================================
00020     [..]
00021       *** DAC Channels ***
00022       ====================
00023     [..]
00024     The device integrates two 12-bit Digital Analog Converters that can
00025     be used independently or simultaneously (dual mode):
00026       (#) DAC channel1 with DAC_OUT1 (PA4) as output
00027       (#) DAC channel2 with DAC_OUT2 (PA5) as output
00028
00029       *** DAC Triggers ***
00030       ====================
00031     [..]
00032     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00033     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00034     [..]
00035     Digital to Analog conversion can be triggered by:
00036       (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
00037           The used pin (GPIOx_Pin9) must be configured in input mode.
00038
00039       (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
00040           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
00041
00042       (#) Software using DAC_TRIGGER_SOFTWARE
00043
00044       *** DAC Buffer mode feature ***
00045       ===============================
00046       [..]
00047       Each DAC channel integrates an output buffer that can be used to
00048       reduce the output impedance, and to drive external loads directly
00049       without having to add an external operational amplifier.
00050       To enable, the output buffer use
00051       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00052       [..]
00053       (@) Refer to the device datasheet for more details about output
00054           impedance value with and without output buffer.
00055
00056        *** DAC wave generation feature ***
00057        ===================================
00058        [..]
00059        Both DAC channels can be used to generate
00060          (#) Noise wave
00061          (#) Triangle wave
00062
00063        *** DAC data format ***
00064        =======================
00065        [..]
00066        The DAC data format can be:
00067          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00068          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00069          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00070
00071        *** DAC data value to voltage correspondence ***
00072        ================================================
00073        [..]
00074        The analog output voltage on each DAC channel pin is determined
00075        by the following equation:
00076        DAC_OUTx = VREF+ * DOR / 4095
00077        with  DOR is the Data Output Register
00078           VEF+ is the input voltage reference (refer to the device datasheet)
00079         e.g. To set DAC_OUT1 to 0.7V, use
00080           Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00081
00082        *** DMA requests  ***
00083        =====================
00084        [..]
00085        A DMA1 request can be generated when an external trigger (but not
00086        a software trigger) occurs if DMA1 requests are enabled using
00087        HAL_DAC_Start_DMA()
00088        [..]
00089        DMA1 requests are mapped as following:
00090          (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
00091              already configured
00092          (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
00093              already configured
00094
00095     -@- For Dual mode and specific signal (Triangle and noise) generation please
00096         refer to Extension Features Driver description
00097
00098
00099                       ##### How to use this driver #####
00100   ==============================================================================
00101     [..]
00102       (+) DAC APB clock must be enabled to get write access to DAC
00103           registers using HAL_DAC_Init()
00104       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00105       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00106       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
00107
00108      *** Polling mode IO operation ***
00109      =================================
00110      [..]
00111        (+) Start the DAC peripheral using HAL_DAC_Start()
00112        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00113        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00114
00115      *** DMA mode IO operation ***
00116      ==============================
00117      [..]
00118        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00119            of data to be transferred at each end of conversion
00120        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
00121            function is executed and user can add his own code by customization of function pointer
00122            HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
00123        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00124             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00125        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00126
00127      *** DAC HAL driver macros list ***
00128      =============================================
00129      [..]
00130        Below the list of most used macros in DAC HAL driver.
00131
00132       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00133       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00134       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00135       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00136
00137      [..]
00138       (@) You can refer to the DAC HAL driver header file for more useful macros
00139
00140  @endverbatim
00141   ******************************************************************************
00142   * @attention
00143   *
00144   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00145   *
00146   * Redistribution and use in source and binary forms, with or without modification,
00147   * are permitted provided that the following conditions are met:
00148   *   1. Redistributions of source code must retain the above copyright notice,
00149   *      this list of conditions and the following disclaimer.
00150   *   2. Redistributions in binary form must reproduce the above copyright notice,
00151   *      this list of conditions and the following disclaimer in the documentation
00152   *      and/or other materials provided with the distribution.
00153   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00154   *      may be used to endorse or promote products derived from this software
00155   *      without specific prior written permission.
00156   *
00157   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00158   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00159   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00160   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00161   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00162   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00163   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00164   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00165   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00166   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00167   *
00168   ******************************************************************************
00169   */
00170
00171
00172 /* Includes ------------------------------------------------------------------*/
00173 #include "stm32f4xx_hal.h"
00174
00175 /** @addtogroup STM32F4xx_HAL_Driver
00176   * @{
00177   */
00178
00179 /** @defgroup DAC DAC
00180   * @brief DAC driver modules
00181   * @{
00182   */
00183
00184 #ifdef HAL_DAC_MODULE_ENABLED
00185
00186 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00187     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00188     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
00189     defined(STM32F469xx) || defined(STM32F479xx)
00190 /* Private typedef -----------------------------------------------------------*/
00191 /* Private define ------------------------------------------------------------*/
00192 /* Private macro -------------------------------------------------------------*/
00193 /* Private variables ---------------------------------------------------------*/
00194 /** @addtogroup DAC_Private_Functions
00195   * @{
00196   */
00197 /* Private function prototypes -----------------------------------------------*/
00198 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00199 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00200 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00201 /**
00202   * @}
00203   */
00204
00205 /* Exported functions --------------------------------------------------------*/
00206 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00207   * @{
00208   */
00209
00210 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00211  *  @brief    Initialization and Configuration functions
00212  *
00213 @verbatim
00214   ==============================================================================
00215               ##### Initialization and de-initialization functions #####
00216   ==============================================================================
00217     [..]  This section provides functions allowing to:
00218       (+) Initialize and configure the DAC.
00219       (+) De-initialize the DAC.
00220
00221 @endverbatim
00222   * @{
00223   */
00224
00225 /**
00226   * @brief  Initializes the DAC peripheral according to the specified parameters
00227   *         in the DAC_InitStruct.
00228   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00229   *         the configuration information for the specified DAC.
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
00233 {
00234   /* Check DAC handle */
00235   if(hdac == NULL)
00236   {
00237      return HAL_ERROR;
00238   }
00239   /* Check the parameters */
00240   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00241
00242   if(hdac->State == HAL_DAC_STATE_RESET)
00243   {
00244     /* Allocate lock resource and initialize it */
00245     hdac->Lock = HAL_UNLOCKED;
00246     /* Init the low level hardware */
00247     HAL_DAC_MspInit(hdac);
00248   }
00249
00250   /* Initialize the DAC state*/
00251   hdac->State = HAL_DAC_STATE_BUSY;
00252
00253   /* Set DAC error code to none */
00254   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00255
00256   /* Initialize the DAC state*/
00257   hdac->State = HAL_DAC_STATE_READY;
00258
00259   /* Return function status */
00260   return HAL_OK;
00261 }
00262
00263 /**
00264   * @brief  Deinitializes the DAC peripheral registers to their default reset values.
00265   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00266   *         the configuration information for the specified DAC.
00267   * @retval HAL status
00268   */
00269 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
00270 {
00271   /* Check DAC handle */
00272   if(hdac == NULL)
00273   {
00274      return HAL_ERROR;
00275   }
00276
00277   /* Check the parameters */
00278   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00279
00280   /* Change DAC state */
00281   hdac->State = HAL_DAC_STATE_BUSY;
00282
00283   /* DeInit the low level hardware */
00284   HAL_DAC_MspDeInit(hdac);
00285
00286   /* Set DAC error code to none */
00287   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00288
00289   /* Change DAC state */
00290   hdac->State = HAL_DAC_STATE_RESET;
00291
00292   /* Release Lock */
00293   __HAL_UNLOCK(hdac);
00294
00295   /* Return function status */
00296   return HAL_OK;
00297 }
00298
00299 /**
00300   * @brief  Initializes the DAC MSP.
00301   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00302   *         the configuration information for the specified DAC.
00303   * @retval None
00304   */
00305 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
00306 {
00307   /* Prevent unused argument(s) compilation warning */
00308   UNUSED(hdac);
00309   /* NOTE : This function Should not be modified, when the callback is needed,
00310             the HAL_DAC_MspInit could be implemented in the user file
00311    */
00312 }
00313
00314 /**
00315   * @brief  DeInitializes the DAC MSP.
00316   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00317   *         the configuration information for the specified DAC.
00318   * @retval None
00319   */
00320 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
00321 {
00322   /* Prevent unused argument(s) compilation warning */
00323   UNUSED(hdac);
00324   /* NOTE : This function Should not be modified, when the callback is needed,
00325             the HAL_DAC_MspDeInit could be implemented in the user file
00326    */
00327 }
00328
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00334  *  @brief    IO operation functions
00335  *
00336 @verbatim
00337   ==============================================================================
00338              ##### IO operation functions #####
00339   ==============================================================================
00340     [..]  This section provides functions allowing to:
00341       (+) Start conversion.
00342       (+) Stop conversion.
00343       (+) Start conversion and enable DMA transfer.
00344       (+) Stop conversion and disable DMA transfer.
00345       (+) Get result of conversion.
00346
00347 @endverbatim
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Enables DAC and starts conversion of channel.
00353   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00354   *         the configuration information for the specified DAC.
00355   * @param  Channel: The selected DAC channel.
00356   *          This parameter can be one of the following values:
00357   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00358   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00362 {
00363   uint32_t tmp1 = 0U, tmp2 = 0U;
00364
00365   /* Check the parameters */
00366   assert_param(IS_DAC_CHANNEL(Channel));
00367
00368   /* Process locked */
00369   __HAL_LOCK(hdac);
00370
00371   /* Change DAC state */
00372   hdac->State = HAL_DAC_STATE_BUSY;
00373
00374   /* Enable the Peripheral */
00375   __HAL_DAC_ENABLE(hdac, Channel);
00376
00377   if(Channel == DAC_CHANNEL_1)
00378   {
00379     tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
00380     tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
00381     /* Check if software trigger enabled */
00382     if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
00383     {
00384       /* Enable the selected DAC software conversion */
00385       hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
00386     }
00387   }
00388   else
00389   {
00390     tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
00391     tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
00392     /* Check if software trigger enabled */
00393     if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
00394     {
00395       /* Enable the selected DAC software conversion*/
00396       hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
00397     }
00398   }
00399
00400   /* Change DAC state */
00401   hdac->State = HAL_DAC_STATE_READY;
00402
00403   /* Process unlocked */
00404   __HAL_UNLOCK(hdac);
00405
00406   /* Return function status */
00407   return HAL_OK;
00408 }
00409
00410 /**
00411   * @brief  Disables DAC and stop conversion of channel.
00412   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00413   *         the configuration information for the specified DAC.
00414   * @param  Channel: The selected DAC channel.
00415   *          This parameter can be one of the following values:
00416   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00417   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00418   * @retval HAL status
00419   */
00420 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
00421 {
00422   /* Check the parameters */
00423   assert_param(IS_DAC_CHANNEL(Channel));
00424
00425   /* Disable the Peripheral */
00426   __HAL_DAC_DISABLE(hdac, Channel);
00427
00428   /* Change DAC state */
00429   hdac->State = HAL_DAC_STATE_READY;
00430
00431   /* Return function status */
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @brief  Enables DAC and starts conversion of channel.
00437   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00438   *         the configuration information for the specified DAC.
00439   * @param  Channel: The selected DAC channel.
00440   *          This parameter can be one of the following values:
00441   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00442   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00443   * @param  pData: The destination peripheral Buffer address.
00444   * @param  Length: The length of data to be transferred from memory to DAC peripheral
00445   * @param  Alignment: Specifies the data alignment for DAC channel.
00446   *          This parameter can be one of the following values:
00447   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00448   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00449   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00450   * @retval HAL status
00451   */
00452 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00453 {
00454   uint32_t tmpreg = 0U;
00455
00456   /* Check the parameters */
00457   assert_param(IS_DAC_CHANNEL(Channel));
00458   assert_param(IS_DAC_ALIGN(Alignment));
00459
00460   /* Process locked */
00461   __HAL_LOCK(hdac);
00462
00463   /* Change DAC state */
00464   hdac->State = HAL_DAC_STATE_BUSY;
00465
00466   if(Channel == DAC_CHANNEL_1)
00467   {
00468     /* Set the DMA transfer complete callback for channel1 */
00469     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00470
00471     /* Set the DMA half transfer complete callback for channel1 */
00472     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00473
00474     /* Set the DMA error callback for channel1 */
00475     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00476
00477     /* Enable the selected DAC channel1 DMA request */
00478     hdac->Instance->CR |= DAC_CR_DMAEN1;
00479
00480     /* Case of use of channel 1 */
00481     switch(Alignment)
00482     {
00483       case DAC_ALIGN_12B_R:
00484         /* Get DHR12R1 address */
00485         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00486         break;
00487       case DAC_ALIGN_12B_L:
00488         /* Get DHR12L1 address */
00489         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00490         break;
00491       case DAC_ALIGN_8B_R:
00492         /* Get DHR8R1 address */
00493         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00494         break;
00495       default:
00496         break;
00497     }
00498   }
00499   else
00500   {
00501     /* Set the DMA transfer complete callback for channel2 */
00502     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00503
00504     /* Set the DMA half transfer complete callback for channel2 */
00505     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00506
00507     /* Set the DMA error callback for channel2 */
00508     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00509
00510     /* Enable the selected DAC channel2 DMA request */
00511     hdac->Instance->CR |= DAC_CR_DMAEN2;
00512
00513     /* Case of use of channel 2 */
00514     switch(Alignment)
00515     {
00516       case DAC_ALIGN_12B_R:
00517         /* Get DHR12R2 address */
00518         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00519         break;
00520       case DAC_ALIGN_12B_L:
00521         /* Get DHR12L2 address */
00522         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00523         break;
00524       case DAC_ALIGN_8B_R:
00525         /* Get DHR8R2 address */
00526         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00527         break;
00528       default:
00529         break;
00530     }
00531   }
00532
00533   /* Enable the DMA Stream */
00534   if(Channel == DAC_CHANNEL_1)
00535   {
00536     /* Enable the DAC DMA underrun interrupt */
00537     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00538
00539     /* Enable the DMA Stream */
00540     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00541   }
00542   else
00543   {
00544     /* Enable the DAC DMA underrun interrupt */
00545     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00546
00547     /* Enable the DMA Stream */
00548     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00549   }
00550
00551   /* Enable the Peripheral */
00552   __HAL_DAC_ENABLE(hdac, Channel);
00553
00554   /* Process Unlocked */
00555   __HAL_UNLOCK(hdac);
00556
00557   /* Return function status */
00558   return HAL_OK;
00559 }
00560
00561 /**
00562   * @brief  Disables DAC and stop conversion of channel.
00563   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00564   *         the configuration information for the specified DAC.
00565   * @param  Channel: The selected DAC channel.
00566   *          This parameter can be one of the following values:
00567   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00568   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00569   * @retval HAL status
00570   */
00571 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
00572 {
00573   HAL_StatusTypeDef status = HAL_OK;
00574
00575   /* Check the parameters */
00576   assert_param(IS_DAC_CHANNEL(Channel));
00577
00578   /* Disable the selected DAC channel DMA request */
00579    hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
00580
00581   /* Disable the Peripheral */
00582   __HAL_DAC_DISABLE(hdac, Channel);
00583
00584   /* Disable the DMA Channel */
00585   /* Channel1 is used */
00586   if(Channel == DAC_CHANNEL_1)
00587   {
00588     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00589   }
00590   else /* Channel2 is used for */
00591   {
00592     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00593   }
00594
00595   /* Check if DMA Channel effectively disabled */
00596   if(status != HAL_OK)
00597   {
00598     /* Update DAC state machine to error */
00599     hdac->State = HAL_DAC_STATE_ERROR;
00600   }
00601   else
00602   {
00603     /* Change DAC state */
00604     hdac->State = HAL_DAC_STATE_READY;
00605   }
00606
00607   /* Return function status */
00608   return status;
00609 }
00610
00611 /**
00612   * @brief  Returns the last data output value of the selected DAC channel.
00613   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00614   *         the configuration information for the specified DAC.
00615   * @param  Channel: The selected DAC channel.
00616   *          This parameter can be one of the following values:
00617   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00618   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00619   * @retval The selected DAC channel data output value.
00620   */
00621 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00622 {
00623   /* Check the parameters */
00624   assert_param(IS_DAC_CHANNEL(Channel));
00625
00626   /* Returns the DAC channel data output register value */
00627   if(Channel == DAC_CHANNEL_1)
00628   {
00629     return hdac->Instance->DOR1;
00630   }
00631   else
00632   {
00633     return hdac->Instance->DOR2;
00634   }
00635 }
00636
00637 /**
00638   * @brief  Handles DAC interrupt request
00639   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00640   *         the configuration information for the specified DAC.
00641   * @retval None
00642   */
00643 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
00644 {
00645   /* Check underrun channel 1 flag */
00646   if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00647   {
00648     /* Change DAC state to error state */
00649     hdac->State = HAL_DAC_STATE_ERROR;
00650
00651     /* Set DAC error code to channel1 DMA underrun error */
00652     hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
00653
00654     /* Clear the underrun flag */
00655     __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
00656
00657     /* Disable the selected DAC channel1 DMA request */
00658     hdac->Instance->CR &= ~DAC_CR_DMAEN1;
00659
00660     /* Error callback */
00661     HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00662   }
00663   /* Check underrun channel 2 flag */
00664   if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00665   {
00666     /* Change DAC state to error state */
00667     hdac->State = HAL_DAC_STATE_ERROR;
00668
00669     /* Set DAC error code to channel2 DMA underrun error */
00670     hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
00671
00672     /* Clear the underrun flag */
00673     __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
00674
00675     /* Disable the selected DAC channel1 DMA request */
00676     hdac->Instance->CR &= ~DAC_CR_DMAEN2;
00677
00678     /* Error callback */
00679     HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00680   }
00681 }
00682
00683 /**
00684   * @brief  Conversion complete callback in non blocking mode for Channel1
00685   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00686   *         the configuration information for the specified DAC.
00687   * @retval None
00688   */
00689 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00690 {
00691   /* Prevent unused argument(s) compilation warning */
00692   UNUSED(hdac);
00693   /* NOTE : This function Should not be modified, when the callback is needed,
00694             the HAL_DAC_ConvCpltCallback could be implemented in the user file
00695    */
00696 }
00697
00698 /**
00699   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1
00700   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00701   *         the configuration information for the specified DAC.
00702   * @retval None
00703   */
00704 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00705 {
00706   /* Prevent unused argument(s) compilation warning */
00707   UNUSED(hdac);
00708   /* NOTE : This function Should not be modified, when the callback is needed,
00709             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00710    */
00711 }
00712
00713 /**
00714   * @brief  Error DAC callback for Channel1.
00715   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00716   *         the configuration information for the specified DAC.
00717   * @retval None
00718   */
00719 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00720 {
00721   /* Prevent unused argument(s) compilation warning */
00722   UNUSED(hdac);
00723   /* NOTE : This function Should not be modified, when the callback is needed,
00724             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
00725    */
00726 }
00727
00728 /**
00729   * @brief  DMA underrun DAC callback for channel1.
00730   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00731   *         the configuration information for the specified DAC.
00732   * @retval None
00733   */
00734 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00735 {
00736   /* Prevent unused argument(s) compilation warning */
00737   UNUSED(hdac);
00738   /* NOTE : This function Should not be modified, when the callback is needed,
00739             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00740    */
00741 }
00742
00743 /**
00744   * @}
00745   */
00746
00747 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00748  *  @brief      Peripheral Control functions
00749  *
00750 @verbatim
00751   ==============================================================================
00752              ##### Peripheral Control functions #####
00753   ==============================================================================
00754     [..]  This section provides functions allowing to:
00755       (+) Configure channels.
00756       (+) Set the specified data holding register value for DAC channel.
00757
00758 @endverbatim
00759   * @{
00760   */
00761
00762 /**
00763   * @brief  Configures the selected DAC channel.
00764   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00765   *         the configuration information for the specified DAC.
00766   * @param  sConfig: DAC configuration structure.
00767   * @param  Channel: The selected DAC channel.
00768   *          This parameter can be one of the following values:
00769   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00770   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00771   * @retval HAL status
00772   */
00773 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00774 {
00775   uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
00776
00777   /* Check the DAC parameters */
00778   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
00779   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
00780   assert_param(IS_DAC_CHANNEL(Channel));
00781
00782   /* Process locked */
00783   __HAL_LOCK(hdac);
00784
00785   /* Change DAC state */
00786   hdac->State = HAL_DAC_STATE_BUSY;
00787
00788   /* Get the DAC CR value */
00789   tmpreg1 = hdac->Instance->CR;
00790   /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
00791   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
00792   /* Configure for the selected DAC channel: buffer output, trigger */
00793   /* Set TSELx and TENx bits according to DAC_Trigger value */
00794   /* Set BOFFx bit according to DAC_OutputBuffer value */
00795   tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
00796   /* Calculate CR register value depending on DAC_Channel */
00797   tmpreg1 |= tmpreg2 << Channel;
00798   /* Write to DAC CR */
00799   hdac->Instance->CR = tmpreg1;
00800   /* Disable wave generation */
00801   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
00802
00803   /* Change DAC state */
00804   hdac->State = HAL_DAC_STATE_READY;
00805
00806   /* Process unlocked */
00807   __HAL_UNLOCK(hdac);
00808
00809   /* Return function status */
00810   return HAL_OK;
00811 }
00812
00813 /**
00814   * @brief  Set the specified data holding register value for DAC channel.
00815   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00816   *         the configuration information for the specified DAC.
00817   * @param  Channel: The selected DAC channel.
00818   *          This parameter can be one of the following values:
00819   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00820   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00821   * @param  Alignment: Specifies the data alignment.
00822   *          This parameter can be one of the following values:
00823   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00824   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00825   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00826   * @param  Data: Data to be loaded in the selected data holding register.
00827   * @retval HAL status
00828   */
00829 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00830 {
00831   __IO uint32_t tmp = 0U;
00832
00833   /* Check the parameters */
00834   assert_param(IS_DAC_CHANNEL(Channel));
00835   assert_param(IS_DAC_ALIGN(Alignment));
00836   assert_param(IS_DAC_DATA(Data));
00837
00838   tmp = (uint32_t)hdac->Instance;
00839   if(Channel == DAC_CHANNEL_1)
00840   {
00841     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00842   }
00843   else
00844   {
00845     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00846   }
00847
00848   /* Set the DAC channel1 selected data holding register */
00849   *(__IO uint32_t *) tmp = Data;
00850
00851   /* Return function status */
00852   return HAL_OK;
00853 }
00854
00855 /**
00856   * @}
00857   */
00858
00859 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
00860  *  @brief   Peripheral State and Errors functions
00861  *
00862 @verbatim
00863   ==============================================================================
00864             ##### Peripheral State and Errors functions #####
00865   ==============================================================================
00866     [..]
00867     This subsection provides functions allowing to
00868       (+) Check the DAC state.
00869       (+) Check the DAC Errors.
00870
00871 @endverbatim
00872   * @{
00873   */
00874
00875 /**
00876   * @brief  return the DAC state
00877   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00878   *         the configuration information for the specified DAC.
00879   * @retval HAL state
00880   */
00881 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
00882 {
00883   /* Return DAC state */
00884   return hdac->State;
00885 }
00886
00887
00888 /**
00889   * @brief  Return the DAC error code
00890   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00891   *         the configuration information for the specified DAC.
00892   * @retval DAC Error Code
00893   */
00894 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
00895 {
00896   return hdac->ErrorCode;
00897 }
00898
00899 /**
00900   * @}
00901   */
00902
00903 /**
00904   * @brief  DMA conversion complete callback.
00905   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00906   *                the configuration information for the specified DMA module.
00907   * @retval None
00908   */
00909 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
00910 {
00911   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00912
00913   HAL_DAC_ConvCpltCallbackCh1(hdac);
00914
00915   hdac->State= HAL_DAC_STATE_READY;
00916 }
00917
00918 /**
00919   * @brief  DMA half transfer complete callback.
00920   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00921   *                the configuration information for the specified DMA module.
00922   * @retval None
00923   */
00924 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
00925 {
00926     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00927     /* Conversion complete callback */
00928     HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
00929 }
00930
00931 /**
00932   * @brief  DMA error callback
00933   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00934   *                the configuration information for the specified DMA module.
00935   * @retval None
00936   */
00937 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
00938 {
00939   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00940
00941   /* Set DAC error code to DMA error */
00942   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00943
00944   HAL_DAC_ErrorCallbackCh1(hdac);
00945
00946   hdac->State= HAL_DAC_STATE_READY;
00947 }
00948
00949 /**
00950   * @}
00951   */
00952 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00953           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
00954           STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
00955 #endif /* HAL_DAC_MODULE_ENABLED */
00956
00957 /**
00958   * @}
00959   */
00960
00961 /**
00962   * @}
00963   */
00964
00965 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac.h Source File

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stm32f4xx_hal_dac.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DAC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DAC_H
00040 #define __STM32F4xx_HAL_DAC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00047     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00048     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
00049     defined(STM32F469xx) || defined(STM32F479xx)
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32f4xx_hal_def.h"
00053
00054 /** @addtogroup STM32F4xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @addtogroup DAC
00059   * @{
00060   */
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 /** @defgroup DAC_Exported_Types DAC Exported Types
00064   * @{
00065   */
00066
00067 /**
00068   * @brief HAL State structures definition
00069   */
00070 typedef enum
00071 {
00072   HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
00073   HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
00074   HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
00075   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
00076   HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
00077 }HAL_DAC_StateTypeDef;
00078
00079 /**
00080   * @brief DAC handle Structure definition
00081   */
00082 typedef struct
00083 {
00084   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00085
00086   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00087
00088   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00089
00090   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00091
00092   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00093
00094   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00095
00096 }DAC_HandleTypeDef;
00097
00098 /**
00099   * @brief DAC Configuration regular Channel structure definition
00100   */
00101 typedef struct
00102 {
00103   uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
00104                                    This parameter can be a value of @ref DAC_trigger_selection */
00105
00106   uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00107                                    This parameter can be a value of @ref DAC_output_buffer */
00108 }DAC_ChannelConfTypeDef;
00109 /**
00110   * @}
00111   */
00112
00113 /* Exported constants --------------------------------------------------------*/
00114 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00115   * @{
00116   */
00117
00118 /** @defgroup DAC_Error_Code DAC Error Code
00119   * @{
00120   */
00121 #define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
00122 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DAM underrun error   */
00123 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DAM underrun error   */
00124 #define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup DAC_trigger_selection DAC Trigger Selection
00130   * @{
00131   */
00132
00133 #define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
00134                                                                        has been loaded, and not by external trigger */
00135 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00136 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00137 #define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00138 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00139 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00140 #define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
00141
00142 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00143 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup DAC_output_buffer  DAC Output Buffer
00149   * @{
00150   */
00151 #define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000U)
00152 #define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
00153 /**
00154   * @}
00155   */
00156
00157 /** @defgroup DAC_Channel_selection DAC Channel Selection
00158   * @{
00159   */
00160 #define DAC_CHANNEL_1                      ((uint32_t)0x00000000U)
00161 #define DAC_CHANNEL_2                      ((uint32_t)0x00000010U)
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup DAC_data_alignment DAC Data Alignment
00167   * @{
00168   */
00169 #define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000U)
00170 #define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004U)
00171 #define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008U)
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup DAC_flags_definition DAC Flags Definition
00177   * @{
00178   */
00179 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00180 #define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup DAC_IT_definition DAC IT Definition
00186   * @{
00187   */
00188 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00189 #define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00190 /**
00191   * @}
00192   */
00193
00194 /**
00195   * @}
00196   */
00197
00198 /* Exported macro ------------------------------------------------------------*/
00199 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00200   * @{
00201   */
00202
00203 /** @brief Reset DAC handle state
00204   * @param  __HANDLE__: specifies the DAC handle.
00205   * @retval None
00206   */
00207 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00208
00209 /** @brief Enable the DAC channel
00210   * @param  __HANDLE__: specifies the DAC handle.
00211   * @param  __DAC_Channel__: specifies the DAC channel
00212   * @retval None
00213   */
00214 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
00215
00216 /** @brief Disable the DAC channel
00217   * @param  __HANDLE__: specifies the DAC handle
00218   * @param  __DAC_Channel__: specifies the DAC channel.
00219   * @retval None
00220   */
00221 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
00222
00223 /** @brief Enable the DAC interrupt
00224   * @param  __HANDLE__: specifies the DAC handle
00225   * @param  __INTERRUPT__: specifies the DAC interrupt.
00226   * @retval None
00227   */
00228 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00229
00230 /** @brief Disable the DAC interrupt
00231   * @param  __HANDLE__: specifies the DAC handle
00232   * @param  __INTERRUPT__: specifies the DAC interrupt.
00233   * @retval None
00234   */
00235 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00236
00237 /** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
00238   * @param __HANDLE__: DAC handle
00239   * @param __INTERRUPT__: DAC interrupt source to check
00240   *          This parameter can be any combination of the following values:
00241   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00242   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00243   * @retval State of interruption (SET or RESET)
00244   */
00245 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00246
00247 /** @brief  Get the selected DAC's flag status.
00248   * @param  __HANDLE__: specifies the DAC handle.
00249   * @param  __FLAG__: specifies the flag to clear.
00250   *         This parameter can be any combination of the following values:
00251   *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
00252   *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
00253   * @retval None
00254   */
00255 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00256
00257 /** @brief  Clear the DAC's flag.
00258   * @param  __HANDLE__: specifies the DAC handle.
00259   * @param  __FLAG__: specifies the flag to clear.
00260   *         This parameter can be any combination of the following values:
00261   *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
00262   *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
00263   * @retval None
00264   */
00265 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00266 /**
00267   * @}
00268   */
00269
00270 /* Include DAC HAL Extension module */
00271 #include "stm32f4xx_hal_dac_ex.h"
00272
00273 /* Exported functions --------------------------------------------------------*/
00274 /** @addtogroup DAC_Exported_Functions
00275   * @{
00276   */
00277
00278 /** @addtogroup DAC_Exported_Functions_Group1
00279   * @{
00280   */
00281 /* Initialization/de-initialization functions *********************************/
00282 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
00283 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
00284 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
00285 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
00286 /**
00287   * @}
00288   */
00289
00290 /** @addtogroup DAC_Exported_Functions_Group2
00291   * @{
00292   */
00293 /* I/O operation functions ****************************************************/
00294 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
00295 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
00296 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
00297 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
00298 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
00299 /**
00300   * @}
00301   */
00302
00303 /** @addtogroup DAC_Exported_Functions_Group3
00304   * @{
00305   */
00306 /* Peripheral Control functions ***********************************************/
00307 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00308 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00309 /**
00310   * @}
00311   */
00312
00313 /** @addtogroup DAC_Exported_Functions_Group4
00314   * @{
00315   */
00316 /* Peripheral State functions *************************************************/
00317 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
00318 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
00319 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00320
00321 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00322 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00323 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00324 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332 /* Private types -------------------------------------------------------------*/
00333 /* Private variables ---------------------------------------------------------*/
00334 /* Private constants ---------------------------------------------------------*/
00335 /** @defgroup DAC_Private_Constants DAC Private Constants
00336   * @{
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 /* Private macros ------------------------------------------------------------*/
00344 /** @defgroup DAC_Private_Macros DAC Private Macros
00345   * @{
00346   */
00347 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
00348 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00349                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00350                              ((ALIGN) == DAC_ALIGN_8B_R))
00351 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00352                                  ((CHANNEL) == DAC_CHANNEL_2))
00353 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00354                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00355
00356 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00357                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00358                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
00359                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00360                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
00361                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00362                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00363                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00364                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00365
00366 /** @brief Set DHR12R1 alignment
00367   * @param  __ALIGNMENT__: specifies the DAC alignment
00368   * @retval None
00369   */
00370 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
00371
00372 /** @brief  Set DHR12R2 alignment
00373   * @param  __ALIGNMENT__: specifies the DAC alignment
00374   * @retval None
00375   */
00376 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
00377
00378 /** @brief  Set DHR12RD alignment
00379   * @param  __ALIGNMENT__: specifies the DAC alignment
00380   * @retval None
00381   */
00382 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
00383
00384 /**
00385   * @}
00386   */
00387
00388 /* Private functions ---------------------------------------------------------*/
00389 /** @defgroup DAC_Private_Functions DAC Private Functions
00390   * @{
00391   */
00392 /**
00393   * @}
00394   */
00395 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00396           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
00397           STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
00398
00399 /**
00400   * @}
00401   */
00402
00403 /**
00404   * @}
00405   */
00406
00407 #ifdef __cplusplus
00408 }
00409 #endif
00410
00411 #endif /*__STM32F4xx_HAL_DAC_H */
00412
00413 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac_ex.c Source File

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stm32f4xx_hal_dac_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of DAC extension peripheral:
00010   *           + Extended features functions
00011   *
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
00019           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00020           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
00021       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00022       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00023
00024  @endverbatim
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00029   *
00030   * Redistribution and use in source and binary forms, with or without modification,
00031   * are permitted provided that the following conditions are met:
00032   *   1. Redistributions of source code must retain the above copyright notice,
00033   *      this list of conditions and the following disclaimer.
00034   *   2. Redistributions in binary form must reproduce the above copyright notice,
00035   *      this list of conditions and the following disclaimer in the documentation
00036   *      and/or other materials provided with the distribution.
00037   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00038   *      may be used to endorse or promote products derived from this software
00039   *      without specific prior written permission.
00040   *
00041   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00042   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00043   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00044   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00045   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00046   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00047   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00048   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00049   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00050   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00051   *
00052   ******************************************************************************
00053   */
00054
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32f4xx_hal.h"
00058
00059 /** @addtogroup STM32F4xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup DACEx DACEx
00064   * @brief DAC driver modules
00065   * @{
00066   */
00067
00068 #ifdef HAL_DAC_MODULE_ENABLED
00069
00070 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00071     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00072     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
00073     defined(STM32F469xx) || defined(STM32F479xx)
00074 /* Private typedef -----------------------------------------------------------*/
00075 /* Private define ------------------------------------------------------------*/
00076 /* Private macro -------------------------------------------------------------*/
00077 /* Private variables ---------------------------------------------------------*/
00078 /* Private function prototypes -----------------------------------------------*/
00079 /* Private functions ---------------------------------------------------------*/
00080 /* Exported functions --------------------------------------------------------*/
00081 /** @defgroup DACEx_Exported_Functions DAC Exported Functions
00082   * @{
00083   */
00084
00085 /** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
00086  *  @brief    Extended features functions
00087  *
00088 @verbatim
00089   ==============================================================================
00090                  ##### Extended features functions #####
00091   ==============================================================================
00092     [..]  This section provides functions allowing to:
00093       (+) Start conversion.
00094       (+) Stop conversion.
00095       (+) Start conversion and enable DMA transfer.
00096       (+) Stop conversion and disable DMA transfer.
00097       (+) Get result of conversion.
00098       (+) Get result of dual mode conversion.
00099
00100 @endverbatim
00101   * @{
00102   */
00103
00104 /**
00105   * @brief  Returns the last data output value of the selected DAC channel.
00106   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00107   *         the configuration information for the specified DAC.
00108   * @retval The selected DAC channel data output value.
00109   */
00110 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
00111 {
00112   uint32_t tmp = 0U;
00113
00114   tmp |= hdac->Instance->DOR1;
00115
00116   tmp |= hdac->Instance->DOR2 << 16U;
00117
00118   /* Returns the DAC channel data output register value */
00119   return tmp;
00120 }
00121
00122 /**
00123   * @brief  Enables or disables the selected DAC channel wave generation.
00124   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00125   *         the configuration information for the specified DAC.
00126   * @param  Channel: The selected DAC channel.
00127   *          This parameter can be one of the following values:
00128   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
00129   * @param  Amplitude: Select max triangle amplitude.
00130   *          This parameter can be one of the following values:
00131   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00132   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00133   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00134   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00135   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00136   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00137   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00138   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00139   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00140   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00141   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00142   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00143   * @retval HAL status
00144   */
00145 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00146 {
00147   /* Check the parameters */
00148   assert_param(IS_DAC_CHANNEL(Channel));
00149   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00150
00151   /* Process locked */
00152   __HAL_LOCK(hdac);
00153
00154   /* Change DAC state */
00155   hdac->State = HAL_DAC_STATE_BUSY;
00156
00157   /* Enable the selected wave generation for the selected DAC channel */
00158   MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
00159
00160   /* Change DAC state */
00161   hdac->State = HAL_DAC_STATE_READY;
00162
00163   /* Process unlocked */
00164   __HAL_UNLOCK(hdac);
00165
00166   /* Return function status */
00167   return HAL_OK;
00168 }
00169
00170 /**
00171   * @brief  Enables or disables the selected DAC channel wave generation.
00172   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00173   *         the configuration information for the specified DAC.
00174   * @param  Channel: The selected DAC channel.
00175   *          This parameter can be one of the following values:
00176   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
00177   * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
00178   *          This parameter can be one of the following values:
00179   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00180   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00181   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00182   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00183   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00184   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00185   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00186   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00187   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00188   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00189   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00190   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00194 {
00195   /* Check the parameters */
00196   assert_param(IS_DAC_CHANNEL(Channel));
00197   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00198
00199   /* Process locked */
00200   __HAL_LOCK(hdac);
00201
00202   /* Change DAC state */
00203   hdac->State = HAL_DAC_STATE_BUSY;
00204
00205   /* Enable the selected wave generation for the selected DAC channel */
00206   MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
00207
00208   /* Change DAC state */
00209   hdac->State = HAL_DAC_STATE_READY;
00210
00211   /* Process unlocked */
00212   __HAL_UNLOCK(hdac);
00213
00214   /* Return function status */
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  Set the specified data holding register value for dual DAC channel.
00220   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00221   *               the configuration information for the specified DAC.
00222   * @param  Alignment: Specifies the data alignment for dual channel DAC.
00223   *          This parameter can be one of the following values:
00224   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00225   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00226   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00227   * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
00228   * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
00229   * @note   In dual mode, a unique register access is required to write in both
00230   *          DAC channels at the same time.
00231   * @retval HAL status
00232   */
00233 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00234 {
00235   uint32_t data = 0U, tmp = 0U;
00236
00237   /* Check the parameters */
00238   assert_param(IS_DAC_ALIGN(Alignment));
00239   assert_param(IS_DAC_DATA(Data1));
00240   assert_param(IS_DAC_DATA(Data2));
00241
00242   /* Calculate and set dual DAC data holding register value */
00243   if (Alignment == DAC_ALIGN_8B_R)
00244   {
00245     data = ((uint32_t)Data2 << 8U) | Data1;
00246   }
00247   else
00248   {
00249     data = ((uint32_t)Data2 << 16U) | Data1;
00250   }
00251
00252   tmp = (uint32_t)hdac->Instance;
00253   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00254
00255   /* Set the dual DAC selected data holding register */
00256   *(__IO uint32_t *)tmp = data;
00257
00258   /* Return function status */
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @}
00264   */
00265
00266 /**
00267   * @brief  Conversion complete callback in non blocking mode for Channel2
00268   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00269   *         the configuration information for the specified DAC.
00270   * @retval None
00271   */
00272 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00273 {
00274   /* Prevent unused argument(s) compilation warning */
00275   UNUSED(hdac);
00276   /* NOTE : This function Should not be modified, when the callback is needed,
00277             the HAL_DAC_ConvCpltCallback could be implemented in the user file
00278    */
00279 }
00280
00281 /**
00282   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2
00283   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00284   *         the configuration information for the specified DAC.
00285   * @retval None
00286   */
00287 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00288 {
00289   /* Prevent unused argument(s) compilation warning */
00290   UNUSED(hdac);
00291   /* NOTE : This function Should not be modified, when the callback is needed,
00292             the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
00293    */
00294 }
00295
00296 /**
00297   * @brief  Error DAC callback for Channel2.
00298   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00299   *         the configuration information for the specified DAC.
00300   * @retval None
00301   */
00302 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00303 {
00304   /* Prevent unused argument(s) compilation warning */
00305   UNUSED(hdac);
00306   /* NOTE : This function Should not be modified, when the callback is needed,
00307             the HAL_DAC_ErrorCallback could be implemented in the user file
00308    */
00309 }
00310
00311 /**
00312   * @brief  DMA underrun DAC callback for channel2.
00313   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00314   *         the configuration information for the specified DAC.
00315   * @retval None
00316   */
00317 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00318 {
00319   /* Prevent unused argument(s) compilation warning */
00320   UNUSED(hdac);
00321   /* NOTE : This function Should not be modified, when the callback is needed,
00322             the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
00323    */
00324 }
00325
00326 /**
00327   * @brief  DMA conversion complete callback.
00328   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00329   *                the configuration information for the specified DMA module.
00330   * @retval None
00331   */
00332 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
00333 {
00334   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00335
00336   HAL_DACEx_ConvCpltCallbackCh2(hdac);
00337
00338   hdac->State= HAL_DAC_STATE_READY;
00339 }
00340
00341 /**
00342   * @brief  DMA half transfer complete callback.
00343   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00344   *                the configuration information for the specified DMA module.
00345   * @retval None
00346   */
00347 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
00348 {
00349     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00350     /* Conversion complete callback */
00351     HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
00352 }
00353
00354 /**
00355   * @brief  DMA error callback
00356   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00357   *                the configuration information for the specified DMA module.
00358   * @retval None
00359   */
00360 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
00361 {
00362   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00363
00364   /* Set DAC error code to DMA error */
00365   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00366
00367   HAL_DACEx_ErrorCallbackCh2(hdac);
00368
00369   hdac->State= HAL_DAC_STATE_READY;
00370 }
00371
00372 /**
00373   * @}
00374   */
00375
00376 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00377           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
00378           STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
00379
00380 #endif /* HAL_DAC_MODULE_ENABLED */
00381
00382 /**
00383   * @}
00384   */
00385
00386 /**
00387   * @}
00388   */
00389
00390 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dac_ex.h Source File

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stm32f4xx_hal_dac_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DAC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DAC_EX_H
00040 #define __STM32F4xx_HAL_DAC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00047     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00048     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
00049     defined(STM32F469xx) || defined(STM32F479xx)
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32f4xx_hal_def.h"
00053
00054 /** @addtogroup STM32F4xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @addtogroup DACEx
00059   * @{
00060   */
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 /* Exported constants --------------------------------------------------------*/
00064 /** @defgroup DACEx_Exported_Constants DAC Exported Constants
00065   * @{
00066   */
00067
00068 /** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
00069   * @{
00070   */
00071 #define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00072 #define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00073 #define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00074 #define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00075 #define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00076 #define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00077 #define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00078 #define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00079 #define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00080 #define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00081 #define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00082 #define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00083 #define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
00084 #define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00085 #define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
00086 #define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00087 #define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
00088 #define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00089 #define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
00090 #define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00091 #define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
00092 #define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00093 #define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
00094 #define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported macro ------------------------------------------------------------*/
00104 /* Exported functions --------------------------------------------------------*/
00105 /** @addtogroup DACEx_Exported_Functions
00106   * @{
00107   */
00108
00109 /** @addtogroup DACEx_Exported_Functions_Group1
00110   * @{
00111   */
00112 /* Extension features functions ***********************************************/
00113 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
00114 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00115 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00116 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00117
00118 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00119 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00120 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
00121 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
00122 /**
00123   * @}
00124   */
00125
00126 /**
00127   * @}
00128   */
00129 /* Private types -------------------------------------------------------------*/
00130 /* Private variables ---------------------------------------------------------*/
00131 /* Private constants ---------------------------------------------------------*/
00132 /** @defgroup DACEx_Private_Constants DAC Private Constants
00133   * @{
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140 /* Private macros ------------------------------------------------------------*/
00141 /** @defgroup DACEx_Private_Macros DAC Private Macros
00142   * @{
00143   */
00144 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00145                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00146                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00147                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00148                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00149                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00150                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00151                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00152                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00153                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00154                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00155                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00156                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00157                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00158                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00159                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00160                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00161                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00162                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00163                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00164                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00165                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00166                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00167                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00168 /**
00169   * @}
00170   */
00171
00172 /* Private functions ---------------------------------------------------------*/
00173 /** @defgroup DACEx_Private_Functions DAC Private Functions
00174   * @{
00175   */
00176 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00177 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00178 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00179 /**
00180   * @}
00181   */
00182 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00183           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
00184           STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @}
00192   */
00193
00194 #ifdef __cplusplus
00195 }
00196 #endif
00197
00198 #endif /*__STM32F4xx_HAL_DAC_EX_H */
00199
00200 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi.c Source File

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stm32f4xx_hal_dcmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dcmi.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DCMI HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020       The sequence below describes how to use this driver to capture image
00021       from a camera module connected to the DCMI Interface.
00022       This sequence does not take into account the configuration of the
00023       camera module, which should be made before to configure and enable
00024       the DCMI to capture images.
00025
00026     (#) Program the required configuration through following parameters:
00027         horizontal and vertical polarity, pixel clock polarity, Capture Rate,
00028         Synchronization Mode, code of the frame delimiter and data width
00029         using HAL_DCMI_Init() function.
00030
00031     (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
00032         register to the destination memory buffer.
00033
00034     (#) Program the required configuration through following parameters:
00035         DCMI mode, destination memory Buffer address and the data length
00036         and enable capture using HAL_DCMI_Start_DMA() function.
00037
00038     (#) Optionally, configure and Enable the CROP feature to select a rectangular
00039         window from the received image using HAL_DCMI_ConfigCrop()
00040         and HAL_DCMI_EnableCROP() functions
00041
00042     (#) The capture can be stopped using HAL_DCMI_Stop() function.
00043
00044     (#) To control DCMI state you can use the function HAL_DCMI_GetState().
00045
00046      *** DCMI HAL driver macros list ***
00047      =============================================
00048      [..]
00049        Below the list of most used macros in DCMI HAL driver.
00050
00051       (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
00052       (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
00053       (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
00054       (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
00055       (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
00056       (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
00057       (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
00058
00059      [..]
00060        (@) You can refer to the DCMI HAL driver header file for more useful macros
00061
00062   @endverbatim
00063   ******************************************************************************
00064   * @attention
00065   *
00066   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00067   *
00068   * Redistribution and use in source and binary forms, with or without modification,
00069   * are permitted provided that the following conditions are met:
00070   *   1. Redistributions of source code must retain the above copyright notice,
00071   *      this list of conditions and the following disclaimer.
00072   *   2. Redistributions in binary form must reproduce the above copyright notice,
00073   *      this list of conditions and the following disclaimer in the documentation
00074   *      and/or other materials provided with the distribution.
00075   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00076   *      may be used to endorse or promote products derived from this software
00077   *      without specific prior written permission.
00078   *
00079   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00080   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00081   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00082   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00083   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00084   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00085   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00086   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00087   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00088   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32f4xx_hal.h"
00095
00096 /** @addtogroup STM32F4xx_HAL_Driver
00097   * @{
00098   */
00099 /** @defgroup DCMI DCMI
00100   * @brief DCMI HAL module driver
00101   * @{
00102   */
00103
00104 #ifdef HAL_DCMI_MODULE_ENABLED
00105
00106 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
00107     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00108     defined(STM32F479xx)
00109 /* Private typedef -----------------------------------------------------------*/
00110 /* Private define ------------------------------------------------------------*/
00111 #define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000U)  /* 1s  */
00112 /* Private macro -------------------------------------------------------------*/
00113 /* Private variables ---------------------------------------------------------*/
00114 /* Private function prototypes -----------------------------------------------*/
00115 static void       DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
00116 static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
00117
00118 /* Exported functions --------------------------------------------------------*/
00119
00120 /** @defgroup DCMI_Exported_Functions DCMI Exported Functions
00121   * @{
00122   */
00123
00124 /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
00125   *  @brief   Initialization and Configuration functions
00126   *
00127 @verbatim
00128  ===============================================================================
00129                 ##### Initialization and Configuration functions #####
00130  ===============================================================================
00131     [..]  This section provides functions allowing to:
00132       (+) Initialize and configure the DCMI
00133       (+) De-initialize the DCMI
00134
00135 @endverbatim
00136   * @{
00137   */
00138
00139 /**
00140   * @brief  Initializes the DCMI according to the specified
00141   *         parameters in the DCMI_InitTypeDef and create the associated handle.
00142   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00143   *                the configuration information for DCMI.
00144   * @retval HAL status
00145   */
00146 __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
00147 {
00148   /* Check the DCMI peripheral state */
00149   if(hdcmi == NULL)
00150   {
00151      return HAL_ERROR;
00152   }
00153
00154   /* Check function parameters */
00155   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
00156   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
00157   assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
00158   assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
00159   assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
00160   assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
00161   assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
00162   assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
00163
00164   if(hdcmi->State == HAL_DCMI_STATE_RESET)
00165   {
00166     /* Allocate lock resource and initialize it */
00167     hdcmi->Lock = HAL_UNLOCKED;
00168     /* Init the low level hardware */
00169     HAL_DCMI_MspInit(hdcmi);
00170   }
00171
00172   /* Change the DCMI state */
00173   hdcmi->State = HAL_DCMI_STATE_BUSY;
00174   /* Configures the HS, VS, DE and PC polarity */
00175   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |
00176                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |
00177                            DCMI_CR_ESS);
00178   hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
00179                                      hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  | \
00180                                      hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
00181                                      hdcmi->Init.JPEGMode);
00182
00183   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
00184   {
00185     DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
00186                   ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8U)|
00187                   ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16U) |
00188                   ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24U));
00189
00190   }
00191
00192   /* Enable DCMI by setting DCMIEN bit */
00193   __HAL_DCMI_ENABLE(hdcmi);
00194
00195   /* Update error code */
00196   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00197
00198   /* Initialize the DCMI state*/
00199   hdcmi->State  = HAL_DCMI_STATE_READY;
00200
00201   return HAL_OK;
00202 }
00203
00204 /**
00205   * @brief  Deinitializes the DCMI peripheral registers to their default reset
00206   *         values.
00207   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00208   *                the configuration information for DCMI.
00209   * @retval HAL status
00210   */
00211
00212 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
00213 {
00214   /* DeInit the low level hardware */
00215   HAL_DCMI_MspDeInit(hdcmi);
00216
00217   /* Update error code */
00218   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00219
00220   /* Initialize the DCMI state*/
00221   hdcmi->State = HAL_DCMI_STATE_RESET;
00222
00223   /* Release Lock */
00224   __HAL_UNLOCK(hdcmi);
00225
00226   return HAL_OK;
00227 }
00228
00229 /**
00230   * @brief  Initializes the DCMI MSP.
00231   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00232   *                the configuration information for DCMI.
00233   * @retval None
00234   */
00235 __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
00236 {
00237   /* Prevent unused argument(s) compilation warning */
00238   UNUSED(hdcmi);
00239   /* NOTE : This function Should not be modified, when the callback is needed,
00240             the HAL_DCMI_MspInit could be implemented in the user file
00241    */
00242 }
00243
00244 /**
00245   * @brief  DeInitializes the DCMI MSP.
00246   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00247   *                the configuration information for DCMI.
00248   * @retval None
00249   */
00250 __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
00251 {
00252   /* Prevent unused argument(s) compilation warning */
00253   UNUSED(hdcmi);
00254   /* NOTE : This function Should not be modified, when the callback is needed,
00255             the HAL_DCMI_MspDeInit could be implemented in the user file
00256    */
00257 }
00258
00259 /**
00260   * @}
00261   */
00262 /** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
00263   *  @brief   IO operation functions
00264   *
00265 @verbatim
00266  ===============================================================================
00267                       #####  IO operation functions  #####
00268  ===============================================================================
00269     [..]  This section provides functions allowing to:
00270       (+) Configure destination address and data length and
00271           Enables DCMI DMA request and enables DCMI capture
00272       (+) Stop the DCMI capture.
00273       (+) Handles DCMI interrupt request.
00274
00275 @endverbatim
00276   * @{
00277   */
00278
00279 /**
00280   * @brief  Enables DCMI DMA request and enables DCMI capture
00281   * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains
00282   *                    the configuration information for DCMI.
00283   * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.
00284   * @param  pData:     The destination memory Buffer address (LCD Frame buffer).
00285   * @param  Length:    The length of capture to be transferred.
00286   * @retval HAL status
00287   */
00288 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
00289 {
00290   /* Initialize the second memory address */
00291   uint32_t SecondMemAddress = 0U;
00292
00293   /* Check function parameters */
00294   assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
00295
00296   /* Process Locked */
00297   __HAL_LOCK(hdcmi);
00298
00299   /* Enable the Line, Vsync, Error and Overrun interrupts */
00300   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVF);
00301
00302   /* Disable the End of Frame interrupt */
00303   __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
00304
00305   /* Lock the DCMI peripheral state */
00306   hdcmi->State = HAL_DCMI_STATE_BUSY;
00307
00308   /* Check the parameters */
00309   assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
00310
00311   /* Configure the DCMI Mode */
00312   hdcmi->Instance->CR &= ~(DCMI_CR_CM);
00313   hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);
00314
00315   /* Set the DMA memory0 conversion complete callback */
00316   hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
00317
00318   /* Set the DMA error callback */
00319   hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
00320
00321   if(Length <= 0xFFFFU)
00322   {
00323     /* Enable the DMA Stream */
00324     HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
00325   }
00326   else /* DCMI_DOUBLE_BUFFER Mode */
00327   {
00328     /* Set the DMA memory1 conversion complete callback */
00329     hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
00330
00331     /* Initialize transfer parameters */
00332     hdcmi->XferCount = 1U;
00333     hdcmi->XferSize = Length;
00334     hdcmi->pBuffPtr = pData;
00335
00336     /* Get the number of buffer */
00337     while(hdcmi->XferSize > 0xFFFFU)
00338     {
00339       hdcmi->XferSize = (hdcmi->XferSize/2U);
00340       hdcmi->XferCount = hdcmi->XferCount*2U;
00341     }
00342
00343     /* Update DCMI counter  and transfer number*/
00344     hdcmi->XferCount = (hdcmi->XferCount - 2U);
00345     hdcmi->XferTransferNumber = hdcmi->XferCount;
00346
00347     /* Update second memory address */
00348     SecondMemAddress = (uint32_t)(pData + (4U*hdcmi->XferSize));
00349
00350     /* Start DMA multi buffer transfer */
00351     HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
00352   }
00353
00354   /* Enable Capture */
00355   DCMI->CR |= DCMI_CR_CAPTURE;
00356
00357   /* Return function status */
00358   return HAL_OK;
00359 }
00360
00361 /**
00362   * @brief  Disable DCMI DMA request and Disable DCMI capture
00363   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00364   *                the configuration information for DCMI.
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
00368 {
00369   uint32_t tickstart = 0U;
00370
00371   /* Lock the DCMI peripheral state */
00372   hdcmi->State = HAL_DCMI_STATE_BUSY;
00373
00374   __HAL_DCMI_DISABLE(hdcmi);
00375
00376   /* Disable Capture */
00377   DCMI->CR &= ~(DCMI_CR_CAPTURE);
00378
00379   /* Get tick */
00380   tickstart = HAL_GetTick();
00381
00382   /* Check if the DCMI capture effectively disabled */
00383   while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U)
00384   {
00385     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)
00386     {
00387       /* Process Unlocked */
00388       __HAL_UNLOCK(hdcmi);
00389
00390       /* Update error code */
00391       hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
00392
00393       /* Change DCMI state */
00394       hdcmi->State = HAL_DCMI_STATE_TIMEOUT;
00395
00396       return HAL_TIMEOUT;
00397     }
00398   }
00399
00400   /* Disable the DMA */
00401   HAL_DMA_Abort(hdcmi->DMA_Handle);
00402
00403   /* Update error code */
00404   hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
00405
00406   /* Change DCMI state */
00407   hdcmi->State = HAL_DCMI_STATE_READY;
00408
00409   /* Process Unlocked */
00410   __HAL_UNLOCK(hdcmi);
00411
00412   /* Return function status */
00413   return HAL_OK;
00414 }
00415
00416 /**
00417   * @brief  Handles DCMI interrupt request.
00418   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00419   *                the configuration information for the DCMI.
00420   * @retval None
00421   */
00422 void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
00423 {
00424   /* Synchronization error interrupt management *******************************/
00425   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)
00426   {
00427     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)
00428     {
00429       /* Clear the Synchronization error flag */
00430       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
00431
00432       /* Update error code */
00433       hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
00434
00435       /* Change DCMI state */
00436       hdcmi->State = HAL_DCMI_STATE_ERROR;
00437
00438       /* Process Unlocked */
00439       __HAL_UNLOCK(hdcmi);
00440
00441       /* Abort the DMA Transfer */
00442       HAL_DMA_Abort(hdcmi->DMA_Handle);
00443
00444       /* Synchronization error Callback */
00445       HAL_DCMI_ErrorCallback(hdcmi);
00446     }
00447   }
00448   /* Overflow interrupt management ********************************************/
00449   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET)
00450   {
00451     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)
00452     {
00453       /* Clear the Overflow flag */
00454       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);
00455
00456       /* Update error code */
00457       hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;
00458
00459       /* Change DCMI state */
00460       hdcmi->State = HAL_DCMI_STATE_ERROR;
00461
00462       /* Process Unlocked */
00463       __HAL_UNLOCK(hdcmi);
00464
00465       /* Abort the DMA Transfer */
00466       HAL_DMA_Abort(hdcmi->DMA_Handle);
00467
00468       /* Overflow Callback */
00469       HAL_DCMI_ErrorCallback(hdcmi);
00470     }
00471   }
00472   /* Line Interrupt management ************************************************/
00473   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)
00474   {
00475     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)
00476     {
00477       /* Clear the Line interrupt flag */
00478       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
00479
00480       /* Process Unlocked */
00481       __HAL_UNLOCK(hdcmi);
00482
00483       /* Line interrupt Callback */
00484       HAL_DCMI_LineEventCallback(hdcmi);
00485     }
00486   }
00487   /* VSYNC interrupt management ***********************************************/
00488   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)
00489   {
00490     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)
00491     {
00492       /* Clear the VSYNC flag */
00493       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
00494
00495       /* Process Unlocked */
00496       __HAL_UNLOCK(hdcmi);
00497
00498       /* VSYNC Callback */
00499       HAL_DCMI_VsyncEventCallback(hdcmi);
00500     }
00501   }
00502   /* End of Frame interrupt management ****************************************/
00503   if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
00504   {
00505     if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)
00506     {
00507       /* Disable the Line interrupt when using snapshot mode */
00508       if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
00509       {
00510         __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE);
00511       }
00512       /* Disable the End of frame, Vsync, Error and Overrun interrupts */
00513       __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVF);
00514
00515       /* Clear the End of Frame flag */
00516       __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
00517
00518       /* Process Unlocked */
00519       __HAL_UNLOCK(hdcmi);
00520
00521       /* End of Frame Callback */
00522       HAL_DCMI_FrameEventCallback(hdcmi);
00523     }
00524   }
00525 }
00526
00527 /**
00528 * @brief  Error DCMI callback.
00529   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00530   *                the configuration information for DCMI.
00531   * @retval None
00532   */
00533 __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
00534 {
00535   /* Prevent unused argument(s) compilation warning */
00536   UNUSED(hdcmi);
00537   /* NOTE : This function Should not be modified, when the callback is needed,
00538             the HAL_DCMI_ErrorCallback could be implemented in the user file
00539    */
00540 }
00541
00542 /**
00543   * @brief  Line Event callback.
00544   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00545   *                the configuration information for DCMI.
00546   * @retval None
00547   */
00548 __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
00549 {
00550   /* Prevent unused argument(s) compilation warning */
00551   UNUSED(hdcmi);
00552   /* NOTE : This function Should not be modified, when the callback is needed,
00553             the HAL_DCMI_LineEventCallback could be implemented in the user file
00554    */
00555 }
00556
00557 /**
00558   * @brief  VSYNC Event callback.
00559   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00560   *                the configuration information for DCMI.
00561   * @retval None
00562   */
00563 __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
00564 {
00565   /* Prevent unused argument(s) compilation warning */
00566   UNUSED(hdcmi);
00567   /* NOTE : This function Should not be modified, when the callback is needed,
00568             the HAL_DCMI_VsyncEventCallback could be implemented in the user file
00569    */
00570 }
00571
00572 /**
00573   * @brief  Frame Event callback.
00574   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00575   *                the configuration information for DCMI.
00576   * @retval None
00577   */
00578 __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
00579 {
00580   /* Prevent unused argument(s) compilation warning */
00581   UNUSED(hdcmi);
00582   /* NOTE : This function Should not be modified, when the callback is needed,
00583             the HAL_DCMI_FrameEventCallback could be implemented in the user file
00584    */
00585 }
00586
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
00592   *  @brief    Peripheral Control functions
00593   *
00594 @verbatim
00595  ===============================================================================
00596                     ##### Peripheral Control functions #####
00597  ===============================================================================
00598 [..]  This section provides functions allowing to:
00599       (+) Configure the CROP feature.
00600       (+) Enable/Disable the CROP feature.
00601
00602 @endverbatim
00603   * @{
00604   */
00605
00606 /**
00607   * @brief  Configure the DCMI CROP coordinate.
00608   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00609   *                the configuration information for DCMI.
00610   * @param  X0:    DCMI window X offset
00611   * @param  Y0:    DCMI window Y offset
00612   * @param  XSize: DCMI Pixel per line
00613   * @param  YSize: DCMI Line number
00614   * @retval HAL status
00615   */
00616 HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
00617 {
00618   /* Process Locked */
00619   __HAL_LOCK(hdcmi);
00620
00621   /* Lock the DCMI peripheral state */
00622   hdcmi->State = HAL_DCMI_STATE_BUSY;
00623
00624   /* Check the parameters */
00625   assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
00626   assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
00627   assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
00628   assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
00629
00630   /* Configure CROP */
00631   DCMI->CWSIZER = (XSize | (YSize << 16U));
00632   DCMI->CWSTRTR = (X0 | (Y0 << 16U));
00633
00634   /* Initialize the DCMI state*/
00635   hdcmi->State  = HAL_DCMI_STATE_READY;
00636
00637   /* Process Unlocked */
00638   __HAL_UNLOCK(hdcmi);
00639
00640   return HAL_OK;
00641 }
00642
00643 /**
00644   * @brief  Disable the Crop feature.
00645   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00646   *                the configuration information for DCMI.
00647   * @retval HAL status
00648   */
00649 HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
00650 {
00651   /* Process Locked */
00652   __HAL_LOCK(hdcmi);
00653
00654   /* Lock the DCMI peripheral state */
00655   hdcmi->State = HAL_DCMI_STATE_BUSY;
00656
00657   /* Disable DCMI Crop feature */
00658   DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
00659
00660   /* Change the DCMI state*/
00661   hdcmi->State = HAL_DCMI_STATE_READY;
00662
00663   /* Process Unlocked */
00664   __HAL_UNLOCK(hdcmi);
00665
00666   return HAL_OK;
00667 }
00668
00669 /**
00670   * @brief  Enable the Crop feature.
00671   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00672   *                the configuration information for DCMI.
00673   * @retval HAL status
00674   */
00675 HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
00676 {
00677   /* Process Locked */
00678   __HAL_LOCK(hdcmi);
00679
00680   /* Lock the DCMI peripheral state */
00681   hdcmi->State = HAL_DCMI_STATE_BUSY;
00682
00683   /* Enable DCMI Crop feature */
00684   DCMI->CR |= (uint32_t)DCMI_CR_CROP;
00685
00686   /* Change the DCMI state*/
00687   hdcmi->State = HAL_DCMI_STATE_READY;
00688
00689   /* Process Unlocked */
00690   __HAL_UNLOCK(hdcmi);
00691
00692   return HAL_OK;
00693 }
00694
00695 /**
00696   * @}
00697   */
00698
00699 /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
00700   *  @brief    Peripheral State functions
00701   *
00702 @verbatim
00703  ===============================================================================
00704                ##### Peripheral State and Errors functions #####
00705  ===============================================================================
00706     [..]
00707     This subsection provides functions allowing to
00708       (+) Check the DCMI state.
00709       (+) Get the specific DCMI error flag.
00710
00711 @endverbatim
00712   * @{
00713   */
00714
00715 /**
00716   * @brief  Return the DCMI state
00717   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00718   *                the configuration information for DCMI.
00719   * @retval HAL state
00720   */
00721 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
00722 {
00723   return hdcmi->State;
00724 }
00725
00726 /**
00727   * @brief  Return the DCMI error code
00728   * @param  hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
00729   *               the configuration information for DCMI.
00730   * @retval DCMI Error Code
00731   */
00732 uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
00733 {
00734   return hdcmi->ErrorCode;
00735 }
00736 /**
00737   * @}
00738   */
00739
00740 /* Private functions ---------------------------------------------------------*/
00741 /** @defgroup DCMI_Private_Functions DCMI Private Functions
00742   * @{
00743   */
00744
00745 /**
00746   * @brief  DMA conversion complete callback.
00747   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00748   *                the configuration information for the specified DMA module.
00749   * @retval None
00750   */
00751 static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
00752 {
00753   uint32_t tmp = 0U;
00754
00755   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00756   hdcmi->State= HAL_DCMI_STATE_READY;
00757
00758   if(hdcmi->XferCount != 0U)
00759   {
00760     /* Update memory 0 address location */
00761     tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
00762     if(((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U))
00763     {
00764       tmp = hdcmi->DMA_Handle->Instance->M0AR;
00765       HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY0);
00766       hdcmi->XferCount--;
00767     }
00768     /* Update memory 1 address location */
00769     else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0U)
00770     {
00771       tmp = hdcmi->DMA_Handle->Instance->M1AR;
00772       HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U*hdcmi->XferSize)), MEMORY1);
00773       hdcmi->XferCount--;
00774     }
00775   }
00776   /* Update memory 0 address location */
00777   else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0U)
00778   {
00779     hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
00780   }
00781   /* Update memory 1 address location */
00782   else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0U)
00783   {
00784     tmp = hdcmi->pBuffPtr;
00785     hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4U*hdcmi->XferSize));
00786     hdcmi->XferCount = hdcmi->XferTransferNumber;
00787   }
00788
00789   /* Enable the Frame interrupt */
00790   __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
00791 }
00792
00793 /**
00794   * @brief  DMA error callback
00795   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00796   *                the configuration information for the specified DMA module.
00797   * @retval None
00798   */
00799 static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
00800 {
00801   DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00802   hdcmi->State= HAL_DCMI_STATE_READY;
00803   HAL_DCMI_ErrorCallback(hdcmi);
00804 }
00805 /**
00806   * @}
00807   */
00808
00809 /**
00810   * @}
00811   */
00812 #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00813           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
00814           STM32F479xx */
00815 #endif /* HAL_DCMI_MODULE_ENABLED */
00816 /**
00817   * @}
00818   */
00819
00820 /**
00821   * @}
00822   */
00823
00824 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi.h Source File

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stm32f4xx_hal_dcmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dcmi.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DCMI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DCMI_H
00040 #define __STM32F4xx_HAL_DCMI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
00047     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00048     defined(STM32F479xx)
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_hal_def.h"
00051
00052 /* Include DCMI HAL Extended module */
00053 /* (include on top of file since DCMI structures are defined in extended file) */
00054 #include "stm32f4xx_hal_dcmi_ex.h"
00055
00056 /** @addtogroup STM32F4xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @addtogroup DCMI DCMI
00061   * @brief DCMI HAL module driver
00062   * @{
00063   */
00064
00065 /* Exported types ------------------------------------------------------------*/
00066 /** @defgroup DCMI_Exported_Types DCMI Exported Types
00067   * @{
00068   */
00069 /**
00070   * @brief DCMI Error source
00071   */
00072 typedef enum
00073 {
00074   DCMI_ERROR_SYNC = 1,     /*!< Synchronisation error */
00075   DCMI_OVERRUN   = 2,      /*!< DCMI Overrun */
00076 }DCMI_ErrorTypeDef;
00077
00078
00079 /**
00080   * @brief  HAL DCMI State structures definition
00081   */
00082 typedef enum
00083 {
00084   HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
00085   HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
00086   HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
00087   HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
00088   HAL_DCMI_STATE_ERROR             = 0x04U   /*!< DCMI error state                      */
00089 }HAL_DCMI_StateTypeDef;
00090
00091 /**
00092   * @brief  DCMI handle Structure definition
00093   */
00094 typedef struct
00095 {
00096   DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
00097
00098   DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */
00099
00100   HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
00101
00102   __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
00103
00104   __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */
00105
00106   __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
00107
00108   uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */
00109
00110   uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
00111
00112   DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
00113
00114   __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
00115
00116 }DCMI_HandleTypeDef;
00117 /**
00118   * @}
00119   */
00120
00121 /* Exported constants --------------------------------------------------------*/
00122 /** @defgroup DCMI_Exported_Constants DCMI Exported Constants
00123   * @{
00124   */
00125
00126 /** @defgroup DCMI_Error_Code DCMI Error Code
00127   * @{
00128   */
00129 #define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */
00130 #define HAL_DCMI_ERROR_OVF       ((uint32_t)0x00000001U)    /*!< Overflow error        */
00131 #define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002U)    /*!< Synchronization error */
00132 #define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
00138   * @{
00139   */
00140 #define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000U)  /*!< The received data are transferred continuously
00141                                                                     into the destination memory through the DMA             */
00142 #define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of
00143                                                                     frame and then transfers a single frame through the DMA */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
00149   * @{
00150   */
00151 #define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)
00152                                                                    is synchronized with the HSYNC/VSYNC signals                  */
00153 #define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with
00154                                                                    synchronization codes embedded in the data flow               */
00155
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
00161   * @{
00162   */
00163 #define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000U)      /*!< Pixel clock active on Falling edge */
00164 #define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
00165
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
00171   * @{
00172   */
00173 #define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Vertical synchronization active Low  */
00174 #define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
00181   * @{
00182   */
00183 #define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Horizontal synchronization active Low  */
00184 #define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
00191   * @{
00192   */
00193 #define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000U)    /*!< Mode JPEG Disabled  */
00194 #define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
00201   * @{
00202   */
00203 #define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000U)      /*!< All frames are captured        */
00204 #define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
00205 #define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
00206
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
00212   * @{
00213   */
00214 #define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */
00215 #define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
00216 #define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
00217 #define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
00224   * @{
00225   */
00226 #define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFFU)  /*!< Window coordinate */
00227
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup DCMI_Window_Height DCMI Window Height
00233   * @{
00234   */
00235 #define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFFU)  /*!< Window Height */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
00242   * @{
00243   */
00244 #define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)
00245 #define DCMI_IT_OVF      ((uint32_t)DCMI_IER_OVF_IE)
00246 #define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)
00247 #define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)
00248 #define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup DCMI_Flags DCMI Flags
00254   * @{
00255   */
00256
00257 /**
00258   * @brief   DCMI SR register
00259   */
00260 #define DCMI_FLAG_HSYNC     ((uint32_t)0x2001U) /* State of HSYNC pin with the correct programmed polarity */
00261 #define DCMI_FLAG_VSYNC     ((uint32_t)0x2002U) /* State of VSYNC pin with the correct programmed polarity */
00262 #define DCMI_FLAG_FNE       ((uint32_t)0x2004U) /* Status of the FIFO */
00263 /**
00264   * @brief   DCMI RISR register
00265   */
00266 #define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RISR_FRAME_RIS)
00267 #define DCMI_FLAG_OVFRI      ((uint32_t)DCMI_RISR_OVF_RIS)
00268 #define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RISR_ERR_RIS)
00269 #define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RISR_VSYNC_RIS)
00270 #define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RISR_LINE_RIS)
00271 /**
00272   * @brief   DCMI MISR register
00273   */
00274 #define DCMI_FLAG_FRAMEMI    ((uint32_t)0x1001U)
00275 #define DCMI_FLAG_OVFMI      ((uint32_t)0x1002U)
00276 #define DCMI_FLAG_ERRMI      ((uint32_t)0x1004U)
00277 #define DCMI_FLAG_VSYNCMI    ((uint32_t)0x1008U)
00278 #define DCMI_FLAG_LINEMI     ((uint32_t)0x1010U)
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Exported macro ------------------------------------------------------------*/
00288 /** @defgroup DCMI_Exported_Macros DCMI Exported Macros
00289   * @{
00290   */
00291
00292 /** @brief Reset DCMI handle state
00293   * @param  __HANDLE__: specifies the DCMI handle.
00294   * @retval None
00295   */
00296 #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
00297
00298 /**
00299   * @brief  Enable the DCMI.
00300   * @param  __HANDLE__: DCMI handle
00301   * @retval None
00302   */
00303 #define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
00304
00305 /**
00306   * @brief  Disable the DCMI.
00307   * @param  __HANDLE__: DCMI handle
00308   * @retval None
00309   */
00310 #define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
00311
00312 /* Interrupt & Flag management */
00313 /**
00314   * @brief  Get the DCMI pending flags.
00315   * @param  __HANDLE__: DCMI handle
00316   * @param  __FLAG__: Get the specified flag.
00317   *         This parameter can be any combination of the following values:
00318   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
00319   *            @arg DCMI_FLAG_OVFRI: Overflow flag
00320   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag
00321   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag
00322   *            @arg DCMI_FLAG_LINERI: Line flag
00323   *            @arg DCMI_FLAG_FRAMEMI: Frame capture complete flag mask
00324   *            @arg DCMI_FLAG_OVFMI: Overflow flag mask
00325   *            @arg DCMI_FLAG_ERRMI: Synchronization error flag mask
00326   *            @arg DCMI_FLAG_VSYNCMI: VSYNC flag mask
00327   *            @arg DCMI_FLAG_LINEMI: Line flag mask
00328   *            @arg DCMI_FLAG_HSYNC: HSYNC flag
00329   *            @arg DCMI_FLAG_VSYNC: VSYNC flag
00330   *            @arg DCMI_FLAG_FNE: FNE flag
00331   * @retval The state of FLAG.
00332   */
00333 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
00334 ((((__FLAG__) & 0x3000U) == 0x00U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
00335  (((__FLAG__) & 0x2000U) == 0x00U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
00336
00337 /**
00338   * @brief  Clear the DCMI pending flags.
00339   * @param  __HANDLE__: DCMI handle
00340   * @param  __FLAG__: specifies the flag to clear.
00341   *         This parameter can be any combination of the following values:
00342   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
00343   *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
00344   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
00345   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
00346   *            @arg DCMI_FLAG_LINERI: Line flag mask
00347   * @retval None
00348   */
00349 #define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00350
00351 /**
00352   * @brief  Enable the specified DCMI interrupts.
00353   * @param  __HANDLE__:    DCMI handle
00354   * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
00355   *         This parameter can be any combination of the following values:
00356   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00357   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00358   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00359   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00360   *            @arg DCMI_IT_LINE: Line interrupt mask
00361   * @retval None
00362   */
00363 #define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00364
00365 /**
00366   * @brief  Disable the specified DCMI interrupts.
00367   * @param  __HANDLE__: DCMI handle
00368   * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
00369   *         This parameter can be any combination of the following values:
00370   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00371   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00372   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00373   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00374   *            @arg DCMI_IT_LINE: Line interrupt mask
00375   * @retval None
00376   */
00377 #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00378
00379 /**
00380   * @brief  Check whether the specified DCMI interrupt has occurred or not.
00381   * @param  __HANDLE__: DCMI handle
00382   * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.
00383   *         This parameter can be one of the following values:
00384   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
00385   *            @arg DCMI_IT_OVF: Overflow interrupt mask
00386   *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
00387   *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
00388   *            @arg DCMI_IT_LINE: Line interrupt mask
00389   * @retval The state of INTERRUPT.
00390   */
00391 #define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
00392
00393 /**
00394   * @}
00395   */
00396
00397 /* Exported functions --------------------------------------------------------*/
00398 /** @addtogroup DCMI_Exported_Functions
00399   * @{
00400   */
00401
00402 /** @addtogroup DCMI_Exported_Functions_Group1
00403  * @{
00404  */
00405
00406 /* Initialization and de-initialization functions *****************************/
00407 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
00408 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
00409 void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
00410 void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
00411 /**
00412   * @}
00413   */
00414
00415 /** @addtogroup DCMI_Exported_Functions_Group2
00416  * @{
00417  */
00418
00419 /* IO operation functions *****************************************************/
00420 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
00421 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
00422 void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
00423 void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
00424 void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
00425 void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
00426 void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
00427 /**
00428   * @}
00429   */
00430
00431 /** @addtogroup DCMI_Exported_Functions_Group3
00432  * @{
00433  */
00434 /* Peripheral Control functions ***********************************************/
00435 HAL_StatusTypeDef     HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
00436 HAL_StatusTypeDef     HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
00437 HAL_StatusTypeDef     HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
00438 /**
00439   * @}
00440   */
00441
00442 /** @addtogroup DCMI_Exported_Functions_Group4
00443  * @{
00444  */
00445 /* Peripheral State functions *************************************************/
00446 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
00447 uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /* Private types -------------------------------------------------------------*/
00457 /* Private variables ---------------------------------------------------------*/
00458 /* Private constants ---------------------------------------------------------*/
00459 /* Private macro -------------------------------------------------------------*/
00460 /** @defgroup DCMI_Private_Macros DCMI Private Macros
00461   * @{
00462   */
00463 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
00464                                    ((MODE) == DCMI_MODE_SNAPSHOT))
00465
00466 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
00467                               ((MODE) == DCMI_SYNCHRO_EMBEDDED))
00468
00469 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
00470                                       ((POLARITY) == DCMI_PCKPOLARITY_RISING))
00471
00472 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
00473                                      ((POLARITY) == DCMI_VSPOLARITY_HIGH))
00474
00475 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
00476                                      ((POLARITY) == DCMI_HSPOLARITY_HIGH))
00477
00478 #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
00479                                      ((JPEG_MODE) == DCMI_JPEG_ENABLE))
00480
00481 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
00482                                     ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
00483                                     ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
00484
00485 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
00486                                     ((DATA) == DCMI_EXTEND_DATA_10B) || \
00487                                     ((DATA) == DCMI_EXTEND_DATA_12B) || \
00488                                     ((DATA) == DCMI_EXTEND_DATA_14B))
00489
00490 #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
00491
00492 #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
00493
00494 /**
00495   * @}
00496   */
00497
00498 /* Private functions ---------------------------------------------------------*/
00499 /** @addtogroup DCMI_Private_Functions DCMI Private Functions
00500   * @{
00501   */
00502
00503 /**
00504   * @}
00505   */
00506
00507 #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00508           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
00509           STM32F479xx */
00510
00511 /**
00512   * @}
00513   */
00514
00515 /**
00516   * @}
00517   */
00518
00519 #ifdef __cplusplus
00520 }
00521 #endif
00522
00523 #endif /* __STM32F4xx_HAL_DCMI_H */
00524
00525 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi_ex.c Source File

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stm32f4xx_hal_dcmi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dcmi_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DCMI Extension HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of DCMI extension peripheral:
00010   *           + Extension features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### DCMI peripheral extension features  #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the DCMI interface for STM32F446xx
00018        devices contains the following additional features :
00019
00020        (+) Support of Black and White cameras
00021
00022                      ##### How to use this driver #####
00023   ==============================================================================
00024   [..] This driver provides functions to manage the Black and White feature
00025
00026   @endverbatim
00027   ******************************************************************************
00028   * @attention
00029   *
00030   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00031   *
00032   * Redistribution and use in source and binary forms, with or without modification,
00033   * are permitted provided that the following conditions are met:
00034   *   1. Redistributions of source code must retain the above copyright notice,
00035   *      this list of conditions and the following disclaimer.
00036   *   2. Redistributions in binary form must reproduce the above copyright notice,
00037   *      this list of conditions and the following disclaimer in the documentation
00038   *      and/or other materials provided with the distribution.
00039   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00040   *      may be used to endorse or promote products derived from this software
00041   *      without specific prior written permission.
00042   *
00043   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00044   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00045   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00046   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00047   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00048   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00049   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00050   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00051   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00052   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00053   *
00054   ******************************************************************************
00055   */
00056
00057 /* Includes ------------------------------------------------------------------*/
00058 #include "stm32f4xx_hal.h"
00059
00060 /** @addtogroup STM32F4xx_HAL_Driver
00061   * @{
00062   */
00063 /** @defgroup DCMIEx DCMIEx
00064   * @brief DCMI Extended HAL module driver
00065   * @{
00066   */
00067
00068 #ifdef HAL_DCMI_MODULE_ENABLED
00069
00070 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) ||\
00071     defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00072 /* Private typedef -----------------------------------------------------------*/
00073 /* Private define ------------------------------------------------------------*/
00074 /* Private macro -------------------------------------------------------------*/
00075 /* Private variables ---------------------------------------------------------*/
00076 /* Private function prototypes -----------------------------------------------*/
00077 /* Exported functions --------------------------------------------------------*/
00078
00079 /** @defgroup DCMIEx_Exported_Functions DCMI Extended Exported Functions
00080   * @{
00081   */
00082
00083 /** @defgroup DCMIEx_Exported_Functions_Group1 Initialization and Configuration functions
00084  *  @brief   Initialization and Configuration functions
00085  *
00086 @verbatim
00087  ===============================================================================
00088                 ##### Initialization and Configuration functions #####
00089  ===============================================================================
00090     [..]  This section provides functions allowing to:
00091       (+) Initialize and configure the DCMI
00092       (+) De-initialize the DCMI
00093
00094 @endverbatim
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  Initializes the DCMI according to the specified
00100   *         parameters in the DCMI_InitTypeDef and create the associated handle.
00101   * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
00102   *                the configuration information for DCMI.
00103   * @retval HAL status
00104   */
00105 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
00106 {
00107   /* Check the DCMI peripheral state */
00108   if(hdcmi == NULL)
00109   {
00110      return HAL_ERROR;
00111   }
00112
00113   /* Check function parameters */
00114   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
00115   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
00116   assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
00117   assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
00118   assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
00119   assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
00120   assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
00121   assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
00122 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00123   assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
00124   assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
00125   assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
00126   assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
00127 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00128   if(hdcmi->State == HAL_DCMI_STATE_RESET)
00129   {
00130     /* Init the low level hardware */
00131     HAL_DCMI_MspInit(hdcmi);
00132   }
00133
00134   /* Change the DCMI state */
00135   hdcmi->State = HAL_DCMI_STATE_BUSY;
00136                           /* Configures the HS, VS, DE and PC polarity */
00137   hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |\
00138                            DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |\
00139                            DCMI_CR_ESS
00140 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00141                            | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
00142                            DCMI_CR_LSM | DCMI_CR_OELS
00143 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00144                            );
00145   hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
00146                                      hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  |\
00147                                      hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
00148                                      hdcmi->Init.JPEGMode
00149 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00150                                      | hdcmi->Init.ByteSelectMode |\
00151                                      hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
00152                                      hdcmi->Init.LineSelectStart
00153 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00154                                      );
00155   if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
00156   {
00157     DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
00158                   ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8U)|
00159                   ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16U) |
00160                   ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24U));
00161
00162   }
00163
00164   /* Enable DCMI by setting DCMIEN bit */
00165   __HAL_DCMI_ENABLE(hdcmi);
00166
00167   /* Update error code */
00168   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
00169
00170   /* Initialize the DCMI state*/
00171   hdcmi->State  = HAL_DCMI_STATE_READY;
00172
00173   return HAL_OK;
00174 }
00175
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188 #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx ||\
00189           STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00190 #endif /* HAL_DCMI_MODULE_ENABLED */
00191 /**
00192   * @}
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dcmi_ex.h Source File

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stm32f4xx_hal_dcmi_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dcmi_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DCMI Extension HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DCMI_EX_H
00040 #define __STM32F4xx_HAL_DCMI_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
00047     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00048     defined(STM32F479xx)
00049
00050 /* Includes ------------------------------------------------------------------*/
00051 #include "stm32f4xx_hal_def.h"
00052
00053
00054 /** @addtogroup STM32F4xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @addtogroup DCMIEx
00059   * @brief DCMI HAL module driver
00060   * @{
00061   */
00062
00063 /* Exported types ------------------------------------------------------------*/
00064 /** @defgroup DCMIEx_Exported_Types DCMI Extended Exported Types
00065   * @{
00066   */
00067 /**
00068   * @brief   DCMIEx Embedded Synchronisation CODE Init structure definition
00069   */
00070 typedef struct
00071 {
00072   uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
00073   uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
00074   uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
00075   uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
00076 }DCMI_CodesInitTypeDef;
00077
00078 /**
00079   * @brief   DCMI Init structure definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
00084                                              This parameter can be a value of @ref DCMI_Synchronization_Mode */
00085
00086   uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
00087                                              This parameter can be a value of @ref DCMI_PIXCK_Polarity       */
00088
00089   uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
00090                                              This parameter can be a value of @ref DCMI_VSYNC_Polarity       */
00091
00092   uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
00093                                              This parameter can be a value of @ref DCMI_HSYNC_Polarity       */
00094
00095   uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
00096                                              This parameter can be a value of @ref DCMI_Capture_Rate         */
00097
00098   uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
00099                                              This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
00100
00101   DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the frame start delimiter.                */
00102
00103   uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
00104                                              This parameter can be a value of @ref DCMI_MODE_JPEG            */
00105 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00106   uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface
00107                                             This parameter can be a value of @ref DCMIEx_Byte_Select_Mode      */
00108
00109   uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd
00110                                             This parameter can be a value of @ref DCMIEx_Byte_Select_Start     */
00111
00112   uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface
00113                                             This parameter can be a value of @ref DCMIEx_Line_Select_Mode      */
00114
00115   uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd
00116                                             This parameter can be a value of @ref DCMIEx_Line_Select_Start     */
00117
00118 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00119 }DCMI_InitTypeDef;
00120
00121 /**
00122   * @}
00123   */
00124
00125 /* Exported constants --------------------------------------------------------*/
00126 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00127 /** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants
00128   * @{
00129   */
00130
00131 /** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode
00132   * @{
00133   */
00134 #define DCMI_BSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received data */
00135 #define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
00136 #define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
00137 #define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start
00144   * @{
00145   */
00146 #define DCMI_OEBS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
00147 #define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
00148
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode
00154   * @{
00155   */
00156 #define DCMI_LSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received lines */
00157 #define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start
00164   * @{
00165   */
00166 #define DCMI_OELS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
00167 #define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /* Exported macro ------------------------------------------------------------*/
00178 /* Exported functions --------------------------------------------------------*/
00179 /* Private types -------------------------------------------------------------*/
00180 /* Private variables ---------------------------------------------------------*/
00181 /* Private constants ---------------------------------------------------------*/
00182 /* Private macro -------------------------------------------------------------*/
00183
00184 /** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros
00185   * @{
00186   */
00187 #define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
00188                                        ((MODE) == DCMI_BSM_OTHER) || \
00189                                        ((MODE) == DCMI_BSM_ALTERNATE_4) || \
00190                                        ((MODE) == DCMI_BSM_ALTERNATE_2))
00191
00192 #define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
00193                                             ((POLARITY) == DCMI_OEBS_EVEN))
00194
00195 #define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
00196                                        ((MODE) == DCMI_LSM_ALTERNATE_2))
00197
00198 #define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
00199                                             ((POLARITY) == DCMI_OELS_EVEN))
00200 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00201 /**
00202   * @}
00203   */
00204
00205 /* Private functions ---------------------------------------------------------*/
00206 #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00207           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
00208           STM32F479xx */
00209 /**
00210   * @}
00211   */
00212
00213 /**
00214   * @}
00215   */
00216
00217 #ifdef __cplusplus
00218 }
00219 #endif
00220
00221 #endif /* __STM32F4xx_HAL_DCMI_H */
00222
00223 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma2d.c Source File

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stm32f4xx_hal_dma2d.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dma2d.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DMA2D HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the DMA2D peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#) Program the required configuration through following parameters:
00021           the Transfer Mode, the output color mode and the output offset using
00022           HAL_DMA2D_Init() function.
00023
00024       (#) Program the required configuration through following parameters:
00025           the input color mode, the input color, input alpha value, alpha mode
00026           and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
00027           or/and background layer.
00028
00029      *** Polling mode IO operation ***
00030      =================================
00031     [..]
00032        (+) Configure the pdata, Destination and data length and Enable
00033            the transfer using HAL_DMA2D_Start()
00034        (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
00035            user can specify the value of timeout according to his end application.
00036
00037      *** Interrupt mode IO operation ***
00038      ===================================
00039      [..]
00040        (#) Configure the pdata, Destination and data length and Enable
00041            the transfer using HAL_DMA2D_Start_IT()
00042        (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
00043        (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
00044            add his own function by customization of function pointer XferCpltCallback and
00045            XferErrorCallback (i.e a member of DMA2D handle structure).
00046
00047          -@-   In Register-to-Memory transfer mode, the pdata parameter is the register
00048                color, in Memory-to-memory or memory-to-memory with pixel format
00049                conversion the pdata is the source address.
00050
00051          -@-   Configure the foreground source address, the background source address,
00052                the Destination and data length and Enable the transfer using
00053                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
00054                in interrupt mode.
00055
00056          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
00057                are used if the memory to memory with blending transfer mode is selected.
00058
00059       (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
00060           HAL_DMA2D_EnableCLUT() functions.
00061
00062       (#) Optionally, configure and enable LineInterrupt using the following function:
00063           HAL_DMA2D_ProgramLineEvent().
00064
00065       (#) The transfer can be suspended, continued and aborted using the following
00066           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
00067
00068       (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()
00069
00070      *** DMA2D HAL driver macros list ***
00071      =============================================
00072      [..]
00073        Below the list of most used macros in DMA2D HAL driver :
00074
00075       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
00076       (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
00077       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
00078       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
00079       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
00080       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
00081       (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
00082
00083      [..]
00084       (@) You can refer to the DMA2D HAL driver header file for more useful macros
00085
00086   @endverbatim
00087   ******************************************************************************
00088   * @attention
00089   *
00090   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00091   *
00092   * Redistribution and use in source and binary forms, with or without modification,
00093   * are permitted provided that the following conditions are met:
00094   *   1. Redistributions of source code must retain the above copyright notice,
00095   *      this list of conditions and the following disclaimer.
00096   *   2. Redistributions in binary form must reproduce the above copyright notice,
00097   *      this list of conditions and the following disclaimer in the documentation
00098   *      and/or other materials provided with the distribution.
00099   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00100   *      may be used to endorse or promote products derived from this software
00101   *      without specific prior written permission.
00102   *
00103   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00104   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00105   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00106   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00107   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00108   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00109   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00110   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00111   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00112   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00113   *
00114   ******************************************************************************
00115   */
00116
00117 /* Includes ------------------------------------------------------------------*/
00118 #include "stm32f4xx_hal.h"
00119
00120 /** @addtogroup STM32F4xx_HAL_Driver
00121   * @{
00122   */
00123 /** @addtogroup DMA2D
00124   * @brief DMA2D HAL module driver
00125   * @{
00126   */
00127
00128 #ifdef HAL_DMA2D_MODULE_ENABLED
00129
00130 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00131
00132 /* Private types -------------------------------------------------------------*/
00133 /* Private define ------------------------------------------------------------*/
00134 /** @addtogroup DMA2D_Private_Defines
00135   * @{
00136   */
00137 #define HAL_TIMEOUT_DMA2D_ABORT      ((uint32_t)1000U)  /* 1s  */
00138 #define HAL_TIMEOUT_DMA2D_SUSPEND    ((uint32_t)1000U)  /* 1s  */
00139 /**
00140   * @}
00141   */
00142
00143 /* Private variables ---------------------------------------------------------*/
00144 /* Private constants ---------------------------------------------------------*/
00145 /* Private macro -------------------------------------------------------------*/
00146 /* Private function prototypes -----------------------------------------------*/
00147 /** @addtogroup DMA2D_Private_Functions_Prototypes
00148   * @{
00149   */
00150 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00151 /**
00152   * @}
00153   */
00154
00155 /* Private functions ---------------------------------------------------------*/
00156 /* Exported functions --------------------------------------------------------*/
00157 /** @addtogroup DMA2D_Exported_Functions
00158   * @{
00159   */
00160
00161 /** @defgroup DMA2D_Group1 Initialization and Configuration functions
00162  *  @brief   Initialization and Configuration functions
00163  *
00164 @verbatim
00165  ===============================================================================
00166                 ##### Initialization and Configuration functions #####
00167  ===============================================================================
00168     [..]  This section provides functions allowing to:
00169       (+) Initialize and configure the DMA2D
00170       (+) De-initialize the DMA2D
00171
00172 @endverbatim
00173   * @{
00174   */
00175
00176 /**
00177   * @brief  Initializes the DMA2D according to the specified
00178   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
00179   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00180   *                 the configuration information for the DMA2D.
00181   * @retval HAL status
00182   */
00183 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
00184 {
00185   uint32_t tmp = 0U;
00186
00187   /* Check the DMA2D peripheral state */
00188   if(hdma2d == NULL)
00189   {
00190      return HAL_ERROR;
00191   }
00192
00193   /* Check the parameters */
00194   assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
00195   assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
00196   assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
00197   assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
00198
00199   if(hdma2d->State == HAL_DMA2D_STATE_RESET)
00200   {
00201     /* Allocate lock resource and initialize it */
00202     hdma2d->Lock = HAL_UNLOCKED;
00203     /* Init the low level hardware */
00204     HAL_DMA2D_MspInit(hdma2d);
00205   }
00206
00207   /* Change DMA2D peripheral state */
00208   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00209
00210 /* DMA2D CR register configuration -------------------------------------------*/
00211   /* Get the CR register value */
00212   tmp = hdma2d->Instance->CR;
00213
00214   /* Clear Mode bits */
00215   tmp &= (uint32_t)~DMA2D_CR_MODE;
00216
00217   /* Prepare the value to be wrote to the CR register */
00218   tmp |= hdma2d->Init.Mode;
00219
00220   /* Write to DMA2D CR register */
00221   hdma2d->Instance->CR = tmp;
00222
00223 /* DMA2D OPFCCR register configuration ---------------------------------------*/
00224   /* Get the OPFCCR register value */
00225   tmp = hdma2d->Instance->OPFCCR;
00226
00227   /* Clear Color Mode bits */
00228   tmp &= (uint32_t)~DMA2D_OPFCCR_CM;
00229
00230   /* Prepare the value to be wrote to the OPFCCR register */
00231   tmp |= hdma2d->Init.ColorMode;
00232
00233   /* Write to DMA2D OPFCCR register */
00234   hdma2d->Instance->OPFCCR = tmp;
00235
00236 /* DMA2D OOR register configuration ------------------------------------------*/
00237   /* Get the OOR register value */
00238   tmp = hdma2d->Instance->OOR;
00239
00240   /* Clear Offset bits */
00241   tmp &= (uint32_t)~DMA2D_OOR_LO;
00242
00243   /* Prepare the value to be wrote to the OOR register */
00244   tmp |= hdma2d->Init.OutputOffset;
00245
00246   /* Write to DMA2D OOR register */
00247   hdma2d->Instance->OOR = tmp;
00248
00249   /* Update error code */
00250   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00251
00252   /* Initialize the DMA2D state*/
00253   hdma2d->State  = HAL_DMA2D_STATE_READY;
00254
00255   return HAL_OK;
00256 }
00257
00258 /**
00259   * @brief  Deinitializes the DMA2D peripheral registers to their default reset
00260   *         values.
00261   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00262   *                 the configuration information for the DMA2D.
00263   * @retval None
00264   */
00265
00266 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
00267 {
00268   /* Check the DMA2D peripheral state */
00269   if(hdma2d == NULL)
00270   {
00271      return HAL_ERROR;
00272   }
00273
00274   /* DeInit the low level hardware */
00275   HAL_DMA2D_MspDeInit(hdma2d);
00276
00277   /* Update error code */
00278   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00279
00280   /* Initialize the DMA2D state*/
00281   hdma2d->State  = HAL_DMA2D_STATE_RESET;
00282
00283   /* Release Lock */
00284   __HAL_UNLOCK(hdma2d);
00285
00286   return HAL_OK;
00287 }
00288
00289 /**
00290   * @brief  Initializes the DMA2D MSP.
00291   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00292   *                 the configuration information for the DMA2D.
00293   * @retval None
00294   */
00295 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
00296 {
00297   /* Prevent unused argument(s) compilation warning */
00298   UNUSED(hdma2d);
00299   /* NOTE : This function Should not be modified, when the callback is needed,
00300             the HAL_DMA2D_MspInit could be implemented in the user file
00301    */
00302 }
00303
00304 /**
00305   * @brief  DeInitializes the DMA2D MSP.
00306   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00307   *                 the configuration information for the DMA2D.
00308   * @retval None
00309   */
00310 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
00311 {
00312   /* Prevent unused argument(s) compilation warning */
00313   UNUSED(hdma2d);
00314   /* NOTE : This function Should not be modified, when the callback is needed,
00315             the HAL_DMA2D_MspDeInit could be implemented in the user file
00316    */
00317 }
00318
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup DMA2D_Group2 IO operation functions
00324  *  @brief   IO operation functions
00325  *
00326 @verbatim
00327  ===============================================================================
00328                       #####  IO operation functions  #####
00329  ===============================================================================
00330     [..]  This section provides functions allowing to:
00331       (+) Configure the pdata, destination address and data size and
00332           Start DMA2D transfer.
00333       (+) Configure the source for foreground and background, destination address
00334           and data size and Start MultiBuffer DMA2D transfer.
00335       (+) Configure the pdata, destination address and data size and
00336           Start DMA2D transfer with interrupt.
00337       (+) Configure the source for foreground and background, destination address
00338           and data size and Start MultiBuffer DMA2D transfer with interrupt.
00339       (+) Abort DMA2D transfer.
00340       (+) Suspend DMA2D transfer.
00341       (+) Continue DMA2D transfer.
00342       (+) Configure CLUT Loading with interrupt enabled
00343       (+) Poll for transfer complete.
00344       (+) handle DMA2D interrupt request.
00345       (+) Transfer watermark callback.
00346       (+) CLUT Transfer Complete callback.
00347
00348 @endverbatim
00349   * @{
00350   */
00351
00352 /**
00353   * @brief  Start the DMA2D Transfer.
00354   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
00355   *                     the configuration information for the DMA2D.
00356   * @param  pdata:      Configure the source memory Buffer address if
00357   *                     the memory to memory or memory to memory with pixel format
00358   *                     conversion DMA2D mode is selected, and configure
00359   *                     the color value if register to memory DMA2D mode is selected.
00360   * @param  DstAddress: The destination memory Buffer address.
00361   * @param  Width:      The width of data to be transferred from source to destination.
00362   * @param  Height:      The height of data to be transferred from source to destination.
00363   * @retval HAL status
00364   */
00365 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00366 {
00367   /* Check the parameters */
00368   assert_param(IS_DMA2D_LINE(Height));
00369   assert_param(IS_DMA2D_PIXEL(Width));
00370
00371   /* Process locked */
00372   __HAL_LOCK(hdma2d);
00373
00374   /* Change DMA2D peripheral state */
00375   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00376
00377   /* Configure the source, destination address and the data size */
00378   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00379
00380   /* Enable the Peripheral */
00381   __HAL_DMA2D_ENABLE(hdma2d);
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Start the DMA2D Transfer with interrupt enabled.
00388   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
00389   *                     the configuration information for the DMA2D.
00390   * @param  pdata:      Configure the source memory Buffer address if
00391   *                     the memory to memory or memory to memory with pixel format
00392   *                     conversion DMA2D mode is selected, and configure
00393   *                     the color value if register to memory DMA2D mode is selected.
00394   * @param  DstAddress: The destination memory Buffer address.
00395   * @param  Width:      The width of data to be transferred from source to destination.
00396   * @param  Height:     The height of data to be transferred from source to destination.
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00400 {
00401   /* Check the parameters */
00402   assert_param(IS_DMA2D_LINE(Height));
00403   assert_param(IS_DMA2D_PIXEL(Width));
00404
00405   /* Process locked */
00406   __HAL_LOCK(hdma2d);
00407
00408   /* Change DMA2D peripheral state */
00409   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00410
00411   /* Configure the source, destination address and the data size */
00412   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00413
00414  /* Enable the transfer complete,transfer Error and configuration error interrupts */
00415   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
00416
00417   /* Enable the Peripheral */
00418   __HAL_DMA2D_ENABLE(hdma2d);
00419
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief  Start the multi-source DMA2D Transfer.
00425   * @param  hdma2d:      pointer to a DMA2D_HandleTypeDef structure that contains
00426   *                      the configuration information for the DMA2D.
00427   * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
00428   * @param  SrcAddress2: The source memory Buffer address of the background layer.
00429   * @param  DstAddress:  The destination memory Buffer address
00430   * @param  Width:       The width of data to be transferred from source to destination.
00431   * @param  Height:      The height of data to be transferred from source to destination.
00432   * @retval HAL status
00433   */
00434 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00435 {
00436   /* Check the parameters */
00437   assert_param(IS_DMA2D_LINE(Height));
00438   assert_param(IS_DMA2D_PIXEL(Width));
00439
00440   /* Process locked */
00441   __HAL_LOCK(hdma2d);
00442
00443   /* Change DMA2D peripheral state */
00444   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00445
00446   /* Configure DMA2D Stream source2 address */
00447   hdma2d->Instance->BGMAR = SrcAddress2;
00448
00449   /* Configure the source, destination address and the data size */
00450   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00451
00452   /* Enable the Peripheral */
00453   __HAL_DMA2D_ENABLE(hdma2d);
00454
00455   return HAL_OK;
00456 }
00457
00458 /**
00459   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
00460   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
00461   *                     the configuration information for the DMA2D.
00462   * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
00463   * @param  SrcAddress2: The source memory Buffer address of the background layer.
00464   * @param  DstAddress:  The destination memory Buffer address.
00465   * @param  Width:       The width of data to be transferred from source to destination.
00466   * @param  Height:      The height of data to be transferred from source to destination.
00467   * @retval HAL status
00468   */
00469 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00470 {
00471   /* Check the parameters */
00472   assert_param(IS_DMA2D_LINE(Height));
00473   assert_param(IS_DMA2D_PIXEL(Width));
00474
00475   /* Process locked */
00476   __HAL_LOCK(hdma2d);
00477
00478   /* Change DMA2D peripheral state */
00479   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00480
00481   /* Configure DMA2D Stream source2 address */
00482   hdma2d->Instance->BGMAR = SrcAddress2;
00483
00484   /* Configure the source, destination address and the data size */
00485   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00486
00487   /* Enable the transfer complete,transfer Error and configuration error interrupts */
00488   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
00489
00490   /* Enable the Peripheral */
00491   __HAL_DMA2D_ENABLE(hdma2d);
00492
00493   return HAL_OK;
00494 }
00495
00496 /**
00497   * @brief  Abort the DMA2D Transfer.
00498   * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
00499   *                  the configuration information for the DMA2D.
00500   * @retval HAL status
00501   */
00502 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
00503 {
00504   uint32_t tickstart = 0U;
00505   uint32_t regValue;
00506
00507   /* Abort the current DMA2D transfer */
00508   /* Calculate the new CR register value : Reset START bit and Set Abort bit*/
00509   regValue = (hdma2d->Instance->CR & (~DMA2D_CR_START)) | DMA2D_CR_ABORT;
00510   hdma2d->Instance->CR = regValue;
00511
00512   /* Get tick */
00513   tickstart = HAL_GetTick();
00514
00515   /* Check if the DMA2D is effectively disabled */
00516   while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
00517   {
00518     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT)
00519     {
00520       /* Update error code */
00521       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00522
00523       /* Change the DMA2D state */
00524       hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00525
00526       /* Process Unlocked */
00527       __HAL_UNLOCK(hdma2d);
00528
00529       return HAL_TIMEOUT;
00530     }
00531   }
00532   /* Process Unlocked */
00533   __HAL_UNLOCK(hdma2d);
00534
00535   /* Change the DMA2D state*/
00536   hdma2d->State = HAL_DMA2D_STATE_READY;
00537
00538   return HAL_OK;
00539 }
00540
00541 /**
00542   * @brief  Suspend the DMA2D Transfer.
00543   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00544   *                 the configuration information for the DMA2D.
00545   * @retval HAL status
00546   */
00547 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
00548 {
00549   uint32_t tickstart = 0U;
00550
00551   /* Suspend the DMA2D transfer */
00552   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
00553
00554   /* Get tick */
00555   tickstart = HAL_GetTick();
00556
00557   /* Check if the DMA2D is effectively suspended */
00558   while(((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) && \
00559         ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
00560   {
00561     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND)
00562     {
00563       /* Update error code */
00564       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00565
00566       /* Change the DMA2D state */
00567       hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00568
00569       return HAL_TIMEOUT;
00570     }
00571   }
00572   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
00573   if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
00574   {
00575     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00576   }
00577
00578   return HAL_OK;
00579 }
00580
00581 /**
00582   * @brief  Resume the DMA2D Transfer.
00583   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00584   *                 the configuration information for the DMA2D.
00585   * @retval HAL status
00586   */
00587 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
00588 {
00589   /* Check the suspend bit and START bit */
00590   if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
00591   {
00592     /* ongoing transfer is suspended :  Change the DMA2D state before resuming*/
00593     hdma2d->State = HAL_DMA2D_STATE_BUSY;
00594   }
00595
00596   /* Resume the DMA2D transfer */
00597   CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
00598
00599   return HAL_OK;
00600 }
00601
00602 /**
00603   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
00604   * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
00605   *                   the configuration information for the DMA2D.
00606   * @param  CLUTCfg:  pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00607   *                   the configuration information for the color look up table.
00608   * @param  LayerIdx: DMA2D Layer index.
00609   *                   This parameter can be one of the following values:
00610   *                   0(background) / 1(foreground)
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
00614 {
00615   /* Check the parameters */
00616   assert_param(IS_DMA2D_LAYER(LayerIdx));
00617   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
00618   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
00619
00620   /* Process locked */
00621   __HAL_LOCK(hdma2d);
00622
00623   /* Change DMA2D peripheral state */
00624   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00625
00626   /* Configure the CLUT of the background DMA2D layer */
00627   if(LayerIdx == 0U)
00628   {
00629     /* Write to DMA2D BGCMAR register */
00630     hdma2d->Instance->BGCMAR = (uint32_t)CLUTCfg.pCLUT;
00631
00632    /* Write background CLUT size and CLUT color mode */
00633     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));
00634
00635     /* Enable the C-LUT Transfer Complete,transfer Error and C-LUT Access Error interrupts */
00636     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CAE);
00637
00638     /* Enable the CLUT loading for the background */
00639     hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;
00640   }
00641   /* Configure the CLUT of the foreground DMA2D layer */
00642   else
00643   {
00644     /* Write to DMA2D FGCMAR register */
00645     hdma2d->Instance->FGCMAR = (uint32_t)CLUTCfg.pCLUT;
00646
00647     /* Write foreground CLUT size and CLUT color mode */
00648     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));
00649
00650     /* Enable the C-LUT Transfer Complete,transfer Error and C-LUT Access Error interrupts */
00651     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CAE);
00652
00653      /* Enable the CLUT loading for the foreground */
00654     hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;
00655   }
00656
00657
00658   return HAL_OK;
00659 }
00660
00661 /**
00662   * @brief  Polling for transfer complete or CLUT loading.
00663   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00664   *                 the configuration information for the DMA2D.
00665   * @param  Timeout: Timeout duration
00666   * @retval HAL status
00667   */
00668 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
00669 {
00670   uint32_t tickstart = 0U;
00671
00672   /* Polling for DMA2D transfer */
00673   if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
00674   {
00675    /* Get tick */
00676    tickstart = HAL_GetTick();
00677
00678     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
00679     {
00680       if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE|DMA2D_FLAG_TE) != RESET))
00681       {
00682         if (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
00683         {
00684           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
00685         }
00686
00687         if (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
00688         {
00689           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
00690         }
00691         /* Clear the transfer and configuration error flags */
00692         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
00693
00694         /* Change DMA2D state */
00695         hdma2d->State= HAL_DMA2D_STATE_ERROR;
00696
00697         /* Process unlocked */
00698         __HAL_UNLOCK(hdma2d);
00699
00700         return HAL_ERROR;
00701       }
00702       /* Check for the Timeout */
00703       if(Timeout != HAL_MAX_DELAY)
00704       {
00705         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00706         {
00707           /* Process unlocked */
00708           __HAL_UNLOCK(hdma2d);
00709
00710           /* Update error code */
00711           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00712
00713           /* Change the DMA2D state */
00714           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00715
00716           return HAL_TIMEOUT;
00717         }
00718       }
00719     }
00720   }
00721   /* Polling for foreground CLUT loading */
00722   if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0U)
00723   {
00724     /* Get tick */
00725     tickstart = HAL_GetTick();
00726
00727     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
00728     {
00729       if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
00730       {
00731         hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
00732
00733         /* Clear the CLUT Access Error flag */
00734         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
00735
00736         /* Change DMA2D state */
00737         hdma2d->State= HAL_DMA2D_STATE_ERROR;
00738
00739         return HAL_ERROR;
00740       }
00741       /* Check for the Timeout */
00742       if(Timeout != HAL_MAX_DELAY)
00743       {
00744         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00745         {
00746           /* Update error code */
00747           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00748
00749           /* Change the DMA2D state */
00750           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00751
00752           return HAL_TIMEOUT;
00753         }
00754       }
00755     }
00756   }
00757   /* Polling for background CLUT loading */
00758   if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != 0U)
00759   {
00760     /* Get tick */
00761     tickstart = HAL_GetTick();
00762
00763     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
00764     {
00765       if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
00766       {
00767         hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
00768
00769         /* Clear the CLUT Access Error flag */
00770         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
00771
00772         /* Change DMA2D state */
00773         hdma2d->State= HAL_DMA2D_STATE_ERROR;
00774
00775         return HAL_ERROR;
00776       }
00777       /* Check for the Timeout */
00778       if(Timeout != HAL_MAX_DELAY)
00779       {
00780         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00781         {
00782           /* Update error code */
00783           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00784
00785           /* Change the DMA2D state */
00786           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
00787
00788           return HAL_TIMEOUT;
00789         }
00790       }
00791     }
00792   }
00793
00794   /* Clear the transfer complete and CLUT loading flags */
00795   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
00796
00797   /* Change DMA2D state */
00798   hdma2d->State = HAL_DMA2D_STATE_READY;
00799
00800   /* Process unlocked */
00801   __HAL_UNLOCK(hdma2d);
00802
00803   return HAL_OK;
00804 }
00805 /**
00806   * @brief  Handles DMA2D interrupt request.
00807   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00808   *                 the configuration information for the DMA2D.
00809   * @retval HAL status
00810   */
00811 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
00812 {
00813   /* Transfer Error Interrupt management ***************************************/
00814   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
00815   {
00816     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET)
00817     {
00818       /* Disable the transfer Error interrupt */
00819       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
00820
00821       /* Update error code */
00822       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
00823
00824       /* Clear the transfer error flag */
00825       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
00826
00827       /* Change DMA2D state */
00828       hdma2d->State = HAL_DMA2D_STATE_ERROR;
00829
00830       /* Process Unlocked */
00831       __HAL_UNLOCK(hdma2d);
00832
00833       if(hdma2d->XferErrorCallback != NULL)
00834       {
00835         /* Transfer error Callback */
00836         hdma2d->XferErrorCallback(hdma2d);
00837       }
00838     }
00839   }
00840   /* Configuration Error Interrupt management **********************************/
00841   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
00842   {
00843     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET)
00844     {
00845       /* Disable the Configuration Error interrupt */
00846       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
00847
00848       /* Clear the Configuration error flag */
00849       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
00850
00851       /* Update error code */
00852       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
00853
00854       /* Change DMA2D state */
00855       hdma2d->State = HAL_DMA2D_STATE_ERROR;
00856
00857       /* Process Unlocked */
00858       __HAL_UNLOCK(hdma2d);
00859
00860       if(hdma2d->XferErrorCallback != NULL)
00861       {
00862         /* Transfer error Callback */
00863         hdma2d->XferErrorCallback(hdma2d);
00864       }
00865     }
00866   }
00867   /* CLUT access Error Interrupt management ***********************************/
00868   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET)
00869   {
00870     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CAE) != RESET)
00871     {
00872       /* Disable the CLUT access error interrupt */
00873       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
00874
00875       /* Clear the CLUT access error flag */
00876       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
00877
00878       /* Update error code */
00879       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
00880
00881       /* Change DMA2D state */
00882       hdma2d->State = HAL_DMA2D_STATE_ERROR;
00883
00884       /* Process Unlocked */
00885       __HAL_UNLOCK(hdma2d);
00886
00887       if(hdma2d->XferErrorCallback != NULL)
00888       {
00889         /* Transfer error Callback */
00890         hdma2d->XferErrorCallback(hdma2d);
00891       }
00892     }
00893   }
00894   /* Transfer watermark Interrupt management **********************************/
00895   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TW) != RESET)
00896   {
00897     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TW) != RESET)
00898     {
00899       /* Disable the transfer watermark interrupt */
00900       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
00901
00902       /* Clear the transfer watermark flag */
00903       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
00904
00905       /* Transfer watermark Callback */
00906       HAL_DMA2D_LineEventCallback(hdma2d);
00907     }
00908   }
00909   /* Transfer Complete Interrupt management ************************************/
00910   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET)
00911   {
00912     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET)
00913     {
00914       /* Disable the transfer complete interrupt */
00915       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
00916
00917       /* Clear the transfer complete flag */
00918       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
00919
00920       /* Update error code */
00921       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
00922
00923       /* Change DMA2D state */
00924       hdma2d->State = HAL_DMA2D_STATE_READY;
00925
00926       /* Process Unlocked */
00927       __HAL_UNLOCK(hdma2d);
00928
00929       if(hdma2d->XferCpltCallback != NULL)
00930       {
00931         /* Transfer complete Callback */
00932         hdma2d->XferCpltCallback(hdma2d);
00933       }
00934     }
00935   }
00936   /* CLUT Transfer Complete Interrupt management ******************************/
00937   if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) != RESET)
00938   {
00939     if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CTC) != RESET)
00940     {
00941       /* Disable the CLUT transfer complete interrupt */
00942       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
00943
00944       /* Clear the CLUT transfer complete flag */
00945       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
00946
00947       /* Update error code */
00948       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
00949
00950       /* Change DMA2D state */
00951       hdma2d->State = HAL_DMA2D_STATE_READY;
00952
00953       /* Process Unlocked */
00954       __HAL_UNLOCK(hdma2d);
00955
00956       /* CLUT Transfer complete Callback */
00957       HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
00958     }
00959   }
00960
00961 }
00962
00963 /**
00964   * @brief  Transfer watermark callback.
00965   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00966   *                 the configuration information for the DMA2D.
00967   * @retval None
00968   */
00969 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
00970 {
00971   /* Prevent unused argument(s) compilation warning */
00972   UNUSED(hdma2d);
00973
00974   /* NOTE : This function Should not be modified, when the callback is needed,
00975             the HAL_DMA2D_LineEventCallback could be implemented in the user file
00976    */
00977 }
00978
00979 /**
00980   * @brief  CLUT Transfer Complete callback.
00981   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
00982   *                 the configuration information for the DMA2D.
00983   * @retval None
00984   */
00985 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
00986 {
00987   /* Prevent unused argument(s) compilation warning */
00988   UNUSED(hdma2d);
00989
00990   /* NOTE : This function Should not be modified, when the callback is needed,
00991             the HAL_DMA2D_CLUTLoadingCpltCallback could be implemented in the user file
00992    */
00993 }
00994
00995 /**
00996   * @}
00997   */
00998
00999 /** @defgroup DMA2D_Group3 Peripheral Control functions
01000  *  @brief    Peripheral Control functions
01001  *
01002 @verbatim
01003  ===============================================================================
01004                     ##### Peripheral Control functions #####
01005  ===============================================================================
01006     [..]  This section provides functions allowing to:
01007       (+) Configure the DMA2D foreground or/and background parameters.
01008       (+) Configure the DMA2D CLUT transfer.
01009       (+) Enable DMA2D CLUT.
01010       (+) Disable DMA2D CLUT.
01011       (+) Configure the line watermark
01012
01013 @endverbatim
01014   * @{
01015   */
01016 /**
01017   * @brief  Configure the DMA2D Layer according to the specified
01018   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
01019   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01020   *                 the configuration information for the DMA2D.
01021   * @param  LayerIdx: DMA2D Layer index.
01022   *                   This parameter can be one of the following values:
01023   *                   0(background) / 1(foreground)
01024   * @retval HAL status
01025   */
01026 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01027 {
01028   DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
01029
01030   uint32_t tmp = 0U;
01031
01032   /* Check the parameters */
01033   assert_param(IS_DMA2D_LAYER(LayerIdx));
01034   assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
01035
01036   if(hdma2d->Init.Mode != DMA2D_R2M)
01037   {
01038     assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
01039     if(hdma2d->Init.Mode != DMA2D_M2M)
01040     {
01041       assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
01042     }
01043   }
01044
01045   /* Process locked */
01046   __HAL_LOCK(hdma2d);
01047
01048   /* Change DMA2D peripheral state */
01049   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01050
01051   /* Configure the background DMA2D layer */
01052   if(LayerIdx == 0U)
01053   {
01054     /* DMA2D BGPFCR register configuration -----------------------------------*/
01055     /* Get the BGPFCCR register value */
01056     tmp = hdma2d->Instance->BGPFCCR;
01057
01058     /* Clear Input color mode, alpha value and alpha mode bits */
01059     tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA);
01060
01061     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
01062     {
01063       /* Prepare the value to be wrote to the BGPFCCR register */
01064       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | ((pLayerCfg->InputAlpha) & 0xFF000000U));
01065     }
01066     else
01067     {
01068       /* Prepare the value to be wrote to the BGPFCCR register */
01069       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | (pLayerCfg->InputAlpha << 24U));
01070     }
01071
01072     /* Write to DMA2D BGPFCCR register */
01073     hdma2d->Instance->BGPFCCR = tmp;
01074
01075     /* DMA2D BGOR register configuration -------------------------------------*/
01076     /* Get the BGOR register value */
01077     tmp = hdma2d->Instance->BGOR;
01078
01079     /* Clear colors bits */
01080     tmp &= (uint32_t)~DMA2D_BGOR_LO;
01081
01082     /* Prepare the value to be wrote to the BGOR register */
01083     tmp |= pLayerCfg->InputOffset;
01084
01085     /* Write to DMA2D BGOR register */
01086     hdma2d->Instance->BGOR = tmp;
01087
01088     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
01089     {
01090       /* Prepare the value to be wrote to the BGCOLR register */
01091       tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFFU);
01092
01093       /* Write to DMA2D BGCOLR register */
01094       hdma2d->Instance->BGCOLR = tmp;
01095     }
01096   }
01097   /* Configure the foreground DMA2D layer */
01098   else
01099   {
01100     /* DMA2D FGPFCR register configuration -----------------------------------*/
01101     /* Get the FGPFCCR register value */
01102     tmp = hdma2d->Instance->FGPFCCR;
01103
01104     /* Clear Input color mode, alpha value and alpha mode bits */
01105     tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA);
01106
01107     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
01108     {
01109       /* Prepare the value to be wrote to the FGPFCCR register */
01110       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | ((pLayerCfg->InputAlpha) & 0xFF000000U));
01111     }
01112     else
01113     {
01114       /* Prepare the value to be wrote to the FGPFCCR register */
01115       tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16U) | (pLayerCfg->InputAlpha << 24U));
01116     }
01117
01118     /* Write to DMA2D FGPFCCR register */
01119     hdma2d->Instance->FGPFCCR = tmp;
01120
01121     /* DMA2D FGOR register configuration -------------------------------------*/
01122     /* Get the FGOR register value */
01123     tmp = hdma2d->Instance->FGOR;
01124
01125     /* Clear colors bits */
01126     tmp &= (uint32_t)~DMA2D_FGOR_LO;
01127
01128     /* Prepare the value to be wrote to the FGOR register */
01129     tmp |= pLayerCfg->InputOffset;
01130
01131     /* Write to DMA2D FGOR register */
01132     hdma2d->Instance->FGOR = tmp;
01133
01134     if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
01135     {
01136       /* Prepare the value to be wrote to the FGCOLR register */
01137       tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFFU);
01138
01139       /* Write to DMA2D FGCOLR register */
01140       hdma2d->Instance->FGCOLR = tmp;
01141     }
01142   }
01143   /* Initialize the DMA2D state*/
01144   hdma2d->State  = HAL_DMA2D_STATE_READY;
01145
01146   /* Process unlocked */
01147   __HAL_UNLOCK(hdma2d);
01148
01149   return HAL_OK;
01150 }
01151
01152 /**
01153   * @brief  Configure the DMA2D CLUT Transfer.
01154   * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
01155   *                   the configuration information for the DMA2D.
01156   * @param  CLUTCfg:  pointer to a DMA2D_CLUTCfgTypeDef structure that contains
01157   *                   the configuration information for the color look up table.
01158   * @param  LayerIdx: DMA2D Layer index.
01159   *                   This parameter can be one of the following values:
01160   *                   0(background) / 1(foreground)
01161   * @retval HAL status
01162   */
01163 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01164 {
01165   /* Check the parameters */
01166   assert_param(IS_DMA2D_LAYER(LayerIdx));
01167   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01168   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01169
01170   /* Process locked */
01171   __HAL_LOCK(hdma2d);
01172
01173   /* Change DMA2D peripheral state */
01174   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01175
01176   /* Configure the CLUT of the background DMA2D layer */
01177   if(LayerIdx == 0U)
01178   {
01179     /* Write to DMA2D BGCMAR register */
01180     hdma2d->Instance->BGCMAR = (uint32_t)CLUTCfg.pCLUT;
01181
01182    /* Write background CLUT size and CLUT color mode */
01183     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));
01184   }
01185   /* Configure the CLUT of the foreground DMA2D layer */
01186   else
01187   {
01188     /* Write to DMA2D FGCMAR register */
01189     hdma2d->Instance->FGCMAR = (uint32_t)CLUTCfg.pCLUT;
01190
01191     /* Write foreground CLUT size and CLUT color mode */
01192     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), ((CLUTCfg.Size << 8U) | (CLUTCfg.CLUTColorMode << 4U)));
01193   }
01194
01195   /* Set the DMA2D state to Ready*/
01196   hdma2d->State  = HAL_DMA2D_STATE_READY;
01197
01198   /* Process unlocked */
01199   __HAL_UNLOCK(hdma2d);
01200
01201   return HAL_OK;
01202 }
01203
01204 /**
01205   * @brief  Enable the DMA2D CLUT Transfer.
01206   * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
01207   *                   the configuration information for the DMA2D.
01208   * @param  LayerIdx: DMA2D Layer index.
01209   *                   This parameter can be one of the following values:
01210   *                   0(background) / 1(foreground)
01211   * @retval HAL status
01212   */
01213 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01214 {
01215   /* Check the parameters */
01216   assert_param(IS_DMA2D_LAYER(LayerIdx));
01217
01218   /* Process locked */
01219   __HAL_LOCK(hdma2d);
01220
01221   /* Change DMA2D peripheral state */
01222   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01223
01224   if(LayerIdx == 0U)
01225   {
01226     /* Enable the CLUT loading for the background */
01227     hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;
01228   }
01229   else
01230   {
01231     /* Enable the CLUT loading for the foreground */
01232     hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;
01233   }
01234
01235   return HAL_OK;
01236 }
01237
01238 /**
01239   * @brief  Disable the DMA2D CLUT Transfer.
01240   * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
01241   *                   the configuration information for the DMA2D.
01242   * @param  LayerIdx: DMA2D Layer index.
01243   *                   This parameter can be one of the following values:
01244   *                   0(background) / 1(foreground)
01245   * @retval HAL status
01246   */
01247 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01248 {
01249   /* Check the parameters */
01250   assert_param(IS_DMA2D_LAYER(LayerIdx));
01251
01252   if(LayerIdx == 0U)
01253   {
01254     /* Disable the CLUT loading for the background */
01255     hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START;
01256   }
01257   else
01258   {
01259     /* Disable the CLUT loading for the foreground */
01260     hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START;
01261   }
01262
01263   return HAL_OK;
01264 }
01265
01266 /**
01267   * @brief  Define the configuration of the line watermark .
01268   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01269   *                 the configuration information for the DMA2D.
01270   * @param  Line:   Line Watermark configuration.
01271   * @retval HAL status
01272   */
01273
01274 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
01275 {
01276   /* Check the parameters */
01277   assert_param(IS_DMA2D_LineWatermark(Line));
01278
01279   /* Process locked */
01280   __HAL_LOCK(hdma2d);
01281
01282   /* Change DMA2D peripheral state */
01283   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01284
01285   /* Sets the Line watermark configuration */
01286   DMA2D->LWR = (uint32_t)Line;
01287
01288   /* Initialize the DMA2D state*/
01289   hdma2d->State = HAL_DMA2D_STATE_READY;
01290
01291   /* Process unlocked */
01292   __HAL_UNLOCK(hdma2d);
01293
01294   return HAL_OK;
01295 }
01296
01297 /**
01298   * @}
01299   */
01300
01301 /** @defgroup DMA2D_Group4 Peripheral State functions
01302  *  @brief    Peripheral State functions
01303  *
01304 @verbatim
01305  ===============================================================================
01306                   ##### Peripheral State and Errors functions #####
01307  ===============================================================================
01308     [..]
01309     This subsection provides functions allowing to :
01310       (+) Check the DMA2D state
01311       (+) Get error code
01312
01313 @endverbatim
01314   * @{
01315   */
01316
01317 /**
01318   * @brief  Return the DMA2D state
01319   * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
01320   *                 the configuration information for the DMA2D.
01321   * @retval HAL state
01322   */
01323 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
01324 {
01325   return hdma2d->State;
01326 }
01327
01328 /**
01329   * @brief  Return the DMA2D error code
01330   * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
01331   *               the configuration information for DMA2D.
01332   * @retval DMA2D Error Code
01333   */
01334 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
01335 {
01336   return hdma2d->ErrorCode;
01337 }
01338
01339 /**
01340   * @}
01341   */
01342
01343
01344 /**
01345   * @brief  Set the DMA2D Transfer parameter.
01346   * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
01347   *                     the configuration information for the specified DMA2D.
01348   * @param  pdata:      The source memory Buffer address
01349   * @param  DstAddress: The destination memory Buffer address
01350   * @param  Width:      The width of data to be transferred from source to destination.
01351   * @param  Height:     The height of data to be transferred from source to destination.
01352   * @retval HAL status
01353   */
01354 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
01355 {
01356   uint32_t tmp = 0U;
01357   uint32_t tmp1 = 0U;
01358   uint32_t tmp2 = 0U;
01359   uint32_t tmp3 = 0U;
01360   uint32_t tmp4 = 0U;
01361
01362   tmp = Width << 16U;
01363
01364   /* Configure DMA2D data size */
01365   hdma2d->Instance->NLR = (Height | tmp);
01366
01367   /* Configure DMA2D destination address */
01368   hdma2d->Instance->OMAR = DstAddress;
01369
01370   /* Register to memory DMA2D mode selected */
01371   if (hdma2d->Init.Mode == DMA2D_R2M)
01372   {
01373     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
01374     tmp2 = pdata & DMA2D_OCOLR_RED_1;
01375     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
01376     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
01377
01378     /* Prepare the value to be wrote to the OCOLR register according to the color mode */
01379     if (hdma2d->Init.ColorMode == DMA2D_ARGB8888)
01380     {
01381       tmp = (tmp3 | tmp2 | tmp1| tmp4);
01382     }
01383     else if (hdma2d->Init.ColorMode == DMA2D_RGB888)
01384     {
01385       tmp = (tmp3 | tmp2 | tmp4);
01386     }
01387     else if (hdma2d->Init.ColorMode == DMA2D_RGB565)
01388     {
01389       tmp2 = (tmp2 >> 19U);
01390       tmp3 = (tmp3 >> 10U);
01391       tmp4 = (tmp4 >> 3U);
01392       tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
01393     }
01394     else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555)
01395     {
01396       tmp1 = (tmp1 >> 31U);
01397       tmp2 = (tmp2 >> 19U);
01398       tmp3 = (tmp3 >> 11U);
01399       tmp4 = (tmp4 >> 3U);
01400       tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
01401     }
01402     else /* DMA2D_CMode = DMA2D_ARGB4444 */
01403     {
01404       tmp1 = (tmp1 >> 28U);
01405       tmp2 = (tmp2 >> 20U);
01406       tmp3 = (tmp3 >> 12U);
01407       tmp4 = (tmp4 >> 4U);
01408       tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
01409     }
01410     /* Write to DMA2D OCOLR register */
01411     hdma2d->Instance->OCOLR = tmp;
01412   }
01413   else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
01414   {
01415     /* Configure DMA2D source address */
01416     hdma2d->Instance->FGMAR = pdata;
01417   }
01418 }
01419
01420 /**
01421   * @}
01422   */
01423 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
01424 #endif /* HAL_DMA2D_MODULE_ENABLED */
01425 /**
01426   * @}
01427   */
01428
01429 /**
01430   * @}
01431   */
01432
01433 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma2d.h Source File

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stm32f4xx_hal_dma2d.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dma2d.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DMA2D HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DMA2D_H
00040 #define __STM32F4xx_HAL_DMA2D_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00047     defined(STM32F469xx) || defined(STM32F479xx)
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f4xx_hal_def.h"
00050
00051 /** @addtogroup STM32F4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @defgroup DMA2D DMA2D
00056   * @brief DMA2D HAL module driver
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
00062   * @{
00063   */
00064 #define MAX_DMA2D_LAYER  2
00065
00066 /**
00067   * @brief DMA2D color Structure definition
00068   */
00069 typedef struct
00070 {
00071   uint32_t Blue;               /*!< Configures the blue value.
00072                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00073
00074   uint32_t Green;              /*!< Configures the green value.
00075                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00076
00077   uint32_t Red;                /*!< Configures the red value.
00078                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00079 } DMA2D_ColorTypeDef;
00080
00081 /**
00082   * @brief DMA2D CLUT Structure definition
00083   */
00084 typedef struct
00085 {
00086   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
00087
00088   uint32_t CLUTColorMode;           /*!< configures the DMA2D CLUT color mode.
00089                                          This parameter can be one value of @ref DMA2D_CLUT_CM */
00090
00091   uint32_t Size;                    /*!< configures the DMA2D CLUT size.
00092                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
00093 } DMA2D_CLUTCfgTypeDef;
00094
00095 /**
00096   * @brief DMA2D Init structure definition
00097   */
00098 typedef struct
00099 {
00100   uint32_t             Mode;               /*!< configures the DMA2D transfer mode.
00101                                                 This parameter can be one value of @ref DMA2D_Mode */
00102
00103   uint32_t             ColorMode;          /*!< configures the color format of the output image.
00104                                                 This parameter can be one value of @ref DMA2D_Color_Mode */
00105
00106   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
00107                                                 This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0x3FFF. */
00108 } DMA2D_InitTypeDef;
00109
00110 /**
00111   * @brief DMA2D Layer structure definition
00112   */
00113 typedef struct
00114 {
00115   uint32_t             InputOffset;       /*!< configures the DMA2D foreground offset.
00116                                                This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0x3FFF. */
00117
00118   uint32_t             InputColorMode;    /*!< configures the DMA2D foreground color mode .
00119                                                This parameter can be one value of @ref DMA2D_Input_Color_Mode */
00120
00121   uint32_t             AlphaMode;         /*!< configures the DMA2D foreground alpha mode.
00122                                                This parameter can be one value of @ref DMA2D_ALPHA_MODE */
00123
00124   uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
00125                                                This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFFU
00126                                                in case of A8 or A4 color mode (ARGB).
00127                                                Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
00128
00129 } DMA2D_LayerCfgTypeDef;
00130
00131 /**
00132   * @brief  HAL DMA2D State structures definition
00133   */
00134 typedef enum
00135 {
00136   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
00137   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00138   HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing              */
00139   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00140   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
00141   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
00142 }HAL_DMA2D_StateTypeDef;
00143
00144 /**
00145   * @brief  DMA2D handle Structure definition
00146   */
00147 typedef struct __DMA2D_HandleTypeDef
00148 {
00149   DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D Register base address       */
00150
00151   DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters    */
00152
00153   void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback  */
00154
00155   void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback     */
00156
00157   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */
00158
00159   HAL_LockTypeDef             Lock;                                                         /*!< DMA2D Lock                        */
00160
00161   __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state              */
00162
00163   __IO uint32_t               ErrorCode;                                                    /*!< DMA2D Error code                  */
00164 } DMA2D_HandleTypeDef;
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported constants --------------------------------------------------------*/
00170 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
00171   * @{
00172   */
00173
00174 /** @defgroup DMA2D_Error_Code DMA2D Error Code
00175   * @{
00176   */
00177 #define HAL_DMA2D_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error             */
00178 #define HAL_DMA2D_ERROR_TE        ((uint32_t)0x00000001U)    /*!< Transfer error       */
00179 #define HAL_DMA2D_ERROR_CE        ((uint32_t)0x00000002U)    /*!< Configuration error  */
00180 #define HAL_DMA2D_ERROR_CAE       ((uint32_t)0x00000004U)    /*!< CLUT access error    */
00181 #define HAL_DMA2D_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error        */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup DMA2D_Mode DMA2D Mode
00187   * @{
00188   */
00189 #define DMA2D_M2M                            ((uint32_t)0x00000000U)             /*!< DMA2D memory to memory transfer mode */
00190 #define DMA2D_M2M_PFC                        ((uint32_t)0x00010000U)             /*!< DMA2D memory to memory with pixel format conversion transfer mode */
00191 #define DMA2D_M2M_BLEND                      ((uint32_t)0x00020000U)             /*!< DMA2D memory to memory with blending transfer mode */
00192 #define DMA2D_R2M                            ((uint32_t)0x00030000U)             /*!< DMA2D register to memory transfer mode */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup DMA2D_Color_Mode DMA2D Color Mode
00198   * @{
00199   */
00200 #define DMA2D_ARGB8888                       ((uint32_t)0x00000000U)             /*!< ARGB8888 DMA2D color mode */
00201 #define DMA2D_RGB888                         ((uint32_t)0x00000001U)             /*!< RGB888 DMA2D color mode   */
00202 #define DMA2D_RGB565                         ((uint32_t)0x00000002U)             /*!< RGB565 DMA2D color mode   */
00203 #define DMA2D_ARGB1555                       ((uint32_t)0x00000003U)             /*!< ARGB1555 DMA2D color mode */
00204 #define DMA2D_ARGB4444                       ((uint32_t)0x00000004U)             /*!< ARGB4444 DMA2D color mode */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
00210   * @{
00211   */
00212 #define COLOR_VALUE             ((uint32_t)0x000000FFU)                          /*!< color value mask */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup DMA2D_SIZE DMA2D SIZE
00218   * @{
00219   */
00220 #define DMA2D_PIXEL          (DMA2D_NLR_PL >> 16U)                              /*!< DMA2D pixel per line */
00221 #define DMA2D_LINE           DMA2D_NLR_NL                                       /*!< DMA2D number of line */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup DMA2D_Offset DMA2D Offset
00227   * @{
00228   */
00229 #define DMA2D_OFFSET      DMA2D_FGOR_LO            /*!< Line Offset */
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
00235   * @{
00236   */
00237 #define CM_ARGB8888        ((uint32_t)0x00000000U)                               /*!< ARGB8888 color mode */
00238 #define CM_RGB888          ((uint32_t)0x00000001U)                               /*!< RGB888 color mode */
00239 #define CM_RGB565          ((uint32_t)0x00000002U)                               /*!< RGB565 color mode */
00240 #define CM_ARGB1555        ((uint32_t)0x00000003U)                               /*!< ARGB1555 color mode */
00241 #define CM_ARGB4444        ((uint32_t)0x00000004U)                               /*!< ARGB4444 color mode */
00242 #define CM_L8              ((uint32_t)0x00000005U)                               /*!< L8 color mode */
00243 #define CM_AL44            ((uint32_t)0x00000006U)                               /*!< AL44 color mode */
00244 #define CM_AL88            ((uint32_t)0x00000007U)                               /*!< AL88 color mode */
00245 #define CM_L4              ((uint32_t)0x00000008U)                               /*!< L4 color mode */
00246 #define CM_A8              ((uint32_t)0x00000009U)                               /*!< A8 color mode */
00247 #define CM_A4              ((uint32_t)0x0000000AU)                               /*!< A4 color mode */
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
00253   * @{
00254   */
00255 #define DMA2D_NO_MODIF_ALPHA       ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
00256 #define DMA2D_REPLACE_ALPHA        ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */
00257 #define DMA2D_COMBINE_ALPHA        ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value
00258                                                                 with original alpha channel value                              */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
00264   * @{
00265   */
00266 #define DMA2D_CCM_ARGB8888    ((uint32_t)0x00000000U)    /*!< ARGB8888 DMA2D C-LUT color mode */
00267 #define DMA2D_CCM_RGB888      ((uint32_t)0x00000001U)    /*!< RGB888 DMA2D C-LUT color mode   */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup DMA2D_Size_Clut DMA2D Size Clut
00273   * @{
00274   */
00275 #define DMA2D_CLUT_SIZE    (DMA2D_FGPFCCR_CS >> 8U)    /*!< DMA2D C-LUT size */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup DMA2D_DeadTime DMA2D DeadTime
00281   * @{
00282   */
00283 #define LINE_WATERMARK            DMA2D_LWR_LW
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
00289   * @{
00290   */
00291 #define DMA2D_IT_CE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
00292 #define DMA2D_IT_CTC            DMA2D_CR_CTCIE   /*!< C-LUT Transfer Complete Interrupt */
00293 #define DMA2D_IT_CAE            DMA2D_CR_CAEIE   /*!< C-LUT Access Error Interrupt */
00294 #define DMA2D_IT_TW             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
00295 #define DMA2D_IT_TC             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
00296 #define DMA2D_IT_TE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup DMA2D_Flag DMA2D Flag
00302   * @{
00303   */
00304 #define DMA2D_FLAG_CE          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
00305 #define DMA2D_FLAG_CTC         DMA2D_ISR_CTCIF    /*!< C-LUT Transfer Complete Interrupt Flag */
00306 #define DMA2D_FLAG_CAE         DMA2D_ISR_CAEIF    /*!< C-LUT Access Error Interrupt Flag */
00307 #define DMA2D_FLAG_TW          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
00308 #define DMA2D_FLAG_TC          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
00309 #define DMA2D_FLAG_TE          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317 /* Exported macro ------------------------------------------------------------*/
00318 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
00319   * @{
00320   */
00321
00322 /** @brief Reset DMA2D handle state
00323   * @param  __HANDLE__: specifies the DMA2D handle.
00324   * @retval None
00325   */
00326 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
00327
00328 /**
00329   * @brief  Enable the DMA2D.
00330   * @param  __HANDLE__: DMA2D handle
00331   * @retval None.
00332   */
00333 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
00334
00335
00336 /* Interrupt & Flag management */
00337 /**
00338   * @brief  Get the DMA2D pending flags.
00339   * @param  __HANDLE__: DMA2D handle
00340   * @param  __FLAG__: Get the specified flag.
00341   *          This parameter can be any combination of the following values:
00342   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00343   *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
00344   *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
00345   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00346   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00347   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00348   * @retval The state of FLAG.
00349   */
00350 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00351
00352 /**
00353   * @brief  Clears the DMA2D pending flags.
00354   * @param  __HANDLE__: DMA2D handle
00355   * @param  __FLAG__: specifies the flag to clear.
00356   *          This parameter can be any combination of the following values:
00357   *            @arg DMA2D_FLAG_CE:  Configuration error flag
00358   *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
00359   *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
00360   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
00361   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
00362   *            @arg DMA2D_FLAG_TE:  Transfer error flag
00363   * @retval None
00364   */
00365 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
00366
00367 /**
00368   * @brief  Enables the specified DMA2D interrupts.
00369   * @param  __HANDLE__: DMA2D handle
00370   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
00371   *          This parameter can be any combination of the following values:
00372   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00373   *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
00374   *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
00375   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00376   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00377   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00378   * @retval None
00379   */
00380 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00381
00382 /**
00383   * @brief  Disables the specified DMA2D interrupts.
00384   * @param  __HANDLE__: DMA2D handle
00385   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
00386   *          This parameter can be any combination of the following values:
00387   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00388   *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
00389   *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
00390   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00391   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00392   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00393   * @retval None
00394   */
00395 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00396
00397 /**
00398   * @brief  Checks whether the specified DMA2D interrupt has occurred or not.
00399   * @param  __HANDLE__: DMA2D handle
00400   * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
00401   *          This parameter can be one of the following values:
00402   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
00403   *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
00404   *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
00405   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
00406   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
00407   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
00408   * @retval The state of INTERRUPT.
00409   */
00410 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
00411 /**
00412   * @}
00413   */
00414
00415 /* Exported functions --------------------------------------------------------*/
00416 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
00417   * @{
00418   */
00419 /* Initialization and de-initialization functions *******************************/
00420 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
00421 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
00422 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
00423 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
00424
00425 /* IO operation functions *******************************************************/
00426 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00427 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
00428 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00429 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00430 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
00431 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
00432 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
00433 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00434 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
00435 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
00436 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
00437 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
00438
00439 /* Peripheral Control functions *************************************************/
00440 HAL_StatusTypeDef  HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00441 HAL_StatusTypeDef  HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
00442 HAL_StatusTypeDef  HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00443 HAL_StatusTypeDef  HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
00444 HAL_StatusTypeDef  HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
00445
00446 /* Peripheral State functions ***************************************************/
00447 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
00448 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
00449 /**
00450   * @}
00451   */
00452
00453 /* Private types -------------------------------------------------------------*/
00454 /** @defgroup DMA2D_Private_Types DMA2D Private Types
00455   * @{
00456   */
00457
00458 /**
00459   * @}
00460   */
00461
00462 /* Private defines -------------------------------------------------------------*/
00463 /** @defgroup DMA2D_Private_Defines DMA2D Private Defines
00464   * @{
00465   */
00466
00467 /**
00468   * @}
00469   */
00470
00471 /* Private variables ---------------------------------------------------------*/
00472 /** @defgroup DMA2D_Private_Variables DMA2D Private Variables
00473   * @{
00474   */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /* Private constants ---------------------------------------------------------*/
00481 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
00482   * @{
00483   */
00484
00485 /**
00486   * @}
00487   */
00488
00489 /* Private macros ------------------------------------------------------------*/
00490 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
00491   * @{
00492   */
00493 #define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= MAX_DMA2D_LAYER)
00494 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
00495                                                ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
00496 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888)   || \
00497                                                ((MODE_ARGB) == DMA2D_RGB565)   || ((MODE_ARGB) == DMA2D_ARGB1555) || \
00498                                                ((MODE_ARGB) == DMA2D_ARGB4444))
00499 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= COLOR_VALUE)
00500 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
00501 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
00502 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
00503 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888)   || \
00504                                                ((INPUT_CM) == CM_RGB565)   || ((INPUT_CM) == CM_ARGB1555) || \
00505                                                ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8)       || \
00506                                                ((INPUT_CM) == CM_AL44)     || ((INPUT_CM) == CM_AL88)     || \
00507                                                ((INPUT_CM) == CM_L4)       || ((INPUT_CM) == CM_A8)       || \
00508                                                ((INPUT_CM) == CM_A4))
00509 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
00510                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
00511                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
00512 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
00513 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
00514 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
00515 /**
00516   * @}
00517   */
00518
00519 /* Private functions prototypes ---------------------------------------------------------*/
00520 /** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
00521   * @{
00522   */
00523
00524 /**
00525   * @}
00526   */
00527
00528 /* Private functions ---------------------------------------------------------*/
00529 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
00530   * @{
00531   */
00532
00533 /**
00534   * @}
00535   */
00536
00537 /**
00538   * @}
00539   */
00540
00541 /**
00542   * @}
00543   */
00544
00545 #endif /* STM32F427xx || STM32F437xx  || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00546
00547 #ifdef __cplusplus
00548 }
00549 #endif
00550
00551 #endif /* __STM32F4xx_HAL_DMA2D_H */
00552
00553 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma.c Source File

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stm32f4xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DMA HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the Direct Memory Access (DMA) peripheral:
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State and errors functions
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019    (#) Enable and configure the peripheral to be connected to the DMA Stream
00020        (except for internal SRAM/FLASH memories: no initialization is
00021        necessary) please refer to Reference manual for connection between peripherals
00022        and DMA requests .
00023
00024    (#) For a given Stream, program the required configuration through the following parameters:
00025        Transfer Direction, Source and Destination data formats,
00026        Circular, Normal or peripheral flow control mode, Stream Priority level,
00027        Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
00028        Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
00029
00030      *** Polling mode IO operation ***
00031      =================================
00032     [..]
00033           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00034               address and destination address and the Length of data to be transferred
00035           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00036               case a fixed Timeout can be configured by User depending from his application.
00037
00038      *** Interrupt mode IO operation ***
00039      ===================================
00040     [..]
00041           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00042           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00043           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00044               Source address and destination address and the Length of data to be transferred. In this
00045               case the DMA interrupt is configured
00046           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00047           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00048               add his own function by customization of function pointer XferCpltCallback and
00049               XferErrorCallback (i.e a member of DMA handle structure).
00050     [..]
00051      (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00052          detection.
00053
00054      (#) Use HAL_DMA_Abort() function to abort the current transfer
00055
00056      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00057
00058      -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
00059            possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
00060            Half-Word data size for the peripheral to access its data register and set Word data size
00061            for the Memory to gain in access time. Each two half words will be packed and written in
00062            a single access to a Word in the Memory).
00063
00064      -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
00065            and Destination. In this case the Peripheral Data Size will be applied to both Source
00066            and Destination.
00067
00068      *** DMA HAL driver macros list ***
00069      =============================================
00070      [..]
00071        Below the list of most used macros in DMA HAL driver.
00072
00073       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
00074       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
00075       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
00076       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
00077
00078      [..]
00079       (@) You can refer to the DMA HAL driver header file for more useful macros
00080
00081   @endverbatim
00082   ******************************************************************************
00083   * @attention
00084   *
00085   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00086   *
00087   * Redistribution and use in source and binary forms, with or without modification,
00088   * are permitted provided that the following conditions are met:
00089   *   1. Redistributions of source code must retain the above copyright notice,
00090   *      this list of conditions and the following disclaimer.
00091   *   2. Redistributions in binary form must reproduce the above copyright notice,
00092   *      this list of conditions and the following disclaimer in the documentation
00093   *      and/or other materials provided with the distribution.
00094   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00095   *      may be used to endorse or promote products derived from this software
00096   *      without specific prior written permission.
00097   *
00098   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00099   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00100   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00101   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00102   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00103   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00104   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00105   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00106   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00107   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00108   *
00109   ******************************************************************************
00110   */
00111
00112 /* Includes ------------------------------------------------------------------*/
00113 #include "stm32f4xx_hal.h"
00114
00115 /** @addtogroup STM32F4xx_HAL_Driver
00116   * @{
00117   */
00118
00119 /** @defgroup DMA DMA
00120   * @brief DMA HAL module driver
00121   * @{
00122   */
00123
00124 #ifdef HAL_DMA_MODULE_ENABLED
00125
00126 /* Private types -------------------------------------------------------------*/
00127
00128 typedef struct
00129 {
00130   __IO uint32_t ISR;   /*!< DMA interrupt status register */
00131   __IO uint32_t Reserved0;
00132   __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
00133 } DMA_Base_Registers;
00134
00135 /* Private variables ---------------------------------------------------------*/
00136 /* Private constants ---------------------------------------------------------*/
00137 /** @addtogroup DMA_Private_Constants
00138  * @{
00139  */
00140  #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000U)  /* 1s */
00141 /**
00142   * @}
00143   */
00144 /* Private macros ------------------------------------------------------------*/
00145 /* Private functions ---------------------------------------------------------*/
00146 /** @addtogroup DMA_Private_Functions
00147   * @{
00148   */
00149 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00150 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
00151
00152 /**
00153   * @}
00154   */
00155
00156 /* Exported functions ---------------------------------------------------------*/
00157 /** @addtogroup DMA_Exported_Functions
00158   * @{
00159   */
00160
00161 /** @addtogroup DMA_Exported_Functions_Group1
00162   *
00163 @verbatim
00164  ===============================================================================
00165              ##### Initialization and de-initialization functions  #####
00166  ===============================================================================
00167     [..]
00168     This section provides functions allowing to initialize the DMA Stream source
00169     and destination addresses, incrementation and data sizes, transfer direction,
00170     circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
00171     [..]
00172     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00173     reference manual.
00174
00175 @endverbatim
00176   * @{
00177   */
00178
00179 /**
00180   * @brief  Initializes the DMA according to the specified
00181   *         parameters in the DMA_InitTypeDef and create the associated handle.
00182   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
00183   *               the configuration information for the specified DMA Stream.
00184   * @retval HAL status
00185   */
00186 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00187 {
00188   uint32_t tmp = 0U;
00189
00190   /* Check the DMA peripheral state */
00191   if(hdma == NULL)
00192   {
00193     return HAL_ERROR;
00194   }
00195
00196   /* Check the parameters */
00197   assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
00198   assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
00199   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00200   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00201   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00202   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00203   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00204   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00205   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00206   assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
00207   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
00208      when FIFO mode is enabled */
00209   if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
00210   {
00211     assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
00212     assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
00213     assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
00214   }
00215
00216   /* Change DMA peripheral state */
00217   hdma->State = HAL_DMA_STATE_BUSY;
00218
00219   /* Get the CR register value */
00220   tmp = hdma->Instance->CR;
00221
00222   /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
00223   tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
00224                       DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
00225                       DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
00226                       DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
00227
00228   /* Prepare the DMA Stream configuration */
00229   tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
00230           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00231           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00232           hdma->Init.Mode                | hdma->Init.Priority;
00233
00234   /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
00235   if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00236   {
00237     /* Get memory burst and peripheral burst */
00238     tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
00239   }
00240
00241   /* Write to DMA Stream CR register */
00242   hdma->Instance->CR = tmp;
00243
00244   /* Get the FCR register value */
00245   tmp = hdma->Instance->FCR;
00246
00247   /* Clear Direct mode and FIFO threshold bits */
00248   tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
00249
00250   /* Prepare the DMA Stream FIFO configuration */
00251   tmp |= hdma->Init.FIFOMode;
00252
00253   /* the FIFO threshold is not used when the FIFO mode is disabled */
00254   if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
00255   {
00256     /* Get the FIFO threshold */
00257     tmp |= hdma->Init.FIFOThreshold;
00258   }
00259
00260   /* Write to DMA Stream FCR */
00261   hdma->Instance->FCR = tmp;
00262
00263   /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
00264      DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
00265   DMA_CalcBaseAndBitshift(hdma);
00266
00267   /* Initialize the error code */
00268   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00269
00270   /* Initialize the DMA state */
00271   hdma->State = HAL_DMA_STATE_READY;
00272
00273   return HAL_OK;
00274 }
00275
00276 /**
00277   * @brief  DeInitializes the DMA peripheral
00278   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00279   *               the configuration information for the specified DMA Stream.
00280   * @retval HAL status
00281   */
00282 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00283 {
00284   DMA_Base_Registers *regs;
00285
00286   /* Check the DMA peripheral state */
00287   if(hdma == NULL)
00288   {
00289     return HAL_ERROR;
00290   }
00291
00292   /* Check the DMA peripheral state */
00293   if(hdma->State == HAL_DMA_STATE_BUSY)
00294   {
00295      return HAL_ERROR;
00296   }
00297
00298   /* Disable the selected DMA Streamx */
00299   __HAL_DMA_DISABLE(hdma);
00300
00301   /* Reset DMA Streamx control register */
00302   hdma->Instance->CR   = 0U;
00303
00304   /* Reset DMA Streamx number of data to transfer register */
00305   hdma->Instance->NDTR = 0U;
00306
00307   /* Reset DMA Streamx peripheral address register */
00308   hdma->Instance->PAR  = 0U;
00309
00310   /* Reset DMA Streamx memory 0 address register */
00311   hdma->Instance->M0AR = 0U;
00312
00313   /* Reset DMA Streamx memory 1 address register */
00314   hdma->Instance->M1AR = 0U;
00315
00316   /* Reset DMA Streamx FIFO control register */
00317   hdma->Instance->FCR  = (uint32_t)0x00000021U;
00318
00319   /* Get DMA steam Base Address */
00320   regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
00321
00322   /* Clear all interrupt flags at correct offset within the register */
00323   regs->IFCR = 0x3FU << hdma->StreamIndex;
00324
00325   /* Initialize the error code */
00326   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00327
00328   /* Initialize the DMA state */
00329   hdma->State = HAL_DMA_STATE_RESET;
00330
00331   /* Release Lock */
00332   __HAL_UNLOCK(hdma);
00333
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @}
00339   */
00340
00341 /** @addtogroup DMA_Exported_Functions_Group2
00342   *
00343 @verbatim
00344  ===============================================================================
00345                       #####  IO operation functions  #####
00346  ===============================================================================
00347     [..]  This section provides functions allowing to:
00348       (+) Configure the source, destination address and data length and Start DMA transfer
00349       (+) Configure the source, destination address and data length and
00350           Start DMA transfer with interrupt
00351       (+) Abort DMA transfer
00352       (+) Poll for transfer complete
00353       (+) Handle DMA interrupt request
00354
00355 @endverbatim
00356   * @{
00357   */
00358
00359 /**
00360   * @brief  Starts the DMA Transfer.
00361   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00362   *                     the configuration information for the specified DMA Stream.
00363   * @param  SrcAddress: The source memory Buffer address
00364   * @param  DstAddress: The destination memory Buffer address
00365   * @param  DataLength: The length of data to be transferred from source to destination
00366   * @retval HAL status
00367   */
00368 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00369 {
00370   /* Process locked */
00371   __HAL_LOCK(hdma);
00372
00373   /* Change DMA peripheral state */
00374   hdma->State = HAL_DMA_STATE_BUSY;
00375
00376    /* Check the parameters */
00377   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00378
00379   /* Disable the peripheral */
00380   __HAL_DMA_DISABLE(hdma);
00381
00382   /* Configure the source, destination address and the data length */
00383   DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00384
00385   /* Enable the Peripheral */
00386   __HAL_DMA_ENABLE(hdma);
00387
00388   return HAL_OK;
00389 }
00390
00391 /**
00392   * @brief  Start the DMA Transfer with interrupt enabled.
00393   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00394   *                     the configuration information for the specified DMA Stream.
00395   * @param  SrcAddress: The source memory Buffer address
00396   * @param  DstAddress: The destination memory Buffer address
00397   * @param  DataLength: The length of data to be transferred from source to destination
00398   * @retval HAL status
00399   */
00400 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00401 {
00402   /* Process locked */
00403   __HAL_LOCK(hdma);
00404
00405   /* Change DMA peripheral state */
00406   hdma->State = HAL_DMA_STATE_BUSY;
00407
00408    /* Check the parameters */
00409   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00410
00411   /* Disable the peripheral */
00412   __HAL_DMA_DISABLE(hdma);
00413
00414   /* Configure the source, destination address and the data length */
00415   DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00416
00417   /* Enable all interrupts */
00418   hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
00419   hdma->Instance->FCR |= DMA_IT_FE;
00420
00421    /* Enable the Peripheral */
00422   __HAL_DMA_ENABLE(hdma);
00423
00424   return HAL_OK;
00425 }
00426
00427 /**
00428   * @brief  Aborts the DMA Transfer.
00429   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00430   *                 the configuration information for the specified DMA Stream.
00431   *
00432   * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
00433   *        effectively disabled is added. If a Stream is disabled
00434   *        while a data transfer is ongoing, the current data will be transferred
00435   *        and the Stream will be effectively disabled only after the transfer of
00436   *        this single data is finished.
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00440 {
00441   uint32_t tickstart = 0U;
00442
00443   /* Disable the stream */
00444   __HAL_DMA_DISABLE(hdma);
00445
00446   /* Get tick */
00447   tickstart = HAL_GetTick();
00448
00449   /* Check if the DMA Stream is effectively disabled */
00450   while((hdma->Instance->CR & DMA_SxCR_EN) != 0U)
00451   {
00452     /* Check for the Timeout */
00453     if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
00454     {
00455       /* Update error code */
00456       hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
00457
00458       /* Process Unlocked */
00459       __HAL_UNLOCK(hdma);
00460
00461       /* Change the DMA state */
00462       hdma->State = HAL_DMA_STATE_TIMEOUT;
00463
00464       return HAL_TIMEOUT;
00465     }
00466   }
00467   /* Process Unlocked */
00468   __HAL_UNLOCK(hdma);
00469
00470   /* Change the DMA state*/
00471   hdma->State = HAL_DMA_STATE_READY;
00472
00473   return HAL_OK;
00474 }
00475
00476 /**
00477   * @brief  Polling for transfer complete.
00478   * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
00479   *                        the configuration information for the specified DMA Stream.
00480   * @param  CompleteLevel: Specifies the DMA level complete.
00481   * @param  Timeout:       Timeout duration.
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
00485 {
00486   uint32_t temp, tmp, tmp1, tmp2;
00487   uint32_t tickstart = 0U;
00488
00489   /* calculate DMA base and stream number */
00490   DMA_Base_Registers *regs;
00491
00492   regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
00493
00494   /* Get the level transfer complete flag */
00495   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00496   {
00497     /* Transfer Complete flag */
00498     temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
00499   }
00500   else
00501   {
00502     /* Half Transfer Complete flag */
00503     temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00504   }
00505
00506   /* Get tick */
00507   tickstart = HAL_GetTick();
00508
00509   while((regs->ISR & temp) == RESET)
00510   {
00511     tmp  = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
00512     tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
00513     tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
00514     if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
00515     {
00516       if(tmp != RESET)
00517       {
00518         /* Update error code */
00519         hdma->ErrorCode |= HAL_DMA_ERROR_TE;
00520
00521         /* Clear the transfer error flag */
00522         regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
00523       }
00524       if(tmp1 != RESET)
00525       {
00526         /* Update error code */
00527         hdma->ErrorCode |= HAL_DMA_ERROR_FE;
00528
00529         /* Clear the FIFO error flag */
00530         regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
00531       }
00532       if(tmp2 != RESET)
00533       {
00534         /* Update error code */
00535         hdma->ErrorCode |= HAL_DMA_ERROR_DME;
00536
00537         /* Clear the Direct Mode error flag */
00538         regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
00539       }
00540       /* Change the DMA state */
00541       hdma->State= HAL_DMA_STATE_ERROR;
00542
00543       /* Process Unlocked */
00544       __HAL_UNLOCK(hdma);
00545
00546       return HAL_ERROR;
00547     }
00548     /* Check for the Timeout */
00549     if(Timeout != HAL_MAX_DELAY)
00550     {
00551       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00552       {
00553         /* Update error code */
00554         hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
00555
00556         /* Change the DMA state */
00557         hdma->State = HAL_DMA_STATE_TIMEOUT;
00558
00559         /* Process Unlocked */
00560         __HAL_UNLOCK(hdma);
00561
00562         return HAL_TIMEOUT;
00563       }
00564     }
00565   }
00566
00567   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00568   {
00569     /* Clear the half transfer and transfer complete flags */
00570     regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
00571
00572     /* Multi_Buffering mode enabled */
00573     if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
00574     {
00575       /* Current memory buffer used is Memory 0 */
00576       if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
00577       {
00578         /* Change DMA peripheral state */
00579         hdma->State = HAL_DMA_STATE_READY_MEM0;
00580       }
00581       /* Current memory buffer used is Memory 1 */
00582       else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
00583       {
00584         /* Change DMA peripheral state */
00585         hdma->State = HAL_DMA_STATE_READY_MEM1;
00586       }
00587     }
00588     else
00589     {
00590       /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
00591          are complete) */
00592       hdma->State = HAL_DMA_STATE_READY_MEM0;
00593     }
00594     /* Process Unlocked */
00595     __HAL_UNLOCK(hdma);
00596   }
00597   else
00598   {
00599     /* Clear the half transfer complete flag */
00600     regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00601
00602     /* Multi_Buffering mode enabled */
00603     if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
00604     {
00605       /* Current memory buffer used is Memory 0 */
00606       if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
00607       {
00608         /* Change DMA peripheral state */
00609         hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00610       }
00611       /* Current memory buffer used is Memory 1 */
00612       else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
00613       {
00614         /* Change DMA peripheral state */
00615         hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
00616       }
00617     }
00618     else
00619     {
00620       /* Change DMA peripheral state */
00621       hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00622     }
00623   }
00624   return HAL_OK;
00625 }
00626
00627 /**
00628   * @brief  Handles DMA interrupt request.
00629   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00630   *               the configuration information for the specified DMA Stream.
00631   * @retval None
00632   */
00633 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00634 {
00635   /* calculate DMA base and stream number */
00636   DMA_Base_Registers *regs;
00637
00638   regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
00639
00640   /* Transfer Error Interrupt management ***************************************/
00641   if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
00642   {
00643     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
00644     {
00645       /* Disable the transfer error interrupt */
00646       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
00647
00648       /* Clear the transfer error flag */
00649       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
00650
00651       /* Update error code */
00652       hdma->ErrorCode |= HAL_DMA_ERROR_TE;
00653
00654       /* Change the DMA state */
00655       hdma->State = HAL_DMA_STATE_ERROR;
00656
00657       /* Process Unlocked */
00658       __HAL_UNLOCK(hdma);
00659
00660       if(hdma->XferErrorCallback != NULL)
00661       {
00662         /* Transfer error callback */
00663         hdma->XferErrorCallback(hdma);
00664       }
00665     }
00666   }
00667   /* FIFO Error Interrupt management ******************************************/
00668   if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
00669   {
00670     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
00671     {
00672       /* Disable the FIFO Error interrupt */
00673       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
00674
00675       /* Clear the FIFO error flag */
00676       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
00677
00678       /* Update error code */
00679       hdma->ErrorCode |= HAL_DMA_ERROR_FE;
00680
00681       /* Change the DMA state */
00682       hdma->State = HAL_DMA_STATE_ERROR;
00683
00684       /* Process Unlocked */
00685       __HAL_UNLOCK(hdma);
00686
00687       if(hdma->XferErrorCallback != NULL)
00688       {
00689         /* Transfer error callback */
00690         hdma->XferErrorCallback(hdma);
00691       }
00692     }
00693   }
00694   /* Direct Mode Error Interrupt management ***********************************/
00695   if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
00696   {
00697     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
00698     {
00699       /* Disable the direct mode Error interrupt */
00700       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
00701
00702       /* Clear the direct mode error flag */
00703       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
00704
00705       /* Update error code */
00706       hdma->ErrorCode |= HAL_DMA_ERROR_DME;
00707
00708       /* Change the DMA state */
00709       hdma->State = HAL_DMA_STATE_ERROR;
00710
00711       /* Process Unlocked */
00712       __HAL_UNLOCK(hdma);
00713
00714       if(hdma->XferErrorCallback != NULL)
00715       {
00716         /* Transfer error callback */
00717         hdma->XferErrorCallback(hdma);
00718       }
00719     }
00720   }
00721   /* Half Transfer Complete Interrupt management ******************************/
00722   if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
00723   {
00724     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
00725     {
00726       /* Multi_Buffering mode enabled */
00727       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
00728       {
00729         /* Clear the half transfer complete flag */
00730         regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00731
00732         /* Current memory buffer used is Memory 0 */
00733         if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
00734         {
00735           /* Change DMA peripheral state */
00736           hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00737         }
00738         /* Current memory buffer used is Memory 1 */
00739         else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
00740         {
00741           /* Change DMA peripheral state */
00742           hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
00743         }
00744       }
00745       else
00746       {
00747         /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00748         if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
00749         {
00750           /* Disable the half transfer interrupt */
00751           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00752         }
00753         /* Clear the half transfer complete flag */
00754         regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
00755
00756         /* Change DMA peripheral state */
00757         hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
00758       }
00759
00760       if(hdma->XferHalfCpltCallback != NULL)
00761       {
00762         /* Half transfer callback */
00763         hdma->XferHalfCpltCallback(hdma);
00764       }
00765     }
00766   }
00767   /* Transfer Complete Interrupt management ***********************************/
00768   if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
00769   {
00770     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
00771     {
00772       if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
00773       {
00774         /* Clear the transfer complete flag */
00775         regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
00776
00777         /* Current memory buffer used is Memory 0 */
00778         if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
00779         {
00780           if(hdma->XferM1CpltCallback != NULL)
00781           {
00782             /* Transfer complete Callback for memory1 */
00783             hdma->XferM1CpltCallback(hdma);
00784           }
00785         }
00786         /* Current memory buffer used is Memory 1 */
00787         else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
00788         {
00789           if(hdma->XferCpltCallback != NULL)
00790           {
00791             /* Transfer complete Callback for memory0 */
00792             hdma->XferCpltCallback(hdma);
00793           }
00794         }
00795       }
00796       /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
00797       else
00798       {
00799         if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
00800         {
00801           /* Disable the transfer complete interrupt */
00802           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
00803         }
00804         /* Clear the transfer complete flag */
00805         regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
00806
00807         /* Update error code */
00808         hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
00809
00810         /* Change the DMA state */
00811         hdma->State = HAL_DMA_STATE_READY_MEM0;
00812
00813         /* Process Unlocked */
00814         __HAL_UNLOCK(hdma);
00815
00816         if(hdma->XferCpltCallback != NULL)
00817         {
00818           /* Transfer complete callback */
00819           hdma->XferCpltCallback(hdma);
00820         }
00821       }
00822     }
00823   }
00824 }
00825
00826 /**
00827   * @}
00828   */
00829
00830 /** @addtogroup DMA_Exported_Functions_Group3
00831   *
00832 @verbatim
00833  ===============================================================================
00834                     ##### State and Errors functions #####
00835  ===============================================================================
00836     [..]
00837     This subsection provides functions allowing to
00838       (+) Check the DMA state
00839       (+) Get error code
00840
00841 @endverbatim
00842   * @{
00843   */
00844
00845 /**
00846   * @brief  Returns the DMA state.
00847   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00848   *               the configuration information for the specified DMA Stream.
00849   * @retval HAL state
00850   */
00851 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
00852 {
00853   return hdma->State;
00854 }
00855
00856 /**
00857   * @brief  Return the DMA error code
00858   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
00859   *              the configuration information for the specified DMA Stream.
00860   * @retval DMA Error Code
00861   */
00862 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
00863 {
00864   return hdma->ErrorCode;
00865 }
00866
00867 /**
00868   * @}
00869   */
00870
00871 /**
00872   * @}
00873   */
00874
00875 /** @addtogroup DMA_Private_Functions
00876   * @{
00877   */
00878
00879 /**
00880   * @brief  Sets the DMA Transfer parameter.
00881   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00882   *                     the configuration information for the specified DMA Stream.
00883   * @param  SrcAddress: The source memory Buffer address
00884   * @param  DstAddress: The destination memory Buffer address
00885   * @param  DataLength: The length of data to be transferred from source to destination
00886   * @retval HAL status
00887   */
00888 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00889 {
00890   /* Clear DBM bit */
00891   hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
00892
00893   /* Configure DMA Stream data length */
00894   hdma->Instance->NDTR = DataLength;
00895
00896   /* Peripheral to Memory */
00897   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00898   {
00899     /* Configure DMA Stream destination address */
00900     hdma->Instance->PAR = DstAddress;
00901
00902     /* Configure DMA Stream source address */
00903     hdma->Instance->M0AR = SrcAddress;
00904   }
00905   /* Memory to Peripheral */
00906   else
00907   {
00908     /* Configure DMA Stream source address */
00909     hdma->Instance->PAR = SrcAddress;
00910
00911     /* Configure DMA Stream destination address */
00912     hdma->Instance->M0AR = DstAddress;
00913   }
00914 }
00915
00916 /**
00917   * @brief  Returns the DMA Stream base address depending on stream number
00918   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00919   *                     the configuration information for the specified DMA Stream.
00920   * @retval Stream base address
00921   */
00922 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
00923 {
00924   uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
00925
00926   /* lookup table for necessary bitshift of flags within status registers */
00927   static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
00928   hdma->StreamIndex = flagBitshiftOffset[stream_number];
00929
00930   if (stream_number > 3U)
00931   {
00932     /* return pointer to HISR and HIFCR */
00933     hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
00934   }
00935   else
00936   {
00937     /* return pointer to LISR and LIFCR */
00938     hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
00939   }
00940
00941   return hdma->StreamBaseAddress;
00942 }
00943 /**
00944   * @}
00945   */
00946
00947 #endif /* HAL_DMA_MODULE_ENABLED */
00948 /**
00949   * @}
00950   */
00951
00952 /**
00953   * @}
00954   */
00955
00956 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma.h Source File

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stm32f4xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DMA_H
00040 #define __STM32F4xx_HAL_DMA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup DMA_Exported_Types DMA Exported Types
00060   * @brief    DMA Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  DMA Configuration Structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t Channel;              /*!< Specifies the channel used for the specified stream.
00070                                       This parameter can be a value of @ref DMA_Channel_selection                    */
00071
00072   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
00073                                       from memory to memory or from peripheral to memory.
00074                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
00075
00076   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
00077                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
00078
00079   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
00080                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
00081
00082   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
00083                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
00084
00085   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
00086                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
00087
00088   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
00089                                       This parameter can be a value of @ref DMA_mode
00090                                       @note The circular buffer mode cannot be used if the memory-to-memory
00091                                             data transfer is configured on the selected Stream                        */
00092
00093   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
00094                                       This parameter can be a value of @ref DMA_Priority_level                       */
00095
00096   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
00097                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
00098                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
00099                                             memory-to-memory data transfer is configured on the selected stream       */
00100
00101   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
00102                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
00103
00104   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
00105                                       It specifies the amount of data to be transferred in a single non interruptible
00106                                       transaction.
00107                                       This parameter can be a value of @ref DMA_Memory_burst
00108                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00109
00110   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
00111                                       It specifies the amount of data to be transferred in a single non interruptable
00112                                       transaction.
00113                                       This parameter can be a value of @ref DMA_Peripheral_burst
00114                                       @note The burst mode is possible only if the address Increment mode is enabled. */
00115 }DMA_InitTypeDef;
00116
00117
00118 /**
00119   * @brief  HAL DMA State structures definition
00120   */
00121 typedef enum
00122 {
00123   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
00124   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
00125   HAL_DMA_STATE_READY_MEM0        = 0x11U,  /*!< DMA Mem0 process success            */
00126   HAL_DMA_STATE_READY_MEM1        = 0x21U,  /*!< DMA Mem1 process success            */
00127   HAL_DMA_STATE_READY_HALF_MEM0   = 0x31U,  /*!< DMA Mem0 Half process success       */
00128   HAL_DMA_STATE_READY_HALF_MEM1   = 0x41U,  /*!< DMA Mem1 Half process success       */
00129   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
00130   HAL_DMA_STATE_BUSY_MEM0         = 0x12U,  /*!< DMA Mem0 process is ongoing         */
00131   HAL_DMA_STATE_BUSY_MEM1         = 0x22U,  /*!< DMA Mem1 process is ongoing         */
00132   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
00133   HAL_DMA_STATE_ERROR             = 0x04U   /*!< DMA error state                     */
00134 }HAL_DMA_StateTypeDef;
00135
00136 /**
00137   * @brief  HAL DMA Error Code structure definition
00138   */
00139 typedef enum
00140 {
00141   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
00142   HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
00143 }HAL_DMA_LevelCompleteTypeDef;
00144
00145 /**
00146   * @brief  DMA handle Structure definition
00147   */
00148 typedef struct __DMA_HandleTypeDef
00149 {
00150   DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
00151
00152   DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */
00153
00154   HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */
00155
00156   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
00157
00158   void                       *Parent;                                                      /*!< Parent object state                    */
00159
00160   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
00161
00162   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
00163
00164   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
00165
00166   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
00167
00168  __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                         */
00169
00170  uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
00171
00172  uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
00173 }DMA_HandleTypeDef;
00174
00175 /**
00176   * @}
00177   */
00178
00179 /* Exported constants --------------------------------------------------------*/
00180
00181 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00182   * @brief    DMA Exported constants
00183   * @{
00184   */
00185
00186 /** @defgroup DMA_Error_Code DMA Error Code
00187   * @brief    DMA Error Code
00188   * @{
00189   */
00190 #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error             */
00191 #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001U)    /*!< Transfer error       */
00192 #define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002U)    /*!< FIFO error           */
00193 #define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004U)    /*!< Direct Mode error    */
00194 #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error        */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup DMA_Channel_selection DMA Channel selection
00200   * @brief    DMA channel selection
00201   * @{
00202   */
00203 #define DMA_CHANNEL_0        ((uint32_t)0x00000000U)  /*!< DMA Channel 0 */
00204 #define DMA_CHANNEL_1        ((uint32_t)0x02000000U)  /*!< DMA Channel 1 */
00205 #define DMA_CHANNEL_2        ((uint32_t)0x04000000U)  /*!< DMA Channel 2 */
00206 #define DMA_CHANNEL_3        ((uint32_t)0x06000000U)  /*!< DMA Channel 3 */
00207 #define DMA_CHANNEL_4        ((uint32_t)0x08000000U)  /*!< DMA Channel 4 */
00208 #define DMA_CHANNEL_5        ((uint32_t)0x0A000000U)  /*!< DMA Channel 5 */
00209 #define DMA_CHANNEL_6        ((uint32_t)0x0C000000U)  /*!< DMA Channel 6 */
00210 #define DMA_CHANNEL_7        ((uint32_t)0x0E000000U)  /*!< DMA Channel 7 */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00216   * @brief    DMA data transfer direction
00217   * @{
00218   */
00219 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
00220 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
00221 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00227   * @brief    DMA peripheral incremented mode
00228   * @{
00229   */
00230 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
00231 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00237   * @brief    DMA memory incremented mode
00238   * @{
00239   */
00240 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
00241 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00247   * @brief    DMA peripheral data size
00248   * @{
00249   */
00250 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Peripheral data alignment: Byte     */
00251 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
00252 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup DMA_Memory_data_size DMA Memory data size
00258   * @brief    DMA memory data size
00259   * @{
00260   */
00261 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Memory data alignment: Byte     */
00262 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
00263 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup DMA_mode DMA mode
00269   * @brief    DMA mode
00270   * @{
00271   */
00272 #define DMA_NORMAL         ((uint32_t)0x00000000U)       /*!< Normal mode                  */
00273 #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
00274 #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup DMA_Priority_level DMA Priority level
00280   * @brief    DMA priority levels
00281   * @{
00282   */
00283 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low       */
00284 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
00285 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
00286 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
00292   * @brief    DMA FIFO direct mode
00293   * @{
00294   */
00295 #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
00296 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
00302   * @brief    DMA FIFO level
00303   * @{
00304   */
00305 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
00306 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
00307 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
00308 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup DMA_Memory_burst DMA Memory burst
00314   * @brief    DMA memory burst
00315   * @{
00316   */
00317 #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
00318 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
00319 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
00320 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
00326   * @brief    DMA peripheral burst
00327   * @{
00328   */
00329 #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
00330 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
00331 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
00332 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00338   * @brief    DMA interrupts definition
00339   * @{
00340   */
00341 #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
00342 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
00343 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
00344 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
00345 #define DMA_IT_FE                         ((uint32_t)0x00000080U)
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup DMA_flag_definitions DMA flag definitions
00351   * @brief    DMA flag definitions
00352   * @{
00353   */
00354 #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001U)
00355 #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004U)
00356 #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
00357 #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
00358 #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
00359 #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
00360 #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
00361 #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
00362 #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
00363 #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
00364 #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
00365 #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
00366 #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
00367 #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
00368 #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
00369 #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
00370 #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
00371 #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
00372 #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
00373 #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
00374 /**
00375   * @}
00376   */
00377
00378 /**
00379   * @}
00380   */
00381
00382 /* Exported macro ------------------------------------------------------------*/
00383
00384 /** @brief Reset DMA handle state
00385   * @param  __HANDLE__: specifies the DMA handle.
00386   * @retval None
00387   */
00388 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00389
00390 /**
00391   * @brief  Return the current DMA Stream FIFO filled level.
00392   * @param  __HANDLE__: DMA handle
00393   * @retval The FIFO filling state.
00394   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
00395   *                                              and not empty.
00396   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
00397   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
00398   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
00399   *           - DMA_FIFOStatus_Empty: when FIFO is empty
00400   *           - DMA_FIFOStatus_Full: when FIFO is full
00401   */
00402 #define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
00403
00404 /**
00405   * @brief  Enable the specified DMA Stream.
00406   * @param  __HANDLE__: DMA handle
00407   * @retval None
00408   */
00409 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
00410
00411 /**
00412   * @brief  Disable the specified DMA Stream.
00413   * @param  __HANDLE__: DMA handle
00414   * @retval None
00415   */
00416 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
00417
00418 /* Interrupt & Flag management */
00419
00420 /**
00421   * @brief  Return the current DMA Stream transfer complete flag.
00422   * @param  __HANDLE__: DMA handle
00423   * @retval The specified transfer complete flag index.
00424   */
00425 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00426 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
00427  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
00428  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
00429  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
00430  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
00431  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
00432  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
00433  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
00434  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
00435  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
00436  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
00437  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
00438    DMA_FLAG_TCIF3_7)
00439
00440 /**
00441   * @brief  Return the current DMA Stream half transfer complete flag.
00442   * @param  __HANDLE__: DMA handle
00443   * @retval The specified half transfer complete flag index.
00444   */
00445 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00446 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
00447  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
00448  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
00449  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
00450  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
00451  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
00452  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
00453  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
00454  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
00455  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
00456  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
00457  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
00458    DMA_FLAG_HTIF3_7)
00459
00460 /**
00461   * @brief  Return the current DMA Stream transfer error flag.
00462   * @param  __HANDLE__: DMA handle
00463   * @retval The specified transfer error flag index.
00464   */
00465 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00466 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
00467  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
00468  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
00469  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
00470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
00471  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
00472  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
00473  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
00474  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
00475  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
00476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
00477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
00478    DMA_FLAG_TEIF3_7)
00479
00480 /**
00481   * @brief  Return the current DMA Stream FIFO error flag.
00482   * @param  __HANDLE__: DMA handle
00483   * @retval The specified FIFO error flag index.
00484   */
00485 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
00486 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
00487  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
00488  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
00489  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
00490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
00491  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
00492  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
00493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
00494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
00495  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
00496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
00497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
00498    DMA_FLAG_FEIF3_7)
00499
00500 /**
00501   * @brief  Return the current DMA Stream direct mode error flag.
00502   * @param  __HANDLE__: DMA handle
00503   * @retval The specified direct mode error flag index.
00504   */
00505 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
00506 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
00507  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
00508  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
00509  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
00510  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
00511  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
00512  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
00513  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
00514  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
00515  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
00516  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
00517  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
00518    DMA_FLAG_DMEIF3_7)
00519
00520 /**
00521   * @brief  Get the DMA Stream pending flags.
00522   * @param  __HANDLE__: DMA handle
00523   * @param  __FLAG__: Get the specified flag.
00524   *          This parameter can be any combination of the following values:
00525   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
00526   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
00527   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
00528   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
00529   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
00530   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
00531   * @retval The state of FLAG (SET or RESET).
00532   */
00533 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
00534 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
00535  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
00536  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
00537
00538 /**
00539   * @brief  Clear the DMA Stream pending flags.
00540   * @param  __HANDLE__: DMA handle
00541   * @param  __FLAG__: specifies the flag to clear.
00542   *          This parameter can be any combination of the following values:
00543   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
00544   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
00545   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
00546   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
00547   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
00548   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
00549   * @retval None
00550   */
00551 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00552 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
00553  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
00554  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
00555
00556 /**
00557   * @brief  Enable the specified DMA Stream interrupts.
00558   * @param  __HANDLE__: DMA handle
00559   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00560   *        This parameter can be any combination of the following values:
00561   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
00562   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
00563   *           @arg DMA_IT_TE: Transfer error interrupt mask.
00564   *           @arg DMA_IT_FE: FIFO error interrupt mask.
00565   *           @arg DMA_IT_DME: Direct mode error interrupt.
00566   * @retval None
00567   */
00568 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
00569 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
00570
00571 /**
00572   * @brief  Disable the specified DMA Stream interrupts.
00573   * @param  __HANDLE__: DMA handle
00574   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00575   *         This parameter can be any combination of the following values:
00576   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
00577   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
00578   *            @arg DMA_IT_TE: Transfer error interrupt mask.
00579   *            @arg DMA_IT_FE: FIFO error interrupt mask.
00580   *            @arg DMA_IT_DME: Direct mode error interrupt.
00581   * @retval None
00582   */
00583 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
00584 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
00585
00586 /**
00587   * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
00588   * @param  __HANDLE__: DMA handle
00589   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00590   *         This parameter can be one of the following values:
00591   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
00592   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
00593   *            @arg DMA_IT_TE: Transfer error interrupt mask.
00594   *            @arg DMA_IT_FE: FIFO error interrupt mask.
00595   *            @arg DMA_IT_DME: Direct mode error interrupt.
00596   * @retval The state of DMA_IT.
00597   */
00598 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
00599                                                         ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
00600                                                         ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
00601
00602 /**
00603   * @brief  Writes the number of data units to be transferred on the DMA Stream.
00604   * @param  __HANDLE__: DMA handle
00605   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
00606   *          Number of data items depends only on the Peripheral data format.
00607   *
00608   * @note   If Peripheral data format is Bytes: number of data units is equal
00609   *         to total number of bytes to be transferred.
00610   *
00611   * @note   If Peripheral data format is Half-Word: number of data units is
00612   *         equal to total number of bytes to be transferred / 2.
00613   *
00614   * @note   If Peripheral data format is Word: number of data units is equal
00615   *         to total  number of bytes to be transferred / 4.
00616   *
00617   * @retval The number of remaining data units in the current DMAy Streamx transfer.
00618   */
00619 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
00620
00621 /**
00622   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
00623   * @param  __HANDLE__: DMA handle
00624   *
00625   * @retval The number of remaining data units in the current DMA Stream transfer.
00626   */
00627 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
00628
00629
00630 /* Include DMA HAL Extension module */
00631 #include "stm32f4xx_hal_dma_ex.h"
00632
00633 /* Exported functions --------------------------------------------------------*/
00634
00635 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00636   * @brief    DMA Exported functions
00637   * @{
00638   */
00639
00640 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00641   * @brief   Initialization and de-initialization functions
00642   * @{
00643   */
00644 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00645 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
00651   * @brief   I/O operation functions
00652   * @{
00653   */
00654 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00655 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00656 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00657 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
00658 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00659 /**
00660   * @}
00661   */
00662
00663 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
00664   * @brief    Peripheral State functions
00665   * @{
00666   */
00667 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00668 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00669 /**
00670   * @}
00671   */
00672 /**
00673   * @}
00674   */
00675 /* Private Constants -------------------------------------------------------------*/
00676 /** @defgroup DMA_Private_Constants DMA Private Constants
00677   * @brief    DMA private defines and constants
00678   * @{
00679   */
00680 /**
00681   * @}
00682   */
00683
00684 /* Private macros ------------------------------------------------------------*/
00685 /** @defgroup DMA_Private_Macros DMA Private Macros
00686   * @brief    DMA private macros
00687   * @{
00688   */
00689 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
00690                                  ((CHANNEL) == DMA_CHANNEL_1) || \
00691                                  ((CHANNEL) == DMA_CHANNEL_2) || \
00692                                  ((CHANNEL) == DMA_CHANNEL_3) || \
00693                                  ((CHANNEL) == DMA_CHANNEL_4) || \
00694                                  ((CHANNEL) == DMA_CHANNEL_5) || \
00695                                  ((CHANNEL) == DMA_CHANNEL_6) || \
00696                                  ((CHANNEL) == DMA_CHANNEL_7))
00697
00698 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00699                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00700                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00701
00702 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
00703
00704 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00705                                             ((STATE) == DMA_PINC_DISABLE))
00706
00707 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00708                                         ((STATE) == DMA_MINC_DISABLE))
00709
00710 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00711                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00712                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00713
00714 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00715                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00716                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00717
00718 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00719                            ((MODE) == DMA_CIRCULAR) || \
00720                            ((MODE) == DMA_PFCTRL))
00721
00722 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00723                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00724                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00725                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00726
00727 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
00728                                        ((STATE) == DMA_FIFOMODE_ENABLE))
00729
00730 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
00731                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
00732                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
00733                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
00734
00735 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
00736                                     ((BURST) == DMA_MBURST_INC4)   || \
00737                                     ((BURST) == DMA_MBURST_INC8)   || \
00738                                     ((BURST) == DMA_MBURST_INC16))
00739
00740 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
00741                                         ((BURST) == DMA_PBURST_INC4)   || \
00742                                         ((BURST) == DMA_PBURST_INC8)   || \
00743                                         ((BURST) == DMA_PBURST_INC16))
00744 /**
00745   * @}
00746   */
00747
00748 /* Private functions ---------------------------------------------------------*/
00749 /** @defgroup DMA_Private_Functions DMA Private Functions
00750   * @brief    DMA private  functions
00751   * @{
00752   */
00753 /**
00754   * @}
00755   */
00756
00757 /**
00758   * @}
00759   */
00760
00761 /**
00762   * @}
00763   */
00764
00765 #ifdef __cplusplus
00766 }
00767 #endif
00768
00769 #endif /* __STM32F4xx_HAL_DMA_H */
00770
00771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma_ex.c Source File

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  • STM32F4xx_HAL_Driver
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stm32f4xx_hal_dma_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dma_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DMA Extension HAL module driver
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the DMA Extension peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017   The DMA Extension HAL driver can be used as follows:
00018    (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
00019        for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
00020
00021      -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
00022      -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
00023      -@-  In Multi (Double) buffer mode, it is possible to update the base address for
00024           the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
00025
00026   @endverbatim
00027   ******************************************************************************
00028   * @attention
00029   *
00030   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00031   *
00032   * Redistribution and use in source and binary forms, with or without modification,
00033   * are permitted provided that the following conditions are met:
00034   *   1. Redistributions of source code must retain the above copyright notice,
00035   *      this list of conditions and the following disclaimer.
00036   *   2. Redistributions in binary form must reproduce the above copyright notice,
00037   *      this list of conditions and the following disclaimer in the documentation
00038   *      and/or other materials provided with the distribution.
00039   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00040   *      may be used to endorse or promote products derived from this software
00041   *      without specific prior written permission.
00042   *
00043   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00044   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00045   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00046   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00047   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00048   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00049   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00050   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00051   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00052   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00053   *
00054   ******************************************************************************
00055   */
00056
00057 /* Includes ------------------------------------------------------------------*/
00058 #include "stm32f4xx_hal.h"
00059
00060 /** @addtogroup STM32F4xx_HAL_Driver
00061   * @{
00062   */
00063
00064 /** @defgroup DMAEx DMAEx
00065   * @brief DMA Extended HAL module driver
00066   * @{
00067   */
00068
00069 #ifdef HAL_DMA_MODULE_ENABLED
00070
00071 /* Private types -------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private Constants ---------------------------------------------------------*/
00074 /* Private macros ------------------------------------------------------------*/
00075 /* Private functions ---------------------------------------------------------*/
00076 /** @addtogroup DMAEx_Private_Functions
00077   * @{
00078   */
00079 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00080 /**
00081   * @}
00082   */
00083
00084 /* Exported functions ---------------------------------------------------------*/
00085
00086 /** @addtogroup DMAEx_Exported_Functions
00087   * @{
00088   */
00089
00090
00091 /** @addtogroup DMAEx_Exported_Functions_Group1
00092   *
00093 @verbatim
00094  ===============================================================================
00095                 #####  Extended features functions  #####
00096  ===============================================================================
00097     [..]  This section provides functions allowing to:
00098       (+) Configure the source, destination address and data length and
00099           Start MultiBuffer DMA transfer
00100       (+) Configure the source, destination address and data length and
00101           Start MultiBuffer DMA transfer with interrupt
00102       (+) Change on the fly the memory0 or memory1 address.
00103
00104 @endverbatim
00105   * @{
00106   */
00107
00108
00109 /**
00110   * @brief  Starts the multi_buffer DMA Transfer.
00111   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
00112   *                     the configuration information for the specified DMA Stream.
00113   * @param  SrcAddress: The source memory Buffer address
00114   * @param  DstAddress: The destination memory Buffer address
00115   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00116   * @param  DataLength: The length of data to be transferred from source to destination
00117   * @retval HAL status
00118   */
00119 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00120 {
00121   /* Process Locked */
00122   __HAL_LOCK(hdma);
00123
00124   /* Current memory buffer used is Memory 0 */
00125   if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
00126   {
00127     hdma->State = HAL_DMA_STATE_BUSY_MEM0;
00128   }
00129   /* Current memory buffer used is Memory 1 */
00130   else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
00131   {
00132     hdma->State = HAL_DMA_STATE_BUSY_MEM1;
00133   }
00134
00135    /* Check the parameters */
00136   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00137
00138   /* Disable the peripheral */
00139   __HAL_DMA_DISABLE(hdma);
00140
00141   /* Enable the double buffer mode */
00142   hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
00143
00144   /* Configure DMA Stream destination address */
00145   hdma->Instance->M1AR = SecondMemAddress;
00146
00147   /* Configure the source, destination address and the data length */
00148   DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00149
00150   /* Enable the peripheral */
00151   __HAL_DMA_ENABLE(hdma);
00152
00153   return HAL_OK;
00154 }
00155
00156 /**
00157   * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
00158   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00159   *                     the configuration information for the specified DMA Stream.
00160   * @param  SrcAddress: The source memory Buffer address
00161   * @param  DstAddress: The destination memory Buffer address
00162   * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
00163   * @param  DataLength: The length of data to be transferred from source to destination
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
00167 {
00168   /* Process Locked */
00169   __HAL_LOCK(hdma);
00170
00171   /* Current memory buffer used is Memory 0 */
00172   if((hdma->Instance->CR & DMA_SxCR_CT) == 0U)
00173   {
00174     hdma->State = HAL_DMA_STATE_BUSY_MEM0;
00175   }
00176   /* Current memory buffer used is Memory 1 */
00177   else if((hdma->Instance->CR & DMA_SxCR_CT) != 0U)
00178   {
00179     hdma->State = HAL_DMA_STATE_BUSY_MEM1;
00180   }
00181
00182   /* Check the parameters */
00183   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00184
00185   /* Disable the peripheral */
00186   __HAL_DMA_DISABLE(hdma);
00187
00188   /* Enable the Double buffer mode */
00189   hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
00190
00191   /* Configure DMA Stream destination address */
00192   hdma->Instance->M1AR = SecondMemAddress;
00193
00194   /* Configure the source, destination address and the data length */
00195   DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
00196
00197   /* Enable the transfer complete interrupt */
00198   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
00199
00200   /* Enable the Half transfer interrupt */
00201   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
00202
00203   /* Enable the transfer Error interrupt */
00204   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
00205
00206   /* Enable the fifo Error interrupt */
00207   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
00208
00209   /* Enable the direct mode Error interrupt */
00210   __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
00211
00212   /* Enable the peripheral */
00213   __HAL_DMA_ENABLE(hdma);
00214
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  Change the memory0 or memory1 address on the fly.
00220   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00221   *                     the configuration information for the specified DMA Stream.
00222   * @param  Address:    The new address
00223   * @param  memory:     the memory to be changed, This parameter can be one of
00224   *                     the following values:
00225   *                      MEMORY0 /
00226   *                      MEMORY1
00227   * @note   The MEMORY0 address can be changed only when the current transfer use
00228   *         MEMORY1 and the MEMORY1 address can be changed only when the current
00229   *         transfer use MEMORY0.
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
00233 {
00234   if(memory == MEMORY0)
00235   {
00236     /* change the memory0 address */
00237     hdma->Instance->M0AR = Address;
00238   }
00239   else
00240   {
00241     /* change the memory1 address */
00242     hdma->Instance->M1AR = Address;
00243   }
00244
00245   return HAL_OK;
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252 /**
00253   * @}
00254   */
00255
00256 /** @addtogroup DMAEx_Private_Functions
00257   * @{
00258   */
00259
00260 /**
00261   * @brief  Set the DMA Transfer parameter.
00262   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00263   *                     the configuration information for the specified DMA Stream.
00264   * @param  SrcAddress: The source memory Buffer address
00265   * @param  DstAddress: The destination memory Buffer address
00266   * @param  DataLength: The length of data to be transferred from source to destination
00267   * @retval HAL status
00268   */
00269 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00270 {
00271   /* Configure DMA Stream data length */
00272   hdma->Instance->NDTR = DataLength;
00273
00274   /* Peripheral to Memory */
00275   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00276   {
00277     /* Configure DMA Stream destination address */
00278     hdma->Instance->PAR = DstAddress;
00279
00280     /* Configure DMA Stream source address */
00281     hdma->Instance->M0AR = SrcAddress;
00282   }
00283   /* Memory to Peripheral */
00284   else
00285   {
00286     /* Configure DMA Stream source address */
00287     hdma->Instance->PAR = SrcAddress;
00288
00289     /* Configure DMA Stream destination address */
00290     hdma->Instance->M0AR = DstAddress;
00291   }
00292 }
00293
00294 /**
00295   * @}
00296   */
00297
00298 #endif /* HAL_DMA_MODULE_ENABLED */
00299 /**
00300   * @}
00301   */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dma_ex.h Source File

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stm32f4xx_hal_dma_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DMA HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DMA_EX_H
00040 #define __STM32F4xx_HAL_DMA_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMAEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
00059   * @brief DMAEx Exported types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL DMA Memory definition
00065   */
00066 typedef enum
00067 {
00068   MEMORY0      = 0x00U,    /*!< Memory 0     */
00069   MEMORY1      = 0x01U    /*!< Memory 1     */
00070 }HAL_DMA_MemoryTypeDef;
00071
00072 /**
00073   * @}
00074   */
00075
00076 /* Exported functions --------------------------------------------------------*/
00077 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
00078   * @brief   DMAEx Exported functions
00079   * @{
00080   */
00081
00082 /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
00083   * @brief   Extended features functions
00084   * @{
00085   */
00086
00087 /* IO operation functions *******************************************************/
00088 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00089 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
00090 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
00091
00092 /**
00093   * @}
00094   */
00095 /**
00096   * @}
00097   */
00098
00099 /* Private functions ---------------------------------------------------------*/
00100 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
00101   * @brief DMAEx Private functions
00102   * @{
00103   */
00104 /**
00105   * @}
00106   */
00107
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 #ifdef __cplusplus
00117 }
00118 #endif
00119
00120 #endif /*__STM32F4xx_HAL_DMA_EX_H*/
00121
00122 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dsi.c Source File

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stm32f4xx_hal_dsi.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dsi.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   DSI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the DSI peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00018   *
00019   * Redistribution and use in source and binary forms, with or without modification,
00020   * are permitted provided that the following conditions are met:
00021   *   1. Redistributions of source code must retain the above copyright notice,
00022   *      this list of conditions and the following disclaimer.
00023   *   2. Redistributions in binary form must reproduce the above copyright notice,
00024   *      this list of conditions and the following disclaimer in the documentation
00025   *      and/or other materials provided with the distribution.
00026   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00027   *      may be used to endorse or promote products derived from this software
00028   *      without specific prior written permission.
00029   *
00030   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00031   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00032   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00033   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00034   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00035   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00036   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00037   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00038   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00039   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00040   *
00041   ******************************************************************************
00042   */
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f4xx_hal.h"
00046
00047 /** @addtogroup STM32F4xx_HAL_Driver
00048   * @{
00049   */
00050 /** @addtogroup DSI
00051   * @{
00052   */
00053
00054 #ifdef HAL_DSI_MODULE_ENABLED
00055
00056 #if defined(STM32F469xx) || defined(STM32F479xx)
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private defines -----------------------------------------------------------*/
00060 /** @addtogroup DSI_Private_Constants
00061   * @{
00062   */
00063 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U)  /* 1s */
00064
00065 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
00066                             DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
00067                             DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
00068                             DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
00069 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
00070 #define DSI_ERROR_TX_MASK  DSI_ISR1_TOHSTX
00071 #define DSI_ERROR_RX_MASK  DSI_ISR1_TOLPRX
00072 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
00073 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
00074 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
00075 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
00076 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
00077 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
00078 /**
00079   * @}
00080   */
00081
00082 /* Private variables ---------------------------------------------------------*/
00083 /* Private constants ---------------------------------------------------------*/
00084 /* Private macros ------------------------------------------------------------*/
00085 /* Private function prototypes -----------------------------------------------*/
00086 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
00087
00088 /* Private functions ---------------------------------------------------------*/
00089 /**
00090   * @brief  Generic DSI packet header configuration
00091   * @param  DSIx: Pointer to DSI register base
00092   * @param  ChannelID: Virtual channel ID of the header packet
00093   * @param  DataType: Packet data type of the header packet
00094   *                   This parameter can be any value of :
00095   *                      @ref DSI_SHORT_WRITE_PKT_Data_Type
00096   *                   or @ref DSI_LONG_WRITE_PKT_Data_Type
00097   *                   or @ref DSI_SHORT_READ_PKT_Data_Type
00098   *                   or DSI_MAX_RETURN_PKT_SIZE
00099   * @param  Data0: Word count LSB
00100   * @param  Data1: Word count MSB
00101   * @retval None
00102   */
00103 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
00104                                    uint32_t ChannelID,
00105                                    uint32_t DataType,
00106                                    uint32_t Data0,
00107                                    uint32_t Data1)
00108 {
00109   /* Update the DSI packet header with new information */
00110   DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U));
00111 }
00112
00113 /* Exported functions --------------------------------------------------------*/
00114 /** @addtogroup DSI_Exported_Functions
00115   * @{
00116   */
00117
00118 /** @defgroup DSI_Group1 Initialization and Configuration functions
00119  *  @brief   Initialization and Configuration functions
00120  *
00121 @verbatim
00122  ===============================================================================
00123                 ##### Initialization and Configuration functions #####
00124  ===============================================================================
00125     [..]  This section provides functions allowing to:
00126       (+) Initialize and configure the DSI
00127       (+) De-initialize the DSI
00128
00129 @endverbatim
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  Initializes the DSI according to the specified
00135   *         parameters in the DSI_InitTypeDef and create the associated handle.
00136   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00137   *               the configuration information for the DSI.
00138   * @param  PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
00139   *               the PLL Clock structure definition for the DSI.
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
00143 {
00144   uint32_t tickstart = 0U;
00145   uint32_t unitIntervalx4 = 0U;
00146   uint32_t tempIDF = 0U;
00147
00148   /* Check the DSI handle allocation */
00149   if(hdsi == NULL)
00150   {
00151     return HAL_ERROR;
00152   }
00153
00154   /* Check function parameters */
00155   assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
00156   assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
00157   assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
00158   assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
00159   assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
00160
00161   if(hdsi->State == HAL_DSI_STATE_RESET)
00162   {
00163     /* Initialize the low level hardware */
00164     HAL_DSI_MspInit(hdsi);
00165   }
00166
00167   /* Change DSI peripheral state */
00168   hdsi->State = HAL_DSI_STATE_BUSY;
00169
00170   /**************** Turn on the regulator and enable the DSI PLL ****************/
00171
00172     /* Enable the regulator */
00173     __HAL_DSI_REG_ENABLE(hdsi);
00174
00175         /* Get tick */
00176     tickstart = HAL_GetTick();
00177
00178     /* Wait until the regulator is ready */
00179         while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
00180     {
00181       /* Check for the Timeout */
00182       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
00183       {
00184         return HAL_TIMEOUT;
00185       }
00186     }
00187
00188     /* Set the PLL division factors */
00189     hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
00190     hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
00191
00192     /* Enable the DSI PLL */
00193     __HAL_DSI_PLL_ENABLE(hdsi);
00194
00195         /* Get tick */
00196     tickstart = HAL_GetTick();
00197
00198     /* Wait for the lock of the PLL */
00199     while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
00200     {
00201       /* Check for the Timeout */
00202       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
00203       {
00204         return HAL_TIMEOUT;
00205       }
00206     }
00207
00208   /*************************** Set the PHY parameters ***************************/
00209
00210     /* D-PHY clock and digital enable*/
00211     hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
00212
00213     /* Clock lane configuration */
00214     hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
00215     hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
00216
00217     /* Configure the number of active data lanes */
00218     hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
00219     hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
00220
00221   /************************ Set the DSI clock parameters ************************/
00222
00223     /* Set the TX escape clock division factor */
00224     hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
00225     hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;
00226
00227     /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
00228     /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 )          */
00229     /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF)                    */
00230     tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
00231     unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
00232
00233     /* Set the bit period in high-speed mode */
00234     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
00235     hdsi->Instance->WPCR[0U] |= unitIntervalx4;
00236
00237   /****************************** Error management *****************************/
00238
00239     /* Disable all error interrupts and reset the Error Mask */
00240     hdsi->Instance->IER[0U] = 0U;
00241     hdsi->Instance->IER[1U] = 0U;
00242     hdsi->ErrorMsk = 0U;
00243
00244     /* Initialise the error code */
00245     hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
00246
00247   /* Initialize the DSI state*/
00248   hdsi->State = HAL_DSI_STATE_READY;
00249
00250   return HAL_OK;
00251 }
00252
00253 /**
00254   * @brief  De-initializes the DSI peripheral registers to their default reset
00255   *         values.
00256   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00257   *               the configuration information for the DSI.
00258   * @retval HAL status
00259   */
00260 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
00261 {
00262   /* Check the DSI handle allocation */
00263   if(hdsi == NULL)
00264   {
00265     return HAL_ERROR;
00266   }
00267
00268   /* Change DSI peripheral state */
00269   hdsi->State = HAL_DSI_STATE_BUSY;
00270
00271   /* Disable the DSI wrapper */
00272   __HAL_DSI_WRAPPER_DISABLE(hdsi);
00273
00274   /* Disable the DSI host */
00275   __HAL_DSI_DISABLE(hdsi);
00276
00277   /* D-PHY clock and digital disable */
00278   hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
00279
00280   /* Turn off the DSI PLL */
00281   __HAL_DSI_PLL_DISABLE(hdsi);
00282
00283   /* Disable the regulator */
00284   __HAL_DSI_REG_DISABLE(hdsi);
00285
00286   /* DeInit the low level hardware */
00287   HAL_DSI_MspDeInit(hdsi);
00288
00289   /* Initialise the error code */
00290   hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
00291
00292   /* Initialize the DSI state*/
00293   hdsi->State = HAL_DSI_STATE_RESET;
00294
00295   /* Release Lock */
00296   __HAL_UNLOCK(hdsi);
00297
00298   return HAL_OK;
00299 }
00300
00301 /**
00302   * @brief  Return the DSI error code
00303   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00304   *               the configuration information for the DSI.
00305   * @retval DSI Error Code
00306   */
00307 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
00308 {
00309   /* Get the error code */
00310   return hdsi->ErrorCode;
00311 }
00312
00313 /**
00314   * @brief  Enable the error monitor flags
00315   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00316   *               the configuration information for the DSI.
00317   * @param  ActiveErrors: indicates which error interrupts will be enabled.
00318   *                      This parameter can be any combination of @ref DSI_Error_Data_Type.
00319   * @retval HAL status
00320   */
00321 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
00322 {
00323   /* Process locked */
00324   __HAL_LOCK(hdsi);
00325
00326   hdsi->Instance->IER[0U] = 0U;
00327   hdsi->Instance->IER[1U] = 0U;
00328
00329   /* Store active errors to the handle */
00330   hdsi->ErrorMsk = ActiveErrors;
00331
00332   if(ActiveErrors & HAL_DSI_ERROR_ACK)
00333   {
00334     /* Enable the interrupt generation on selected errors */
00335     hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
00336   }
00337
00338   if(ActiveErrors & HAL_DSI_ERROR_PHY)
00339   {
00340     /* Enable the interrupt generation on selected errors */
00341     hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
00342   }
00343
00344   if(ActiveErrors & HAL_DSI_ERROR_TX)
00345   {
00346     /* Enable the interrupt generation on selected errors */
00347     hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
00348   }
00349
00350   if(ActiveErrors & HAL_DSI_ERROR_RX)
00351   {
00352     /* Enable the interrupt generation on selected errors */
00353     hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
00354   }
00355
00356   if(ActiveErrors & HAL_DSI_ERROR_ECC)
00357   {
00358     /* Enable the interrupt generation on selected errors */
00359     hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
00360   }
00361
00362   if(ActiveErrors & HAL_DSI_ERROR_CRC)
00363   {
00364     /* Enable the interrupt generation on selected errors */
00365     hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
00366   }
00367
00368   if(ActiveErrors & HAL_DSI_ERROR_PSE)
00369   {
00370     /* Enable the interrupt generation on selected errors */
00371     hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
00372   }
00373
00374   if(ActiveErrors & HAL_DSI_ERROR_EOT)
00375   {
00376     /* Enable the interrupt generation on selected errors */
00377     hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
00378   }
00379
00380   if(ActiveErrors & HAL_DSI_ERROR_OVF)
00381   {
00382     /* Enable the interrupt generation on selected errors */
00383     hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
00384   }
00385
00386   if(ActiveErrors & HAL_DSI_ERROR_GEN)
00387   {
00388     /* Enable the interrupt generation on selected errors */
00389     hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
00390   }
00391
00392   /* Process Unlocked */
00393   __HAL_UNLOCK(hdsi);
00394
00395   return HAL_OK;
00396 }
00397
00398 /**
00399   * @brief  Initializes the DSI MSP.
00400   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00401   *               the configuration information for the DSI.
00402   * @retval None
00403   */
00404 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
00405 {
00406   /* Prevent unused argument(s) compilation warning */
00407   UNUSED(hdsi);
00408   /* NOTE : This function Should not be modified, when the callback is needed,
00409             the HAL_DSI_MspInit could be implemented in the user file
00410    */
00411 }
00412
00413 /**
00414   * @brief  De-initializes the DSI MSP.
00415   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00416   *               the configuration information for the DSI.
00417   * @retval None
00418   */
00419 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
00420 {
00421   /* Prevent unused argument(s) compilation warning */
00422   UNUSED(hdsi);
00423   /* NOTE : This function Should not be modified, when the callback is needed,
00424             the HAL_DSI_MspDeInit could be implemented in the user file
00425    */
00426 }
00427
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup DSI_Group2 IO operation functions
00433  *  @brief    IO operation functions
00434  *
00435 @verbatim
00436  ===============================================================================
00437                       #####  IO operation functions  #####
00438  ===============================================================================
00439     [..]  This section provides function allowing to:
00440       (+) Handle DSI interrupt request
00441
00442 @endverbatim
00443   * @{
00444   */
00445 /**
00446   * @brief  Handles DSI interrupt request.
00447   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00448   *               the configuration information for the DSI.
00449   * @retval HAL status
00450   */
00451 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
00452 {
00453   uint32_t ErrorStatus0, ErrorStatus1;
00454
00455   /* Tearing Effect Interrupt management ***************************************/
00456   if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
00457   {
00458     if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
00459     {
00460       /* Clear the Tearing Effect Interrupt Flag */
00461       __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
00462
00463       /* Tearing Effect Callback */
00464       HAL_DSI_TearingEffectCallback(hdsi);
00465     }
00466   }
00467
00468   /* End of Refresh Interrupt management ***************************************/
00469   if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
00470   {
00471     if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
00472     {
00473       /* Clear the End of Refresh Interrupt Flag */
00474       __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
00475
00476       /* End of Refresh Callback */
00477       HAL_DSI_EndOfRefreshCallback(hdsi);
00478     }
00479   }
00480
00481   /* Error Interrupts management ***********************************************/
00482   if(hdsi->ErrorMsk != 0U)
00483   {
00484     ErrorStatus0 = hdsi->Instance->ISR[0U];
00485     ErrorStatus0 &= hdsi->Instance->IER[0U];
00486     ErrorStatus1 = hdsi->Instance->ISR[1U];
00487     ErrorStatus1 &= hdsi->Instance->IER[1U];
00488
00489     if(ErrorStatus0 & DSI_ERROR_ACK_MASK)
00490     {
00491       hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
00492     }
00493
00494     if(ErrorStatus0 & DSI_ERROR_PHY_MASK)
00495     {
00496       hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
00497     }
00498
00499     if(ErrorStatus1 & DSI_ERROR_TX_MASK)
00500     {
00501       hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
00502     }
00503
00504     if(ErrorStatus1 & DSI_ERROR_RX_MASK)
00505     {
00506       hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
00507     }
00508
00509     if(ErrorStatus1 & DSI_ERROR_ECC_MASK)
00510     {
00511       hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
00512     }
00513
00514     if(ErrorStatus1 & DSI_ERROR_CRC_MASK)
00515     {
00516       hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
00517     }
00518
00519     if(ErrorStatus1 & DSI_ERROR_PSE_MASK)
00520     {
00521       hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
00522     }
00523
00524     if(ErrorStatus1 & DSI_ERROR_EOT_MASK)
00525     {
00526       hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
00527     }
00528
00529     if(ErrorStatus1 & DSI_ERROR_OVF_MASK)
00530     {
00531       hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
00532     }
00533
00534     if(ErrorStatus1 & DSI_ERROR_GEN_MASK)
00535     {
00536       hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
00537     }
00538
00539     /* Check only selected errors */
00540     if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
00541     {
00542       /* DSI error interrupt user callback */
00543       HAL_DSI_ErrorCallback(hdsi);
00544     }
00545   }
00546 }
00547
00548 /**
00549   * @brief  Tearing Effect DSI callback.
00550   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00551   *               the configuration information for the DSI.
00552   * @retval None
00553   */
00554 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
00555 {
00556   /* Prevent unused argument(s) compilation warning */
00557   UNUSED(hdsi);
00558   /* NOTE : This function Should not be modified, when the callback is needed,
00559             the HAL_DSI_TearingEffectCallback could be implemented in the user file
00560    */
00561 }
00562
00563 /**
00564   * @brief  End of Refresh DSI callback.
00565   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00566   *               the configuration information for the DSI.
00567   * @retval None
00568   */
00569 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
00570 {
00571   /* Prevent unused argument(s) compilation warning */
00572   UNUSED(hdsi);
00573   /* NOTE : This function Should not be modified, when the callback is needed,
00574             the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
00575    */
00576 }
00577
00578 /**
00579   * @brief  Operation Error DSI callback.
00580   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00581   *               the configuration information for the DSI.
00582   * @retval None
00583   */
00584 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
00585 {
00586   /* Prevent unused argument(s) compilation warning */
00587   UNUSED(hdsi);
00588   /* NOTE : This function Should not be modified, when the callback is needed,
00589             the HAL_DSI_ErrorCallback could be implemented in the user file
00590    */
00591 }
00592
00593 /**
00594   * @}
00595   */
00596
00597 /** @defgroup DSI_Group3 Peripheral Control functions
00598  *  @brief    Peripheral Control functions
00599  *
00600 @verbatim
00601  ===============================================================================
00602                     ##### Peripheral Control functions #####
00603  ===============================================================================
00604     [..]  This section provides functions allowing to:
00605       (+)
00606       (+)
00607       (+)
00608
00609 @endverbatim
00610   * @{
00611   */
00612
00613 /**
00614   * @brief  Configure the Generic interface read-back Virtual Channel ID.
00615   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00616   *               the configuration information for the DSI.
00617   * @param  VirtualChannelID: Virtual channel ID
00618   * @retval HAL status
00619   */
00620 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
00621 {
00622   /* Process locked */
00623   __HAL_LOCK(hdsi);
00624
00625   /* Update the GVCID register */
00626   hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
00627   hdsi->Instance->GVCIDR |= VirtualChannelID;
00628
00629   /* Process unlocked */
00630   __HAL_UNLOCK(hdsi);
00631
00632   return HAL_OK;
00633 }
00634
00635 /**
00636   * @brief  Select video mode and configure the corresponding parameters
00637   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00638   *               the configuration information for the DSI.
00639   * @param  VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
00640   *                 the DSI video mode configuration parameters
00641   * @retval HAL status
00642   */
00643 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
00644 {
00645   /* Process locked */
00646   __HAL_LOCK(hdsi);
00647
00648   /* Check the parameters */
00649   assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
00650   assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
00651   assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
00652   assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
00653   assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
00654   assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
00655   assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
00656   assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
00657   assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
00658   assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
00659   assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
00660   assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
00661   assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
00662   /* Check the LooselyPacked variant only in 18-bit mode */
00663   if(VidCfg->ColorCoding == DSI_RGB666)
00664   {
00665     assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
00666   }
00667
00668   /* Select video mode by resetting CMDM and DSIM bits */
00669   hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
00670   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
00671
00672   /* Configure the video mode transmission type */
00673   hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
00674   hdsi->Instance->VMCR |= VidCfg->Mode;
00675
00676   /* Configure the video packet size */
00677   hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
00678   hdsi->Instance->VPCR |= VidCfg->PacketSize;
00679
00680   /* Set the chunks number to be transmitted through the DSI link */
00681   hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
00682   hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
00683
00684   /* Set the size of the null packet */
00685   hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
00686   hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
00687
00688   /* Select the virtual channel for the LTDC interface traffic */
00689   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
00690   hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
00691
00692   /* Configure the polarity of control signals */
00693   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
00694   hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
00695
00696   /* Select the color coding for the host */
00697   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
00698   hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
00699
00700   /* Select the color coding for the wrapper */
00701   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
00702   hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
00703
00704   /* Enable/disable the loosely packed variant to 18-bit configuration */
00705   if(VidCfg->ColorCoding == DSI_RGB666)
00706   {
00707     hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
00708     hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
00709   }
00710
00711   /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
00712   hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
00713   hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
00714
00715   /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
00716   hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
00717   hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
00718
00719   /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
00720   hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
00721   hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
00722
00723   /* Set the Vertical Synchronization Active (VSA) */
00724   hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
00725   hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
00726
00727   /* Set the Vertical Back Porch (VBP)*/
00728   hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
00729   hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
00730
00731   /* Set the Vertical Front Porch (VFP)*/
00732   hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
00733   hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
00734
00735   /* Set the Vertical Active period*/
00736   hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
00737   hdsi->Instance->VVACR |= VidCfg->VerticalActive;
00738
00739   /* Configure the command transmission mode */
00740   hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
00741   hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
00742
00743   /* Low power largest packet size */
00744   hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
00745   hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
00746
00747   /* Low power VACT largest packet size */
00748   hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
00749   hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
00750
00751   /* Enable LP transition in HFP period */
00752   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
00753   hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
00754
00755   /* Enable LP transition in HBP period */
00756   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
00757   hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
00758
00759   /* Enable LP transition in VACT period */
00760   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
00761   hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
00762
00763   /* Enable LP transition in VFP period */
00764   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
00765   hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
00766
00767   /* Enable LP transition in VBP period */
00768   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
00769   hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
00770
00771   /* Enable LP transition in vertical sync period */
00772   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
00773   hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
00774
00775   /* Enable the request for an acknowledge response at the end of a frame */
00776   hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
00777   hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
00778
00779   /* Process unlocked */
00780   __HAL_UNLOCK(hdsi);
00781
00782   return HAL_OK;
00783 }
00784
00785 /**
00786   * @brief  Select adapted command mode and configure the corresponding parameters
00787   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00788   *               the configuration information for the DSI.
00789   * @param  CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
00790   *                 the DSI command mode configuration parameters
00791   * @retval HAL status
00792   */
00793 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
00794 {
00795   /* Process locked */
00796   __HAL_LOCK(hdsi);
00797
00798   /* Check the parameters */
00799   assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
00800   assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
00801   assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
00802   assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
00803   assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
00804   assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
00805   assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
00806   assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
00807   assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
00808
00809   /* Select command mode by setting CMDM and DSIM bits */
00810   hdsi->Instance->MCR |= DSI_MCR_CMDM;
00811   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
00812   hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
00813
00814   /* Select the virtual channel for the LTDC interface traffic */
00815   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
00816   hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
00817
00818   /* Configure the polarity of control signals */
00819   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
00820   hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
00821
00822   /* Select the color coding for the host */
00823   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
00824   hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
00825
00826   /* Select the color coding for the wrapper */
00827   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
00828   hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
00829
00830   /* Configure the maximum allowed size for write memory command */
00831   hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
00832   hdsi->Instance->LCCR |= CmdCfg->CommandSize;
00833
00834   /* Configure the tearing effect source and polarity and select the refresh mode */
00835   hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
00836   hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
00837
00838   /* Configure the tearing effect acknowledge request */
00839   hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
00840   hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
00841
00842   /* Enable the Tearing Effect interrupt */
00843   __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
00844
00845   /* Enable the End of Refresh interrupt */
00846   __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
00847
00848   /* Process unlocked */
00849   __HAL_UNLOCK(hdsi);
00850
00851   return HAL_OK;
00852 }
00853
00854 /**
00855   * @brief  Configure command transmission mode: High-speed or Low-power
00856   *         and enable/disable acknowledge request after packet transmission
00857   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00858   *               the configuration information for the DSI.
00859   * @param  LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
00860   *                the DSI command transmission mode configuration parameters
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
00864 {
00865   /* Process locked */
00866   __HAL_LOCK(hdsi);
00867
00868   assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
00869   assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
00870   assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
00871   assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
00872   assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
00873   assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
00874   assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
00875   assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
00876   assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
00877   assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
00878   assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
00879   assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
00880   assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
00881
00882   /* Select High-speed or Low-power for command transmission */
00883   hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
00884                             DSI_CMCR_GSW1TX |\
00885                             DSI_CMCR_GSW2TX |\
00886                             DSI_CMCR_GSR0TX |\
00887                             DSI_CMCR_GSR1TX |\
00888                             DSI_CMCR_GSR2TX |\
00889                             DSI_CMCR_GLWTX  |\
00890                             DSI_CMCR_DSW0TX |\
00891                             DSI_CMCR_DSW1TX |\
00892                             DSI_CMCR_DSR0TX |\
00893                             DSI_CMCR_DLWTX  |\
00894                             DSI_CMCR_MRDPS);
00895   hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP  |\
00896                            LPCmd->LPGenShortWriteOneP |\
00897                            LPCmd->LPGenShortWriteTwoP |\
00898                            LPCmd->LPGenShortReadNoP   |\
00899                            LPCmd->LPGenShortReadOneP  |\
00900                            LPCmd->LPGenShortReadTwoP  |\
00901                            LPCmd->LPGenLongWrite      |\
00902                            LPCmd->LPDcsShortWriteNoP  |\
00903                            LPCmd->LPDcsShortWriteOneP |\
00904                            LPCmd->LPDcsShortReadNoP   |\
00905                            LPCmd->LPDcsLongWrite      |\
00906                            LPCmd->LPMaxReadPacket);
00907
00908   /* Configure the acknowledge request after each packet transmission */
00909   hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
00910   hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
00911
00912   /* Process unlocked */
00913   __HAL_UNLOCK(hdsi);
00914
00915   return HAL_OK;
00916 }
00917
00918 /**
00919   * @brief  Configure the flow control parameters
00920   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00921   *               the configuration information for the DSI.
00922   * @param  FlowControl: flow control feature(s) to be enabled.
00923   *                      This parameter can be any combination of @ref DSI_FlowControl.
00924   * @retval HAL status
00925   */
00926 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
00927 {
00928   /* Process locked */
00929   __HAL_LOCK(hdsi);
00930
00931   /* Check the parameters */
00932   assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
00933
00934   /* Set the DSI Host Protocol Configuration Register */
00935   hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
00936   hdsi->Instance->PCR |= FlowControl;
00937
00938   /* Process unlocked */
00939   __HAL_UNLOCK(hdsi);
00940
00941   return HAL_OK;
00942 }
00943
00944 /**
00945   * @brief  Configure the DSI PHY timer parameters
00946   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00947   *               the configuration information for the DSI.
00948   * @param  PhyTimers: DSI_PHY_TimerTypeDef structure that contains
00949   *                    the DSI PHY timing parameters
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
00953 {
00954   uint32_t maxTime;
00955   /* Process locked */
00956   __HAL_LOCK(hdsi);
00957
00958   maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
00959
00960   /* Clock lane timer configuration */
00961
00962   /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
00963      High-Speed transmission.
00964      To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
00965      to Low-Power and from Low-Power to High-Speed.
00966      This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
00967      But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
00968
00969      Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
00970   */
00971   hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
00972   hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
00973
00974   /* Data lane timer configuration */
00975   hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
00976   hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
00977
00978   /* Configure the wait period to request HS transmission after a stop state */
00979   hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
00980   hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
00981
00982   /* Process unlocked */
00983   __HAL_UNLOCK(hdsi);
00984
00985   return HAL_OK;
00986 }
00987
00988 /**
00989   * @brief  Configure the DSI HOST timeout parameters
00990   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
00991   *               the configuration information for the DSI.
00992   * @param  HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
00993   *                       the DSI host timeout parameters
00994   * @retval HAL status
00995   */
00996 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
00997 {
00998   /* Process locked */
00999   __HAL_LOCK(hdsi);
01000
01001   /* Set the timeout clock division factor */
01002   hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
01003   hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8U);
01004
01005   /* High-speed transmission timeout */
01006   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
01007   hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
01008
01009   /* Low-power reception timeout */
01010   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
01011   hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
01012
01013   /* High-speed read timeout */
01014   hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
01015   hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
01016
01017   /* Low-power read timeout */
01018   hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
01019   hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
01020
01021   /* High-speed write timeout */
01022   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
01023   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
01024
01025   /* High-speed write presp mode */
01026   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
01027   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
01028
01029   /* Low-speed write timeout */
01030   hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
01031   hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
01032
01033   /* BTA timeout */
01034   hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
01035   hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
01036
01037   /* Process unlocked */
01038   __HAL_UNLOCK(hdsi);
01039
01040   return HAL_OK;
01041 }
01042
01043 /**
01044   * @brief  Start the DSI module
01045   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01046   *               the configuration information for the DSI.
01047   * @retval HAL status
01048   */
01049 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
01050 {
01051   /* Process locked */
01052   __HAL_LOCK(hdsi);
01053
01054   /* Enable the DSI host */
01055   __HAL_DSI_ENABLE(hdsi);
01056
01057   /* Enable the DSI wrapper */
01058   __HAL_DSI_WRAPPER_ENABLE(hdsi);
01059
01060   /* Process unlocked */
01061   __HAL_UNLOCK(hdsi);
01062
01063   return HAL_OK;
01064 }
01065
01066 /**
01067   * @brief  Stop the DSI module
01068   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01069   *               the configuration information for the DSI.
01070   * @retval HAL status
01071   */
01072 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
01073 {
01074   /* Process locked */
01075   __HAL_LOCK(hdsi);
01076
01077   /* Disable the DSI host */
01078   __HAL_DSI_DISABLE(hdsi);
01079
01080   /* Disable the DSI wrapper */
01081   __HAL_DSI_WRAPPER_DISABLE(hdsi);
01082
01083   /* Process unlocked */
01084   __HAL_UNLOCK(hdsi);
01085
01086   return HAL_OK;
01087 }
01088
01089 /**
01090   * @brief  Refresh the display in command mode
01091   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01092   *               the configuration information for the DSI.
01093   * @retval HAL status
01094   */
01095 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
01096 {
01097   /* Process locked */
01098   __HAL_LOCK(hdsi);
01099
01100   /* Update the display */
01101   hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
01102
01103   /* Process unlocked */
01104   __HAL_UNLOCK(hdsi);
01105
01106   return HAL_OK;
01107 }
01108
01109 /**
01110   * @brief  Controls the display color mode in Video mode
01111   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01112   *               the configuration information for the DSI.
01113   * @param  ColorMode: Color mode (full or 8-colors).
01114   *                    This parameter can be any value of @ref DSI_Color_Mode
01115   * @retval HAL status
01116   */
01117 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
01118 {
01119   /* Process locked */
01120   __HAL_LOCK(hdsi);
01121
01122   /* Check the parameters */
01123   assert_param(IS_DSI_COLOR_MODE(ColorMode));
01124
01125   /* Update the display color mode */
01126   hdsi->Instance->WCR &= ~DSI_WCR_COLM;
01127   hdsi->Instance->WCR |= ColorMode;
01128
01129   /* Process unlocked */
01130   __HAL_UNLOCK(hdsi);
01131
01132   return HAL_OK;
01133 }
01134
01135 /**
01136   * @brief  Control the display shutdown in Video mode
01137   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01138   *               the configuration information for the DSI.
01139   * @param  Shutdown: Shut-down (Display-ON or Display-OFF).
01140   *                   This parameter can be any value of @ref DSI_ShutDown
01141   * @retval HAL status
01142   */
01143 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
01144 {
01145   /* Process locked */
01146   __HAL_LOCK(hdsi);
01147
01148   /* Check the parameters */
01149   assert_param(IS_DSI_SHUT_DOWN(Shutdown));
01150
01151   /* Update the display Shutdown */
01152   hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
01153   hdsi->Instance->WCR |= Shutdown;
01154
01155   /* Process unlocked */
01156   __HAL_UNLOCK(hdsi);
01157
01158   return HAL_OK;
01159 }
01160
01161 /**
01162   * @brief  DCS or Generic short write command
01163   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01164   *               the configuration information for the DSI.
01165   * @param  ChannelID: Virtual channel ID.
01166   * @param  Mode: DSI short packet data type.
01167   *               This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
01168   * @param  Param1: DSC command or first generic parameter.
01169   *                 This parameter can be any value of @ref DSI_DCS_Command or a
01170   *                 generic command code.
01171   * @param  Param2: DSC parameter or second generic parameter.
01172   * @retval HAL status
01173   */
01174 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
01175                                      uint32_t ChannelID,
01176                                      uint32_t Mode,
01177                                      uint32_t Param1,
01178                                      uint32_t Param2)
01179 {
01180   uint32_t tickstart = 0U;
01181
01182   /* Process locked */
01183   __HAL_LOCK(hdsi);
01184
01185   /* Check the parameters */
01186   assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
01187
01188   /* Get tick */
01189   tickstart = HAL_GetTick();
01190
01191   /* Wait for Command FIFO Empty */
01192   while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
01193   {
01194     /* Check for the Timeout */
01195     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01196     {
01197       /* Process Unlocked */
01198       __HAL_UNLOCK(hdsi);
01199
01200       return HAL_TIMEOUT;
01201     }
01202   }
01203
01204   /* Configure the packet to send a short DCS command with 0 or 1 parameter */
01205   DSI_ConfigPacketHeader(hdsi->Instance,
01206                          ChannelID,
01207                          Mode,
01208                          Param1,
01209                          Param2);
01210
01211   /* Process unlocked */
01212   __HAL_UNLOCK(hdsi);
01213
01214   return HAL_OK;
01215 }
01216
01217 /**
01218   * @brief  DCS or Generic long write command
01219   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01220   *               the configuration information for the DSI.
01221   * @param  ChannelID: Virtual channel ID.
01222   * @param  Mode: DSI long packet data type.
01223   *               This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
01224   * @param  NbParams: Number of parameters.
01225   * @param  Param1: DSC command or first generic parameter.
01226   *                 This parameter can be any value of @ref DSI_DCS_Command or a
01227   *                 generic command code
01228   * @param  ParametersTable: Pointer to parameter values table.
01229   * @retval HAL status
01230   */
01231 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
01232                                     uint32_t ChannelID,
01233                                     uint32_t Mode,
01234                                     uint32_t NbParams,
01235                                     uint32_t Param1,
01236                                     uint8_t* ParametersTable)
01237 {
01238   uint32_t uicounter = 0U;
01239   uint32_t tickstart = 0U;
01240
01241   /* Process locked */
01242   __HAL_LOCK(hdsi);
01243
01244   /* Check the parameters */
01245   assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
01246
01247   /* Get tick */
01248   tickstart = HAL_GetTick();
01249
01250   /* Wait for Command FIFO Empty */
01251   while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
01252   {
01253     /* Check for the Timeout */
01254     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01255     {
01256       /* Process Unlocked */
01257       __HAL_UNLOCK(hdsi);
01258
01259       return HAL_TIMEOUT;
01260     }
01261   }
01262
01263   /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
01264   while(uicounter < NbParams)
01265   {
01266     if(uicounter == 0x00U)
01267     {
01268       hdsi->Instance->GPDR=(Param1 | \
01269                             ((*(ParametersTable+uicounter))<<8U) | \
01270                             ((*(ParametersTable+uicounter+1U))<<16U) | \
01271                             ((*(ParametersTable+uicounter+2U))<<24U));
01272       uicounter += 3U;
01273     }
01274     else
01275     {
01276       hdsi->Instance->GPDR=((*(ParametersTable+uicounter)) | \
01277                             ((*(ParametersTable+uicounter+1U))<<8U) | \
01278                             ((*(ParametersTable+uicounter+2U))<<16U) | \
01279                             ((*(ParametersTable+uicounter+3U))<<24U));
01280       uicounter+=4U;
01281     }
01282   }
01283
01284   /* Configure the packet to send a long DCS command */
01285   DSI_ConfigPacketHeader(hdsi->Instance,
01286                          ChannelID,
01287                          Mode,
01288                          ((NbParams+1U)&0x00FFU),
01289                          (((NbParams+1U)&0xFF00U)>>8U));
01290
01291   /* Process unlocked */
01292   __HAL_UNLOCK(hdsi);
01293
01294   return HAL_OK;
01295 }
01296
01297 /**
01298   * @brief  Read command (DCS or generic)
01299   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01300   *               the configuration information for the DSI.
01301   * @param  ChannelNbr: Virtual channel ID
01302   * @param  Array: pointer to a buffer to store the payload of a read back operation.
01303   * @param  Size: Data size to be read (in byte).
01304   * @param  Mode: DSI read packet data type.
01305   *               This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
01306   * @param  DCSCmd: DCS get/read command.
01307   * @param  ParametersTable: Pointer to parameter values table.
01308   * @retval HAL status
01309   */
01310 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
01311                                uint32_t ChannelNbr,
01312                                uint8_t* Array,
01313                                uint32_t Size,
01314                                uint32_t Mode,
01315                                uint32_t DCSCmd,
01316                                uint8_t* ParametersTable)
01317 {
01318   uint32_t tickstart = 0U;
01319
01320   /* Process locked */
01321   __HAL_LOCK(hdsi);
01322
01323   /* Check the parameters */
01324   assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
01325
01326   if(Size > 2U)
01327   {
01328     /* set max return packet size */
01329     HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFFU), (((Size)>>8U)&0xFFU));
01330   }
01331
01332   /* Configure the packet to read command */
01333   if (Mode == DSI_DCS_SHORT_PKT_READ)
01334   {
01335     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
01336   }
01337   else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
01338   {
01339     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
01340   }
01341   else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
01342   {
01343     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
01344   }
01345   else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
01346   {
01347     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
01348   }
01349
01350   /* Get tick */
01351   tickstart = HAL_GetTick();
01352
01353   /* Check that the payload read FIFO is not empty */
01354   while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
01355   {
01356     /* Check for the Timeout */
01357     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01358     {
01359       /* Process Unlocked */
01360       __HAL_UNLOCK(hdsi);
01361
01362       return HAL_TIMEOUT;
01363     }
01364   }
01365
01366   /* Get the first byte */
01367   *((uint32_t *)Array) = (hdsi->Instance->GPDR);
01368   if (Size > 4U)
01369   {
01370     Size -= 4U;
01371     Array += 4U;
01372   }
01373   else
01374   {
01375     /* Process unlocked */
01376     __HAL_UNLOCK(hdsi);
01377
01378     return HAL_OK;
01379   }
01380
01381   /* Get tick */
01382   tickstart = HAL_GetTick();
01383
01384   /* Get the remaining bytes if any */
01385   while(((int)(Size)) > 0U)
01386   {
01387     if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
01388     {
01389       *((uint32_t *)Array) = (hdsi->Instance->GPDR);
01390       Size -= 4U;
01391       Array += 4U;
01392     }
01393
01394     /* Check for the Timeout */
01395     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01396     {
01397       /* Process Unlocked */
01398       __HAL_UNLOCK(hdsi);
01399
01400       return HAL_TIMEOUT;
01401     }
01402   }
01403
01404   /* Process unlocked */
01405   __HAL_UNLOCK(hdsi);
01406
01407   return HAL_OK;
01408 }
01409
01410 /**
01411   * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
01412   *         (only data lanes are in ULPM)
01413   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01414   *               the configuration information for the DSI.
01415   * @retval HAL status
01416   */
01417 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
01418 {
01419   uint32_t tickstart = 0U;
01420
01421   /* Process locked */
01422   __HAL_LOCK(hdsi);
01423
01424   /* ULPS Request on Data Lanes */
01425   hdsi->Instance->PUCR |= DSI_PUCR_URDL;
01426
01427   /* Get tick */
01428   tickstart = HAL_GetTick();
01429
01430   /* Wait until the D-PHY active lanes enter into ULPM */
01431   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
01432   {
01433         while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
01434     {
01435       /* Check for the Timeout */
01436       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01437       {
01438         /* Process Unlocked */
01439         __HAL_UNLOCK(hdsi);
01440
01441         return HAL_TIMEOUT;
01442       }
01443     }
01444   }
01445   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
01446   {
01447         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
01448     {
01449       /* Check for the Timeout */
01450       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01451       {
01452         /* Process Unlocked */
01453         __HAL_UNLOCK(hdsi);
01454
01455         return HAL_TIMEOUT;
01456       }
01457     }
01458   }
01459
01460   /* Process unlocked */
01461   __HAL_UNLOCK(hdsi);
01462
01463   return HAL_OK;
01464 }
01465
01466 /**
01467   * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
01468   *         (only data lanes are in ULPM)
01469   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01470   *               the configuration information for the DSI.
01471   * @retval HAL status
01472   */
01473 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
01474 {
01475   uint32_t tickstart = 0U;
01476
01477   /* Process locked */
01478   __HAL_LOCK(hdsi);
01479
01480   /* Exit ULPS on Data Lanes */
01481   hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
01482
01483   /* Get tick */
01484   tickstart = HAL_GetTick();
01485
01486   /* Wait until all active lanes exit ULPM */
01487   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
01488   {
01489         while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
01490     {
01491       /* Check for the Timeout */
01492       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01493       {
01494         /* Process Unlocked */
01495         __HAL_UNLOCK(hdsi);
01496
01497         return HAL_TIMEOUT;
01498       }
01499     }
01500   }
01501   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
01502   {
01503         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
01504     {
01505       /* Check for the Timeout */
01506       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01507       {
01508         /* Process Unlocked */
01509         __HAL_UNLOCK(hdsi);
01510
01511         return HAL_TIMEOUT;
01512       }
01513     }
01514   }
01515
01516   /* De-assert the ULPM requests and the ULPM exit bits */
01517   hdsi->Instance->PUCR = 0U;
01518
01519   /* Process unlocked */
01520   __HAL_UNLOCK(hdsi);
01521
01522   return HAL_OK;
01523 }
01524
01525 /**
01526   * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
01527   *         (both data and clock lanes are in ULPM)
01528   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01529   *               the configuration information for the DSI.
01530   * @retval HAL status
01531   */
01532 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
01533 {
01534   uint32_t tickstart = 0U;
01535
01536   /* Process locked */
01537   __HAL_LOCK(hdsi);
01538
01539   /* Clock lane configuration: no more HS request */
01540   hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
01541
01542   /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
01543   __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
01544
01545   /* ULPS Request on Clock and Data Lanes */
01546   hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
01547
01548   /* Get tick */
01549   tickstart = HAL_GetTick();
01550
01551   /* Wait until all active lanes exit ULPM */
01552   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
01553   {
01554         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
01555     {
01556       /* Check for the Timeout */
01557       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01558       {
01559         /* Process Unlocked */
01560         __HAL_UNLOCK(hdsi);
01561
01562         return HAL_TIMEOUT;
01563       }
01564     }
01565   }
01566   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
01567   {
01568         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
01569     {
01570       /* Check for the Timeout */
01571       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01572       {
01573         /* Process Unlocked */
01574         __HAL_UNLOCK(hdsi);
01575
01576         return HAL_TIMEOUT;
01577       }
01578     }
01579   }
01580
01581   /* Turn off the DSI PLL */
01582   __HAL_DSI_PLL_DISABLE(hdsi);
01583
01584   /* Process unlocked */
01585   __HAL_UNLOCK(hdsi);
01586
01587   return HAL_OK;
01588 }
01589
01590 /**
01591   * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
01592   *         (both data and clock lanes are in ULPM)
01593   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01594   *               the configuration information for the DSI.
01595   * @retval HAL status
01596   */
01597 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
01598 {
01599   uint32_t tickstart = 0U;
01600
01601   /* Process locked */
01602   __HAL_LOCK(hdsi);
01603
01604   /* Turn on the DSI PLL */
01605   __HAL_DSI_PLL_ENABLE(hdsi);
01606
01607   /* Get tick */
01608   tickstart = HAL_GetTick();
01609
01610   /* Wait for the lock of the PLL */
01611   while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
01612   {
01613     /* Check for the Timeout */
01614     if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01615     {
01616       /* Process Unlocked */
01617       __HAL_UNLOCK(hdsi);
01618
01619       return HAL_TIMEOUT;
01620     }
01621   }
01622
01623   /* Exit ULPS on Clock and Data Lanes */
01624   hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
01625
01626   /* Get tick */
01627   tickstart = HAL_GetTick();
01628
01629   /* Wait until all active lanes exit ULPM */
01630   if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
01631   {
01632         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
01633     {
01634       /* Check for the Timeout */
01635       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01636       {
01637         /* Process Unlocked */
01638         __HAL_UNLOCK(hdsi);
01639
01640         return HAL_TIMEOUT;
01641       }
01642     }
01643   }
01644   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
01645   {
01646         while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
01647     {
01648       /* Check for the Timeout */
01649       if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
01650       {
01651         /* Process Unlocked */
01652         __HAL_UNLOCK(hdsi);
01653
01654         return HAL_TIMEOUT;
01655       }
01656     }
01657   }
01658
01659   /* De-assert the ULPM requests and the ULPM exit bits */
01660   hdsi->Instance->PUCR = 0U;
01661
01662   /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
01663   __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
01664
01665   /* Restore clock lane configuration to HS */
01666   hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
01667
01668   /* Process unlocked */
01669   __HAL_UNLOCK(hdsi);
01670
01671   return HAL_OK;
01672 }
01673
01674 /**
01675   * @brief  Start test pattern generation
01676   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01677   *               the configuration information for the DSI.
01678   * @param  Mode: Pattern generator mode
01679   *          This parameter can be one of the following values:
01680   *           0 : Color bars (horizontal or vertical)
01681   *           1 : BER pattern (vertical only)
01682   * @param  Orientation: Pattern generator orientation
01683   *          This parameter can be one of the following values:
01684   *           0 : Vertical color bars
01685   *           1 : Horizontal color bars
01686   * @retval HAL status
01687   */
01688 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
01689 {
01690   /* Process locked */
01691   __HAL_LOCK(hdsi);
01692
01693   /* Configure pattern generator mode and orientation */
01694   hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
01695   hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
01696
01697   /* Enable pattern generator by setting PGE bit */
01698   hdsi->Instance->VMCR |= DSI_VMCR_PGE;
01699
01700   /* Process unlocked */
01701   __HAL_UNLOCK(hdsi);
01702
01703   return HAL_OK;
01704 }
01705
01706 /**
01707   * @brief  Stop test pattern generation
01708   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01709   *               the configuration information for the DSI.
01710   * @retval HAL status
01711   */
01712 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
01713 {
01714   /* Process locked */
01715   __HAL_LOCK(hdsi);
01716
01717   /* Disable pattern generator by clearing PGE bit */
01718   hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
01719
01720   /* Process unlocked */
01721   __HAL_UNLOCK(hdsi);
01722
01723   return HAL_OK;
01724 }
01725
01726 /**
01727   * @brief  Set Slew-Rate And Delay Tuning
01728   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01729   *               the configuration information for the DSI.
01730   * @param  CommDelay: Communication delay to be adjusted.
01731   *                    This parameter can be any value of @ref DSI_Communication_Delay
01732   * @param  Lane: select between clock or data lanes.
01733   *               This parameter can be any value of @ref DSI_Lane_Group
01734   * @param  Value: Custom value of the slew-rate or delay
01735   * @retval HAL status
01736   */
01737 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
01738 {
01739   /* Process locked */
01740   __HAL_LOCK(hdsi);
01741
01742   /* Check function parameters */
01743   assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
01744   assert_param(IS_DSI_LANE_GROUP(Lane));
01745
01746   switch(CommDelay)
01747   {
01748   case DSI_SLEW_RATE_HSTX:
01749     if(Lane == DSI_CLOCK_LANE)
01750     {
01751       /* High-Speed Transmission Slew Rate Control on Clock Lane */
01752       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
01753       hdsi->Instance->WPCR[1U] |= Value<<16U;
01754     }
01755     else if(Lane == DSI_DATA_LANES)
01756     {
01757       /* High-Speed Transmission Slew Rate Control on Data Lanes */
01758       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
01759       hdsi->Instance->WPCR[1U] |= Value<<18U;
01760     }
01761     break;
01762   case DSI_SLEW_RATE_LPTX:
01763     if(Lane == DSI_CLOCK_LANE)
01764     {
01765       /* Low-Power transmission Slew Rate Compensation on Clock Lane */
01766       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
01767       hdsi->Instance->WPCR[1U] |= Value<<6U;
01768     }
01769     else if(Lane == DSI_DATA_LANES)
01770     {
01771       /* Low-Power transmission Slew Rate Compensation on Data Lanes */
01772       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
01773       hdsi->Instance->WPCR[1U] |= Value<<8U;
01774     }
01775     break;
01776   case DSI_HS_DELAY:
01777     if(Lane == DSI_CLOCK_LANE)
01778     {
01779       /* High-Speed Transmission Delay on Clock Lane */
01780       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
01781       hdsi->Instance->WPCR[1U] |= Value;
01782     }
01783     else if(Lane == DSI_DATA_LANES)
01784     {
01785       /* High-Speed Transmission Delay on Data Lanes */
01786       hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
01787       hdsi->Instance->WPCR[1U] |= Value<<2U;
01788     }
01789     break;
01790   default:
01791     break;
01792   }
01793
01794   /* Process unlocked */
01795   __HAL_UNLOCK(hdsi);
01796
01797   return HAL_OK;
01798 }
01799
01800 /**
01801   * @brief  Low-Power Reception Filter Tuning
01802   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01803   *               the configuration information for the DSI.
01804   * @param  Frequency: cutoff frequency of low-pass filter at the input of LPRX
01805   * @retval HAL status
01806   */
01807 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
01808 {
01809   /* Process locked */
01810   __HAL_LOCK(hdsi);
01811
01812   /* Low-Power RX low-pass Filtering Tuning */
01813   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
01814   hdsi->Instance->WPCR[1U] |= Frequency<<25U;
01815
01816   /* Process unlocked */
01817   __HAL_UNLOCK(hdsi);
01818
01819   return HAL_OK;
01820 }
01821
01822 /**
01823   * @brief  Activate an additional current path on all lanes to meet the SDDTx parameter
01824   *         defined in the MIPI D-PHY specification
01825   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01826   *               the configuration information for the DSI.
01827   * @param  State: ENABLE or DISABLE
01828   * @retval HAL status
01829   */
01830 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
01831 {
01832   /* Process locked */
01833   __HAL_LOCK(hdsi);
01834
01835   /* Check function parameters */
01836   assert_param(IS_FUNCTIONAL_STATE(State));
01837
01838   /* Activate/Disactivate additional current path on all lanes */
01839   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
01840   hdsi->Instance->WPCR[1U] |= State<<12U;
01841
01842   /* Process unlocked */
01843   __HAL_UNLOCK(hdsi);
01844
01845   return HAL_OK;
01846 }
01847
01848 /**
01849   * @brief  Custom lane pins configuration
01850   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01851   *               the configuration information for the DSI.
01852   * @param  CustomLane: Function to be applyed on selected lane.
01853   *                     This parameter can be any value of @ref DSI_CustomLane
01854   * @param  Lane: select between clock or data lane 0 or data lane 1.
01855   *               This parameter can be any value of @ref DSI_Lane_Select
01856   * @param  State: ENABLE or DISABLE
01857   * @retval HAL status
01858   */
01859 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
01860 {
01861   /* Process locked */
01862   __HAL_LOCK(hdsi);
01863
01864   /* Check function parameters */
01865   assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
01866   assert_param(IS_DSI_LANE(Lane));
01867   assert_param(IS_FUNCTIONAL_STATE(State));
01868
01869   switch(CustomLane)
01870   {
01871   case DSI_SWAP_LANE_PINS:
01872     if(Lane == DSI_CLOCK_LANE)
01873     {
01874       /* Swap pins on clock lane */
01875       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
01876       hdsi->Instance->WPCR[0U] |= (State<<6U);
01877     }
01878     else if(Lane == DSI_DATA_LANE0)
01879     {
01880       /* Swap pins on data lane 0 */
01881       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
01882       hdsi->Instance->WPCR[0U] |= (State<<7U);
01883     }
01884     else if(Lane == DSI_DATA_LANE1)
01885     {
01886       /* Swap pins on data lane 1 */
01887       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
01888       hdsi->Instance->WPCR[0U] |= (State<<8U);
01889     }
01890     break;
01891   case DSI_INVERT_HS_SIGNAL:
01892     if(Lane == DSI_CLOCK_LANE)
01893     {
01894       /* Invert HS signal on clock lane */
01895       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
01896       hdsi->Instance->WPCR[0U] |= (State<<9U);
01897     }
01898     else if(Lane == DSI_DATA_LANE0)
01899     {
01900       /* Invert HS signal on data lane 0 */
01901       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
01902       hdsi->Instance->WPCR[0U] |= (State<<10U);
01903     }
01904     else if(Lane == DSI_DATA_LANE1)
01905     {
01906       /* Invert HS signal on data lane 1 */
01907       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
01908       hdsi->Instance->WPCR[0U] |= (State<<11U);
01909     }
01910     break;
01911   default:
01912     break;
01913   }
01914
01915   /* Process unlocked */
01916   __HAL_UNLOCK(hdsi);
01917
01918   return HAL_OK;
01919 }
01920
01921 /**
01922   * @brief  Set custom timing for the PHY
01923   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
01924   *               the configuration information for the DSI.
01925   * @param  Timing: PHY timing to be adjusted.
01926   *                 This parameter can be any value of @ref DSI_PHY_Timing
01927   * @param  State: ENABLE or DISABLE
01928   * @param  Value: Custom value of the timing
01929   * @retval HAL status
01930   */
01931 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
01932 {
01933   /* Process locked */
01934   __HAL_LOCK(hdsi);
01935
01936   /* Check function parameters */
01937   assert_param(IS_DSI_PHY_TIMING(Timing));
01938   assert_param(IS_FUNCTIONAL_STATE(State));
01939
01940   switch(Timing)
01941   {
01942   case DSI_TCLK_POST:
01943     /* Enable/Disable custom timing setting */
01944     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
01945     hdsi->Instance->WPCR[0U] |= (State<<27U);
01946
01947     if(State)
01948     {
01949       /* Set custom value */
01950       hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
01951       hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
01952     }
01953
01954     break;
01955   case DSI_TLPX_CLK:
01956     /* Enable/Disable custom timing setting */
01957     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
01958     hdsi->Instance->WPCR[0U] |= (State<<26U);
01959
01960     if(State)
01961     {
01962       /* Set custom value */
01963       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
01964       hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
01965     }
01966
01967     break;
01968   case DSI_THS_EXIT:
01969     /* Enable/Disable custom timing setting */
01970     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
01971     hdsi->Instance->WPCR[0U] |= (State<<25U);
01972
01973     if(State)
01974     {
01975       /* Set custom value */
01976       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
01977       hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
01978     }
01979
01980     break;
01981   case DSI_TLPX_DATA:
01982     /* Enable/Disable custom timing setting */
01983     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
01984     hdsi->Instance->WPCR[0U] |= (State<<24U);
01985
01986     if(State)
01987     {
01988       /* Set custom value */
01989       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
01990       hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
01991     }
01992
01993     break;
01994   case DSI_THS_ZERO:
01995     /* Enable/Disable custom timing setting */
01996     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
01997     hdsi->Instance->WPCR[0U] |= (State<<23U);
01998
01999     if(State)
02000     {
02001       /* Set custom value */
02002       hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
02003       hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
02004     }
02005
02006     break;
02007   case DSI_THS_TRAIL:
02008     /* Enable/Disable custom timing setting */
02009     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
02010     hdsi->Instance->WPCR[0U] |= (State<<22U);
02011
02012     if(State)
02013     {
02014       /* Set custom value */
02015       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
02016       hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
02017     }
02018
02019     break;
02020   case DSI_THS_PREPARE:
02021     /* Enable/Disable custom timing setting */
02022     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
02023     hdsi->Instance->WPCR[0U] |= (State<<21U);
02024
02025     if(State)
02026     {
02027       /* Set custom value */
02028       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
02029       hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
02030     }
02031
02032     break;
02033   case DSI_TCLK_ZERO:
02034     /* Enable/Disable custom timing setting */
02035     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
02036     hdsi->Instance->WPCR[0U] |= (State<<20U);
02037
02038     if(State)
02039     {
02040       /* Set custom value */
02041       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
02042       hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
02043     }
02044
02045     break;
02046   case DSI_TCLK_PREPARE:
02047     /* Enable/Disable custom timing setting */
02048     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
02049     hdsi->Instance->WPCR[0U] |= (State<<19U);
02050
02051     if(State)
02052     {
02053       /* Set custom value */
02054       hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
02055       hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
02056     }
02057
02058     break;
02059   default:
02060     break;
02061   }
02062
02063   /* Process unlocked */
02064   __HAL_UNLOCK(hdsi);
02065
02066   return HAL_OK;
02067 }
02068
02069 /**
02070   * @brief  Force the Clock/Data Lane in TX Stop Mode
02071   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
02072   *               the configuration information for the DSI.
02073   * @param  Lane: select between clock or data lanes.
02074   *               This parameter can be any value of @ref DSI_Lane_Group
02075   * @param  State: ENABLE or DISABLE
02076   * @retval HAL status
02077   */
02078 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
02079 {
02080   /* Process locked */
02081   __HAL_LOCK(hdsi);
02082
02083   /* Check function parameters */
02084   assert_param(IS_DSI_LANE_GROUP(Lane));
02085   assert_param(IS_FUNCTIONAL_STATE(State));
02086
02087   if(Lane == DSI_CLOCK_LANE)
02088   {
02089     /* Force/Unforce the Clock Lane in TX Stop Mode */
02090     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
02091     hdsi->Instance->WPCR[0U] |= (State<<12U);
02092   }
02093   else if(Lane == DSI_DATA_LANES)
02094   {
02095     /* Force/Unforce the Data Lanes in TX Stop Mode */
02096     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
02097     hdsi->Instance->WPCR[0U] |= (State<<13U);
02098   }
02099
02100   /* Process unlocked */
02101   __HAL_UNLOCK(hdsi);
02102
02103   return HAL_OK;
02104 }
02105
02106 /**
02107   * @brief  Forces LP Receiver in Low-Power Mode
02108   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
02109   *               the configuration information for the DSI.
02110   * @param  State: ENABLE or DISABLE
02111   * @retval HAL status
02112   */
02113 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
02114 {
02115   /* Process locked */
02116   __HAL_LOCK(hdsi);
02117
02118   /* Check function parameters */
02119   assert_param(IS_FUNCTIONAL_STATE(State));
02120
02121   /* Force/Unforce LP Receiver in Low-Power Mode */
02122   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
02123   hdsi->Instance->WPCR[1U] |= State<<22U;
02124
02125   /* Process unlocked */
02126   __HAL_UNLOCK(hdsi);
02127
02128   return HAL_OK;
02129 }
02130
02131 /**
02132   * @brief  Force Data Lanes in RX Mode after a BTA
02133   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
02134   *               the configuration information for the DSI.
02135   * @param  State: ENABLE or DISABLE
02136   * @retval HAL status
02137   */
02138 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
02139 {
02140   /* Process locked */
02141   __HAL_LOCK(hdsi);
02142
02143   /* Check function parameters */
02144   assert_param(IS_FUNCTIONAL_STATE(State));
02145
02146   /* Force Data Lanes in RX Mode */
02147   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
02148   hdsi->Instance->WPCR[0U] |= State<<16U;
02149
02150   /* Process unlocked */
02151   __HAL_UNLOCK(hdsi);
02152
02153   return HAL_OK;
02154 }
02155
02156 /**
02157   * @brief  Enable a pull-down on the lanes to prevent from floating states when unused
02158   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
02159   *               the configuration information for the DSI.
02160   * @param  State: ENABLE or DISABLE
02161   * @retval HAL status
02162   */
02163 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
02164 {
02165   /* Process locked */
02166   __HAL_LOCK(hdsi);
02167
02168   /* Check function parameters */
02169   assert_param(IS_FUNCTIONAL_STATE(State));
02170
02171   /* Enable/Disable pull-down on lanes */
02172   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
02173   hdsi->Instance->WPCR[0U] |= State<<18U;
02174
02175   /* Process unlocked */
02176   __HAL_UNLOCK(hdsi);
02177
02178   return HAL_OK;
02179 }
02180
02181 /**
02182   * @brief  Switch off the contention detection on data lanes
02183   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
02184   *               the configuration information for the DSI.
02185   * @param  State: ENABLE or DISABLE
02186   * @retval HAL status
02187   */
02188 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
02189 {
02190   /* Process locked */
02191   __HAL_LOCK(hdsi);
02192
02193   /* Check function parameters */
02194   assert_param(IS_FUNCTIONAL_STATE(State));
02195
02196   /* Contention Detection on Data Lanes OFF */
02197   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
02198   hdsi->Instance->WPCR[0U] |= State<<14U;
02199
02200   /* Process unlocked */
02201   __HAL_UNLOCK(hdsi);
02202
02203   return HAL_OK;
02204 }
02205
02206 /**
02207   * @}
02208   */
02209
02210 /** @defgroup DSI_Group4 Peripheral State and Errors functions
02211  *  @brief    Peripheral State and Errors functions
02212  *
02213 @verbatim
02214  ===============================================================================
02215                   ##### Peripheral State and Errors functions #####
02216  ===============================================================================
02217     [..]
02218     This subsection provides functions allowing to
02219       (+) Check the DSI state.
02220       (+) Get error code.
02221
02222 @endverbatim
02223   * @{
02224   */
02225
02226 /**
02227   * @brief  Return the DSI state
02228   * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains
02229   *               the configuration information for the DSI.
02230   * @retval HAL state
02231   */
02232 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
02233 {
02234   return hdsi->State;
02235 }
02236
02237 /**
02238   * @}
02239   */
02240
02241 /**
02242   * @}
02243   */
02244 #endif /* STM32F469xx || STM32F479xx */
02245 #endif /* HAL_DSI_MODULE_ENABLED */
02246 /**
02247   * @}
02248   */
02249
02250 /**
02251   * @}
02252   */
02253
02254 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_dsi.h Source File

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stm32f4xx_hal_dsi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dsi.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of DSI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_DSI_H
00040 #define __STM32F4xx_HAL_DSI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F469xx) || defined(STM32F479xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @defgroup DSI DSI
00055   * @brief DSI HAL module driver
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /**
00061   * @brief  DSI Init Structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
00066                                            This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
00067
00068   uint32_t TXEscapeCkdiv;             /*!< TX Escape clock division
00069                                            The values 0 and 1 stop the TX_ESC clock generation                    */
00070
00071   uint32_t NumberOfLanes;             /*!< Number of lanes
00072                                            This parameter can be any value of @ref DSI_Number_Of_Lanes            */
00073
00074 }DSI_InitTypeDef;
00075
00076 /**
00077   * @brief  DSI PLL Clock structure definition
00078   */
00079 typedef struct
00080 {
00081   uint32_t PLLNDIV; /*!< PLL Loop Division Factor
00082                          This parameter must be a value between 10 and 125   */
00083
00084   uint32_t PLLIDF;  /*!< PLL Input Division Factor
00085                          This parameter can be any value of @ref DSI_PLL_IDF */
00086
00087   uint32_t PLLODF;  /*!< PLL Output Division Factor
00088                          This parameter can be any value of @ref DSI_PLL_ODF */
00089
00090 }DSI_PLLInitTypeDef;
00091
00092 /**
00093   * @brief  DSI Video mode configuration
00094   */
00095 typedef struct
00096 {
00097   uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                 */
00098
00099   uint32_t ColorCoding;                  /*!< Color coding for LTDC interface
00100                                               This parameter can be any value of @ref DSI_Color_Coding           */
00101
00102   uint32_t LooselyPacked;                /*!< Enable or disable loosely packed stream (needed only when using
00103                                               18-bit configuration).
00104                                               This parameter can be any value of @ref DSI_LooselyPacked          */
00105
00106   uint32_t Mode;                         /*!< Video mode type
00107                                               This parameter can be any value of @ref DSI_Video_Mode_Type        */
00108
00109   uint32_t PacketSize;                   /*!< Video packet size                                                  */
00110
00111   uint32_t NumberOfChunks;               /*!< Number of chunks                                                   */
00112
00113   uint32_t NullPacketSize;               /*!< Null packet size                                                   */
00114
00115   uint32_t HSPolarity;                   /*!< HSYNC pin polarity
00116                                               This parameter can be any value of @ref DSI_HSYNC_Polarity         */
00117
00118   uint32_t VSPolarity;                   /*!< VSYNC pin polarity
00119                                               This parameter can be any value of @ref DSI_VSYNC_Active_Polarity  */
00120
00121   uint32_t DEPolarity;                   /*!< Data Enable pin polarity
00122                                               This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity   */
00123
00124   uint32_t HorizontalSyncActive;         /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
00125
00126   uint32_t HorizontalBackPorch;          /*!< Horizontal back-porch duration (in lane byte clock cycles)         */
00127
00128   uint32_t HorizontalLine;               /*!< Horizontal line duration (in lane byte clock cycles)               */
00129
00130   uint32_t VerticalSyncActive;           /*!< Vertical synchronism active duration                               */
00131
00132   uint32_t VerticalBackPorch;            /*!< Vertical back-porch duration                                       */
00133
00134   uint32_t VerticalFrontPorch;           /*!< Vertical front-porch duration                                      */
00135
00136   uint32_t VerticalActive;               /*!< Vertical active duration                                           */
00137
00138   uint32_t LPCommandEnable;              /*!< Low-power command enable
00139                                               This parameter can be any value of @ref DSI_LP_Command             */
00140
00141   uint32_t LPLargestPacketSize;          /*!< The size, in bytes, of the low power largest packet that
00142                                               can fit in a line during VSA, VBP and VFP regions                  */
00143
00144   uint32_t LPVACTLargestPacketSize;      /*!< The size, in bytes, of the low power largest packet that
00145                                               can fit in a line during VACT region                               */
00146
00147   uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
00148                                               This parameter can be any value of @ref DSI_LP_HFP                 */
00149
00150   uint32_t LPHorizontalBackPorchEnable;  /*!< Low-power horizontal back-porch enable
00151                                               This parameter can be any value of @ref DSI_LP_HBP                 */
00152
00153   uint32_t LPVerticalActiveEnable;       /*!< Low-power vertical active enable
00154                                               This parameter can be any value of @ref DSI_LP_VACT                */
00155
00156   uint32_t LPVerticalFrontPorchEnable;   /*!< Low-power vertical front-porch enable
00157                                               This parameter can be any value of @ref DSI_LP_VFP                 */
00158
00159   uint32_t LPVerticalBackPorchEnable;    /*!< Low-power vertical back-porch enable
00160                                               This parameter can be any value of @ref DSI_LP_VBP                 */
00161
00162   uint32_t LPVerticalSyncActiveEnable;   /*!< Low-power vertical sync active enable
00163                                               This parameter can be any value of @ref DSI_LP_VSYNC               */
00164
00165   uint32_t FrameBTAAcknowledgeEnable;    /*!< Frame bus-turn-around acknowledge enable
00166                                               This parameter can be any value of @ref DSI_FBTA_acknowledge       */
00167
00168 }DSI_VidCfgTypeDef;
00169
00170 /**
00171   * @brief  DSI Adapted command mode configuration
00172   */
00173 typedef struct
00174 {
00175   uint32_t VirtualChannelID;      /*!< Virtual channel ID                                                */
00176
00177   uint32_t ColorCoding;           /*!< Color coding for LTDC interface
00178                                        This parameter can be any value of @ref DSI_Color_Coding          */
00179
00180   uint32_t CommandSize;           /*!< Maximum allowed size for an LTDC write memory command, measured in
00181                                        pixels. This parameter can be any value between 0x00 and 0xFFFFU   */
00182
00183   uint32_t TearingEffectSource;   /*!< Tearing effect source
00184                                        This parameter can be any value of @ref DSI_TearingEffectSource   */
00185
00186   uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
00187                                        This parameter can be any value of @ref DSI_TearingEffectPolarity */
00188
00189   uint32_t HSPolarity;            /*!< HSYNC pin polarity
00190                                        This parameter can be any value of @ref DSI_HSYNC_Polarity        */
00191
00192   uint32_t VSPolarity;            /*!< VSYNC pin polarity
00193                                        This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
00194
00195   uint32_t DEPolarity;            /*!< Data Enable pin polarity
00196                                        This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity  */
00197
00198   uint32_t VSyncPol;              /*!< VSync edge on which the LTDC is halted
00199                                        This parameter can be any value of @ref DSI_Vsync_Polarity        */
00200
00201   uint32_t AutomaticRefresh;      /*!< Automatic refresh mode
00202                                        This parameter can be any value of @ref DSI_AutomaticRefresh      */
00203
00204   uint32_t TEAcknowledgeRequest;  /*!< Tearing Effect Acknowledge Request Enable
00205                                        This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
00206
00207 }DSI_CmdCfgTypeDef;
00208
00209 /**
00210   * @brief  DSI command transmission mode configuration
00211   */
00212 typedef struct
00213 {
00214   uint32_t LPGenShortWriteNoP;  /*!< Generic Short Write Zero parameters Transmission
00215                                      This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP  */
00216
00217   uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
00218                                      This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
00219
00220   uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
00221                                      This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
00222
00223   uint32_t LPGenShortReadNoP;   /*!< Generic Short Read Zero parameters Transmission
00224                                      This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP   */
00225
00226   uint32_t LPGenShortReadOneP;  /*!< Generic Short Read One parameter Transmission
00227                                      This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP  */
00228
00229   uint32_t LPGenShortReadTwoP;  /*!< Generic Short Read Two parameters Transmission
00230                                      This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP  */
00231
00232   uint32_t LPGenLongWrite;      /*!< Generic Long Write Transmission
00233                                      This parameter can be any value of @ref DSI_LP_LPGenLongWrite      */
00234
00235   uint32_t LPDcsShortWriteNoP;  /*!< DCS Short Write Zero parameters Transmission
00236                                      This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP  */
00237
00238   uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
00239                                      This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
00240
00241   uint32_t LPDcsShortReadNoP;   /*!< DCS Short Read Zero parameters Transmission
00242                                      This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP   */
00243
00244   uint32_t LPDcsLongWrite;      /*!< DCS Long Write Transmission
00245                                      This parameter can be any value of @ref DSI_LP_LPDcsLongWrite      */
00246
00247   uint32_t LPMaxReadPacket;     /*!< Maximum Read Packet Size Transmission
00248                                      This parameter can be any value of @ref DSI_LP_LPMaxReadPacket     */
00249
00250   uint32_t AcknowledgeRequest;  /*!< Acknowledge Request Enable
00251                                      This parameter can be any value of @ref DSI_AcknowledgeRequest     */
00252
00253 }DSI_LPCmdTypeDef;
00254
00255 /**
00256   * @brief  DSI PHY Timings definition
00257   */
00258 typedef struct
00259 {
00260   uint32_t ClockLaneHS2LPTime;        /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
00261                                            to low-power transmission                                              */
00262
00263   uint32_t ClockLaneLP2HSTime;        /*!< The maximum time that the D-PHY clock lane takes to go from low-power
00264                                            to high-speed transmission                                             */
00265
00266   uint32_t DataLaneHS2LPTime;         /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
00267                                            to low-power transmission                                              */
00268
00269   uint32_t DataLaneLP2HSTime;         /*!< The maximum time that the D-PHY data lanes takes to go from low-power
00270                                            to high-speed transmission                                             */
00271
00272   uint32_t DataLaneMaxReadTime;       /*!< The maximum time required to perform a read command */
00273
00274   uint32_t StopWaitTime;              /*!< The minimum wait period to request a High-Speed transmission after the
00275                                            Stop state                                                             */
00276
00277 }DSI_PHY_TimerTypeDef;
00278
00279 /**
00280   * @brief  DSI HOST Timeouts definition
00281   */
00282 typedef struct
00283 {
00284   uint32_t TimeoutCkdiv;                 /*!< Time-out clock division                                  */
00285
00286   uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out                         */
00287
00288   uint32_t LowPowerReceptionTimeout;     /*!< Low-power reception time-out                             */
00289
00290   uint32_t HighSpeedReadTimeout;         /*!< High-speed read time-out                                 */
00291
00292   uint32_t LowPowerReadTimeout;          /*!< Low-power read time-out                                  */
00293
00294   uint32_t HighSpeedWriteTimeout;        /*!< High-speed write time-out                                */
00295
00296   uint32_t HighSpeedWritePrespMode;      /*!< High-speed write presp mode
00297                                               This parameter can be any value of @ref DSI_HS_PrespMode */
00298
00299   uint32_t LowPowerWriteTimeout;         /*!< Low-speed write time-out                                 */
00300
00301   uint32_t BTATimeout;                   /*!< BTA time-out                                             */
00302
00303 }DSI_HOST_TimeoutTypeDef;
00304
00305 /**
00306   * @brief  DSI States Structure definition
00307   */
00308 typedef enum
00309 {
00310   HAL_DSI_STATE_RESET   = 0x00U,
00311   HAL_DSI_STATE_READY   = 0x01U,
00312   HAL_DSI_STATE_ERROR   = 0x02U,
00313   HAL_DSI_STATE_BUSY    = 0x03U,
00314   HAL_DSI_STATE_TIMEOUT = 0x04U
00315 }HAL_DSI_StateTypeDef;
00316
00317 /**
00318   * @brief  DSI Handle Structure definition
00319   */
00320 typedef struct
00321 {
00322   DSI_TypeDef               *Instance;    /*!< Register base address      */
00323   DSI_InitTypeDef           Init;         /*!< DSI required parameters    */
00324   HAL_LockTypeDef           Lock;         /*!< DSI peripheral status      */
00325   __IO HAL_DSI_StateTypeDef State;        /*!< DSI communication state    */
00326   __IO uint32_t             ErrorCode;    /*!< DSI Error code             */
00327   uint32_t                  ErrorMsk;     /*!< DSI Error monitoring mask  */
00328 }DSI_HandleTypeDef;
00329
00330 /* Exported constants --------------------------------------------------------*/
00331 /** @defgroup DSI_DCS_Command DSI DCS Command
00332   * @{
00333   */
00334 #define DSI_ENTER_IDLE_MODE       0x39U
00335 #define DSI_ENTER_INVERT_MODE     0x21U
00336 #define DSI_ENTER_NORMAL_MODE     0x13U
00337 #define DSI_ENTER_PARTIAL_MODE    0x12U
00338 #define DSI_ENTER_SLEEP_MODE      0x10U
00339 #define DSI_EXIT_IDLE_MODE        0x38U
00340 #define DSI_EXIT_INVERT_MODE      0x20U
00341 #define DSI_EXIT_SLEEP_MODE       0x11U
00342 #define DSI_GET_3D_CONTROL        0x3FU
00343 #define DSI_GET_ADDRESS_MODE      0x0BU
00344 #define DSI_GET_BLUE_CHANNEL      0x08U
00345 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
00346 #define DSI_GET_DISPLAY_MODE      0x0DU
00347 #define DSI_GET_GREEN_CHANNEL     0x07U
00348 #define DSI_GET_PIXEL_FORMAT      0x0CU
00349 #define DSI_GET_POWER_MODE        0x0AU
00350 #define DSI_GET_RED_CHANNEL       0x06U
00351 #define DSI_GET_SCANLINE          0x45U
00352 #define DSI_GET_SIGNAL_MODE       0x0EU
00353 #define DSI_NOP                   0x00U
00354 #define DSI_READ_DDB_CONTINUE     0xA8U
00355 #define DSI_READ_DDB_START        0xA1U
00356 #define DSI_READ_MEMORY_CONTINUE  0x3EU
00357 #define DSI_READ_MEMORY_START     0x2EU
00358 #define DSI_SET_3D_CONTROL        0x3DU
00359 #define DSI_SET_ADDRESS_MODE      0x36U
00360 #define DSI_SET_COLUMN_ADDRESS    0x2AU
00361 #define DSI_SET_DISPLAY_OFF       0x28U
00362 #define DSI_SET_DISPLAY_ON        0x29U
00363 #define DSI_SET_GAMMA_CURVE       0x26U
00364 #define DSI_SET_PAGE_ADDRESS      0x2BU
00365 #define DSI_SET_PARTIAL_COLUMNS   0x31U
00366 #define DSI_SET_PARTIAL_ROWS      0x30U
00367 #define DSI_SET_PIXEL_FORMAT      0x3AU
00368 #define DSI_SET_SCROLL_AREA       0x33U
00369 #define DSI_SET_SCROLL_START      0x37U
00370 #define DSI_SET_TEAR_OFF          0x34U
00371 #define DSI_SET_TEAR_ON           0x35U
00372 #define DSI_SET_TEAR_SCANLINE     0x44U
00373 #define DSI_SET_VSYNC_TIMING      0x40U
00374 #define DSI_SOFT_RESET            0x01U
00375 #define DSI_WRITE_LUT             0x2DU
00376 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
00377 #define DSI_WRITE_MEMORY_START    0x2CU
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
00383   * @{
00384   */
00385 #define DSI_VID_MODE_NB_PULSES 0U
00386 #define DSI_VID_MODE_NB_EVENTS 1U
00387 #define DSI_VID_MODE_BURST     2U
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup DSI_Color_Mode DSI Color Mode
00393   * @{
00394   */
00395 #define DSI_COLOR_MODE_FULL  ((uint32_t)0x00000000U)
00396 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup DSI_ShutDown DSI ShutDown
00402   * @{
00403   */
00404 #define DSI_DISPLAY_ON  ((uint32_t)0x00000000U)
00405 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup DSI_LP_Command DSI LP Command
00411   * @{
00412   */
00413 #define DSI_LP_COMMAND_DISABLE ((uint32_t)0x00000000U)
00414 #define DSI_LP_COMMAND_ENABLE  DSI_VMCR_LPCE
00415 /**
00416   * @}
00417   */
00418
00419 /** @defgroup DSI_LP_HFP DSI LP HFP
00420   * @{
00421   */
00422 #define DSI_LP_HFP_DISABLE ((uint32_t)0x00000000U)
00423 #define DSI_LP_HFP_ENABLE  DSI_VMCR_LPHFPE
00424 /**
00425   * @}
00426   */
00427
00428 /** @defgroup DSI_LP_HBP DSI LP HBP
00429   * @{
00430   */
00431 #define DSI_LP_HBP_DISABLE ((uint32_t)0x00000000U)
00432 #define DSI_LP_HBP_ENABLE  DSI_VMCR_LPHBPE
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup DSI_LP_VACT DSI LP VACT
00438   * @{
00439   */
00440 #define DSI_LP_VACT_DISABLE ((uint32_t)0x00000000U)
00441 #define DSI_LP_VACT_ENABLE  DSI_VMCR_LPVAE
00442 /**
00443   * @}
00444   */
00445
00446 /** @defgroup DSI_LP_VFP DSI LP VFP
00447   * @{
00448   */
00449 #define DSI_LP_VFP_DISABLE ((uint32_t)0x00000000U)
00450 #define DSI_LP_VFP_ENABLE  DSI_VMCR_LPVFPE
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup DSI_LP_VBP DSI LP VBP
00456   * @{
00457   */
00458 #define DSI_LP_VBP_DISABLE ((uint32_t)0x00000000U)
00459 #define DSI_LP_VBP_ENABLE  DSI_VMCR_LPVBPE
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC
00465   * @{
00466   */
00467 #define DSI_LP_VSYNC_DISABLE ((uint32_t)0x00000000U)
00468 #define DSI_LP_VSYNC_ENABLE  DSI_VMCR_LPVSAE
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
00474   * @{
00475   */
00476 #define DSI_FBTAA_DISABLE ((uint32_t)0x00000000U)
00477 #define DSI_FBTAA_ENABLE  DSI_VMCR_FBTAAE
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
00483   * @{
00484   */
00485 #define DSI_TE_DSILINK  ((uint32_t)0x00000000U)
00486 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
00492   * @{
00493   */
00494 #define DSI_TE_RISING_EDGE  ((uint32_t)0x00000000U)
00495 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
00501   * @{
00502   */
00503 #define DSI_VSYNC_FALLING ((uint32_t)0x00000000U)
00504 #define DSI_VSYNC_RISING  DSI_WCFGR_VSPOL
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
00510   * @{
00511   */
00512 #define DSI_AR_DISABLE ((uint32_t)0x00000000U)
00513 #define DSI_AR_ENABLE  DSI_WCFGR_AR
00514 /**
00515   * @}
00516   */
00517
00518 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
00519   * @{
00520   */
00521 #define DSI_TE_ACKNOWLEDGE_DISABLE ((uint32_t)0x00000000U)
00522 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
00523 /**
00524   * @}
00525   */
00526
00527 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
00528   * @{
00529   */
00530 #define DSI_ACKNOWLEDGE_DISABLE ((uint32_t)0x00000000U)
00531 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
00537   * @{
00538   */
00539 #define DSI_LP_GSW0P_DISABLE ((uint32_t)0x00000000U)
00540 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
00546   * @{
00547   */
00548 #define DSI_LP_GSW1P_DISABLE ((uint32_t)0x00000000U)
00549 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
00550 /**
00551   * @}
00552   */
00553
00554 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
00555   * @{
00556   */
00557 #define DSI_LP_GSW2P_DISABLE ((uint32_t)0x00000000U)
00558 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
00559 /**
00560   * @}
00561   */
00562
00563 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
00564   * @{
00565   */
00566 #define DSI_LP_GSR0P_DISABLE ((uint32_t)0x00000000U)
00567 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
00573   * @{
00574   */
00575 #define DSI_LP_GSR1P_DISABLE ((uint32_t)0x00000000U)
00576 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
00582   * @{
00583   */
00584 #define DSI_LP_GSR2P_DISABLE ((uint32_t)0x00000000U)
00585 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
00591   * @{
00592   */
00593 #define DSI_LP_GLW_DISABLE ((uint32_t)0x00000000U)
00594 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
00600   * @{
00601   */
00602 #define DSI_LP_DSW0P_DISABLE ((uint32_t)0x00000000U)
00603 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
00604 /**
00605   * @}
00606   */
00607
00608 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
00609   * @{
00610   */
00611 #define DSI_LP_DSW1P_DISABLE ((uint32_t)0x00000000U)
00612 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
00613 /**
00614   * @}
00615   */
00616
00617 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
00618   * @{
00619   */
00620 #define DSI_LP_DSR0P_DISABLE ((uint32_t)0x00000000U)
00621 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
00622 /**
00623   * @}
00624   */
00625
00626 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
00627   * @{
00628   */
00629 #define DSI_LP_DLW_DISABLE ((uint32_t)0x00000000U)
00630 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
00636   * @{
00637   */
00638 #define DSI_LP_MRDP_DISABLE ((uint32_t)0x00000000U)
00639 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
00640 /**
00641   * @}
00642   */
00643
00644 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
00645   * @{
00646   */
00647 #define DSI_HS_PM_DISABLE ((uint32_t)0x00000000U)
00648 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
00649 /**
00650   * @}
00651   */
00652
00653
00654 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
00655   * @{
00656   */
00657 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE ((uint32_t)0x00000000U)
00658 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE  DSI_CLCR_ACR
00659 /**
00660   * @}
00661   */
00662
00663 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
00664   * @{
00665   */
00666 #define DSI_ONE_DATA_LANE  0U
00667 #define DSI_TWO_DATA_LANES 1U
00668 /**
00669   * @}
00670   */
00671
00672 /** @defgroup DSI_FlowControl DSI Flow Control
00673   * @{
00674   */
00675 #define DSI_FLOW_CONTROL_CRC_RX  DSI_PCR_CRCRXE
00676 #define DSI_FLOW_CONTROL_ECC_RX  DSI_PCR_ECCRXE
00677 #define DSI_FLOW_CONTROL_BTA     DSI_PCR_BTAE
00678 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
00679 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
00680 #define DSI_FLOW_CONTROL_ALL     (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
00681                                   DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
00682                                   DSI_FLOW_CONTROL_EOTP_TX)
00683 /**
00684   * @}
00685   */
00686
00687 /** @defgroup DSI_Color_Coding DSI Color Coding
00688   * @{
00689   */
00690 #define DSI_RGB565 ((uint32_t)0x00000000U) /*!< The values 0x00000001U and 0x00000002U can also be used for the RGB565 color mode configuration */
00691 #define DSI_RGB666 ((uint32_t)0x00000003U) /*!< The value 0x00000004U can also be used for the RGB666 color mode configuration                 */
00692 #define DSI_RGB888 ((uint32_t)0x00000005U)
00693 /**
00694   * @}
00695   */
00696
00697 /** @defgroup DSI_LooselyPacked DSI Loosely Packed
00698   * @{
00699   */
00700 #define DSI_LOOSELY_PACKED_ENABLE  DSI_LCOLCR_LPE
00701 #define DSI_LOOSELY_PACKED_DISABLE ((uint32_t)0x00000000U)
00702 /**
00703   * @}
00704   */
00705
00706 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
00707   * @{
00708   */
00709 #define DSI_HSYNC_ACTIVE_HIGH       ((uint32_t)0x00000000U)
00710 #define DSI_HSYNC_ACTIVE_LOW        DSI_LPCR_HSP
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
00716   * @{
00717   */
00718 #define DSI_VSYNC_ACTIVE_HIGH       ((uint32_t)0x00000000U)
00719 #define DSI_VSYNC_ACTIVE_LOW        DSI_LPCR_VSP
00720 /**
00721   * @}
00722   */
00723
00724 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
00725   * @{
00726   */
00727 #define DSI_DATA_ENABLE_ACTIVE_HIGH ((uint32_t)0x00000000U)
00728 #define DSI_DATA_ENABLE_ACTIVE_LOW  DSI_LPCR_DEP
00729 /**
00730   * @}
00731   */
00732
00733 /** @defgroup DSI_PLL_IDF DSI PLL IDF
00734   * @{
00735   */
00736 #define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001U)
00737 #define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002U)
00738 #define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003U)
00739 #define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004U)
00740 #define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005U)
00741 #define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006U)
00742 #define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007U)
00743 /**
00744   * @}
00745   */
00746
00747 /** @defgroup DSI_PLL_ODF DSI PLL ODF
00748   * @{
00749   */
00750 #define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000U)
00751 #define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001U)
00752 #define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002U)
00753 #define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003U)
00754 /**
00755   * @}
00756   */
00757
00758 /** @defgroup DSI_Flags DSI Flags
00759   * @{
00760   */
00761 #define DSI_FLAG_TE    DSI_WISR_TEIF
00762 #define DSI_FLAG_ER    DSI_WISR_ERIF
00763 #define DSI_FLAG_BUSY  DSI_WISR_BUSY
00764 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
00765 #define DSI_FLAG_PLLL  DSI_WISR_PLLLIF
00766 #define DSI_FLAG_PLLU  DSI_WISR_PLLUIF
00767 #define DSI_FLAG_RRS   DSI_WISR_RRS
00768 #define DSI_FLAG_RR    DSI_WISR_RRIF
00769 /**
00770   * @}
00771   */
00772
00773 /** @defgroup DSI_Interrupts DSI Interrupts
00774   * @{
00775   */
00776 #define DSI_IT_TE   DSI_WIER_TEIE
00777 #define DSI_IT_ER   DSI_WIER_ERIE
00778 #define DSI_IT_PLLL DSI_WIER_PLLLIE
00779 #define DSI_IT_PLLU DSI_WIER_PLLUIE
00780 #define DSI_IT_RR   DSI_WIER_RRIE
00781 /**
00782   * @}
00783   */
00784
00785 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
00786   * @{
00787   */
00788 #define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U) /*!< DCS short write, no parameters      */
00789 #define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U) /*!< DCS short write, one parameter      */
00790 #define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U) /*!< Generic short write, no parameters  */
00791 #define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U) /*!< Generic short write, one parameter  */
00792 #define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U) /*!< Generic short write, two parameters */
00793 /**
00794   * @}
00795   */
00796
00797 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
00798   * @{
00799   */
00800 #define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U) /*!< DCS long write     */
00801 #define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U) /*!< Generic long write */
00802 /**
00803   * @}
00804   */
00805
00806 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
00807   * @{
00808   */
00809 #define DSI_DCS_SHORT_PKT_READ    ((uint32_t)0x00000006U) /*!< DCS short read                     */
00810 #define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U) /*!< Generic short read, no parameters  */
00811 #define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U) /*!< Generic short read, one parameter  */
00812 #define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U) /*!< Generic short read, two parameters */
00813 /**
00814   * @}
00815   */
00816
00817 /** @defgroup DSI_Error_Data_Type DSI Error Data Type
00818   * @{
00819   */
00820 #define HAL_DSI_ERROR_NONE 0
00821 #define HAL_DSI_ERROR_ACK  ((uint32_t)0x00000001U) /*!< acknowledge errors          */
00822 #define HAL_DSI_ERROR_PHY  ((uint32_t)0x00000002U) /*!< PHY related errors          */
00823 #define HAL_DSI_ERROR_TX   ((uint32_t)0x00000004U) /*!< transmission error          */
00824 #define HAL_DSI_ERROR_RX   ((uint32_t)0x00000008U) /*!< reception error             */
00825 #define HAL_DSI_ERROR_ECC  ((uint32_t)0x00000010U) /*!< ECC errors                  */
00826 #define HAL_DSI_ERROR_CRC  ((uint32_t)0x00000020U) /*!< CRC error                   */
00827 #define HAL_DSI_ERROR_PSE  ((uint32_t)0x00000040U) /*!< Packet Size error           */
00828 #define HAL_DSI_ERROR_EOT  ((uint32_t)0x00000080U) /*!< End Of Transmission error   */
00829 #define HAL_DSI_ERROR_OVF  ((uint32_t)0x00000100U) /*!< FIFO overflow error         */
00830 #define HAL_DSI_ERROR_GEN  ((uint32_t)0x00000200U) /*!< Generic FIFO related errors */
00831 /**
00832   * @}
00833   */
00834
00835 /** @defgroup DSI_Lane_Group DSI Lane Group
00836   * @{
00837   */
00838 #define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
00839 #define DSI_DATA_LANES ((uint32_t)0x00000001U)
00840 /**
00841   * @}
00842   */
00843
00844 /** @defgroup DSI_Communication_Delay DSI Communication Delay
00845   * @{
00846   */
00847 #define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U)
00848 #define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U)
00849 #define DSI_HS_DELAY       ((uint32_t)0x00000002U)
00850 /**
00851   * @}
00852   */
00853
00854 /** @defgroup DSI_CustomLane DSI CustomLane
00855   * @{
00856   */
00857 #define DSI_SWAP_LANE_PINS   ((uint32_t)0x00000000U)
00858 #define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U)
00859 /**
00860   * @}
00861   */
00862
00863 /** @defgroup DSI_Lane_Select DSI Lane Select
00864   * @{
00865   */
00866 #define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
00867 #define DSI_DATA_LANE0 ((uint32_t)0x00000001U)
00868 #define DSI_DATA_LANE1 ((uint32_t)0x00000002U)
00869 /**
00870   * @}
00871   */
00872
00873 /** @defgroup DSI_PHY_Timing DSI PHY Timing
00874   * @{
00875   */
00876 #define DSI_TCLK_POST    ((uint32_t)0x00000000U)
00877 #define DSI_TLPX_CLK     ((uint32_t)0x00000001U)
00878 #define DSI_THS_EXIT     ((uint32_t)0x00000002U)
00879 #define DSI_TLPX_DATA    ((uint32_t)0x00000003U)
00880 #define DSI_THS_ZERO     ((uint32_t)0x00000004U)
00881 #define DSI_THS_TRAIL    ((uint32_t)0x00000005U)
00882 #define DSI_THS_PREPARE  ((uint32_t)0x00000006U)
00883 #define DSI_TCLK_ZERO    ((uint32_t)0x00000007U)
00884 #define DSI_TCLK_PREPARE ((uint32_t)0x00000008U)
00885 /**
00886   * @}
00887   */
00888
00889 /* Exported macros -----------------------------------------------------------*/
00890 /**
00891   * @brief  Enables the DSI host.
00892   * @param  __HANDLE__: DSI handle
00893   * @retval None.
00894   */
00895 #define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN)
00896
00897 /**
00898   * @brief  Disables the DSI host.
00899   * @param  __HANDLE__: DSI handle
00900   * @retval None.
00901   */
00902 #define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
00903
00904 /**
00905   * @brief  Enables the DSI wrapper.
00906   * @param  __HANDLE__: DSI handle
00907   * @retval None.
00908   */
00909 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN)
00910
00911 /**
00912   * @brief  Disable the DSI wrapper.
00913   * @param  __HANDLE__: DSI handle
00914   * @retval None.
00915   */
00916 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
00917
00918 /**
00919   * @brief  Enables the DSI PLL.
00920   * @param  __HANDLE__: DSI handle
00921   * @retval None.
00922   */
00923 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN)
00924
00925 /**
00926   * @brief  Disables the DSI PLL.
00927   * @param  __HANDLE__: DSI handle
00928   * @retval None.
00929   */
00930 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
00931
00932 /**
00933   * @brief  Enables the DSI regulator.
00934   * @param  __HANDLE__: DSI handle
00935   * @retval None.
00936   */
00937 #define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN)
00938
00939 /**
00940   * @brief  Disables the DSI regulator.
00941   * @param  __HANDLE__: DSI handle
00942   * @retval None.
00943   */
00944 #define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
00945
00946 /**
00947   * @brief  Get the DSI pending flags.
00948   * @param  __HANDLE__: DSI handle.
00949   * @param  __FLAG__: Get the specified flag.
00950   *          This parameter can be any combination of the following values:
00951   *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag
00952   *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag
00953   *            @arg DSI_FLAG_BUSY : Busy Flag
00954   *            @arg DSI_FLAG_PLLLS: PLL Lock Status
00955   *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
00956   *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
00957   *            @arg DSI_FLAG_RRS  : Regulator Ready Flag
00958   *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag
00959   * @retval The state of FLAG (SET or RESET).
00960   */
00961 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
00962
00963 /**
00964   * @brief  Clears the DSI pending flags.
00965   * @param  __HANDLE__: DSI handle.
00966   * @param  __FLAG__: specifies the flag to clear.
00967   *          This parameter can be any combination of the following values:
00968   *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag
00969   *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag
00970   *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
00971   *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
00972   *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag
00973   * @retval None
00974   */
00975 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
00976
00977 /**
00978   * @brief  Enables the specified DSI interrupts.
00979   * @param  __HANDLE__: DSI handle.
00980   * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled.
00981   *          This parameter can be any combination of the following values:
00982   *            @arg DSI_IT_TE  : Tearing Effect Interrupt
00983   *            @arg DSI_IT_ER  : End of Refresh Interrupt
00984   *            @arg DSI_IT_PLLL: PLL Lock Interrupt
00985   *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
00986   *            @arg DSI_IT_RR  : Regulator Ready Interrupt
00987   * @retval None
00988   */
00989 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
00990
00991 /**
00992   * @brief  Disables the specified DSI interrupts.
00993   * @param  __HANDLE__: DSI handle
00994   * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled.
00995   *          This parameter can be any combination of the following values:
00996   *            @arg DSI_IT_TE  : Tearing Effect Interrupt
00997   *            @arg DSI_IT_ER  : End of Refresh Interrupt
00998   *            @arg DSI_IT_PLLL: PLL Lock Interrupt
00999   *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
01000   *            @arg DSI_IT_RR  : Regulator Ready Interrupt
01001   * @retval None
01002   */
01003 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
01004
01005 /**
01006   * @brief  Checks whether the specified DSI interrupt has occurred or not.
01007   * @param  __HANDLE__: DSI handle
01008   * @param  __INTERRUPT__: specifies the DSI interrupt source to check.
01009   *          This parameter can be one of the following values:
01010   *            @arg DSI_IT_TE  : Tearing Effect Interrupt
01011   *            @arg DSI_IT_ER  : End of Refresh Interrupt
01012   *            @arg DSI_IT_PLLL: PLL Lock Interrupt
01013   *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
01014   *            @arg DSI_IT_RR  : Regulator Ready Interrupt
01015   * @retval The state of INTERRUPT (SET or RESET).
01016   */
01017 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__))
01018
01019 /* Exported functions --------------------------------------------------------*/
01020 /** @defgroup DSI_Exported_Functions DSI Exported Functions
01021   * @{
01022   */
01023 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
01024 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
01025 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
01026 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
01027
01028 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
01029 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
01030 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
01031 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
01032
01033 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
01034 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
01035 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
01036 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
01037 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
01038 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimings);
01039 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
01040 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
01041 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
01042 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
01043 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
01044 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
01045 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
01046                                      uint32_t ChannelID,
01047                                      uint32_t Mode,
01048                                      uint32_t Param1,
01049                                      uint32_t Param2);
01050 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
01051                                     uint32_t ChannelID,
01052                                     uint32_t Mode,
01053                                     uint32_t Nbparams,
01054                                     uint32_t Param1,
01055                                     uint8_t* ParametersTable);
01056 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
01057                                uint32_t ChannelNbr,
01058                                uint8_t* Array,
01059                                uint32_t Size,
01060                                uint32_t Mode,
01061                                uint32_t DCSCmd,
01062                                uint8_t* ParametersTable);
01063 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
01064 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
01065 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
01066 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
01067
01068 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
01069 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
01070
01071 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
01072 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
01073 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
01074 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
01075 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
01076 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
01077 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
01078 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
01079 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
01080 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
01081
01082 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
01083 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
01084 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
01085 /**
01086   * @}
01087   */
01088
01089 /* Private types -------------------------------------------------------------*/
01090 /** @defgroup DSI_Private_Types DSI Private Types
01091   * @{
01092   */
01093
01094 /**
01095   * @}
01096   */
01097
01098 /* Private defines -----------------------------------------------------------*/
01099 /** @defgroup DSI_Private_Defines DSI Private Defines
01100   * @{
01101   */
01102
01103 /**
01104   * @}
01105   */
01106
01107 /* Private variables ---------------------------------------------------------*/
01108 /** @defgroup DSI_Private_Variables DSI Private Variables
01109   * @{
01110   */
01111
01112 /**
01113   * @}
01114   */
01115
01116 /* Private constants ---------------------------------------------------------*/
01117 /** @defgroup DSI_Private_Constants DSI Private Constants
01118   * @{
01119   */
01120 #define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037U) /*!< Maximum return packet configuration */
01121 /**
01122   * @}
01123   */
01124
01125 /* Private macros ------------------------------------------------------------*/
01126 /** @defgroup DSI_Private_Macros DSI Private Macros
01127   * @{
01128   */
01129 #define IS_DSI_PLL_NDIV(NDIV)                       ((10U <= (NDIV)) && ((NDIV) <= 125U))
01130 #define IS_DSI_PLL_IDF(IDF)                         (((IDF) == DSI_PLL_IN_DIV1) || \
01131                                                      ((IDF) == DSI_PLL_IN_DIV2) || \
01132                                                      ((IDF) == DSI_PLL_IN_DIV3) || \
01133                                                      ((IDF) == DSI_PLL_IN_DIV4) || \
01134                                                      ((IDF) == DSI_PLL_IN_DIV5) || \
01135                                                      ((IDF) == DSI_PLL_IN_DIV6) || \
01136                                                      ((IDF) == DSI_PLL_IN_DIV7))
01137 #define IS_DSI_PLL_ODF(ODF)                         (((ODF) == DSI_PLL_OUT_DIV1) || \
01138                                                      ((ODF) == DSI_PLL_OUT_DIV2) || \
01139                                                      ((ODF) == DSI_PLL_OUT_DIV4) || \
01140                                                      ((ODF) == DSI_PLL_OUT_DIV8))
01141 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
01142 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
01143 #define IS_DSI_FLOW_CONTROL(FlowControl)            (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
01144 #define IS_DSI_COLOR_CODING(ColorCoding)            ((ColorCoding) <= 5U)
01145 #define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
01146 #define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
01147 #define IS_DSI_VSYNC_POLARITY(VSYNC)                (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
01148 #define IS_DSI_HSYNC_POLARITY(HSYNC)                (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
01149 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)       (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
01150                                                      ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
01151                                                      ((VideoModeType) == DSI_VID_MODE_BURST))
01152 #define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
01153 #define IS_DSI_SHUT_DOWN(ShutDown)                  (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
01154 #define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
01155 #define IS_DSI_LP_HFP(LPHFP)                        (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
01156 #define IS_DSI_LP_HBP(LPHBP)                        (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
01157 #define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
01158 #define IS_DSI_LP_VFP(LPVFP)                        (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
01159 #define IS_DSI_LP_VBP(LPVBP)                        (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
01160 #define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
01161 #define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
01162 #define IS_DSI_TE_SOURCE(TESource)                  (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
01163 #define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
01164 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
01165 #define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
01166 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
01167 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
01168 #define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
01169 #define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
01170 #define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
01171 #define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
01172 #define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
01173 #define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
01174 #define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
01175 #define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
01176 #define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
01177 #define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
01178 #define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
01179 #define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
01180 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)        (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
01181                                                      ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
01182                                                      ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
01183                                                      ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
01184                                                      ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
01185 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE)         (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
01186                                                      ((MODE) == DSI_GEN_LONG_PKT_WRITE))
01187 #define IS_DSI_READ_PACKET_TYPE(MODE)               (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
01188                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
01189                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
01190                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
01191 #define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
01192 #define IS_DSI_LANE_GROUP(Lane)                     (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
01193 #define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
01194 #define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
01195 #define IS_DSI_PHY_TIMING(Timing)                   (((Timing) == DSI_TCLK_POST   ) || \
01196                                                      ((Timing) == DSI_TLPX_CLK    ) || \
01197                                                      ((Timing) == DSI_THS_EXIT    ) || \
01198                                                      ((Timing) == DSI_TLPX_DATA   ) || \
01199                                                      ((Timing) == DSI_THS_ZERO    ) || \
01200                                                      ((Timing) == DSI_THS_TRAIL   ) || \
01201                                                      ((Timing) == DSI_THS_PREPARE ) || \
01202                                                      ((Timing) == DSI_TCLK_ZERO   ) || \
01203                                                      ((Timing) == DSI_TCLK_PREPARE))
01204
01205 /**
01206   * @}
01207   */
01208
01209 /* Private functions prototypes ----------------------------------------------*/
01210 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
01211   * @{
01212   */
01213
01214 /**
01215   * @}
01216   */
01217
01218 /* Private functions ---------------------------------------------------------*/
01219 /** @defgroup DSI_Private_Functions DSI Private Functions
01220   * @{
01221   */
01222
01223 /**
01224   * @}
01225   */
01226
01227 /**
01228   * @}
01229   */
01230
01231 /**
01232   * @}
01233   */
01234 #endif /* STM32F469xx || STM32F479xx */
01235
01236 #ifdef __cplusplus
01237 }
01238 #endif
01239
01240 #endif /* __STM32F4xx_HAL_DSI_H */
01241
01242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_eth.c Source File

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stm32f4xx_hal_eth.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_eth.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   ETH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Ethernet (ETH) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#)Declare a ETH_HandleTypeDef handle structure, for example:
00021          ETH_HandleTypeDef  heth;
00022
00023       (#)Fill parameters of Init structure in heth handle
00024
00025       (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
00026
00027       (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
00028           (##) Enable the Ethernet interface clock using
00029                (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
00030                (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
00031                (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
00032
00033           (##) Initialize the related GPIO clocks
00034           (##) Configure Ethernet pin-out
00035           (##) Configure Ethernet NVIC interrupt (IT mode)
00036
00037       (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
00038           (##) HAL_ETH_DMATxDescListInit(); for Transmission process
00039           (##) HAL_ETH_DMARxDescListInit(); for Reception process
00040
00041       (#)Enable MAC and DMA transmission and reception:
00042           (##) HAL_ETH_Start();
00043
00044       (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
00045          the frame to MAC TX FIFO:
00046          (##) HAL_ETH_TransmitFrame();
00047
00048       (#)Poll for a received frame in ETH RX DMA Descriptors and get received
00049          frame parameters
00050          (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
00051
00052       (#) Get a received frame when an ETH RX interrupt occurs:
00053          (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
00054
00055       (#) Communicate with external PHY device:
00056          (##) Read a specific register from the PHY
00057               HAL_ETH_ReadPHYRegister();
00058          (##) Write data to a specific RHY register:
00059               HAL_ETH_WritePHYRegister();
00060
00061       (#) Configure the Ethernet MAC after ETH peripheral initialization
00062           HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
00063
00064       (#) Configure the Ethernet DMA after ETH peripheral initialization
00065           HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
00066
00067       -@- The PTP protocol and the DMA descriptors ring mode are not supported
00068           in this driver
00069
00070   @endverbatim
00071   ******************************************************************************
00072   * @attention
00073   *
00074   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00075   *
00076   * Redistribution and use in source and binary forms, with or without modification,
00077   * are permitted provided that the following conditions are met:
00078   *   1. Redistributions of source code must retain the above copyright notice,
00079   *      this list of conditions and the following disclaimer.
00080   *   2. Redistributions in binary form must reproduce the above copyright notice,
00081   *      this list of conditions and the following disclaimer in the documentation
00082   *      and/or other materials provided with the distribution.
00083   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00084   *      may be used to endorse or promote products derived from this software
00085   *      without specific prior written permission.
00086   *
00087   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00088   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00089   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00090   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00091   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00092   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00093   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00094   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00095   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00096   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00097   *
00098   ******************************************************************************
00099   */
00100
00101 /* Includes ------------------------------------------------------------------*/
00102 #include "stm32f4xx_hal.h"
00103
00104 /** @addtogroup STM32F4xx_HAL_Driver
00105   * @{
00106   */
00107
00108 /** @defgroup ETH ETH
00109   * @brief ETH HAL module driver
00110   * @{
00111   */
00112
00113 #ifdef HAL_ETH_MODULE_ENABLED
00114
00115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
00116     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00117
00118 /* Private typedef -----------------------------------------------------------*/
00119 /* Private define ------------------------------------------------------------*/
00120 /** @defgroup ETH_Private_Constants ETH Private Constants
00121   * @{
00122   */
00123 #define ETH_TIMEOUT_SWRESET                ((uint32_t)500U)
00124 #define ETH_TIMEOUT_LINKED_STATE          ((uint32_t)5000U)
00125 #define ETH_TIMEOUT_AUTONEGO_COMPLETED    ((uint32_t)5000U)
00126
00127 /**
00128   * @}
00129   */
00130 /* Private macro -------------------------------------------------------------*/
00131 /* Private variables ---------------------------------------------------------*/
00132 /* Private function prototypes -----------------------------------------------*/
00133 /** @defgroup ETH_Private_Functions ETH Private Functions
00134   * @{
00135   */
00136 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
00137 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
00138 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
00139 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
00140 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
00141 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
00142 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
00143 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
00144 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
00145 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
00146 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
00147
00148 /**
00149   * @}
00150   */
00151 /* Private functions ---------------------------------------------------------*/
00152
00153 /** @defgroup ETH_Exported_Functions ETH Exported Functions
00154   * @{
00155   */
00156
00157 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
00158   *  @brief   Initialization and Configuration functions
00159   *
00160   @verbatim
00161   ===============================================================================
00162             ##### Initialization and de-initialization functions #####
00163   ===============================================================================
00164   [..]  This section provides functions allowing to:
00165       (+) Initialize and configure the Ethernet peripheral
00166       (+) De-initialize the Ethernet peripheral
00167
00168   @endverbatim
00169   * @{
00170   */
00171
00172 /**
00173   * @brief  Initializes the Ethernet MAC and DMA according to default
00174   *         parameters.
00175   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00176   *         the configuration information for ETHERNET module
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
00180 {
00181   uint32_t tmpreg1 = 0U, phyreg = 0U;
00182   uint32_t hclk = 60000000U;
00183   uint32_t tickstart = 0U;
00184   uint32_t err = ETH_SUCCESS;
00185
00186   /* Check the ETH peripheral state */
00187   if(heth == NULL)
00188   {
00189     return HAL_ERROR;
00190   }
00191
00192   /* Check parameters */
00193   assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
00194   assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
00195   assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
00196   assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
00197
00198   if(heth->State == HAL_ETH_STATE_RESET)
00199   {
00200     /* Allocate lock resource and initialize it */
00201     heth->Lock = HAL_UNLOCKED;
00202     /* Init the low level hardware : GPIO, CLOCK, NVIC. */
00203     HAL_ETH_MspInit(heth);
00204   }
00205
00206   /* Enable SYSCFG Clock */
00207   __HAL_RCC_SYSCFG_CLK_ENABLE();
00208
00209   /* Select MII or RMII Mode*/
00210   SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
00211   SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
00212
00213   /* Ethernet Software reset */
00214   /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
00215   /* After reset all the registers holds their respective reset values */
00216   (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
00217
00218   /* Get tick */
00219   tickstart = HAL_GetTick();
00220
00221   /* Wait for software reset */
00222   while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
00223   {
00224     /* Check for the Timeout */
00225     if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
00226     {
00227       heth->State= HAL_ETH_STATE_TIMEOUT;
00228
00229       /* Process Unlocked */
00230       __HAL_UNLOCK(heth);
00231
00232       /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
00233          not available, please check your external PHY or the IO configuration */
00234       return HAL_TIMEOUT;
00235     }
00236   }
00237
00238   /*-------------------------------- MAC Initialization ----------------------*/
00239   /* Get the ETHERNET MACMIIAR value */
00240   tmpreg1 = (heth->Instance)->MACMIIAR;
00241   /* Clear CSR Clock Range CR[2:0] bits */
00242   tmpreg1 &= ETH_MACMIIAR_CR_MASK;
00243
00244   /* Get hclk frequency value */
00245   hclk = HAL_RCC_GetHCLKFreq();
00246
00247   /* Set CR bits depending on hclk value */
00248   if((hclk >= 20000000U)&&(hclk < 35000000U))
00249   {
00250     /* CSR Clock Range between 20-35 MHz */
00251     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
00252   }
00253   else if((hclk >= 35000000U)&&(hclk < 60000000U))
00254   {
00255     /* CSR Clock Range between 35-60 MHz */
00256     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
00257   }
00258   else if((hclk >= 60000000U)&&(hclk < 100000000U))
00259   {
00260     /* CSR Clock Range between 60-100 MHz */
00261     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
00262   }
00263   else if((hclk >= 100000000U)&&(hclk < 150000000U))
00264   {
00265     /* CSR Clock Range between 100-150 MHz */
00266     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
00267   }
00268   else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
00269   {
00270     /* CSR Clock Range between 150-183 MHz */
00271     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
00272   }
00273
00274   /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
00275   (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
00276
00277   /*-------------------- PHY initialization and configuration ----------------*/
00278   /* Put the PHY in reset mode */
00279   if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
00280   {
00281     /* In case of write timeout */
00282     err = ETH_ERROR;
00283
00284     /* Config MAC and DMA */
00285     ETH_MACDMAConfig(heth, err);
00286
00287     /* Set the ETH peripheral state to READY */
00288     heth->State = HAL_ETH_STATE_READY;
00289
00290     /* Return HAL_ERROR */
00291     return HAL_ERROR;
00292   }
00293
00294   /* Delay to assure PHY reset */
00295   HAL_Delay(PHY_RESET_DELAY);
00296
00297   if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
00298   {
00299     /* Get tick */
00300     tickstart = HAL_GetTick();
00301
00302     /* We wait for linked status */
00303     do
00304     {
00305       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
00306
00307       /* Check for the Timeout */
00308       if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
00309       {
00310         /* In case of write timeout */
00311         err = ETH_ERROR;
00312
00313         /* Config MAC and DMA */
00314         ETH_MACDMAConfig(heth, err);
00315
00316         heth->State= HAL_ETH_STATE_READY;
00317
00318         /* Process Unlocked */
00319         __HAL_UNLOCK(heth);
00320
00321         return HAL_TIMEOUT;
00322       }
00323     } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
00324
00325
00326     /* Enable Auto-Negotiation */
00327     if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
00328     {
00329       /* In case of write timeout */
00330       err = ETH_ERROR;
00331
00332       /* Config MAC and DMA */
00333       ETH_MACDMAConfig(heth, err);
00334
00335       /* Set the ETH peripheral state to READY */
00336       heth->State = HAL_ETH_STATE_READY;
00337
00338       /* Return HAL_ERROR */
00339       return HAL_ERROR;
00340     }
00341
00342     /* Get tick */
00343     tickstart = HAL_GetTick();
00344
00345     /* Wait until the auto-negotiation will be completed */
00346     do
00347     {
00348       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
00349
00350       /* Check for the Timeout */
00351       if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
00352       {
00353         /* In case of write timeout */
00354         err = ETH_ERROR;
00355
00356         /* Config MAC and DMA */
00357         ETH_MACDMAConfig(heth, err);
00358
00359         heth->State= HAL_ETH_STATE_READY;
00360
00361         /* Process Unlocked */
00362         __HAL_UNLOCK(heth);
00363
00364         return HAL_TIMEOUT;
00365       }
00366
00367     } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
00368
00369     /* Read the result of the auto-negotiation */
00370     if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
00371     {
00372       /* In case of write timeout */
00373       err = ETH_ERROR;
00374
00375       /* Config MAC and DMA */
00376       ETH_MACDMAConfig(heth, err);
00377
00378       /* Set the ETH peripheral state to READY */
00379       heth->State = HAL_ETH_STATE_READY;
00380
00381       /* Return HAL_ERROR */
00382       return HAL_ERROR;
00383     }
00384
00385     /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
00386     if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
00387     {
00388       /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
00389       (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
00390     }
00391     else
00392     {
00393       /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
00394       (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
00395     }
00396     /* Configure the MAC with the speed fixed by the auto-negotiation process */
00397     if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
00398     {
00399       /* Set Ethernet speed to 10M following the auto-negotiation */
00400       (heth->Init).Speed = ETH_SPEED_10M;
00401     }
00402     else
00403     {
00404       /* Set Ethernet speed to 100M following the auto-negotiation */
00405       (heth->Init).Speed = ETH_SPEED_100M;
00406     }
00407   }
00408   else /* AutoNegotiation Disable */
00409   {
00410     /* Check parameters */
00411     assert_param(IS_ETH_SPEED(heth->Init.Speed));
00412     assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
00413
00414     /* Set MAC Speed and Duplex Mode */
00415     if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
00416                                                 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
00417     {
00418       /* In case of write timeout */
00419       err = ETH_ERROR;
00420
00421       /* Config MAC and DMA */
00422       ETH_MACDMAConfig(heth, err);
00423
00424       /* Set the ETH peripheral state to READY */
00425       heth->State = HAL_ETH_STATE_READY;
00426
00427       /* Return HAL_ERROR */
00428       return HAL_ERROR;
00429     }
00430
00431     /* Delay to assure PHY configuration */
00432     HAL_Delay(PHY_CONFIG_DELAY);
00433   }
00434
00435   /* Config MAC and DMA */
00436   ETH_MACDMAConfig(heth, err);
00437
00438   /* Set ETH HAL State to Ready */
00439   heth->State= HAL_ETH_STATE_READY;
00440
00441   /* Return function status */
00442   return HAL_OK;
00443 }
00444
00445 /**
00446   * @brief  De-Initializes the ETH peripheral.
00447   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00448   *         the configuration information for ETHERNET module
00449   * @retval HAL status
00450   */
00451 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
00452 {
00453   /* Set the ETH peripheral state to BUSY */
00454   heth->State = HAL_ETH_STATE_BUSY;
00455
00456   /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
00457   HAL_ETH_MspDeInit(heth);
00458
00459   /* Set ETH HAL state to Disabled */
00460   heth->State= HAL_ETH_STATE_RESET;
00461
00462   /* Release Lock */
00463   __HAL_UNLOCK(heth);
00464
00465   /* Return function status */
00466   return HAL_OK;
00467 }
00468
00469 /**
00470   * @brief  Initializes the DMA Tx descriptors in chain mode.
00471   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00472   *         the configuration information for ETHERNET module
00473   * @param  DMATxDescTab: Pointer to the first Tx desc list
00474   * @param  TxBuff: Pointer to the first TxBuffer list
00475   * @param  TxBuffCount: Number of the used Tx desc in the list
00476   * @retval HAL status
00477   */
00478 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
00479 {
00480   uint32_t i = 0U;
00481   ETH_DMADescTypeDef *dmatxdesc;
00482
00483   /* Process Locked */
00484   __HAL_LOCK(heth);
00485
00486   /* Set the ETH peripheral state to BUSY */
00487   heth->State = HAL_ETH_STATE_BUSY;
00488
00489   /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
00490   heth->TxDesc = DMATxDescTab;
00491
00492   /* Fill each DMATxDesc descriptor with the right values */
00493   for(i=0U; i < TxBuffCount; i++)
00494   {
00495     /* Get the pointer on the ith member of the Tx Desc list */
00496     dmatxdesc = DMATxDescTab + i;
00497
00498     /* Set Second Address Chained bit */
00499     dmatxdesc->Status = ETH_DMATXDESC_TCH;
00500
00501     /* Set Buffer1 address pointer */
00502     dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
00503
00504     if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
00505     {
00506       /* Set the DMA Tx descriptors checksum insertion */
00507       dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
00508     }
00509
00510     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
00511     if(i < (TxBuffCount-1U))
00512     {
00513       /* Set next descriptor address register with next descriptor base address */
00514       dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
00515     }
00516     else
00517     {
00518       /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
00519       dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
00520     }
00521   }
00522
00523   /* Set Transmit Descriptor List Address Register */
00524   (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
00525
00526   /* Set ETH HAL State to Ready */
00527   heth->State= HAL_ETH_STATE_READY;
00528
00529   /* Process Unlocked */
00530   __HAL_UNLOCK(heth);
00531
00532   /* Return function status */
00533   return HAL_OK;
00534 }
00535
00536 /**
00537   * @brief  Initializes the DMA Rx descriptors in chain mode.
00538   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00539   *         the configuration information for ETHERNET module
00540   * @param  DMARxDescTab: Pointer to the first Rx desc list
00541   * @param  RxBuff: Pointer to the first RxBuffer list
00542   * @param  RxBuffCount: Number of the used Rx desc in the list
00543   * @retval HAL status
00544   */
00545 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
00546 {
00547   uint32_t i = 0U;
00548   ETH_DMADescTypeDef *DMARxDesc;
00549
00550   /* Process Locked */
00551   __HAL_LOCK(heth);
00552
00553   /* Set the ETH peripheral state to BUSY */
00554   heth->State = HAL_ETH_STATE_BUSY;
00555
00556   /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
00557   heth->RxDesc = DMARxDescTab;
00558
00559   /* Fill each DMARxDesc descriptor with the right values */
00560   for(i=0U; i < RxBuffCount; i++)
00561   {
00562     /* Get the pointer on the ith member of the Rx Desc list */
00563     DMARxDesc = DMARxDescTab+i;
00564
00565     /* Set Own bit of the Rx descriptor Status */
00566     DMARxDesc->Status = ETH_DMARXDESC_OWN;
00567
00568     /* Set Buffer1 size and Second Address Chained bit */
00569     DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
00570
00571     /* Set Buffer1 address pointer */
00572     DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
00573
00574     if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
00575     {
00576       /* Enable Ethernet DMA Rx Descriptor interrupt */
00577       DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
00578     }
00579
00580     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
00581     if(i < (RxBuffCount-1U))
00582     {
00583       /* Set next descriptor address register with next descriptor base address */
00584       DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
00585     }
00586     else
00587     {
00588       /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
00589       DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
00590     }
00591   }
00592
00593   /* Set Receive Descriptor List Address Register */
00594   (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
00595
00596   /* Set ETH HAL State to Ready */
00597   heth->State= HAL_ETH_STATE_READY;
00598
00599   /* Process Unlocked */
00600   __HAL_UNLOCK(heth);
00601
00602   /* Return function status */
00603   return HAL_OK;
00604 }
00605
00606 /**
00607   * @brief  Initializes the ETH MSP.
00608   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00609   *         the configuration information for ETHERNET module
00610   * @retval None
00611   */
00612 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
00613 {
00614   /* Prevent unused argument(s) compilation warning */
00615   UNUSED(heth);
00616   /* NOTE : This function Should not be modified, when the callback is needed,
00617   the HAL_ETH_MspInit could be implemented in the user file
00618   */
00619 }
00620
00621 /**
00622   * @brief  DeInitializes ETH MSP.
00623   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00624   *         the configuration information for ETHERNET module
00625   * @retval None
00626   */
00627 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
00628 {
00629   /* Prevent unused argument(s) compilation warning */
00630   UNUSED(heth);
00631   /* NOTE : This function Should not be modified, when the callback is needed,
00632   the HAL_ETH_MspDeInit could be implemented in the user file
00633   */
00634 }
00635
00636 /**
00637   * @}
00638   */
00639
00640 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
00641   *  @brief   Data transfers functions
00642   *
00643   @verbatim
00644   ==============================================================================
00645                           ##### IO operation functions #####
00646   ==============================================================================
00647   [..]  This section provides functions allowing to:
00648         (+) Transmit a frame
00649             HAL_ETH_TransmitFrame();
00650         (+) Receive a frame
00651             HAL_ETH_GetReceivedFrame();
00652             HAL_ETH_GetReceivedFrame_IT();
00653         (+) Read from an External PHY register
00654             HAL_ETH_ReadPHYRegister();
00655         (+) Write to an External PHY register
00656             HAL_ETH_WritePHYRegister();
00657
00658   @endverbatim
00659
00660   * @{
00661   */
00662
00663 /**
00664   * @brief  Sends an Ethernet frame.
00665   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00666   *         the configuration information for ETHERNET module
00667   * @param  FrameLength: Amount of data to be sent
00668   * @retval HAL status
00669   */
00670 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
00671 {
00672   uint32_t bufcount = 0U, size = 0U, i = 0U;
00673
00674   /* Process Locked */
00675   __HAL_LOCK(heth);
00676
00677   /* Set the ETH peripheral state to BUSY */
00678   heth->State = HAL_ETH_STATE_BUSY;
00679
00680   if (FrameLength == 0U)
00681   {
00682     /* Set ETH HAL state to READY */
00683     heth->State = HAL_ETH_STATE_READY;
00684
00685     /* Process Unlocked */
00686     __HAL_UNLOCK(heth);
00687
00688     return  HAL_ERROR;
00689   }
00690
00691   /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
00692   if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
00693   {
00694     /* OWN bit set */
00695     heth->State = HAL_ETH_STATE_BUSY_TX;
00696
00697     /* Process Unlocked */
00698     __HAL_UNLOCK(heth);
00699
00700     return HAL_ERROR;
00701   }
00702
00703   /* Get the number of needed Tx buffers for the current frame */
00704   if (FrameLength > ETH_TX_BUF_SIZE)
00705   {
00706     bufcount = FrameLength/ETH_TX_BUF_SIZE;
00707     if (FrameLength % ETH_TX_BUF_SIZE)
00708     {
00709       bufcount++;
00710     }
00711   }
00712   else
00713   {
00714     bufcount = 1U;
00715   }
00716   if (bufcount == 1U)
00717   {
00718     /* Set LAST and FIRST segment */
00719     heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
00720     /* Set frame size */
00721     heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
00722     /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
00723     heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
00724     /* Point to next descriptor */
00725     heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
00726   }
00727   else
00728   {
00729     for (i=0U; i< bufcount; i++)
00730     {
00731       /* Clear FIRST and LAST segment bits */
00732       heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
00733
00734       if (i == 0U)
00735       {
00736         /* Setting the first segment bit */
00737         heth->TxDesc->Status |= ETH_DMATXDESC_FS;
00738       }
00739
00740       /* Program size */
00741       heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
00742
00743       if (i == (bufcount-1U))
00744       {
00745         /* Setting the last segment bit */
00746         heth->TxDesc->Status |= ETH_DMATXDESC_LS;
00747         size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
00748         heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
00749       }
00750
00751       /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
00752       heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
00753       /* point to next descriptor */
00754       heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
00755     }
00756   }
00757
00758   /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
00759   if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
00760   {
00761     /* Clear TBUS ETHERNET DMA flag */
00762     (heth->Instance)->DMASR = ETH_DMASR_TBUS;
00763     /* Resume DMA transmission*/
00764     (heth->Instance)->DMATPDR = 0U;
00765   }
00766
00767   /* Set ETH HAL State to Ready */
00768   heth->State = HAL_ETH_STATE_READY;
00769
00770   /* Process Unlocked */
00771   __HAL_UNLOCK(heth);
00772
00773   /* Return function status */
00774   return HAL_OK;
00775 }
00776
00777 /**
00778   * @brief  Checks for received frames.
00779   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00780   *         the configuration information for ETHERNET module
00781   * @retval HAL status
00782   */
00783 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
00784 {
00785   uint32_t framelength = 0U;
00786
00787   /* Process Locked */
00788   __HAL_LOCK(heth);
00789
00790   /* Check the ETH state to BUSY */
00791   heth->State = HAL_ETH_STATE_BUSY;
00792
00793   /* Check if segment is not owned by DMA */
00794   /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
00795   if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
00796   {
00797     /* Check if last segment */
00798     if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
00799     {
00800       /* increment segment count */
00801       (heth->RxFrameInfos).SegCount++;
00802
00803       /* Check if last segment is first segment: one segment contains the frame */
00804       if ((heth->RxFrameInfos).SegCount == 1U)
00805       {
00806         (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
00807       }
00808
00809       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
00810
00811       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
00812       framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
00813       heth->RxFrameInfos.length = framelength;
00814
00815       /* Get the address of the buffer start address */
00816       heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
00817       /* point to next descriptor */
00818       heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
00819
00820       /* Set HAL State to Ready */
00821       heth->State = HAL_ETH_STATE_READY;
00822
00823       /* Process Unlocked */
00824       __HAL_UNLOCK(heth);
00825
00826       /* Return function status */
00827       return HAL_OK;
00828     }
00829     /* Check if first segment */
00830     else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
00831     {
00832       (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
00833       (heth->RxFrameInfos).LSRxDesc = NULL;
00834       (heth->RxFrameInfos).SegCount = 1U;
00835       /* Point to next descriptor */
00836       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00837     }
00838     /* Check if intermediate segment */
00839     else
00840     {
00841       (heth->RxFrameInfos).SegCount++;
00842       /* Point to next descriptor */
00843       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00844     }
00845   }
00846
00847   /* Set ETH HAL State to Ready */
00848   heth->State = HAL_ETH_STATE_READY;
00849
00850   /* Process Unlocked */
00851   __HAL_UNLOCK(heth);
00852
00853   /* Return function status */
00854   return HAL_ERROR;
00855 }
00856
00857 /**
00858   * @brief  Gets the Received frame in interrupt mode.
00859   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00860   *         the configuration information for ETHERNET module
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
00864 {
00865   uint32_t descriptorscancounter = 0U;
00866
00867   /* Process Locked */
00868   __HAL_LOCK(heth);
00869
00870   /* Set ETH HAL State to BUSY */
00871   heth->State = HAL_ETH_STATE_BUSY;
00872
00873   /* Scan descriptors owned by CPU */
00874   while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
00875   {
00876     /* Just for security */
00877     descriptorscancounter++;
00878
00879     /* Check if first segment in frame */
00880     /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
00881     if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
00882     {
00883       heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
00884       heth->RxFrameInfos.SegCount = 1U;
00885       /* Point to next descriptor */
00886       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00887     }
00888     /* Check if intermediate segment */
00889     /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
00890     else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
00891     {
00892       /* Increment segment count */
00893       (heth->RxFrameInfos.SegCount)++;
00894       /* Point to next descriptor */
00895       heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
00896     }
00897     /* Should be last segment */
00898     else
00899     {
00900       /* Last segment */
00901       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
00902
00903       /* Increment segment count */
00904       (heth->RxFrameInfos.SegCount)++;
00905
00906       /* Check if last segment is first segment: one segment contains the frame */
00907       if ((heth->RxFrameInfos.SegCount) == 1U)
00908       {
00909         heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
00910       }
00911
00912       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
00913       heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
00914
00915       /* Get the address of the buffer start address */
00916       heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
00917
00918       /* Point to next descriptor */
00919       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00920
00921       /* Set HAL State to Ready */
00922       heth->State = HAL_ETH_STATE_READY;
00923
00924       /* Process Unlocked */
00925       __HAL_UNLOCK(heth);
00926
00927       /* Return function status */
00928       return HAL_OK;
00929     }
00930   }
00931
00932   /* Set HAL State to Ready */
00933   heth->State = HAL_ETH_STATE_READY;
00934
00935   /* Process Unlocked */
00936   __HAL_UNLOCK(heth);
00937
00938   /* Return function status */
00939   return HAL_ERROR;
00940 }
00941
00942 /**
00943   * @brief  This function handles ETH interrupt request.
00944   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00945   *         the configuration information for ETHERNET module
00946   * @retval HAL status
00947   */
00948 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
00949 {
00950   /* Frame received */
00951   if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
00952   {
00953     /* Receive complete callback */
00954     HAL_ETH_RxCpltCallback(heth);
00955
00956      /* Clear the Eth DMA Rx IT pending bits */
00957     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
00958
00959     /* Set HAL State to Ready */
00960     heth->State = HAL_ETH_STATE_READY;
00961
00962     /* Process Unlocked */
00963     __HAL_UNLOCK(heth);
00964
00965   }
00966   /* Frame transmitted */
00967   else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
00968   {
00969     /* Transfer complete callback */
00970     HAL_ETH_TxCpltCallback(heth);
00971
00972     /* Clear the Eth DMA Tx IT pending bits */
00973     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
00974
00975     /* Set HAL State to Ready */
00976     heth->State = HAL_ETH_STATE_READY;
00977
00978     /* Process Unlocked */
00979     __HAL_UNLOCK(heth);
00980   }
00981
00982   /* Clear the interrupt flags */
00983   __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
00984
00985   /* ETH DMA Error */
00986   if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
00987   {
00988     /* Ethernet Error callback */
00989     HAL_ETH_ErrorCallback(heth);
00990
00991     /* Clear the interrupt flags */
00992     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
00993
00994     /* Set HAL State to Ready */
00995     heth->State = HAL_ETH_STATE_READY;
00996
00997     /* Process Unlocked */
00998     __HAL_UNLOCK(heth);
00999   }
01000 }
01001
01002 /**
01003   * @brief  Tx Transfer completed callbacks.
01004   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01005   *         the configuration information for ETHERNET module
01006   * @retval None
01007   */
01008 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
01009 {
01010   /* Prevent unused argument(s) compilation warning */
01011   UNUSED(heth);
01012   /* NOTE : This function Should not be modified, when the callback is needed,
01013   the HAL_ETH_TxCpltCallback could be implemented in the user file
01014   */
01015 }
01016
01017 /**
01018   * @brief  Rx Transfer completed callbacks.
01019   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01020   *         the configuration information for ETHERNET module
01021   * @retval None
01022   */
01023 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
01024 {
01025   /* Prevent unused argument(s) compilation warning */
01026   UNUSED(heth);
01027   /* NOTE : This function Should not be modified, when the callback is needed,
01028   the HAL_ETH_TxCpltCallback could be implemented in the user file
01029   */
01030 }
01031
01032 /**
01033   * @brief  Ethernet transfer error callbacks
01034   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01035   *         the configuration information for ETHERNET module
01036   * @retval None
01037   */
01038 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
01039 {
01040   /* Prevent unused argument(s) compilation warning */
01041   UNUSED(heth);
01042   /* NOTE : This function Should not be modified, when the callback is needed,
01043   the HAL_ETH_TxCpltCallback could be implemented in the user file
01044   */
01045 }
01046
01047 /**
01048   * @brief  Reads a PHY register
01049   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01050   *         the configuration information for ETHERNET module
01051   * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
01052   *                This parameter can be one of the following values:
01053   *                   PHY_BCR: Transceiver Basic Control Register,
01054   *                   PHY_BSR: Transceiver Basic Status Register.
01055   *                   More PHY register could be read depending on the used PHY
01056   * @param RegValue: PHY register value
01057   * @retval HAL status
01058   */
01059 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
01060 {
01061   uint32_t tmpreg1 = 0U;
01062   uint32_t tickstart = 0U;
01063
01064   /* Check parameters */
01065   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
01066
01067   /* Check the ETH peripheral state */
01068   if(heth->State == HAL_ETH_STATE_BUSY_RD)
01069   {
01070     return HAL_BUSY;
01071   }
01072   /* Set ETH HAL State to BUSY_RD */
01073   heth->State = HAL_ETH_STATE_BUSY_RD;
01074
01075   /* Get the ETHERNET MACMIIAR value */
01076   tmpreg1 = heth->Instance->MACMIIAR;
01077
01078   /* Keep only the CSR Clock Range CR[2:0] bits value */
01079   tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
01080
01081   /* Prepare the MII address register value */
01082   tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address   */
01083   tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR);                   /* Set the PHY register address */
01084   tmpreg1 &= ~ETH_MACMIIAR_MW;                                           /* Set the read mode            */
01085   tmpreg1 |= ETH_MACMIIAR_MB;                                            /* Set the MII Busy bit         */
01086
01087   /* Write the result value into the MII Address register */
01088   heth->Instance->MACMIIAR = tmpreg1;
01089
01090   /* Get tick */
01091   tickstart = HAL_GetTick();
01092
01093   /* Check for the Busy flag */
01094   while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
01095   {
01096     /* Check for the Timeout */
01097     if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
01098     {
01099       heth->State= HAL_ETH_STATE_READY;
01100
01101       /* Process Unlocked */
01102       __HAL_UNLOCK(heth);
01103
01104       return HAL_TIMEOUT;
01105     }
01106
01107     tmpreg1 = heth->Instance->MACMIIAR;
01108   }
01109
01110   /* Get MACMIIDR value */
01111   *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
01112
01113   /* Set ETH HAL State to READY */
01114   heth->State = HAL_ETH_STATE_READY;
01115
01116   /* Return function status */
01117   return HAL_OK;
01118 }
01119
01120 /**
01121   * @brief  Writes to a PHY register.
01122   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01123   *         the configuration information for ETHERNET module
01124   * @param  PHYReg: PHY register address, is the index of one of the 32 PHY register.
01125   *          This parameter can be one of the following values:
01126   *             PHY_BCR: Transceiver Control Register.
01127   *             More PHY register could be written depending on the used PHY
01128   * @param  RegValue: the value to write
01129   * @retval HAL status
01130   */
01131 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
01132 {
01133   uint32_t tmpreg1 = 0U;
01134   uint32_t tickstart = 0U;
01135
01136   /* Check parameters */
01137   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
01138
01139   /* Check the ETH peripheral state */
01140   if(heth->State == HAL_ETH_STATE_BUSY_WR)
01141   {
01142     return HAL_BUSY;
01143   }
01144   /* Set ETH HAL State to BUSY_WR */
01145   heth->State = HAL_ETH_STATE_BUSY_WR;
01146
01147   /* Get the ETHERNET MACMIIAR value */
01148   tmpreg1 = heth->Instance->MACMIIAR;
01149
01150   /* Keep only the CSR Clock Range CR[2:0] bits value */
01151   tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
01152
01153   /* Prepare the MII register address value */
01154   tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
01155   tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR);                 /* Set the PHY register address */
01156   tmpreg1 |= ETH_MACMIIAR_MW;                                           /* Set the write mode */
01157   tmpreg1 |= ETH_MACMIIAR_MB;                                           /* Set the MII Busy bit */
01158
01159   /* Give the value to the MII data register */
01160   heth->Instance->MACMIIDR = (uint16_t)RegValue;
01161
01162   /* Write the result value into the MII Address register */
01163   heth->Instance->MACMIIAR = tmpreg1;
01164
01165   /* Get tick */
01166   tickstart = HAL_GetTick();
01167
01168   /* Check for the Busy flag */
01169   while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
01170   {
01171     /* Check for the Timeout */
01172     if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
01173     {
01174       heth->State= HAL_ETH_STATE_READY;
01175
01176       /* Process Unlocked */
01177       __HAL_UNLOCK(heth);
01178
01179       return HAL_TIMEOUT;
01180     }
01181
01182     tmpreg1 = heth->Instance->MACMIIAR;
01183   }
01184
01185   /* Set ETH HAL State to READY */
01186   heth->State = HAL_ETH_STATE_READY;
01187
01188   /* Return function status */
01189   return HAL_OK;
01190 }
01191
01192 /**
01193   * @}
01194   */
01195
01196 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
01197  *  @brief    Peripheral Control functions
01198  *
01199 @verbatim
01200  ===============================================================================
01201                   ##### Peripheral Control functions #####
01202  ===============================================================================
01203     [..]  This section provides functions allowing to:
01204       (+) Enable MAC and DMA transmission and reception.
01205           HAL_ETH_Start();
01206       (+) Disable MAC and DMA transmission and reception.
01207           HAL_ETH_Stop();
01208       (+) Set the MAC configuration in runtime mode
01209           HAL_ETH_ConfigMAC();
01210       (+) Set the DMA configuration in runtime mode
01211           HAL_ETH_ConfigDMA();
01212
01213 @endverbatim
01214   * @{
01215   */
01216
01217  /**
01218   * @brief  Enables Ethernet MAC and DMA reception/transmission
01219   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01220   *         the configuration information for ETHERNET module
01221   * @retval HAL status
01222   */
01223 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
01224 {
01225   /* Process Locked */
01226   __HAL_LOCK(heth);
01227
01228   /* Set the ETH peripheral state to BUSY */
01229   heth->State = HAL_ETH_STATE_BUSY;
01230
01231   /* Enable transmit state machine of the MAC for transmission on the MII */
01232   ETH_MACTransmissionEnable(heth);
01233
01234   /* Enable receive state machine of the MAC for reception from the MII */
01235   ETH_MACReceptionEnable(heth);
01236
01237   /* Flush Transmit FIFO */
01238   ETH_FlushTransmitFIFO(heth);
01239
01240   /* Start DMA transmission */
01241   ETH_DMATransmissionEnable(heth);
01242
01243   /* Start DMA reception */
01244   ETH_DMAReceptionEnable(heth);
01245
01246   /* Set the ETH state to READY*/
01247   heth->State= HAL_ETH_STATE_READY;
01248
01249   /* Process Unlocked */
01250   __HAL_UNLOCK(heth);
01251
01252   /* Return function status */
01253   return HAL_OK;
01254 }
01255
01256 /**
01257   * @brief  Stop Ethernet MAC and DMA reception/transmission
01258   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01259   *         the configuration information for ETHERNET module
01260   * @retval HAL status
01261   */
01262 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
01263 {
01264   /* Process Locked */
01265   __HAL_LOCK(heth);
01266
01267   /* Set the ETH peripheral state to BUSY */
01268   heth->State = HAL_ETH_STATE_BUSY;
01269
01270   /* Stop DMA transmission */
01271   ETH_DMATransmissionDisable(heth);
01272
01273   /* Stop DMA reception */
01274   ETH_DMAReceptionDisable(heth);
01275
01276   /* Disable receive state machine of the MAC for reception from the MII */
01277   ETH_MACReceptionDisable(heth);
01278
01279   /* Flush Transmit FIFO */
01280   ETH_FlushTransmitFIFO(heth);
01281
01282   /* Disable transmit state machine of the MAC for transmission on the MII */
01283   ETH_MACTransmissionDisable(heth);
01284
01285   /* Set the ETH state*/
01286   heth->State = HAL_ETH_STATE_READY;
01287
01288   /* Process Unlocked */
01289   __HAL_UNLOCK(heth);
01290
01291   /* Return function status */
01292   return HAL_OK;
01293 }
01294
01295 /**
01296   * @brief  Set ETH MAC Configuration.
01297   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01298   *         the configuration information for ETHERNET module
01299   * @param  macconf: MAC Configuration structure
01300   * @retval HAL status
01301   */
01302 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
01303 {
01304   uint32_t tmpreg1 = 0U;
01305
01306   /* Process Locked */
01307   __HAL_LOCK(heth);
01308
01309   /* Set the ETH peripheral state to BUSY */
01310   heth->State= HAL_ETH_STATE_BUSY;
01311
01312   assert_param(IS_ETH_SPEED(heth->Init.Speed));
01313   assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
01314
01315   if (macconf != NULL)
01316   {
01317     /* Check the parameters */
01318     assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
01319     assert_param(IS_ETH_JABBER(macconf->Jabber));
01320     assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
01321     assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
01322     assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
01323     assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
01324     assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
01325     assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
01326     assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
01327     assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
01328     assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
01329     assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
01330     assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
01331     assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
01332     assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
01333     assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
01334     assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
01335     assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
01336     assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
01337     assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
01338     assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
01339     assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
01340     assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
01341     assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
01342     assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
01343     assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
01344     assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
01345
01346     /*------------------------ ETHERNET MACCR Configuration --------------------*/
01347     /* Get the ETHERNET MACCR value */
01348     tmpreg1 = (heth->Instance)->MACCR;
01349     /* Clear WD, PCE, PS, TE and RE bits */
01350     tmpreg1 &= ETH_MACCR_CLEAR_MASK;
01351
01352     tmpreg1 |= (uint32_t)(macconf->Watchdog |
01353                          macconf->Jabber |
01354                          macconf->InterFrameGap |
01355                          macconf->CarrierSense |
01356                          (heth->Init).Speed |
01357                          macconf->ReceiveOwn |
01358                          macconf->LoopbackMode |
01359                          (heth->Init).DuplexMode |
01360                          macconf->ChecksumOffload |
01361                          macconf->RetryTransmission |
01362                          macconf->AutomaticPadCRCStrip |
01363                          macconf->BackOffLimit |
01364                          macconf->DeferralCheck);
01365
01366     /* Write to ETHERNET MACCR */
01367     (heth->Instance)->MACCR = (uint32_t)tmpreg1;
01368
01369     /* Wait until the write operation will be taken into account :
01370     at least four TX_CLK/RX_CLK clock cycles */
01371     tmpreg1 = (heth->Instance)->MACCR;
01372     HAL_Delay(ETH_REG_WRITE_DELAY);
01373     (heth->Instance)->MACCR = tmpreg1;
01374
01375     /*----------------------- ETHERNET MACFFR Configuration --------------------*/
01376     /* Write to ETHERNET MACFFR */
01377     (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
01378                                           macconf->SourceAddrFilter |
01379                                           macconf->PassControlFrames |
01380                                           macconf->BroadcastFramesReception |
01381                                           macconf->DestinationAddrFilter |
01382                                           macconf->PromiscuousMode |
01383                                           macconf->MulticastFramesFilter |
01384                                           macconf->UnicastFramesFilter);
01385
01386      /* Wait until the write operation will be taken into account :
01387      at least four TX_CLK/RX_CLK clock cycles */
01388      tmpreg1 = (heth->Instance)->MACFFR;
01389      HAL_Delay(ETH_REG_WRITE_DELAY);
01390      (heth->Instance)->MACFFR = tmpreg1;
01391
01392      /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
01393      /* Write to ETHERNET MACHTHR */
01394      (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
01395
01396      /* Write to ETHERNET MACHTLR */
01397      (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
01398      /*----------------------- ETHERNET MACFCR Configuration --------------------*/
01399
01400      /* Get the ETHERNET MACFCR value */
01401      tmpreg1 = (heth->Instance)->MACFCR;
01402      /* Clear xx bits */
01403      tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
01404
01405      tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
01406                           macconf->ZeroQuantaPause |
01407                           macconf->PauseLowThreshold |
01408                           macconf->UnicastPauseFrameDetect |
01409                           macconf->ReceiveFlowControl |
01410                           macconf->TransmitFlowControl);
01411
01412      /* Write to ETHERNET MACFCR */
01413      (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
01414
01415      /* Wait until the write operation will be taken into account :
01416      at least four TX_CLK/RX_CLK clock cycles */
01417      tmpreg1 = (heth->Instance)->MACFCR;
01418      HAL_Delay(ETH_REG_WRITE_DELAY);
01419      (heth->Instance)->MACFCR = tmpreg1;
01420
01421      /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
01422      (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
01423                                               macconf->VLANTagIdentifier);
01424
01425       /* Wait until the write operation will be taken into account :
01426       at least four TX_CLK/RX_CLK clock cycles */
01427       tmpreg1 = (heth->Instance)->MACVLANTR;
01428       HAL_Delay(ETH_REG_WRITE_DELAY);
01429       (heth->Instance)->MACVLANTR = tmpreg1;
01430   }
01431   else /* macconf == NULL : here we just configure Speed and Duplex mode */
01432   {
01433     /*------------------------ ETHERNET MACCR Configuration --------------------*/
01434     /* Get the ETHERNET MACCR value */
01435     tmpreg1 = (heth->Instance)->MACCR;
01436
01437     /* Clear FES and DM bits */
01438     tmpreg1 &= ~((uint32_t)0x00004800U);
01439
01440     tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
01441
01442     /* Write to ETHERNET MACCR */
01443     (heth->Instance)->MACCR = (uint32_t)tmpreg1;
01444
01445     /* Wait until the write operation will be taken into account:
01446     at least four TX_CLK/RX_CLK clock cycles */
01447     tmpreg1 = (heth->Instance)->MACCR;
01448     HAL_Delay(ETH_REG_WRITE_DELAY);
01449     (heth->Instance)->MACCR = tmpreg1;
01450   }
01451
01452   /* Set the ETH state to Ready */
01453   heth->State= HAL_ETH_STATE_READY;
01454
01455   /* Process Unlocked */
01456   __HAL_UNLOCK(heth);
01457
01458   /* Return function status */
01459   return HAL_OK;
01460 }
01461
01462 /**
01463   * @brief  Sets ETH DMA Configuration.
01464   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01465   *         the configuration information for ETHERNET module
01466   * @param  dmaconf: DMA Configuration structure
01467   * @retval HAL status
01468   */
01469 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
01470 {
01471   uint32_t tmpreg1 = 0U;
01472
01473   /* Process Locked */
01474   __HAL_LOCK(heth);
01475
01476   /* Set the ETH peripheral state to BUSY */
01477   heth->State= HAL_ETH_STATE_BUSY;
01478
01479   /* Check parameters */
01480   assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
01481   assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
01482   assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
01483   assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
01484   assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
01485   assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
01486   assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
01487   assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
01488   assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
01489   assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
01490   assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
01491   assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
01492   assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
01493   assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
01494   assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
01495   assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
01496
01497   /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
01498   /* Get the ETHERNET DMAOMR value */
01499   tmpreg1 = (heth->Instance)->DMAOMR;
01500   /* Clear xx bits */
01501   tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
01502
01503   tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
01504                        dmaconf->ReceiveStoreForward |
01505                        dmaconf->FlushReceivedFrame |
01506                        dmaconf->TransmitStoreForward |
01507                        dmaconf->TransmitThresholdControl |
01508                        dmaconf->ForwardErrorFrames |
01509                        dmaconf->ForwardUndersizedGoodFrames |
01510                        dmaconf->ReceiveThresholdControl |
01511                        dmaconf->SecondFrameOperate);
01512
01513   /* Write to ETHERNET DMAOMR */
01514   (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
01515
01516   /* Wait until the write operation will be taken into account:
01517   at least four TX_CLK/RX_CLK clock cycles */
01518   tmpreg1 = (heth->Instance)->DMAOMR;
01519   HAL_Delay(ETH_REG_WRITE_DELAY);
01520   (heth->Instance)->DMAOMR = tmpreg1;
01521
01522   /*----------------------- ETHERNET DMABMR Configuration --------------------*/
01523   (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
01524                                          dmaconf->FixedBurst |
01525                                          dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
01526                                          dmaconf->TxDMABurstLength |
01527                                          dmaconf->EnhancedDescriptorFormat |
01528                                          (dmaconf->DescriptorSkipLength << 2U) |
01529                                          dmaconf->DMAArbitration |
01530                                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
01531
01532    /* Wait until the write operation will be taken into account:
01533       at least four TX_CLK/RX_CLK clock cycles */
01534    tmpreg1 = (heth->Instance)->DMABMR;
01535    HAL_Delay(ETH_REG_WRITE_DELAY);
01536    (heth->Instance)->DMABMR = tmpreg1;
01537
01538    /* Set the ETH state to Ready */
01539    heth->State= HAL_ETH_STATE_READY;
01540
01541    /* Process Unlocked */
01542    __HAL_UNLOCK(heth);
01543
01544    /* Return function status */
01545    return HAL_OK;
01546 }
01547
01548 /**
01549   * @}
01550   */
01551
01552 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
01553   *  @brief   Peripheral State functions
01554   *
01555   @verbatim
01556   ===============================================================================
01557                          ##### Peripheral State functions #####
01558   ===============================================================================
01559   [..]
01560   This subsection permits to get in run-time the status of the peripheral
01561   and the data flow.
01562        (+) Get the ETH handle state:
01563            HAL_ETH_GetState();
01564
01565
01566   @endverbatim
01567   * @{
01568   */
01569
01570 /**
01571   * @brief  Return the ETH HAL state
01572   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01573   *         the configuration information for ETHERNET module
01574   * @retval HAL state
01575   */
01576 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
01577 {
01578   /* Return ETH state */
01579   return heth->State;
01580 }
01581
01582 /**
01583   * @}
01584   */
01585
01586 /**
01587   * @}
01588   */
01589
01590 /** @addtogroup ETH_Private_Functions
01591   * @{
01592   */
01593
01594 /**
01595   * @brief  Configures Ethernet MAC and DMA with default parameters.
01596   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01597   *         the configuration information for ETHERNET module
01598   * @param  err: Ethernet Init error
01599   * @retval HAL status
01600   */
01601 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
01602 {
01603   ETH_MACInitTypeDef macinit;
01604   ETH_DMAInitTypeDef dmainit;
01605   uint32_t tmpreg1 = 0U;
01606
01607   if (err != ETH_SUCCESS) /* Auto-negotiation failed */
01608   {
01609     /* Set Ethernet duplex mode to Full-duplex */
01610     (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
01611
01612     /* Set Ethernet speed to 100M */
01613     (heth->Init).Speed = ETH_SPEED_100M;
01614   }
01615
01616   /* Ethernet MAC default initialization **************************************/
01617   macinit.Watchdog = ETH_WATCHDOG_ENABLE;
01618   macinit.Jabber = ETH_JABBER_ENABLE;
01619   macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
01620   macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
01621   macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
01622   macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
01623   if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
01624   {
01625     macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
01626   }
01627   else
01628   {
01629     macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
01630   }
01631   macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
01632   macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
01633   macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
01634   macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
01635   macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
01636   macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
01637   macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
01638   macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
01639   macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
01640   macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
01641   macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
01642   macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
01643   macinit.HashTableHigh = 0x0U;
01644   macinit.HashTableLow = 0x0U;
01645   macinit.PauseTime = 0x0U;
01646   macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
01647   macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
01648   macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
01649   macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
01650   macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
01651   macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
01652   macinit.VLANTagIdentifier = 0x0U;
01653
01654   /*------------------------ ETHERNET MACCR Configuration --------------------*/
01655   /* Get the ETHERNET MACCR value */
01656   tmpreg1 = (heth->Instance)->MACCR;
01657   /* Clear WD, PCE, PS, TE and RE bits */
01658   tmpreg1 &= ETH_MACCR_CLEAR_MASK;
01659   /* Set the WD bit according to ETH Watchdog value */
01660   /* Set the JD: bit according to ETH Jabber value */
01661   /* Set the IFG bit according to ETH InterFrameGap value */
01662   /* Set the DCRS bit according to ETH CarrierSense value */
01663   /* Set the FES bit according to ETH Speed value */
01664   /* Set the DO bit according to ETH ReceiveOwn value */
01665   /* Set the LM bit according to ETH LoopbackMode value */
01666   /* Set the DM bit according to ETH Mode value */
01667   /* Set the IPCO bit according to ETH ChecksumOffload value */
01668   /* Set the DR bit according to ETH RetryTransmission value */
01669   /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
01670   /* Set the BL bit according to ETH BackOffLimit value */
01671   /* Set the DC bit according to ETH DeferralCheck value */
01672   tmpreg1 |= (uint32_t)(macinit.Watchdog |
01673                        macinit.Jabber |
01674                        macinit.InterFrameGap |
01675                        macinit.CarrierSense |
01676                        (heth->Init).Speed |
01677                        macinit.ReceiveOwn |
01678                        macinit.LoopbackMode |
01679                        (heth->Init).DuplexMode |
01680                        macinit.ChecksumOffload |
01681                        macinit.RetryTransmission |
01682                        macinit.AutomaticPadCRCStrip |
01683                        macinit.BackOffLimit |
01684                        macinit.DeferralCheck);
01685
01686   /* Write to ETHERNET MACCR */
01687   (heth->Instance)->MACCR = (uint32_t)tmpreg1;
01688
01689   /* Wait until the write operation will be taken into account:
01690      at least four TX_CLK/RX_CLK clock cycles */
01691   tmpreg1 = (heth->Instance)->MACCR;
01692   HAL_Delay(ETH_REG_WRITE_DELAY);
01693   (heth->Instance)->MACCR = tmpreg1;
01694
01695   /*----------------------- ETHERNET MACFFR Configuration --------------------*/
01696   /* Set the RA bit according to ETH ReceiveAll value */
01697   /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
01698   /* Set the PCF bit according to ETH PassControlFrames value */
01699   /* Set the DBF bit according to ETH BroadcastFramesReception value */
01700   /* Set the DAIF bit according to ETH DestinationAddrFilter value */
01701   /* Set the PR bit according to ETH PromiscuousMode value */
01702   /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
01703   /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
01704   /* Write to ETHERNET MACFFR */
01705   (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
01706                                         macinit.SourceAddrFilter |
01707                                         macinit.PassControlFrames |
01708                                         macinit.BroadcastFramesReception |
01709                                         macinit.DestinationAddrFilter |
01710                                         macinit.PromiscuousMode |
01711                                         macinit.MulticastFramesFilter |
01712                                         macinit.UnicastFramesFilter);
01713
01714    /* Wait until the write operation will be taken into account:
01715       at least four TX_CLK/RX_CLK clock cycles */
01716    tmpreg1 = (heth->Instance)->MACFFR;
01717    HAL_Delay(ETH_REG_WRITE_DELAY);
01718    (heth->Instance)->MACFFR = tmpreg1;
01719
01720    /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
01721    /* Write to ETHERNET MACHTHR */
01722    (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
01723
01724    /* Write to ETHERNET MACHTLR */
01725    (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
01726    /*----------------------- ETHERNET MACFCR Configuration -------------------*/
01727
01728    /* Get the ETHERNET MACFCR value */
01729    tmpreg1 = (heth->Instance)->MACFCR;
01730    /* Clear xx bits */
01731    tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
01732
01733    /* Set the PT bit according to ETH PauseTime value */
01734    /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
01735    /* Set the PLT bit according to ETH PauseLowThreshold value */
01736    /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
01737    /* Set the RFE bit according to ETH ReceiveFlowControl value */
01738    /* Set the TFE bit according to ETH TransmitFlowControl value */
01739    tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
01740                         macinit.ZeroQuantaPause |
01741                         macinit.PauseLowThreshold |
01742                         macinit.UnicastPauseFrameDetect |
01743                         macinit.ReceiveFlowControl |
01744                         macinit.TransmitFlowControl);
01745
01746    /* Write to ETHERNET MACFCR */
01747    (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
01748
01749    /* Wait until the write operation will be taken into account:
01750    at least four TX_CLK/RX_CLK clock cycles */
01751    tmpreg1 = (heth->Instance)->MACFCR;
01752    HAL_Delay(ETH_REG_WRITE_DELAY);
01753    (heth->Instance)->MACFCR = tmpreg1;
01754
01755    /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
01756    /* Set the ETV bit according to ETH VLANTagComparison value */
01757    /* Set the VL bit according to ETH VLANTagIdentifier value */
01758    (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
01759                                             macinit.VLANTagIdentifier);
01760
01761     /* Wait until the write operation will be taken into account:
01762        at least four TX_CLK/RX_CLK clock cycles */
01763     tmpreg1 = (heth->Instance)->MACVLANTR;
01764     HAL_Delay(ETH_REG_WRITE_DELAY);
01765     (heth->Instance)->MACVLANTR = tmpreg1;
01766
01767     /* Ethernet DMA default initialization ************************************/
01768     dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
01769     dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
01770     dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
01771     dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
01772     dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
01773     dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
01774     dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
01775     dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
01776     dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
01777     dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
01778     dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
01779     dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
01780     dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
01781     dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
01782     dmainit.DescriptorSkipLength = 0x0U;
01783     dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
01784
01785     /* Get the ETHERNET DMAOMR value */
01786     tmpreg1 = (heth->Instance)->DMAOMR;
01787     /* Clear xx bits */
01788     tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
01789
01790     /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
01791     /* Set the RSF bit according to ETH ReceiveStoreForward value */
01792     /* Set the DFF bit according to ETH FlushReceivedFrame value */
01793     /* Set the TSF bit according to ETH TransmitStoreForward value */
01794     /* Set the TTC bit according to ETH TransmitThresholdControl value */
01795     /* Set the FEF bit according to ETH ForwardErrorFrames value */
01796     /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
01797     /* Set the RTC bit according to ETH ReceiveThresholdControl value */
01798     /* Set the OSF bit according to ETH SecondFrameOperate value */
01799     tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
01800                          dmainit.ReceiveStoreForward |
01801                          dmainit.FlushReceivedFrame |
01802                          dmainit.TransmitStoreForward |
01803                          dmainit.TransmitThresholdControl |
01804                          dmainit.ForwardErrorFrames |
01805                          dmainit.ForwardUndersizedGoodFrames |
01806                          dmainit.ReceiveThresholdControl |
01807                          dmainit.SecondFrameOperate);
01808
01809     /* Write to ETHERNET DMAOMR */
01810     (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
01811
01812     /* Wait until the write operation will be taken into account:
01813        at least four TX_CLK/RX_CLK clock cycles */
01814     tmpreg1 = (heth->Instance)->DMAOMR;
01815     HAL_Delay(ETH_REG_WRITE_DELAY);
01816     (heth->Instance)->DMAOMR = tmpreg1;
01817
01818     /*----------------------- ETHERNET DMABMR Configuration ------------------*/
01819     /* Set the AAL bit according to ETH AddressAlignedBeats value */
01820     /* Set the FB bit according to ETH FixedBurst value */
01821     /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
01822     /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
01823     /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
01824     /* Set the DSL bit according to ETH DesciptorSkipLength value */
01825     /* Set the PR and DA bits according to ETH DMAArbitration value */
01826     (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
01827                                           dmainit.FixedBurst |
01828                                           dmainit.RxDMABurstLength |    /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
01829                                           dmainit.TxDMABurstLength |
01830                                           dmainit.EnhancedDescriptorFormat |
01831                                           (dmainit.DescriptorSkipLength << 2U) |
01832                                           dmainit.DMAArbitration |
01833                                           ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
01834
01835      /* Wait until the write operation will be taken into account:
01836         at least four TX_CLK/RX_CLK clock cycles */
01837      tmpreg1 = (heth->Instance)->DMABMR;
01838      HAL_Delay(ETH_REG_WRITE_DELAY);
01839      (heth->Instance)->DMABMR = tmpreg1;
01840
01841      if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
01842      {
01843        /* Enable the Ethernet Rx Interrupt */
01844        __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
01845      }
01846
01847      /* Initialize MAC address in ethernet MAC */
01848      ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
01849 }
01850
01851 /**
01852   * @brief  Configures the selected MAC address.
01853   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01854   *         the configuration information for ETHERNET module
01855   * @param  MacAddr: The MAC address to configure
01856   *          This parameter can be one of the following values:
01857   *             @arg ETH_MAC_Address0: MAC Address0
01858   *             @arg ETH_MAC_Address1: MAC Address1
01859   *             @arg ETH_MAC_Address2: MAC Address2
01860   *             @arg ETH_MAC_Address3: MAC Address3
01861   * @param  Addr: Pointer to MAC address buffer data (6 bytes)
01862   * @retval HAL status
01863   */
01864 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
01865 {
01866   uint32_t tmpreg1;
01867
01868   /* Check the parameters */
01869   assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
01870
01871   /* Calculate the selected MAC address high register */
01872   tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
01873   /* Load the selected MAC address high register */
01874   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
01875   /* Calculate the selected MAC address low register */
01876   tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
01877
01878   /* Load the selected MAC address low register */
01879   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
01880 }
01881
01882 /**
01883   * @brief  Enables the MAC transmission.
01884   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01885   *         the configuration information for ETHERNET module
01886   * @retval None
01887   */
01888 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
01889 {
01890   __IO uint32_t tmpreg1 = 0U;
01891
01892   /* Enable the MAC transmission */
01893   (heth->Instance)->MACCR |= ETH_MACCR_TE;
01894
01895   /* Wait until the write operation will be taken into account:
01896      at least four TX_CLK/RX_CLK clock cycles */
01897   tmpreg1 = (heth->Instance)->MACCR;
01898   HAL_Delay(ETH_REG_WRITE_DELAY);
01899   (heth->Instance)->MACCR = tmpreg1;
01900 }
01901
01902 /**
01903   * @brief  Disables the MAC transmission.
01904   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01905   *         the configuration information for ETHERNET module
01906   * @retval None
01907   */
01908 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
01909 {
01910   __IO uint32_t tmpreg1 = 0U;
01911
01912   /* Disable the MAC transmission */
01913   (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
01914
01915   /* Wait until the write operation will be taken into account:
01916      at least four TX_CLK/RX_CLK clock cycles */
01917   tmpreg1 = (heth->Instance)->MACCR;
01918   HAL_Delay(ETH_REG_WRITE_DELAY);
01919   (heth->Instance)->MACCR = tmpreg1;
01920 }
01921
01922 /**
01923   * @brief  Enables the MAC reception.
01924   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01925   *         the configuration information for ETHERNET module
01926   * @retval None
01927   */
01928 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
01929 {
01930   __IO uint32_t tmpreg1 = 0U;
01931
01932   /* Enable the MAC reception */
01933   (heth->Instance)->MACCR |= ETH_MACCR_RE;
01934
01935   /* Wait until the write operation will be taken into account:
01936      at least four TX_CLK/RX_CLK clock cycles */
01937   tmpreg1 = (heth->Instance)->MACCR;
01938   HAL_Delay(ETH_REG_WRITE_DELAY);
01939   (heth->Instance)->MACCR = tmpreg1;
01940 }
01941
01942 /**
01943   * @brief  Disables the MAC reception.
01944   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01945   *         the configuration information for ETHERNET module
01946   * @retval None
01947   */
01948 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
01949 {
01950   __IO uint32_t tmpreg1 = 0U;
01951
01952   /* Disable the MAC reception */
01953   (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
01954
01955   /* Wait until the write operation will be taken into account:
01956      at least four TX_CLK/RX_CLK clock cycles */
01957   tmpreg1 = (heth->Instance)->MACCR;
01958   HAL_Delay(ETH_REG_WRITE_DELAY);
01959   (heth->Instance)->MACCR = tmpreg1;
01960 }
01961
01962 /**
01963   * @brief  Enables the DMA transmission.
01964   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01965   *         the configuration information for ETHERNET module
01966   * @retval None
01967   */
01968 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
01969 {
01970   /* Enable the DMA transmission */
01971   (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
01972 }
01973
01974 /**
01975   * @brief  Disables the DMA transmission.
01976   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01977   *         the configuration information for ETHERNET module
01978   * @retval None
01979   */
01980 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
01981 {
01982   /* Disable the DMA transmission */
01983   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
01984 }
01985
01986 /**
01987   * @brief  Enables the DMA reception.
01988   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01989   *         the configuration information for ETHERNET module
01990   * @retval None
01991   */
01992 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
01993 {
01994   /* Enable the DMA reception */
01995   (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
01996 }
01997
01998 /**
01999   * @brief  Disables the DMA reception.
02000   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02001   *         the configuration information for ETHERNET module
02002   * @retval None
02003   */
02004 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
02005 {
02006   /* Disable the DMA reception */
02007   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
02008 }
02009
02010 /**
02011   * @brief  Clears the ETHERNET transmit FIFO.
02012   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
02013   *         the configuration information for ETHERNET module
02014   * @retval None
02015   */
02016 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
02017 {
02018   __IO uint32_t tmpreg1 = 0U;
02019
02020   /* Set the Flush Transmit FIFO bit */
02021   (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
02022
02023   /* Wait until the write operation will be taken into account:
02024      at least four TX_CLK/RX_CLK clock cycles */
02025   tmpreg1 = (heth->Instance)->DMAOMR;
02026   HAL_Delay(ETH_REG_WRITE_DELAY);
02027   (heth->Instance)->DMAOMR = tmpreg1;
02028 }
02029
02030 /**
02031   * @}
02032   */
02033
02034 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
02035           STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
02036 #endif /* HAL_ETH_MODULE_ENABLED */
02037 /**
02038   * @}
02039   */
02040
02041 /**
02042   * @}
02043   */
02044
02045 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_eth.h Source File

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stm32f4xx_hal_eth.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_eth.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of ETH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_ETH_H
00040 #define __STM32F4xx_HAL_ETH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
00047     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f4xx_hal_def.h"
00050
00051 /** @addtogroup STM32F4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup ETH
00056   * @{
00057   */
00058
00059 /** @addtogroup ETH_Private_Macros
00060   * @{
00061   */
00062 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
00063 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
00064                                      ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
00065 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
00066                              ((SPEED) == ETH_SPEED_100M))
00067 #define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \
00068                                   ((MODE) == ETH_MODE_HALFDUPLEX))
00069 #define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
00070                                  ((MODE) == ETH_RXINTERRUPT_MODE))
00071 #define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
00072                                       ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
00073 #define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
00074                                               ((MODE) == ETH_MEDIA_INTERFACE_RMII))
00075 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
00076                               ((CMD) == ETH_WATCHDOG_DISABLE))
00077 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
00078                             ((CMD) == ETH_JABBER_DISABLE))
00079 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
00080                                      ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
00081                                      ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
00082                                      ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
00083                                      ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
00084                                      ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
00085                                      ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
00086                                      ((GAP) == ETH_INTERFRAMEGAP_40BIT))
00087 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
00088                                    ((CMD) == ETH_CARRIERSENCE_DISABLE))
00089 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
00090                                  ((CMD) == ETH_RECEIVEOWN_DISABLE))
00091 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
00092                                    ((CMD) == ETH_LOOPBACKMODE_DISABLE))
00093 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
00094                                       ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
00095 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
00096                                         ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
00097 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
00098                                             ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
00099 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
00100                                      ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
00101                                      ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
00102                                      ((LIMIT) == ETH_BACKOFFLIMIT_1))
00103 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
00104                                     ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
00105 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
00106                                  ((CMD) == ETH_RECEIVEAll_DISABLE))
00107 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
00108                                         ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
00109                                         ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
00110 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
00111                                      ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
00112                                      ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
00113 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
00114                                                 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
00115 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
00116                                                 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
00117 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
00118                                       ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
00119 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
00120                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
00121                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
00122                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
00123 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
00124                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
00125                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
00126 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
00127 #define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
00128                                         ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
00129 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
00130                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
00131                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
00132                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
00133 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
00134                                                 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
00135 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
00136                                          ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
00137 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
00138                                           ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
00139 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
00140                                                 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
00141 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
00142 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
00143                                          ((ADDRESS) == ETH_MAC_ADDRESS1) || \
00144                                          ((ADDRESS) == ETH_MAC_ADDRESS2) || \
00145                                          ((ADDRESS) == ETH_MAC_ADDRESS3))
00146 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
00147                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \
00148                                         ((ADDRESS) == ETH_MAC_ADDRESS3))
00149 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
00150                                            ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
00151 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
00152                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
00153                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
00154                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
00155                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
00156                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
00157 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
00158                                                ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
00159 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
00160                                            ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
00161 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
00162                                          ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
00163 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
00164                                             ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
00165 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
00166                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
00167                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
00168                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
00169                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
00170                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
00171                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
00172                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
00173 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
00174                                           ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
00175 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
00176                                                     ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
00177 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
00178                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
00179                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
00180                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
00181 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
00182                                           ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
00183 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
00184                                            ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
00185 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
00186                                  ((CMD) == ETH_FIXEDBURST_DISABLE))
00187 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
00188                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
00189                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
00190                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
00191                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
00192                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
00193                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
00194                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
00195                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
00196                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
00197                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
00198                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
00199 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
00200                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
00201                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
00202                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
00203                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
00204                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
00205                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
00206                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
00207                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
00208                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
00209                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
00210                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
00211 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
00212 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
00213                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
00214                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
00215                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
00216                                                        ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
00217 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
00218                                          ((FLAG) == ETH_DMATXDESC_IC) || \
00219                                          ((FLAG) == ETH_DMATXDESC_LS) || \
00220                                          ((FLAG) == ETH_DMATXDESC_FS) || \
00221                                          ((FLAG) == ETH_DMATXDESC_DC) || \
00222                                          ((FLAG) == ETH_DMATXDESC_DP) || \
00223                                          ((FLAG) == ETH_DMATXDESC_TTSE) || \
00224                                          ((FLAG) == ETH_DMATXDESC_TER) || \
00225                                          ((FLAG) == ETH_DMATXDESC_TCH) || \
00226                                          ((FLAG) == ETH_DMATXDESC_TTSS) || \
00227                                          ((FLAG) == ETH_DMATXDESC_IHE) || \
00228                                          ((FLAG) == ETH_DMATXDESC_ES) || \
00229                                          ((FLAG) == ETH_DMATXDESC_JT) || \
00230                                          ((FLAG) == ETH_DMATXDESC_FF) || \
00231                                          ((FLAG) == ETH_DMATXDESC_PCE) || \
00232                                          ((FLAG) == ETH_DMATXDESC_LCA) || \
00233                                          ((FLAG) == ETH_DMATXDESC_NC) || \
00234                                          ((FLAG) == ETH_DMATXDESC_LCO) || \
00235                                          ((FLAG) == ETH_DMATXDESC_EC) || \
00236                                          ((FLAG) == ETH_DMATXDESC_VF) || \
00237                                          ((FLAG) == ETH_DMATXDESC_CC) || \
00238                                          ((FLAG) == ETH_DMATXDESC_ED) || \
00239                                          ((FLAG) == ETH_DMATXDESC_UF) || \
00240                                          ((FLAG) == ETH_DMATXDESC_DB))
00241 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
00242                                             ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
00243 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
00244                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
00245                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
00246                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
00247 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
00248 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
00249                                          ((FLAG) == ETH_DMARXDESC_AFM) || \
00250                                          ((FLAG) == ETH_DMARXDESC_ES) || \
00251                                          ((FLAG) == ETH_DMARXDESC_DE) || \
00252                                          ((FLAG) == ETH_DMARXDESC_SAF) || \
00253                                          ((FLAG) == ETH_DMARXDESC_LE) || \
00254                                          ((FLAG) == ETH_DMARXDESC_OE) || \
00255                                          ((FLAG) == ETH_DMARXDESC_VLAN) || \
00256                                          ((FLAG) == ETH_DMARXDESC_FS) || \
00257                                          ((FLAG) == ETH_DMARXDESC_LS) || \
00258                                          ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
00259                                          ((FLAG) == ETH_DMARXDESC_LC) || \
00260                                          ((FLAG) == ETH_DMARXDESC_FT) || \
00261                                          ((FLAG) == ETH_DMARXDESC_RWT) || \
00262                                          ((FLAG) == ETH_DMARXDESC_RE) || \
00263                                          ((FLAG) == ETH_DMARXDESC_DBE) || \
00264                                          ((FLAG) == ETH_DMARXDESC_CE) || \
00265                                          ((FLAG) == ETH_DMARXDESC_MAMPCE))
00266 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
00267                                           ((BUFFER) == ETH_DMARXDESC_BUFFER2))
00268 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
00269                                    ((FLAG) == ETH_PMT_FLAG_MPR))
00270 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
00271 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
00272                                    ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
00273                                    ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
00274                                    ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
00275                                    ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
00276                                    ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
00277                                    ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
00278                                    ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
00279                                    ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
00280                                    ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
00281                                    ((FLAG) == ETH_DMA_FLAG_T))
00282 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
00283 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
00284                                ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
00285                                ((IT) == ETH_MAC_IT_PMT))
00286 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
00287                                    ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
00288                                    ((FLAG) == ETH_MAC_FLAG_PMT))
00289 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
00290 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
00291                                ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
00292                                ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
00293                                ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
00294                                ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
00295                                ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
00296                                ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
00297                                ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
00298                                ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
00299 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
00300                                            ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
00301 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFFU) == 0x00U) || (((IT) & (uint32_t)0xEFFDFF9FU) == 0x00U)) && \
00302                            ((IT) != 0x00U))
00303 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
00304                                ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
00305                                ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
00306 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
00307                                                 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @addtogroup ETH_Private_Defines
00314   * @{
00315   */
00316 /* Delay to wait when writing to some Ethernet registers */
00317 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)
00318
00319 /* ETHERNET Errors */
00320 #define  ETH_SUCCESS            ((uint32_t)0U)
00321 #define  ETH_ERROR              ((uint32_t)1U)
00322
00323 /* ETHERNET DMA Tx descriptors Collision Count Shift */
00324 #define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3U)
00325
00326 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
00327 #define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16U)
00328
00329 /* ETHERNET DMA Rx descriptors Frame Length Shift */
00330 #define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16U)
00331
00332 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
00333 #define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16U)
00334
00335 /* ETHERNET DMA Rx descriptors Frame length Shift */
00336 #define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16U)
00337
00338 /* ETHERNET MAC address offsets */
00339 #define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U)  /* ETHERNET MAC address high offset */
00340 #define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U)  /* ETHERNET MAC address low offset */
00341
00342 /* ETHERNET MACMIIAR register Mask */
00343 #define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3U)
00344
00345 /* ETHERNET MACCR register Mask */
00346 #define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810FU)
00347
00348 /* ETHERNET MACFCR register Mask */
00349 #define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41U)
00350
00351 /* ETHERNET DMAOMR register Mask */
00352 #define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23U)
00353
00354 /* ETHERNET Remote Wake-up frame register length */
00355 #define ETH_WAKEUP_REGISTER_LENGTH      8
00356
00357 /* ETHERNET Missed frames counter Shift */
00358 #define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17U
00359  /**
00360   * @}
00361   */
00362
00363 /* Exported types ------------------------------------------------------------*/
00364 /** @defgroup ETH_Exported_Types ETH Exported Types
00365   * @{
00366   */
00367
00368 /**
00369   * @brief  HAL State structures definition
00370   */
00371 typedef enum
00372 {
00373   HAL_ETH_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */
00374   HAL_ETH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00375   HAL_ETH_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */
00376   HAL_ETH_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing               */
00377   HAL_ETH_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing                  */
00378   HAL_ETH_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission and Reception process is ongoing */
00379   HAL_ETH_STATE_BUSY_WR           = 0x42U,    /*!< Write process is ongoing                           */
00380   HAL_ETH_STATE_BUSY_RD           = 0x82U,    /*!< Read process is ongoing                            */
00381   HAL_ETH_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                      */
00382   HAL_ETH_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */
00383 }HAL_ETH_StateTypeDef;
00384
00385 /**
00386   * @brief  ETH Init Structure definition
00387   */
00388
00389 typedef struct
00390 {
00391   uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
00392                                                            The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
00393                                                            and the mode (half/full-duplex).
00394                                                            This parameter can be a value of @ref ETH_AutoNegotiation */
00395
00396   uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.
00397                                                            This parameter can be a value of @ref ETH_Speed */
00398
00399   uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
00400                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
00401
00402   uint16_t             PhyAddress;                /*!< Ethernet PHY address.
00403                                                            This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
00404
00405   uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
00406
00407   uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
00408                                                            This parameter can be a value of @ref ETH_Rx_Mode */
00409
00410   uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software.
00411                                                          This parameter can be a value of @ref ETH_Checksum_Mode */
00412
00413   uint32_t             MediaInterface;            /*!< Selects the media-independent interface or the reduced media-independent interface.
00414                                                          This parameter can be a value of @ref ETH_Media_Interface */
00415
00416 } ETH_InitTypeDef;
00417
00418
00419  /**
00420   * @brief  ETH MAC Configuration Structure definition
00421   */
00422
00423 typedef struct
00424 {
00425   uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer
00426                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
00427                                                            When disabled, the MAC can receive up to 16384 bytes.
00428                                                            This parameter can be a value of @ref ETH_Watchdog */
00429
00430   uint32_t             Jabber;                    /*!< Selects or not Jabber timer
00431                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
00432                                                            When disabled, the MAC can send up to 16384 bytes.
00433                                                            This parameter can be a value of @ref ETH_Jabber */
00434
00435   uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.
00436                                                            This parameter can be a value of @ref ETH_Inter_Frame_Gap */
00437
00438   uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.
00439                                                            This parameter can be a value of @ref ETH_Carrier_Sense */
00440
00441   uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,
00442                                                            ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
00443                                                            in Half-Duplex mode.
00444                                                            This parameter can be a value of @ref ETH_Receive_Own */
00445
00446   uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.
00447                                                            This parameter can be a value of @ref ETH_Loop_Back_Mode */
00448
00449   uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
00450                                                            This parameter can be a value of @ref ETH_Checksum_Offload */
00451
00452   uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
00453                                                            when a collision occurs (Half-Duplex mode).
00454                                                            This parameter can be a value of @ref ETH_Retry_Transmission */
00455
00456   uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
00457                                                            This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
00458
00459   uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.
00460                                                            This parameter can be a value of @ref ETH_Back_Off_Limit */
00461
00462   uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).
00463                                                            This parameter can be a value of @ref ETH_Deferral_Check */
00464
00465   uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).
00466                                                            This parameter can be a value of @ref ETH_Receive_All */
00467
00468   uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.
00469                                                            This parameter can be a value of @ref ETH_Source_Addr_Filter */
00470
00471   uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
00472                                                            This parameter can be a value of @ref ETH_Pass_Control_Frames */
00473
00474   uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.
00475                                                            This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
00476
00477   uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.
00478                                                            This parameter can be a value of @ref ETH_Destination_Addr_Filter */
00479
00480   uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
00481                                                            This parameter can be a value of @ref ETH_Promiscuous_Mode */
00482
00483   uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
00484                                                            This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
00485
00486   uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
00487                                                            This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
00488
00489   uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.
00490                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
00491
00492   uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.
00493                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU  */
00494
00495   uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
00496                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
00497
00498   uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
00499                                                            This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
00500
00501   uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
00502                                                            automatic retransmission of PAUSE Frame.
00503                                                            This parameter can be a value of @ref ETH_Pause_Low_Threshold */
00504
00505   uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
00506                                                            unicast address and unique multicast address).
00507                                                            This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
00508
00509   uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
00510                                                            disable its transmitter for a specified time (Pause Time)
00511                                                            This parameter can be a value of @ref ETH_Receive_Flow_Control */
00512
00513   uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
00514                                                            or the MAC back-pressure operation (Half-Duplex mode)
00515                                                            This parameter can be a value of @ref ETH_Transmit_Flow_Control */
00516
00517   uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
00518                                                            comparison and filtering.
00519                                                            This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
00520
00521   uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
00522
00523 } ETH_MACInitTypeDef;
00524
00525 /**
00526   * @brief  ETH DMA Configuration Structure definition
00527   */
00528
00529 typedef struct
00530 {
00531  uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
00532                                                              This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
00533
00534   uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.
00535                                                              This parameter can be a value of @ref ETH_Receive_Store_Forward */
00536
00537   uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.
00538                                                              This parameter can be a value of @ref ETH_Flush_Received_Frame */
00539
00540   uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.
00541                                                              This parameter can be a value of @ref ETH_Transmit_Store_Forward */
00542
00543   uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
00544                                                              This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
00545
00546   uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.
00547                                                              This parameter can be a value of @ref ETH_Forward_Error_Frames */
00548
00549   uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
00550                                                              and length less than 64 bytes) including pad-bytes and CRC)
00551                                                              This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
00552
00553   uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.
00554                                                              This parameter can be a value of @ref ETH_Receive_Threshold_Control */
00555
00556   uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
00557                                                              frame of Transmit data even before obtaining the status for the first frame.
00558                                                              This parameter can be a value of @ref ETH_Second_Frame_Operate */
00559
00560   uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.
00561                                                              This parameter can be a value of @ref ETH_Address_Aligned_Beats */
00562
00563   uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.
00564                                                              This parameter can be a value of @ref ETH_Fixed_Burst */
00565
00566   uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
00567                                                              This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
00568
00569   uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
00570                                                              This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
00571
00572   uint32_t             EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format.
00573                                                              This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
00574
00575   uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
00576                                                              This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
00577
00578   uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.
00579                                                              This parameter can be a value of @ref ETH_DMA_Arbitration */
00580 } ETH_DMAInitTypeDef;
00581
00582
00583 /**
00584   * @brief  ETH DMA Descriptors data structure definition
00585   */
00586
00587 typedef struct
00588 {
00589   __IO uint32_t   Status;           /*!< Status */
00590
00591   uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
00592
00593   uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
00594
00595   uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
00596
00597   /*!< Enhanced ETHERNET DMA PTP Descriptors */
00598   uint32_t   ExtendedStatus;        /*!< Extended status for PTP receive descriptor */
00599
00600   uint32_t   Reserved1;             /*!< Reserved */
00601
00602   uint32_t   TimeStampLow;          /*!< Time Stamp Low value for transmit and receive */
00603
00604   uint32_t   TimeStampHigh;         /*!< Time Stamp High value for transmit and receive */
00605
00606 } ETH_DMADescTypeDef;
00607
00608 /**
00609   * @brief  Received Frame Informations structure definition
00610   */
00611 typedef struct
00612 {
00613   ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */
00614
00615   ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */
00616
00617   uint32_t  SegCount;                    /*!< Segment count */
00618
00619   uint32_t length;                       /*!< Frame length */
00620
00621   uint32_t buffer;                       /*!< Frame buffer */
00622
00623 } ETH_DMARxFrameInfos;
00624
00625 /**
00626   * @brief  ETH Handle Structure definition
00627   */
00628
00629 typedef struct
00630 {
00631   ETH_TypeDef                *Instance;     /*!< Register base address       */
00632
00633   ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */
00634
00635   uint32_t                   LinkStatus;    /*!< Ethernet link status        */
00636
00637   ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */
00638
00639   ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */
00640
00641   ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */
00642
00643   __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */
00644
00645   HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */
00646
00647 } ETH_HandleTypeDef;
00648
00649  /**
00650   * @}
00651   */
00652
00653 /* Exported constants --------------------------------------------------------*/
00654 /** @defgroup ETH_Exported_Constants ETH Exported Constants
00655   * @{
00656   */
00657
00658 /** @defgroup ETH_Buffers_setting ETH Buffers setting
00659   * @{
00660   */
00661 #define ETH_MAX_PACKET_SIZE       ((uint32_t)1524U)    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
00662 #define ETH_HEADER                ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
00663 #define ETH_CRC                   ((uint32_t)4U)    /*!< Ethernet CRC */
00664 #define ETH_EXTRA                 ((uint32_t)2U)    /*!< Extra bytes in some cases */
00665 #define ETH_VLAN_TAG              ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */
00666 #define ETH_MIN_ETH_PAYLOAD       ((uint32_t)46U)    /*!< Minimum Ethernet payload size */
00667 #define ETH_MAX_ETH_PAYLOAD       ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */
00668 #define ETH_JUMBO_FRAME_PAYLOAD   ((uint32_t)9000U)    /*!< Jumbo frame payload size */
00669
00670  /* Ethernet driver receive buffers are organized in a chained linked-list, when
00671     an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
00672     to the driver receive buffers memory.
00673
00674     Depending on the size of the received ethernet packet and the size of
00675     each ethernet driver receive buffer, the received packet can take one or more
00676     ethernet driver receive buffer.
00677
00678     In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
00679     and the total count of the driver receive buffers ETH_RXBUFNB.
00680
00681     The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
00682     example, they can be reconfigured in the application layer to fit the application
00683     needs */
00684
00685 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
00686    packet */
00687 #ifndef ETH_RX_BUF_SIZE
00688  #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE
00689 #endif
00690
00691 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
00692 #ifndef ETH_RXBUFNB
00693  #define ETH_RXBUFNB             ((uint32_t)5U)     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
00694 #endif
00695
00696
00697  /* Ethernet driver transmit buffers are organized in a chained linked-list, when
00698     an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
00699     driver transmit buffers memory to the TxFIFO.
00700
00701     Depending on the size of the Ethernet packet to be transmitted and the size of
00702     each ethernet driver transmit buffer, the packet to be transmitted can take
00703     one or more ethernet driver transmit buffer.
00704
00705     In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
00706     and the total count of the driver transmit buffers ETH_TXBUFNB.
00707
00708     The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
00709     example, they can be reconfigured in the application layer to fit the application
00710     needs */
00711
00712 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
00713    packet */
00714 #ifndef ETH_TX_BUF_SIZE
00715  #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
00716 #endif
00717
00718 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
00719 #ifndef ETH_TXBUFNB
00720  #define ETH_TXBUFNB             ((uint32_t)5U)      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
00721 #endif
00722
00723  /**
00724   * @}
00725   */
00726
00727 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
00728   * @{
00729   */
00730
00731 /*
00732    DMA Tx Descriptor
00733   -----------------------------------------------------------------------------------------------
00734   TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
00735   -----------------------------------------------------------------------------------------------
00736   TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
00737   -----------------------------------------------------------------------------------------------
00738   TDES2 |                         Buffer1 Address [31:0]                                         |
00739   -----------------------------------------------------------------------------------------------
00740   TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
00741   -----------------------------------------------------------------------------------------------
00742 */
00743
00744 /**
00745   * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
00746   */
00747 #define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
00748 #define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000U)  /*!< Interrupt on Completion */
00749 #define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000U)  /*!< Last Segment */
00750 #define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000U)  /*!< First Segment */
00751 #define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000U)  /*!< Disable CRC */
00752 #define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */
00753 #define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Time Stamp Enable */
00754 #define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000U)  /*!< Checksum Insertion Control: 4 cases */
00755 #define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is bypassed */
00756 #define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000U)  /*!< IPV4 header Checksum Insertion */
00757 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000U)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
00758 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000U)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
00759 #define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000U)  /*!< Transmit End of Ring */
00760 #define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000U)  /*!< Second Address Chained */
00761 #define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Time Stamp Status */
00762 #define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000U)  /*!< IP Header Error */
00763 #define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
00764 #define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */
00765 #define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000U)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
00766 #define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */
00767 #define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */
00768 #define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */
00769 #define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */
00770 #define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */
00771 #define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080U)  /*!< VLAN Frame */
00772 #define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078U)  /*!< Collision Count */
00773 #define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004U)  /*!< Excessive Deferral */
00774 #define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002U)  /*!< Underflow Error: late data arrival from the memory */
00775 #define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001U)  /*!< Deferred Bit */
00776
00777 /**
00778   * @brief  Bit definition of TDES1 register
00779   */
00780 #define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000U)  /*!< Transmit Buffer2 Size */
00781 #define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFFU)  /*!< Transmit Buffer1 Size */
00782
00783 /**
00784   * @brief  Bit definition of TDES2 register
00785   */
00786 #define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer */
00787
00788 /**
00789   * @brief  Bit definition of TDES3 register
00790   */
00791 #define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */
00792
00793   /*---------------------------------------------------------------------------------------------
00794   TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
00795   -----------------------------------------------------------------------------------------------
00796   TDES7 |                         Transmit Time Stamp High [31:0]                                |
00797   ----------------------------------------------------------------------------------------------*/
00798
00799 /* Bit definition of TDES6 register */
00800  #define ETH_DMAPTPTXDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /* Transmit Time Stamp Low */
00801
00802 /* Bit definition of TDES7 register */
00803  #define ETH_DMAPTPTXDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /* Transmit Time Stamp High */
00804
00805 /**
00806   * @}
00807   */
00808 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
00809   * @{
00810   */
00811
00812 /*
00813   DMA Rx Descriptor
00814   --------------------------------------------------------------------------------------------------------------------
00815   RDES0 | OWN(31) |                                             Status [30:0]                                          |
00816   ---------------------------------------------------------------------------------------------------------------------
00817   RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
00818   ---------------------------------------------------------------------------------------------------------------------
00819   RDES2 |                                       Buffer1 Address [31:0]                                                 |
00820   ---------------------------------------------------------------------------------------------------------------------
00821   RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
00822   ---------------------------------------------------------------------------------------------------------------------
00823 */
00824
00825 /**
00826   * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
00827   */
00828 #define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */
00829 #define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000U)  /*!< DA Filter Fail for the rx frame  */
00830 #define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000U)  /*!< Receive descriptor frame length  */
00831 #define ETH_DMARXDESC_ES          ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
00832 #define ETH_DMARXDESC_DE          ((uint32_t)0x00004000U)  /*!< Descriptor error: no more descriptors for receive frame  */
00833 #define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000U)  /*!< SA Filter Fail for the received frame */
00834 #define ETH_DMARXDESC_LE          ((uint32_t)0x00001000U)  /*!< Frame size not matching with length field */
00835 #define ETH_DMARXDESC_OE          ((uint32_t)0x00000800U)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
00836 #define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400U)  /*!< VLAN Tag: received frame is a VLAN frame */
00837 #define ETH_DMARXDESC_FS          ((uint32_t)0x00000200U)  /*!< First descriptor of the frame  */
00838 #define ETH_DMARXDESC_LS          ((uint32_t)0x00000100U)  /*!< Last descriptor of the frame  */
00839 #define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080U)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */
00840 #define ETH_DMARXDESC_LC          ((uint32_t)0x00000040U)  /*!< Late collision occurred during reception   */
00841 #define ETH_DMARXDESC_FT          ((uint32_t)0x00000020U)  /*!< Frame type - Ethernet, otherwise 802.3    */
00842 #define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010U)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
00843 #define ETH_DMARXDESC_RE          ((uint32_t)0x00000008U)  /*!< Receive error: error reported by MII interface  */
00844 #define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004U)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
00845 #define ETH_DMARXDESC_CE          ((uint32_t)0x00000002U)  /*!< CRC error */
00846 #define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001U)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
00847
00848 /**
00849   * @brief  Bit definition of RDES1 register
00850   */
00851 #define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000U)  /*!< Disable Interrupt on Completion */
00852 #define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000U)  /*!< Receive Buffer2 Size */
00853 #define ETH_DMARXDESC_RER   ((uint32_t)0x00008000U)  /*!< Receive End of Ring */
00854 #define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000U)  /*!< Second Address Chained */
00855 #define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFFU)  /*!< Receive Buffer1 Size */
00856
00857 /**
00858   * @brief  Bit definition of RDES2 register
00859   */
00860 #define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer */
00861
00862 /**
00863   * @brief  Bit definition of RDES3 register
00864   */
00865 #define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */
00866
00867 /*---------------------------------------------------------------------------------------------------------------------
00868   RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
00869   ---------------------------------------------------------------------------------------------------------------------
00870   RDES5 |                                            Reserved[31:0]                                                    |
00871   ---------------------------------------------------------------------------------------------------------------------
00872   RDES6 |                                       Receive Time Stamp Low [31:0]                                          |
00873   ---------------------------------------------------------------------------------------------------------------------
00874   RDES7 |                                       Receive Time Stamp High [31:0]                                         |
00875   --------------------------------------------------------------------------------------------------------------------*/
00876
00877 /* Bit definition of RDES4 register */
00878 #define ETH_DMAPTPRXDESC_PTPV     ((uint32_t)0x00002000U)  /* PTP Version */
00879 #define ETH_DMAPTPRXDESC_PTPFT    ((uint32_t)0x00001000U)  /* PTP Frame Type */
00880 #define ETH_DMAPTPRXDESC_PTPMT    ((uint32_t)0x00000F00U)  /* PTP Message Type */
00881   #define ETH_DMAPTPRXDESC_PTPMT_SYNC                      ((uint32_t)0x00000100U)  /* SYNC message (all clock types) */
00882   #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  ((uint32_t)0x00000200U)  /* FollowUp message (all clock types) */
00883   #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  ((uint32_t)0x00000300U)  /* DelayReq message (all clock types) */
00884   #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 ((uint32_t)0x00000400U)  /* DelayResp message (all clock types) */
00885   #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        ((uint32_t)0x00000500U)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
00886   #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          ((uint32_t)0x00000600U)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */
00887   #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
00888 #define ETH_DMAPTPRXDESC_IPV6PR   ((uint32_t)0x00000080U)  /* IPv6 Packet Received */
00889 #define ETH_DMAPTPRXDESC_IPV4PR   ((uint32_t)0x00000040U)  /* IPv4 Packet Received */
00890 #define ETH_DMAPTPRXDESC_IPCB  ((uint32_t)0x00000020U)  /* IP Checksum Bypassed */
00891 #define ETH_DMAPTPRXDESC_IPPE  ((uint32_t)0x00000010U)  /* IP Payload Error */
00892 #define ETH_DMAPTPRXDESC_IPHE  ((uint32_t)0x00000008U)  /* IP Header Error */
00893 #define ETH_DMAPTPRXDESC_IPPT  ((uint32_t)0x00000007U)  /* IP Payload Type */
00894   #define ETH_DMAPTPRXDESC_IPPT_UDP                 ((uint32_t)0x00000001U)  /* UDP payload encapsulated in the IP datagram */
00895   #define ETH_DMAPTPRXDESC_IPPT_TCP                 ((uint32_t)0x00000002U)  /* TCP payload encapsulated in the IP datagram */
00896   #define ETH_DMAPTPRXDESC_IPPT_ICMP                ((uint32_t)0x00000003U)  /* ICMP payload encapsulated in the IP datagram */
00897
00898 /* Bit definition of RDES6 register */
00899 #define ETH_DMAPTPRXDESC_RTSL  ((uint32_t)0xFFFFFFFFU)  /* Receive Time Stamp Low */
00900
00901 /* Bit definition of RDES7 register */
00902 #define ETH_DMAPTPRXDESC_RTSH  ((uint32_t)0xFFFFFFFFU)  /* Receive Time Stamp High */
00903 /**
00904   * @}
00905   */
00906  /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
00907   * @{
00908   */
00909 #define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001U)
00910 #define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000U)
00911
00912 /**
00913   * @}
00914   */
00915 /** @defgroup ETH_Speed ETH Speed
00916   * @{
00917   */
00918 #define ETH_SPEED_10M        ((uint32_t)0x00000000U)
00919 #define ETH_SPEED_100M       ((uint32_t)0x00004000U)
00920
00921 /**
00922   * @}
00923   */
00924 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
00925   * @{
00926   */
00927 #define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800U)
00928 #define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000U)
00929 /**
00930   * @}
00931   */
00932 /** @defgroup ETH_Rx_Mode ETH Rx Mode
00933   * @{
00934   */
00935 #define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000U)
00936 #define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001U)
00937 /**
00938   * @}
00939   */
00940
00941 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
00942   * @{
00943   */
00944 #define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000U)
00945 #define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001U)
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup ETH_Media_Interface ETH Media Interface
00951   * @{
00952   */
00953 #define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000U)
00954 #define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
00955 /**
00956   * @}
00957   */
00958
00959 /** @defgroup ETH_Watchdog ETH Watchdog
00960   * @{
00961   */
00962 #define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000U)
00963 #define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000U)
00964 /**
00965   * @}
00966   */
00967
00968 /** @defgroup ETH_Jabber ETH Jabber
00969   * @{
00970   */
00971 #define ETH_JABBER_ENABLE    ((uint32_t)0x00000000U)
00972 #define ETH_JABBER_DISABLE   ((uint32_t)0x00400000U)
00973 /**
00974   * @}
00975   */
00976
00977 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
00978   * @{
00979   */
00980 #define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000U)  /*!< minimum IFG between frames during transmission is 96Bit */
00981 #define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000U)  /*!< minimum IFG between frames during transmission is 88Bit */
00982 #define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000U)  /*!< minimum IFG between frames during transmission is 80Bit */
00983 #define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000U)  /*!< minimum IFG between frames during transmission is 72Bit */
00984 #define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000U)  /*!< minimum IFG between frames during transmission is 64Bit */
00985 #define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000U)  /*!< minimum IFG between frames during transmission is 56Bit */
00986 #define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000U)  /*!< minimum IFG between frames during transmission is 48Bit */
00987 #define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000U)  /*!< minimum IFG between frames during transmission is 40Bit */
00988 /**
00989   * @}
00990   */
00991
00992 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
00993   * @{
00994   */
00995 #define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000U)
00996 #define ETH_CARRIERSENCE_DISABLE  ((uint32_t)0x00010000U)
00997 /**
00998   * @}
00999   */
01000
01001 /** @defgroup ETH_Receive_Own ETH Receive Own
01002   * @{
01003   */
01004 #define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000U)
01005 #define ETH_RECEIVEOWN_DISABLE    ((uint32_t)0x00002000U)
01006 /**
01007   * @}
01008   */
01009
01010 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
01011   * @{
01012   */
01013 #define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000U)
01014 #define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000U)
01015 /**
01016   * @}
01017   */
01018
01019 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
01020   * @{
01021   */
01022 #define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400U)
01023 #define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000U)
01024 /**
01025   * @}
01026   */
01027
01028 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
01029   * @{
01030   */
01031 #define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000U)
01032 #define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200U)
01033 /**
01034   * @}
01035   */
01036
01037 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
01038   * @{
01039   */
01040 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080U)
01041 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000U)
01042 /**
01043   * @}
01044   */
01045
01046 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
01047   * @{
01048   */
01049 #define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000U)
01050 #define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020U)
01051 #define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040U)
01052 #define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060U)
01053 /**
01054   * @}
01055   */
01056
01057 /** @defgroup ETH_Deferral_Check ETH Deferral Check
01058   * @{
01059   */
01060 #define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010U)
01061 #define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000U)
01062 /**
01063   * @}
01064   */
01065
01066 /** @defgroup ETH_Receive_All ETH Receive All
01067   * @{
01068   */
01069 #define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000U)
01070 #define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000U)
01071 /**
01072   * @}
01073   */
01074
01075 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
01076   * @{
01077   */
01078 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200U)
01079 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300U)
01080 #define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000U)
01081 /**
01082   * @}
01083   */
01084
01085 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
01086   * @{
01087   */
01088 #define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040U)  /*!< MAC filters all control frames from reaching the application */
01089 #define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080U)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
01090 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U)  /*!< MAC forwards control frames that pass the Address Filter. */
01091 /**
01092   * @}
01093   */
01094
01095 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
01096   * @{
01097   */
01098 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000U)
01099 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020U)
01100 /**
01101   * @}
01102   */
01103
01104 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
01105   * @{
01106   */
01107 #define ETH_DESTINATIONADDRFILTER_NORMAL    ((uint32_t)0x00000000U)
01108 #define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008U)
01109 /**
01110   * @}
01111   */
01112
01113 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
01114   * @{
01115   */
01116 #define ETH_PROMISCUOUS_MODE_ENABLE     ((uint32_t)0x00000001U)
01117 #define ETH_PROMISCUOUS_MODE_DISABLE    ((uint32_t)0x00000000U)
01118 /**
01119   * @}
01120   */
01121
01122 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
01123   * @{
01124   */
01125 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ((uint32_t)0x00000404U)
01126 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ((uint32_t)0x00000004U)
01127 #define ETH_MULTICASTFRAMESFILTER_PERFECT             ((uint32_t)0x00000000U)
01128 #define ETH_MULTICASTFRAMESFILTER_NONE                ((uint32_t)0x00000010U)
01129 /**
01130   * @}
01131   */
01132
01133 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
01134   * @{
01135   */
01136 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)
01137 #define ETH_UNICASTFRAMESFILTER_HASHTABLE        ((uint32_t)0x00000002U)
01138 #define ETH_UNICASTFRAMESFILTER_PERFECT          ((uint32_t)0x00000000U)
01139 /**
01140   * @}
01141   */
01142
01143 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
01144   * @{
01145   */
01146 #define ETH_ZEROQUANTAPAUSE_ENABLE     ((uint32_t)0x00000000U)
01147 #define ETH_ZEROQUANTAPAUSE_DISABLE    ((uint32_t)0x00000080U)
01148 /**
01149   * @}
01150   */
01151
01152 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
01153   * @{
01154   */
01155 #define ETH_PAUSELOWTHRESHOLD_MINUS4        ((uint32_t)0x00000000U)  /*!< Pause time minus 4 slot times */
01156 #define ETH_PAUSELOWTHRESHOLD_MINUS28       ((uint32_t)0x00000010U)  /*!< Pause time minus 28 slot times */
01157 #define ETH_PAUSELOWTHRESHOLD_MINUS144      ((uint32_t)0x00000020U)  /*!< Pause time minus 144 slot times */
01158 #define ETH_PAUSELOWTHRESHOLD_MINUS256      ((uint32_t)0x00000030U)  /*!< Pause time minus 256 slot times */
01159 /**
01160   * @}
01161   */
01162
01163 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
01164   * @{
01165   */
01166 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  ((uint32_t)0x00000008U)
01167 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)
01168 /**
01169   * @}
01170   */
01171
01172 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
01173   * @{
01174   */
01175 #define ETH_RECEIVEFLOWCONTROL_ENABLE       ((uint32_t)0x00000004U)
01176 #define ETH_RECEIVEFLOWCONTROL_DISABLE      ((uint32_t)0x00000000U)
01177 /**
01178   * @}
01179   */
01180
01181 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
01182   * @{
01183   */
01184 #define ETH_TRANSMITFLOWCONTROL_ENABLE      ((uint32_t)0x00000002U)
01185 #define ETH_TRANSMITFLOWCONTROL_DISABLE     ((uint32_t)0x00000000U)
01186 /**
01187   * @}
01188   */
01189
01190 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
01191   * @{
01192   */
01193 #define ETH_VLANTAGCOMPARISON_12BIT    ((uint32_t)0x00010000U)
01194 #define ETH_VLANTAGCOMPARISON_16BIT    ((uint32_t)0x00000000U)
01195 /**
01196   * @}
01197   */
01198
01199 /** @defgroup ETH_MAC_addresses ETH MAC addresses
01200   * @{
01201   */
01202 #define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)
01203 #define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)
01204 #define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)
01205 #define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)
01206 /**
01207   * @}
01208   */
01209
01210 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
01211   * @{
01212   */
01213 #define ETH_MAC_ADDRESSFILTER_SA       ((uint32_t)0x00000000U)
01214 #define ETH_MAC_ADDRESSFILTER_DA       ((uint32_t)0x00000008U)
01215 /**
01216   * @}
01217   */
01218
01219 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
01220   * @{
01221   */
01222 #define ETH_MAC_ADDRESSMASK_BYTE6      ((uint32_t)0x20000000U)  /*!< Mask MAC Address high reg bits [15:8] */
01223 #define ETH_MAC_ADDRESSMASK_BYTE5      ((uint32_t)0x10000000U)  /*!< Mask MAC Address high reg bits [7:0] */
01224 #define ETH_MAC_ADDRESSMASK_BYTE4      ((uint32_t)0x08000000U)  /*!< Mask MAC Address low reg bits [31:24] */
01225 #define ETH_MAC_ADDRESSMASK_BYTE3      ((uint32_t)0x04000000U)  /*!< Mask MAC Address low reg bits [23:16] */
01226 #define ETH_MAC_ADDRESSMASK_BYTE2      ((uint32_t)0x02000000U)  /*!< Mask MAC Address low reg bits [15:8] */
01227 #define ETH_MAC_ADDRESSMASK_BYTE1      ((uint32_t)0x01000000U)  /*!< Mask MAC Address low reg bits [70] */
01228 /**
01229   * @}
01230   */
01231
01232 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
01233   * @{
01234   */
01235 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000U)
01236 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  ((uint32_t)0x04000000U)
01237 /**
01238   * @}
01239   */
01240
01241 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
01242   * @{
01243   */
01244 #define ETH_RECEIVESTOREFORWARD_ENABLE      ((uint32_t)0x02000000U)
01245 #define ETH_RECEIVESTOREFORWARD_DISABLE     ((uint32_t)0x00000000U)
01246 /**
01247   * @}
01248   */
01249
01250 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
01251   * @{
01252   */
01253 #define ETH_FLUSHRECEIVEDFRAME_ENABLE       ((uint32_t)0x00000000U)
01254 #define ETH_FLUSHRECEIVEDFRAME_DISABLE      ((uint32_t)0x01000000U)
01255 /**
01256   * @}
01257   */
01258
01259 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
01260   * @{
01261   */
01262 #define ETH_TRANSMITSTOREFORWARD_ENABLE     ((uint32_t)0x00200000U)
01263 #define ETH_TRANSMITSTOREFORWARD_DISABLE    ((uint32_t)0x00000000U)
01264 /**
01265   * @}
01266   */
01267
01268 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
01269   * @{
01270   */
01271 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ((uint32_t)0x00000000U)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
01272 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ((uint32_t)0x00004000U)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
01273 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ((uint32_t)0x00008000U)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
01274 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ((uint32_t)0x0000C000U)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
01275 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ((uint32_t)0x00010000U)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
01276 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ((uint32_t)0x00014000U)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
01277 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ((uint32_t)0x00018000U)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
01278 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ((uint32_t)0x0001C000U)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
01279 /**
01280   * @}
01281   */
01282
01283 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
01284   * @{
01285   */
01286 #define ETH_FORWARDERRORFRAMES_ENABLE       ((uint32_t)0x00000080U)
01287 #define ETH_FORWARDERRORFRAMES_DISABLE      ((uint32_t)0x00000000U)
01288 /**
01289   * @}
01290   */
01291
01292 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
01293   * @{
01294   */
01295 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040U)
01296 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  ((uint32_t)0x00000000U)
01297 /**
01298   * @}
01299   */
01300
01301 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
01302   * @{
01303   */
01304 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      ((uint32_t)0x00000000U)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
01305 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      ((uint32_t)0x00000008U)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
01306 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      ((uint32_t)0x00000010U)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
01307 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     ((uint32_t)0x00000018U)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
01308 /**
01309   * @}
01310   */
01311
01312 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
01313   * @{
01314   */
01315 #define ETH_SECONDFRAMEOPERARTE_ENABLE       ((uint32_t)0x00000004U)
01316 #define ETH_SECONDFRAMEOPERARTE_DISABLE      ((uint32_t)0x00000000U)
01317 /**
01318   * @}
01319   */
01320
01321 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
01322   * @{
01323   */
01324 #define ETH_ADDRESSALIGNEDBEATS_ENABLE      ((uint32_t)0x02000000U)
01325 #define ETH_ADDRESSALIGNEDBEATS_DISABLE     ((uint32_t)0x00000000U)
01326 /**
01327   * @}
01328   */
01329
01330 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
01331   * @{
01332   */
01333 #define ETH_FIXEDBURST_ENABLE     ((uint32_t)0x00010000U)
01334 #define ETH_FIXEDBURST_DISABLE    ((uint32_t)0x00000000U)
01335 /**
01336   * @}
01337   */
01338
01339 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
01340   * @{
01341   */
01342 #define ETH_RXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00020000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
01343 #define ETH_RXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00040000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
01344 #define ETH_RXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00080000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
01345 #define ETH_RXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00100000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
01346 #define ETH_RXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00200000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
01347 #define ETH_RXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00400000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
01348 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01020000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
01349 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01040000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
01350 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
01351 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
01352 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
01353 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01400000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
01354 /**
01355   * @}
01356   */
01357
01358 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
01359   * @{
01360   */
01361 #define ETH_TXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00000100U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
01362 #define ETH_TXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00000200U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
01363 #define ETH_TXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00000400U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
01364 #define ETH_TXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00000800U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
01365 #define ETH_TXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00001000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
01366 #define ETH_TXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00002000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
01367 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01000100U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
01368 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01000200U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
01369 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
01370 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
01371 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
01372 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01002000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
01373 /**
01374   * @}
01375   */
01376
01377 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
01378   * @{
01379   */
01380 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE              ((uint32_t)0x00000080U)
01381 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE             ((uint32_t)0x00000000U)
01382 /**
01383   * @}
01384   */
01385
01386 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
01387   * @{
01388   */
01389 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000U)
01390 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000U)
01391 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000U)
01392 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000U)
01393 #define ETH_DMAARBITRATION_RXPRIORTX             ((uint32_t)0x00000002U)
01394 /**
01395   * @}
01396   */
01397
01398 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
01399   * @{
01400   */
01401 #define ETH_DMATXDESC_LASTSEGMENTS      ((uint32_t)0x40000000U)  /*!< Last Segment */
01402 #define ETH_DMATXDESC_FIRSTSEGMENT      ((uint32_t)0x20000000U)  /*!< First Segment */
01403 /**
01404   * @}
01405   */
01406
01407 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
01408   * @{
01409   */
01410 #define ETH_DMATXDESC_CHECKSUMBYPASS             ((uint32_t)0x00000000U)   /*!< Checksum engine bypass */
01411 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER         ((uint32_t)0x00400000U)   /*!< IPv4 header checksum insertion  */
01412 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  ((uint32_t)0x00800000U)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
01413 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     ((uint32_t)0x00C00000U)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
01414 /**
01415   * @}
01416   */
01417
01418 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
01419   * @{
01420   */
01421 #define ETH_DMARXDESC_BUFFER1     ((uint32_t)0x00000000U)  /*!< DMA Rx Desc Buffer1 */
01422 #define ETH_DMARXDESC_BUFFER2     ((uint32_t)0x00000001U)  /*!< DMA Rx Desc Buffer2 */
01423 /**
01424   * @}
01425   */
01426
01427 /** @defgroup ETH_PMT_Flags ETH PMT Flags
01428   * @{
01429   */
01430 #define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000U)  /*!< Wake-Up Frame Filter Register Pointer Reset */
01431 #define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040U)  /*!< Wake-Up Frame Received */
01432 #define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020U)  /*!< Magic Packet Received */
01433 /**
01434   * @}
01435   */
01436
01437 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
01438   * @{
01439   */
01440 #define ETH_MMC_IT_TGF       ((uint32_t)0x00200000U)  /*!< When Tx good frame counter reaches half the maximum value */
01441 #define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000U)  /*!< When Tx good multi col counter reaches half the maximum value */
01442 #define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000U)  /*!< When Tx good single col counter reaches half the maximum value */
01443 /**
01444   * @}
01445   */
01446
01447 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
01448   * @{
01449   */
01450 #define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000U)  /*!< When Rx good unicast frames counter reaches half the maximum value */
01451 #define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040U)  /*!< When Rx alignment error counter reaches half the maximum value */
01452 #define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020U)  /*!< When Rx crc error counter reaches half the maximum value */
01453 /**
01454   * @}
01455   */
01456
01457 /** @defgroup ETH_MAC_Flags ETH MAC Flags
01458   * @{
01459   */
01460 #define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200U)  /*!< Time stamp trigger flag (on MAC) */
01461 #define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040U)  /*!< MMC transmit flag  */
01462 #define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020U)  /*!< MMC receive flag */
01463 #define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010U)  /*!< MMC flag (on MAC) */
01464 #define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008U)  /*!< PMT flag (on MAC) */
01465 /**
01466   * @}
01467   */
01468
01469 /** @defgroup ETH_DMA_Flags ETH DMA Flags
01470   * @{
01471   */
01472 #define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000U)  /*!< Time-stamp trigger interrupt (on DMA) */
01473 #define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000U)  /*!< PMT interrupt (on DMA) */
01474 #define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000U)  /*!< MMC interrupt (on DMA) */
01475 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
01476 #define ETH_DMA_FLAG_READWRITEERROR    ((uint32_t)0x01000000U)  /*!< Error bits 0-write transfer, 1-read transfer */
01477 #define ETH_DMA_FLAG_ACCESSERROR       ((uint32_t)0x02000000U)  /*!< Error bits 0-data buffer, 1-desc. access */
01478 #define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000U)  /*!< Normal interrupt summary flag */
01479 #define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000U)  /*!< Abnormal interrupt summary flag */
01480 #define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000U)  /*!< Early receive flag */
01481 #define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000U)  /*!< Fatal bus error flag */
01482 #define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400U)  /*!< Early transmit flag */
01483 #define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200U)  /*!< Receive watchdog timeout flag */
01484 #define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100U)  /*!< Receive process stopped flag */
01485 #define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080U)  /*!< Receive buffer unavailable flag */
01486 #define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040U)  /*!< Receive flag */
01487 #define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020U)  /*!< Underflow flag */
01488 #define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010U)  /*!< Overflow flag */
01489 #define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008U)  /*!< Transmit jabber timeout flag */
01490 #define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004U)  /*!< Transmit buffer unavailable flag */
01491 #define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002U)  /*!< Transmit process stopped flag */
01492 #define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001U)  /*!< Transmit flag */
01493 /**
01494   * @}
01495   */
01496
01497 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
01498   * @{
01499   */
01500 #define ETH_MAC_IT_TST       ((uint32_t)0x00000200U)  /*!< Time stamp trigger interrupt (on MAC) */
01501 #define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040U)  /*!< MMC transmit interrupt */
01502 #define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020U)  /*!< MMC receive interrupt */
01503 #define ETH_MAC_IT_MMC       ((uint32_t)0x00000010U)  /*!< MMC interrupt (on MAC) */
01504 #define ETH_MAC_IT_PMT       ((uint32_t)0x00000008U)  /*!< PMT interrupt (on MAC) */
01505 /**
01506   * @}
01507   */
01508
01509 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
01510   * @{
01511   */
01512 #define ETH_DMA_IT_TST       ((uint32_t)0x20000000U)  /*!< Time-stamp trigger interrupt (on DMA) */
01513 #define ETH_DMA_IT_PMT       ((uint32_t)0x10000000U)  /*!< PMT interrupt (on DMA) */
01514 #define ETH_DMA_IT_MMC       ((uint32_t)0x08000000U)  /*!< MMC interrupt (on DMA) */
01515 #define ETH_DMA_IT_NIS       ((uint32_t)0x00010000U)  /*!< Normal interrupt summary */
01516 #define ETH_DMA_IT_AIS       ((uint32_t)0x00008000U)  /*!< Abnormal interrupt summary */
01517 #define ETH_DMA_IT_ER        ((uint32_t)0x00004000U)  /*!< Early receive interrupt */
01518 #define ETH_DMA_IT_FBE       ((uint32_t)0x00002000U)  /*!< Fatal bus error interrupt */
01519 #define ETH_DMA_IT_ET        ((uint32_t)0x00000400U)  /*!< Early transmit interrupt */
01520 #define ETH_DMA_IT_RWT       ((uint32_t)0x00000200U)  /*!< Receive watchdog timeout interrupt */
01521 #define ETH_DMA_IT_RPS       ((uint32_t)0x00000100U)  /*!< Receive process stopped interrupt */
01522 #define ETH_DMA_IT_RBU       ((uint32_t)0x00000080U)  /*!< Receive buffer unavailable interrupt */
01523 #define ETH_DMA_IT_R         ((uint32_t)0x00000040U)  /*!< Receive interrupt */
01524 #define ETH_DMA_IT_TU        ((uint32_t)0x00000020U)  /*!< Underflow interrupt */
01525 #define ETH_DMA_IT_RO        ((uint32_t)0x00000010U)  /*!< Overflow interrupt */
01526 #define ETH_DMA_IT_TJT       ((uint32_t)0x00000008U)  /*!< Transmit jabber timeout interrupt */
01527 #define ETH_DMA_IT_TBU       ((uint32_t)0x00000004U)  /*!< Transmit buffer unavailable interrupt */
01528 #define ETH_DMA_IT_TPS       ((uint32_t)0x00000002U)  /*!< Transmit process stopped interrupt */
01529 #define ETH_DMA_IT_T         ((uint32_t)0x00000001U)  /*!< Transmit interrupt */
01530 /**
01531   * @}
01532   */
01533
01534 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
01535   * @{
01536   */
01537 #define ETH_DMA_TRANSMITPROCESS_STOPPED     ((uint32_t)0x00000000U)  /*!< Stopped - Reset or Stop Tx Command issued */
01538 #define ETH_DMA_TRANSMITPROCESS_FETCHING    ((uint32_t)0x00100000U)  /*!< Running - fetching the Tx descriptor */
01539 #define ETH_DMA_TRANSMITPROCESS_WAITING     ((uint32_t)0x00200000U)  /*!< Running - waiting for status */
01540 #define ETH_DMA_TRANSMITPROCESS_READING     ((uint32_t)0x00300000U)  /*!< Running - reading the data from host memory */
01541 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000U)  /*!< Suspended - Tx Descriptor unavailable */
01542 #define ETH_DMA_TRANSMITPROCESS_CLOSING     ((uint32_t)0x00700000U)  /*!< Running - closing Rx descriptor */
01543
01544 /**
01545   * @}
01546   */
01547
01548
01549 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
01550   * @{
01551   */
01552 #define ETH_DMA_RECEIVEPROCESS_STOPPED      ((uint32_t)0x00000000U)  /*!< Stopped - Reset or Stop Rx Command issued */
01553 #define ETH_DMA_RECEIVEPROCESS_FETCHING     ((uint32_t)0x00020000U)  /*!< Running - fetching the Rx descriptor */
01554 #define ETH_DMA_RECEIVEPROCESS_WAITING      ((uint32_t)0x00060000U)  /*!< Running - waiting for packet */
01555 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ((uint32_t)0x00080000U)  /*!< Suspended - Rx Descriptor unavailable */
01556 #define ETH_DMA_RECEIVEPROCESS_CLOSING      ((uint32_t)0x000A0000U)  /*!< Running - closing descriptor */
01557 #define ETH_DMA_RECEIVEPROCESS_QUEUING      ((uint32_t)0x000E0000U)  /*!< Running - queuing the receive frame into host memory */
01558
01559 /**
01560   * @}
01561   */
01562
01563 /** @defgroup ETH_DMA_overflow ETH DMA overflow
01564   * @{
01565   */
01566 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      ((uint32_t)0x10000000U)  /*!< Overflow bit for FIFO overflow counter */
01567 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U)  /*!< Overflow bit for missed frame counter */
01568 /**
01569   * @}
01570   */
01571
01572 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
01573   * @{
01574   */
01575 #define ETH_EXTI_LINE_WAKEUP              ((uint32_t)0x00080000U)  /*!< External interrupt line 19 Connected to the ETH EXTI Line */
01576
01577 /**
01578   * @}
01579   */
01580
01581 /**
01582   * @}
01583   */
01584
01585 /* Exported macro ------------------------------------------------------------*/
01586 /** @defgroup ETH_Exported_Macros ETH Exported Macros
01587  *  @brief macros to handle interrupts and specific clock configurations
01588  * @{
01589  */
01590
01591 /** @brief Reset ETH handle state
01592   * @param  __HANDLE__: specifies the ETH handle.
01593   * @retval None
01594   */
01595 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
01596
01597 /**
01598   * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
01599   * @param  __HANDLE__: ETH Handle
01600   * @param  __FLAG__: specifies the flag of TDES0 to check.
01601   * @retval the ETH_DMATxDescFlag (SET or RESET).
01602   */
01603 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
01604
01605 /**
01606   * @brief  Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
01607   * @param  __HANDLE__: ETH Handle
01608   * @param  __FLAG__: specifies the flag of RDES0 to check.
01609   * @retval the ETH_DMATxDescFlag (SET or RESET).
01610   */
01611 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
01612
01613 /**
01614   * @brief  Enables the specified DMA Rx Desc receive interrupt.
01615   * @param  __HANDLE__: ETH Handle
01616   * @retval None
01617   */
01618 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
01619
01620 /**
01621   * @brief  Disables the specified DMA Rx Desc receive interrupt.
01622   * @param  __HANDLE__: ETH Handle
01623   * @retval None
01624   */
01625 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
01626
01627 /**
01628   * @brief  Set the specified DMA Rx Desc Own bit.
01629   * @param  __HANDLE__: ETH Handle
01630   * @retval None
01631   */
01632 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
01633
01634 /**
01635   * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
01636   * @param  __HANDLE__: ETH Handle
01637   * @retval The Transmit descriptor collision counter value.
01638   */
01639 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
01640
01641 /**
01642   * @brief  Set the specified DMA Tx Desc Own bit.
01643   * @param  __HANDLE__: ETH Handle
01644   * @retval None
01645   */
01646 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
01647
01648 /**
01649   * @brief  Enables the specified DMA Tx Desc Transmit interrupt.
01650   * @param  __HANDLE__: ETH Handle
01651   * @retval None
01652   */
01653 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
01654
01655 /**
01656   * @brief  Disables the specified DMA Tx Desc Transmit interrupt.
01657   * @param  __HANDLE__: ETH Handle
01658   * @retval None
01659   */
01660 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
01661
01662 /**
01663   * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
01664   * @param  __HANDLE__: ETH Handle
01665   * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
01666   *   This parameter can be one of the following values:
01667   *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
01668   *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
01669   *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
01670   *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
01671   * @retval None
01672   */
01673 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
01674
01675 /**
01676   * @brief  Enables the DMA Tx Desc CRC.
01677   * @param  __HANDLE__: ETH Handle
01678   * @retval None
01679   */
01680 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
01681
01682 /**
01683   * @brief  Disables the DMA Tx Desc CRC.
01684   * @param  __HANDLE__: ETH Handle
01685   * @retval None
01686   */
01687 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
01688
01689 /**
01690   * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
01691   * @param  __HANDLE__: ETH Handle
01692   * @retval None
01693   */
01694 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
01695
01696 /**
01697   * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
01698   * @param  __HANDLE__: ETH Handle
01699   * @retval None
01700   */
01701 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
01702
01703 /**
01704  * @brief  Enables the specified ETHERNET MAC interrupts.
01705   * @param  __HANDLE__   : ETH Handle
01706   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01707   *   enabled or disabled.
01708   *   This parameter can be any combination of the following values:
01709   *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
01710   *     @arg ETH_MAC_IT_PMT : PMT interrupt
01711   * @retval None
01712   */
01713 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
01714
01715 /**
01716   * @brief  Disables the specified ETHERNET MAC interrupts.
01717   * @param  __HANDLE__   : ETH Handle
01718   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01719   *   enabled or disabled.
01720   *   This parameter can be any combination of the following values:
01721   *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
01722   *     @arg ETH_MAC_IT_PMT : PMT interrupt
01723   * @retval None
01724   */
01725 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
01726
01727 /**
01728   * @brief  Initiate a Pause Control Frame (Full-duplex only).
01729   * @param  __HANDLE__: ETH Handle
01730   * @retval None
01731   */
01732 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
01733
01734 /**
01735   * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
01736   * @param  __HANDLE__: ETH Handle
01737   * @retval The new state of flow control busy status bit (SET or RESET).
01738   */
01739 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
01740
01741 /**
01742   * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).
01743   * @param  __HANDLE__: ETH Handle
01744   * @retval None
01745   */
01746 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
01747
01748 /**
01749   * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).
01750   * @param  __HANDLE__: ETH Handle
01751   * @retval None
01752   */
01753 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
01754
01755 /**
01756   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
01757   * @param  __HANDLE__: ETH Handle
01758   * @param  __FLAG__: specifies the flag to check.
01759   *   This parameter can be one of the following values:
01760   *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
01761   *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
01762   *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag
01763   *     @arg ETH_MAC_FLAG_MMC  : MMC flag
01764   *     @arg ETH_MAC_FLAG_PMT  : PMT flag
01765   * @retval The state of ETHERNET MAC flag.
01766   */
01767 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
01768
01769 /**
01770   * @brief  Enables the specified ETHERNET DMA interrupts.
01771   * @param  __HANDLE__   : ETH Handle
01772   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01773   *   enabled @ref ETH_DMA_Interrupts
01774   * @retval None
01775   */
01776 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
01777
01778 /**
01779   * @brief  Disables the specified ETHERNET DMA interrupts.
01780   * @param  __HANDLE__   : ETH Handle
01781   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01782   *   disabled. @ref ETH_DMA_Interrupts
01783   * @retval None
01784   */
01785 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
01786
01787 /**
01788   * @brief  Clears the ETHERNET DMA IT pending bit.
01789   * @param  __HANDLE__   : ETH Handle
01790   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
01791   * @retval None
01792   */
01793 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
01794
01795 /**
01796   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01797 * @param  __HANDLE__: ETH Handle
01798   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
01799   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
01800   */
01801 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
01802
01803 /**
01804   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01805   * @param  __HANDLE__: ETH Handle
01806   * @param  __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
01807   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
01808   */
01809 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR = (__FLAG__))
01810
01811 /**
01812   * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
01813   * @param  __HANDLE__: ETH Handle
01814   * @param  __OVERFLOW__: specifies the DMA overflow flag to check.
01815   *   This parameter can be one of the following values:
01816   *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
01817   *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
01818   * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
01819   */
01820 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)       (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
01821
01822 /**
01823   * @brief  Set the DMA Receive status watchdog timer register value
01824   * @param  __HANDLE__: ETH Handle
01825   * @param  __VALUE__: DMA Receive status watchdog timer register value
01826   * @retval None
01827   */
01828 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
01829
01830 /**
01831   * @brief  Enables any unicast packet filtered by the MAC address
01832   *   recognition to be a wake-up frame.
01833   * @param  __HANDLE__: ETH Handle.
01834   * @retval None
01835   */
01836 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
01837
01838 /**
01839   * @brief  Disables any unicast packet filtered by the MAC address
01840   *   recognition to be a wake-up frame.
01841   * @param  __HANDLE__: ETH Handle.
01842   * @retval None
01843   */
01844 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
01845
01846 /**
01847   * @brief  Enables the MAC Wake-Up Frame Detection.
01848   * @param  __HANDLE__: ETH Handle.
01849   * @retval None
01850   */
01851 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
01852
01853 /**
01854   * @brief  Disables the MAC Wake-Up Frame Detection.
01855   * @param  __HANDLE__: ETH Handle.
01856   * @retval None
01857   */
01858 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
01859
01860 /**
01861   * @brief  Enables the MAC Magic Packet Detection.
01862   * @param  __HANDLE__: ETH Handle.
01863   * @retval None
01864   */
01865 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
01866
01867 /**
01868   * @brief  Disables the MAC Magic Packet Detection.
01869   * @param  __HANDLE__: ETH Handle.
01870   * @retval None
01871   */
01872 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
01873
01874 /**
01875   * @brief  Enables the MAC Power Down.
01876   * @param  __HANDLE__: ETH Handle
01877   * @retval None
01878   */
01879 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
01880
01881 /**
01882   * @brief  Disables the MAC Power Down.
01883   * @param  __HANDLE__: ETH Handle
01884   * @retval None
01885   */
01886 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
01887
01888 /**
01889   * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
01890   * @param  __HANDLE__: ETH Handle.
01891   * @param  __FLAG__: specifies the flag to check.
01892   *   This parameter can be one of the following values:
01893   *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
01894   *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
01895   *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
01896   * @retval The new state of ETHERNET PMT Flag (SET or RESET).
01897   */
01898 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
01899
01900 /**
01901   * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
01902   * @param   __HANDLE__: ETH Handle.
01903   * @retval None
01904   */
01905 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
01906
01907 /**
01908   * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
01909   * @param  __HANDLE__: ETH Handle.
01910   * @retval None
01911   */
01912 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
01913                                                                           (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
01914
01915 /**
01916   * @brief  Enables the MMC Counter Freeze.
01917   * @param  __HANDLE__: ETH Handle.
01918   * @retval None
01919   */
01920 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
01921
01922 /**
01923   * @brief  Disables the MMC Counter Freeze.
01924   * @param  __HANDLE__: ETH Handle.
01925   * @retval None
01926   */
01927 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
01928
01929 /**
01930   * @brief  Enables the MMC Reset On Read.
01931   * @param  __HANDLE__: ETH Handle.
01932   * @retval None
01933   */
01934 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
01935
01936 /**
01937   * @brief  Disables the MMC Reset On Read.
01938   * @param  __HANDLE__: ETH Handle.
01939   * @retval None
01940   */
01941 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
01942
01943 /**
01944   * @brief  Enables the MMC Counter Stop Rollover.
01945   * @param  __HANDLE__: ETH Handle.
01946   * @retval None
01947   */
01948 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
01949
01950 /**
01951   * @brief  Disables the MMC Counter Stop Rollover.
01952   * @param  __HANDLE__: ETH Handle.
01953   * @retval None
01954   */
01955 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
01956
01957 /**
01958   * @brief  Resets the MMC Counters.
01959   * @param   __HANDLE__: ETH Handle.
01960   * @retval None
01961   */
01962 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
01963
01964 /**
01965   * @brief  Enables the specified ETHERNET MMC Rx interrupts.
01966   * @param   __HANDLE__: ETH Handle.
01967   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
01968   *   This parameter can be one of the following values:
01969   *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
01970   *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
01971   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
01972   * @retval None
01973   */
01974 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
01975 /**
01976   * @brief  Disables the specified ETHERNET MMC Rx interrupts.
01977   * @param   __HANDLE__: ETH Handle.
01978   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
01979   *   This parameter can be one of the following values:
01980   *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
01981   *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
01982   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
01983   * @retval None
01984   */
01985 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
01986 /**
01987   * @brief  Enables the specified ETHERNET MMC Tx interrupts.
01988   * @param   __HANDLE__: ETH Handle.
01989   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
01990   *   This parameter can be one of the following values:
01991   *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
01992   *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
01993   *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
01994   * @retval None
01995   */
01996 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
01997
01998 /**
01999   * @brief  Disables the specified ETHERNET MMC Tx interrupts.
02000   * @param   __HANDLE__: ETH Handle.
02001   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
02002   *   This parameter can be one of the following values:
02003   *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
02004   *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
02005   *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
02006   * @retval None
02007   */
02008 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
02009
02010 /**
02011   * @brief  Enables the ETH External interrupt line.
02012   * @retval None
02013   */
02014 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
02015
02016 /**
02017   * @brief  Disables the ETH External interrupt line.
02018   * @retval None
02019   */
02020 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
02021
02022 /**
02023   * @brief Enable event on ETH External event line.
02024   * @retval None.
02025   */
02026 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()  EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
02027
02028 /**
02029   * @brief Disable event on ETH External event line
02030   * @retval None.
02031   */
02032 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
02033
02034 /**
02035   * @brief  Get flag of the ETH External interrupt line.
02036   * @retval None
02037   */
02038 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
02039
02040 /**
02041   * @brief  Clear flag of the ETH External interrupt line.
02042   * @retval None
02043   */
02044 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
02045
02046 /**
02047   * @brief  Enables rising edge trigger to the ETH External interrupt line.
02048   * @retval None
02049   */
02050 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
02051
02052 /**
02053   * @brief  Disables the rising edge trigger to the ETH External interrupt line.
02054   * @retval None
02055   */
02056 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
02057
02058 /**
02059   * @brief  Enables falling edge trigger to the ETH External interrupt line.
02060   * @retval None
02061   */
02062 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
02063
02064 /**
02065   * @brief  Disables falling edge trigger to the ETH External interrupt line.
02066   * @retval None
02067   */
02068 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
02069
02070 /**
02071   * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.
02072   * @retval None
02073   */
02074 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
02075                                                                  EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
02076                                                                 }while(0)
02077
02078 /**
02079   * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.
02080   * @retval None
02081   */
02082 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
02083                                                                  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
02084                                                                 }while(0)
02085
02086 /**
02087   * @brief Generate a Software interrupt on selected EXTI line.
02088   * @retval None.
02089   */
02090 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()                  EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
02091
02092 /**
02093   * @}
02094   */
02095 /* Exported functions --------------------------------------------------------*/
02096
02097 /** @addtogroup ETH_Exported_Functions
02098   * @{
02099   */
02100
02101 /* Initialization and de-initialization functions  ****************************/
02102
02103 /** @addtogroup ETH_Exported_Functions_Group1
02104   * @{
02105   */
02106 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
02107 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
02108 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
02109 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
02110 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
02111 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
02112
02113 /**
02114   * @}
02115   */
02116 /* IO operation functions  ****************************************************/
02117
02118 /** @addtogroup ETH_Exported_Functions_Group2
02119   * @{
02120   */
02121 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
02122 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
02123 /* Communication with PHY functions*/
02124 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
02125 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
02126 /* Non-Blocking mode: Interrupt */
02127 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
02128 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
02129 /* Callback in non blocking modes (Interrupt) */
02130 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
02131 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
02132 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
02133 /**
02134   * @}
02135   */
02136
02137 /* Peripheral Control functions  **********************************************/
02138
02139 /** @addtogroup ETH_Exported_Functions_Group3
02140   * @{
02141   */
02142
02143 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
02144 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
02145 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
02146 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
02147 /**
02148   * @}
02149   */
02150
02151 /* Peripheral State functions  ************************************************/
02152
02153 /** @addtogroup ETH_Exported_Functions_Group4
02154   * @{
02155   */
02156 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
02157 /**
02158   * @}
02159   */
02160
02161 /**
02162   * @}
02163   */
02164
02165 /**
02166   * @}
02167   */
02168
02169 /**
02170   * @}
02171   */
02172
02173 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
02174           STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
02175
02176 #ifdef __cplusplus
02177 }
02178 #endif
02179
02180 #endif /* __STM32F4xx_HAL_ETH_H */
02181
02182
02183 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash.c Source File

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stm32f4xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the internal FLASH memory:
00010   *           + Program operations functions
00011   *           + Memory Control functions
00012   *           + Peripheral Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### FLASH peripheral features #####
00017   ==============================================================================
00018
00019   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00020        to the Flash memory. It implements the erase and program Flash memory operations
00021        and the read and write protection mechanisms.
00022
00023   [..] The Flash memory interface accelerates code execution with a system of instruction
00024        prefetch and cache lines.
00025
00026   [..] The FLASH main features are:
00027       (+) Flash memory read operations
00028       (+) Flash memory program/erase operations
00029       (+) Read / write protections
00030       (+) Prefetch on I-Code
00031       (+) 64 cache lines of 128 bits on I-Code
00032       (+) 8 cache lines of 128 bits on D-Code
00033
00034
00035                      ##### How to use this driver #####
00036   ==============================================================================
00037     [..]
00038       This driver provides functions and macros to configure and program the FLASH
00039       memory of all STM32F4xx devices.
00040
00041       (#) FLASH Memory IO Programming functions:
00042            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00043                 HAL_FLASH_Lock() functions
00044            (++) Program functions: byte, half word, word and double word
00045            (++) There Two modes of programming :
00046             (+++) Polling mode using HAL_FLASH_Program() function
00047             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00048
00049       (#) Interrupts and flags management functions :
00050            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00051            (++) Wait for last FLASH operation according to its status
00052            (++) Get error flag status by calling HAL_SetErrorCode()
00053
00054     [..]
00055       In addition to these functions, this driver includes a set of macros allowing
00056       to handle the following operations:
00057        (+) Set the latency
00058        (+) Enable/Disable the prefetch buffer
00059        (+) Enable/Disable the Instruction cache and the Data cache
00060        (+) Reset the Instruction cache and the Data cache
00061        (+) Enable/Disable the FLASH interrupts
00062        (+) Monitor the FLASH flags status
00063
00064   @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00069   *
00070   * Redistribution and use in source and binary forms, with or without modification,
00071   * are permitted provided that the following conditions are met:
00072   *   1. Redistributions of source code must retain the above copyright notice,
00073   *      this list of conditions and the following disclaimer.
00074   *   2. Redistributions in binary form must reproduce the above copyright notice,
00075   *      this list of conditions and the following disclaimer in the documentation
00076   *      and/or other materials provided with the distribution.
00077   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00078   *      may be used to endorse or promote products derived from this software
00079   *      without specific prior written permission.
00080   *
00081   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00082   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00083   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00084   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00085   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00086   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00087   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00088   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00089   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00090   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00091   *
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32f4xx_hal.h"
00097
00098 /** @addtogroup STM32F4xx_HAL_Driver
00099   * @{
00100   */
00101
00102 /** @defgroup FLASH FLASH
00103   * @brief FLASH HAL module driver
00104   * @{
00105   */
00106
00107 #ifdef HAL_FLASH_MODULE_ENABLED
00108
00109 /* Private typedef -----------------------------------------------------------*/
00110 /* Private define ------------------------------------------------------------*/
00111 /** @addtogroup FLASH_Private_Constants
00112   * @{
00113   */
00114 #define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
00115 /**
00116   * @}
00117   */
00118 /* Private macro -------------------------------------------------------------*/
00119 /* Private variables ---------------------------------------------------------*/
00120 /** @addtogroup FLASH_Private_Variables
00121   * @{
00122   */
00123 /* Variable used for Erase sectors under interruption */
00124 FLASH_ProcessTypeDef pFlash;
00125 /**
00126   * @}
00127   */
00128
00129 /* Private function prototypes -----------------------------------------------*/
00130 /** @addtogroup FLASH_Private_Functions
00131   * @{
00132   */
00133 /* Program operations */
00134 static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
00135 static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
00136 static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
00137 static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
00138 static void   FLASH_SetErrorCode(void);
00139
00140 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported functions --------------------------------------------------------*/
00146 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00151  *  @brief   Programming operation functions
00152  *
00153 @verbatim
00154  ===============================================================================
00155                   ##### Programming operation functions #####
00156  ===============================================================================
00157     [..]
00158     This subsection provides a set of functions allowing to manage the FLASH
00159     program operations.
00160
00161 @endverbatim
00162   * @{
00163   */
00164
00165 /**
00166   * @brief  Program byte, halfword, word or double word at a specified address
00167   * @param  TypeProgram:  Indicate the way to program at a specified address.
00168   *                           This parameter can be a value of @ref FLASH_Type_Program
00169   * @param  Address:  specifies the address to be programmed.
00170   * @param  Data: specifies the data to be programmed
00171   *
00172   * @retval HAL_StatusTypeDef HAL Status
00173   */
00174 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00175 {
00176   HAL_StatusTypeDef status = HAL_ERROR;
00177
00178   /* Process Locked */
00179   __HAL_LOCK(&pFlash);
00180
00181   /* Check the parameters */
00182   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00183
00184   /* Wait for last operation to be completed */
00185   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00186
00187   if(status == HAL_OK)
00188   {
00189     if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
00190     {
00191       /*Program byte (8-bit) at a specified address.*/
00192       FLASH_Program_Byte(Address, (uint8_t) Data);
00193     }
00194     else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
00195     {
00196       /*Program halfword (16-bit) at a specified address.*/
00197       FLASH_Program_HalfWord(Address, (uint16_t) Data);
00198     }
00199     else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
00200     {
00201       /*Program word (32-bit) at a specified address.*/
00202       FLASH_Program_Word(Address, (uint32_t) Data);
00203     }
00204     else
00205     {
00206       /*Program double word (64-bit) at a specified address.*/
00207       FLASH_Program_DoubleWord(Address, Data);
00208     }
00209
00210     /* Wait for last operation to be completed */
00211     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00212
00213     /* If the program operation is completed, disable the PG Bit */
00214     FLASH->CR &= (~FLASH_CR_PG);
00215   }
00216
00217   /* Process Unlocked */
00218   __HAL_UNLOCK(&pFlash);
00219
00220   return status;
00221 }
00222
00223 /**
00224   * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
00225   * @param  TypeProgram:  Indicate the way to program at a specified address.
00226   *                           This parameter can be a value of @ref FLASH_Type_Program
00227   * @param  Address:  specifies the address to be programmed.
00228   * @param  Data: specifies the data to be programmed
00229   *
00230   * @retval HAL Status
00231   */
00232 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00233 {
00234   HAL_StatusTypeDef status = HAL_OK;
00235
00236   /* Process Locked */
00237   __HAL_LOCK(&pFlash);
00238
00239   /* Check the parameters */
00240   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00241
00242   /* Enable End of FLASH Operation interrupt */
00243   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
00244
00245   /* Enable Error source interrupt */
00246   __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
00247
00248   pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
00249   pFlash.Address = Address;
00250
00251   if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
00252   {
00253     /*Program byte (8-bit) at a specified address.*/
00254       FLASH_Program_Byte(Address, (uint8_t) Data);
00255   }
00256   else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
00257   {
00258     /*Program halfword (16-bit) at a specified address.*/
00259     FLASH_Program_HalfWord(Address, (uint16_t) Data);
00260   }
00261   else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
00262   {
00263     /*Program word (32-bit) at a specified address.*/
00264     FLASH_Program_Word(Address, (uint32_t) Data);
00265   }
00266   else
00267   {
00268     /*Program double word (64-bit) at a specified address.*/
00269     FLASH_Program_DoubleWord(Address, Data);
00270   }
00271
00272   return status;
00273 }
00274
00275 /**
00276   * @brief This function handles FLASH interrupt request.
00277   * @retval None
00278   */
00279 void HAL_FLASH_IRQHandler(void)
00280 {
00281   uint32_t addresstmp = 0U;
00282
00283   /* Check FLASH operation error flags */
00284   if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
00285     FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
00286   {
00287     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
00288     {
00289       /*return the faulty sector*/
00290       addresstmp = pFlash.Sector;
00291       pFlash.Sector = 0xFFFFFFFFU;
00292     }
00293     else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
00294     {
00295       /*return the faulty bank*/
00296       addresstmp = pFlash.Bank;
00297     }
00298     else
00299     {
00300       /*return the faulty address*/
00301       addresstmp = pFlash.Address;
00302     }
00303
00304     /*Save the Error code*/
00305     FLASH_SetErrorCode();
00306
00307     /* FLASH error interrupt user callback */
00308     HAL_FLASH_OperationErrorCallback(addresstmp);
00309
00310     /*Stop the procedure ongoing*/
00311     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00312   }
00313
00314   /* Check FLASH End of Operation flag  */
00315   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
00316   {
00317     /* Clear FLASH End of Operation pending bit */
00318     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00319
00320     if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
00321     {
00322       /*Nb of sector to erased can be decreased*/
00323       pFlash.NbSectorsToErase--;
00324
00325       /* Check if there are still sectors to erase*/
00326       if(pFlash.NbSectorsToErase != 0U)
00327       {
00328         addresstmp = pFlash.Sector;
00329         /*Indicate user which sector has been erased*/
00330         HAL_FLASH_EndOfOperationCallback(addresstmp);
00331
00332         /*Increment sector number*/
00333         pFlash.Sector++;
00334         addresstmp = pFlash.Sector;
00335         FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
00336       }
00337       else
00338       {
00339         /*No more sectors to Erase, user callback can be called.*/
00340         /*Reset Sector and stop Erase sectors procedure*/
00341         pFlash.Sector = addresstmp = 0xFFFFFFFFU;
00342         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00343
00344         /* Flush the caches to be sure of the data consistency */
00345         FLASH_FlushCaches() ;
00346
00347         /* FLASH EOP interrupt user callback */
00348         HAL_FLASH_EndOfOperationCallback(addresstmp);
00349       }
00350     }
00351     else
00352     {
00353       if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
00354       {
00355         /* MassErase ended. Return the selected bank */
00356         /* Flush the caches to be sure of the data consistency */
00357         FLASH_FlushCaches() ;
00358
00359         /* FLASH EOP interrupt user callback */
00360         HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
00361       }
00362       else
00363       {
00364         /*Program ended. Return the selected address*/
00365         /* FLASH EOP interrupt user callback */
00366         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00367       }
00368       pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00369     }
00370   }
00371
00372   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00373   {
00374     /* Operation is completed, disable the PG, SER, SNB and MER Bits */
00375     CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
00376
00377     /* Disable End of FLASH Operation interrupt */
00378     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
00379
00380     /* Disable Error source interrupt */
00381     __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
00382
00383     /* Process Unlocked */
00384     __HAL_UNLOCK(&pFlash);
00385   }
00386 }
00387
00388 /**
00389   * @brief  FLASH end of operation interrupt callback
00390   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00391   *                  Mass Erase: Bank number which has been requested to erase
00392   *                  Sectors Erase: Sector which has been erased
00393   *                    (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
00394   *                  Program: Address which was selected for data program
00395   * @retval None
00396   */
00397 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00398 {
00399   /* Prevent unused argument(s) compilation warning */
00400   UNUSED(ReturnValue);
00401   /* NOTE : This function Should not be modified, when the callback is needed,
00402             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00403    */
00404 }
00405
00406 /**
00407   * @brief  FLASH operation error interrupt callback
00408   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00409   *                 Mass Erase: Bank number which has been requested to erase
00410   *                 Sectors Erase: Sector number which returned an error
00411   *                 Program: Address which was selected for data program
00412   * @retval None
00413   */
00414 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00415 {
00416   /* Prevent unused argument(s) compilation warning */
00417   UNUSED(ReturnValue);
00418   /* NOTE : This function Should not be modified, when the callback is needed,
00419             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00420    */
00421 }
00422
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00428  *  @brief   management functions
00429  *
00430 @verbatim
00431  ===============================================================================
00432                       ##### Peripheral Control functions #####
00433  ===============================================================================
00434     [..]
00435     This subsection provides a set of functions allowing to control the FLASH
00436     memory operations.
00437
00438 @endverbatim
00439   * @{
00440   */
00441
00442 /**
00443   * @brief  Unlock the FLASH control register access
00444   * @retval HAL Status
00445   */
00446 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00447 {
00448   if((FLASH->CR & FLASH_CR_LOCK) != RESET)
00449   {
00450     /* Authorize the FLASH Registers access */
00451     FLASH->KEYR = FLASH_KEY1;
00452     FLASH->KEYR = FLASH_KEY2;
00453   }
00454   else
00455   {
00456     return HAL_ERROR;
00457   }
00458
00459   return HAL_OK;
00460 }
00461
00462 /**
00463   * @brief  Locks the FLASH control register access
00464   * @retval HAL Status
00465   */
00466 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00467 {
00468   /* Set the LOCK Bit to lock the FLASH Registers access */
00469   FLASH->CR |= FLASH_CR_LOCK;
00470
00471   return HAL_OK;
00472 }
00473
00474 /**
00475   * @brief  Unlock the FLASH Option Control Registers access.
00476   * @retval HAL Status
00477   */
00478 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00479 {
00480   if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
00481   {
00482     /* Authorizes the Option Byte register programming */
00483     FLASH->OPTKEYR = FLASH_OPT_KEY1;
00484     FLASH->OPTKEYR = FLASH_OPT_KEY2;
00485   }
00486   else
00487   {
00488     return HAL_ERROR;
00489   }
00490
00491   return HAL_OK;
00492 }
00493
00494 /**
00495   * @brief  Lock the FLASH Option Control Registers access.
00496   * @retval HAL Status
00497   */
00498 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00499 {
00500   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00501   FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
00502
00503   return HAL_OK;
00504 }
00505
00506 /**
00507   * @brief  Launch the option byte loading.
00508   * @retval HAL Status
00509   */
00510 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00511 {
00512   /* Set the OPTSTRT bit in OPTCR register */
00513   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
00514
00515   /* Wait for last operation to be completed */
00516   return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
00517 }
00518
00519 /**
00520   * @}
00521   */
00522
00523 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
00524  *  @brief   Peripheral Errors functions
00525  *
00526 @verbatim
00527  ===============================================================================
00528                 ##### Peripheral Errors functions #####
00529  ===============================================================================
00530     [..]
00531     This subsection permits to get in run-time Errors of the FLASH peripheral.
00532
00533 @endverbatim
00534   * @{
00535   */
00536
00537 /**
00538   * @brief  Get the specific FLASH error flag.
00539   * @retval FLASH_ErrorCode: The returned value can be a combination of:
00540   *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
00541   *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
00542   *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
00543   *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
00544   *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
00545   *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
00546   */
00547 uint32_t HAL_FLASH_GetError(void)
00548 {
00549    return pFlash.ErrorCode;
00550 }
00551
00552 /**
00553   * @}
00554   */
00555
00556 /**
00557   * @brief  Wait for a FLASH operation to complete.
00558   * @param  Timeout: maximum flash operationtimeout
00559   * @retval HAL Status
00560   */
00561 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00562 {
00563   uint32_t tickstart = 0U;
00564
00565   /* Clear Error Code */
00566   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00567
00568   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00569      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00570      flag will be set */
00571   /* Get tick */
00572   tickstart = HAL_GetTick();
00573
00574   while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
00575   {
00576     if(Timeout != HAL_MAX_DELAY)
00577     {
00578       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00579       {
00580         return HAL_TIMEOUT;
00581       }
00582     }
00583   }
00584
00585   /* Check FLASH End of Operation flag  */
00586   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00587   {
00588     /* Clear FLASH End of Operation pending bit */
00589     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00590   }
00591
00592   if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
00593                            FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
00594   {
00595     /*Save the error code*/
00596     FLASH_SetErrorCode();
00597     return HAL_ERROR;
00598   }
00599
00600   /* If there is no error flag set */
00601   return HAL_OK;
00602
00603 }
00604
00605 /**
00606   * @brief  Program a double word (64-bit) at a specified address.
00607   * @note   This function must be used when the device voltage range is from
00608   *         2.7V to 3.6V and Vpp in the range 7V to 9V.
00609   *
00610   * @note   If an erase and a program operations are requested simultaneously,
00611   *         the erase operation is performed before the program one.
00612   *
00613   * @param  Address: specifies the address to be programmed.
00614   * @param  Data: specifies the data to be programmed.
00615   * @retval None
00616   */
00617 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
00618 {
00619   /* Check the parameters */
00620   assert_param(IS_FLASH_ADDRESS(Address));
00621
00622   /* If the previous operation is completed, proceed to program the new data */
00623   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
00624   FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
00625   FLASH->CR |= FLASH_CR_PG;
00626
00627   *(__IO uint64_t*)Address = Data;
00628 }
00629
00630
00631 /**
00632   * @brief  Program word (32-bit) at a specified address.
00633   * @note   This function must be used when the device voltage range is from
00634   *         2.7V to 3.6V.
00635   *
00636   * @note   If an erase and a program operations are requested simultaneously,
00637   *         the erase operation is performed before the program one.
00638   *
00639   * @param  Address: specifies the address to be programmed.
00640   * @param  Data: specifies the data to be programmed.
00641   * @retval None
00642   */
00643 static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
00644 {
00645   /* Check the parameters */
00646   assert_param(IS_FLASH_ADDRESS(Address));
00647
00648   /* If the previous operation is completed, proceed to program the new data */
00649   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
00650   FLASH->CR |= FLASH_PSIZE_WORD;
00651   FLASH->CR |= FLASH_CR_PG;
00652
00653   *(__IO uint32_t*)Address = Data;
00654 }
00655
00656 /**
00657   * @brief  Program a half-word (16-bit) at a specified address.
00658   * @note   This function must be used when the device voltage range is from
00659   *         2.1V to 3.6V.
00660   *
00661   * @note   If an erase and a program operations are requested simultaneously,
00662   *         the erase operation is performed before the program one.
00663   *
00664   * @param  Address: specifies the address to be programmed.
00665   * @param  Data: specifies the data to be programmed.
00666   * @retval None
00667   */
00668 static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
00669 {
00670   /* Check the parameters */
00671   assert_param(IS_FLASH_ADDRESS(Address));
00672
00673   /* If the previous operation is completed, proceed to program the new data */
00674   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
00675   FLASH->CR |= FLASH_PSIZE_HALF_WORD;
00676   FLASH->CR |= FLASH_CR_PG;
00677
00678   *(__IO uint16_t*)Address = Data;
00679 }
00680
00681 /**
00682   * @brief  Program byte (8-bit) at a specified address.
00683   * @note   This function must be used when the device voltage range is from
00684   *         1.8V to 3.6V.
00685   *
00686   * @note   If an erase and a program operations are requested simultaneously,
00687   *         the erase operation is performed before the program one.
00688   *
00689   * @param  Address: specifies the address to be programmed.
00690   * @param  Data: specifies the data to be programmed.
00691   * @retval None
00692   */
00693 static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
00694 {
00695   /* Check the parameters */
00696   assert_param(IS_FLASH_ADDRESS(Address));
00697
00698   /* If the previous operation is completed, proceed to program the new data */
00699   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
00700   FLASH->CR |= FLASH_PSIZE_BYTE;
00701   FLASH->CR |= FLASH_CR_PG;
00702
00703   *(__IO uint8_t*)Address = Data;
00704 }
00705
00706 /**
00707   * @brief  Set the specific FLASH error flag.
00708   * @retval None
00709   */
00710 static void FLASH_SetErrorCode(void)
00711 {
00712   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
00713   {
00714    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
00715
00716    /* Clear FLASH write protection error pending bit */
00717    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
00718   }
00719
00720   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
00721   {
00722    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
00723
00724    /* Clear FLASH Programming alignment error pending bit */
00725    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
00726   }
00727
00728   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
00729   {
00730     pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
00731
00732     /* Clear FLASH Programming parallelism error pending bit */
00733     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
00734   }
00735
00736   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
00737   {
00738     pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
00739
00740     /* Clear FLASH Programming sequence error pending bit */
00741     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
00742   }
00743
00744   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
00745   {
00746     pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
00747
00748     /* Clear FLASH Proprietary readout protection error pending bit */
00749     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
00750   }
00751
00752   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
00753   {
00754     pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
00755
00756     /* Clear FLASH Operation error pending bit */
00757     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
00758   }
00759 }
00760
00761 /**
00762   * @}
00763   */
00764
00765 #endif /* HAL_FLASH_MODULE_ENABLED */
00766
00767 /**
00768   * @}
00769   */
00770
00771 /**
00772   * @}
00773   */
00774
00775 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash.h Source File

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stm32f4xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of FLASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_FLASH_H
00040 #define __STM32F4xx_HAL_FLASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASH
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  FLASH Procedure structure definition
00064   */
00065 typedef enum
00066 {
00067   FLASH_PROC_NONE = 0U,
00068   FLASH_PROC_SECTERASE,
00069   FLASH_PROC_MASSERASE,
00070   FLASH_PROC_PROGRAM
00071 } FLASH_ProcedureTypeDef;
00072
00073 /**
00074   * @brief  FLASH handle Structure definition
00075   */
00076 typedef struct
00077 {
00078   __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/
00079
00080   __IO uint32_t               NbSectorsToErase;   /*Internal variable to save the remaining sectors to erase in IT context*/
00081
00082   __IO uint8_t                VoltageForErase;    /*Internal variable to provide voltage range selected by user in IT context*/
00083
00084   __IO uint32_t               Sector;             /*Internal variable to define the current sector which is erasing*/
00085
00086   __IO uint32_t               Bank;               /*Internal variable to save current bank selected during mass erase*/
00087
00088   __IO uint32_t               Address;            /*Internal variable to save address selected for program*/
00089
00090   HAL_LockTypeDef             Lock;               /* FLASH locking object                */
00091
00092   __IO uint32_t               ErrorCode;          /* FLASH error code                    */
00093
00094 }FLASH_ProcessTypeDef;
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00102   * @{
00103   */
00104 /** @defgroup FLASH_Error_Code FLASH Error Code
00105   * @brief    FLASH Error Code
00106   * @{
00107   */
00108 #define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)    /*!< No error                      */
00109 #define HAL_FLASH_ERROR_RD           ((uint32_t)0x00000001U)    /*!< Read Protection error         */
00110 #define HAL_FLASH_ERROR_PGS          ((uint32_t)0x00000002U)    /*!< Programming Sequence error    */
00111 #define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004U)    /*!< Programming Parallelism error */
00112 #define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */
00113 #define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */
00114 #define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup FLASH_Type_Program FLASH Type Program
00120   * @{
00121   */
00122 #define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00U)  /*!< Program byte (8-bit) at a specified address           */
00123 #define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01U)  /*!< Program a half-word (16-bit) at a specified address   */
00124 #define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02U)  /*!< Program a word (32-bit) at a specified address        */
00125 #define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03U)  /*!< Program a double word (64-bit) at a specified address */
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup FLASH_Flag_definition FLASH Flag definition
00131   * @brief Flag definition
00132   * @{
00133   */
00134 #define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
00135 #define FLASH_FLAG_OPERR               FLASH_SR_SOP            /*!< FLASH operation Error flag                */
00136 #define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
00137 #define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
00138 #define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
00139 #define FLASH_FLAG_PGSERR              FLASH_SR_PGSERR         /*!< FLASH Programming Sequence error flag     */
00140 #define FLASH_FLAG_RDERR               ((uint32_t)0x00000100U)  /*!< Read Protection error flag (PCROP)        */
00141 #define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
00147   * @brief FLASH Interrupt definition
00148   * @{
00149   */
00150 #define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
00151 #define FLASH_IT_ERR                   ((uint32_t)0x02000000U)  /*!< Error Interrupt source                  */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
00157   * @{
00158   */
00159 #define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)
00160 #define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100U)
00161 #define FLASH_PSIZE_WORD           ((uint32_t)0x00000200U)
00162 #define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300U)
00163 #define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup FLASH_Keys FLASH Keys
00169   * @{
00170   */
00171 #define RDP_KEY                  ((uint16_t)0x00A5U)
00172 #define FLASH_KEY1               ((uint32_t)0x45670123U)
00173 #define FLASH_KEY2               ((uint32_t)0xCDEF89ABU)
00174 #define FLASH_OPT_KEY1           ((uint32_t)0x08192A3BU)
00175 #define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7FU)
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /* Exported macro ------------------------------------------------------------*/
00185 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00186   * @{
00187   */
00188 /**
00189   * @brief  Set the FLASH Latency.
00190   * @param  __LATENCY__: FLASH Latency
00191   *         The value of this parameter depend on device used within the same series
00192   * @retval none
00193   */
00194 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
00195
00196 /**
00197   * @brief  Get the FLASH Latency.
00198   * @retval FLASH Latency
00199   *          The value of this parameter depend on device used within the same series
00200   */
00201 #define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
00202
00203 /**
00204   * @brief  Enable the FLASH prefetch buffer.
00205   * @retval none
00206   */
00207 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
00208
00209 /**
00210   * @brief  Disable the FLASH prefetch buffer.
00211   * @retval none
00212   */
00213 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
00214
00215 /**
00216   * @brief  Enable the FLASH instruction cache.
00217   * @retval none
00218   */
00219 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_ICEN)
00220
00221 /**
00222   * @brief  Disable the FLASH instruction cache.
00223   * @retval none
00224   */
00225 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_ICEN))
00226
00227 /**
00228   * @brief  Enable the FLASH data cache.
00229   * @retval none
00230   */
00231 #define __HAL_FLASH_DATA_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_DCEN)
00232
00233 /**
00234   * @brief  Disable the FLASH data cache.
00235   * @retval none
00236   */
00237 #define __HAL_FLASH_DATA_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_DCEN))
00238
00239 /**
00240   * @brief  Resets the FLASH instruction Cache.
00241   * @note   This function must be used only when the Instruction Cache is disabled.
00242   * @retval None
00243   */
00244 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \
00245                                                   FLASH->ACR &= ~FLASH_ACR_ICRST; \
00246                                                  }while(0)
00247
00248 /**
00249   * @brief  Resets the FLASH data Cache.
00250   * @note   This function must be used only when the data Cache is disabled.
00251   * @retval None
00252   */
00253 #define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \
00254                                            FLASH->ACR &= ~FLASH_ACR_DCRST; \
00255                                           }while(0)
00256 /**
00257   * @brief  Enable the specified FLASH interrupt.
00258   * @param  __INTERRUPT__ : FLASH interrupt
00259   *         This parameter can be any combination of the following values:
00260   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00261   *     @arg FLASH_IT_ERR: Error Interrupt
00262   * @retval none
00263   */
00264 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
00265
00266 /**
00267   * @brief  Disable the specified FLASH interrupt.
00268   * @param  __INTERRUPT__ : FLASH interrupt
00269   *         This parameter can be any combination of the following values:
00270   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00271   *     @arg FLASH_IT_ERR: Error Interrupt
00272   * @retval none
00273   */
00274 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
00275
00276 /**
00277   * @brief  Get the specified FLASH flag status.
00278   * @param  __FLAG__: specifies the FLASH flag to check.
00279   *          This parameter can be one of the following values:
00280   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
00281   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
00282   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
00283   *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
00284   *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
00285   *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
00286   *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
00287   *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
00288   * @retval The new state of __FLAG__ (SET or RESET).
00289   */
00290 #define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__))==(__FLAG__))
00291
00292 /**
00293   * @brief  Clear the specified FLASH flag.
00294   * @param  __FLAG__: specifies the FLASH flags to clear.
00295   *          This parameter can be any combination of the following values:
00296   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag
00297   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag
00298   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
00299   *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
00300   *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
00301   *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
00302   *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
00303   * @retval none
00304   */
00305 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
00306 /**
00307   * @}
00308   */
00309
00310 /* Include FLASH HAL Extension module */
00311 #include "stm32f4xx_hal_flash_ex.h"
00312 #include "stm32f4xx_hal_flash_ramfunc.h"
00313
00314 /* Exported functions --------------------------------------------------------*/
00315 /** @addtogroup FLASH_Exported_Functions
00316   * @{
00317   */
00318 /** @addtogroup FLASH_Exported_Functions_Group1
00319   * @{
00320   */
00321 /* Program operation functions  ***********************************************/
00322 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00323 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00324 /* FLASH IRQ handler method */
00325 void HAL_FLASH_IRQHandler(void);
00326 /* Callbacks in non blocking modes */
00327 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00328 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00329 /**
00330   * @}
00331   */
00332
00333 /** @addtogroup FLASH_Exported_Functions_Group2
00334   * @{
00335   */
00336 /* Peripheral Control functions  **********************************************/
00337 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
00338 HAL_StatusTypeDef HAL_FLASH_Lock(void);
00339 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
00340 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
00341 /* Option bytes control */
00342 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
00343 /**
00344   * @}
00345   */
00346
00347 /** @addtogroup FLASH_Exported_Functions_Group3
00348   * @{
00349   */
00350 /* Peripheral State functions  ************************************************/
00351 uint32_t HAL_FLASH_GetError(void);
00352 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
00353 /**
00354   * @}
00355   */
00356
00357 /**
00358   * @}
00359   */
00360 /* Private types -------------------------------------------------------------*/
00361 /* Private variables ---------------------------------------------------------*/
00362 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00363   * @{
00364   */
00365
00366 /**
00367   * @}
00368   */
00369 /* Private constants ---------------------------------------------------------*/
00370 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00371   * @{
00372   */
00373
00374 /**
00375   * @brief   ACR register byte 0 (Bits[7:0]) base address
00376   */
00377 #define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00U)
00378 /**
00379   * @brief   OPTCR register byte 0 (Bits[7:0]) base address
00380   */
00381 #define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14U)
00382 /**
00383   * @brief   OPTCR register byte 1 (Bits[15:8]) base address
00384   */
00385 #define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15U)
00386 /**
00387   * @brief   OPTCR register byte 2 (Bits[23:16]) base address
00388   */
00389 #define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16U)
00390 /**
00391   * @brief   OPTCR register byte 3 (Bits[31:24]) base address
00392   */
00393 #define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17U)
00394
00395 /**
00396   * @}
00397   */
00398
00399 /* Private macros ------------------------------------------------------------*/
00400 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00401   * @{
00402   */
00403
00404 /** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
00405   * @{
00406   */
00407 #define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
00408                                     ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
00409                                     ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
00410                                     ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
00411 /**
00412   * @}
00413   */
00414
00415 /**
00416   * @}
00417   */
00418
00419 /* Private functions ---------------------------------------------------------*/
00420 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00421   * @{
00422   */
00423
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /**
00433   * @}
00434   */
00435
00436 #ifdef __cplusplus
00437 }
00438 #endif
00439
00440 #endif /* __STM32F4xx_HAL_FLASH_H */
00441
00442 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ex.c Source File

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stm32f4xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Extended FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the FLASH extension peripheral:
00010   *           + Extended programming operations functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                    ##### Flash Extension features #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and
00018        STM32F429xx/439xx devices contains the following additional features
00019
00020        (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
00021            capability (RWW)
00022        (+) Dual bank memory organization
00023        (+) PCROP protection for all banks
00024
00025                       ##### How to use this driver #####
00026   ==============================================================================
00027   [..] This driver provides functions to configure and program the FLASH memory
00028        of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
00029        devices. It includes
00030       (#) FLASH Memory Erase functions:
00031            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00032                 HAL_FLASH_Lock() functions
00033            (++) Erase function: Erase sector, erase all sectors
00034            (++) There are two modes of erase :
00035              (+++) Polling Mode using HAL_FLASHEx_Erase()
00036              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00037
00038       (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
00039            (++) Set/Reset the write protection
00040            (++) Set the Read protection Level
00041            (++) Set the BOR level
00042            (++) Program the user Option Bytes
00043       (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
00044        (++) Extended space (bank 2) erase function
00045        (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
00046        (++) Dual Boot activation
00047        (++) Write protection configuration for bank 2
00048        (++) PCROP protection configuration and control for both banks
00049
00050   @endverbatim
00051   ******************************************************************************
00052   * @attention
00053   *
00054   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00055   *
00056   * Redistribution and use in source and binary forms, with or without modification,
00057   * are permitted provided that the following conditions are met:
00058   *   1. Redistributions of source code must retain the above copyright notice,
00059   *      this list of conditions and the following disclaimer.
00060   *   2. Redistributions in binary form must reproduce the above copyright notice,
00061   *      this list of conditions and the following disclaimer in the documentation
00062   *      and/or other materials provided with the distribution.
00063   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00064   *      may be used to endorse or promote products derived from this software
00065   *      without specific prior written permission.
00066   *
00067   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00068   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00069   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00070   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00071   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00072   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00073   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00074   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00075   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00076   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00077   *
00078   ******************************************************************************
00079   */
00080
00081 /* Includes ------------------------------------------------------------------*/
00082 #include "stm32f4xx_hal.h"
00083
00084 /** @addtogroup STM32F4xx_HAL_Driver
00085   * @{
00086   */
00087
00088 /** @defgroup FLASHEx FLASHEx
00089   * @brief FLASH HAL Extension module driver
00090   * @{
00091   */
00092
00093 #ifdef HAL_FLASH_MODULE_ENABLED
00094
00095 /* Private typedef -----------------------------------------------------------*/
00096 /* Private define ------------------------------------------------------------*/
00097 /** @addtogroup FLASHEx_Private_Constants
00098   * @{
00099   */
00100 #define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */
00101 /**
00102   * @}
00103   */
00104
00105 /* Private macro -------------------------------------------------------------*/
00106 /* Private variables ---------------------------------------------------------*/
00107 /** @addtogroup FLASHEx_Private_Variables
00108   * @{
00109   */
00110 extern FLASH_ProcessTypeDef pFlash;
00111 /**
00112   * @}
00113   */
00114
00115 /* Private function prototypes -----------------------------------------------*/
00116 /** @addtogroup FLASHEx_Private_Functions
00117   * @{
00118   */
00119 /* Option bytes control */
00120 static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
00121 static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
00122 static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
00123 static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
00124 static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
00125 static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
00126 static uint8_t            FLASH_OB_GetUser(void);
00127 static uint16_t           FLASH_OB_GetWRP(void);
00128 static uint8_t            FLASH_OB_GetRDP(void);
00129 static uint8_t            FLASH_OB_GetBOR(void);
00130
00131 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
00132     defined(STM32F446xx)
00133 static HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);
00134 static HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);
00135 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00136
00137 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00138 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
00139 static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
00140 static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
00141 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00142
00143 extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported functions --------------------------------------------------------*/
00149 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
00150   * @{
00151   */
00152
00153 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
00154  *  @brief   Extended IO operation functions
00155  *
00156 @verbatim
00157  ===============================================================================
00158                 ##### Extended programming operation functions #####
00159  ===============================================================================
00160     [..]
00161     This subsection provides a set of functions allowing to manage the Extension FLASH
00162     programming operations.
00163
00164 @endverbatim
00165   * @{
00166   */
00167 /**
00168   * @brief  Perform a mass erase or erase the specified FLASH memory sectors
00169   * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
00170   *         contains the configuration information for the erasing.
00171   *
00172   * @param[out]  SectorError: pointer to variable  that
00173   *         contains the configuration information on faulty sector in case of error
00174   *         (0xFFFFFFFFU means that all the sectors have been correctly erased)
00175   *
00176   * @retval HAL Status
00177   */
00178 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
00179 {
00180   HAL_StatusTypeDef status = HAL_ERROR;
00181   uint32_t index = 0U;
00182
00183   /* Process Locked */
00184   __HAL_LOCK(&pFlash);
00185
00186   /* Check the parameters */
00187   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00188
00189   /* Wait for last operation to be completed */
00190   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00191
00192   if(status == HAL_OK)
00193   {
00194     /*Initialization of SectorError variable*/
00195     *SectorError = 0xFFFFFFFFU;
00196
00197     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00198     {
00199       /*Mass erase to be done*/
00200       FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
00201
00202       /* Wait for last operation to be completed */
00203       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00204
00205       /* if the erase operation is completed, disable the MER Bit */
00206       FLASH->CR &= (~FLASH_MER_BIT);
00207     }
00208     else
00209     {
00210       /* Check the parameters */
00211       assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
00212
00213       /* Erase by sector by sector to be done*/
00214       for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
00215       {
00216         FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
00217
00218         /* Wait for last operation to be completed */
00219         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00220
00221         /* If the erase operation is completed, disable the SER and SNB Bits */
00222         CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
00223
00224         if(status != HAL_OK)
00225         {
00226           /* In case of error, stop erase procedure and return the faulty sector*/
00227           *SectorError = index;
00228           break;
00229         }
00230       }
00231     }
00232     /* Flush the caches to be sure of the data consistency */
00233     FLASH_FlushCaches();
00234   }
00235
00236   /* Process Unlocked */
00237   __HAL_UNLOCK(&pFlash);
00238
00239   return status;
00240 }
00241
00242 /**
00243   * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
00244   * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
00245   *         contains the configuration information for the erasing.
00246   *
00247   * @retval HAL Status
00248   */
00249 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00250 {
00251   HAL_StatusTypeDef status = HAL_OK;
00252
00253   /* Process Locked */
00254   __HAL_LOCK(&pFlash);
00255
00256   /* Check the parameters */
00257   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00258
00259   /* Enable End of FLASH Operation interrupt */
00260   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
00261
00262   /* Enable Error source interrupt */
00263   __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
00264
00265   /* Clear pending flags (if any) */
00266   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
00267                          FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);
00268
00269   if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00270   {
00271     /*Mass erase to be done*/
00272     pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
00273     pFlash.Bank = pEraseInit->Banks;
00274     FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
00275   }
00276   else
00277   {
00278     /* Erase by sector to be done*/
00279
00280     /* Check the parameters */
00281     assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
00282
00283     pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
00284     pFlash.NbSectorsToErase = pEraseInit->NbSectors;
00285     pFlash.Sector = pEraseInit->Sector;
00286     pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
00287
00288     /*Erase 1st sector and wait for IT*/
00289     FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
00290   }
00291
00292   return status;
00293 }
00294
00295 /**
00296   * @brief   Program option bytes
00297   * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
00298   *         contains the configuration information for the programming.
00299   *
00300   * @retval HAL Status
00301   */
00302 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00303 {
00304   HAL_StatusTypeDef status = HAL_ERROR;
00305
00306   /* Process Locked */
00307   __HAL_LOCK(&pFlash);
00308
00309   /* Check the parameters */
00310   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00311
00312   /*Write protection configuration*/
00313   if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
00314   {
00315     assert_param(IS_WRPSTATE(pOBInit->WRPState));
00316     if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
00317     {
00318       /*Enable of Write protection on the selected Sector*/
00319       status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
00320     }
00321     else
00322     {
00323       /*Disable of Write protection on the selected Sector*/
00324       status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
00325     }
00326   }
00327
00328   /*Read protection configuration*/
00329   if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
00330   {
00331     status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
00332   }
00333
00334   /*USER  configuration*/
00335   if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
00336   {
00337     status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW,
00338                                      pOBInit->USERConfig&OB_STOP_NO_RST,
00339                                      pOBInit->USERConfig&OB_STDBY_NO_RST);
00340   }
00341
00342   /*BOR Level  configuration*/
00343   if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
00344   {
00345     status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
00346   }
00347
00348   /* Process Unlocked */
00349   __HAL_UNLOCK(&pFlash);
00350
00351   return status;
00352 }
00353
00354 /**
00355   * @brief   Get the Option byte configuration
00356   * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
00357   *         contains the configuration information for the programming.
00358   *
00359   * @retval None
00360   */
00361 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00362 {
00363   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
00364
00365   /*Get WRP*/
00366   pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
00367
00368   /*Get RDP Level*/
00369   pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
00370
00371   /*Get USER*/
00372   pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
00373
00374   /*Get BOR Level*/
00375   pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
00376 }
00377
00378 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00379     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00380     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00381     defined(STM32F479xx)
00382 /**
00383   * @brief   Program option bytes
00384   * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
00385   *         contains the configuration information for the programming.
00386   *
00387   * @retval HAL Status
00388   */
00389 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
00390 {
00391   HAL_StatusTypeDef status = HAL_ERROR;
00392
00393   /* Check the parameters */
00394   assert_param(IS_OBEX(pAdvOBInit->OptionType));
00395
00396   /*Program PCROP option byte*/
00397   if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
00398   {
00399     /* Check the parameters */
00400     assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
00401     if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
00402     {
00403       /*Enable of Write protection on the selected Sector*/
00404 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
00405     defined(STM32F411xE) || defined(STM32F446xx)
00406       status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
00407 #else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00408       status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
00409 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00410     }
00411     else
00412     {
00413       /*Disable of Write protection on the selected Sector*/
00414 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
00415     defined(STM32F411xE) || defined(STM32F446xx)
00416       status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
00417 #else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00418       status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
00419 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00420     }
00421   }
00422
00423 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00424   /*Program BOOT config option byte*/
00425   if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
00426   {
00427     status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
00428   }
00429 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00430
00431   return status;
00432 }
00433
00434 /**
00435   * @brief   Get the OBEX byte configuration
00436   * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
00437   *         contains the configuration information for the programming.
00438   *
00439   * @retval None
00440   */
00441 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
00442 {
00443 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
00444     defined(STM32F411xE) || defined(STM32F446xx)
00445   /*Get Sector*/
00446   pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
00447 #else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00448   /*Get Sector for Bank1*/
00449   pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
00450
00451   /*Get Sector for Bank2*/
00452   pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
00453
00454   /*Get Boot config OB*/
00455   pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
00456 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00457 }
00458
00459 /**
00460   * @brief  Select the Protection Mode
00461   *
00462   * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
00463   *         Global Read Out Protection modification (from level1 to level0)
00464   * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
00465   * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
00466   * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
00467   *         STM32F469xx/STM32F479xx devices.
00468   *
00469   * @retval HAL Status
00470   */
00471 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
00472 {
00473   uint8_t optiontmp = 0xFFU;
00474
00475   /* Mask SPRMOD bit */
00476   optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU);
00477
00478   /* Update Option Byte */
00479   *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
00480
00481   return HAL_OK;
00482 }
00483
00484 /**
00485   * @brief  Deselect the Protection Mode
00486   *
00487   * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
00488   *         Global Read Out Protection modification (from level1 to level0)
00489   * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
00490   * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
00491   * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
00492   *         STM32F469xx/STM32F479xx devices.
00493   *
00494   * @retval HAL Status
00495   */
00496 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
00497 {
00498   uint8_t optiontmp = 0xFFU;
00499
00500   /* Mask SPRMOD bit */
00501   optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7FU);
00502
00503   /* Update Option Byte */
00504   *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);
00505
00506   return HAL_OK;
00507 }
00508 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
00509           STM32F411xE || STM32F469xx || STM32F479xx */
00510
00511 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00512 /**
00513   * @brief  Returns the FLASH Write Protection Option Bytes value for Bank 2
00514   * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.
00515   * @retval The FLASH Write Protection  Option Bytes value
00516   */
00517 uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
00518 {
00519   /* Return the FLASH write protection Register value */
00520   return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
00521 }
00522 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00523
00524 /**
00525   * @}
00526   */
00527
00528 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00529 /**
00530   * @brief  Full erase of FLASH memory sectors
00531   * @param  VoltageRange: The device voltage range which defines the erase parallelism.
00532   *          This parameter can be one of the following values:
00533   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
00534   *                                  the operation will be done by byte (8-bit)
00535   *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
00536   *                                  the operation will be done by half word (16-bit)
00537   *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
00538   *                                  the operation will be done by word (32-bit)
00539   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
00540   *                                  the operation will be done by double word (64-bit)
00541   *
00542   * @param  Banks: Banks to be erased
00543   *          This parameter can be one of the following values:
00544   *            @arg FLASH_BANK_1: Bank1 to be erased
00545   *            @arg FLASH_BANK_2: Bank2 to be erased
00546   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
00547   *
00548   * @retval HAL Status
00549   */
00550 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
00551 {
00552   /* Check the parameters */
00553   assert_param(IS_VOLTAGERANGE(VoltageRange));
00554   assert_param(IS_FLASH_BANK(Banks));
00555
00556   /* if the previous operation is completed, proceed to erase all sectors */
00557   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
00558
00559   if(Banks == FLASH_BANK_BOTH)
00560   {
00561     /* bank1 & bank2 will be erased*/
00562     FLASH->CR |= FLASH_MER_BIT;
00563   }
00564   else if(Banks == FLASH_BANK_1)
00565   {
00566     /*Only bank1 will be erased*/
00567     FLASH->CR |= FLASH_CR_MER1;
00568   }
00569   else
00570   {
00571     /*Only bank2 will be erased*/
00572     FLASH->CR |= FLASH_CR_MER2;
00573   }
00574   FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
00575 }
00576
00577 /**
00578   * @brief  Erase the specified FLASH memory sector
00579   * @param  Sector: FLASH sector to erase
00580   *         The value of this parameter depend on device used within the same series
00581   * @param  VoltageRange: The device voltage range which defines the erase parallelism.
00582   *          This parameter can be one of the following values:
00583   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
00584   *                                  the operation will be done by byte (8-bit)
00585   *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
00586   *                                  the operation will be done by half word (16-bit)
00587   *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
00588   *                                  the operation will be done by word (32-bit)
00589   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
00590   *                                  the operation will be done by double word (64-bit)
00591   *
00592   * @retval None
00593   */
00594 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
00595 {
00596   uint32_t tmp_psize = 0U;
00597
00598   /* Check the parameters */
00599   assert_param(IS_FLASH_SECTOR(Sector));
00600   assert_param(IS_VOLTAGERANGE(VoltageRange));
00601
00602   if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
00603   {
00604      tmp_psize = FLASH_PSIZE_BYTE;
00605   }
00606   else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
00607   {
00608     tmp_psize = FLASH_PSIZE_HALF_WORD;
00609   }
00610   else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
00611   {
00612     tmp_psize = FLASH_PSIZE_WORD;
00613   }
00614   else
00615   {
00616     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
00617   }
00618
00619   /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
00620   if(Sector > FLASH_SECTOR_11)
00621   {
00622     Sector += 4U;
00623   }
00624   /* If the previous operation is completed, proceed to erase the sector */
00625   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
00626   FLASH->CR |= tmp_psize;
00627   CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
00628   FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
00629   FLASH->CR |= FLASH_CR_STRT;
00630 }
00631
00632 /**
00633   * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
00634   *
00635   * @note   When the memory read protection level is selected (RDP level = 1),
00636   *         it is not possible to program or erase the flash sector i if CortexM4
00637   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00638   * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
00639   *
00640   * @param  WRPSector: specifies the sector(s) to be write protected.
00641   *          This parameter can be one of the following values:
00642   *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
00643   *            @arg OB_WRP_SECTOR_All
00644   * @note   BANK2 starts from OB_WRP_SECTOR_12
00645   *
00646   * @param  Banks: Enable write protection on all the sectors for the specific bank
00647   *          This parameter can be one of the following values:
00648   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
00649   *            @arg FLASH_BANK_2: WRP on all sectors of bank2
00650   *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
00651   *
00652   * @retval HAL FLASH State
00653   */
00654 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
00655 {
00656   HAL_StatusTypeDef status = HAL_OK;
00657
00658   /* Check the parameters */
00659   assert_param(IS_OB_WRP_SECTOR(WRPSector));
00660   assert_param(IS_FLASH_BANK(Banks));
00661
00662   /* Wait for last operation to be completed */
00663   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00664
00665   if(status == HAL_OK)
00666   {
00667     if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
00668          (WRPSector < OB_WRP_SECTOR_12))
00669     {
00670        if(WRPSector == OB_WRP_SECTOR_All)
00671        {
00672           /*Write protection on all sector of BANK1*/
00673           *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12U));
00674        }
00675        else
00676        {
00677           /*Write protection done on sectors of BANK1*/
00678           *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
00679        }
00680     }
00681     else
00682     {
00683       /*Write protection done on sectors of BANK2*/
00684       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));
00685     }
00686
00687     /*Write protection on all sector of BANK2*/
00688     if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
00689     {
00690       /* Wait for last operation to be completed */
00691       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00692
00693       if(status == HAL_OK)
00694       {
00695         *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12U));
00696       }
00697     }
00698
00699   }
00700   return status;
00701 }
00702
00703 /**
00704   * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
00705   *
00706   * @note   When the memory read protection level is selected (RDP level = 1),
00707   *         it is not possible to program or erase the flash sector i if CortexM4
00708   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00709   * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
00710   *
00711   * @param  WRPSector: specifies the sector(s) to be write protected.
00712   *          This parameter can be one of the following values:
00713   *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
00714   *            @arg OB_WRP_Sector_All
00715   * @note   BANK2 starts from OB_WRP_SECTOR_12
00716   *
00717   * @param  Banks: Disable write protection on all the sectors for the specific bank
00718   *          This parameter can be one of the following values:
00719   *            @arg FLASH_BANK_1: Bank1 to be erased
00720   *            @arg FLASH_BANK_2: Bank2 to be erased
00721   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
00722   *
00723   * @retval HAL Status
00724   */
00725 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
00726 {
00727   HAL_StatusTypeDef status = HAL_OK;
00728
00729   /* Check the parameters */
00730   assert_param(IS_OB_WRP_SECTOR(WRPSector));
00731   assert_param(IS_FLASH_BANK(Banks));
00732
00733   /* Wait for last operation to be completed */
00734   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00735
00736   if(status == HAL_OK)
00737   {
00738     if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
00739          (WRPSector < OB_WRP_SECTOR_12))
00740     {
00741        if(WRPSector == OB_WRP_SECTOR_All)
00742        {
00743           /*Write protection on all sector of BANK1*/
00744           *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
00745        }
00746        else
00747        {
00748           /*Write protection done on sectors of BANK1*/
00749           *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
00750        }
00751     }
00752     else
00753     {
00754       /*Write protection done on sectors of BANK2*/
00755       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
00756     }
00757
00758     /*Write protection on all sector  of BANK2*/
00759     if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
00760     {
00761       /* Wait for last operation to be completed */
00762       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00763
00764       if(status == HAL_OK)
00765       {
00766         *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12U);
00767       }
00768     }
00769
00770   }
00771
00772   return status;
00773 }
00774
00775 /**
00776   * @brief  Configure the Dual Bank Boot.
00777   *
00778   * @note   This function can be used only for STM32F42xxx/43xxx devices.
00779   *
00780   * @param  BootConfig specifies the Dual Bank Boot Option byte.
00781   *          This parameter can be one of the following values:
00782   *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
00783   *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
00784   * @retval None
00785   */
00786 static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
00787 {
00788   HAL_StatusTypeDef status = HAL_OK;
00789
00790   /* Check the parameters */
00791   assert_param(IS_OB_BOOT(BootConfig));
00792
00793   /* Wait for last operation to be completed */
00794   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00795
00796   if(status == HAL_OK)
00797   {
00798     /* Set Dual Bank Boot */
00799     *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
00800     *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
00801   }
00802
00803   return status;
00804 }
00805
00806 /**
00807   * @brief  Enable the read/write protection (PCROP) of the desired
00808   *         sectors of Bank 1 and/or Bank 2.
00809   * @note   This function can be used only for STM32F42xxx/43xxx devices.
00810   * @param  SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
00811   *          This parameter can be one of the following values:
00812   *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
00813   *            @arg OB_PCROP_SECTOR__All
00814   * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
00815   *          This parameter can be one of the following values:
00816   *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
00817   *            @arg OB_PCROP_SECTOR__All
00818   * @param  Banks Enable PCROP protection on all the sectors for the specific bank
00819   *          This parameter can be one of the following values:
00820   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
00821   *            @arg FLASH_BANK_2: WRP on all sectors of bank2
00822   *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
00823   *
00824   * @retval HAL Status
00825   */
00826 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
00827 {
00828   HAL_StatusTypeDef status = HAL_OK;
00829
00830   assert_param(IS_FLASH_BANK(Banks));
00831
00832   /* Wait for last operation to be completed */
00833   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00834
00835   if(status == HAL_OK)
00836   {
00837     if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
00838     {
00839       assert_param(IS_OB_PCROP(SectorBank1));
00840       /*Write protection done on sectors of BANK1*/
00841       *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1;
00842     }
00843     else
00844     {
00845       assert_param(IS_OB_PCROP(SectorBank2));
00846       /*Write protection done on sectors of BANK2*/
00847       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
00848     }
00849
00850     /*Write protection on all sector  of BANK2*/
00851     if(Banks == FLASH_BANK_BOTH)
00852     {
00853       assert_param(IS_OB_PCROP(SectorBank2));
00854       /* Wait for last operation to be completed */
00855       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00856
00857       if(status == HAL_OK)
00858       {
00859         /*Write protection done on sectors of BANK2*/
00860         *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
00861       }
00862     }
00863
00864   }
00865
00866   return status;
00867 }
00868
00869
00870 /**
00871   * @brief  Disable the read/write protection (PCROP) of the desired
00872   *         sectors  of Bank 1 and/or Bank 2.
00873   * @note   This function can be used only for STM32F42xxx/43xxx devices.
00874   * @param  SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
00875   *          This parameter can be one of the following values:
00876   *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
00877   *            @arg OB_PCROP_SECTOR__All
00878   * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
00879   *          This parameter can be one of the following values:
00880   *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
00881   *            @arg OB_PCROP_SECTOR__All
00882   * @param  Banks Disable PCROP protection on all the sectors for the specific bank
00883   *          This parameter can be one of the following values:
00884   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
00885   *            @arg FLASH_BANK_2: WRP on all sectors of bank2
00886   *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
00887   *
00888   * @retval HAL Status
00889   */
00890 static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
00891 {
00892   HAL_StatusTypeDef status = HAL_OK;
00893
00894   /* Check the parameters */
00895   assert_param(IS_FLASH_BANK(Banks));
00896
00897   /* Wait for last operation to be completed */
00898   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00899
00900   if(status == HAL_OK)
00901   {
00902     if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
00903     {
00904       assert_param(IS_OB_PCROP(SectorBank1));
00905       /*Write protection done on sectors of BANK1*/
00906       *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1);
00907     }
00908     else
00909     {
00910       /*Write protection done on sectors of BANK2*/
00911       assert_param(IS_OB_PCROP(SectorBank2));
00912       *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
00913     }
00914
00915     /*Write protection on all sector  of BANK2*/
00916     if(Banks == FLASH_BANK_BOTH)
00917     {
00918       assert_param(IS_OB_PCROP(SectorBank2));
00919      /* Wait for last operation to be completed */
00920       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00921
00922       if(status == HAL_OK)
00923       {
00924         /*Write protection done on sectors of BANK2*/
00925         *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
00926       }
00927     }
00928
00929   }
00930
00931   return status;
00932
00933 }
00934
00935 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00936
00937 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00938     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00939     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00940 /**
00941   * @brief  Mass erase of FLASH memory
00942   * @param  VoltageRange: The device voltage range which defines the erase parallelism.
00943   *          This parameter can be one of the following values:
00944   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
00945   *                                  the operation will be done by byte (8-bit)
00946   *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
00947   *                                  the operation will be done by half word (16-bit)
00948   *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
00949   *                                  the operation will be done by word (32-bit)
00950   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
00951   *                                  the operation will be done by double word (64-bit)
00952   *
00953   * @param  Banks: Banks to be erased
00954   *          This parameter can be one of the following values:
00955   *            @arg FLASH_BANK_1: Bank1 to be erased
00956   *
00957   * @retval None
00958   */
00959 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
00960 {
00961   /* Check the parameters */
00962   assert_param(IS_VOLTAGERANGE(VoltageRange));
00963   assert_param(IS_FLASH_BANK(Banks));
00964
00965   /* If the previous operation is completed, proceed to erase all sectors */
00966   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
00967   FLASH->CR |= FLASH_CR_MER;
00968   FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
00969 }
00970
00971 /**
00972   * @brief  Erase the specified FLASH memory sector
00973   * @param  Sector: FLASH sector to erase
00974   *         The value of this parameter depend on device used within the same series
00975   * @param  VoltageRange: The device voltage range which defines the erase parallelism.
00976   *          This parameter can be one of the following values:
00977   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
00978   *                                  the operation will be done by byte (8-bit)
00979   *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
00980   *                                  the operation will be done by half word (16-bit)
00981   *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
00982   *                                  the operation will be done by word (32-bit)
00983   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
00984   *                                  the operation will be done by double word (64-bit)
00985   *
00986   * @retval None
00987   */
00988 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
00989 {
00990   uint32_t tmp_psize = 0U;
00991
00992   /* Check the parameters */
00993   assert_param(IS_FLASH_SECTOR(Sector));
00994   assert_param(IS_VOLTAGERANGE(VoltageRange));
00995
00996   if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
00997   {
00998      tmp_psize = FLASH_PSIZE_BYTE;
00999   }
01000   else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
01001   {
01002     tmp_psize = FLASH_PSIZE_HALF_WORD;
01003   }
01004   else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
01005   {
01006     tmp_psize = FLASH_PSIZE_WORD;
01007   }
01008   else
01009   {
01010     tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
01011   }
01012
01013   /* If the previous operation is completed, proceed to erase the sector */
01014   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
01015   FLASH->CR |= tmp_psize;
01016   CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
01017   FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
01018   FLASH->CR |= FLASH_CR_STRT;
01019 }
01020
01021 /**
01022   * @brief  Enable the write protection of the desired bank 1 sectors
01023   *
01024   * @note   When the memory read protection level is selected (RDP level = 1),
01025   *         it is not possible to program or erase the flash sector i if CortexM4
01026   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
01027   * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
01028   *
01029   * @param  WRPSector: specifies the sector(s) to be write protected.
01030   *         The value of this parameter depend on device used within the same series
01031   *
01032   * @param  Banks: Enable write protection on all the sectors for the specific bank
01033   *          This parameter can be one of the following values:
01034   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
01035   *
01036   * @retval HAL Status
01037   */
01038 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
01039 {
01040   HAL_StatusTypeDef status = HAL_OK;
01041
01042   /* Check the parameters */
01043   assert_param(IS_OB_WRP_SECTOR(WRPSector));
01044   assert_param(IS_FLASH_BANK(Banks));
01045
01046   /* Wait for last operation to be completed */
01047   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01048
01049   if(status == HAL_OK)
01050   {
01051     *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
01052   }
01053
01054   return status;
01055 }
01056
01057 /**
01058   * @brief  Disable the write protection of the desired bank 1 sectors
01059   *
01060   * @note   When the memory read protection level is selected (RDP level = 1),
01061   *         it is not possible to program or erase the flash sector i if CortexM4
01062   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
01063   * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
01064   *
01065   * @param  WRPSector: specifies the sector(s) to be write protected.
01066   *         The value of this parameter depend on device used within the same series
01067   *
01068   * @param  Banks: Enable write protection on all the sectors for the specific bank
01069   *          This parameter can be one of the following values:
01070   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
01071   *
01072   * @retval HAL Status
01073   */
01074 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
01075 {
01076   HAL_StatusTypeDef status = HAL_OK;
01077
01078   /* Check the parameters */
01079   assert_param(IS_OB_WRP_SECTOR(WRPSector));
01080   assert_param(IS_FLASH_BANK(Banks));
01081
01082   /* Wait for last operation to be completed */
01083   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01084
01085   if(status == HAL_OK)
01086   {
01087     *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
01088   }
01089
01090   return status;
01091 }
01092 #endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
01093
01094 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
01095     defined(STM32F411xE) || defined(STM32F446xx)
01096 /**
01097   * @brief  Enable the read/write protection (PCROP) of the desired sectors.
01098   * @note   This function can be used only for STM32F401xx devices.
01099   * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
01100   *          This parameter can be one of the following values:
01101   *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
01102   *            @arg OB_PCROP_Sector_All
01103   * @retval HAL Status
01104   */
01105 static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
01106 {
01107   HAL_StatusTypeDef status = HAL_OK;
01108
01109   /* Check the parameters */
01110   assert_param(IS_OB_PCROP(Sector));
01111
01112   /* Wait for last operation to be completed */
01113   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01114
01115   if(status == HAL_OK)
01116   {
01117     *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
01118   }
01119
01120   return status;
01121 }
01122
01123
01124 /**
01125   * @brief  Disable the read/write protection (PCROP) of the desired sectors.
01126   * @note   This function can be used only for STM32F401xx devices.
01127   * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
01128   *          This parameter can be one of the following values:
01129   *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
01130   *            @arg OB_PCROP_Sector_All
01131   * @retval HAL Status
01132   */
01133 static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
01134 {
01135   HAL_StatusTypeDef status = HAL_OK;
01136
01137   /* Check the parameters */
01138   assert_param(IS_OB_PCROP(Sector));
01139
01140   /* Wait for last operation to be completed */
01141   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01142
01143   if(status == HAL_OK)
01144   {
01145     *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector);
01146   }
01147
01148   return status;
01149
01150 }
01151 #endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
01152
01153 /**
01154   * @brief  Set the read protection level.
01155   * @param  Level: specifies the read protection level.
01156   *          This parameter can be one of the following values:
01157   *            @arg OB_RDP_LEVEL_0: No protection
01158   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
01159   *            @arg OB_RDP_LEVEL_2: Full chip protection
01160   *
01161   * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
01162   *
01163   * @retval HAL Status
01164   */
01165 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
01166 {
01167   HAL_StatusTypeDef status = HAL_OK;
01168
01169   /* Check the parameters */
01170   assert_param(IS_OB_RDP_LEVEL(Level));
01171
01172   /* Wait for last operation to be completed */
01173   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01174
01175   if(status == HAL_OK)
01176   {
01177     *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
01178   }
01179
01180   return status;
01181 }
01182
01183 /**
01184   * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
01185   * @param  Iwdg: Selects the IWDG mode
01186   *          This parameter can be one of the following values:
01187   *            @arg OB_IWDG_SW: Software IWDG selected
01188   *            @arg OB_IWDG_HW: Hardware IWDG selected
01189   * @param  Stop: Reset event when entering STOP mode.
01190   *          This parameter  can be one of the following values:
01191   *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
01192   *            @arg OB_STOP_RST: Reset generated when entering in STOP
01193   * @param  Stdby: Reset event when entering Standby mode.
01194   *          This parameter  can be one of the following values:
01195   *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
01196   *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
01197   * @retval HAL Status
01198   */
01199 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
01200 {
01201   uint8_t optiontmp = 0xFFU;
01202   HAL_StatusTypeDef status = HAL_OK;
01203
01204   /* Check the parameters */
01205   assert_param(IS_OB_IWDG_SOURCE(Iwdg));
01206   assert_param(IS_OB_STOP_SOURCE(Stop));
01207   assert_param(IS_OB_STDBY_SOURCE(Stdby));
01208
01209   /* Wait for last operation to be completed */
01210   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01211
01212   if(status == HAL_OK)
01213   {
01214     /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
01215     optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1FU);
01216
01217     /* Update User Option Byte */
01218     *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
01219   }
01220
01221   return status;
01222 }
01223
01224 /**
01225   * @brief  Set the BOR Level.
01226   * @param  Level: specifies the Option Bytes BOR Reset Level.
01227   *          This parameter can be one of the following values:
01228   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
01229   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
01230   *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
01231   *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
01232   * @retval HAL Status
01233   */
01234 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
01235 {
01236   /* Check the parameters */
01237   assert_param(IS_OB_BOR_LEVEL(Level));
01238
01239   /* Set the BOR Level */
01240   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
01241   *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
01242
01243   return HAL_OK;
01244
01245 }
01246
01247 /**
01248   * @brief  Return the FLASH User Option Byte value.
01249   * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
01250   *         and RST_STDBY(Bit2).
01251   */
01252 static uint8_t FLASH_OB_GetUser(void)
01253 {
01254   /* Return the User Option Byte */
01255   return ((uint8_t)(FLASH->OPTCR & 0xE0U));
01256 }
01257
01258 /**
01259   * @brief  Return the FLASH Write Protection Option Bytes value.
01260   * @retval uint16_t FLASH Write Protection Option Bytes value
01261   */
01262 static uint16_t FLASH_OB_GetWRP(void)
01263 {
01264   /* Return the FLASH write protection Register value */
01265   return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
01266 }
01267
01268 /**
01269   * @brief  Returns the FLASH Read Protection level.
01270   * @retval FLASH ReadOut Protection Status:
01271   *         This parameter can be one of the following values:
01272   *            @arg OB_RDP_LEVEL_0: No protection
01273   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
01274   *            @arg OB_RDP_LEVEL_2: Full chip protection
01275   */
01276 static uint8_t FLASH_OB_GetRDP(void)
01277 {
01278   uint8_t readstatus = OB_RDP_LEVEL_0;
01279
01280   if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))
01281   {
01282     readstatus = OB_RDP_LEVEL_2;
01283   }
01284   else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
01285   {
01286     readstatus = OB_RDP_LEVEL_1;
01287   }
01288   else
01289   {
01290     readstatus = OB_RDP_LEVEL_0;
01291   }
01292
01293   return readstatus;
01294 }
01295
01296 /**
01297   * @brief  Returns the FLASH BOR level.
01298   * @retval uint8_t The FLASH BOR level:
01299   *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
01300   *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
01301   *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
01302   *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V
01303   */
01304 static uint8_t FLASH_OB_GetBOR(void)
01305 {
01306   /* Return the FLASH BOR level */
01307   return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0CU);
01308 }
01309
01310 /**
01311   * @brief  Flush the instruction and data caches
01312   * @retval None
01313   */
01314 void FLASH_FlushCaches(void)
01315 {
01316   /* Flush instruction cache  */
01317   if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET)
01318   {
01319     /* Disable instruction cache  */
01320     __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
01321     /* Reset instruction cache */
01322     __HAL_FLASH_INSTRUCTION_CACHE_RESET();
01323     /* Enable instruction cache */
01324     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
01325   }
01326
01327   /* Flush data cache */
01328   if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
01329   {
01330     /* Disable data cache  */
01331     __HAL_FLASH_DATA_CACHE_DISABLE();
01332     /* Reset data cache */
01333     __HAL_FLASH_DATA_CACHE_RESET();
01334     /* Enable data cache */
01335     __HAL_FLASH_DATA_CACHE_ENABLE();
01336   }
01337 }
01338
01339 /**
01340   * @}
01341   */
01342
01343 #endif /* HAL_FLASH_MODULE_ENABLED */
01344
01345 /**
01346   * @}
01347   */
01348
01349 /**
01350   * @}
01351   */
01352
01353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ex.h Source File

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stm32f4xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of FLASH HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_FLASH_EX_H
00040 #define __STM32F4xx_HAL_FLASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASHEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  FLASH Erase structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t TypeErase;   /*!< Mass erase or sector Erase.
00068                              This parameter can be a value of @ref FLASHEx_Type_Erase */
00069
00070   uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
00071                              This parameter must be a value of @ref FLASHEx_Banks */
00072
00073   uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
00074                              This parameter must be a value of @ref FLASHEx_Sectors */
00075
00076   uint32_t NbSectors;   /*!< Number of sectors to be erased.
00077                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
00078
00079   uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
00080                              This parameter must be a value of @ref FLASHEx_Voltage_Range */
00081
00082 } FLASH_EraseInitTypeDef;
00083
00084 /**
00085   * @brief  FLASH Option Bytes Program structure definition
00086   */
00087 typedef struct
00088 {
00089   uint32_t OptionType;   /*!< Option byte to be configured.
00090                               This parameter can be a value of @ref FLASHEx_Option_Type */
00091
00092   uint32_t WRPState;     /*!< Write protection activation or deactivation.
00093                               This parameter can be a value of @ref FLASHEx_WRP_State */
00094
00095   uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.
00096                               The value of this parameter depend on device used within the same series */
00097
00098   uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
00099                               This parameter must be a value of @ref FLASHEx_Banks */
00100
00101   uint32_t RDPLevel;     /*!< Set the read protection level.
00102                               This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
00103
00104   uint32_t BORLevel;     /*!< Set the BOR Level.
00105                               This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
00106
00107   uint8_t  USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
00108
00109 } FLASH_OBProgramInitTypeDef;
00110
00111 /**
00112   * @brief  FLASH Advanced Option Bytes Program structure definition
00113   */
00114 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00115     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00116     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00117     defined(STM32F479xx)
00118 typedef struct
00119 {
00120   uint32_t OptionType;     /*!< Option byte to be configured for extension.
00121                                 This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
00122
00123   uint32_t PCROPState;     /*!< PCROP activation or deactivation.
00124                                 This parameter can be a value of @ref FLASHEx_PCROP_State */
00125
00126 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00127   uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.
00128                                 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
00129 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00130
00131 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00132   uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.
00133                                 This parameter must be a value of @ref FLASHEx_Banks */
00134
00135   uint16_t SectorsBank1;   /*!< Specifies the sector(s) set for PCROP for Bank1.
00136                                 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
00137
00138   uint16_t SectorsBank2;   /*!< Specifies the sector(s) set for PCROP for Bank2.
00139                                 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
00140
00141   uint8_t BootConfig;      /*!< Specifies Option bytes for boot config.
00142                                 This parameter can be a value of @ref FLASHEx_Dual_Boot */
00143
00144 #endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00145 }FLASH_AdvOBProgramInitTypeDef;
00146 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported constants --------------------------------------------------------*/
00152
00153 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
00154   * @{
00155   */
00156
00157 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
00158   * @{
00159   */
00160 #define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00U)  /*!< Sectors erase only          */
00161 #define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01U)  /*!< Flash Mass erase activation */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
00167   * @{
00168   */
00169 #define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00U)  /*!< Device operating range: 1.8V to 2.1V                */
00170 #define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01U)  /*!< Device operating range: 2.1V to 2.7V                */
00171 #define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02U)  /*!< Device operating range: 2.7V to 3.6V                */
00172 #define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03U)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup FLASHEx_WRP_State FLASH WRP State
00178   * @{
00179   */
00180 #define OB_WRPSTATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable the write protection of the desired bank 1 sectors */
00181 #define OB_WRPSTATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable the write protection of the desired bank 1 sectors  */
00182 /**
00183   * @}
00184   */
00185
00186 /** @defgroup FLASHEx_Option_Type FLASH Option Type
00187   * @{
00188   */
00189 #define OPTIONBYTE_WRP        ((uint32_t)0x01U)  /*!< WRP option byte configuration  */
00190 #define OPTIONBYTE_RDP        ((uint32_t)0x02U)  /*!< RDP option byte configuration  */
00191 #define OPTIONBYTE_USER       ((uint32_t)0x04U)  /*!< USER option byte configuration */
00192 #define OPTIONBYTE_BOR        ((uint32_t)0x08U)  /*!< BOR option byte configuration  */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
00198   * @{
00199   */
00200 #define OB_RDP_LEVEL_0   ((uint8_t)0xAAU)
00201 #define OB_RDP_LEVEL_1   ((uint8_t)0x55U)
00202 #define OB_RDP_LEVEL_2   ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
00203                                               it s no more possible to go back to level 1 or 0 */
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
00209   * @{
00210   */
00211 #define OB_IWDG_SW                     ((uint8_t)0x20U)  /*!< Software IWDG selected */
00212 #define OB_IWDG_HW                     ((uint8_t)0x00U)  /*!< Hardware IWDG selected */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
00218   * @{
00219   */
00220 #define OB_STOP_NO_RST                 ((uint8_t)0x40U) /*!< No reset generated when entering in STOP */
00221 #define OB_STOP_RST                    ((uint8_t)0x00U) /*!< Reset generated when entering in STOP    */
00222 /**
00223   * @}
00224   */
00225
00226
00227 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
00228   * @{
00229   */
00230 #define OB_STDBY_NO_RST                ((uint8_t)0x80U) /*!< No reset generated when entering in STANDBY */
00231 #define OB_STDBY_RST                   ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY    */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
00237   * @{
00238   */
00239 #define OB_BOR_LEVEL3          ((uint8_t)0x00U)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
00240 #define OB_BOR_LEVEL2          ((uint8_t)0x04U)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
00241 #define OB_BOR_LEVEL1          ((uint8_t)0x08U)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
00242 #define OB_BOR_OFF             ((uint8_t)0x0CU)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
00243 /**
00244   * @}
00245   */
00246
00247 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00248     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00249     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00250     defined(STM32F479xx)
00251 /** @defgroup FLASHEx_PCROP_State FLASH PCROP State
00252   * @{
00253   */
00254 #define OB_PCROP_STATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable PCROP */
00255 #define OB_PCROP_STATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable PCROP  */
00256 /**
00257   * @}
00258   */
00259 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
00260           STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00261
00262 /** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
00263   * @{
00264   */
00265 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00266     defined(STM32F469xx) || defined(STM32F479xx)
00267 #define OPTIONBYTE_PCROP        ((uint32_t)0x01U)  /*!< PCROP option byte configuration      */
00268 #define OPTIONBYTE_BOOTCONFIG   ((uint32_t)0x02U)  /*!< BOOTConfig option byte configuration */
00269 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00270
00271 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00272     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00273 #define OPTIONBYTE_PCROP        ((uint32_t)0x01U)  /*!<PCROP option byte configuration */
00274 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup FLASH_Latency FLASH Latency
00280   * @{
00281   */
00282 /*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/
00283 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00284     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00285 #define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
00286 #define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
00287 #define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
00288 #define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
00289 #define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
00290 #define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
00291 #define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
00292 #define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
00293 #define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
00294 #define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
00295 #define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
00296 #define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
00297 #define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
00298 #define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
00299 #define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
00300 #define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
00301 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00302 /*--------------------------------------------------------------------------------------------------------------*/
00303
00304 /*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx -----------------------------------*/
00305 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00306     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00307     defined(STM32F410Rx) || defined(STM32F411xE)
00308
00309 #define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
00310 #define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
00311 #define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
00312 #define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
00313 #define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
00314 #define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
00315 #define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
00316 #define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
00317 #endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE */
00318 /*--------------------------------------------------------------------------------------------------------------*/
00319
00320 /**
00321   * @}
00322   */
00323
00324
00325 /** @defgroup FLASHEx_Banks FLASH Banks
00326   * @{
00327   */
00328 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00329     defined(STM32F469xx) || defined(STM32F479xx)
00330 #define FLASH_BANK_1     ((uint32_t)1U) /*!< Bank 1   */
00331 #define FLASH_BANK_2     ((uint32_t)2U) /*!< Bank 2   */
00332 #define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
00333 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00334
00335 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00336     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00337     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00338 #define FLASH_BANK_1     ((uint32_t)1U) /*!< Bank 1   */
00339 #endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
00345   * @{
00346   */
00347 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00348     defined(STM32F469xx) || defined(STM32F479xx)
00349 #define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
00350 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00351
00352 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00353     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00354     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00355 #define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
00356 #endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup FLASHEx_Sectors FLASH Sectors
00362   * @{
00363   */
00364 /*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/
00365 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00366     defined(STM32F469xx) || defined(STM32F479xx)
00367 #define FLASH_SECTOR_0     ((uint32_t)0U)  /*!< Sector Number 0   */
00368 #define FLASH_SECTOR_1     ((uint32_t)1U)  /*!< Sector Number 1   */
00369 #define FLASH_SECTOR_2     ((uint32_t)2U)  /*!< Sector Number 2   */
00370 #define FLASH_SECTOR_3     ((uint32_t)3U)  /*!< Sector Number 3   */
00371 #define FLASH_SECTOR_4     ((uint32_t)4U)  /*!< Sector Number 4   */
00372 #define FLASH_SECTOR_5     ((uint32_t)5U)  /*!< Sector Number 5   */
00373 #define FLASH_SECTOR_6     ((uint32_t)6U)  /*!< Sector Number 6   */
00374 #define FLASH_SECTOR_7     ((uint32_t)7U)  /*!< Sector Number 7   */
00375 #define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */
00376 #define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */
00377 #define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */
00378 #define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */
00379 #define FLASH_SECTOR_12    ((uint32_t)12U) /*!< Sector Number 12  */
00380 #define FLASH_SECTOR_13    ((uint32_t)13U) /*!< Sector Number 13  */
00381 #define FLASH_SECTOR_14    ((uint32_t)14U) /*!< Sector Number 14  */
00382 #define FLASH_SECTOR_15    ((uint32_t)15U) /*!< Sector Number 15  */
00383 #define FLASH_SECTOR_16    ((uint32_t)16U) /*!< Sector Number 16  */
00384 #define FLASH_SECTOR_17    ((uint32_t)17U) /*!< Sector Number 17  */
00385 #define FLASH_SECTOR_18    ((uint32_t)18U) /*!< Sector Number 18  */
00386 #define FLASH_SECTOR_19    ((uint32_t)19U) /*!< Sector Number 19  */
00387 #define FLASH_SECTOR_20    ((uint32_t)20U) /*!< Sector Number 20  */
00388 #define FLASH_SECTOR_21    ((uint32_t)21U) /*!< Sector Number 21  */
00389 #define FLASH_SECTOR_22    ((uint32_t)22U) /*!< Sector Number 22  */
00390 #define FLASH_SECTOR_23    ((uint32_t)23U) /*!< Sector Number 23  */
00391 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00392 /*-----------------------------------------------------------------------------------------------------*/
00393
00394 /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
00395 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00396 #define FLASH_SECTOR_0     ((uint32_t)0U)  /*!< Sector Number 0   */
00397 #define FLASH_SECTOR_1     ((uint32_t)1U)  /*!< Sector Number 1   */
00398 #define FLASH_SECTOR_2     ((uint32_t)2U)  /*!< Sector Number 2   */
00399 #define FLASH_SECTOR_3     ((uint32_t)3U)  /*!< Sector Number 3   */
00400 #define FLASH_SECTOR_4     ((uint32_t)4U)  /*!< Sector Number 4   */
00401 #define FLASH_SECTOR_5     ((uint32_t)5U)  /*!< Sector Number 5   */
00402 #define FLASH_SECTOR_6     ((uint32_t)6U)  /*!< Sector Number 6   */
00403 #define FLASH_SECTOR_7     ((uint32_t)7U)  /*!< Sector Number 7   */
00404 #define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */
00405 #define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */
00406 #define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */
00407 #define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */
00408 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00409 /*-----------------------------------------------------------------------------------------------------*/
00410
00411 /*--------------------------------------------- STM32F401xC -------------------------------------------*/
00412 #if defined(STM32F401xC)
00413 #define FLASH_SECTOR_0     ((uint32_t)0U) /*!< Sector Number 0   */
00414 #define FLASH_SECTOR_1     ((uint32_t)1U) /*!< Sector Number 1   */
00415 #define FLASH_SECTOR_2     ((uint32_t)2U) /*!< Sector Number 2   */
00416 #define FLASH_SECTOR_3     ((uint32_t)3U) /*!< Sector Number 3   */
00417 #define FLASH_SECTOR_4     ((uint32_t)4U) /*!< Sector Number 4   */
00418 #define FLASH_SECTOR_5     ((uint32_t)5U) /*!< Sector Number 5   */
00419 #endif /* STM32F401xC */
00420 /*-----------------------------------------------------------------------------------------------------*/
00421
00422 /*--------------------------------------------- STM32F410xx -------------------------------------------*/
00423 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00424 #define FLASH_SECTOR_0     ((uint32_t)0U) /*!< Sector Number 0   */
00425 #define FLASH_SECTOR_1     ((uint32_t)1U) /*!< Sector Number 1   */
00426 #define FLASH_SECTOR_2     ((uint32_t)2U) /*!< Sector Number 2   */
00427 #define FLASH_SECTOR_3     ((uint32_t)3U) /*!< Sector Number 3   */
00428 #define FLASH_SECTOR_4     ((uint32_t)4U) /*!< Sector Number 4   */
00429 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00430 /*-----------------------------------------------------------------------------------------------------*/
00431
00432 /*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
00433 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
00434 #define FLASH_SECTOR_0     ((uint32_t)0U) /*!< Sector Number 0   */
00435 #define FLASH_SECTOR_1     ((uint32_t)1U) /*!< Sector Number 1   */
00436 #define FLASH_SECTOR_2     ((uint32_t)2U) /*!< Sector Number 2   */
00437 #define FLASH_SECTOR_3     ((uint32_t)3U) /*!< Sector Number 3   */
00438 #define FLASH_SECTOR_4     ((uint32_t)4U) /*!< Sector Number 4   */
00439 #define FLASH_SECTOR_5     ((uint32_t)5U) /*!< Sector Number 5   */
00440 #define FLASH_SECTOR_6     ((uint32_t)6U) /*!< Sector Number 6   */
00441 #define FLASH_SECTOR_7     ((uint32_t)7U) /*!< Sector Number 7   */
00442 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
00443 /*-----------------------------------------------------------------------------------------------------*/
00444
00445 /**
00446   * @}
00447   */
00448
00449 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
00450   * @{
00451   */
00452 /*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/
00453 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00454     defined(STM32F469xx) || defined(STM32F479xx)
00455 #define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
00456 #define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
00457 #define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
00458 #define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
00459 #define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
00460 #define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
00461 #define OB_WRP_SECTOR_6       ((uint32_t)0x00000040U) /*!< Write protection of Sector6     */
00462 #define OB_WRP_SECTOR_7       ((uint32_t)0x00000080U) /*!< Write protection of Sector7     */
00463 #define OB_WRP_SECTOR_8       ((uint32_t)0x00000100U) /*!< Write protection of Sector8     */
00464 #define OB_WRP_SECTOR_9       ((uint32_t)0x00000200U) /*!< Write protection of Sector9     */
00465 #define OB_WRP_SECTOR_10      ((uint32_t)0x00000400U) /*!< Write protection of Sector10    */
00466 #define OB_WRP_SECTOR_11      ((uint32_t)0x00000800U) /*!< Write protection of Sector11    */
00467 #define OB_WRP_SECTOR_12      ((uint32_t)0x00000001U << 12) /*!< Write protection of Sector12    */
00468 #define OB_WRP_SECTOR_13      ((uint32_t)0x00000002U << 12) /*!< Write protection of Sector13    */
00469 #define OB_WRP_SECTOR_14      ((uint32_t)0x00000004U << 12) /*!< Write protection of Sector14    */
00470 #define OB_WRP_SECTOR_15      ((uint32_t)0x00000008U << 12) /*!< Write protection of Sector15    */
00471 #define OB_WRP_SECTOR_16      ((uint32_t)0x00000010U << 12) /*!< Write protection of Sector16    */
00472 #define OB_WRP_SECTOR_17      ((uint32_t)0x00000020U << 12) /*!< Write protection of Sector17    */
00473 #define OB_WRP_SECTOR_18      ((uint32_t)0x00000040U << 12) /*!< Write protection of Sector18    */
00474 #define OB_WRP_SECTOR_19      ((uint32_t)0x00000080U << 12) /*!< Write protection of Sector19    */
00475 #define OB_WRP_SECTOR_20      ((uint32_t)0x00000100U << 12) /*!< Write protection of Sector20    */
00476 #define OB_WRP_SECTOR_21      ((uint32_t)0x00000200U << 12) /*!< Write protection of Sector21    */
00477 #define OB_WRP_SECTOR_22      ((uint32_t)0x00000400U << 12) /*!< Write protection of Sector22    */
00478 #define OB_WRP_SECTOR_23      ((uint32_t)0x00000800U << 12) /*!< Write protection of Sector23    */
00479 #define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU << 12) /*!< Write protection of all Sectors */
00480 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00481 /*-----------------------------------------------------------------------------------------------------*/
00482
00483 /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
00484 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00485 #define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
00486 #define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
00487 #define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
00488 #define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
00489 #define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
00490 #define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
00491 #define OB_WRP_SECTOR_6       ((uint32_t)0x00000040U) /*!< Write protection of Sector6     */
00492 #define OB_WRP_SECTOR_7       ((uint32_t)0x00000080U) /*!< Write protection of Sector7     */
00493 #define OB_WRP_SECTOR_8       ((uint32_t)0x00000100U) /*!< Write protection of Sector8     */
00494 #define OB_WRP_SECTOR_9       ((uint32_t)0x00000200U) /*!< Write protection of Sector9     */
00495 #define OB_WRP_SECTOR_10      ((uint32_t)0x00000400U) /*!< Write protection of Sector10    */
00496 #define OB_WRP_SECTOR_11      ((uint32_t)0x00000800U) /*!< Write protection of Sector11    */
00497 #define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
00498 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00499 /*-----------------------------------------------------------------------------------------------------*/
00500
00501 /*--------------------------------------------- STM32F401xC -------------------------------------------*/
00502 #if defined(STM32F401xC)
00503 #define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
00504 #define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
00505 #define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
00506 #define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
00507 #define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
00508 #define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
00509 #define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
00510 #endif /* STM32F401xC */
00511 /*-----------------------------------------------------------------------------------------------------*/
00512
00513 /*--------------------------------------------- STM32F410xx -------------------------------------------*/
00514 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00515 #define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
00516 #define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
00517 #define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
00518 #define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
00519 #define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
00520 #define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
00521 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00522 /*-----------------------------------------------------------------------------------------------------*/
00523
00524 /*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
00525 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
00526 #define OB_WRP_SECTOR_0       ((uint32_t)0x00000001U) /*!< Write protection of Sector0     */
00527 #define OB_WRP_SECTOR_1       ((uint32_t)0x00000002U) /*!< Write protection of Sector1     */
00528 #define OB_WRP_SECTOR_2       ((uint32_t)0x00000004U) /*!< Write protection of Sector2     */
00529 #define OB_WRP_SECTOR_3       ((uint32_t)0x00000008U) /*!< Write protection of Sector3     */
00530 #define OB_WRP_SECTOR_4       ((uint32_t)0x00000010U) /*!< Write protection of Sector4     */
00531 #define OB_WRP_SECTOR_5       ((uint32_t)0x00000020U) /*!< Write protection of Sector5     */
00532 #define OB_WRP_SECTOR_6       ((uint32_t)0x00000040U) /*!< Write protection of Sector6     */
00533 #define OB_WRP_SECTOR_7       ((uint32_t)0x00000080U) /*!< Write protection of Sector7     */
00534 #define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFFU) /*!< Write protection of all Sectors */
00535 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
00536 /*-----------------------------------------------------------------------------------------------------*/
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
00542   * @{
00543   */
00544 /*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/
00545 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00546     defined(STM32F469xx) || defined(STM32F479xx)
00547 #define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
00548 #define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
00549 #define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
00550 #define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
00551 #define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
00552 #define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector5      */
00553 #define OB_PCROP_SECTOR_6        ((uint32_t)0x00000040U) /*!< PC Read/Write protection of Sector6      */
00554 #define OB_PCROP_SECTOR_7        ((uint32_t)0x00000080U) /*!< PC Read/Write protection of Sector7      */
00555 #define OB_PCROP_SECTOR_8        ((uint32_t)0x00000100U) /*!< PC Read/Write protection of Sector8      */
00556 #define OB_PCROP_SECTOR_9        ((uint32_t)0x00000200U) /*!< PC Read/Write protection of Sector9      */
00557 #define OB_PCROP_SECTOR_10       ((uint32_t)0x00000400U) /*!< PC Read/Write protection of Sector10     */
00558 #define OB_PCROP_SECTOR_11       ((uint32_t)0x00000800U) /*!< PC Read/Write protection of Sector11     */
00559 #define OB_PCROP_SECTOR_12       ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector12     */
00560 #define OB_PCROP_SECTOR_13       ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector13     */
00561 #define OB_PCROP_SECTOR_14       ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector14     */
00562 #define OB_PCROP_SECTOR_15       ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector15     */
00563 #define OB_PCROP_SECTOR_16       ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector16     */
00564 #define OB_PCROP_SECTOR_17       ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector17     */
00565 #define OB_PCROP_SECTOR_18       ((uint32_t)0x00000040U) /*!< PC Read/Write protection of Sector18     */
00566 #define OB_PCROP_SECTOR_19       ((uint32_t)0x00000080U) /*!< PC Read/Write protection of Sector19     */
00567 #define OB_PCROP_SECTOR_20       ((uint32_t)0x00000100U) /*!< PC Read/Write protection of Sector20     */
00568 #define OB_PCROP_SECTOR_21       ((uint32_t)0x00000200U) /*!< PC Read/Write protection of Sector21     */
00569 #define OB_PCROP_SECTOR_22       ((uint32_t)0x00000400U) /*!< PC Read/Write protection of Sector22     */
00570 #define OB_PCROP_SECTOR_23       ((uint32_t)0x00000800U) /*!< PC Read/Write protection of Sector23     */
00571 #define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
00572 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00573 /*-----------------------------------------------------------------------------------------------------*/
00574
00575 /*--------------------------------------------- STM32F401xC -------------------------------------------*/
00576 #if defined(STM32F401xC)
00577 #define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
00578 #define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
00579 #define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
00580 #define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
00581 #define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
00582 #define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector5      */
00583 #define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
00584 #endif /* STM32F401xC */
00585 /*-----------------------------------------------------------------------------------------------------*/
00586
00587 /*--------------------------------------------- STM32F410xx -------------------------------------------*/
00588 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00589 #define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
00590 #define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
00591 #define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
00592 #define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
00593 #define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
00594 #define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
00595 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00596 /*-----------------------------------------------------------------------------------------------------*/
00597
00598 /*------------------ STM32F401xE/STM32F411xE/STM32F446xx ----------------------------------------------*/
00599 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
00600 #define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001U) /*!< PC Read/Write protection of Sector0      */
00601 #define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002U) /*!< PC Read/Write protection of Sector1      */
00602 #define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004U) /*!< PC Read/Write protection of Sector2      */
00603 #define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008U) /*!< PC Read/Write protection of Sector3      */
00604 #define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010U) /*!< PC Read/Write protection of Sector4      */
00605 #define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020U) /*!< PC Read/Write protection of Sector5      */
00606 #define OB_PCROP_SECTOR_6        ((uint32_t)0x00000040U) /*!< PC Read/Write protection of Sector6      */
00607 #define OB_PCROP_SECTOR_7        ((uint32_t)0x00000080U) /*!< PC Read/Write protection of Sector7      */
00608 #define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFFU) /*!< PC Read/Write protection of all Sectors  */
00609 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
00610 /*-----------------------------------------------------------------------------------------------------*/
00611
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
00617   * @{
00618   */
00619 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00620     defined(STM32F469xx) || defined(STM32F479xx)
00621 #define OB_DUAL_BOOT_ENABLE   ((uint8_t)0x10U) /*!< Dual Bank Boot Enable                             */
00622 #define OB_DUAL_BOOT_DISABLE  ((uint8_t)0x00U) /*!< Dual Bank Boot Disable, always boot on User Flash */
00623 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup  FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
00629   * @{
00630   */
00631 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00632     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00633     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00634     defined(STM32F479xx)
00635 #define OB_PCROP_DESELECTED     ((uint8_t)0x00U) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
00636 #define OB_PCROP_SELECTED       ((uint8_t)0x80U) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
00637 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
00638           STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00639 /**
00640   * @}
00641   */
00642
00643 /**
00644   * @}
00645   */
00646
00647 /* Exported macro ------------------------------------------------------------*/
00648
00649 /* Exported functions --------------------------------------------------------*/
00650 /** @addtogroup FLASHEx_Exported_Functions
00651   * @{
00652   */
00653
00654 /** @addtogroup FLASHEx_Exported_Functions_Group1
00655   * @{
00656   */
00657 /* Extension Program operation functions  *************************************/
00658 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
00659 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00660 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00661 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00662
00663 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00664     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00665     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00666     defined(STM32F479xx)
00667 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
00668 void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
00669 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
00670 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
00671 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
00672           STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00673
00674 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00675     defined(STM32F469xx) || defined(STM32F479xx)
00676 uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
00677 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00678 /**
00679   * @}
00680   */
00681
00682 /**
00683   * @}
00684   */
00685 /* Private types -------------------------------------------------------------*/
00686 /* Private variables ---------------------------------------------------------*/
00687 /* Private constants ---------------------------------------------------------*/
00688 /** @defgroup FLASHEx_Private_Constants FLASH Private Constants
00689   * @{
00690   */
00691 /*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/
00692 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00693 #define FLASH_SECTOR_TOTAL  24U
00694 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00695
00696 /*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/
00697 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00698 #define FLASH_SECTOR_TOTAL  12U
00699 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00700
00701 /*--------------------------------------------- STM32F401xC -------------------------------------------*/
00702 #if defined(STM32F401xC)
00703 #define FLASH_SECTOR_TOTAL  6U
00704 #endif /* STM32F401xC */
00705
00706 /*--------------------------------------------- STM32F410xx -------------------------------------------*/
00707 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00708 #define FLASH_SECTOR_TOTAL  5U
00709 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00710
00711 /*-------------------------------------- STM32F401xE/STM32F411xE/STM32F446xx --------------------------*/
00712 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
00713 #define FLASH_SECTOR_TOTAL  8U
00714 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
00715
00716 /**
00717   * @brief OPTCR1 register byte 2 (Bits[23:16]) base address
00718   */
00719 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00720 #define OPTCR1_BYTE2_ADDRESS         ((uint32_t)0x40023C1AU)
00721 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00722
00723 /**
00724   * @}
00725   */
00726
00727 /* Private macros ------------------------------------------------------------*/
00728 /** @defgroup FLASHEx_Private_Macros FLASH Private Macros
00729   * @{
00730   */
00731
00732 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
00733   * @{
00734   */
00735
00736 #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
00737                                   ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00738
00739 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
00740                                ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
00741                                ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
00742                                ((RANGE) == FLASH_VOLTAGE_RANGE_4))
00743
00744 #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
00745                            ((VALUE) == OB_WRPSTATE_ENABLE))
00746
00747 #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
00748
00749 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
00750                                 ((LEVEL) == OB_RDP_LEVEL_1) ||\
00751                                 ((LEVEL) == OB_RDP_LEVEL_2))
00752
00753 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00754
00755 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
00756
00757 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
00758
00759 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
00760                                 ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
00761
00762 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00763     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00764     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00765     defined(STM32F479xx)
00766 #define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
00767                              ((VALUE) == OB_PCROP_STATE_ENABLE))
00768 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
00769           STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00770
00771 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00772     defined(STM32F469xx) || defined(STM32F479xx)
00773 #define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
00774                        ((VALUE) == OPTIONBYTE_BOOTCONFIG))
00775 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00776
00777 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00778     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00779 #define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))
00780 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00781
00782 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00783     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00784 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
00785                                    ((LATENCY) == FLASH_LATENCY_1)  || \
00786                                    ((LATENCY) == FLASH_LATENCY_2)  || \
00787                                    ((LATENCY) == FLASH_LATENCY_3)  || \
00788                                    ((LATENCY) == FLASH_LATENCY_4)  || \
00789                                    ((LATENCY) == FLASH_LATENCY_5)  || \
00790                                    ((LATENCY) == FLASH_LATENCY_6)  || \
00791                                    ((LATENCY) == FLASH_LATENCY_7)  || \
00792                                    ((LATENCY) == FLASH_LATENCY_8)  || \
00793                                    ((LATENCY) == FLASH_LATENCY_9)  || \
00794                                    ((LATENCY) == FLASH_LATENCY_10) || \
00795                                    ((LATENCY) == FLASH_LATENCY_11) || \
00796                                    ((LATENCY) == FLASH_LATENCY_12) || \
00797                                    ((LATENCY) == FLASH_LATENCY_13) || \
00798                                    ((LATENCY) == FLASH_LATENCY_14) || \
00799                                    ((LATENCY) == FLASH_LATENCY_15))
00800 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00801
00802 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00803     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00804     defined(STM32F410Rx) || defined(STM32F411xE)
00805 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
00806                                    ((LATENCY) == FLASH_LATENCY_1)  || \
00807                                    ((LATENCY) == FLASH_LATENCY_2)  || \
00808                                    ((LATENCY) == FLASH_LATENCY_3)  || \
00809                                    ((LATENCY) == FLASH_LATENCY_4)  || \
00810                                    ((LATENCY) == FLASH_LATENCY_5)  || \
00811                                    ((LATENCY) == FLASH_LATENCY_6)  || \
00812                                    ((LATENCY) == FLASH_LATENCY_7))
00813 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
00814
00815 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00816 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
00817                              ((BANK) == FLASH_BANK_2)  || \
00818                              ((BANK) == FLASH_BANK_BOTH))
00819 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
00820
00821 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00822     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00823     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00824 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
00825 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */
00826
00827 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00828 #define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
00829                                   ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
00830                                   ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
00831                                   ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
00832                                   ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
00833                                   ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
00834                                   ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
00835                                   ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
00836                                   ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
00837                                   ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
00838                                   ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
00839                                   ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
00840 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00841
00842 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00843 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
00844                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
00845                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
00846                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
00847                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
00848                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))
00849 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00850
00851 #if defined(STM32F401xC)
00852 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
00853                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
00854                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5))
00855 #endif /* STM32F401xC */
00856
00857 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00858 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
00859                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
00860                                  ((SECTOR) == FLASH_SECTOR_4))
00861 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00862
00863 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
00864 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
00865                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
00866                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
00867                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
00868 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
00869
00870 #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
00871 #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
00872
00873 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00874 #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00875 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00876
00877 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00878 #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00879 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00880
00881 #if defined(STM32F401xC)
00882 #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00883 #endif /* STM32F401xC */
00884
00885 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00886 #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00887 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00888
00889 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
00890 #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00891 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
00892
00893 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00894 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00895 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00896
00897 #if defined(STM32F401xC)
00898 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00899 #endif /* STM32F401xC */
00900
00901 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00902 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00903 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00904
00905 #if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
00906 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
00907 #endif /* STM32F401xE || STM32F411xE || STM32F446xx */
00908
00909 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00910     defined(STM32F469xx) || defined(STM32F479xx)
00911 #define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
00912 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00913
00914 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00915     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
00916     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00917     defined(STM32F479xx)
00918 #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
00919 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
00920           STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00921 /**
00922   * @}
00923   */
00924
00925 /**
00926   * @}
00927   */
00928
00929 /* Private functions ---------------------------------------------------------*/
00930 /** @defgroup FLASHEx_Private_Functions FLASH Private Functions
00931   * @{
00932   */
00933 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
00934 void FLASH_FlushCaches(void);
00935 /**
00936   * @}
00937   */
00938
00939 /**
00940   * @}
00941   */
00942
00943 /**
00944   * @}
00945   */
00946
00947 #ifdef __cplusplus
00948 }
00949 #endif
00950
00951 #endif /* __STM32F4xx_HAL_FLASH_EX_H */
00952
00953 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ramfunc.c Source File

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stm32f4xx_hal_flash_ramfunc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_flash_ramfunc.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   FLASH RAMFUNC module driver.
00008   *          This file provides a FLASH firmware functions which should be
00009   *          executed from internal SRAM
00010   *            + Stop/Start the flash interface while System Run
00011   *            + Enable/Disable the flash sleep while System Run
00012   @verbatim
00013   ==============================================================================
00014                     ##### APIs executed from Internal RAM #####
00015   ==============================================================================
00016   [..]
00017     *** ARM Compiler ***
00018     --------------------
00019     [..] RAM functions are defined using the toolchain options.
00020          Functions that are be executed in RAM should reside in a separate
00021          source module. Using the 'Options for File' dialog you can simply change
00022          the 'Code / Const' area of a module to a memory space in physical RAM.
00023          Available memory areas are declared in the 'Target' tab of the
00024          Options for Target' dialog.
00025
00026     *** ICCARM Compiler ***
00027     -----------------------
00028     [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
00029
00030     *** GNU Compiler ***
00031     --------------------
00032     [..] RAM functions are defined using a specific toolchain attribute
00033          "__attribute__((section(".RamFunc")))".
00034
00035   @endverbatim
00036   ******************************************************************************
00037   * @attention
00038   *
00039   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00040   *
00041   * Redistribution and use in source and binary forms, with or without modification,
00042   * are permitted provided that the following conditions are met:
00043   *   1. Redistributions of source code must retain the above copyright notice,
00044   *      this list of conditions and the following disclaimer.
00045   *   2. Redistributions in binary form must reproduce the above copyright notice,
00046   *      this list of conditions and the following disclaimer in the documentation
00047   *      and/or other materials provided with the distribution.
00048   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00049   *      may be used to endorse or promote products derived from this software
00050   *      without specific prior written permission.
00051   *
00052   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00053   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00054   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00055   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00056   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00057   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00058   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00059   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00060   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00061   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00062   *
00063   ******************************************************************************
00064   */
00065
00066 /* Includes ------------------------------------------------------------------*/
00067 #include "stm32f4xx_hal.h"
00068
00069 /** @addtogroup STM32F4xx_HAL_Driver
00070   * @{
00071   */
00072
00073 /** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
00074   * @brief FLASH functions executed from RAM
00075   * @{
00076   */
00077 #ifdef HAL_FLASH_MODULE_ENABLED
00078 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00079 /* Private typedef -----------------------------------------------------------*/
00080 /* Private define ------------------------------------------------------------*/
00081 /* Private macro -------------------------------------------------------------*/
00082 /* Private variables ---------------------------------------------------------*/
00083 /* Private function prototypes -----------------------------------------------*/
00084 /* Exported functions --------------------------------------------------------*/
00085 /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
00090   *  @brief Peripheral Extended features functions
00091   *
00092 @verbatim
00093
00094  ===============================================================================
00095                       ##### ramfunc functions #####
00096  ===============================================================================
00097     [..]
00098     This subsection provides a set of functions that should be executed from RAM
00099     transfers.
00100
00101 @endverbatim
00102   * @{
00103   */
00104
00105 /**
00106   * @brief Stop the flash interface while System Run
00107   * @note  This mode is only available for STM32F41xxx/STM32F446xx devices.
00108   * @note  This mode couldn't be set while executing with the flash itself.
00109   *        It should be done with specific routine executed from RAM.
00110   * @retval None
00111   */
00112 __RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void)
00113 {
00114   /* Enable Power ctrl clock */
00115   __HAL_RCC_PWR_CLK_ENABLE();
00116   /* Stop the flash interface while System Run */
00117   SET_BIT(PWR->CR, PWR_CR_FISSR);
00118
00119   return HAL_OK;
00120 }
00121
00122 /**
00123   * @brief Start the flash interface while System Run
00124   * @note  This mode is only available for STM32F411xx/STM32F446xx devices.
00125   * @note  This mode couldn't be set while executing with the flash itself.
00126   *        It should be done with specific routine executed from RAM.
00127   * @retval None
00128   */
00129 __RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void)
00130 {
00131   /* Enable Power ctrl clock */
00132   __HAL_RCC_PWR_CLK_ENABLE();
00133   /* Start the flash interface while System Run */
00134   CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
00135
00136   return HAL_OK;
00137 }
00138
00139 /**
00140   * @brief Enable the flash sleep while System Run
00141   * @note  This mode is only available for STM32F41xxx/STM32F446xx devices.
00142   * @note  This mode could n't be set while executing with the flash itself.
00143   *        It should be done with specific routine executed from RAM.
00144   * @retval None
00145   */
00146 __RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void)
00147 {
00148   /* Enable Power ctrl clock */
00149   __HAL_RCC_PWR_CLK_ENABLE();
00150   /* Enable the flash sleep while System Run */
00151   SET_BIT(PWR->CR, PWR_CR_FMSSR);
00152
00153   return HAL_OK;
00154 }
00155
00156 /**
00157   * @brief Disable the flash sleep while System Run
00158   * @note  This mode is only available for STM32F41xxx/STM32F446xx devices.
00159   * @note  This mode couldn't be set while executing with the flash itself.
00160   *        It should be done with specific routine executed from RAM.
00161   * @retval None
00162   */
00163 __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void)
00164 {
00165   /* Enable Power ctrl clock */
00166   __HAL_RCC_PWR_CLK_ENABLE();
00167   /* Disable the flash sleep while System Run */
00168   CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
00169
00170   return HAL_OK;
00171 }
00172
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 #endif /* STM32F410xx || STM32F411xE || STM32F446xx */
00182 #endif /* HAL_FLASH_MODULE_ENABLED */
00183 /**
00184   * @}
00185   */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_flash_ramfunc.h Source File

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stm32f4xx_hal_flash_ramfunc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_flash_ramfunc.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of FLASH RAMFUNC driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_FLASH_RAMFUNC_H
00040 #define __STM32F4xx_FLASH_RAMFUNC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx)
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup FLASH_RAMFUNC
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported macro ------------------------------------------------------------*/
00060 /* Exported functions --------------------------------------------------------*/
00061 /** @addtogroup FLASH_RAMFUNC_Exported_Functions
00062   * @{
00063   */
00064
00065 /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
00066   * @{
00067   */
00068 __RAM_FUNC HAL_FLASHEx_StopFlashInterfaceClk(void);
00069 __RAM_FUNC HAL_FLASHEx_StartFlashInterfaceClk(void);
00070 __RAM_FUNC HAL_FLASHEx_EnableFlashSleepMode(void);
00071 __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void);
00072 /**
00073   * @}
00074   */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /**
00085   * @}
00086   */
00087
00088 #endif /* STM32F410xx || STM32F411xE || STM32F446xx */
00089 #ifdef __cplusplus
00090 }
00091 #endif
00092
00093
00094 #endif /* __STM32F4xx_FLASH_RAMFUNC_H */
00095
00096 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c.c Source File

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stm32f4xx_hal_fmpi2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_fmpi2c.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   FMPI2C HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020     The FMPI2C HAL driver can be used as follows:
00021
00022     (#) Declare a FMPI2C_HandleTypeDef handle structure, for example:
00023         FMPI2C_HandleTypeDef  hfmpi2c;
00024
00025     (#)Initialize the FMPI2C low level resources by implementing the HAL_FMPI2C_MspInit() API:
00026         (##) Enable the FMPI2Cx interface clock
00027         (##) FMPI2C pins configuration
00028             (+++) Enable the clock for the FMPI2C GPIOs
00029             (+++) Configure FMPI2C pins as alternate function open-drain
00030         (##) NVIC configuration if you need to use interrupt process
00031             (+++) Configure the FMPI2Cx interrupt priority
00032             (+++) Enable the NVIC FMPI2C IRQ Channel
00033         (##) DMA Configuration if you need to use DMA process
00034             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00035             (+++) Enable the DMAx interface clock using
00036             (+++) Configure the DMA handle parameters
00037             (+++) Configure the DMA Tx or Rx channel
00038             (+++) Associate the initialized DMA handle to the hfmpi2c DMA Tx or Rx handle
00039             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00040                   the DMA Tx or Rx channel
00041
00042     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00043         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.
00044
00045     (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware
00046         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_FMPI2C_MspInit(&hfmpi2c) API.
00047
00048     (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady()
00049
00050     (#) For FMPI2C IO and IO MEM operations, three operation modes are available within this driver :
00051
00052     *** Polling mode IO operation ***
00053     =================================
00054     [..]
00055       (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit()
00056       (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive()
00057       (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit()
00058       (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive()
00059
00060     *** Polling mode IO MEM operation ***
00061     =====================================
00062     [..]
00063       (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write()
00064       (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read()
00065
00066
00067     *** Interrupt mode IO operation ***
00068     ===================================
00069     [..]
00070       (+) Transmit in master mode an amount of data in no blocking mode using HAL_FMPI2C_Master_Transmit_IT()
00071       (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
00072            add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
00073       (+) Receive in master mode an amount of data in no blocking mode using HAL_FMPI2C_Master_Receive_IT()
00074       (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
00075            add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
00076       (+) Transmit in slave mode an amount of data in no blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
00077       (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
00078            add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
00079       (+) Receive in slave mode an amount of data in no blocking mode using HAL_FMPI2C_Slave_Receive_IT()
00080       (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
00081            add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
00082       (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
00083            add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
00084
00085         *** Interrupt mode IO sequential operation ***
00086     ==============================================
00087     [..]
00088       (+@) These interfaces allow to manage a sequential transfer with a repeated start condition
00089           when a direction change during transfer
00090       (+) A specific option manage the different steps of a sequential transfer
00091       (+) Different steps option FMPI2C_XferOptions_definition are listed below :
00092       (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
00093       (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a start condition with data to transfer without a final stop condition
00094       (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
00095              manage only the new data to transfer if no direction change and without a final stop condition in both cases
00096       (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
00097              manage only the new data to transfer if no direction change and with a final stop condition in both cases
00098
00099       (+) Sequential transmit in master FMPI2C mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT()
00100       (++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
00101            add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
00102       (+) Sequential receive in master FMPI2C mode an amount of data in non blocking mode using HAL_FMPI2C_Master_Sequential_Receive_IT()
00103       (++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
00104            add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
00105       (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
00106       (++) The associated previous transfer callback is called at the end of abort process
00107       (++) mean HAL_FMPI2C_MasterTxCpltCallback() in case of previous state was master transmit
00108       (++) mean HAL_FMPI2C_MasterRxCpltCallback() in case of previous state was master receive
00109       (+) Enable/disable the Address listen mode in slave FMPI2C mode
00110            using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT()
00111       (++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can
00112            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00113       (++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can
00114            add his own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback()
00115       (+) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Transmit_IT()
00116       (++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
00117            add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
00118       (+) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Receive_IT()
00119       (++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
00120            add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
00121
00122     *** Interrupt mode IO MEM operation ***
00123     =======================================
00124     [..]
00125       (+) Write an amount of data in no blocking mode with Interrupt to a specific memory address using
00126           HAL_FMPI2C_Mem_Write_IT()
00127       (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
00128            add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
00129       (+) Read an amount of data in no blocking mode with Interrupt from a specific memory address using
00130           HAL_FMPI2C_Mem_Read_IT()
00131       (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
00132            add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
00133       (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
00134            add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
00135
00136     *** DMA mode IO operation ***
00137     ==============================
00138     [..]
00139       (+) Transmit in master mode an amount of data in no blocking mode (DMA) using
00140           HAL_FMPI2C_Master_Transmit_DMA()
00141       (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
00142            add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
00143       (+) Receive in master mode an amount of data in no blocking mode (DMA) using
00144           HAL_FMPI2C_Master_Receive_DMA()
00145       (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
00146            add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
00147       (+) Transmit in slave mode an amount of data in no blocking mode (DMA) using
00148           HAL_FMPI2C_Slave_Transmit_DMA()
00149       (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
00150            add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
00151       (+) Receive in slave mode an amount of data in no blocking mode (DMA) using
00152           HAL_FMPI2C_Slave_Receive_DMA()
00153       (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
00154            add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
00155       (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
00156            add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
00157
00158     *** DMA mode IO MEM operation ***
00159     =================================
00160     [..]
00161       (+) Write an amount of data in no blocking mode with DMA to a specific memory address using
00162           HAL_FMPI2C_Mem_Write_DMA()
00163       (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
00164            add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
00165       (+) Read an amount of data in no blocking mode with DMA from a specific memory address using
00166           HAL_FMPI2C_Mem_Read_DMA()
00167       (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
00168            add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
00169       (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
00170            add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
00171
00172      *** FMPI2C HAL driver macros list ***
00173      ==================================
00174      [..]
00175        Below the list of most used macros in FMPI2C HAL driver.
00176
00177       (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
00178       (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
00179       (+) __HAL_FMPI2C_GET_FLAG : Checks whether the specified FMPI2C flag is set or not
00180       (+) __HAL_FMPI2C_CLEAR_FLAG : Clears the specified FMPI2C pending flag
00181       (+) __HAL_FMPI2C_ENABLE_IT: Enables the specified FMPI2C interrupt
00182       (+) __HAL_FMPI2C_DISABLE_IT: Disables the specified FMPI2C interrupt
00183
00184      [..]
00185        (@) You can refer to the FMPI2C HAL driver header file for more useful macros
00186
00187   @endverbatim
00188   ******************************************************************************
00189   * @attention
00190   *
00191   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00192   *
00193   * Redistribution and use in source and binary forms, with or without modification,
00194   * are permitted provided that the following conditions are met:
00195   *   1. Redistributions of source code must retain the above copyright notice,
00196   *      this list of conditions and the following disclaimer.
00197   *   2. Redistributions in binary form must reproduce the above copyright notice,
00198   *      this list of conditions and the following disclaimer in the documentation
00199   *      and/or other materials provided with the distribution.
00200   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00201   *      may be used to endorse or promote products derived from this software
00202   *      without specific prior written permission.
00203   *
00204   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00205   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00206   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00207   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00208   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00209   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00210   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00211   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00212   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00213   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00214   *
00215   ******************************************************************************
00216   */
00217
00218 /* Includes ------------------------------------------------------------------*/
00219 #include "stm32f4xx_hal.h"
00220
00221 /** @addtogroup STM32F4xx_HAL_Driver
00222   * @{
00223   */
00224
00225 /** @defgroup FMPI2C FMPI2C
00226   * @brief FMPI2C HAL module driver
00227   * @{
00228   */
00229
00230 #ifdef HAL_FMPI2C_MODULE_ENABLED
00231
00232 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
00233
00234 /* Private typedef -----------------------------------------------------------*/
00235 /* Private define ------------------------------------------------------------*/
00236
00237 /** @defgroup FMPI2C_Private_Define FMPI2C Private Define
00238   * @{
00239   */
00240 #define TIMING_CLEAR_MASK      ((uint32_t)0xF0FFFFFFU)  /*!< FMPI2C TIMING clear register Mask */
00241 #define FMPI2C_TIMEOUT_ADDR    ((uint32_t)10000U)       /*!< 10 s  */
00242 #define FMPI2C_TIMEOUT_BUSY    ((uint32_t)25U)          /*!< 25 ms */
00243 #define FMPI2C_TIMEOUT_DIR     ((uint32_t)25U)          /*!< 25 ms */
00244 #define FMPI2C_TIMEOUT_RXNE    ((uint32_t)25U)          /*!< 25 ms */
00245 #define FMPI2C_TIMEOUT_STOPF   ((uint32_t)25U)          /*!< 25 ms */
00246 #define FMPI2C_TIMEOUT_TC      ((uint32_t)25U)          /*!< 25 ms */
00247 #define FMPI2C_TIMEOUT_TCR     ((uint32_t)25U)          /*!< 25 ms */
00248 #define FMPI2C_TIMEOUT_TXIS    ((uint32_t)25U)          /*!< 25 ms */
00249 #define FMPI2C_TIMEOUT_FLAG    ((uint32_t)25U)          /*!< 25 ms */
00250
00251 #define MAX_NBYTE_SIZE      255U
00252 #define SlaveAddr_SHIFT     7U
00253 #define SlaveAddr_MSK       0x06U
00254
00255 /* Private define for @ref PreviousState usage */
00256 #define FMPI2C_STATE_MSK             ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~HAL_FMPI2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
00257 #define FMPI2C_STATE_NONE            ((uint32_t)(HAL_FMPI2C_MODE_NONE))                                                        /*!< Default Value                                          */
00258 #define FMPI2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00259 #define FMPI2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00260 #define FMPI2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00261 #define FMPI2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00262 #define FMPI2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00263 #define FMPI2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /* Private macro -------------------------------------------------------------*/
00270 /* Private variables ---------------------------------------------------------*/
00271 /* Private function prototypes -----------------------------------------------*/
00272
00273 /** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
00274   * @{
00275   */
00276 static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00277 static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00278 static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00279 static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00280 static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
00281 static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
00282 static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma);
00283
00284 static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
00285 static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
00286 static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00287 static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
00288 static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
00289 static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
00290 static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout);
00291
00292 static HAL_StatusTypeDef FMPI2C_Master_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
00293 static HAL_StatusTypeDef FMPI2C_Slave_ISR(FMPI2C_HandleTypeDef *hfmpi2c);
00294
00295 static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
00296 static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
00297
00298 static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00299 /**
00300   * @}
00301   */
00302
00303 /* Exported functions --------------------------------------------------------*/
00304
00305 /** @defgroup FMPI2C_Exported_Functions FMPI2C Exported Functions
00306   * @{
00307   */
00308
00309 /** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
00310   * @brief    Initialization and Configuration functions
00311   *
00312 @verbatim
00313  ===============================================================================
00314               ##### Initialization and de-initialization functions #####
00315  ===============================================================================
00316     [..]  This subsection provides a set of functions allowing to initialize and
00317           deinitialize the FMPI2Cx peripheral:
00318
00319       (+) User must Implement HAL_FMPI2C_MspInit() function in which he configures
00320           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00321
00322       (+) Call the function HAL_FMPI2C_Init() to configure the selected device with
00323           the selected configuration:
00324         (++) Clock Timing
00325         (++) Own Address 1
00326         (++) Addressing mode (Master, Slave)
00327         (++) Dual Addressing mode
00328         (++) Own Address 2
00329         (++) Own Address 2 Mask
00330         (++) General call mode
00331         (++) Nostretch mode
00332
00333       (+) Call the function HAL_FMPI2C_DeInit() to restore the default configuration
00334           of the selected FMPI2Cx peripheral.
00335
00336 @endverbatim
00337   * @{
00338   */
00339
00340 /**
00341   * @brief  Initializes the FMPI2C according to the specified parameters
00342   *         in the FMPI2C_InitTypeDef and initialize the associated handle.
00343   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00344   *                the configuration information for the specified FMPI2C.
00345   * @retval HAL status
00346   */
00347 HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
00348 {
00349   /* Check the FMPI2C handle allocation */
00350   if(hfmpi2c == NULL)
00351   {
00352     return HAL_ERROR;
00353   }
00354
00355   /* Check the parameters */
00356   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
00357   assert_param(IS_FMPI2C_OWN_ADDRESS1(hfmpi2c->Init.OwnAddress1));
00358   assert_param(IS_FMPI2C_ADDRESSING_MODE(hfmpi2c->Init.AddressingMode));
00359   assert_param(IS_FMPI2C_DUAL_ADDRESS(hfmpi2c->Init.DualAddressMode));
00360   assert_param(IS_FMPI2C_OWN_ADDRESS2(hfmpi2c->Init.OwnAddress2));
00361   assert_param(IS_FMPI2C_OWN_ADDRESS2_MASK(hfmpi2c->Init.OwnAddress2Masks));
00362   assert_param(IS_FMPI2C_GENERAL_CALL(hfmpi2c->Init.GeneralCallMode));
00363   assert_param(IS_FMPI2C_NO_STRETCH(hfmpi2c->Init.NoStretchMode));
00364
00365   if(hfmpi2c->State == HAL_FMPI2C_STATE_RESET)
00366   {
00367     /* Allocate lock resource and initialize it */
00368     hfmpi2c->Lock = HAL_UNLOCKED;
00369
00370     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00371     HAL_FMPI2C_MspInit(hfmpi2c);
00372   }
00373
00374   hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
00375
00376   /* Disable the selected FMPI2C peripheral */
00377   __HAL_FMPI2C_DISABLE(hfmpi2c);
00378
00379   /*---------------------------- FMPI2Cx TIMINGR Configuration ------------------*/
00380   /* Configure FMPI2Cx: Frequency range */
00381   hfmpi2c->Instance->TIMINGR = hfmpi2c->Init.Timing & TIMING_CLEAR_MASK;
00382
00383   /*---------------------------- FMPI2Cx OAR1 Configuration ---------------------*/
00384   /* Configure FMPI2Cx: Own Address1 and ack own address1 mode */
00385   hfmpi2c->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN;
00386   if(hfmpi2c->Init.OwnAddress1 != 0U)
00387   {
00388     if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
00389     {
00390       hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1);
00391     }
00392     else /* FMPI2C_ADDRESSINGMODE_10BIT */
00393     {
00394       hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1);
00395     }
00396   }
00397
00398   /*---------------------------- FMPI2Cx CR2 Configuration ----------------------*/
00399   /* Configure FMPI2Cx: Addressing Master mode */
00400   if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
00401   {
00402     hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10);
00403   }
00404   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00405   hfmpi2c->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK);
00406
00407   /*---------------------------- FMPI2Cx OAR2 Configuration ---------------------*/
00408   /* Configure FMPI2Cx: Dual mode and Own Address2 */
00409   hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8U));
00410
00411   /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/
00412   /* Configure FMPI2Cx: Generalcall and NoStretch mode */
00413   hfmpi2c->Instance->CR1 = (hfmpi2c->Init.GeneralCallMode | hfmpi2c->Init.NoStretchMode);
00414
00415   /* Enable the selected FMPI2C peripheral */
00416   __HAL_FMPI2C_ENABLE(hfmpi2c);
00417
00418   hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
00419   hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00420   hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
00421   hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
00422
00423   return HAL_OK;
00424 }
00425
00426 /**
00427   * @brief  DeInitialize the FMPI2C peripheral.
00428   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00429   *                the configuration information for the specified FMPI2C.
00430   * @retval HAL status
00431   */
00432 HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
00433 {
00434   /* Check the FMPI2C handle allocation */
00435   if(hfmpi2c == NULL)
00436   {
00437     return HAL_ERROR;
00438   }
00439
00440   /* Check the parameters */
00441   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
00442
00443   hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
00444
00445   /* Disable the FMPI2C Peripheral Clock */
00446   __HAL_FMPI2C_DISABLE(hfmpi2c);
00447
00448   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00449   HAL_FMPI2C_MspDeInit(hfmpi2c);
00450
00451   hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
00452   hfmpi2c->State = HAL_FMPI2C_STATE_RESET;
00453   hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
00454   hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
00455
00456   /* Release Lock */
00457   __HAL_UNLOCK(hfmpi2c);
00458
00459   return HAL_OK;
00460 }
00461
00462 /**
00463   * @brief Initialize the FMPI2C MSP.
00464   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00465   *                the configuration information for the specified FMPI2C.
00466   * @retval None
00467   */
00468  __weak void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c)
00469 {
00470   /* Prevent unused argument(s) compilation warning */
00471   UNUSED(hfmpi2c);
00472   /* NOTE : This function Should not be modified, when the callback is needed,
00473             the HAL_FMPI2C_MspInit could be implemented in the user file
00474    */
00475 }
00476
00477 /**
00478   * @brief DeInitialize the FMPI2C MSP.
00479   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00480   *                the configuration information for the specified FMPI2C.
00481   * @retval None
00482   */
00483  __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
00484 {
00485   /* Prevent unused argument(s) compilation warning */
00486   UNUSED(hfmpi2c);
00487   /* NOTE : This function Should not be modified, when the callback is needed,
00488             the HAL_FMPI2C_MspDeInit could be implemented in the user file
00489    */
00490 }
00491
00492 /**
00493   * @}
00494   */
00495
00496 /** @defgroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
00497   *  @brief   Data transfers functions
00498   *
00499 @verbatim
00500  ===============================================================================
00501                       ##### IO operation functions #####
00502  ===============================================================================
00503     [..]
00504     This subsection provides a set of functions allowing to manage the FMPI2C data
00505     transfers.
00506
00507     (#) There are two modes of transfer:
00508        (++) Blocking mode : The communication is performed in the polling mode.
00509             The status of all data processing is returned by the same function
00510             after finishing transfer.
00511        (++) No Blocking mode : The communication is performed using Interrupts
00512             or DMA. These functions return the status of the transfer startup.
00513             The end of the data processing will be indicated through the
00514             dedicated FMPI2C IRQ when using Interrupt mode or the DMA IRQ when
00515             using DMA mode.
00516
00517     (#) Blocking mode functions are :
00518         (++) HAL_FMPI2C_Master_Transmit()
00519         (++) HAL_FMPI2C_Master_Receive()
00520         (++) HAL_FMPI2C_Slave_Transmit()
00521         (++) HAL_FMPI2C_Slave_Receive()
00522         (++) HAL_FMPI2C_Mem_Write()
00523         (++) HAL_FMPI2C_Mem_Read()
00524         (++) HAL_FMPI2C_IsDeviceReady()
00525
00526     (#) No Blocking mode functions with Interrupt are :
00527         (++) HAL_FMPI2C_Master_Transmit_IT()
00528         (++) HAL_FMPI2C_Master_Receive_IT()
00529         (++) HAL_FMPI2C_Slave_Transmit_IT()
00530         (++) HAL_FMPI2C_Slave_Receive_IT()
00531         (++) HAL_FMPI2C_Mem_Write_IT()
00532         (++) HAL_FMPI2C_Mem_Read_IT()
00533
00534     (#) No Blocking mode functions with DMA are :
00535         (++) HAL_FMPI2C_Master_Transmit_DMA()
00536         (++) HAL_FMPI2C_Master_Receive_DMA()
00537         (++) HAL_FMPI2C_Slave_Transmit_DMA()
00538         (++) HAL_FMPI2C_Slave_Receive_DMA()
00539         (++) HAL_FMPI2C_Mem_Write_DMA()
00540         (++) HAL_FMPI2C_Mem_Read_DMA()
00541
00542     (#) A set of Transfer Complete Callbacks are provided in no Blocking mode:
00543         (++) HAL_FMPI2C_MemTxCpltCallback()
00544         (++) HAL_FMPI2C_MemRxCpltCallback()
00545         (++) HAL_FMPI2C_MasterTxCpltCallback()
00546         (++) HAL_FMPI2C_MasterRxCpltCallback()
00547         (++) HAL_FMPI2C_SlaveTxCpltCallback()
00548         (++) HAL_FMPI2C_SlaveRxCpltCallback()
00549         (++) HAL_FMPI2C_ErrorCallback()
00550
00551 @endverbatim
00552   * @{
00553   */
00554
00555 /**
00556   * @brief  Transmits in master mode an amount of data in blocking mode.
00557   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00558   *                the configuration information for the specified FMPI2C.
00559   * @param  DevAddress Target device address
00560   * @param  pData Pointer to data buffer
00561   * @param  Size Amount of data to be sent
00562   * @param  Timeout Timeout duration
00563   * @retval HAL status
00564   */
00565 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00566 {
00567   uint32_t sizetmp = 0U;
00568
00569   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00570   {
00571     if((pData == NULL ) || (Size == 0U))
00572     {
00573       return  HAL_ERROR;
00574     }
00575
00576     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
00577     {
00578       return HAL_BUSY;
00579     }
00580
00581     /* Process Locked */
00582     __HAL_LOCK(hfmpi2c);
00583
00584     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
00585     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
00586     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
00587
00588     /* Send Slave Address */
00589     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00590     /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
00591     if(Size > MAX_NBYTE_SIZE)
00592     {
00593       FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
00594       sizetmp = MAX_NBYTE_SIZE;
00595     }
00596     else
00597     {
00598       FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
00599       sizetmp = Size;
00600     }
00601
00602     do
00603     {
00604       /* Wait until TXIS flag is set */
00605       if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
00606       {
00607         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
00608         {
00609           return HAL_ERROR;
00610         }
00611         else
00612         {
00613           return HAL_TIMEOUT;
00614         }
00615       }
00616       /* Write data to TXDR */
00617       hfmpi2c->Instance->TXDR = (*pData++);
00618       sizetmp--;
00619       Size--;
00620
00621       if((sizetmp == 0U)&&(Size!=0U))
00622       {
00623         /* Wait until TXE flag is set */
00624         if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
00625         {
00626           return HAL_TIMEOUT;
00627         }
00628
00629         if(Size > MAX_NBYTE_SIZE)
00630         {
00631           FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
00632           sizetmp = MAX_NBYTE_SIZE;
00633         }
00634         else
00635         {
00636           FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
00637           sizetmp = Size;
00638         }
00639       }
00640
00641     }while(Size > 0U);
00642
00643     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00644     /* Wait until STOPF flag is set */
00645     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
00646     {
00647       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
00648       {
00649         return HAL_ERROR;
00650       }
00651       else
00652       {
00653         return HAL_TIMEOUT;
00654       }
00655     }
00656
00657     /* Clear STOP Flag */
00658     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
00659
00660     /* Clear Configuration Register 2 */
00661     FMPI2C_RESET_CR2(hfmpi2c);
00662
00663     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00664     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
00665
00666     /* Process Unlocked */
00667     __HAL_UNLOCK(hfmpi2c);
00668
00669     return HAL_OK;
00670   }
00671   else
00672   {
00673     return HAL_BUSY;
00674   }
00675 }
00676
00677 /**
00678   * @brief  Receives in master mode an amount of data in blocking mode.
00679   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00680   *                the configuration information for the specified FMPI2C.
00681   * @param  DevAddress Target device address
00682   * @param  pData Pointer to data buffer
00683   * @param  Size Amount of data to be sent
00684   * @param  Timeout Timeout duration
00685   * @retval HAL status
00686   */
00687 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00688 {
00689   uint32_t sizetmp = 0U;
00690
00691   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00692   {
00693     if((pData == NULL ) || (Size == 0U))
00694     {
00695       return  HAL_ERROR;
00696     }
00697
00698     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
00699     {
00700       return HAL_BUSY;
00701     }
00702
00703     /* Process Locked */
00704     __HAL_LOCK(hfmpi2c);
00705
00706     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
00707     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
00708     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
00709
00710     /* Send Slave Address */
00711     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00712     /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
00713     if(Size > MAX_NBYTE_SIZE)
00714     {
00715       FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
00716       sizetmp = MAX_NBYTE_SIZE;
00717     }
00718     else
00719     {
00720       FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
00721       sizetmp = Size;
00722     }
00723
00724     do
00725     {
00726       /* Wait until RXNE flag is set */
00727       if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00728       {
00729         return HAL_TIMEOUT;
00730       }
00731
00732       /* Write data to RXDR */
00733       (*pData++) =hfmpi2c->Instance->RXDR;
00734       sizetmp--;
00735       Size--;
00736
00737       if((sizetmp == 0U)&&(Size!=0U))
00738       {
00739         /* Wait until TCR flag is set */
00740         if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
00741         {
00742           return HAL_TIMEOUT;
00743         }
00744
00745         if(Size > MAX_NBYTE_SIZE)
00746         {
00747           FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
00748           sizetmp = MAX_NBYTE_SIZE;
00749         }
00750         else
00751         {
00752           FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
00753           sizetmp = Size;
00754         }
00755       }
00756
00757     }while(Size > 0U);
00758
00759     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00760     /* Wait until STOPF flag is set */
00761     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
00762     {
00763       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
00764       {
00765         return HAL_ERROR;
00766       }
00767       else
00768       {
00769         return HAL_TIMEOUT;
00770       }
00771     }
00772
00773     /* Clear STOP Flag */
00774     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
00775
00776     /* Clear Configuration Register 2 */
00777     FMPI2C_RESET_CR2(hfmpi2c);
00778
00779     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00780     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
00781
00782     /* Process Unlocked */
00783     __HAL_UNLOCK(hfmpi2c);
00784
00785     return HAL_OK;
00786   }
00787   else
00788   {
00789     return HAL_BUSY;
00790   }
00791 }
00792
00793 /**
00794   * @brief  Transmits in slave mode an amount of data in blocking mode.
00795   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00796   *                the configuration information for the specified FMPI2C.
00797   * @param  pData Pointer to data buffer
00798   * @param  Size Amount of data to be sent
00799   * @param  Timeout Timeout duration
00800   * @retval HAL status
00801   */
00802 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00803 {
00804   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00805   {
00806     if((pData == NULL ) || (Size == 0U))
00807     {
00808       return  HAL_ERROR;
00809     }
00810
00811     /* Process Locked */
00812     __HAL_LOCK(hfmpi2c);
00813
00814     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
00815     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
00816     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
00817
00818     /* Enable Address Acknowledge */
00819     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
00820
00821     /* Wait until ADDR flag is set */
00822     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00823     {
00824       /* Disable Address Acknowledge */
00825       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00826       return HAL_TIMEOUT;
00827     }
00828
00829     /* Clear ADDR flag */
00830     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
00831
00832     /* If 10bit addressing mode is selected */
00833     if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
00834     {
00835       /* Wait until ADDR flag is set */
00836       if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00837       {
00838         /* Disable Address Acknowledge */
00839         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00840         return HAL_TIMEOUT;
00841       }
00842
00843       /* Clear ADDR flag */
00844       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
00845     }
00846
00847     /* Wait until DIR flag is set Transmitter mode */
00848     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
00849     {
00850       /* Disable Address Acknowledge */
00851       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00852       return HAL_TIMEOUT;
00853     }
00854
00855     do
00856     {
00857       /* Wait until TXIS flag is set */
00858       if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
00859       {
00860         /* Disable Address Acknowledge */
00861         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00862
00863         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
00864         {
00865           return HAL_ERROR;
00866         }
00867         else
00868         {
00869           return HAL_TIMEOUT;
00870         }
00871       }
00872
00873       /* Write data to TXDR */
00874       hfmpi2c->Instance->TXDR = (*pData++);
00875       Size--;
00876     }while(Size > 0U);
00877
00878     /* Wait until STOP flag is set */
00879     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
00880     {
00881       /* Disable Address Acknowledge */
00882       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00883
00884       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
00885       {
00886         /* Normal use case for Transmitter mode */
00887         /* A NACK is generated to confirm the end of transfer */
00888         hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
00889       }
00890       else
00891       {
00892         return HAL_TIMEOUT;
00893       }
00894     }
00895
00896     /* Clear STOP flag */
00897     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
00898
00899     /* Wait until BUSY flag is reset */
00900     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
00901     {
00902       /* Disable Address Acknowledge */
00903       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00904       return HAL_TIMEOUT;
00905     }
00906
00907     /* Disable Address Acknowledge */
00908     hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00909
00910     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00911     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
00912
00913     /* Process Unlocked */
00914     __HAL_UNLOCK(hfmpi2c);
00915
00916     return HAL_OK;
00917   }
00918   else
00919   {
00920     return HAL_BUSY;
00921   }
00922 }
00923
00924 /**
00925   * @brief  Receive in slave mode an amount of data in blocking mode
00926   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00927   *                the configuration information for the specified FMPI2C.
00928   * @param  pData Pointer to data buffer
00929   * @param  Size Amount of data to be sent
00930   * @param  Timeout Timeout duration
00931   * @retval HAL status
00932   */
00933 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00934 {
00935   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00936   {
00937     if((pData == NULL ) || (Size == 0U))
00938     {
00939       return  HAL_ERROR;
00940     }
00941
00942     /* Process Locked */
00943     __HAL_LOCK(hfmpi2c);
00944
00945     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
00946     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
00947     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
00948
00949     /* Enable Address Acknowledge */
00950     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
00951
00952     /* Wait until ADDR flag is set */
00953     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00954     {
00955       /* Disable Address Acknowledge */
00956       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00957       return HAL_TIMEOUT;
00958     }
00959
00960     /* Clear ADDR flag */
00961     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
00962
00963     /* Wait until DIR flag is reset Receiver mode */
00964     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout) != HAL_OK)
00965     {
00966       /* Disable Address Acknowledge */
00967       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00968       return HAL_TIMEOUT;
00969     }
00970
00971     while(Size > 0U)
00972     {
00973       /* Wait until RXNE flag is set */
00974       if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
00975       {
00976         /* Disable Address Acknowledge */
00977         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00978         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
00979         {
00980           return HAL_TIMEOUT;
00981         }
00982         else
00983         {
00984           return HAL_ERROR;
00985         }
00986       }
00987
00988       /* Read data from RXDR */
00989       (*pData++) = hfmpi2c->Instance->RXDR;
00990       Size--;
00991     }
00992
00993     /* Wait until STOP flag is set */
00994     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
00995     {
00996       /* Disable Address Acknowledge */
00997       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
00998
00999       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01000       {
01001         return HAL_ERROR;
01002       }
01003       else
01004       {
01005         return HAL_TIMEOUT;
01006       }
01007     }
01008
01009     /* Clear STOP flag */
01010     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
01011
01012     /* Wait until BUSY flag is reset */
01013     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
01014     {
01015       /* Disable Address Acknowledge */
01016       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01017       return HAL_TIMEOUT;
01018     }
01019
01020
01021     /* Disable Address Acknowledge */
01022     hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01023
01024     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
01025     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
01026
01027     /* Process Unlocked */
01028     __HAL_UNLOCK(hfmpi2c);
01029
01030     return HAL_OK;
01031   }
01032   else
01033   {
01034     return HAL_BUSY;
01035   }
01036 }
01037
01038 /**
01039   * @brief  Transmit in master mode an amount of data in no blocking mode with Interrupt
01040   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01041   *                the configuration information for the specified FMPI2C.
01042   * @param  DevAddress Target device address
01043   * @param  pData Pointer to data buffer
01044   * @param  Size Amount of data to be sent
01045   * @retval HAL status
01046   */
01047 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01048 {
01049   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01050   {
01051     if((pData == NULL) || (Size == 0U))
01052     {
01053       return  HAL_ERROR;
01054     }
01055
01056     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
01057     {
01058       return HAL_BUSY;
01059     }
01060
01061     /* Process Locked */
01062     __HAL_LOCK(hfmpi2c);
01063
01064     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
01065     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
01066     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
01067     hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
01068
01069     hfmpi2c->pBuffPtr = pData;
01070     hfmpi2c->XferCount = Size;
01071     if(Size > MAX_NBYTE_SIZE)
01072     {
01073       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
01074     }
01075     else
01076     {
01077       hfmpi2c->XferSize = Size;
01078     }
01079
01080     /* Send Slave Address */
01081     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01082     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
01083     {
01084       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
01085     }
01086     else
01087     {
01088       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
01089     }
01090
01091     /* Process Unlocked */
01092     __HAL_UNLOCK(hfmpi2c);
01093
01094     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
01095               to avoid the risk of FMPI2C interrupt handle execution before current
01096               process unlock */
01097
01098
01099     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01100     /* possible to enable all of these */
01101     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
01102     __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
01103
01104     return HAL_OK;
01105   }
01106   else
01107   {
01108     return HAL_BUSY;
01109   }
01110 }
01111
01112 /**
01113   * @brief  Receive in master mode an amount of data in no blocking mode with Interrupt
01114   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01115   *                the configuration information for the specified FMPI2C.
01116   * @param  DevAddress Target device address
01117   * @param  pData Pointer to data buffer
01118   * @param  Size Amount of data to be sent
01119   * @retval HAL status
01120   */
01121 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01122 {
01123   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01124   {
01125     if((pData == NULL) || (Size == 0U))
01126     {
01127       return  HAL_ERROR;
01128     }
01129
01130     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
01131     {
01132       return HAL_BUSY;
01133     }
01134
01135     /* Process Locked */
01136     __HAL_LOCK(hfmpi2c);
01137
01138     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
01139     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
01140     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
01141     hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
01142
01143     hfmpi2c->pBuffPtr = pData;
01144     hfmpi2c->XferCount = Size;
01145     if(Size > MAX_NBYTE_SIZE)
01146     {
01147       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
01148     }
01149     else
01150     {
01151       hfmpi2c->XferSize = Size;
01152     }
01153
01154     /* Send Slave Address */
01155     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01156     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
01157     {
01158       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
01159     }
01160     else
01161     {
01162       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
01163     }
01164
01165     /* Process Unlocked */
01166     __HAL_UNLOCK(hfmpi2c);
01167
01168     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
01169               to avoid the risk of FMPI2C interrupt handle execution before current
01170               process unlock */
01171
01172     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01173     /* possible to enable all of these */
01174     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
01175     __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
01176
01177     return HAL_OK;
01178   }
01179   else
01180   {
01181     return HAL_BUSY;
01182   }
01183 }
01184
01185 /**
01186   * @brief  Transmit in slave mode an amount of data in no blocking mode with Interrupt
01187   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01188   *                the configuration information for the specified FMPI2C.
01189   * @param  pData Pointer to data buffer
01190   * @param  Size Amount of data to be sent
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
01194 {
01195   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01196   {
01197     if((pData == NULL) || (Size == 0U))
01198     {
01199       return  HAL_ERROR;
01200     }
01201
01202     /* Process Locked */
01203     __HAL_LOCK(hfmpi2c);
01204
01205     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
01206     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
01207     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
01208     hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
01209
01210     /* Enable Address Acknowledge */
01211     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
01212
01213     hfmpi2c->pBuffPtr = pData;
01214     hfmpi2c->XferSize = Size;
01215     hfmpi2c->XferCount = Size;
01216
01217     /* Process Unlocked */
01218     __HAL_UNLOCK(hfmpi2c);
01219
01220     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
01221               to avoid the risk of FMPI2C interrupt handle execution before current
01222               process unlock */
01223
01224     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01225     /* possible to enable all of these */
01226     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
01227     __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_TXI );
01228
01229     return HAL_OK;
01230   }
01231   else
01232   {
01233     return HAL_BUSY;
01234   }
01235 }
01236
01237 /**
01238   * @brief  Receive in slave mode an amount of data in no blocking mode with Interrupt
01239   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01240   *                the configuration information for the specified FMPI2C.
01241   * @param  pData Pointer to data buffer
01242   * @param  Size Amount of data to be sent
01243   * @retval HAL status
01244   */
01245 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
01246 {
01247   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01248   {
01249     if((pData == NULL) || (Size == 0U))
01250     {
01251       return  HAL_ERROR;
01252     }
01253
01254     /* Process Locked */
01255     __HAL_LOCK(hfmpi2c);
01256
01257     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
01258     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
01259     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
01260     hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
01261
01262     /* Enable Address Acknowledge */
01263     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
01264
01265     hfmpi2c->pBuffPtr = pData;
01266     hfmpi2c->XferSize = Size;
01267     hfmpi2c->XferCount = Size;
01268
01269     /* Process Unlocked */
01270     __HAL_UNLOCK(hfmpi2c);
01271
01272     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
01273               to avoid the risk of FMPI2C interrupt handle execution before current
01274               process unlock */
01275
01276     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01277     /* possible to enable all of these */
01278     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
01279     __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI);
01280
01281     return HAL_OK;
01282   }
01283   else
01284   {
01285     return HAL_BUSY;
01286   }
01287 }
01288
01289 /**
01290   * @brief  Transmit in master mode an amount of data in no blocking mode with DMA
01291   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01292   *                the configuration information for the specified FMPI2C.
01293   * @param  DevAddress Target device address
01294   * @param  pData Pointer to data buffer
01295   * @param  Size Amount of data to be sent
01296   * @retval HAL status
01297   */
01298 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01299 {
01300   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01301   {
01302     if((pData == NULL) || (Size == 0U))
01303     {
01304       return  HAL_ERROR;
01305     }
01306
01307     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
01308     {
01309       return HAL_BUSY;
01310     }
01311
01312     /* Process Locked */
01313     __HAL_LOCK(hfmpi2c);
01314
01315     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
01316     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
01317     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
01318
01319     hfmpi2c->pBuffPtr = pData;
01320     hfmpi2c->XferCount = Size;
01321     if(Size > MAX_NBYTE_SIZE)
01322     {
01323       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
01324     }
01325     else
01326     {
01327       hfmpi2c->XferSize = Size;
01328     }
01329
01330     /* Set the FMPI2C DMA transfer complete callback */
01331     hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
01332
01333     /* Set the DMA error callback */
01334     hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
01335
01336     /* Enable the DMA channel */
01337     HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
01338
01339     /* Send Slave Address */
01340     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01341     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
01342     {
01343       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
01344     }
01345     else
01346     {
01347       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
01348     }
01349
01350     /* Wait until TXIS flag is set */
01351     if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
01352     {
01353       /* Disable Address Acknowledge */
01354       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01355
01356       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01357       {
01358         return HAL_ERROR;
01359       }
01360       else
01361       {
01362         return HAL_TIMEOUT;
01363       }
01364     }
01365
01366     /* Enable DMA Request */
01367     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
01368
01369     /* Process Unlocked */
01370     __HAL_UNLOCK(hfmpi2c);
01371
01372     return HAL_OK;
01373   }
01374   else
01375   {
01376     return HAL_BUSY;
01377   }
01378 }
01379
01380 /**
01381   * @brief  Receive in master mode an amount of data in no blocking mode with DMA
01382   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01383   *                the configuration information for the specified FMPI2C.
01384   * @param  DevAddress Target device address
01385   * @param  pData Pointer to data buffer
01386   * @param  Size Amount of data to be sent
01387   * @retval HAL status
01388   */
01389 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01390 {
01391   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01392   {
01393     if((pData == NULL) || (Size == 0U))
01394     {
01395       return  HAL_ERROR;
01396     }
01397
01398     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
01399     {
01400       return HAL_BUSY;
01401     }
01402
01403     /* Process Locked */
01404     __HAL_LOCK(hfmpi2c);
01405
01406     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
01407     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
01408     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
01409
01410     hfmpi2c->pBuffPtr = pData;
01411     hfmpi2c->XferCount = Size;
01412     if(Size > MAX_NBYTE_SIZE)
01413     {
01414       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
01415     }
01416     else
01417     {
01418       hfmpi2c->XferSize = Size;
01419     }
01420
01421     /* Set the FMPI2C DMA transfer complete callback */
01422     hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
01423
01424     /* Set the DMA error callback */
01425     hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
01426
01427     /* Enable the DMA channel */
01428     HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
01429
01430     /* Send Slave Address */
01431     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01432     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
01433     {
01434       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
01435     }
01436     else
01437     {
01438       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
01439     }
01440
01441     /* Wait until RXNE flag is set */
01442     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
01443     {
01444       return HAL_TIMEOUT;
01445     }
01446
01447
01448     /* Enable DMA Request */
01449     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
01450
01451     /* Process Unlocked */
01452     __HAL_UNLOCK(hfmpi2c);
01453
01454     return HAL_OK;
01455   }
01456   else
01457   {
01458     return HAL_BUSY;
01459   }
01460 }
01461
01462 /**
01463   * @brief  Transmit in slave mode an amount of data in no blocking mode with DMA
01464   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01465   *                the configuration information for the specified FMPI2C.
01466   * @param  pData Pointer to data buffer
01467   * @param  Size Amount of data to be sent
01468   * @retval HAL status
01469   */
01470 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
01471 {
01472   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01473   {
01474     if((pData == NULL) || (Size == 0U))
01475     {
01476       return  HAL_ERROR;
01477     }
01478     /* Process Locked */
01479     __HAL_LOCK(hfmpi2c);
01480
01481     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
01482     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
01483     hfmpi2c->ErrorCode   = HAL_FMPI2C_ERROR_NONE;
01484
01485     hfmpi2c->pBuffPtr = pData;
01486     hfmpi2c->XferCount = Size;
01487     hfmpi2c->XferSize = Size;
01488
01489     /* Set the FMPI2C DMA transfer complete callback */
01490     hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
01491
01492     /* Set the DMA error callback */
01493     hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
01494
01495     /* Enable the DMA channel */
01496     HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
01497
01498     /* Enable Address Acknowledge */
01499     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
01500
01501     /* Wait until ADDR flag is set */
01502     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
01503     {
01504       /* Disable Address Acknowledge */
01505       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01506       return HAL_TIMEOUT;
01507     }
01508
01509     /* Clear ADDR flag */
01510     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
01511
01512     /* If 10bits addressing mode is selected */
01513     if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
01514     {
01515       /* Wait until ADDR flag is set */
01516       if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
01517       {
01518         /* Disable Address Acknowledge */
01519         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01520         return HAL_TIMEOUT;
01521       }
01522
01523       /* Clear ADDR flag */
01524       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
01525     }
01526
01527     /* Wait until DIR flag is set Transmitter mode */
01528     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
01529     {
01530       /* Disable Address Acknowledge */
01531       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01532       return HAL_TIMEOUT;
01533     }
01534
01535     /* Enable DMA Request */
01536     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
01537
01538     /* Process Unlocked */
01539     __HAL_UNLOCK(hfmpi2c);
01540
01541     return HAL_OK;
01542   }
01543   else
01544   {
01545     return HAL_BUSY;
01546   }
01547 }
01548
01549 /**
01550   * @brief  Receive in slave mode an amount of data in no blocking mode with DMA
01551   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01552   *                the configuration information for the specified FMPI2C.
01553   * @param  pData Pointer to data buffer
01554   * @param  Size Amount of data to be sent
01555   * @retval HAL status
01556   */
01557 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
01558 {
01559   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01560   {
01561     if((pData == NULL) || (Size == 0U))
01562     {
01563       return  HAL_ERROR;
01564     }
01565     /* Process Locked */
01566     __HAL_LOCK(hfmpi2c);
01567
01568     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
01569     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
01570     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
01571
01572     hfmpi2c->pBuffPtr = pData;
01573     hfmpi2c->XferSize = Size;
01574     hfmpi2c->XferCount = Size;
01575
01576     /* Set the FMPI2C DMA transfer complete callback */
01577     hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
01578
01579     /* Set the DMA error callback */
01580     hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
01581
01582     /* Enable the DMA channel */
01583     HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, Size);
01584
01585     /* Enable Address Acknowledge */
01586     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
01587
01588     /* Wait until ADDR flag is set */
01589     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, FMPI2C_TIMEOUT_ADDR) != HAL_OK)
01590     {
01591       /* Disable Address Acknowledge */
01592       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01593       return HAL_TIMEOUT;
01594     }
01595
01596     /* Clear ADDR flag */
01597     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
01598
01599     /* Wait until DIR flag is set Receiver mode */
01600     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, FMPI2C_TIMEOUT_DIR) != HAL_OK)
01601     {
01602       /* Disable Address Acknowledge */
01603       hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
01604       return HAL_TIMEOUT;
01605     }
01606
01607     /* Enable DMA Request */
01608     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
01609
01610     /* Process Unlocked */
01611     __HAL_UNLOCK(hfmpi2c);
01612
01613     return HAL_OK;
01614   }
01615   else
01616   {
01617     return HAL_BUSY;
01618   }
01619 }
01620
01621 /**
01622   * @brief  Write an amount of data in blocking mode to a specific memory address
01623   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01624   *                the configuration information for the specified FMPI2C.
01625   * @param  DevAddress Target device address
01626   * @param  MemAddress Internal memory address
01627   * @param  MemAddSize Size of internal memory address
01628   * @param  pData Pointer to data buffer
01629   * @param  Size Amount of data to be sent
01630   * @param  Timeout Timeout duration
01631   * @retval HAL status
01632   */
01633 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01634 {
01635   uint32_t Sizetmp = 0U;
01636
01637   /* Check the parameters */
01638   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
01639
01640   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01641   {
01642     if((pData == NULL) || (Size == 0U))
01643     {
01644       return  HAL_ERROR;
01645     }
01646
01647     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
01648     {
01649       return HAL_BUSY;
01650     }
01651
01652     /* Process Locked */
01653     __HAL_LOCK(hfmpi2c);
01654
01655     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
01656     hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
01657     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
01658
01659     /* Send Slave Address and Memory Address */
01660     if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
01661     {
01662       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01663       {
01664         /* Process Unlocked */
01665         __HAL_UNLOCK(hfmpi2c);
01666         return HAL_ERROR;
01667       }
01668       else
01669       {
01670         /* Process Unlocked */
01671         __HAL_UNLOCK(hfmpi2c);
01672         return HAL_TIMEOUT;
01673       }
01674     }
01675
01676     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
01677     /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
01678     if(Size > MAX_NBYTE_SIZE)
01679     {
01680       FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
01681       Sizetmp = MAX_NBYTE_SIZE;
01682     }
01683     else
01684     {
01685       FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
01686       Sizetmp = Size;
01687     }
01688
01689     do
01690     {
01691       /* Wait until TXIS flag is set */
01692       if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
01693       {
01694         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01695         {
01696           return HAL_ERROR;
01697         }
01698         else
01699         {
01700           return HAL_TIMEOUT;
01701         }
01702       }
01703
01704       /* Write data to DR */
01705       hfmpi2c->Instance->TXDR = (*pData++);
01706       Sizetmp--;
01707       Size--;
01708
01709       if((Sizetmp == 0U)&&(Size!=0U))
01710       {
01711         /* Wait until TCR flag is set */
01712         if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
01713         {
01714           return HAL_TIMEOUT;
01715         }
01716
01717         if(Size > MAX_NBYTE_SIZE)
01718         {
01719           FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
01720           Sizetmp = MAX_NBYTE_SIZE;
01721         }
01722         else
01723         {
01724           FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
01725           Sizetmp = Size;
01726         }
01727       }
01728
01729     }while(Size > 0U);
01730
01731     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01732     /* Wait until STOPF flag is reset */
01733     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
01734     {
01735       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01736       {
01737         return HAL_ERROR;
01738       }
01739       else
01740       {
01741         return HAL_TIMEOUT;
01742       }
01743     }
01744
01745     /* Clear STOP Flag */
01746     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
01747
01748     /* Clear Configuration Register 2 */
01749     FMPI2C_RESET_CR2(hfmpi2c);
01750
01751     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
01752     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
01753
01754     /* Process Unlocked */
01755     __HAL_UNLOCK(hfmpi2c);
01756
01757     return HAL_OK;
01758   }
01759   else
01760   {
01761     return HAL_BUSY;
01762   }
01763 }
01764
01765 /**
01766   * @brief  Read an amount of data in blocking mode from a specific memory address
01767   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01768   *                the configuration information for the specified FMPI2C.
01769   * @param  DevAddress Target device address
01770   * @param  MemAddress Internal memory address
01771   * @param  MemAddSize Size of internal memory address
01772   * @param  pData Pointer to data buffer
01773   * @param  Size Amount of data to be sent
01774   * @param  Timeout Timeout duration
01775   * @retval HAL status
01776   */
01777 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01778 {
01779   uint32_t Sizetmp = 0U;
01780
01781   /* Check the parameters */
01782   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
01783
01784   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01785   {
01786     if((pData == NULL) || (Size == 0U))
01787     {
01788       return  HAL_ERROR;
01789     }
01790
01791     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
01792     {
01793       return HAL_BUSY;
01794     }
01795
01796     /* Process Locked */
01797     __HAL_LOCK(hfmpi2c);
01798
01799     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
01800     hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
01801     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
01802
01803     /* Send Slave Address and Memory Address */
01804     if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
01805     {
01806       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01807       {
01808         /* Process Unlocked */
01809         __HAL_UNLOCK(hfmpi2c);
01810         return HAL_ERROR;
01811       }
01812       else
01813       {
01814         /* Process Unlocked */
01815         __HAL_UNLOCK(hfmpi2c);
01816         return HAL_TIMEOUT;
01817       }
01818     }
01819
01820     /* Send Slave Address */
01821     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01822     /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
01823     if(Size > MAX_NBYTE_SIZE)
01824     {
01825       FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
01826       Sizetmp = MAX_NBYTE_SIZE;
01827     }
01828     else
01829     {
01830       FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
01831       Sizetmp = Size;
01832     }
01833
01834     do
01835     {
01836       /* Wait until RXNE flag is set */
01837       if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
01838       {
01839         return HAL_TIMEOUT;
01840       }
01841
01842       /* Read data from RXDR */
01843       (*pData++) = hfmpi2c->Instance->RXDR;
01844
01845       /* Decrement the Size counter */
01846       Sizetmp--;
01847       Size--;
01848
01849       if((Sizetmp == 0U)&&(Size!=0U))
01850       {
01851         /* Wait until TCR flag is set */
01852         if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
01853         {
01854           return HAL_TIMEOUT;
01855         }
01856
01857         if(Size > MAX_NBYTE_SIZE)
01858         {
01859           FMPI2C_TransferConfig(hfmpi2c,DevAddress,MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
01860           Sizetmp = MAX_NBYTE_SIZE;
01861         }
01862         else
01863         {
01864           FMPI2C_TransferConfig(hfmpi2c,DevAddress,Size, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
01865           Sizetmp = Size;
01866         }
01867       }
01868
01869     }while(Size > 0U);
01870
01871     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01872     /* Wait until STOPF flag is reset */
01873     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
01874     {
01875       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01876       {
01877         return HAL_ERROR;
01878       }
01879       else
01880       {
01881         return HAL_TIMEOUT;
01882       }
01883     }
01884
01885     /* Clear STOP Flag */
01886     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
01887
01888     /* Clear Configuration Register 2 */
01889     FMPI2C_RESET_CR2(hfmpi2c);
01890
01891     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
01892     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
01893
01894     /* Process Unlocked */
01895     __HAL_UNLOCK(hfmpi2c);
01896
01897     return HAL_OK;
01898   }
01899   else
01900   {
01901     return HAL_BUSY;
01902   }
01903 }
01904
01905 /**
01906   * @brief  Write an amount of data in no blocking mode with Interrupt to a specific memory address
01907   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
01908   *                the configuration information for the specified FMPI2C.
01909   * @param  DevAddress Target device address
01910   * @param  MemAddress Internal memory address
01911   * @param  MemAddSize Size of internal memory address
01912   * @param  pData Pointer to data buffer
01913   * @param  Size Amount of data to be sent
01914   * @retval HAL status
01915   */
01916 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
01917 {
01918   /* Check the parameters */
01919   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
01920
01921   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
01922   {
01923     if((pData == NULL) || (Size == 0U))
01924     {
01925       return  HAL_ERROR;
01926     }
01927
01928     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
01929     {
01930       return HAL_BUSY;
01931     }
01932
01933     /* Process Locked */
01934     __HAL_LOCK(hfmpi2c);
01935
01936     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
01937     hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
01938     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
01939     hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
01940
01941     hfmpi2c->pBuffPtr = pData;
01942     hfmpi2c->XferCount = Size;
01943     if(Size > MAX_NBYTE_SIZE)
01944     {
01945       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
01946     }
01947     else
01948     {
01949       hfmpi2c->XferSize = Size;
01950     }
01951
01952     /* Send Slave Address and Memory Address */
01953     if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
01954     {
01955       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
01956       {
01957         /* Process Unlocked */
01958         __HAL_UNLOCK(hfmpi2c);
01959         return HAL_ERROR;
01960       }
01961       else
01962       {
01963         /* Process Unlocked */
01964         __HAL_UNLOCK(hfmpi2c);
01965         return HAL_TIMEOUT;
01966       }
01967     }
01968
01969     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
01970     /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
01971     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
01972     {
01973       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
01974     }
01975     else
01976     {
01977       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
01978     }
01979
01980     /* Process Unlocked */
01981     __HAL_UNLOCK(hfmpi2c);
01982
01983     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
01984               to avoid the risk of FMPI2C interrupt handle execution before current
01985               process unlock */
01986
01987     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01988     /* possible to enable all of these */
01989     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
01990     __HAL_FMPI2C_ENABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI );
01991
01992     return HAL_OK;
01993   }
01994   else
01995   {
01996     return HAL_BUSY;
01997   }
01998 }
01999
02000 /**
02001   * @brief  Read an amount of data in no blocking mode with Interrupt from a specific memory address
02002   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02003   *                the configuration information for the specified FMPI2C.
02004   * @param  DevAddress Target device address
02005   * @param  MemAddress Internal memory address
02006   * @param  MemAddSize Size of internal memory address
02007   * @param  pData Pointer to data buffer
02008   * @param  Size Amount of data to be sent
02009   * @retval HAL status
02010   */
02011 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02012 {
02013   /* Check the parameters */
02014   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
02015
02016   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
02017   {
02018     if((pData == NULL) || (Size == 0U))
02019     {
02020       return  HAL_ERROR;
02021     }
02022
02023     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
02024     {
02025       return HAL_BUSY;
02026     }
02027
02028     /* Process Locked */
02029     __HAL_LOCK(hfmpi2c);
02030
02031     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
02032     hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
02033     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02034     hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
02035
02036     hfmpi2c->pBuffPtr = pData;
02037     hfmpi2c->XferCount = Size;
02038     if(Size > MAX_NBYTE_SIZE)
02039     {
02040       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
02041     }
02042     else
02043     {
02044       hfmpi2c->XferSize = Size;
02045     }
02046
02047     /* Send Slave Address and Memory Address */
02048     if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
02049     {
02050       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
02051       {
02052         /* Process Unlocked */
02053         __HAL_UNLOCK(hfmpi2c);
02054         return HAL_ERROR;
02055       }
02056       else
02057       {
02058         /* Process Unlocked */
02059         __HAL_UNLOCK(hfmpi2c);
02060         return HAL_TIMEOUT;
02061       }
02062     }
02063
02064     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
02065     /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */
02066     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
02067     {
02068       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
02069     }
02070     else
02071     {
02072       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
02073     }
02074
02075     /* Process Unlocked */
02076     __HAL_UNLOCK(hfmpi2c);
02077
02078     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
02079               to avoid the risk of FMPI2C interrupt handle execution before current
02080               process unlock */
02081
02082     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02083     /* possible to enable all of these */
02084     /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
02085     __HAL_FMPI2C_ENABLE_IT(hfmpi2c, FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI );
02086
02087     return HAL_OK;
02088   }
02089   else
02090   {
02091     return HAL_BUSY;
02092   }
02093 }
02094
02095 /**
02096   * @brief  Write an amount of data in no blocking mode with DMA to a specific memory address
02097   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02098   *                the configuration information for the specified FMPI2C.
02099   * @param  DevAddress Target device address
02100   * @param  MemAddress Internal memory address
02101   * @param  MemAddSize Size of internal memory address
02102   * @param  pData Pointer to data buffer
02103   * @param  Size Amount of data to be sent
02104   * @retval HAL status
02105   */
02106 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02107 {
02108   /* Check the parameters */
02109   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
02110
02111   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
02112   {
02113     if((pData == NULL) || (Size == 0U))
02114     {
02115       return  HAL_ERROR;
02116     }
02117
02118     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
02119     {
02120       return HAL_BUSY;
02121     }
02122
02123     /* Process Locked */
02124     __HAL_LOCK(hfmpi2c);
02125
02126     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
02127     hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
02128     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02129
02130     hfmpi2c->pBuffPtr = pData;
02131     hfmpi2c->XferCount = Size;
02132     if(Size > MAX_NBYTE_SIZE)
02133     {
02134       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
02135     }
02136     else
02137     {
02138       hfmpi2c->XferSize = Size;
02139     }
02140
02141     /* Set the FMPI2C DMA transfer complete callback */
02142     hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMemTransmitCplt;
02143
02144     /* Set the DMA error callback */
02145     hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
02146
02147     /* Enable the DMA channel */
02148     HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
02149
02150     /* Send Slave Address and Memory Address */
02151     if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
02152     {
02153       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
02154       {
02155         /* Process Unlocked */
02156         __HAL_UNLOCK(hfmpi2c);
02157         return HAL_ERROR;
02158       }
02159       else
02160       {
02161         /* Process Unlocked */
02162         __HAL_UNLOCK(hfmpi2c);
02163         return HAL_TIMEOUT;
02164       }
02165     }
02166
02167     /* Send Slave Address */
02168     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
02169     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
02170     {
02171       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
02172     }
02173     else
02174     {
02175       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
02176     }
02177
02178     /* Wait until TXIS flag is set */
02179     if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
02180     {
02181       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
02182       {
02183         return HAL_ERROR;
02184       }
02185       else
02186       {
02187         return HAL_TIMEOUT;
02188       }
02189     }
02190
02191     /* Enable DMA Request */
02192     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
02193
02194     /* Process Unlocked */
02195     __HAL_UNLOCK(hfmpi2c);
02196
02197     return HAL_OK;
02198   }
02199   else
02200   {
02201     return HAL_BUSY;
02202   }
02203 }
02204
02205 /**
02206   * @brief  Reads an amount of data in no blocking mode with DMA from a specific memory address.
02207   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02208   *                the configuration information for the specified FMPI2C.
02209   * @param  DevAddress Target device address
02210   * @param  MemAddress Internal memory address
02211   * @param  MemAddSize Size of internal memory address
02212   * @param  pData Pointer to data buffer
02213   * @param  Size Amount of data to be read
02214   * @retval HAL status
02215   */
02216 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02217 {
02218   /* Check the parameters */
02219   assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
02220
02221   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
02222   {
02223     if((pData == NULL) || (Size == 0U))
02224     {
02225       return  HAL_ERROR;
02226     }
02227
02228     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
02229     {
02230       return HAL_BUSY;
02231     }
02232
02233     /* Process Locked */
02234     __HAL_LOCK(hfmpi2c);
02235
02236     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
02237     hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM;
02238
02239     hfmpi2c->pBuffPtr = pData;
02240     hfmpi2c->XferCount = Size;
02241     if(Size > MAX_NBYTE_SIZE)
02242     {
02243       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
02244     }
02245     else
02246     {
02247       hfmpi2c->XferSize = Size;
02248     }
02249
02250     /* Set the FMPI2C DMA transfer complete callback */
02251     hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMemReceiveCplt;
02252
02253     /* Set the DMA error callback */
02254     hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
02255
02256     /* Enable the DMA channel */
02257     HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
02258
02259     /* Send Slave Address and Memory Address */
02260     if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG) != HAL_OK)
02261     {
02262       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
02263       {
02264         /* Process Unlocked */
02265         __HAL_UNLOCK(hfmpi2c);
02266         return HAL_ERROR;
02267       }
02268       else
02269       {
02270         /* Process Unlocked */
02271         __HAL_UNLOCK(hfmpi2c);
02272         return HAL_TIMEOUT;
02273       }
02274     }
02275
02276     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
02277     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
02278     {
02279       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
02280     }
02281     else
02282     {
02283       FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
02284     }
02285
02286     /* Wait until RXNE flag is set */
02287     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
02288     {
02289       return HAL_TIMEOUT;
02290     }
02291
02292     /* Enable DMA Request */
02293     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
02294
02295     /* Process Unlocked */
02296     __HAL_UNLOCK(hfmpi2c);
02297
02298     return HAL_OK;
02299   }
02300   else
02301   {
02302     return HAL_BUSY;
02303   }
02304 }
02305
02306 /**
02307   * @brief  Checks if target device is ready for communication.
02308   * @note   This function is used with Memory devices
02309   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02310   *                the configuration information for the specified FMPI2C.
02311   * @param  DevAddress Target device address
02312   * @param  Trials Number of trials
02313   * @param  Timeout Timeout duration
02314   * @retval HAL status
02315   */
02316 HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
02317 {
02318   uint32_t tickstart = 0U;
02319
02320   __IO uint32_t FMPI2C_Trials = 0U;
02321
02322   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
02323   {
02324     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
02325     {
02326       return HAL_BUSY;
02327     }
02328
02329     /* Process Locked */
02330     __HAL_LOCK(hfmpi2c);
02331
02332     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
02333     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02334
02335     do
02336     {
02337       /* Generate Start */
02338       hfmpi2c->Instance->CR2 = FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode,DevAddress);
02339
02340       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02341       /* Wait until STOPF flag is set or a NACK flag is set*/
02342       tickstart = HAL_GetTick();
02343       while((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
02344       {
02345         if(Timeout != HAL_MAX_DELAY)
02346         {
02347           if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
02348           {
02349             /* Device is ready */
02350             hfmpi2c->State = HAL_FMPI2C_STATE_READY;
02351             /* Process Unlocked */
02352             __HAL_UNLOCK(hfmpi2c);
02353             return HAL_TIMEOUT;
02354           }
02355         }
02356       }
02357
02358       /* Check if the NACKF flag has not been set */
02359       if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET)
02360       {
02361         /* Wait until STOPF flag is reset */
02362         if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
02363         {
02364           return HAL_TIMEOUT;
02365         }
02366
02367         /* Clear STOP Flag */
02368         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
02369
02370         /* Device is ready */
02371         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
02372
02373         /* Process Unlocked */
02374         __HAL_UNLOCK(hfmpi2c);
02375
02376         return HAL_OK;
02377       }
02378       else
02379       {
02380         /* Wait until STOPF flag is reset */
02381         if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
02382         {
02383           return HAL_TIMEOUT;
02384         }
02385
02386         /* Clear NACK Flag */
02387         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
02388
02389         /* Clear STOP Flag, auto generated with autoend*/
02390         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
02391       }
02392
02393       /* Check if the maximum allowed number of trials has been reached */
02394       if(FMPI2C_Trials++ == Trials)
02395       {
02396         /* Generate Stop */
02397         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
02398
02399         /* Wait until STOPF flag is reset */
02400         if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
02401         {
02402           return HAL_TIMEOUT;
02403         }
02404
02405         /* Clear STOP Flag */
02406         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
02407       }
02408     }while(FMPI2C_Trials < Trials);
02409
02410     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
02411
02412     /* Process Unlocked */
02413     __HAL_UNLOCK(hfmpi2c);
02414
02415     return HAL_TIMEOUT;
02416   }
02417   else
02418   {
02419     return HAL_BUSY;
02420   }
02421 }
02422
02423 /**
02424   * @brief  Sequential transmit in master FMPI2C mode an amount of data in no blocking mode with Interrupt.
02425   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02426   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02427   *                the configuration information for the specified FMPI2C.
02428   * @param  DevAddress Target device address
02429   * @param  pData Pointer to data buffer
02430   * @param  Size Amount of data to be sent
02431   * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
02432   * @retval HAL status
02433   */
02434 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02435 {
02436   /* Check the parameters */
02437   assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02438
02439   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
02440   {
02441     /* Process Locked */
02442     __HAL_LOCK(hfmpi2c);
02443
02444     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
02445     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
02446     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02447
02448     /* Prepare transfer parameters */
02449     hfmpi2c->pBuffPtr = pData;
02450     hfmpi2c->XferCount = Size;
02451     hfmpi2c->XferOptions = XferOptions;
02452
02453     if(Size > MAX_NBYTE_SIZE)
02454     {
02455       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
02456     }
02457     else
02458     {
02459       hfmpi2c->XferSize = Size;
02460     }
02461
02462     /* Send Slave Address */
02463     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
02464     if((hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount))
02465     {
02466       FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
02467     }
02468     else
02469     {
02470       /* If transfer direction not change, do not generate Restart Condition */
02471       /* Mean Previous state is same as current state */
02472       if(hfmpi2c->PreviousState == FMPI2C_STATE_SLAVE_BUSY_TX)
02473       {
02474         FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
02475       }
02476       /* Else transfer direction change, so generate Restart with new transfer direction */
02477       else
02478       {
02479         FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_GENERATE_START_WRITE);
02480       }
02481     }
02482
02483     /* Process Unlocked */
02484     __HAL_UNLOCK(hfmpi2c);
02485
02486     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
02487               to avoid the risk of FMPI2C interrupt handle execution before current
02488               process unlock */
02489     FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_TX);
02490
02491     return HAL_OK;
02492   }
02493   else
02494   {
02495     return HAL_BUSY;
02496   }
02497 }
02498
02499 /**
02500   * @brief  Sequential receive in master FMPI2C mode an amount of data in no blocking mode with Interrupt
02501   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02502   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02503   *                the configuration information for the specified FMPI2C.
02504   * @param  DevAddress Target device address
02505   * @param  pData Pointer to data buffer
02506   * @param  Size Amount of data to be sent
02507   * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
02508   * @retval HAL status
02509   */
02510 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02511 {
02512   /* Check the parameters */
02513   assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02514
02515   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
02516   {
02517     /* Process Locked */
02518     __HAL_LOCK(hfmpi2c);
02519
02520     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
02521     hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
02522     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02523
02524     /* Prepare transfer parameters */
02525     hfmpi2c->pBuffPtr = pData;
02526     hfmpi2c->XferCount = Size;
02527     hfmpi2c->XferOptions = XferOptions;
02528
02529     if(Size > MAX_NBYTE_SIZE)
02530     {
02531       hfmpi2c->XferSize = MAX_NBYTE_SIZE;
02532     }
02533     else
02534     {
02535       hfmpi2c->XferSize = Size;
02536     }
02537
02538     /* Send Slave Address */
02539     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
02540     if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
02541     {
02542       FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
02543     }
02544     else
02545     {
02546       /* If transfer direction not change, do not generate Restart Condition */
02547       /* Mean Previous state is same as current state */
02548       if(hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX)
02549       {
02550         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
02551       }
02552       /* Else transfer direction change, so generate Restart with new transfer direction */
02553       else
02554       {
02555         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_GENERATE_START_READ);
02556       }
02557     }
02558
02559     /* Process Unlocked */
02560     __HAL_UNLOCK(hfmpi2c);
02561
02562     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
02563               to avoid the risk of FMPI2C interrupt handle execution before current
02564               process unlock */
02565     FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_RX);
02566
02567     return HAL_OK;
02568   }
02569   else
02570   {
02571     return HAL_BUSY;
02572   }
02573 }
02574
02575 /**
02576   * @brief  Sequential transmit in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt
02577   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02578   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02579   *                the configuration information for the specified FMPI2C.
02580   * @param  pData Pointer to data buffer
02581   * @param  Size Amount of data to be sent
02582   * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
02583   * @retval HAL status
02584   */
02585 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02586 {
02587   /* Check the parameters */
02588   assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02589
02590   if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
02591   {
02592     if((pData == NULL) || (Size == 0U))
02593     {
02594       return  HAL_ERROR;
02595     }
02596
02597     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02598     FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR | FMPI2C_IT_TX);
02599
02600     /* Process Locked */
02601     __HAL_LOCK(hfmpi2c);
02602
02603     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
02604     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
02605     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02606
02607     /* Enable Address Acknowledge */
02608     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
02609
02610     /* Prepare transfer parameters */
02611     hfmpi2c->pBuffPtr = pData;
02612     hfmpi2c->XferSize = Size;
02613     hfmpi2c->XferCount = Size;
02614     hfmpi2c->XferOptions = XferOptions;
02615
02616     /* Clear ADDR flag after prepare the transfer parameters */
02617     /* This action will generate an acknowledge to the Master */
02618     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
02619
02620     /* Process Unlocked */
02621     __HAL_UNLOCK(hfmpi2c);
02622
02623     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
02624     to avoid the risk of FMPI2C interrupt handle execution before current
02625     process unlock */
02626     /* REnable ADDR interrupt */
02627     FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_TX | FMPI2C_IT_ADDR);
02628
02629     return HAL_OK;
02630   }
02631   else
02632   {
02633     return HAL_ERROR;
02634   }
02635 }
02636
02637 /**
02638   * @brief  Sequential receive in slave/device FMPI2C mode an amount of data in no blocking mode with Interrupt
02639   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02640   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02641   *                the configuration information for the specified FMPI2C.
02642   * @param  pData Pointer to data buffer
02643   * @param  Size Amount of data to be sent
02644   * @param  XferOptions Options of Transfer, value of @ref FMPI2C_XferOptions_definition
02645   * @retval HAL status
02646   */
02647 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02648 {
02649   /* Check the parameters */
02650   assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02651
02652   if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
02653   {
02654     if((pData == NULL) || (Size == 0U))
02655     {
02656       return  HAL_ERROR;
02657     }
02658
02659     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02660     FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR | FMPI2C_IT_RX);
02661
02662     /* Process Locked */
02663     __HAL_LOCK(hfmpi2c);
02664
02665     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX_LISTEN;
02666     hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
02667     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02668
02669     /* Enable Address Acknowledge */
02670     hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
02671
02672     /* Prepare transfer parameters */
02673     hfmpi2c->pBuffPtr = pData;
02674     hfmpi2c->XferSize = Size;
02675     hfmpi2c->XferCount = Size;
02676     hfmpi2c->XferOptions = XferOptions;
02677
02678     /* Clear ADDR flag after prepare the transfer parameters */
02679     /* This action will generate an acknowledge to the Master */
02680     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
02681
02682     /* Process Unlocked */
02683     __HAL_UNLOCK(hfmpi2c);
02684
02685     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
02686     to avoid the risk of FMPI2C interrupt handle execution before current
02687     process unlock */
02688     /* REnable ADDR interrupt */
02689     FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_RX | FMPI2C_IT_ADDR);
02690
02691     return HAL_OK;
02692   }
02693   else
02694   {
02695     return HAL_ERROR;
02696   }
02697 }
02698
02699 /**
02700   * @brief  Enable the Address listen mode with Interrupt.
02701   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02702   *                the configuration information for the specified FMPI2C.
02703   * @retval HAL status
02704   */
02705 HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
02706 {
02707   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
02708   {
02709     hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
02710
02711     /* Enable the Address Match interrupt */
02712     FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_ADDR);
02713
02714     return HAL_OK;
02715   }
02716   else
02717   {
02718     return HAL_BUSY;
02719   }
02720 }
02721
02722 /**
02723   * @brief  Disable the Address listen mode with Interrupt.
02724   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02725   *                the configuration information for the specified FMPI2C
02726   * @retval HAL status
02727   */
02728 HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
02729 {
02730   /* Declaration of tmp to prevent undefined behavior of volatile usage */
02731   uint32_t tmp;
02732
02733   /* Disable Address listen mode only if a transfer is not ongoing */
02734   if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
02735   {
02736     tmp = (uint32_t)(hfmpi2c->State) & FMPI2C_STATE_MSK;
02737     hfmpi2c->PreviousState = tmp | (uint32_t)(hfmpi2c->Mode);
02738     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
02739     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
02740
02741     /* Disable the Address Match interrupt */
02742     FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR);
02743
02744     return HAL_OK;
02745   }
02746   else
02747   {
02748     return HAL_BUSY;
02749   }
02750 }
02751
02752 /**
02753   * @brief  Abort a master/host FMPI2C process communication with Interrupt.
02754   * @note   This abort can be called only if state is ready
02755   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02756   *                the configuration information for the specified FMPI2C.
02757   * @param  DevAddress Target device address
02758   * @retval HAL status
02759   */
02760 HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress)
02761 {
02762   if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || \
02763      ((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) && ((hfmpi2c->PreviousState & ((uint32_t)HAL_FMPI2C_MODE_MASTER)) == HAL_FMPI2C_MODE_MASTER)))
02764   {
02765     /* Process Locked */
02766     __HAL_LOCK(hfmpi2c);
02767
02768     /* Keep the same state as previous */
02769     /* to perform as well the call of the corresponding end of transfer callback */
02770     if((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE))
02771     {
02772       hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
02773       hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
02774     }
02775     else if((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE))
02776     {
02777       hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
02778       hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
02779     }
02780
02781     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
02782
02783     /* Set NBYTES to 1 to generate a dummy read on FMPI2C peripheral */
02784     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
02785     FMPI2C_TransferConfig(hfmpi2c, DevAddress, 1U, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_STOP);
02786
02787     /* Process Unlocked */
02788     __HAL_UNLOCK(hfmpi2c);
02789
02790     /* Note : The FMPI2C interrupts must be enabled after unlocking current process
02791               to avoid the risk of FMPI2C interrupt handle execution before current
02792               process unlock */
02793     if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) && (hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
02794     {
02795       FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_TX);
02796     }
02797     if((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) && (hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
02798     {
02799       FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_IT_RX);
02800     }
02801
02802     return HAL_OK;
02803   }
02804   else
02805   {
02806     /* Wrong usage of abort function */
02807     /* This function should be used only in case of abort monitored by master device */
02808     return HAL_ERROR;
02809   }
02810 }
02811
02812 /**
02813   * @}
02814   */
02815
02816 /** @defgroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
02817   * @{
02818   */
02819
02820 /**
02821   * @brief  This function handles FMPI2C event interrupt request.
02822   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02823   *                the configuration information for the specified FMPI2C.
02824   * @retval None
02825   */
02826 void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
02827 {
02828   uint32_t tmpisrvalue = 0U;
02829
02830   /* Use a local variable to store the current ISR flags */
02831   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
02832   tmpisrvalue = FMPI2C_GET_ISR_REG(hfmpi2c);
02833
02834   /* FMPI2C in mode Transmitter ---------------------------------------------------*/
02835   if(((FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TXIS) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TCR) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TC) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_STOPF) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_AF) != RESET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_TXI)) != RESET))
02836   {
02837     /* Slave mode selected */
02838     if(hfmpi2c->Mode  == HAL_FMPI2C_MODE_SLAVE)
02839     {
02840       FMPI2C_Slave_ISR(hfmpi2c);
02841     }
02842     /* Master or Memory mode selected */
02843     if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM))
02844     {
02845       FMPI2C_Master_ISR(hfmpi2c);
02846     }
02847   }
02848
02849   /* FMPI2C in mode Receiver ----------------------------------------------------*/
02850   if(((FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_RXNE) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TCR) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_TC) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_STOPF) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_AF) != RESET)) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, (FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_RXI)) != RESET))
02851   {
02852     /* Slave mode selected */
02853     if(hfmpi2c->Mode  == HAL_FMPI2C_MODE_SLAVE)
02854     {
02855       FMPI2C_Slave_ISR(hfmpi2c);
02856     }
02857     /* Master or Memory mode selected */
02858     if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM))
02859     {
02860       FMPI2C_Master_ISR(hfmpi2c);
02861     }
02862   }
02863
02864    /* FMPI2C in mode Listener Only --------------------------------------------------*/
02865   if(((FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_ADDR) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_STOPF) != RESET) || (FMPI2C_CHECK_FLAG(tmpisrvalue, FMPI2C_FLAG_AF) != RESET)) && ((__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ADDRI) != RESET) || (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_STOPI) != RESET) || (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_NACKI) != RESET)))
02866   {
02867     if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
02868     {
02869       if((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) || (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) || (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
02870       {
02871         FMPI2C_Slave_ISR(hfmpi2c);
02872       }
02873     }
02874     else
02875     {
02876       if(hfmpi2c->Mode == HAL_FMPI2C_MODE_SLAVE)
02877       {
02878         FMPI2C_Slave_ISR(hfmpi2c);
02879       }
02880     }
02881   }
02882 }
02883
02884 /**
02885   * @brief  This function handles FMPI2C error interrupt request.
02886   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02887   *                the configuration information for the specified FMPI2C.
02888   * @retval None
02889   */
02890 void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
02891 {
02892   /* FMPI2C Bus error interrupt occurred ------------------------------------*/
02893   if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BERR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
02894   {
02895     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR;
02896
02897     /* Clear BERR flag */
02898     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_BERR);
02899   }
02900
02901   /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02902   if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_OVR) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
02903   {
02904     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR;
02905
02906     /* Clear OVR flag */
02907     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_OVR);
02908   }
02909
02910   /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/
02911   if((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO) == SET) && (__HAL_FMPI2C_GET_IT_SOURCE(hfmpi2c, FMPI2C_IT_ERRI) == SET))
02912   {
02913     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO;
02914
02915     /* Clear ARLO flag */
02916     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO);
02917   }
02918
02919   /* Call the Error Callback in case of Error detected */
02920   if((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) !=  HAL_FMPI2C_ERROR_NONE)
02921   {
02922     if(((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) || (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)) && (hfmpi2c->Mode == HAL_FMPI2C_MODE_SLAVE))
02923     {
02924       /* Reset only HAL_FMPI2C_STATE_SLAVE_BUSY_XX */
02925       /* keep HAL_FMPI2C_STATE_LISTEN if set */
02926       hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
02927       hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
02928     }
02929     else
02930     {
02931       hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
02932       hfmpi2c->State = HAL_FMPI2C_STATE_READY;
02933     }
02934
02935     HAL_FMPI2C_ErrorCallback(hfmpi2c);
02936   }
02937 }
02938
02939 /**
02940   * @brief  Master Tx Transfer completed callback.
02941   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02942   *                the configuration information for the specified FMPI2C.
02943   * @retval None
02944   */
02945  __weak void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
02946 {
02947   /* Prevent unused argument(s) compilation warning */
02948   UNUSED(hfmpi2c);
02949   /* NOTE : This function should not be modified, when the callback is needed,
02950             the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
02951    */
02952 }
02953
02954 /**
02955   * @brief  Master Rx Transfer completed callback.
02956   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02957   *                the configuration information for the specified FMPI2C.
02958   * @retval None
02959   */
02960 __weak void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
02961 {
02962   /* Prevent unused argument(s) compilation warning */
02963   UNUSED(hfmpi2c);
02964   /* NOTE : This function Should not be modified, when the callback is needed,
02965             the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
02966    */
02967 }
02968
02969 /** @brief  Slave Tx Transfer completed callback.
02970   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02971   *                the configuration information for the specified FMPI2C.
02972   * @retval None
02973   */
02974  __weak void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
02975 {
02976   /* Prevent unused argument(s) compilation warning */
02977   UNUSED(hfmpi2c);
02978   /* NOTE : This function Should not be modified, when the callback is needed,
02979             the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
02980    */
02981 }
02982
02983 /**
02984   * @brief  Slave Rx Transfer completed callback.
02985   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
02986   *                the configuration information for the specified FMPI2C.
02987   * @retval None
02988   */
02989 __weak void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
02990 {
02991   /* Prevent unused argument(s) compilation warning */
02992   UNUSED(hfmpi2c);
02993   /* NOTE : This function Should not be modified, when the callback is needed,
02994             the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
02995    */
02996 }
02997
02998 /**
02999   * @brief  Slave Address Match callback.
03000   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03001   *                the configuration information for the specified FMPI2C.
03002   * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XferOptions_definition
03003   * @param  AddrMatchCode: Address Match Code
03004   * @retval None
03005   */
03006 __weak void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
03007 {
03008   /* Prevent unused argument(s) compilation warning */
03009   UNUSED(hfmpi2c);
03010   UNUSED(TransferDirection);
03011   UNUSED(AddrMatchCode);
03012   /* NOTE : This function should not be modified, when the callback is needed,
03013             the HAL_FMPI2C_AddrCallback() could be implemented in the user file
03014    */
03015 }
03016
03017 /**
03018   * @brief  Listen Complete callback.
03019   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03020   *                the configuration information for the specified FMPI2C.
03021   * @retval None
03022   */
03023 __weak void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
03024 {
03025   /* Prevent unused argument(s) compilation warning */
03026   UNUSED(hfmpi2c);
03027   /* NOTE : This function should not be modified, when the callback is needed,
03028             the HAL_FMPI2C_ListenCpltCallback() could be implemented in the user file
03029    */
03030 }
03031
03032 /**
03033   * @brief  Memory Tx Transfer completed callback.
03034   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03035   *                the configuration information for the specified FMPI2C.
03036   * @retval None
03037   */
03038  __weak void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
03039 {
03040   /* Prevent unused argument(s) compilation warning */
03041   UNUSED(hfmpi2c);
03042   /* NOTE : This function should not be modified, when the callback is needed,
03043             the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
03044    */
03045 }
03046
03047 /**
03048   * @brief  Memory Rx Transfer completed callback.
03049   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03050   *                the configuration information for the specified FMPI2C.
03051   * @retval None
03052   */
03053 __weak void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c)
03054 {
03055   /* Prevent unused argument(s) compilation warning */
03056   UNUSED(hfmpi2c);
03057   /* NOTE : This function Should not be modified, when the callback is needed,
03058             the HAL_FMPI2C_TxCpltCallback could be implemented in the user file
03059    */
03060 }
03061
03062 /**
03063   * @brief  FMPI2C error callback.
03064   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03065   *                the configuration information for the specified FMPI2C.
03066   * @retval None
03067   */
03068  __weak void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c)
03069 {
03070   /* Prevent unused argument(s) compilation warning */
03071   UNUSED(hfmpi2c);
03072   /* NOTE : This function Should not be modified, when the callback is needed,
03073             the HAL_FMPI2C_ErrorCallback could be implemented in the user file
03074    */
03075 }
03076
03077 /**
03078   * @}
03079   */
03080
03081 /** @defgroup FMPI2C_Exported_Functions_Group3 Peripheral State and Errors functions
03082   *  @brief   Peripheral State and Errors functions
03083   *
03084 @verbatim
03085  ===============================================================================
03086             ##### Peripheral State and Errors functions #####
03087  ===============================================================================
03088     [..]
03089     This subsection permit to get in run-time the status of the peripheral
03090     and the data flow.
03091
03092 @endverbatim
03093   * @{
03094   */
03095
03096 /**
03097   * @brief  Return the FMPI2C handle state.
03098   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03099   *                the configuration information for the specified FMPI2C.
03100   * @retval HAL state
03101   */
03102 HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c)
03103 {
03104   /* Return FMPI2C handle state */
03105   return hfmpi2c->State;
03106 }
03107
03108 /**
03109   * @brief  Returns the FMPI2C Master, Slave, Memory or no mode.
03110   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03111   *         the configuration information for FMPI2C module
03112   * @retval HAL mode
03113   */
03114 HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c)
03115 {
03116   return hfmpi2c->Mode;
03117 }
03118
03119 /**
03120   * @brief  Return the FMPI2C error code.
03121   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03122   *              the configuration information for the specified FMPI2C.
03123   * @retval FMPI2C Error Code
03124   */
03125 uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
03126 {
03127   return hfmpi2c->ErrorCode;
03128 }
03129
03130 /**
03131   * @}
03132   */
03133
03134 /**
03135   * @}
03136   */
03137
03138 /** @addtogroup FMPI2C_Private_Functions
03139   * @{
03140   */
03141 /**
03142   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
03143   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03144   *                the configuration information for the specified FMPI2C.
03145   * @retval HAL status
03146   */
03147 static HAL_StatusTypeDef FMPI2C_Master_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
03148 {
03149   uint16_t DevAddress;
03150
03151   /* Process Locked */
03152   __HAL_LOCK(hfmpi2c);
03153
03154   if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
03155   {
03156     /* Clear NACK Flag */
03157     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
03158
03159     /* Set corresponding Error Code */
03160     /* No need to generate STOP, it is automatically done */
03161     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
03162
03163     /* Process Unlocked */
03164     __HAL_UNLOCK(hfmpi2c);
03165
03166     /* Call the Error callback to prevent upper layer */
03167     HAL_FMPI2C_ErrorCallback(hfmpi2c);
03168   }
03169   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) != RESET)
03170   {
03171     if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
03172     {
03173       /* Disable Interrupt */
03174       FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
03175
03176       /* Clear STOP Flag */
03177       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
03178
03179       /* Clear Configuration Register 2 */
03180       FMPI2C_RESET_CR2(hfmpi2c);
03181
03182       if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
03183       {
03184         /* Disable the selected FMPI2C peripheral */
03185         __HAL_FMPI2C_DISABLE(hfmpi2c);
03186
03187         hfmpi2c->PreviousState = FMPI2C_STATE_MEM_BUSY_TX;
03188         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03189
03190         /* Process Unlocked */
03191         __HAL_UNLOCK(hfmpi2c);
03192
03193         /* REenable the selected FMPI2C peripheral */
03194         __HAL_FMPI2C_ENABLE(hfmpi2c);
03195
03196         /* Call the corresponding callback to inform upper layer of End of Transfer */
03197         HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
03198       }
03199       else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
03200       {
03201         /* Flush TX register if not empty */
03202         if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
03203         {
03204           __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE);
03205         }
03206
03207         hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX;
03208         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03209
03210         /* Process Unlocked */
03211         __HAL_UNLOCK(hfmpi2c);
03212
03213         /* Call the corresponding callback to inform upper layer of End of Transfer */
03214         HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
03215       }
03216     }
03217     else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
03218     {
03219       /* Disable Interrupt */
03220       FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
03221
03222       /* Clear STOP Flag */
03223       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
03224
03225       /* Clear Configuration Register 2 */
03226       FMPI2C_RESET_CR2(hfmpi2c);
03227
03228       if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
03229       {
03230         hfmpi2c->PreviousState = FMPI2C_STATE_MEM_BUSY_RX;
03231         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03232
03233         /* Process Unlocked */
03234         __HAL_UNLOCK(hfmpi2c);
03235
03236         /* Call the corresponding callback to inform upper layer of End of Transfer */
03237         HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
03238       }
03239       else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
03240       {
03241         hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX;
03242         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03243
03244         /* Process Unlocked */
03245         __HAL_UNLOCK(hfmpi2c);
03246
03247         /* Call the corresponding callback to inform upper layer of End of Transfer */
03248         HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
03249       }
03250     }
03251   }
03252   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) != RESET)
03253   {
03254     /* Read data from RXDR */
03255     (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
03256     hfmpi2c->XferSize--;
03257     hfmpi2c->XferCount--;
03258   }
03259   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
03260   {
03261     /* Write data to TXDR */
03262     hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
03263     hfmpi2c->XferSize--;
03264     hfmpi2c->XferCount--;
03265   }
03266   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TCR) != RESET)
03267   {
03268     if((hfmpi2c->XferSize == 0U)&&(hfmpi2c->XferCount!=0U))
03269     {
03270       DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
03271
03272       if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
03273       {
03274         FMPI2C_TransferConfig(hfmpi2c, DevAddress, MAX_NBYTE_SIZE, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
03275         hfmpi2c->XferSize = MAX_NBYTE_SIZE;
03276       }
03277       else
03278       {
03279         hfmpi2c->XferSize = hfmpi2c->XferCount;
03280         if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
03281         {
03282           FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
03283         }
03284         else
03285         {
03286           FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
03287         }
03288       }
03289     }
03290     else if((hfmpi2c->XferSize == 0U)&&(hfmpi2c->XferCount==0U))
03291     {
03292       /* Call TxCpltCallback() if no stop mode is set */
03293       if(FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
03294       {
03295         if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
03296         {
03297           /* Disable Interrupt */
03298           FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
03299           hfmpi2c->PreviousState = hfmpi2c->State;
03300           hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03301
03302           /* Process Unlocked */
03303           __HAL_UNLOCK(hfmpi2c);
03304
03305           /* Call the corresponding callback to inform upper layer of End of Transfer */
03306           if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
03307           {
03308             HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
03309           }
03310           else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
03311           {
03312             HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
03313           }
03314         }
03315         else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
03316         {
03317           FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
03318           hfmpi2c->PreviousState = hfmpi2c->State;
03319           hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03320
03321           /* Process Unlocked */
03322           __HAL_UNLOCK(hfmpi2c);
03323
03324           /* Call the corresponding callback to inform upper layer of End of Transfer */
03325           if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
03326           {
03327             HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
03328           }
03329           else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
03330           {
03331             HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
03332           }
03333         }
03334       }
03335     }
03336   }
03337   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TC) != RESET)
03338   {
03339     if(hfmpi2c->XferCount == 0U)
03340     {
03341       if(FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
03342       {
03343         /* No Generate Stop, to permit restart mode */
03344         /* The stop will be done at the end of transfer, when FMPI2C_AUTOEND_MODE enable */
03345         if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
03346         {
03347           /* Disable Interrupt */
03348           FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
03349           hfmpi2c->PreviousState = hfmpi2c->State;
03350           hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03351
03352           /* Process Unlocked */
03353           __HAL_UNLOCK(hfmpi2c);
03354
03355           /* Call the corresponding callback to inform upper layer of End of Transfer */
03356           if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
03357           {
03358             HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
03359           }
03360           else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
03361           {
03362             HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
03363           }
03364         }
03365         else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
03366         {
03367           FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
03368           hfmpi2c->PreviousState = hfmpi2c->State;
03369           hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03370
03371           /* Process Unlocked */
03372           __HAL_UNLOCK(hfmpi2c);
03373
03374           /* Call the corresponding callback to inform upper layer of End of Transfer */
03375           if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
03376           {
03377             HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
03378           }
03379           else if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
03380           {
03381             HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
03382           }
03383         }
03384       }
03385     }
03386   }
03387
03388   /* Process Unlocked */
03389   __HAL_UNLOCK(hfmpi2c);
03390
03391   return HAL_OK;
03392 }
03393
03394 /**
03395   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
03396   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03397   *                the configuration information for the specified FMPI2C.
03398   * @retval HAL status
03399   */
03400 static HAL_StatusTypeDef FMPI2C_Slave_ISR(FMPI2C_HandleTypeDef *hfmpi2c)
03401 {
03402   uint8_t TransferDirection = 0U;
03403   uint16_t SlaveAddrCode = 0U;
03404   uint16_t OwnAdd1Code = 0U;
03405   uint16_t OwnAdd2Code = 0U;
03406
03407   /* Process Locked */
03408   __HAL_LOCK(hfmpi2c);
03409
03410   if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) != RESET)
03411   {
03412     /* Check that FMPI2C transfer finished */
03413     /* if yes, normal usecase, a NACK is sent by the Master when Transfer is finished */
03414     /* Mean XferCount == 0*/
03415     /* So clear Flag NACKF only */
03416     if(hfmpi2c->XferCount == 0U)
03417     {
03418        if(((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \
03419         (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN))
03420       {
03421         hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
03422         /* Disable all Interrupts*/
03423         FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_ADDR | FMPI2C_IT_RX | FMPI2C_IT_TX);
03424
03425         /* Clear NACK Flag */
03426         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
03427
03428         hfmpi2c->PreviousState = hfmpi2c->State;
03429         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03430
03431         /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
03432         HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
03433       }
03434       else if((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
03435       {
03436         /* Last Byte is Transmitted */
03437         /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
03438         FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
03439         hfmpi2c->PreviousState = hfmpi2c->State;
03440         hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
03441
03442         /* Clear NACK Flag */
03443         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
03444
03445         /* Check if TXIS flag is SET */
03446         if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
03447         {
03448           /* Send a dummy data, to clear TXIS event */
03449           hfmpi2c->Instance->TXDR = 0x00U;
03450
03451           /* Flush TX register if not empty */
03452           if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
03453           {
03454             __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE);
03455           }
03456         }
03457
03458         /* Process Unlocked */
03459         __HAL_UNLOCK(hfmpi2c);
03460
03461         /* Call the Tx complete callback to inform upper layer of the end of transmit process */
03462         HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
03463       }
03464       else
03465       {
03466         /* Clear NACK Flag */
03467         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
03468
03469         /* Process Unlocked */
03470         __HAL_UNLOCK(hfmpi2c);
03471       }
03472     }
03473     else
03474     {
03475       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the Master*/
03476       /* Clear NACK Flag */
03477       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
03478
03479       if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
03480       {
03481         /* Set HAL State to "Idle" State, mean to LISTEN state */
03482         /* So reset Slave Busy state */
03483         hfmpi2c->PreviousState = hfmpi2c->State;
03484         hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
03485
03486         /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
03487         FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX | FMPI2C_IT_TX);
03488       }
03489
03490       /* Set ErrorCode corresponding to a Non-Acknowledge */
03491       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
03492
03493       /* Process Unlocked */
03494       __HAL_UNLOCK(hfmpi2c);
03495
03496       /* Call the Error callback to prevent upper layer */
03497       HAL_FMPI2C_ErrorCallback(hfmpi2c);
03498     }
03499   }
03500
03501   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR) != RESET)
03502   {
03503     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
03504     /* Other ADDRInterrupt will be treat in next Listen usecase */
03505     if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
03506     {
03507       TransferDirection = FMPI2C_GET_DIR(hfmpi2c);
03508       SlaveAddrCode = FMPI2C_GET_ADDR_MATCH(hfmpi2c);
03509       OwnAdd1Code = FMPI2C_GET_OWN_ADDRESS1(hfmpi2c);
03510       OwnAdd2Code = FMPI2C_GET_OWN_ADDRESS2(hfmpi2c);
03511
03512       /* If 10bits addressing mode is selected */
03513       if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
03514       {
03515         if((SlaveAddrCode & SlaveAddr_MSK) == ((OwnAdd1Code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
03516         {
03517           SlaveAddrCode = OwnAdd1Code;
03518           hfmpi2c->AddrEventCount++;
03519           if(hfmpi2c->AddrEventCount == 2U)
03520           {
03521             /* Reset Address Event counter  */
03522             hfmpi2c->AddrEventCount = 0U;
03523
03524             /* Clear ADDR flag */
03525             __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
03526
03527             /* Process Unlocked */
03528             __HAL_UNLOCK(hfmpi2c);
03529
03530             /* Call Slave Addr callback */
03531             HAL_FMPI2C_AddrCallback(hfmpi2c, TransferDirection, SlaveAddrCode);
03532           }
03533         }
03534         else
03535         {
03536           SlaveAddrCode = OwnAdd2Code;
03537           __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_ADDRI);
03538
03539           /* Process Unlocked */
03540           __HAL_UNLOCK(hfmpi2c);
03541
03542           /* Call Slave Addr callback */
03543           HAL_FMPI2C_AddrCallback(hfmpi2c, TransferDirection, SlaveAddrCode);
03544         }
03545       }
03546
03547       /* If 7 bits addressing mode is selected */
03548       else if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
03549       {
03550         __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_ADDRI);
03551
03552         /* Clear ADDR flag */
03553         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
03554
03555         /* Process Unlocked */
03556         __HAL_UNLOCK(hfmpi2c);
03557
03558         /* Call Slave Addr callback */
03559         HAL_FMPI2C_AddrCallback(hfmpi2c, TransferDirection, SlaveAddrCode);
03560       }
03561     }
03562     else
03563     {
03564       /* Clear ADDR flag */
03565       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
03566
03567       /* Process Unlocked */
03568       __HAL_UNLOCK(hfmpi2c);
03569     }
03570   }
03571   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) != RESET)
03572   {
03573     if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
03574     {
03575       if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
03576       {
03577         /* Read data from RXDR */
03578         (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
03579         hfmpi2c->XferSize--;
03580         hfmpi2c->XferCount--;
03581
03582         if(hfmpi2c->XferCount == 0U)
03583         {
03584           /* Last Byte is received, disable Interrupt */
03585           FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_RX);
03586
03587           /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_RX, keep only HAL_FMPI2C_STATE_LISTEN */
03588           hfmpi2c->PreviousState = hfmpi2c->State;
03589           hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
03590
03591           /* Process Unlocked */
03592           __HAL_UNLOCK(hfmpi2c);
03593
03594           /* Call the Rx complete callback to inform upper layer of the end of receive process */
03595           HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
03596         }
03597       }
03598     }
03599     else
03600     {
03601       /* Read data from RXDR */
03602       (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
03603       hfmpi2c->XferSize--;
03604       hfmpi2c->XferCount--;
03605     }
03606   }
03607   else if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
03608   {
03609     /* Write data to TXDR only if XferCount not reach "0" */
03610     /* A TXIS flag can be set, during STOP treatment      */
03611     /* Check if all Datas have already been sent */
03612     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
03613     if(hfmpi2c->XferCount > 0U)
03614     {
03615       /* Write data to TXDR */
03616       hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
03617       hfmpi2c->XferCount--;
03618       hfmpi2c->XferSize--;
03619     }
03620     else
03621     {
03622       if((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
03623       {
03624         /* Last Byte is Transmitted */
03625         /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
03626         FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_IT_TX);
03627         hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX;
03628         hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
03629
03630         /* Process Unlocked */
03631         __HAL_UNLOCK(hfmpi2c);
03632
03633         /* Call the Tx complete callback to inform upper layer of the end of transmit process */
03634         HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
03635       }
03636     }
03637   }
03638
03639   /* Check if STOPF is set */
03640   if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) != RESET)
03641   {
03642     /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
03643     __HAL_FMPI2C_DISABLE_IT(hfmpi2c,FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI);
03644
03645     /* Disable Address Acknowledge */
03646     hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
03647
03648     /* Clear Configuration Register 2 */
03649     FMPI2C_RESET_CR2(hfmpi2c);
03650
03651     /* Clear STOP Flag */
03652     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
03653
03654     /* Clear ADDR flag */
03655     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
03656
03657     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03658
03659     if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
03660     {
03661       hfmpi2c->XferOptions = 0U;
03662       hfmpi2c->PreviousState = hfmpi2c->State;
03663
03664       /* Process Unlocked */
03665       __HAL_UNLOCK(hfmpi2c);
03666
03667       /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
03668       HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
03669     }
03670     else
03671     {
03672       /* Process Unlocked */
03673       __HAL_UNLOCK(hfmpi2c);
03674
03675       /* Call the Slave Tx Complete callback */
03676       HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
03677     }
03678   }
03679
03680   /* Process Unlocked */
03681   __HAL_UNLOCK(hfmpi2c);
03682
03683   return HAL_OK;
03684 }
03685
03686 /**
03687   * @brief  Master sends target device address followed by internal memory address for write request.
03688   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03689   *                the configuration information for the specified FMPI2C.
03690   * @param  DevAddress Target device address
03691   * @param  MemAddress Internal memory address
03692   * @param  MemAddSize Size of internal memory address
03693   * @param  Timeout Timeout duration
03694   * @retval HAL status
03695   */
03696 static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
03697 {
03698   FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
03699
03700   /* Wait until TXIS flag is set */
03701   if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
03702   {
03703     if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03704     {
03705       return HAL_ERROR;
03706     }
03707     else
03708     {
03709       return HAL_TIMEOUT;
03710     }
03711   }
03712
03713   /* If Memory address size is 8Bit */
03714   if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
03715   {
03716     /* Send Memory Address */
03717     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
03718   }
03719   /* If Memory address size is 16Bit */
03720   else
03721   {
03722     /* Send MSB of Memory Address */
03723     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
03724
03725     /* Wait until TXIS flag is set */
03726     if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
03727     {
03728       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03729       {
03730         return HAL_ERROR;
03731       }
03732       else
03733       {
03734         return HAL_TIMEOUT;
03735       }
03736     }
03737
03738     /* Send LSB of Memory Address */
03739     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
03740   }
03741
03742   /* Wait until TCR flag is set */
03743   if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
03744   {
03745     return HAL_TIMEOUT;
03746   }
03747
03748 return HAL_OK;
03749 }
03750
03751 /**
03752   * @brief  Master sends target device address followed by internal memory address for read request.
03753   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
03754   *                the configuration information for the specified FMPI2C.
03755   * @param  DevAddress Target device address
03756   * @param  MemAddress Internal memory address
03757   * @param  MemAddSize Size of internal memory address
03758   * @param  Timeout Timeout duration
03759   * @retval HAL status
03760   */
03761 static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
03762 {
03763   FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
03764
03765   /* Wait until TXIS flag is set */
03766   if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
03767   {
03768     if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03769     {
03770       return HAL_ERROR;
03771     }
03772     else
03773     {
03774       return HAL_TIMEOUT;
03775     }
03776   }
03777
03778   /* If Memory address size is 8Bit */
03779   if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
03780   {
03781     /* Send Memory Address */
03782     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
03783   }
03784   /* If Memory address size is 16Bit */
03785   else
03786   {
03787     /* Send MSB of Memory Address */
03788     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
03789
03790     /* Wait until TXIS flag is set */
03791     if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout) != HAL_OK)
03792     {
03793       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03794       {
03795         return HAL_ERROR;
03796       }
03797       else
03798       {
03799         return HAL_TIMEOUT;
03800       }
03801     }
03802
03803     /* Send LSB of Memory Address */
03804     hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
03805   }
03806
03807   /* Wait until TC flag is set */
03808   if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout) != HAL_OK)
03809   {
03810     return HAL_TIMEOUT;
03811   }
03812
03813   return HAL_OK;
03814 }
03815
03816 /**
03817   * @brief  DMA FMPI2C master transmit process complete callback.
03818   * @param  hdma DMA handle
03819   * @retval None
03820   */
03821 static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
03822 {
03823   uint16_t DevAddress;
03824   FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
03825
03826   /* Check if last DMA request was done with RELOAD */
03827   /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
03828   if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
03829   {
03830     /* Wait until TCR flag is set */
03831     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
03832     {
03833       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
03834     }
03835
03836     /* Disable DMA Request */
03837     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
03838
03839     /* Check if Errors has been detected during transfer */
03840     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
03841     {
03842       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03843       /* Wait until STOPF flag is reset */
03844       if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
03845       {
03846         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03847         {
03848           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
03849         }
03850         else
03851         {
03852           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
03853         }
03854       }
03855
03856       /* Clear STOP Flag */
03857       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
03858
03859       /* Clear Configuration Register 2 */
03860       FMPI2C_RESET_CR2(hfmpi2c);
03861
03862       hfmpi2c->XferCount = 0U;
03863
03864       hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03865       hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
03866       HAL_FMPI2C_ErrorCallback(hfmpi2c);
03867     }
03868     else
03869     {
03870       hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
03871       hfmpi2c->XferCount -= hfmpi2c->XferSize;
03872       if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
03873       {
03874         hfmpi2c->XferSize = MAX_NBYTE_SIZE;
03875       }
03876       else
03877       {
03878         hfmpi2c->XferSize = hfmpi2c->XferCount;
03879       }
03880
03881       DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
03882
03883       /* Enable the DMA channel */
03884       HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
03885
03886       /* Send Slave Address */
03887       /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
03888       if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
03889       {
03890         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
03891       }
03892       else
03893       {
03894         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
03895       }
03896
03897       /* Wait until TXIS flag is set */
03898       if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
03899       {
03900         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03901         /* Wait until STOPF flag is reset */
03902         if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
03903         {
03904           if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03905           {
03906             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
03907           }
03908           else
03909           {
03910             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
03911           }
03912         }
03913
03914         /* Clear STOP Flag */
03915         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
03916
03917         /* Clear Configuration Register 2 */
03918         FMPI2C_RESET_CR2(hfmpi2c);
03919
03920         hfmpi2c->XferCount = 0U;
03921
03922         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03923         HAL_FMPI2C_ErrorCallback(hfmpi2c);
03924       }
03925       else
03926       {
03927         /* Enable DMA Request */
03928         hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
03929       }
03930     }
03931   }
03932   else
03933   {
03934     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03935     /* Wait until STOPF flag is reset */
03936     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
03937     {
03938       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03939       {
03940         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
03941       }
03942       else
03943       {
03944         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
03945       }
03946     }
03947
03948     /* Clear STOP Flag */
03949     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
03950
03951     /* Clear Configuration Register 2 */
03952     FMPI2C_RESET_CR2(hfmpi2c);
03953
03954     /* Disable DMA Request */
03955     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
03956
03957     hfmpi2c->XferCount = 0U;
03958
03959     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
03960     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
03961
03962    /* Check if Errors has been detected during transfer */
03963     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
03964     {
03965       HAL_FMPI2C_ErrorCallback(hfmpi2c);
03966     }
03967     else
03968     {
03969       HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
03970     }
03971   }
03972 }
03973
03974 /**
03975   * @brief  DMA FMPI2C slave transmit process complete callback.
03976   * @param  hdma DMA handle
03977   * @retval None
03978   */
03979 static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
03980 {
03981   FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
03982
03983   /* Wait until STOP flag is set */
03984   if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
03985   {
03986     if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
03987     {
03988       /* Normal Use case, a AF is generated by master */
03989       /* to inform slave the end of transfer */
03990       hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
03991     }
03992     else
03993     {
03994       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
03995     }
03996   }
03997
03998   /* Clear STOP flag */
03999   __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
04000
04001   /* Wait until BUSY flag is reset */
04002   if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
04003   {
04004     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04005   }
04006
04007   /* Disable DMA Request */
04008   hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
04009
04010   hfmpi2c->XferCount = 0U;
04011
04012   hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04013   hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04014
04015   /* Check if Errors has been detected during transfer */
04016   if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04017   {
04018     HAL_FMPI2C_ErrorCallback(hfmpi2c);
04019   }
04020   else
04021   {
04022     HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
04023   }
04024 }
04025
04026 /**
04027   * @brief DMA FMPI2C master receive process complete callback
04028   * @param  hdma DMA handle
04029   * @retval None
04030   */
04031 static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
04032 {
04033   FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04034   uint16_t DevAddress;
04035
04036   /* Check if last DMA request was done with RELOAD */
04037   /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
04038   if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
04039   {
04040     /* Wait until TCR flag is set */
04041     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
04042     {
04043       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04044     }
04045
04046     /* Disable DMA Request */
04047     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
04048
04049     /* Check if Errors has been detected during transfer */
04050     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04051     {
04052       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04053       /* Wait until STOPF flag is reset */
04054       if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04055       {
04056         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04057         {
04058           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04059         }
04060         else
04061         {
04062           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04063         }
04064       }
04065
04066       /* Clear STOP Flag */
04067       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04068
04069       /* Clear Configuration Register 2 */
04070       FMPI2C_RESET_CR2(hfmpi2c);
04071
04072       hfmpi2c->XferCount = 0U;
04073
04074       hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04075       hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04076       HAL_FMPI2C_ErrorCallback(hfmpi2c);
04077     }
04078     else
04079     {
04080       hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
04081       hfmpi2c->XferCount -= hfmpi2c->XferSize;
04082       if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
04083       {
04084         hfmpi2c->XferSize = MAX_NBYTE_SIZE;
04085       }
04086       else
04087       {
04088         hfmpi2c->XferSize = hfmpi2c->XferCount;
04089       }
04090
04091       DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
04092
04093       /* Enable the DMA channel */
04094       HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
04095
04096       /* Send Slave Address */
04097       /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
04098       if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
04099       {
04100         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
04101       }
04102       else
04103       {
04104         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
04105       }
04106
04107       /* Wait until RXNE flag is set */
04108       if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
04109       {
04110         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04111       }
04112
04113       /* Check if Errors has been detected during transfer */
04114       if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04115       {
04116         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04117         /* Wait until STOPF flag is reset */
04118         if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04119         {
04120           if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04121           {
04122             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04123           }
04124           else
04125           {
04126             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04127           }
04128         }
04129
04130         /* Clear STOP Flag */
04131         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04132
04133         /* Clear Configuration Register 2 */
04134         FMPI2C_RESET_CR2(hfmpi2c);
04135
04136         hfmpi2c->XferCount = 0U;
04137
04138         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04139         hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04140
04141         HAL_FMPI2C_ErrorCallback(hfmpi2c);
04142       }
04143       else
04144       {
04145         /* Enable DMA Request */
04146         hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
04147       }
04148     }
04149   }
04150   else
04151   {
04152     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04153     /* Wait until STOPF flag is reset */
04154     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04155     {
04156       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04157       {
04158         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04159       }
04160       else
04161       {
04162         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04163       }
04164     }
04165
04166     /* Clear STOP Flag */
04167     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04168
04169     /* Clear Configuration Register 2 */
04170     FMPI2C_RESET_CR2(hfmpi2c);
04171
04172     /* Disable DMA Request */
04173     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
04174
04175     hfmpi2c->XferCount = 0U;
04176
04177     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04178     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04179
04180     /* Check if Errors has been detected during transfer */
04181     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04182     {
04183       HAL_FMPI2C_ErrorCallback(hfmpi2c);
04184     }
04185     else
04186     {
04187       HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
04188     }
04189   }
04190 }
04191
04192 /**
04193   * @brief  DMA FMPI2C slave receive process complete callback.
04194   * @param  hdma DMA handle
04195   * @retval None
04196   */
04197 static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
04198 {
04199   FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04200
04201   /* Wait until STOPF flag is reset */
04202   if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04203   {
04204     if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04205     {
04206       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04207     }
04208     else
04209     {
04210       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04211     }
04212   }
04213
04214   /* Clear STOPF flag */
04215   __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04216
04217   /* Wait until BUSY flag is reset */
04218   if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY) != HAL_OK)
04219
04220   {
04221     hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04222   }
04223
04224   /* Disable DMA Request */
04225   hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
04226
04227   /* Disable Address Acknowledge */
04228   hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
04229
04230   hfmpi2c->XferCount = 0U;
04231
04232   hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04233   hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04234
04235   /* Check if Errors has been detected during transfer */
04236   if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04237   {
04238     HAL_FMPI2C_ErrorCallback(hfmpi2c);
04239   }
04240   else
04241   {
04242     HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
04243   }
04244 }
04245
04246 /**
04247   * @brief DMA FMPI2C Memory Write process complete callback
04248   * @param hdma DMA handle
04249   * @retval None
04250   */
04251 static void FMPI2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
04252 {
04253   uint16_t DevAddress;
04254   FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04255
04256   /* Check if last DMA request was done with RELOAD */
04257   /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
04258   if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
04259   {
04260     /* Wait until TCR flag is set */
04261     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
04262     {
04263       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04264     }
04265
04266     /* Disable DMA Request */
04267     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
04268
04269     /* Check if Errors has been detected during transfer */
04270     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04271     {
04272       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04273       /* Wait until STOPF flag is reset */
04274       if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04275       {
04276         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04277         {
04278           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04279         }
04280         else
04281         {
04282           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04283         }
04284       }
04285
04286       /* Clear STOP Flag */
04287       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04288
04289       /* Clear Configuration Register 2 */
04290       FMPI2C_RESET_CR2(hfmpi2c);
04291
04292       hfmpi2c->XferCount = 0U;
04293
04294       hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04295       hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04296       HAL_FMPI2C_ErrorCallback(hfmpi2c);
04297     }
04298     else
04299     {
04300       hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
04301       hfmpi2c->XferCount -= hfmpi2c->XferSize;
04302       if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
04303       {
04304         hfmpi2c->XferSize = MAX_NBYTE_SIZE;
04305       }
04306       else
04307       {
04308         hfmpi2c->XferSize = hfmpi2c->XferCount;
04309       }
04310
04311       DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
04312
04313       /* Enable the DMA channel */
04314       HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
04315
04316       /* Send Slave Address */
04317       /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
04318       if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
04319       {
04320         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
04321       }
04322       else
04323       {
04324         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
04325       }
04326
04327       /* Wait until TXIS flag is set */
04328       if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_TXIS) != HAL_OK)
04329       {
04330         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04331         /* Wait until STOPF flag is reset */
04332         if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04333         {
04334           if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04335           {
04336             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04337           }
04338           else
04339           {
04340             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04341           }
04342         }
04343
04344         /* Clear STOP Flag */
04345         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04346
04347         /* Clear Configuration Register 2 */
04348         FMPI2C_RESET_CR2(hfmpi2c);
04349
04350         hfmpi2c->XferCount = 0U;
04351
04352         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04353         hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04354         HAL_FMPI2C_ErrorCallback(hfmpi2c);
04355       }
04356       else
04357       {
04358         /* Enable DMA Request */
04359         hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
04360       }
04361     }
04362   }
04363   else
04364   {
04365     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04366     /* Wait until STOPF flag is reset */
04367     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04368     {
04369       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04370       {
04371         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04372       }
04373       else
04374       {
04375         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04376       }
04377     }
04378
04379     /* Clear STOP Flag */
04380     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04381
04382     /* Clear Configuration Register 2 */
04383     FMPI2C_RESET_CR2(hfmpi2c);
04384
04385     /* Disable DMA Request */
04386     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
04387
04388     hfmpi2c->XferCount = 0U;
04389
04390     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04391     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04392
04393     /* Check if Errors has been detected during transfer */
04394     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04395     {
04396       HAL_FMPI2C_ErrorCallback(hfmpi2c);
04397     }
04398     else
04399     {
04400       HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
04401     }
04402   }
04403 }
04404
04405 /**
04406   * @brief  DMA FMPI2C Memory Read process complete callback
04407   * @param  hdma DMA handle
04408   * @retval None
04409   */
04410 static void FMPI2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
04411 {
04412   FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04413   uint16_t DevAddress;
04414
04415   /* Check if last DMA request was done with RELOAD */
04416   /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
04417   if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
04418   {
04419     /* Wait until TCR flag is set */
04420     if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, FMPI2C_TIMEOUT_TCR) != HAL_OK)
04421     {
04422       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04423     }
04424
04425     /* Disable DMA Request */
04426     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
04427
04428     /* Check if Errors has been detected during transfer */
04429     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04430     {
04431       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04432       /* Wait until STOPF flag is reset */
04433       if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04434       {
04435         if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04436         {
04437           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04438         }
04439         else
04440         {
04441           hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04442         }
04443       }
04444
04445       /* Clear STOP Flag */
04446       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04447
04448       /* Clear Configuration Register 2 */
04449       FMPI2C_RESET_CR2(hfmpi2c);
04450
04451       hfmpi2c->XferCount = 0U;
04452
04453       hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04454       hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04455       HAL_FMPI2C_ErrorCallback(hfmpi2c);
04456     }
04457     else
04458     {
04459       hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
04460       hfmpi2c->XferCount -= hfmpi2c->XferSize;
04461       if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
04462       {
04463         hfmpi2c->XferSize = MAX_NBYTE_SIZE;
04464       }
04465       else
04466       {
04467         hfmpi2c->XferSize = hfmpi2c->XferCount;
04468       }
04469
04470       DevAddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
04471
04472       /* Enable the DMA channel */
04473       HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
04474
04475       /* Send Slave Address */
04476       /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */
04477       if( (hfmpi2c->XferSize == MAX_NBYTE_SIZE) && (hfmpi2c->XferSize < hfmpi2c->XferCount) )
04478       {
04479         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
04480       }
04481       else
04482       {
04483         FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
04484       }
04485
04486       /* Wait until RXNE flag is set */
04487       if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, FMPI2C_TIMEOUT_RXNE) != HAL_OK)
04488       {
04489         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04490       }
04491
04492       /* Check if Errors has been detected during transfer */
04493       if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04494       {
04495         /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04496         /* Wait until STOPF flag is reset */
04497         if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04498         {
04499           if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04500           {
04501             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04502           }
04503           else
04504           {
04505             hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04506           }
04507         }
04508
04509         /* Clear STOP Flag */
04510         __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04511
04512         /* Clear Configuration Register 2 */
04513         FMPI2C_RESET_CR2(hfmpi2c);
04514
04515         hfmpi2c->XferCount = 0U;
04516
04517         hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04518         hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04519         HAL_FMPI2C_ErrorCallback(hfmpi2c);
04520       }
04521       else
04522       {
04523         /* Enable DMA Request */
04524         hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
04525       }
04526     }
04527   }
04528   else
04529   {
04530     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
04531     /* Wait until STOPF flag is reset */
04532     if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, FMPI2C_TIMEOUT_STOPF) != HAL_OK)
04533     {
04534       if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
04535       {
04536         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
04537       }
04538       else
04539       {
04540         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04541       }
04542     }
04543
04544     /* Clear STOP Flag */
04545     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04546
04547     /* Clear Configuration Register 2 */
04548     FMPI2C_RESET_CR2(hfmpi2c);
04549
04550     /* Disable DMA Request */
04551     hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
04552
04553     hfmpi2c->XferCount = 0U;
04554
04555     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04556     hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04557
04558     /* Check if Errors has been detected during transfer */
04559     if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
04560     {
04561       HAL_FMPI2C_ErrorCallback(hfmpi2c);
04562     }
04563     else
04564     {
04565       HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
04566     }
04567   }
04568 }
04569
04570 /**
04571   * @brief  DMA FMPI2C communication error callback.
04572   * @param hdma DMA handle
04573   * @retval None
04574   */
04575 static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
04576 {
04577   FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04578
04579   /* Disable Acknowledge */
04580   hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
04581
04582   hfmpi2c->XferCount = 0U;
04583
04584   hfmpi2c->State = HAL_FMPI2C_STATE_READY;
04585   hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
04586
04587   hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
04588
04589   HAL_FMPI2C_ErrorCallback(hfmpi2c);
04590 }
04591
04592 /**
04593   * @brief  This function handles FMPI2C Communication Timeout.
04594   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
04595   *                the configuration information for the specified FMPI2C.
04596   * @param  Flag Specifies the FMPI2C flag to check.
04597   * @param  Status The new Flag status (SET or RESET).
04598   * @param  Timeout Timeout duration
04599   * @retval HAL status
04600   */
04601 static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
04602 {
04603   uint32_t tickstart = HAL_GetTick();
04604
04605   /* Wait until flag is set */
04606   if(Status == RESET)
04607   {
04608     while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == RESET)
04609     {
04610       /* Check for the Timeout */
04611       if(Timeout != HAL_MAX_DELAY)
04612       {
04613         if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04614         {
04615           hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04616           /* Process Unlocked */
04617           __HAL_UNLOCK(hfmpi2c);
04618           return HAL_TIMEOUT;
04619         }
04620       }
04621     }
04622   }
04623   else
04624   {
04625     while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) != RESET)
04626     {
04627       /* Check for the Timeout */
04628       if(Timeout != HAL_MAX_DELAY)
04629       {
04630         if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04631         {
04632           hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04633           /* Process Unlocked */
04634           __HAL_UNLOCK(hfmpi2c);
04635           return HAL_TIMEOUT;
04636         }
04637       }
04638     }
04639   }
04640   return HAL_OK;
04641 }
04642
04643 /**
04644   * @brief  This function handles FMPI2C Communication Timeout for specific usage of TXIS flag.
04645   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
04646   *                the configuration information for the specified FMPI2C.
04647   * @param  Timeout Timeout duration
04648   * @retval HAL status
04649   */
04650 static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
04651 {
04652   uint32_t tickstart = HAL_GetTick();
04653
04654   while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
04655   {
04656     /* Check if a NACK is detected */
04657     if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
04658     {
04659       return HAL_ERROR;
04660     }
04661
04662     /* Check for the Timeout */
04663     if(Timeout != HAL_MAX_DELAY)
04664     {
04665       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04666       {
04667         hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04668         hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04669
04670         /* Process Unlocked */
04671         __HAL_UNLOCK(hfmpi2c);
04672
04673         return HAL_TIMEOUT;
04674       }
04675     }
04676   }
04677   return HAL_OK;
04678 }
04679
04680 /**
04681   * @brief  This function handles FMPI2C Communication Timeout for specific usage of STOP flag.
04682   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
04683   *                the configuration information for the specified FMPI2C.
04684   * @param  Timeout Timeout duration
04685   * @retval HAL status
04686   */
04687 static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
04688 {
04689   uint32_t tickstart = 0x00U;
04690   tickstart = HAL_GetTick();
04691
04692   while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
04693   {
04694     /* Check if a NACK is detected */
04695     if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout) != HAL_OK)
04696     {
04697       return HAL_ERROR;
04698     }
04699
04700     /* Check for the Timeout */
04701     if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04702     {
04703       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04704       hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04705
04706       /* Process Unlocked */
04707       __HAL_UNLOCK(hfmpi2c);
04708
04709       return HAL_TIMEOUT;
04710     }
04711   }
04712   return HAL_OK;
04713 }
04714
04715 /**
04716   * @brief  This function handles FMPI2C Communication Timeout for specific usage of RXNE flag.
04717   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
04718   *                the configuration information for the specified FMPI2C.
04719   * @param  Timeout Timeout duration
04720   * @retval HAL status
04721   */
04722 static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
04723 {
04724   uint32_t tickstart = 0x00U;
04725   tickstart = HAL_GetTick();
04726
04727   while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
04728   {
04729     /* Check if a STOPF is detected */
04730     if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
04731     {
04732       /* Clear STOP Flag */
04733       __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04734
04735       /* Clear Configuration Register 2 */
04736       FMPI2C_RESET_CR2(hfmpi2c);
04737
04738       hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
04739       hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04740
04741       /* Process Unlocked */
04742       __HAL_UNLOCK(hfmpi2c);
04743
04744       return HAL_ERROR;
04745     }
04746
04747     /* Check for the Timeout */
04748     if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04749     {
04750       hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
04751       hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04752
04753       /* Process Unlocked */
04754       __HAL_UNLOCK(hfmpi2c);
04755
04756       return HAL_TIMEOUT;
04757     }
04758   }
04759   return HAL_OK;
04760 }
04761
04762 /**
04763   * @brief  This function handles Acknowledge failed detection during an FMPI2C Communication.
04764   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
04765   *                the configuration information for the specified FMPI2C.
04766   * @param  Timeout Timeout duration
04767   * @retval HAL status
04768   */
04769 static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout)
04770 {
04771   uint32_t tickstart = 0x00U;
04772   tickstart = HAL_GetTick();
04773
04774   if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
04775   {
04776     /* Generate stop if necessary only in case of FMPI2C peripheral in MASTER mode or MEMORY mode */
04777      if((hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) || (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM))
04778     {
04779       /* No need to generate the STOP condition if AUTOEND mode is enabled */
04780       /* Generate the STOP condition only in case of SOFTEND mode is enabled */
04781       if((hfmpi2c->Instance->CR2 & FMPI2C_AUTOEND_MODE) != FMPI2C_AUTOEND_MODE)
04782       {
04783         /* Generate Stop */
04784         hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
04785       }
04786     }
04787
04788     /* Wait until STOP Flag is reset */
04789     /* AutoEnd should be initiate after AF */
04790     while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
04791     {
04792       /* Check for the Timeout */
04793       if(Timeout != HAL_MAX_DELAY)
04794       {
04795         if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04796         {
04797           hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04798           /* Process Unlocked */
04799           __HAL_UNLOCK(hfmpi2c);
04800           return HAL_TIMEOUT;
04801         }
04802       }
04803     }
04804
04805     /* Clear NACKF Flag */
04806     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
04807
04808     /* Clear STOP Flag */
04809     __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
04810
04811     /* Clear Configuration Register 2 */
04812     FMPI2C_RESET_CR2(hfmpi2c);
04813
04814     hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
04815     hfmpi2c->State= HAL_FMPI2C_STATE_READY;
04816
04817     /* Process Unlocked */
04818     __HAL_UNLOCK(hfmpi2c);
04819
04820     return HAL_ERROR;
04821   }
04822   return HAL_OK;
04823 }
04824
04825 /**
04826   * @brief  Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
04827   * @param  hfmpi2c FMPI2C handle.
04828   * @param  DevAddress Specifies the slave address to be programmed.
04829   * @param  Size Specifies the number of bytes to be programmed.
04830   *   This parameter must be a value between 0 and 255.
04831   * @param  Mode New state of the FMPI2C START condition generation.
04832   *   This parameter can be one of the following values:
04833   *     @arg @ref FMPI2C_RELOAD_MODE Enable Reload mode .
04834   *     @arg @ref FMPI2C_AUTOEND_MODE Enable Automatic end mode.
04835   *     @arg @ref FMPI2C_SOFTEND_MODE Enable Software end mode.
04836   * @param  Request New state of the FMPI2C START condition generation.
04837   *   This parameter can be one of the following values:
04838   *     @arg @ref FMPI2C_NO_STARTSTOP Don't Generate stop and start condition.
04839   *     @arg @ref FMPI2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
04840   *     @arg @ref FMPI2C_GENERATE_START_READ Generate Restart for read request.
04841   *     @arg @ref FMPI2C_GENERATE_START_WRITE Generate Restart for write request.
04842   * @retval None
04843   */
04844 static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
04845 {
04846   uint32_t tmpreg = 0U;
04847
04848   /* Check the parameters */
04849   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
04850   assert_param(IS_TRANSFER_MODE(Mode));
04851   assert_param(IS_TRANSFER_REQUEST(Request));
04852
04853   /* Get the CR2 register value */
04854   tmpreg = hfmpi2c->Instance->CR2;
04855
04856   /* clear tmpreg specific bits */
04857   tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP));
04858
04859   /* update tmpreg */
04860   tmpreg |= (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << 16U) & FMPI2C_CR2_NBYTES) | \
04861             (uint32_t)Mode | (uint32_t)Request);
04862
04863   /* update CR2 register */
04864   hfmpi2c->Instance->CR2 = tmpreg;
04865 }
04866
04867 /**
04868   * @brief  Manage the enabling of Interrupts.
04869   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
04870   *                the configuration information for the specified FMPI2C.
04871   * @param  InterruptRequest Value of @ref FMPI2C_Interrupt_configuration_definition.
04872   * @retval HAL status
04873   */
04874 static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
04875 {
04876   uint32_t tmpisr = 0U;
04877
04878   if((InterruptRequest & FMPI2C_IT_ADDR) == FMPI2C_IT_ADDR)
04879   {
04880     /* Enable ADDR and STOP interrupt */
04881     tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
04882   }
04883
04884   if((InterruptRequest & FMPI2C_IT_TX) == FMPI2C_IT_TX)
04885   {
04886     /* Enable ERR, TC, STOP, NACK and RXI interrupt */
04887     tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
04888   }
04889
04890   if((InterruptRequest & FMPI2C_IT_RX) == FMPI2C_IT_RX)
04891   {
04892     /* Enable ERR, TC, STOP, NACK and TXI interrupt */
04893     tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
04894   }
04895
04896   /* Enable interrupts only at the end */
04897   /* to avoid the risk of FMPI2C interrupt handle execution before */
04898   /* all interrupts requested done */
04899   __HAL_FMPI2C_ENABLE_IT(hfmpi2c, tmpisr);
04900
04901   return HAL_OK;
04902 }
04903
04904 /**
04905   * @brief  Manage the disabling of Interrupts.
04906   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
04907   *                the configuration information for the specified FMPI2C.
04908   * @param  InterruptRequest Value of @ref FMPI2C_Interrupt_configuration_definition.
04909   * @retval HAL status
04910   */
04911 static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
04912 {
04913   uint32_t tmpisr = 0U;
04914
04915   if((InterruptRequest & FMPI2C_IT_TX) == FMPI2C_IT_TX)
04916   {
04917     /* Disable TC and TXI interrupts */
04918     tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_TXI;
04919
04920     if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
04921     {
04922       /* Disable NACK and STOP interrupts */
04923       tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI;
04924     }
04925   }
04926
04927   if((InterruptRequest & FMPI2C_IT_RX) == FMPI2C_IT_RX)
04928   {
04929     /* Disable TC and RXI interrupts */
04930     tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_RXI;
04931
04932     if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
04933     {
04934       /* Disable NACK and STOP interrupts */
04935       tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI;
04936     }
04937   }
04938
04939   if((InterruptRequest & FMPI2C_IT_ADDR) == FMPI2C_IT_ADDR)
04940   {
04941     /* Disable ADDR, NACK and STOP interrupts */
04942     tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI;
04943   }
04944
04945   /* Disable interrupts only at the end */
04946   /* to avoid a breaking situation like at "t" time */
04947   /* all disable interrupts request are not done */
04948   __HAL_FMPI2C_DISABLE_IT(hfmpi2c, tmpisr);
04949
04950   return HAL_OK;
04951 }
04952
04953 /**
04954   * @}
04955   */
04956 #endif /* STM32F410xx || STM32F446xx */
04957 #endif /* HAL_FMPI2C_MODULE_ENABLED */
04958 /**
04959   * @}
04960   */
04961
04962 /**
04963   * @}
04964   */
04965
04966 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c.h Source File

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stm32f4xx_hal_fmpi2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_fmpi2c.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of FMPI2C HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_FMPI2C_H
00040 #define __STM32F4xx_HAL_FMPI2C_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f4xx_hal_def.h"
00050
00051 /** @addtogroup STM32F4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup FMPI2C
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup FMPI2C_Configuration_Structure_definition FMPI2C Configuration Structure definition
00065   * @brief  FMPI2C Configuration Structure definition
00066   * @{
00067   */
00068 typedef struct
00069 {
00070   uint32_t Timing;              /*!< Specifies the FMPI2C_TIMINGR_register value.
00071                                   This parameter calculated by referring to FMPI2C initialization
00072                                          section in Reference manual */
00073
00074   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00075                                   This parameter can be a 7-bit or 10-bit address. */
00076
00077   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00078                                   This parameter can be a value of @ref FMPI2C_addressing_mode */
00079
00080   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00081                                   This parameter can be a value of @ref FMPI2C_dual_addressing_mode */
00082
00083   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00084                                   This parameter can be a 7-bit address. */
00085
00086   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
00087                                   This parameter can be a value of @ref FMPI2C_own_address2_masks */
00088
00089   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00090                                   This parameter can be a value of @ref FMPI2C_general_call_addressing_mode */
00091
00092   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00093                                   This parameter can be a value of @ref FMPI2C_nostretch_mode */
00094
00095 }FMPI2C_InitTypeDef;
00096
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup HAL_state_structure_definition HAL state structure definition
00102   * @brief  HAL State structure definition
00103   * @{
00104   */
00105
00106 typedef enum
00107 {
00108   HAL_FMPI2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00109   HAL_FMPI2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00110   HAL_FMPI2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00111   HAL_FMPI2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00112   HAL_FMPI2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00113   HAL_FMPI2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00114   HAL_FMPI2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00115                                                  process is ongoing                            */
00116   HAL_FMPI2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00117                                                  process is ongoing                            */
00118   HAL_FMPI2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00119   HAL_FMPI2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00120 }HAL_FMPI2C_StateTypeDef;
00121
00122 /**
00123   * @brief  HAL State structures definition
00124   */
00125 typedef enum
00126 {
00127   HAL_FMPI2C_MODE_NONE               = 0x00U,   /*!< No FMPI2C communication on going             */
00128   HAL_FMPI2C_MODE_MASTER             = 0x10U,   /*!< FMPI2C communication is in Master Mode       */
00129   HAL_FMPI2C_MODE_SLAVE              = 0x20U,   /*!< FMPI2C communication is in Slave Mode        */
00130   HAL_FMPI2C_MODE_MEM                = 0x40U    /*!< FMPI2C communication is in Memory Mode       */
00131
00132 }HAL_FMPI2C_ModeTypeDef;
00133
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition
00139   * @brief  FMPI2C Error Code definition
00140   * @{
00141   */
00142 #define HAL_FMPI2C_ERROR_NONE              ((uint32_t)0x00000000U)    /*!< No error              */
00143 #define HAL_FMPI2C_ERROR_BERR              ((uint32_t)0x00000001U)    /*!< BERR error            */
00144 #define HAL_FMPI2C_ERROR_ARLO              ((uint32_t)0x00000002U)    /*!< ARLO error            */
00145 #define HAL_FMPI2C_ERROR_AF                ((uint32_t)0x00000004U)    /*!< ACKF error            */
00146 #define HAL_FMPI2C_ERROR_OVR               ((uint32_t)0x00000008U)    /*!< OVR error             */
00147 #define HAL_FMPI2C_ERROR_DMA               ((uint32_t)0x00000010U)    /*!< DMA transfer error    */
00148 #define HAL_FMPI2C_ERROR_TIMEOUT           ((uint32_t)0x00000020U)    /*!< Timeout error         */
00149 #define HAL_FMPI2C_ERROR_SIZE              ((uint32_t)0x00000040U)    /*!< Size Management error */
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup FMPI2C_XferOptions_definition  FMPI2C XferOptions definition
00155   * @{
00156   */
00157 #define FMPI2C_NO_OPTION_FRAME             ((uint32_t)0xFFFF0000U)
00158 #define FMPI2C_FIRST_FRAME                 ((uint32_t)FMPI2C_SOFTEND_MODE)
00159 #define FMPI2C_NEXT_FRAME                  ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
00160 #define FMPI2C_FIRST_AND_LAST_FRAME        ((uint32_t)FMPI2C_AUTOEND_MODE)
00161 #define FMPI2C_LAST_FRAME                  ((uint32_t)FMPI2C_AUTOEND_MODE)
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition
00167   * @brief  FMPI2C handle Structure definition
00168   * @{
00169   */
00170 typedef struct
00171 {
00172   FMPI2C_TypeDef                *Instance;    /*!< FMPI2C registers base address     */
00173
00174   FMPI2C_InitTypeDef            Init;         /*!< FMPI2C communication parameters   */
00175
00176   uint8_t                    *pBuffPtr;       /*!< Pointer to FMPI2C transfer buffer */
00177
00178   uint16_t                   XferSize;        /*!< FMPI2C transfer size              */
00179
00180   __IO uint16_t              XferCount;       /*!< FMPI2C transfer counter           */
00181
00182   __IO uint32_t              XferOptions;     /*!< FMPI2C transfer options           */
00183
00184   __IO uint32_t              PreviousState;   /*!< FMPI2C communication Previous state */
00185
00186   DMA_HandleTypeDef          *hdmatx;         /*!< FMPI2C Tx DMA handle parameters   */
00187
00188   DMA_HandleTypeDef          *hdmarx;         /*!< FMPI2C Rx DMA handle parameters   */
00189
00190   HAL_LockTypeDef            Lock;            /*!< FMPI2C locking object             */
00191
00192   __IO HAL_FMPI2C_StateTypeDef  State;           /*!< FMPI2C communication state     */
00193
00194   __IO HAL_FMPI2C_ModeTypeDef   Mode;            /*!< FMPI2C communication mode      */
00195
00196   __IO uint32_t              ErrorCode;       /*!< FMPI2C Error code                 */
00197
00198   __IO uint32_t              AddrEventCount;  /*!< FMPI2C Address Event counter     */
00199 }FMPI2C_HandleTypeDef;
00200 /**
00201   * @}
00202   */
00203
00204 /**
00205   * @}
00206   */
00207 /* Exported constants --------------------------------------------------------*/
00208
00209 /** @defgroup FMPI2C_Exported_Constants FMPI2C Exported Constants
00210   * @{
00211   */
00212
00213 /** @defgroup FMPI2C_addressing_mode FMPI2C addressing mode
00214   * @{
00215   */
00216 #define FMPI2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001U)
00217 #define FMPI2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002U)
00218
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup FMPI2C_dual_addressing_mode FMPI2C dual addressing mode
00224   * @{
00225   */
00226
00227 #define FMPI2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000U)
00228 #define FMPI2C_DUALADDRESS_ENABLE          FMPI2C_OAR2_OA2EN
00229
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup FMPI2C_own_address2_masks FMPI2C own address2 masks
00235   * @{
00236   */
00237
00238 #define FMPI2C_OA2_NOMASK                  ((uint8_t)0x00U)
00239 #define FMPI2C_OA2_MASK01                  ((uint8_t)0x01U)
00240 #define FMPI2C_OA2_MASK02                  ((uint8_t)0x02U)
00241 #define FMPI2C_OA2_MASK03                  ((uint8_t)0x03U)
00242 #define FMPI2C_OA2_MASK04                  ((uint8_t)0x04U)
00243 #define FMPI2C_OA2_MASK05                  ((uint8_t)0x05U)
00244 #define FMPI2C_OA2_MASK06                  ((uint8_t)0x06U)
00245 #define FMPI2C_OA2_MASK07                  ((uint8_t)0x07U)
00246
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup FMPI2C_general_call_addressing_mode FMPI2C general call addressing mode
00252   * @{
00253   */
00254 #define FMPI2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000U)
00255 #define FMPI2C_GENERALCALL_ENABLE          FMPI2C_CR1_GCEN
00256
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup FMPI2C_nostretch_mode FMPI2C nostretch mode
00262   * @{
00263   */
00264 #define FMPI2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000U)
00265 #define FMPI2C_NOSTRETCH_ENABLE            FMPI2C_CR1_NOSTRETCH
00266
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup FMPI2C_Memory_Address_Size FMPI2C Memory Address Size
00272   * @{
00273   */
00274 #define FMPI2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)
00275 #define FMPI2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002U)
00276
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup FMPI2C_XferDirection_definition FMPI2C XferDirection definition
00282   * @{
00283   */
00284 #define FMPI2C_DIRECTION_RECEIVE           ((uint32_t)0x00000000U)
00285 #define FMPI2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000001U)
00286
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup FMPI2C_ReloadEndMode_definition FMPI2C ReloadEndMode definition
00292   * @{
00293   */
00294 #define  FMPI2C_RELOAD_MODE                FMPI2C_CR2_RELOAD
00295 #define  FMPI2C_AUTOEND_MODE               FMPI2C_CR2_AUTOEND
00296 #define  FMPI2C_SOFTEND_MODE               ((uint32_t)0x00000000U)
00297
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup FMPI2C_StartStopMode_definition FMPI2C StartStopMode definition
00303   * @{
00304   */
00305
00306 #define  FMPI2C_NO_STARTSTOP               ((uint32_t)0x00000000U)
00307 #define  FMPI2C_GENERATE_STOP              FMPI2C_CR2_STOP
00308 #define  FMPI2C_GENERATE_START_READ        (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
00309 #define  FMPI2C_GENERATE_START_WRITE       FMPI2C_CR2_START
00310
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup FMPI2C_Interrupt_configuration_definition FMPI2C Interrupt configuration definition
00316   * @brief FMPI2C Interrupt definition
00317   *        Elements values convention: 0xXXXXXXXX
00318   *           - XXXXXXXX  : Interrupt control mask
00319   * @{
00320   */
00321 #define FMPI2C_IT_ERRI                     FMPI2C_CR1_ERRIE
00322 #define FMPI2C_IT_TCI                      FMPI2C_CR1_TCIE
00323 #define FMPI2C_IT_STOPI                    FMPI2C_CR1_STOPIE
00324 #define FMPI2C_IT_NACKI                    FMPI2C_CR1_NACKIE
00325 #define FMPI2C_IT_ADDRI                    FMPI2C_CR1_ADDRIE
00326 #define FMPI2C_IT_RXI                      FMPI2C_CR1_RXIE
00327 #define FMPI2C_IT_TXI                      FMPI2C_CR1_TXIE
00328 #define FMPI2C_IT_TX                       (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI)
00329 #define FMPI2C_IT_RX                       (FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI)
00330 #define FMPI2C_IT_ADDR                     (FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI)
00331
00332 /**
00333   * @}
00334   */
00335
00336
00337 /** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
00338   * @{
00339   */
00340 #define FMPI2C_FLAG_TXE                    FMPI2C_ISR_TXE
00341 #define FMPI2C_FLAG_TXIS                   FMPI2C_ISR_TXIS
00342 #define FMPI2C_FLAG_RXNE                   FMPI2C_ISR_RXNE
00343 #define FMPI2C_FLAG_ADDR                   FMPI2C_ISR_ADDR
00344 #define FMPI2C_FLAG_AF                     FMPI2C_ISR_NACKF
00345 #define FMPI2C_FLAG_STOPF                  FMPI2C_ISR_STOPF
00346 #define FMPI2C_FLAG_TC                     FMPI2C_ISR_TC
00347 #define FMPI2C_FLAG_TCR                    FMPI2C_ISR_TCR
00348 #define FMPI2C_FLAG_BERR                   FMPI2C_ISR_BERR
00349 #define FMPI2C_FLAG_ARLO                   FMPI2C_ISR_ARLO
00350 #define FMPI2C_FLAG_OVR                    FMPI2C_ISR_OVR
00351 #define FMPI2C_FLAG_PECERR                 FMPI2C_ISR_PECERR
00352 #define FMPI2C_FLAG_TIMEOUT                FMPI2C_ISR_TIMEOUT
00353 #define FMPI2C_FLAG_ALERT                  FMPI2C_ISR_ALERT
00354 #define FMPI2C_FLAG_BUSY                   FMPI2C_ISR_BUSY
00355 #define FMPI2C_FLAG_DIR                    FMPI2C_ISR_DIR
00356 /**
00357   * @}
00358   */
00359
00360 /**
00361   * @}
00362   */
00363
00364 /* Exported macros -----------------------------------------------------------*/
00365 /** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
00366   * @{
00367   */
00368
00369 /** @brief Reset FMPI2C handle state.
00370   * @param  __HANDLE__ specifies the FMPI2C Handle.
00371   * @retval None
00372   */
00373 #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
00374
00375 /** @brief  Enable the specified FMPI2C interrupt.
00376   * @param  __HANDLE__ specifies the FMPI2C Handle.
00377   * @param  __INTERRUPT__: specifies the interrupt source to enable.
00378   *         This parameter can be one of the following values:
00379   *            @arg @ref FMPI2C_IT_ERRI  Errors interrupt enable
00380   *            @arg @ref FMPI2C_IT_TCI   Transfer complete interrupt enable
00381   *            @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
00382   *            @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
00383   *            @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
00384   *            @arg @ref FMPI2C_IT_RXI   RX interrupt enable
00385   *            @arg @ref FMPI2C_IT_TXI   TX interrupt enable
00386   *
00387   * @retval None
00388   */
00389
00390 #define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00391
00392 /** @brief  Disable the specified FMPI2C interrupt.
00393   * @param  __HANDLE__ specifies the FMPI2C Handle.
00394   * @param  __INTERRUPT__: specifies the interrupt source to disable.
00395   *         This parameter can be one of the following values:
00396   *            @arg @ref FMPI2C_IT_ERRI  Errors interrupt enable
00397   *            @arg @ref FMPI2C_IT_TCI   Transfer complete interrupt enable
00398   *            @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
00399   *            @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
00400   *            @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
00401   *            @arg @ref FMPI2C_IT_RXI   RX interrupt enable
00402   *            @arg @ref FMPI2C_IT_TXI   TX interrupt enable
00403   *
00404   * @retval None
00405   */
00406 #define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00407
00408 /** @brief  Check whether the specified FMPI2C interrupt source is enabled or not.
00409   * @param  __HANDLE__ specifies the FMPI2C Handle.
00410   * @param  __INTERRUPT__: specifies the FMPI2C interrupt source to check.
00411   *         This parameter can be one of the following values:
00412   *            @arg @ref FMPI2C_IT_ERRI  Errors interrupt enable
00413   *            @arg @ref FMPI2C_IT_TCI   Transfer complete interrupt enable
00414   *            @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
00415   *            @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
00416   *            @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
00417   *            @arg @ref FMPI2C_IT_RXI   RX interrupt enable
00418   *            @arg @ref FMPI2C_IT_TXI   TX interrupt enable
00419   *
00420   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00421   */
00422 #define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00423
00424 /** @brief  Check whether the specified FMPI2C flag is set or not.
00425   * @param  __HANDLE__ specifies the FMPI2C Handle.
00426   * @param  __FLAG__ specifies the flag to check.
00427   *         This parameter can be one of the following values:
00428   *            @arg @ref FMPI2C_FLAG_TXE     Transmit data register empty
00429   *            @arg @ref FMPI2C_FLAG_TXIS    Transmit interrupt status
00430   *            @arg @ref FMPI2C_FLAG_RXNE    Receive data register not empty
00431   *            @arg @ref FMPI2C_FLAG_ADDR    Address matched (slave mode)
00432   *            @arg @ref FMPI2C_FLAG_AF      Acknowledge failure received flag
00433   *            @arg @ref FMPI2C_FLAG_STOPF   STOP detection flag
00434   *            @arg @ref FMPI2C_FLAG_TC      Transfer complete (master mode)
00435   *            @arg @ref FMPI2C_FLAG_TCR     Transfer complete reload
00436   *            @arg @ref FMPI2C_FLAG_BERR    Bus error
00437   *            @arg @ref FMPI2C_FLAG_ARLO    Arbitration lost
00438   *            @arg @ref FMPI2C_FLAG_OVR     Overrun/Underrun
00439   *            @arg @ref FMPI2C_FLAG_PECERR  PEC error in reception
00440   *            @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00441   *            @arg @ref FMPI2C_FLAG_ALERT   SMBus alert
00442   *            @arg @ref FMPI2C_FLAG_BUSY    Bus busy
00443   *            @arg @ref FMPI2C_FLAG_DIR     Transfer direction (slave mode)
00444   *
00445   * @retval The new state of __FLAG__ (TRUE or FALSE).
00446   */
00447 #define FMPI2C_FLAG_MASK  ((uint32_t)0x0001FFFFU)
00448 #define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
00449
00450 /** @brief  Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
00451   * @param  __HANDLE__ specifies the FMPI2C Handle.
00452   * @param  __FLAG__ specifies the flag to clear.
00453   *          This parameter can be any combination of the following values:
00454   *            @arg @ref FMPI2C_FLAG_TXE     Transmit data register empty
00455   *            @arg @ref FMPI2C_FLAG_ADDR    Address matched (slave mode)
00456   *            @arg @ref FMPI2C_FLAG_AF      Acknowledge failure received flag
00457   *            @arg @ref FMPI2C_FLAG_STOPF   STOP detection flag
00458   *            @arg @ref FMPI2C_FLAG_BERR    Bus error
00459   *            @arg @ref FMPI2C_FLAG_ARLO    Arbitration lost
00460   *            @arg @ref FMPI2C_FLAG_OVR     Overrun/Underrun
00461   *            @arg @ref FMPI2C_FLAG_PECERR  PEC error in reception
00462   *            @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00463   *            @arg @ref FMPI2C_FLAG_ALERT   SMBus alert
00464   *
00465   * @retval None
00466   */
00467 #define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
00468                                                                                          ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00469
00470 /** @brief  Enable the specified FMPI2C peripheral.
00471   * @param  __HANDLE__ specifies the FMPI2C Handle.
00472   * @retval None
00473   */
00474 #define __HAL_FMPI2C_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->CR1,  FMPI2C_CR1_PE))
00475
00476 /** @brief  Disable the specified FMPI2C peripheral.
00477   * @param  __HANDLE__ specifies the FMPI2C Handle.
00478   * @retval None
00479   */
00480 #define __HAL_FMPI2C_DISABLE(__HANDLE__)   (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
00481
00482 /**
00483   * @}
00484   */
00485
00486 /* Include FMPI2C HAL Extended module */
00487 #include "stm32f4xx_hal_fmpi2c_ex.h"
00488
00489 /* Exported functions --------------------------------------------------------*/
00490 /** @addtogroup FMPI2C_Exported_Functions
00491   * @{
00492   */
00493
00494 /** @addtogroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
00495   * @{
00496   */
00497 /* Initialization and de-initialization functions******************************/
00498 HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c);
00499 HAL_StatusTypeDef HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hfmpi2c);
00500 void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c);
00501 void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
00502 /**
00503   * @}
00504   */
00505
00506 /** @addtogroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
00507   * @{
00508   */
00509 /* IO operation functions  ****************************************************/
00510  /******* Blocking mode: Polling */
00511 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00512 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00513 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00514 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00515 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00516 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00517 HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00518
00519  /******* Non-Blocking mode: Interrupt */
00520 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00521 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00522 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
00523 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
00524 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00525 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00526
00527 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00528 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00529 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00530 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00531 HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
00532 HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
00533 HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
00534
00535  /******* Non-Blocking mode: DMA */
00536 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00537 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00538 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
00539 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
00540 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00541 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00542 /**
00543   * @}
00544   */
00545
00546 /** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00547   * @{
00548   */
00549  /******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00550 void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
00551 void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
00552 void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00553 void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00554 void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00555 void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00556 void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00557 void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00558 void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00559 void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00560 void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c);
00561 /**
00562   * @}
00563   */
00564
00565 /** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State and Errors functions
00566   * @{
00567   */
00568 /* Peripheral State, Mode and Errors functions  *********************************/
00569 HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c);
00570 HAL_FMPI2C_ModeTypeDef  HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c);
00571 uint32_t             HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
00572
00573 /**
00574   * @}
00575   */
00576
00577 /**
00578   * @}
00579   */
00580
00581 /* Private constants ---------------------------------------------------------*/
00582 /** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
00583   * @{
00584   */
00585
00586 /**
00587   * @}
00588   */
00589
00590 /* Private macros ------------------------------------------------------------*/
00591 /** @defgroup FMPI2C_Private_Macro FMPI2C Private Macros
00592   * @{
00593   */
00594
00595 #define IS_FMPI2C_ADDRESSING_MODE(MODE)    (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
00596                                           ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
00597
00598 #define IS_FMPI2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
00599                                           ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
00600
00601 #define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == FMPI2C_OA2_NOMASK)  || \
00602                                           ((MASK) == FMPI2C_OA2_MASK01) || \
00603                                           ((MASK) == FMPI2C_OA2_MASK02) || \
00604                                           ((MASK) == FMPI2C_OA2_MASK03) || \
00605                                           ((MASK) == FMPI2C_OA2_MASK04) || \
00606                                           ((MASK) == FMPI2C_OA2_MASK05) || \
00607                                           ((MASK) == FMPI2C_OA2_MASK06) || \
00608                                           ((MASK) == FMPI2C_OA2_MASK07))
00609
00610 #define IS_FMPI2C_GENERAL_CALL(CALL)       (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
00611                                           ((CALL) == FMPI2C_GENERALCALL_ENABLE))
00612
00613 #define IS_FMPI2C_NO_STRETCH(STRETCH)      (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
00614                                           ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
00615
00616 #define IS_FMPI2C_MEMADD_SIZE(SIZE)        (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
00617                                           ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
00618
00619 #define IS_TRANSFER_MODE(MODE)          (((MODE) == FMPI2C_RELOAD_MODE)   || \
00620                                           ((MODE) == FMPI2C_AUTOEND_MODE) || \
00621                                           ((MODE) == FMPI2C_AUTOEND_MODE |FMPI2C_RELOAD_MODE) || \
00622                                           ((MODE) == FMPI2C_SOFTEND_MODE))
00623
00624 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == FMPI2C_GENERATE_STOP)         || \
00625                                           ((REQUEST) == FMPI2C_GENERATE_START_READ)  || \
00626                                           ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
00627                                           ((REQUEST) == FMPI2C_NO_STARTSTOP))
00628
00629 #define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == FMPI2C_FIRST_FRAME)              || \
00630                                                        ((REQUEST) == FMPI2C_NEXT_FRAME)               || \
00631                                                        ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME)     || \
00632                                                        ((REQUEST) == FMPI2C_LAST_FRAME))
00633
00634 #define FMPI2C_RESET_CR2(__HANDLE__)       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
00635
00636 #define FMPI2C_GET_ADDR_MATCH(__HANDLE__)                (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U)
00637 #define FMPI2C_GET_DIR(__HANDLE__)                       (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
00638 #define FMPI2C_GET_STOP_MODE(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
00639 #define FMPI2C_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
00640 #define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)))
00641 #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__)              ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
00642 #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__)              ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
00643
00644
00645 #define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FFU)
00646 #define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FFU)
00647
00648 #define FMPI2C_MEM_ADD_MSB(__ADDRESS__)    ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00649 #define FMPI2C_MEM_ADD_LSB(__ADDRESS__)    ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00650
00651 #define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__)   (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
00652                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
00653 /**
00654   * @}
00655   */
00656
00657 /* Private Functions ---------------------------------------------------------*/
00658 /** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
00659   * @{
00660   */
00661 /* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */
00662 /**
00663   * @}
00664   */
00665
00666 /**
00667   * @}
00668   */
00669
00670 /**
00671   * @}
00672   */
00673 #endif /* STM32F410xx || STM32F446xx */
00674 #ifdef __cplusplus
00675 }
00676 #endif
00677
00678
00679 #endif /* __STM32F4xx_HAL_FMPI2C_H */
00680
00681 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c_ex.c Source File

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stm32f4xx_hal_fmpi2c_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_fmpi2c_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   FMPI2C Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of FMPI2C Extended peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### FMPI2C peripheral Extended features  #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the FMPI2C interface for STM32F4xx
00018        devices contains the following additional features
00019
00020        (+) Possibility to disable or enable Analog Noise Filter
00021        (+) Use of a configured Digital Noise Filter
00022        (+) Disable or enable wakeup from Stop mode
00023
00024                      ##### How to use this driver #####
00025   ==============================================================================
00026   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00027     (#) Configure FMPI2C Analog noise filter using the function HAL_FMPI2CEx_ConfigAnalogFilter()
00028     (#) Configure FMPI2C Digital noise filter using the function HAL_FMPI2CEx_ConfigDigitalFilter()
00029     (#) Configure the enable or disable of FMPI2C Wake Up Mode using the functions :
00030           (++) HAL_FMPI2CEx_EnableWakeUp()
00031           (++) HAL_FMPI2CEx_DisableWakeUp()
00032     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00033           (++) HAL_FMPI2CEx_EnableFastModePlus()
00034           (++) HAL_FMPI2CEx_DisbleFastModePlus()
00035   @endverbatim
00036   ******************************************************************************
00037   * @attention
00038   *
00039   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00040   *
00041   * Redistribution and use in source and binary forms, with or without modification,
00042   * are permitted provided that the following conditions are met:
00043   *   1. Redistributions of source code must retain the above copyright notice,
00044   *      this list of conditions and the following disclaimer.
00045   *   2. Redistributions in binary form must reproduce the above copyright notice,
00046   *      this list of conditions and the following disclaimer in the documentation
00047   *      and/or other materials provided with the distribution.
00048   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00049   *      may be used to endorse or promote products derived from this software
00050   *      without specific prior written permission.
00051   *
00052   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00053   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00054   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00055   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00056   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00057   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00058   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00059   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00060   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00061   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00062   *
00063   ******************************************************************************
00064   */
00065
00066 /* Includes ------------------------------------------------------------------*/
00067 #include "stm32f4xx_hal.h"
00068
00069 /** @addtogroup STM32F4xx_HAL_Driver
00070   * @{
00071   */
00072
00073 /** @defgroup FMPI2CEx FMPI2CEx
00074   * @brief FMPI2C Extended HAL module driver
00075   * @{
00076   */
00077
00078 #ifdef HAL_FMPI2C_MODULE_ENABLED
00079
00080 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
00081
00082 /* Private typedef -----------------------------------------------------------*/
00083 /* Private define ------------------------------------------------------------*/
00084 /* Private macro -------------------------------------------------------------*/
00085 /* Private variables ---------------------------------------------------------*/
00086 /* Private function prototypes -----------------------------------------------*/
00087 /* Private functions ---------------------------------------------------------*/
00088
00089 /** @defgroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
00090   * @{
00091   */
00092
00093 /** @defgroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
00094   * @brief    Extended features functions
00095   *
00096 @verbatim
00097  ===============================================================================
00098                       ##### Extended features functions #####
00099  ===============================================================================
00100     [..] This section provides functions allowing to:
00101       (+) Configure Noise Filters
00102       (+) Configure Wake Up Feature
00103
00104 @endverbatim
00105   * @{
00106   */
00107
00108 /**
00109   * @brief  Configure FMPI2C Analog noise filter.
00110   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00111   *                the configuration information for the specified FMPI2Cx peripheral.
00112   * @param  AnalogFilter New state of the Analog filter.
00113   * @retval HAL status
00114   */
00115 HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter)
00116 {
00117   /* Check the parameters */
00118   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
00119   assert_param(IS_FMPI2C_ANALOG_FILTER(AnalogFilter));
00120
00121   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00122   {
00123     /* Process Locked */
00124     __HAL_LOCK(hfmpi2c);
00125
00126     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
00127
00128     /* Disable the selected FMPI2C peripheral */
00129     __HAL_FMPI2C_DISABLE(hfmpi2c);
00130
00131     /* Reset FMPI2Cx ANOFF bit */
00132     hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_ANFOFF);
00133
00134     /* Set analog filter bit*/
00135     hfmpi2c->Instance->CR1 |= AnalogFilter;
00136
00137     __HAL_FMPI2C_ENABLE(hfmpi2c);
00138
00139     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00140
00141     /* Process Unlocked */
00142     __HAL_UNLOCK(hfmpi2c);
00143
00144     return HAL_OK;
00145   }
00146   else
00147   {
00148     return HAL_BUSY;
00149   }
00150 }
00151
00152 /**
00153   * @brief  Configure FMPI2C Digital noise filter.
00154   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00155   *                the configuration information for the specified FMPI2Cx peripheral.
00156   * @param  DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
00160 {
00161   uint32_t tmpreg = 0U;
00162
00163   /* Check the parameters */
00164   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
00165   assert_param(IS_FMPI2C_DIGITAL_FILTER(DigitalFilter));
00166
00167   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00168   {
00169     /* Process Locked */
00170     __HAL_LOCK(hfmpi2c);
00171
00172     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
00173
00174     /* Disable the selected FMPI2C peripheral */
00175     __HAL_FMPI2C_DISABLE(hfmpi2c);
00176
00177     /* Get the old register value */
00178     tmpreg = hfmpi2c->Instance->CR1;
00179
00180     /* Reset FMPI2Cx DNF bits [11:8] */
00181     tmpreg &= ~(FMPI2C_CR1_DFN);
00182
00183     /* Set FMPI2Cx DNF coefficient */
00184     tmpreg |= DigitalFilter << 8U;
00185
00186     /* Store the new register value */
00187     hfmpi2c->Instance->CR1 = tmpreg;
00188
00189     __HAL_FMPI2C_ENABLE(hfmpi2c);
00190
00191     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00192
00193     /* Process Unlocked */
00194     __HAL_UNLOCK(hfmpi2c);
00195
00196     return HAL_OK;
00197   }
00198   else
00199   {
00200     return HAL_BUSY;
00201   }
00202 }
00203
00204 /**
00205   * @brief  Enable FMPI2C wakeup from stop mode.
00206   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00207   *                the configuration information for the specified FMPI2Cx peripheral.
00208   * @retval HAL status
00209   */
00210 HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
00211 {
00212   /* Check the parameters */
00213   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
00214
00215   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00216   {
00217     /* Process Locked */
00218     __HAL_LOCK(hfmpi2c);
00219
00220     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
00221
00222     /* Disable the selected FMPI2C peripheral */
00223     __HAL_FMPI2C_DISABLE(hfmpi2c);
00224
00225     /* Enable wakeup from stop mode */
00226     hfmpi2c->Instance->CR1 |= FMPI2C_CR1_WUPEN;
00227
00228     __HAL_FMPI2C_ENABLE(hfmpi2c);
00229
00230     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00231
00232     /* Process Unlocked */
00233     __HAL_UNLOCK(hfmpi2c);
00234
00235     return HAL_OK;
00236   }
00237   else
00238   {
00239     return HAL_BUSY;
00240   }
00241 }
00242
00243
00244 /**
00245   * @brief  Disable FMPI2C wakeup from stop mode.
00246   * @param  hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
00247   *                the configuration information for the specified FMPI2Cx peripheral.
00248   * @retval HAL status
00249   */
00250 HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c)
00251 {
00252   /* Check the parameters */
00253   assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
00254
00255   if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
00256   {
00257     /* Process Locked */
00258     __HAL_LOCK(hfmpi2c);
00259
00260     hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
00261
00262     /* Disable the selected FMPI2C peripheral */
00263     __HAL_FMPI2C_DISABLE(hfmpi2c);
00264
00265     /* Enable wakeup from stop mode */
00266     hfmpi2c->Instance->CR1 &= ~(FMPI2C_CR1_WUPEN);
00267
00268     __HAL_FMPI2C_ENABLE(hfmpi2c);
00269
00270     hfmpi2c->State = HAL_FMPI2C_STATE_READY;
00271
00272     /* Process Unlocked */
00273     __HAL_UNLOCK(hfmpi2c);
00274
00275     return HAL_OK;
00276   }
00277   else
00278   {
00279     return HAL_BUSY;
00280   }
00281 }
00282
00283 /**
00284   * @brief Enable the FMPI2C fast mode plus driving capability.
00285   * @param ConfigFastModePlus Selects the pin.
00286   *   This parameter can be one of the @ref FMPI2CEx_FastModePlus values
00287   * @retval None
00288   */
00289 void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00290 {
00291   /* Check the parameter */
00292   assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
00293
00294   /* Enable SYSCFG clock */
00295   __HAL_RCC_SYSCFG_CLK_ENABLE();
00296
00297   /* Enable fast mode plus driving capability for selected pin */
00298   SET_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
00299 }
00300
00301 /**
00302   * @brief Disable the FMPI2C fast mode plus driving capability.
00303   * @param ConfigFastModePlus Selects the pin.
00304   *   This parameter can be one of the @ref FMPI2CEx_FastModePlus values
00305   * @retval None
00306   */
00307 void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00308 {
00309   /* Check the parameter */
00310   assert_param(IS_FMPI2C_FASTMODEPLUS(ConfigFastModePlus));
00311
00312   /* Enable SYSCFG clock */
00313   __HAL_RCC_SYSCFG_CLK_ENABLE();
00314
00315   /* Disable fast mode plus driving capability for selected pin */
00316   CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus);
00317 }
00318
00319 /**
00320   * @}
00321   */
00322
00323 /**
00324   * @}
00325   */
00326 #endif /* STM32F410xx || STM32F446xx */
00327 #endif /* HAL_FMPI2C_MODULE_ENABLED */
00328 /**
00329   * @}
00330   */
00331
00332 /**
00333   * @}
00334   */
00335
00336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_fmpi2c_ex.h Source File

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stm32f4xx_hal_fmpi2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_fmpi2c_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of FMPI2C HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_FMPI2C_EX_H
00040 #define __STM32F4xx_HAL_FMPI2C_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f4xx_hal_def.h"
00050
00051 /** @addtogroup STM32F4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup FMPI2CEx
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /* Exported constants --------------------------------------------------------*/
00061
00062 /** @defgroup FMPI2CEx_Exported_Constants FMPI2C Extended Exported Constants
00063   * @{
00064   */
00065
00066 /** @defgroup FMPI2CEx_Analog_Filter FMPI2C Extended Analog Filter
00067   * @{
00068   */
00069 #define FMPI2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000U)
00070 #define FMPI2C_ANALOGFILTER_DISABLE       FMPI2C_CR1_ANFOFF
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup FMPI2CEx_FastModePlus FMPI2C Extended Fast Mode Plus
00076   * @{
00077   */
00078 #define FMPI2C_FASTMODEPLUS_SCL            SYSCFG_CFGR_FMPI2C1_SCL  /*!< Enable Fast Mode Plus on FMPI2C1 SCL pins       */
00079 #define FMPI2C_FASTMODEPLUS_SDA            SYSCFG_CFGR_FMPI2C1_SDA  /*!< Enable Fast Mode Plus on FMPI2C1 SDA pins       */
00080 /**
00081   * @}
00082   */
00083
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported macro ------------------------------------------------------------*/
00089 /* Exported functions --------------------------------------------------------*/
00090
00091 /** @addtogroup FMPI2CEx_Exported_Functions FMPI2C Extended Exported Functions
00092   * @{
00093   */
00094
00095 /** @addtogroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
00096   * @brief    Extended features functions
00097   * @{
00098   */
00099
00100 /* Peripheral Control functions  ************************************************/
00101 HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t AnalogFilter);
00102 HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter);
00103 HAL_StatusTypeDef HAL_FMPI2CEx_EnableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c);
00104 HAL_StatusTypeDef HAL_FMPI2CEx_DisableWakeUp (FMPI2C_HandleTypeDef *hfmpi2c);
00105 void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00106 void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00107
00108 /* Private constants ---------------------------------------------------------*/
00109 /** @defgroup FMPI2CEx_Private_Constants FMPI2C Extended Private Constants
00110   * @{
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Private macros ------------------------------------------------------------*/
00118 /** @defgroup FMPI2CEx_Private_Macro FMPI2C Extended Private Macros
00119   * @{
00120   */
00121 #define IS_FMPI2C_ANALOG_FILTER(FILTER)    (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
00122                                             ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
00123
00124 #define IS_FMPI2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00125
00126 #define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
00127                                             (((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
00128 /**
00129   * @}
00130   */
00131
00132 /* Private Functions ---------------------------------------------------------*/
00133 /** @defgroup FMPI2CEx_Private_Functions FMPI2C Extended Private Functions
00134   * @{
00135   */
00136 /* Private functions are defined in stm32f4xx_hal_fmpi2c_ex.c file */
00137 /**
00138   * @}
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /**
00146   * @}
00147   */
00148
00149 /**
00150   * @}
00151   */
00152
00153 /**
00154   * @}
00155   */
00156 #endif /* STM32F410xx || STM32F446xx */
00157 #ifdef __cplusplus
00158 }
00159 #endif
00160
00161 #endif /* __STM32F4xx_HAL_FMPI2C_EX_H */
00162
00163
00164 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_gpio.c Source File

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  • STM32F4xx_HAL_Driver
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stm32f4xx_hal_gpio.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   GPIO HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### GPIO Peripheral features #####
00016   ==============================================================================
00017   [..]
00018   Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
00019   port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
00020   in several modes:
00021   (+) Input mode
00022   (+) Analog mode
00023   (+) Output mode
00024   (+) Alternate function mode
00025   (+) External interrupt/event lines
00026
00027   [..]
00028   During and just after reset, the alternate functions and external interrupt
00029   lines are not active and the I/O ports are configured in input floating mode.
00030
00031   [..]
00032   All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00033   activated or not.
00034
00035   [..]
00036   In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00037   type and the IO speed can be selected depending on the VDD value.
00038
00039   [..]
00040   All ports have external interrupt/event capability. To use external interrupt
00041   lines, the port must be configured in input mode. All available GPIO pins are
00042   connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00043
00044   [..]
00045   The external interrupt/event controller consists of up to 23 edge detectors
00046   (16 lines are connected to GPIO) for generating event/interrupt requests (each
00047   input line can be independently configured to select the type (interrupt or event)
00048   and the corresponding trigger event (rising or falling or both). Each line can
00049   also be masked independently.
00050
00051                      ##### How to use this driver #####
00052   ==============================================================================
00053   [..]
00054     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00055
00056     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00057         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00058         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00059              structure.
00060         (++) In case of Output or alternate function mode selection: the speed is
00061              configured through "Speed" member from GPIO_InitTypeDef structure.
00062         (++) In alternate mode is selection, the alternate function connected to the IO
00063              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00064         (++) Analog mode is required when a pin is to be used as ADC channel
00065              or DAC output.
00066         (++) In case of external interrupt/event selection the "Mode" member from
00067              GPIO_InitTypeDef structure select the type (interrupt or event) and
00068              the corresponding trigger event (rising or falling or both).
00069
00070     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00071         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00072         HAL_NVIC_EnableIRQ().
00073
00074     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00075
00076     (#) To set/reset the level of a pin configured in output mode use
00077         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00078
00079     (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00080
00081
00082     (#) During and just after reset, the alternate functions are not
00083         active and the GPIO pins are configured in input floating mode (except JTAG
00084         pins).
00085
00086     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00087         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00088         priority over the GPIO function.
00089
00090     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00091         general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
00092         The HSE has priority over the GPIO function.
00093
00094   @endverbatim
00095   ******************************************************************************
00096   * @attention
00097   *
00098   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00099   *
00100   * Redistribution and use in source and binary forms, with or without modification,
00101   * are permitted provided that the following conditions are met:
00102   *   1. Redistributions of source code must retain the above copyright notice,
00103   *      this list of conditions and the following disclaimer.
00104   *   2. Redistributions in binary form must reproduce the above copyright notice,
00105   *      this list of conditions and the following disclaimer in the documentation
00106   *      and/or other materials provided with the distribution.
00107   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00108   *      may be used to endorse or promote products derived from this software
00109   *      without specific prior written permission.
00110   *
00111   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00112   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00113   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00114   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00115   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00116   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00117   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00118   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00119   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00120   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00121   *
00122   ******************************************************************************
00123   */
00124
00125 /* Includes ------------------------------------------------------------------*/
00126 #include "stm32f4xx_hal.h"
00127
00128 /** @addtogroup STM32F4xx_HAL_Driver
00129   * @{
00130   */
00131
00132 /** @defgroup GPIO GPIO
00133   * @brief GPIO HAL module driver
00134   * @{
00135   */
00136
00137 #ifdef HAL_GPIO_MODULE_ENABLED
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
00142   * @{
00143   */
00144 #define GPIO_MODE             ((uint32_t)0x00000003U)
00145 #define EXTI_MODE             ((uint32_t)0x10000000U)
00146 #define GPIO_MODE_IT          ((uint32_t)0x00010000U)
00147 #define GPIO_MODE_EVT         ((uint32_t)0x00020000U)
00148 #define RISING_EDGE           ((uint32_t)0x00100000U)
00149 #define FALLING_EDGE          ((uint32_t)0x00200000U)
00150 #define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010U)
00151
00152 #define GPIO_NUMBER           ((uint32_t)16U)
00153 /**
00154   * @}
00155   */
00156 /* Private macro -------------------------------------------------------------*/
00157 /* Private variables ---------------------------------------------------------*/
00158 /* Private function prototypes -----------------------------------------------*/
00159 /* Private functions ---------------------------------------------------------*/
00160 /* Exported functions --------------------------------------------------------*/
00161 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00162   * @{
00163   */
00164
00165 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
00166  *  @brief    Initialization and Configuration functions
00167  *
00168 @verbatim
00169  ===============================================================================
00170               ##### Initialization and de-initialization functions #####
00171  ===============================================================================
00172   [..]
00173     This section provides functions allowing to initialize and de-initialize the GPIOs
00174     to be ready for use.
00175
00176 @endverbatim
00177   * @{
00178   */
00179
00180
00181 /**
00182   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00183   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
00184   *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
00185   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
00186   *         the configuration information for the specified GPIO peripheral.
00187   * @retval None
00188   */
00189 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00190 {
00191   uint32_t position;
00192   uint32_t ioposition = 0x00U;
00193   uint32_t iocurrent = 0x00U;
00194   uint32_t temp = 0x00U;
00195
00196   /* Check the parameters */
00197   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00198   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00199   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00200   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00201
00202   /* Configure the port pins */
00203   for(position = 0U; position < GPIO_NUMBER; position++)
00204   {
00205     /* Get the IO position */
00206     ioposition = ((uint32_t)0x01U) << position;
00207     /* Get the current IO position */
00208     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
00209
00210     if(iocurrent == ioposition)
00211     {
00212       /*--------------------- GPIO Mode Configuration ------------------------*/
00213       /* In case of Alternate function mode selection */
00214       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00215       {
00216         /* Check the Alternate function parameter */
00217         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00218         /* Configure Alternate function mapped with the current IO */
00219         temp = GPIOx->AFR[position >> 3U];
00220         temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
00221         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
00222         GPIOx->AFR[position >> 3U] = temp;
00223       }
00224
00225       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00226       temp = GPIOx->MODER;
00227       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
00228       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
00229       GPIOx->MODER = temp;
00230
00231       /* In case of Output or Alternate function mode selection */
00232       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
00233          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00234       {
00235         /* Check the Speed parameter */
00236         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00237         /* Configure the IO Speed */
00238         temp = GPIOx->OSPEEDR;
00239         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
00240         temp |= (GPIO_Init->Speed << (position * 2U));
00241         GPIOx->OSPEEDR = temp;
00242
00243         /* Configure the IO Output Type */
00244         temp = GPIOx->OTYPER;
00245         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
00246         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
00247         GPIOx->OTYPER = temp;
00248       }
00249
00250       /* Activate the Pull-up or Pull down resistor for the current IO */
00251       temp = GPIOx->PUPDR;
00252       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
00253       temp |= ((GPIO_Init->Pull) << (position * 2U));
00254       GPIOx->PUPDR = temp;
00255
00256       /*--------------------- EXTI Mode Configuration ------------------------*/
00257       /* Configure the External Interrupt or event for the current IO */
00258       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00259       {
00260         /* Enable SYSCFG Clock */
00261         __HAL_RCC_SYSCFG_CLK_ENABLE();
00262
00263         temp = SYSCFG->EXTICR[position >> 2U];
00264         temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03U)));
00265         temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
00266         SYSCFG->EXTICR[position >> 2U] = temp;
00267
00268         /* Clear EXTI line configuration */
00269         temp = EXTI->IMR;
00270         temp &= ~((uint32_t)iocurrent);
00271         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00272         {
00273           temp |= iocurrent;
00274         }
00275         EXTI->IMR = temp;
00276
00277         temp = EXTI->EMR;
00278         temp &= ~((uint32_t)iocurrent);
00279         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00280         {
00281           temp |= iocurrent;
00282         }
00283         EXTI->EMR = temp;
00284
00285         /* Clear Rising Falling edge configuration */
00286         temp = EXTI->RTSR;
00287         temp &= ~((uint32_t)iocurrent);
00288         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00289         {
00290           temp |= iocurrent;
00291         }
00292         EXTI->RTSR = temp;
00293
00294         temp = EXTI->FTSR;
00295         temp &= ~((uint32_t)iocurrent);
00296         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00297         {
00298           temp |= iocurrent;
00299         }
00300         EXTI->FTSR = temp;
00301       }
00302     }
00303   }
00304 }
00305
00306 /**
00307   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
00308   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
00309   *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
00310   * @param  GPIO_Pin: specifies the port bit to be written.
00311   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00312   * @retval None
00313   */
00314 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00315 {
00316   uint32_t position;
00317   uint32_t ioposition = 0x00U;
00318   uint32_t iocurrent = 0x00U;
00319   uint32_t tmp = 0x00U;
00320
00321   /* Check the parameters */
00322   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00323
00324   /* Configure the port pins */
00325   for(position = 0U; position < GPIO_NUMBER; position++)
00326   {
00327     /* Get the IO position */
00328     ioposition = ((uint32_t)0x01U) << position;
00329     /* Get the current IO position */
00330     iocurrent = (GPIO_Pin) & ioposition;
00331
00332     if(iocurrent == ioposition)
00333     {
00334       /*------------------------- GPIO Mode Configuration --------------------*/
00335       /* Configure IO Direction in Input Floating Mode */
00336       GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
00337
00338       /* Configure the default Alternate Function in current IO */
00339       GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
00340
00341       /* Configure the default value for IO Speed */
00342       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
00343
00344       /* Configure the default value IO Output Type */
00345       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
00346
00347       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00348       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
00349
00350       /*------------------------- EXTI Mode Configuration --------------------*/
00351       tmp = SYSCFG->EXTICR[position >> 2U];
00352       tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U)));
00353       if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
00354       {
00355         /* Configure the External Interrupt or event for the current IO */
00356         tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U));
00357         SYSCFG->EXTICR[position >> 2U] &= ~tmp;
00358
00359         /* Clear EXTI line configuration */
00360         EXTI->IMR &= ~((uint32_t)iocurrent);
00361         EXTI->EMR &= ~((uint32_t)iocurrent);
00362
00363         /* Clear Rising Falling edge configuration */
00364         EXTI->RTSR &= ~((uint32_t)iocurrent);
00365         EXTI->FTSR &= ~((uint32_t)iocurrent);
00366       }
00367     }
00368   }
00369 }
00370
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00376  *  @brief   GPIO Read and Write
00377  *
00378 @verbatim
00379  ===============================================================================
00380                        ##### IO operation functions #####
00381  ===============================================================================
00382
00383 @endverbatim
00384   * @{
00385   */
00386
00387 /**
00388   * @brief  Reads the specified input port pin.
00389   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
00390   *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
00391   * @param  GPIO_Pin: specifies the port bit to read.
00392   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00393   * @retval The input port pin value.
00394   */
00395 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00396 {
00397   GPIO_PinState bitstatus;
00398
00399   /* Check the parameters */
00400   assert_param(IS_GPIO_PIN(GPIO_Pin));
00401
00402   if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
00403   {
00404     bitstatus = GPIO_PIN_SET;
00405   }
00406   else
00407   {
00408     bitstatus = GPIO_PIN_RESET;
00409   }
00410   return bitstatus;
00411 }
00412
00413 /**
00414   * @brief  Sets or clears the selected data port bit.
00415   *
00416   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
00417   *         accesses. In this way, there is no risk of an IRQ occurring between
00418   *         the read and the modify access.
00419   *
00420   * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
00421   *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
00422   * @param  GPIO_Pin: specifies the port bit to be written.
00423   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00424   * @param  PinState: specifies the value to be written to the selected bit.
00425   *          This parameter can be one of the GPIO_PinState enum values:
00426   *            @arg GPIO_PIN_RESET: to clear the port pin
00427   *            @arg GPIO_PIN_SET: to set the port pin
00428   * @retval None
00429   */
00430 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00431 {
00432   /* Check the parameters */
00433   assert_param(IS_GPIO_PIN(GPIO_Pin));
00434   assert_param(IS_GPIO_PIN_ACTION(PinState));
00435
00436   if(PinState != GPIO_PIN_RESET)
00437   {
00438     GPIOx->BSRR = GPIO_Pin;
00439   }
00440   else
00441   {
00442     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
00443   }
00444 }
00445
00446 /**
00447   * @brief  Toggles the specified GPIO pins.
00448   * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
00449   *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
00450   * @param  GPIO_Pin: Specifies the pins to be toggled.
00451   * @retval None
00452   */
00453 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00454 {
00455   /* Check the parameters */
00456   assert_param(IS_GPIO_PIN(GPIO_Pin));
00457
00458   GPIOx->ODR ^= GPIO_Pin;
00459 }
00460
00461 /**
00462   * @brief  Locks GPIO Pins configuration registers.
00463   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00464   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00465   * @note   The configuration of the locked GPIO pins can no longer be modified
00466   *         until the next reset.
00467   * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family
00468   * @param  GPIO_Pin: specifies the port bit to be locked.
00469   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
00470   * @retval None
00471   */
00472 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00473 {
00474   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00475
00476   /* Check the parameters */
00477   assert_param(IS_GPIO_PIN(GPIO_Pin));
00478
00479   /* Apply lock key write sequence */
00480   tmp |= GPIO_Pin;
00481   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00482   GPIOx->LCKR = tmp;
00483   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00484   GPIOx->LCKR = GPIO_Pin;
00485   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00486   GPIOx->LCKR = tmp;
00487   /* Read LCKK bit*/
00488   tmp = GPIOx->LCKR;
00489
00490  if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
00491   {
00492     return HAL_OK;
00493   }
00494   else
00495   {
00496     return HAL_ERROR;
00497   }
00498 }
00499
00500 /**
00501   * @brief  This function handles EXTI interrupt request.
00502   * @param  GPIO_Pin: Specifies the pins connected EXTI line
00503   * @retval None
00504   */
00505 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00506 {
00507   /* EXTI line interrupt detected */
00508   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
00509   {
00510     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00511     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00512   }
00513 }
00514
00515 /**
00516   * @brief  EXTI line detection callbacks.
00517   * @param  GPIO_Pin: Specifies the pins connected EXTI line
00518   * @retval None
00519   */
00520 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00521 {
00522   /* Prevent unused argument(s) compilation warning */
00523   UNUSED(GPIO_Pin);
00524   /* NOTE: This function Should not be modified, when the callback is needed,
00525            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00526    */
00527 }
00528
00529 /**
00530   * @}
00531   */
00532
00533
00534 /**
00535   * @}
00536   */
00537
00538 #endif /* HAL_GPIO_MODULE_ENABLED */
00539 /**
00540   * @}
00541   */
00542
00543 /**
00544   * @}
00545   */
00546
00547 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_gpio.h Source File

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stm32f4xx_hal_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of GPIO HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_GPIO_H
00040 #define __STM32F4xx_HAL_GPIO_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup GPIO
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief GPIO Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
00068                            This parameter can be any value of @ref GPIO_pins_define */
00069
00070   uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
00071                            This parameter can be a value of @ref GPIO_mode_define */
00072
00073   uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00074                            This parameter can be a value of @ref GPIO_pull_define */
00075
00076   uint32_t Speed;     /*!< Specifies the speed for the selected pins.
00077                            This parameter can be a value of @ref GPIO_speed_define */
00078
00079   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
00080                             This parameter can be a value of @ref GPIO_Alternate_function_selection */
00081 }GPIO_InitTypeDef;
00082
00083 /**
00084   * @brief  GPIO Bit SET and Bit RESET enumeration
00085   */
00086 typedef enum
00087 {
00088   GPIO_PIN_RESET = 0,
00089   GPIO_PIN_SET
00090 }GPIO_PinState;
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported constants --------------------------------------------------------*/
00096
00097 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup GPIO_pins_define GPIO pins define
00102   * @{
00103   */
00104 #define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
00105 #define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
00106 #define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
00107 #define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
00108 #define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
00109 #define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
00110 #define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
00111 #define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
00112 #define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
00113 #define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
00114 #define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
00115 #define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
00116 #define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
00117 #define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
00118 #define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
00119 #define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
00120 #define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
00121
00122 #define GPIO_PIN_MASK              ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup GPIO_mode_define GPIO mode define
00128   * @brief GPIO Configuration Mode
00129   *        Elements values convention: 0xX0yz00YZ
00130   *           - X  : GPIO mode or EXTI Mode
00131   *           - y  : External IT or Event trigger detection
00132   *           - z  : IO configuration on External IT or Event
00133   *           - Y  : Output type (Push Pull or Open Drain)
00134   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00135   * @{
00136   */
00137 #define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000U)   /*!< Input Floating Mode                   */
00138 #define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001U)   /*!< Output Push Pull Mode                 */
00139 #define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011U)   /*!< Output Open Drain Mode                */
00140 #define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002U)   /*!< Alternate Function Push Pull Mode     */
00141 #define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012U)   /*!< Alternate Function Open Drain Mode    */
00142
00143 #define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003U)   /*!< Analog Mode  */
00144
00145 #define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
00146 #define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
00147 #define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00148
00149 #define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000U)   /*!< External Event Mode with Rising edge trigger detection               */
00150 #define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000U)   /*!< External Event Mode with Falling edge trigger detection              */
00151 #define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup GPIO_speed_define  GPIO speed define
00157   * @brief GPIO Output Maximum frequency
00158   * @{
00159   */
00160 #define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000U)  /*!< IO works at 2 MHz, please refer to the product datasheet */
00161 #define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001U)  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
00162 #define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002U)  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
00163 #define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003U)  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
00164 /**
00165   * @}
00166   */
00167
00168  /** @defgroup GPIO_pull_define GPIO pull define
00169    * @brief GPIO Pull-Up or Pull-Down Activation
00170    * @{
00171    */
00172 #define  GPIO_NOPULL        ((uint32_t)0x00000000U)   /*!< No Pull-up or Pull-down activation  */
00173 #define  GPIO_PULLUP        ((uint32_t)0x00000001U)   /*!< Pull-up activation                  */
00174 #define  GPIO_PULLDOWN      ((uint32_t)0x00000002U)   /*!< Pull-down activation                */
00175 /**
00176   * @}
00177   */
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported macro ------------------------------------------------------------*/
00184 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00185   * @{
00186   */
00187
00188 /**
00189   * @brief  Checks whether the specified EXTI line flag is set or not.
00190   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
00191   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00192   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00193   */
00194 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
00195
00196 /**
00197   * @brief  Clears the EXTI's line pending flags.
00198   * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
00199   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00200   * @retval None
00201   */
00202 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
00203
00204 /**
00205   * @brief  Checks whether the specified EXTI line is asserted or not.
00206   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00207   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00208   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00209   */
00210 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
00211
00212 /**
00213   * @brief  Clears the EXTI's line pending bits.
00214   * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
00215   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00216   * @retval None
00217   */
00218 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
00219
00220 /**
00221   * @brief  Generates a Software interrupt on selected EXTI line.
00222   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00223   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00224   * @retval None
00225   */
00226 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
00227 /**
00228   * @}
00229   */
00230
00231 /* Include GPIO HAL Extension module */
00232 #include "stm32f4xx_hal_gpio_ex.h"
00233
00234 /* Exported functions --------------------------------------------------------*/
00235 /** @addtogroup GPIO_Exported_Functions
00236   * @{
00237   */
00238
00239 /** @addtogroup GPIO_Exported_Functions_Group1
00240   * @{
00241   */
00242 /* Initialization and de-initialization functions *****************************/
00243 void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00244 void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00245 /**
00246   * @}
00247   */
00248
00249 /** @addtogroup GPIO_Exported_Functions_Group2
00250   * @{
00251   */
00252 /* IO operation functions *****************************************************/
00253 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00254 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00255 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00256 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00257 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00258 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00259
00260 /**
00261   * @}
00262   */
00263
00264 /**
00265   * @}
00266   */
00267 /* Private types -------------------------------------------------------------*/
00268 /* Private variables ---------------------------------------------------------*/
00269 /* Private constants ---------------------------------------------------------*/
00270 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00271   * @{
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 /* Private macros ------------------------------------------------------------*/
00279 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00280   * @{
00281   */
00282 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00283 #define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
00284 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
00285                             ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
00286                             ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
00287                             ((MODE) == GPIO_MODE_AF_PP)              ||\
00288                             ((MODE) == GPIO_MODE_AF_OD)              ||\
00289                             ((MODE) == GPIO_MODE_IT_RISING)          ||\
00290                             ((MODE) == GPIO_MODE_IT_FALLING)         ||\
00291                             ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
00292                             ((MODE) == GPIO_MODE_EVT_RISING)         ||\
00293                             ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
00294                             ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
00295                             ((MODE) == GPIO_MODE_ANALOG))
00296 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
00297                               ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
00298 #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
00299                             ((PULL) == GPIO_PULLDOWN))
00300 /**
00301   * @}
00302   */
00303
00304 /* Private functions ---------------------------------------------------------*/
00305 /** @defgroup GPIO_Private_Functions GPIO Private Functions
00306   * @{
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 #ifdef __cplusplus
00322 }
00323 #endif
00324
00325 #endif /* __STM32F4xx_HAL_GPIO_H */
00326
00327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_gpio_ex.h Source File

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stm32f4xx_hal_gpio_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of GPIO HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_GPIO_EX_H
00040 #define __STM32F4xx_HAL_GPIO_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup GPIOEx GPIOEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
00064   * @{
00065   */
00066
00067 /*------------------------------------------ STM32F429xx/STM32F439xx ---------*/
00068 #if defined(STM32F429xx) || defined(STM32F439xx)
00069 /**
00070   * @brief   AF 0 selection
00071   */
00072 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00073 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00074 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00075 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00076 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00077
00078 /**
00079   * @brief   AF 1 selection
00080   */
00081 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00082 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00083
00084 /**
00085   * @brief   AF 2 selection
00086   */
00087 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00088 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00089 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00090
00091 /**
00092   * @brief   AF 3 selection
00093   */
00094 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00095 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00096 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00097 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00098
00099 /**
00100   * @brief   AF 4 selection
00101   */
00102 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00103 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00104 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00105
00106 /**
00107   * @brief   AF 5 selection
00108   */
00109 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
00110 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00111 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
00112 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
00113 #define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
00114 #define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
00115 #define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
00116
00117 /**
00118   * @brief   AF 6 selection
00119   */
00120 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00121 #define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
00122 #define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
00123
00124 /**
00125   * @brief   AF 7 selection
00126   */
00127 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00128 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00129 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
00130 #define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
00131
00132 /**
00133   * @brief   AF 8 selection
00134   */
00135 #define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
00136 #define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
00137 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00138 #define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
00139 #define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
00140
00141 /**
00142   * @brief   AF 9 selection
00143   */
00144 #define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
00145 #define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */
00146 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
00147 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
00148 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
00149 #define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */
00150
00151 /**
00152   * @brief   AF 10 selection
00153   */
00154 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00155 #define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
00156
00157 /**
00158   * @brief   AF 11 selection
00159   */
00160 #define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
00161
00162 /**
00163   * @brief   AF 12 selection
00164   */
00165 #define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
00166 #define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
00167 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
00168
00169 /**
00170   * @brief   AF 13 selection
00171   */
00172 #define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
00173
00174 /**
00175   * @brief   AF 14 selection
00176   */
00177 #define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */
00178
00179 /**
00180   * @brief   AF 15 selection
00181   */
00182 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00183 #endif /* STM32F429xx || STM32F439xx */
00184 /*----------------------------------------------------------------------------*/
00185
00186 /*---------------------------------- STM32F427xx/STM32F437xx------------------*/
00187 #if defined(STM32F427xx) || defined(STM32F437xx)
00188 /**
00189   * @brief   AF 0 selection
00190   */
00191 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00192 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00193 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00194 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00195 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00196
00197 /**
00198   * @brief   AF 1 selection
00199   */
00200 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00201 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00202
00203 /**
00204   * @brief   AF 2 selection
00205   */
00206 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00207 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00208 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00209
00210 /**
00211   * @brief   AF 3 selection
00212   */
00213 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00214 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00215 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00216 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00217
00218 /**
00219   * @brief   AF 4 selection
00220   */
00221 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00222 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00223 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00224
00225 /**
00226   * @brief   AF 5 selection
00227   */
00228 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
00229 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00230 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
00231 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
00232 #define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
00233 #define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
00234 /** @brief  GPIO_Legacy
00235   */
00236 #define GPIO_AF5_I2S3ext       GPIO_AF5_SPI3    /* I2S3ext_SD Alternate Function mapping  */
00237
00238 /**
00239   * @brief   AF 6 selection
00240   */
00241 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00242 #define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
00243 #define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
00244
00245 /**
00246   * @brief   AF 7 selection
00247   */
00248 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00249 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00250 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
00251 #define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
00252
00253 /**
00254   * @brief   AF 8 selection
00255   */
00256 #define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
00257 #define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
00258 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00259 #define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
00260 #define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
00261
00262 /**
00263   * @brief   AF 9 selection
00264   */
00265 #define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
00266 #define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
00267 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
00268 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
00269 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
00270
00271 /**
00272   * @brief   AF 10 selection
00273   */
00274 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00275 #define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
00276
00277 /**
00278   * @brief   AF 11 selection
00279   */
00280 #define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
00281
00282 /**
00283   * @brief   AF 12 selection
00284   */
00285 #define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
00286 #define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
00287 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
00288
00289 /**
00290   * @brief   AF 13 selection
00291   */
00292 #define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
00293
00294 /**
00295   * @brief   AF 15 selection
00296   */
00297 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00298 #endif /* STM32F427xx || STM32F437xx */
00299 /*----------------------------------------------------------------------------*/
00300
00301 /*---------------------------------- STM32F407xx/STM32F417xx------------------*/
00302 #if defined(STM32F407xx) || defined(STM32F417xx)
00303 /**
00304   * @brief   AF 0 selection
00305   */
00306 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00307 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00308 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00309 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00310 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00311
00312 /**
00313   * @brief   AF 1 selection
00314   */
00315 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00316 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00317
00318 /**
00319   * @brief   AF 2 selection
00320   */
00321 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00322 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00323 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00324
00325 /**
00326   * @brief   AF 3 selection
00327   */
00328 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00329 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00330 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00331 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00332
00333 /**
00334   * @brief   AF 4 selection
00335   */
00336 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00337 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00338 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00339
00340 /**
00341   * @brief   AF 5 selection
00342   */
00343 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
00344 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00345 #define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
00346
00347 /**
00348   * @brief   AF 6 selection
00349   */
00350 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00351 #define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
00352
00353 /**
00354   * @brief   AF 7 selection
00355   */
00356 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00357 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00358 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
00359 #define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
00360
00361 /**
00362   * @brief   AF 8 selection
00363   */
00364 #define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
00365 #define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
00366 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00367
00368 /**
00369   * @brief   AF 9 selection
00370   */
00371 #define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
00372 #define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
00373 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
00374 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
00375 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
00376
00377 /**
00378   * @brief   AF 10 selection
00379   */
00380 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00381 #define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
00382
00383 /**
00384   * @brief   AF 11 selection
00385   */
00386 #define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
00387
00388 /**
00389   * @brief   AF 12 selection
00390   */
00391 #define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FSMC Alternate Function mapping                     */
00392 #define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
00393 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
00394
00395 /**
00396   * @brief   AF 13 selection
00397   */
00398 #define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
00399
00400 /**
00401   * @brief   AF 15 selection
00402   */
00403 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00404 #endif /* STM32F407xx || STM32F417xx */
00405 /*----------------------------------------------------------------------------*/
00406
00407 /*---------------------------------- STM32F405xx/STM32F415xx------------------*/
00408 #if defined(STM32F405xx) || defined(STM32F415xx)
00409 /**
00410   * @brief   AF 0 selection
00411   */
00412 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00413 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00414 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00415 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00416 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00417
00418 /**
00419   * @brief   AF 1 selection
00420   */
00421 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00422 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00423
00424 /**
00425   * @brief   AF 2 selection
00426   */
00427 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00428 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00429 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00430
00431 /**
00432   * @brief   AF 3 selection
00433   */
00434 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00435 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00436 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00437 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00438
00439 /**
00440   * @brief   AF 4 selection
00441   */
00442 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00443 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00444 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00445
00446 /**
00447   * @brief   AF 5 selection
00448   */
00449 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
00450 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00451 #define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
00452
00453 /**
00454   * @brief   AF 6 selection
00455   */
00456 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00457 #define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
00458
00459 /**
00460   * @brief   AF 7 selection
00461   */
00462 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00463 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00464 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
00465 #define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
00466
00467 /**
00468   * @brief   AF 8 selection
00469   */
00470 #define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
00471 #define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
00472 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00473
00474 /**
00475   * @brief   AF 9 selection
00476   */
00477 #define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
00478 #define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
00479 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
00480 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
00481 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
00482
00483 /**
00484   * @brief   AF 10 selection
00485   */
00486 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00487 #define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
00488
00489 /**
00490   * @brief   AF 12 selection
00491   */
00492 #define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FSMC Alternate Function mapping                     */
00493 #define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
00494 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
00495
00496 /**
00497   * @brief   AF 15 selection
00498   */
00499 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00500 #endif /* STM32F405xx || STM32F415xx */
00501
00502 /*----------------------------------------------------------------------------*/
00503
00504 /*---------------------------------------- STM32F401xx------------------------*/
00505 #if defined(STM32F401xC) || defined(STM32F401xE)
00506 /**
00507   * @brief   AF 0 selection
00508   */
00509 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00510 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00511 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00512 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00513 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00514
00515 /**
00516   * @brief   AF 1 selection
00517   */
00518 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00519 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00520
00521 /**
00522   * @brief   AF 2 selection
00523   */
00524 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00525 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00526 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00527
00528 /**
00529   * @brief   AF 3 selection
00530   */
00531 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00532 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00533 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00534
00535 /**
00536   * @brief   AF 4 selection
00537   */
00538 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00539 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00540 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00541
00542 /**
00543   * @brief   AF 5 selection
00544   */
00545 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
00546 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00547 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
00548 #define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping   */
00549
00550 /**
00551   * @brief   AF 6 selection
00552   */
00553 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00554 #define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
00555
00556 /**
00557   * @brief   AF 7 selection
00558   */
00559 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00560 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00561 #define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
00562
00563 /**
00564   * @brief   AF 8 selection
00565   */
00566 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00567
00568 /**
00569   * @brief   AF 9 selection
00570   */
00571 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
00572 #define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */
00573 #define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping  */
00574
00575
00576 /**
00577   * @brief   AF 10 selection
00578   */
00579 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00580
00581 /**
00582   * @brief   AF 12 selection
00583   */
00584 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */
00585
00586 /**
00587   * @brief   AF 15 selection
00588   */
00589 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00590 #endif /* STM32F401xC || STM32F401xE */
00591 /*----------------------------------------------------------------------------*/
00592 /*---------------------------------------- STM32F411xx------------------------*/
00593 #if defined(STM32F411xE)
00594 /**
00595   * @brief   AF 0 selection
00596   */
00597 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00598 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00599 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00600 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00601 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00602
00603 /**
00604   * @brief   AF 1 selection
00605   */
00606 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00607 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00608
00609 /**
00610   * @brief   AF 2 selection
00611   */
00612 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00613 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00614 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00615
00616 /**
00617   * @brief   AF 3 selection
00618   */
00619 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00620 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00621 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00622
00623 /**
00624   * @brief   AF 4 selection
00625   */
00626 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00627 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00628 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00629
00630 /**
00631   * @brief   AF 5 selection
00632   */
00633 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
00634 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00635 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
00636 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
00637 #define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
00638
00639 /**
00640   * @brief   AF 6 selection
00641   */
00642 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */
00643 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00644 #define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4/I2S4 Alternate Function mapping  */
00645 #define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */
00646 #define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
00647
00648 /**
00649   * @brief   AF 7 selection
00650   */
00651 #define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */
00652 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00653 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00654 #define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
00655
00656 /**
00657   * @brief   AF 8 selection
00658   */
00659 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00660
00661 /**
00662   * @brief   AF 9 selection
00663   */
00664 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
00665 #define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */
00666 #define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping  */
00667
00668 /**
00669   * @brief   AF 10 selection
00670   */
00671 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00672
00673 /**
00674   * @brief   AF 12 selection
00675   */
00676 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */
00677
00678 /**
00679   * @brief   AF 15 selection
00680   */
00681 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00682 #endif /* STM32F411xE */
00683
00684 /*---------------------------------------- STM32F410xx------------------------*/
00685 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00686 /**
00687   * @brief   AF 0 selection
00688   */
00689 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00690 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00691 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00692 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00693 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00694
00695 /**
00696   * @brief   AF 1 selection
00697   */
00698 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00699 #define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */
00700
00701 /**
00702   * @brief   AF 2 selection
00703   */
00704 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00705
00706 /**
00707   * @brief   AF 3 selection
00708   */
00709 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00710 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00711
00712 /**
00713   * @brief   AF 4 selection
00714   */
00715 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00716 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00717 #define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */
00718
00719 /**
00720   * @brief   AF 5 selection
00721   */
00722 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
00723 #if defined(STM32F410Cx) || defined(STM32F410Rx)
00724 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00725 #endif /* STM32F410Cx || STM32F410Rx */
00726
00727 /**
00728   * @brief   AF 6 selection
00729   */
00730 #define GPIO_AF6_SPI1          ((uint8_t)0x06U)  /* SPI1 Alternate Function mapping  */
00731 #if defined(STM32F410Cx) || defined(STM32F410Rx)
00732 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */
00733 #endif /* STM32F410Cx || STM32F410Rx */
00734 #define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */
00735 /**
00736   * @brief   AF 7 selection
00737   */
00738 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00739 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00740
00741 /**
00742   * @brief   AF 8 selection
00743   */
00744 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00745
00746 /**
00747   * @brief   AF 9 selection
00748   */
00749 #define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */
00750 #define GPIO_AF9_FMPI2C1       ((uint8_t)0x09U)  /* FMPI2C1 Alternate Function mapping */
00751
00752 /**
00753   * @brief   AF 15 selection
00754   */
00755 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00756 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00757
00758 /*---------------------------------------- STM32F446xx -----------------------*/
00759 #if defined(STM32F446xx)
00760 /**
00761   * @brief   AF 0 selection
00762   */
00763 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00764 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00765 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00766 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00767 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00768
00769 /**
00770   * @brief   AF 1 selection
00771   */
00772 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00773 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00774
00775 /**
00776   * @brief   AF 2 selection
00777   */
00778 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00779 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00780 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00781
00782 /**
00783   * @brief   AF 3 selection
00784   */
00785 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00786 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00787 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00788 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00789 #define GPIO_AF3_CEC           ((uint8_t)0x03U)  /* CEC Alternate Function mapping   */
00790
00791 /**
00792   * @brief   AF 4 selection
00793   */
00794 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00795 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00796 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00797 #define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */
00798 #define GPIO_AF4_CEC           ((uint8_t)0x04U)  /* CEC Alternate Function mapping  */
00799
00800 /**
00801   * @brief   AF 5 selection
00802   */
00803 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */
00804 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00805 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
00806 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
00807
00808 /**
00809   * @brief   AF 6 selection
00810   */
00811 #define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping  */
00812 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00813 #define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4 Alternate Function mapping       */
00814 #define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
00815
00816 /**
00817   * @brief   AF 7 selection
00818   */
00819 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00820 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00821 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
00822 #define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */
00823 #define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2/I2S2 Alternate Function mapping  */
00824 #define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */
00825 #define GPIO_AF7_SPDIFRX       ((uint8_t)0x07U)  /* SPDIFRX Alternate Function mapping      */
00826
00827 /**
00828   * @brief   AF 8 selection
00829   */
00830 #define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
00831 #define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
00832 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00833 #define GPIO_AF8_SPDIFRX       ((uint8_t)0x08U)  /* SPDIFRX Alternate Function mapping  */
00834 #define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */
00835
00836 /**
00837   * @brief   AF 9 selection
00838   */
00839 #define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */
00840 #define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */
00841 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */
00842 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */
00843 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */
00844 #define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping  */
00845
00846 /**
00847   * @brief   AF 10 selection
00848   */
00849 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00850 #define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
00851 #define GPIO_AF10_SAI2          ((uint8_t)0x0AU)  /* SAI2 Alternate Function mapping   */
00852 #define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping  */
00853
00854 /**
00855   * @brief   AF 11 selection
00856   */
00857 #define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
00858
00859 /**
00860   * @brief   AF 12 selection
00861   */
00862 #define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
00863 #define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
00864 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
00865
00866 /**
00867   * @brief   AF 13 selection
00868   */
00869 #define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
00870
00871 /**
00872   * @brief   AF 15 selection
00873   */
00874 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00875
00876 #endif /* STM32F446xx */
00877 /*----------------------------------------------------------------------------*/
00878
00879 /*-------------------------------- STM32F469xx/STM32F479xx--------------------*/
00880 #if defined(STM32F469xx) || defined(STM32F479xx)
00881 /**
00882   * @brief   AF 0 selection
00883   */
00884 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */
00885 #define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00886 #define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
00887 #define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00888 #define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */
00889
00890 /**
00891   * @brief   AF 1 selection
00892   */
00893 #define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */
00894 #define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */
00895
00896 /**
00897   * @brief   AF 2 selection
00898   */
00899 #define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */
00900 #define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */
00901 #define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */
00902
00903 /**
00904   * @brief   AF 3 selection
00905   */
00906 #define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */
00907 #define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */
00908 #define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */
00909 #define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */
00910
00911 /**
00912   * @brief   AF 4 selection
00913   */
00914 #define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */
00915 #define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */
00916 #define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */
00917
00918 /**
00919   * @brief   AF 5 selection
00920   */
00921 #define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */
00922 #define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */
00923 #define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */
00924 #define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */
00925 #define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */
00926 #define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */
00927 #define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */
00928
00929 /**
00930   * @brief   AF 6 selection
00931   */
00932 #define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */
00933 #define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */
00934 #define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */
00935
00936 /**
00937   * @brief   AF 7 selection
00938   */
00939 #define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */
00940 #define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */
00941 #define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */
00942 #define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */
00943
00944 /**
00945   * @brief   AF 8 selection
00946   */
00947 #define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */
00948 #define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */
00949 #define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */
00950 #define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */
00951 #define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */
00952
00953 /**
00954   * @brief   AF 9 selection
00955   */
00956 #define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */
00957 #define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */
00958 #define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */
00959 #define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */
00960 #define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */
00961 #define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */
00962 #define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping    */
00963
00964 /**
00965   * @brief   AF 10 selection
00966   */
00967 #define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */
00968 #define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */
00969 #define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping   */
00970
00971 /**
00972   * @brief   AF 11 selection
00973   */
00974 #define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */
00975
00976 /**
00977   * @brief   AF 12 selection
00978   */
00979 #define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */
00980 #define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */
00981 #define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */
00982
00983 /**
00984   * @brief   AF 13 selection
00985   */
00986 #define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */
00987 #define GPIO_AF13_DSI           ((uint8_t)0x0DU)  /* DSI Alternate Function mapping  */
00988
00989 /**
00990   * @brief   AF 14 selection
00991   */
00992 #define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */
00993
00994 /**
00995   * @brief   AF 15 selection
00996   */
00997 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */
00998
00999 #endif /* STM32F469xx || STM32F479xx */
01000 /*----------------------------------------------------------------------------*/
01001 /**
01002   * @}
01003   */
01004
01005 /**
01006   * @}
01007   */
01008
01009 /* Exported macro ------------------------------------------------------------*/
01010 /** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
01011   * @{
01012   */
01013 /**
01014   * @}
01015   */
01016
01017 /* Exported functions --------------------------------------------------------*/
01018 /** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
01019   * @{
01020   */
01021 /**
01022   * @}
01023   */
01024
01025 /* Private types -------------------------------------------------------------*/
01026 /* Private variables ---------------------------------------------------------*/
01027 /* Private constants ---------------------------------------------------------*/
01028 /** @defgroup GPIOEx_Private_Constants GPIO Private Constants
01029   * @{
01030   */
01031 /**
01032   * @}
01033   */
01034
01035 /* Private macros ------------------------------------------------------------*/
01036 /** @defgroup GPIOEx_Private_Macros GPIO Private Macros
01037   * @{
01038   */
01039 /** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
01040   * @{
01041   */
01042 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
01043 #define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
01044                                                ((__GPIOx__) == (GPIOB))? 1U :\
01045                                                ((__GPIOx__) == (GPIOC))? 2U :\
01046                                                ((__GPIOx__) == (GPIOD))? 3U :\
01047                                                ((__GPIOx__) == (GPIOE))? 4U :\
01048                                                ((__GPIOx__) == (GPIOF))? 5U :\
01049                                                ((__GPIOx__) == (GPIOG))? 6U :\
01050                                                ((__GPIOx__) == (GPIOH))? 7U :\
01051                                                ((__GPIOx__) == (GPIOI))? 8U : 9U)
01052 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
01053
01054 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
01055     defined(STM32F469xx) || defined(STM32F479xx)
01056 #define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
01057                                                ((__GPIOx__) == (GPIOB))? 1U :\
01058                                                ((__GPIOx__) == (GPIOC))? 2U :\
01059                                                ((__GPIOx__) == (GPIOD))? 3U :\
01060                                                ((__GPIOx__) == (GPIOE))? 4U :\
01061                                                ((__GPIOx__) == (GPIOF))? 5U :\
01062                                                ((__GPIOx__) == (GPIOG))? 6U :\
01063                                                ((__GPIOx__) == (GPIOH))? 7U :\
01064                                                ((__GPIOx__) == (GPIOI))? 8U :\
01065                                                ((__GPIOx__) == (GPIOJ))? 9U : 10U)
01066 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
01067
01068 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
01069 #define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
01070                                                ((__GPIOx__) == (GPIOB))? 1U :\
01071                                                ((__GPIOx__) == (GPIOC))? 2U :\
01072                                                ((__GPIOx__) == (GPIOH))? 7U : 8U)
01073 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
01074
01075 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
01076 #define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
01077                                                ((__GPIOx__) == (GPIOB))? 1U :\
01078                                                ((__GPIOx__) == (GPIOC))? 2U :\
01079                                                ((__GPIOx__) == (GPIOD))? 3U :\
01080                                                ((__GPIOx__) == (GPIOE))? 4U : 5U)
01081 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
01082
01083 #if defined(STM32F446xx)
01084 #define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
01085                                                ((__GPIOx__) == (GPIOB))? 1U :\
01086                                                ((__GPIOx__) == (GPIOC))? 2U :\
01087                                                ((__GPIOx__) == (GPIOD))? 3U :\
01088                                                ((__GPIOx__) == (GPIOE))? 4U :\
01089                                                ((__GPIOx__) == (GPIOF))? 5U :\
01090                                                ((__GPIOx__) == (GPIOG))? 6U : 8U)
01091 #endif /* STM32F446xx */
01092
01093 /**
01094   * @}
01095   */
01096
01097 /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
01098   * @{
01099   */
01100 /*------------------------- STM32F429xx/STM32F439xx---------------------------*/
01101 #if defined(STM32F429xx) || defined(STM32F439xx)
01102 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01103                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01104                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01105                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01106                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01107                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
01108                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
01109                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
01110                           ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
01111                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
01112                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01113                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
01114                           ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
01115                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
01116                           ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
01117                           ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
01118                           ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
01119                           ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
01120                           ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
01121                           ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
01122                           ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
01123                           ((AF) == GPIO_AF14_LTDC))
01124
01125 #endif /* STM32F429xx || STM32F439xx */
01126 /*----------------------------------------------------------------------------*/
01127
01128 /*---------------------------------- STM32F427xx/STM32F437xx------------------*/
01129 #if defined(STM32F427xx) || defined(STM32F437xx)
01130 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01131                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01132                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01133                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01134                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01135                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
01136                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
01137                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
01138                           ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
01139                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
01140                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01141                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
01142                           ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
01143                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
01144                           ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
01145                           ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
01146                           ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
01147                           ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
01148                           ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
01149                           ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
01150                           ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))
01151
01152 #endif /* STM32F427xx || STM32F437xx */
01153 /*----------------------------------------------------------------------------*/
01154
01155 /*---------------------------------- STM32F407xx/STM32F417xx------------------*/
01156 #if defined(STM32F407xx) || defined(STM32F417xx)
01157 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01158                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01159                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01160                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01161                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01162                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
01163                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
01164                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
01165                           ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
01166                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
01167                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01168                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
01169                           ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
01170                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
01171                           ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
01172                           ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
01173                           ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
01174                           ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
01175
01176 #endif /* STM32F407xx || STM32F417xx */
01177 /*----------------------------------------------------------------------------*/
01178
01179 /*---------------------------------- STM32F405xx/STM32F415xx------------------*/
01180 #if defined(STM32F405xx) || defined(STM32F415xx)
01181 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01182                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01183                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01184                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01185                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01186                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
01187                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
01188                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
01189                           ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
01190                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
01191                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01192                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
01193                           ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
01194                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
01195                           ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
01196                           ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
01197                           ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
01198
01199 #endif /* STM32F405xx || STM32F415xx */
01200
01201 /*----------------------------------------------------------------------------*/
01202
01203 /*---------------------------------------- STM32F401xx------------------------*/
01204 #if defined(STM32F401xC) || defined(STM32F401xE)
01205 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01206                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01207                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01208                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01209                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01210                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
01211                           ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
01212                           ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
01213                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
01214                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01215                           ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
01216                           ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
01217                           ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
01218
01219 #endif /* STM32F401xC || STM32F401xE */
01220 /*----------------------------------------------------------------------------*/
01221 /*---------------------------------------- STM32F410xx------------------------*/
01222 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
01223 #define IS_GPIO_AF(AF)   (((AF) < 10U) || ((AF) == 15U))
01224 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
01225
01226 /*---------------------------------------- STM32F411xx------------------------*/
01227 #if defined(STM32F411xE)
01228 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01229                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01230                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01231                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01232                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01233                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
01234                           ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
01235                           ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
01236                           ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF6_SPI4)       || \
01237                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
01238                           ((AF) == GPIO_AF6_SPI5)       || ((AF) == GPIO_AF7_SPI3)       || \
01239                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01240                           ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
01241                           ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
01242                           ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
01243
01244 #endif /* STM32F411xE */
01245 /*----------------------------------------------------------------------------*/
01246
01247 /*----------------------------------------------- STM32F446xx ----------------*/
01248 #if defined(STM32F446xx)
01249 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01250                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01251                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01252                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01253                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01254                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
01255                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
01256                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
01257                           ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
01258                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
01259                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01260                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
01261                           ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
01262                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
01263                           ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
01264                           ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
01265                           ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
01266                           ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
01267                           ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
01268                           ((AF) == GPIO_AF3_CEC)        ||  ((AF) == GPIO_AF4_CEC)       || \
01269                           ((AF) == GPIO_AF5_SPI3)       ||  ((AF) == GPIO_AF6_SPI2)      || \
01270                           ((AF) == GPIO_AF6_SPI4)       ||  ((AF) == GPIO_AF7_UART5)     || \
01271                           ((AF) == GPIO_AF7_SPI2)       ||  ((AF) == GPIO_AF7_SPI3)      || \
01272                           ((AF) == GPIO_AF7_SPDIFRX)    ||  ((AF) == GPIO_AF8_SPDIFRX)   || \
01273                           ((AF) == GPIO_AF8_SAI2)       ||  ((AF) == GPIO_AF9_QSPI)      || \
01274                           ((AF) == GPIO_AF10_SAI2)      ||  ((AF) == GPIO_AF10_QSPI))
01275
01276 #endif /* STM32F446xx */
01277 /*----------------------------------------------------------------------------*/
01278
01279 /*------------------------------------------- STM32F469xx/STM32F479xx --------*/
01280 #if defined(STM32F469xx) || defined(STM32F479xx)
01281 #define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
01282                           ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
01283                           ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
01284                           ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
01285                           ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
01286                           ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
01287                           ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
01288                           ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
01289                           ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
01290                           ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
01291                           ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
01292                           ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
01293                           ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
01294                           ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
01295                           ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
01296                           ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
01297                           ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
01298                           ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
01299                           ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
01300                           ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
01301                           ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF6_SAI1)       || \
01302                           ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI)      || \
01303                           ((AF) == GPIO_AF9_QSPI)       || ((AF) == GPIO_AF10_QSPI))
01304
01305 #endif /* STM32F469xx || STM32F479xx */
01306 /*----------------------------------------------------------------------------*/
01307
01308 /**
01309   * @}
01310   */
01311
01312 /**
01313   * @}
01314   */
01315
01316 /* Private functions ---------------------------------------------------------*/
01317 /** @defgroup GPIOEx_Private_Functions GPIO Private Functions
01318   * @{
01319   */
01320
01321 /**
01322   * @}
01323   */
01324
01325 /**
01326   * @}
01327   */
01328
01329 /**
01330   * @}
01331   */
01332
01333 #ifdef __cplusplus
01334 }
01335 #endif
01336
01337 #endif /* __STM32F4xx_HAL_GPIO_EX_H */
01338
01339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash.c Source File

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stm32f4xx_hal_hash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_hash.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   HASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the HASH peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + HASH/HMAC Processing functions by algorithm using polling mode
00012   *           + HASH/HMAC functions by algorithm using interrupt mode
00013   *           + HASH/HMAC functions by algorithm using DMA mode
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                      ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021     The HASH HAL driver can be used as follows:
00022     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
00023         (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
00024         (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
00025             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
00026             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
00027             (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
00028         (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
00029             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00030             (+++) Configure and enable one DMA stream one for managing data transfer from
00031                 memory to peripheral (input stream). Managing data transfer from
00032                 peripheral to memory can be performed only using CPU
00033             (+++) Associate the initialized DMA handle to the HASH DMA handle
00034                 using  __HAL_LINKDMA()
00035             (+++) Configure the priority and enable the NVIC for the transfer complete
00036                 interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00037     (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
00038         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
00039         (##) For HMAC, the encryption key.
00040         (##) For HMAC, the key size used for encryption.
00041     (#)Three processing functions are available:
00042         (##) Polling mode: processing APIs are blocking functions
00043              i.e. they process the data and wait till the digest computation is finished
00044              e.g. HAL_HASH_SHA1_Start()
00045         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00046                 i.e. they process the data under interrupt
00047                 e.g. HAL_HASH_SHA1_Start_IT()
00048         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00049              not used for data transfer i.e. the data transfer is ensured by DMA
00050                 e.g. HAL_HASH_SHA1_Start_DMA()
00051     (#)When the processing function is called at first time after HAL_HASH_Init()
00052        the HASH peripheral is initialized and processes the buffer in input.
00053        After that, the digest computation is started.
00054        When processing multi-buffer use the accumulate function to write the
00055        data in the peripheral without starting the digest computation. In last
00056        buffer use the start function to input the last buffer ans start the digest
00057        computation.
00058        (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
00059        (##) write (n-1)th data buffer in the peripheral without starting the digest computation
00060        (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
00061     (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
00062     (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
00063        After that, call the finish function in order to get the digest value
00064        e.g. HAL_HASH_SHA1_Finish()
00065     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
00066
00067   @endverbatim
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00072   *
00073   * Redistribution and use in source and binary forms, with or without modification,
00074   * are permitted provided that the following conditions are met:
00075   *   1. Redistributions of source code must retain the above copyright notice,
00076   *      this list of conditions and the following disclaimer.
00077   *   2. Redistributions in binary form must reproduce the above copyright notice,
00078   *      this list of conditions and the following disclaimer in the documentation
00079   *      and/or other materials provided with the distribution.
00080   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00081   *      may be used to endorse or promote products derived from this software
00082   *      without specific prior written permission.
00083   *
00084   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00085   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00086   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00087   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00088   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00089   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00090   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00091   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00092   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00093   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00094   *
00095   ******************************************************************************
00096   */
00097
00098 /* Includes ------------------------------------------------------------------*/
00099 #include "stm32f4xx_hal.h"
00100
00101 /** @addtogroup STM32F4xx_HAL_Driver
00102   * @{
00103   */
00104
00105 /** @defgroup HASH HASH
00106   * @brief HASH HAL module driver.
00107   * @{
00108   */
00109
00110 #ifdef HAL_HASH_MODULE_ENABLED
00111
00112 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /** @defgroup HASH_Private_Functions HASH Private Functions
00120   * @{
00121   */
00122 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
00123 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
00124 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
00125 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
00126 /**
00127   * @}
00128   */
00129
00130 /* Private functions ---------------------------------------------------------*/
00131 /** @addtogroup HASH_Private_Functions
00132   * @{
00133   */
00134
00135 /**
00136   * @brief  DMA HASH Input Data complete callback.
00137   * @param  hdma: DMA handle
00138   * @retval None
00139   */
00140 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
00141 {
00142   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00143   uint32_t inputaddr = 0U;
00144   uint32_t buffersize = 0U;
00145
00146   if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
00147   {
00148     /* Disable the DMA transfer */
00149     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00150
00151     /* Change HASH peripheral state */
00152     hhash->State = HAL_HASH_STATE_READY;
00153
00154     /* Call Input data transfer complete callback */
00155     HAL_HASH_InCpltCallback(hhash);
00156   }
00157   else
00158   {
00159     /* Increment Interrupt counter */
00160     hhash->HashInCount++;
00161     /* Disable the DMA transfer before starting the next transfer */
00162     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00163
00164     if(hhash->HashInCount <= 2U)
00165     {
00166       /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
00167       if(hhash->HashInCount == 1U)
00168       {
00169         inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00170         buffersize = hhash->HashBuffSize;
00171       }
00172       /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
00173       else if(hhash->HashInCount == 2U)
00174       {
00175         inputaddr = (uint32_t)hhash->Init.pKey;
00176         buffersize = hhash->Init.KeySize;
00177       }
00178       /* Configure the number of valid bits in last word of the message */
00179       MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
00180
00181       /* Set the HASH DMA transfer complete */
00182       hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
00183
00184       /* Enable the DMA In DMA Stream */
00185       HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
00186
00187       /* Enable DMA requests */
00188       HASH->CR |= (HASH_CR_DMAE);
00189     }
00190     else
00191     {
00192       /* Disable the DMA transfer */
00193       HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00194
00195       /* Reset the InCount */
00196       hhash->HashInCount = 0U;
00197
00198       /* Change HASH peripheral state */
00199       hhash->State = HAL_HASH_STATE_READY;
00200
00201       /* Call Input data transfer complete callback */
00202       HAL_HASH_InCpltCallback(hhash);
00203     }
00204   }
00205 }
00206
00207 /**
00208   * @brief  DMA HASH communication error callback.
00209   * @param  hdma: DMA handle
00210   * @retval None
00211   */
00212 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
00213 {
00214   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00215   hhash->State= HAL_HASH_STATE_READY;
00216   HAL_HASH_ErrorCallback(hhash);
00217 }
00218
00219 /**
00220   * @brief  Writes the input buffer in data register.
00221   * @param  pInBuffer: Pointer to input buffer
00222   * @param  Size: The size of input buffer
00223   * @retval None
00224   */
00225 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
00226 {
00227   uint32_t buffercounter;
00228   uint32_t inputaddr = (uint32_t) pInBuffer;
00229
00230   for(buffercounter = 0U; buffercounter < Size; buffercounter+=4)
00231   {
00232     HASH->DIN = *(uint32_t*)inputaddr;
00233     inputaddr+=4U;
00234   }
00235 }
00236
00237 /**
00238   * @brief  Provides the message digest result.
00239   * @param  pMsgDigest: Pointer to the message digest
00240   * @param  Size: The size of the message digest in bytes
00241   * @retval None
00242   */
00243 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
00244 {
00245   uint32_t msgdigest = (uint32_t)pMsgDigest;
00246
00247   switch(Size)
00248   {
00249   case 16U:
00250     /* Read the message digest */
00251     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00252     msgdigest+=4U;
00253     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00254     msgdigest+=4U;
00255     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00256     msgdigest+=4U;
00257     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00258     break;
00259   case 20U:
00260     /* Read the message digest */
00261     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00262     msgdigest+=4U;
00263     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00264     msgdigest+=4U;
00265     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00266     msgdigest+=4U;
00267     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00268     msgdigest+=4U;
00269     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
00270     break;
00271   case 28U:
00272     /* Read the message digest */
00273     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00274     msgdigest+=4U;
00275     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00276     msgdigest+=4U;
00277     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00278     msgdigest+=4U;
00279     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00280     msgdigest+=4U;
00281     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
00282     msgdigest+=4U;
00283     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
00284     msgdigest+=4U;
00285     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
00286     break;
00287   case 32U:
00288     /* Read the message digest */
00289     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00290     msgdigest+=4U;
00291     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00292     msgdigest+=4U;
00293     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00294     msgdigest+=4U;
00295     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00296     msgdigest+=4U;
00297     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
00298     msgdigest+=4U;
00299     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
00300     msgdigest+=4U;
00301     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
00302     msgdigest+=4U;
00303     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7U]);
00304     break;
00305   default:
00306     break;
00307   }
00308 }
00309
00310 /**
00311   * @}
00312   */
00313
00314 /* Exported functions --------------------------------------------------------*/
00315 /** @addtogroup HASH_Exported_Functions
00316   * @{
00317   */
00318
00319
00320 /** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
00321  *  @brief    Initialization and Configuration functions.
00322  *
00323 @verbatim
00324  ===============================================================================
00325               ##### Initialization and de-initialization functions #####
00326  ===============================================================================
00327     [..]  This section provides functions allowing to:
00328       (+) Initialize the HASH according to the specified parameters
00329           in the HASH_InitTypeDef and creates the associated handle.
00330       (+) DeInitialize the HASH peripheral.
00331       (+) Initialize the HASH MSP.
00332       (+) DeInitialize HASH MSP.
00333
00334 @endverbatim
00335   * @{
00336   */
00337
00338 /**
00339   * @brief  Initializes the HASH according to the specified parameters in the
00340             HASH_HandleTypeDef and creates the associated handle.
00341   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00342   *         the configuration information for HASH module
00343   * @retval HAL status
00344   */
00345 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
00346 {
00347   /* Check the hash handle allocation */
00348   if(hhash == NULL)
00349   {
00350     return HAL_ERROR;
00351   }
00352
00353   /* Check the parameters */
00354   assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
00355
00356   if(hhash->State == HAL_HASH_STATE_RESET)
00357   {
00358     /* Allocate lock resource and initialize it */
00359     hhash->Lock = HAL_UNLOCKED;
00360     /* Init the low level hardware */
00361     HAL_HASH_MspInit(hhash);
00362   }
00363
00364   /* Change the HASH state */
00365   hhash->State = HAL_HASH_STATE_BUSY;
00366
00367   /* Reset HashInCount, HashBuffSize and HashITCounter */
00368   hhash->HashInCount = 0U;
00369   hhash->HashBuffSize = 0U;
00370   hhash->HashITCounter = 0U;
00371
00372   /* Set the data type */
00373   HASH->CR |= (uint32_t) (hhash->Init.DataType);
00374
00375   /* Change the HASH state */
00376   hhash->State = HAL_HASH_STATE_READY;
00377
00378   /* Set the default HASH phase */
00379   hhash->Phase = HAL_HASH_PHASE_READY;
00380
00381   /* Return function status */
00382   return HAL_OK;
00383 }
00384
00385 /**
00386   * @brief  DeInitializes the HASH peripheral.
00387   * @note   This API must be called before starting a new processing.
00388   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00389   *         the configuration information for HASH module
00390   * @retval HAL status
00391   */
00392 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
00393 {
00394   /* Check the HASH handle allocation */
00395   if(hhash == NULL)
00396   {
00397     return HAL_ERROR;
00398   }
00399
00400   /* Change the HASH state */
00401   hhash->State = HAL_HASH_STATE_BUSY;
00402
00403   /* Set the default HASH phase */
00404   hhash->Phase = HAL_HASH_PHASE_READY;
00405
00406   /* Reset HashInCount, HashBuffSize and HashITCounter */
00407   hhash->HashInCount = 0U;
00408   hhash->HashBuffSize = 0U;
00409   hhash->HashITCounter = 0U;
00410
00411   /* DeInit the low level hardware */
00412   HAL_HASH_MspDeInit(hhash);
00413
00414   /* Change the HASH state */
00415   hhash->State = HAL_HASH_STATE_RESET;
00416
00417   /* Release Lock */
00418   __HAL_UNLOCK(hhash);
00419
00420   /* Return function status */
00421   return HAL_OK;
00422 }
00423
00424 /**
00425   * @brief  Initializes the HASH MSP.
00426   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00427   *         the configuration information for HASH module
00428   * @retval None
00429   */
00430 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
00431 {
00432   /* Prevent unused argument(s) compilation warning */
00433   UNUSED(hhash);
00434   /* NOTE: This function Should not be modified, when the callback is needed,
00435            the HAL_HASH_MspInit could be implemented in the user file
00436    */
00437 }
00438
00439 /**
00440   * @brief  DeInitializes HASH MSP.
00441   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00442   *         the configuration information for HASH module
00443   * @retval None
00444   */
00445 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
00446 {
00447   /* Prevent unused argument(s) compilation warning */
00448   UNUSED(hhash);
00449   /* NOTE: This function Should not be modified, when the callback is needed,
00450            the HAL_HASH_MspDeInit could be implemented in the user file
00451    */
00452 }
00453
00454 /**
00455   * @brief  Input data transfer complete callback.
00456   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00457   *         the configuration information for HASH module
00458   * @retval None
00459   */
00460  __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
00461 {
00462   /* Prevent unused argument(s) compilation warning */
00463   UNUSED(hhash);
00464   /* NOTE: This function Should not be modified, when the callback is needed,
00465            the HAL_HASH_InCpltCallback could be implemented in the user file
00466    */
00467 }
00468
00469 /**
00470   * @brief  Data transfer Error callback.
00471   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00472   *         the configuration information for HASH module
00473   * @retval None
00474   */
00475  __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
00476 {
00477   /* Prevent unused argument(s) compilation warning */
00478   UNUSED(hhash);
00479   /* NOTE: This function Should not be modified, when the callback is needed,
00480            the HAL_HASH_ErrorCallback could be implemented in the user file
00481    */
00482 }
00483
00484 /**
00485   * @brief  Digest computation complete callback. It is used only with interrupt.
00486   * @note   This callback is not relevant with DMA.
00487   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00488   *         the configuration information for HASH module
00489   * @retval None
00490   */
00491  __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
00492 {
00493   /* Prevent unused argument(s) compilation warning */
00494   UNUSED(hhash);
00495   /* NOTE: This function Should not be modified, when the callback is needed,
00496            the HAL_HASH_DgstCpltCallback could be implemented in the user file
00497    */
00498 }
00499
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
00505  *  @brief   processing functions using polling mode
00506  *
00507 @verbatim
00508  ===============================================================================
00509               ##### HASH processing using polling mode functions#####
00510  ===============================================================================
00511     [..]  This section provides functions allowing to calculate in polling mode
00512           the hash value using one of the following algorithms:
00513       (+) MD5
00514       (+) SHA1
00515
00516 @endverbatim
00517   * @{
00518   */
00519
00520 /**
00521   * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
00522             The digest is available in pOutBuffer.
00523   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00524   *         the configuration information for HASH module
00525   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00526   * @param  Size: Length of the input buffer in bytes.
00527   *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
00528   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
00529   *          and appending the input buffer is no more possible.
00530   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
00531   * @param  Timeout: Timeout value
00532   * @retval HAL status
00533   */
00534 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00535 {
00536   uint32_t tickstart = 0U;
00537
00538   /* Process Locked */
00539   __HAL_LOCK(hhash);
00540
00541   /* Change the HASH state */
00542   hhash->State = HAL_HASH_STATE_BUSY;
00543
00544   /* Check if initialization phase has already been performed */
00545   if(hhash->Phase == HAL_HASH_PHASE_READY)
00546   {
00547     /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
00548        the message digest of a new message */
00549     HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
00550   }
00551
00552   /* Set the phase */
00553   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00554
00555   /* Configure the number of valid bits in last word of the message */
00556   __HAL_HASH_SET_NBVALIDBITS(Size);
00557
00558   /* Write input buffer in data register */
00559   HASH_WriteData(pInBuffer, Size);
00560
00561   /* Start the digest calculation */
00562   __HAL_HASH_START_DIGEST();
00563
00564   /* Get tick */
00565   tickstart = HAL_GetTick();
00566
00567   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
00568   {
00569     /* Check for the Timeout */
00570     if(Timeout != HAL_MAX_DELAY)
00571     {
00572       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00573       {
00574         /* Change state */
00575         hhash->State = HAL_HASH_STATE_TIMEOUT;
00576
00577         /* Process Unlocked */
00578         __HAL_UNLOCK(hhash);
00579
00580         return HAL_TIMEOUT;
00581       }
00582     }
00583   }
00584
00585   /* Read the message digest */
00586   HASH_GetDigest(pOutBuffer, 16U);
00587
00588   /* Change the HASH state */
00589   hhash->State = HAL_HASH_STATE_READY;
00590
00591   /* Process Unlocked */
00592   __HAL_UNLOCK(hhash);
00593
00594   /* Return function status */
00595   return HAL_OK;
00596 }
00597
00598 /**
00599   * @brief  Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
00600   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00601   *         the configuration information for HASH module
00602   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00603   * @param  Size: Length of the input buffer in bytes.
00604   *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
00605   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
00606   *          and appending the input buffer is no more possible.
00607   * @retval HAL status
00608   */
00609 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00610 {
00611   /* Process Locked */
00612   __HAL_LOCK(hhash);
00613
00614   /* Change the HASH state */
00615   hhash->State = HAL_HASH_STATE_BUSY;
00616
00617   /* Check if initialization phase has already been performed */
00618   if(hhash->Phase == HAL_HASH_PHASE_READY)
00619   {
00620     /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
00621        the message digest of a new message */
00622     HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
00623   }
00624
00625   /* Set the phase */
00626   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00627
00628   /* Configure the number of valid bits in last word of the message */
00629   __HAL_HASH_SET_NBVALIDBITS(Size);
00630
00631   /* Write input buffer in data register */
00632   HASH_WriteData(pInBuffer, Size);
00633
00634   /* Change the HASH state */
00635   hhash->State = HAL_HASH_STATE_READY;
00636
00637   /* Process Unlocked */
00638   __HAL_UNLOCK(hhash);
00639
00640   /* Return function status */
00641   return HAL_OK;
00642 }
00643
00644 /**
00645   * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
00646             The digest is available in pOutBuffer.
00647   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00648   *         the configuration information for HASH module
00649   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00650   * @param  Size: Length of the input buffer in bytes.
00651   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00652   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00653   * @param  Timeout: Timeout value
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00657 {
00658   uint32_t tickstart = 0U;
00659
00660   /* Process Locked */
00661   __HAL_LOCK(hhash);
00662
00663   /* Change the HASH state */
00664   hhash->State = HAL_HASH_STATE_BUSY;
00665
00666   /* Check if initialization phase has already been performed */
00667   if(hhash->Phase == HAL_HASH_PHASE_READY)
00668   {
00669     /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
00670        the message digest of a new message */
00671     HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
00672   }
00673
00674   /* Set the phase */
00675   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00676
00677   /* Configure the number of valid bits in last word of the message */
00678   __HAL_HASH_SET_NBVALIDBITS(Size);
00679
00680   /* Write input buffer in data register */
00681   HASH_WriteData(pInBuffer, Size);
00682
00683   /* Start the digest calculation */
00684   __HAL_HASH_START_DIGEST();
00685
00686   /* Get tick */
00687   tickstart = HAL_GetTick();
00688
00689   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
00690     {
00691       /* Check for the Timeout */
00692       if(Timeout != HAL_MAX_DELAY)
00693       {
00694         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00695         {
00696           /* Change state */
00697           hhash->State = HAL_HASH_STATE_TIMEOUT;
00698
00699           /* Process Unlocked */
00700           __HAL_UNLOCK(hhash);
00701
00702           return HAL_TIMEOUT;
00703         }
00704       }
00705     }
00706
00707   /* Read the message digest */
00708   HASH_GetDigest(pOutBuffer, 20U);
00709
00710   /* Change the HASH state */
00711   hhash->State = HAL_HASH_STATE_READY;
00712
00713   /* Process Unlocked */
00714   __HAL_UNLOCK(hhash);
00715
00716   /* Return function status */
00717   return HAL_OK;
00718 }
00719
00720 /**
00721   * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
00722   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00723   *         the configuration information for HASH module
00724   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00725   * @param  Size: Length of the input buffer in bytes.
00726   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00727   * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
00728   * @retval HAL status
00729   */
00730 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00731 {
00732   /* Check the parameters */
00733   assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
00734
00735   /* Process Locked */
00736   __HAL_LOCK(hhash);
00737
00738   /* Change the HASH state */
00739   hhash->State = HAL_HASH_STATE_BUSY;
00740
00741   /* Check if initialization phase has already been performed */
00742   if(hhash->Phase == HAL_HASH_PHASE_READY)
00743   {
00744     /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
00745        the message digest of a new message */
00746     HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
00747   }
00748
00749   /* Set the phase */
00750   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00751
00752   /* Configure the number of valid bits in last word of the message */
00753   __HAL_HASH_SET_NBVALIDBITS(Size);
00754
00755   /* Write input buffer in data register */
00756   HASH_WriteData(pInBuffer, Size);
00757
00758   /* Change the HASH state */
00759   hhash->State = HAL_HASH_STATE_READY;
00760
00761   /* Process Unlocked */
00762   __HAL_UNLOCK(hhash);
00763
00764   /* Return function status */
00765   return HAL_OK;
00766 }
00767
00768 /**
00769   * @}
00770   */
00771
00772 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
00773  *  @brief   processing functions using interrupt mode.
00774  *
00775 @verbatim
00776  ===============================================================================
00777               ##### HASH processing using interrupt mode functions #####
00778  ===============================================================================
00779     [..]  This section provides functions allowing to calculate in interrupt mode
00780           the hash value using one of the following algorithms:
00781       (+) MD5
00782       (+) SHA1
00783
00784 @endverbatim
00785   * @{
00786   */
00787
00788 /**
00789   * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
00790   *         The digest is available in pOutBuffer.
00791   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00792   *         the configuration information for HASH module
00793   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00794   * @param  Size: Length of the input buffer in bytes.
00795   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00796   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
00797   * @retval HAL status
00798   */
00799 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00800 {
00801   uint32_t inputaddr;
00802   uint32_t outputaddr;
00803   uint32_t buffercounter;
00804   uint32_t inputcounter;
00805
00806   /* Process Locked */
00807   __HAL_LOCK(hhash);
00808
00809   if(hhash->State == HAL_HASH_STATE_READY)
00810   {
00811     /* Change the HASH state */
00812     hhash->State = HAL_HASH_STATE_BUSY;
00813
00814     hhash->HashInCount = Size;
00815     hhash->pHashInBuffPtr = pInBuffer;
00816     hhash->pHashOutBuffPtr = pOutBuffer;
00817
00818     /* Check if initialization phase has already been performed */
00819     if(hhash->Phase == HAL_HASH_PHASE_READY)
00820     {
00821       /* Select the SHA1 mode */
00822       HASH->CR |= HASH_ALGOSELECTION_MD5;
00823       /* Reset the HASH processor core, so that the HASH will be ready to compute
00824          the message digest of a new message */
00825       HASH->CR |= HASH_CR_INIT;
00826     }
00827     /* Reset interrupt counter */
00828     hhash->HashITCounter = 0U;
00829
00830     /* Set the phase */
00831     hhash->Phase = HAL_HASH_PHASE_PROCESS;
00832
00833     /* Process Unlocked */
00834     __HAL_UNLOCK(hhash);
00835
00836     /* Enable Interrupts */
00837     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
00838
00839     /* Return function status */
00840     return HAL_OK;
00841   }
00842   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
00843   {
00844     outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
00845     /* Read the Output block from the Output FIFO */
00846     *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
00847     outputaddr+=4U;
00848     *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
00849     outputaddr+=4U;
00850     *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
00851     outputaddr+=4U;
00852     *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
00853
00854     if(hhash->HashInCount == 0U)
00855     {
00856       /* Disable Interrupts */
00857       HASH->IMR = 0U;
00858       /* Change the HASH state */
00859       hhash->State = HAL_HASH_STATE_READY;
00860       /* Call digest computation complete callback */
00861       HAL_HASH_DgstCpltCallback(hhash);
00862
00863       /* Process Unlocked */
00864       __HAL_UNLOCK(hhash);
00865
00866       /* Return function status */
00867       return HAL_OK;
00868     }
00869   }
00870   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
00871   {
00872     if(hhash->HashInCount >= 68U)
00873     {
00874       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00875       /* Write the Input block in the Data IN register */
00876       for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
00877       {
00878         HASH->DIN = *(uint32_t*)inputaddr;
00879         inputaddr+=4U;
00880       }
00881       if(hhash->HashITCounter == 0U)
00882       {
00883         HASH->DIN = *(uint32_t*)inputaddr;
00884
00885         if(hhash->HashInCount >= 68U)
00886         {
00887           /* Decrement buffer counter */
00888           hhash->HashInCount -= 68U;
00889           hhash->pHashInBuffPtr+= 68U;
00890         }
00891         else
00892         {
00893           hhash->HashInCount = 0U;
00894           hhash->pHashInBuffPtr+= hhash->HashInCount;
00895         }
00896         /* Set Interrupt counter */
00897         hhash->HashITCounter = 1U;
00898       }
00899       else
00900       {
00901         /* Decrement buffer counter */
00902         hhash->HashInCount -= 64U;
00903         hhash->pHashInBuffPtr+= 64U;
00904       }
00905     }
00906     else
00907     {
00908       /* Get the buffer address */
00909       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00910       /* Get the buffer counter */
00911       inputcounter = hhash->HashInCount;
00912       /* Disable Interrupts */
00913       HASH->IMR &= ~(HASH_IT_DINI);
00914       /* Configure the number of valid bits in last word of the message */
00915       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
00916
00917       if((inputcounter > 4U) && (inputcounter%4U))
00918       {
00919         inputcounter = (inputcounter+4U-inputcounter%4U);
00920       }
00921       else if ((inputcounter < 4U) && (inputcounter != 0U))
00922       {
00923         inputcounter = 4U;
00924       }
00925       /* Write the Input block in the Data IN register */
00926       for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
00927       {
00928         HASH->DIN = *(uint32_t*)inputaddr;
00929         inputaddr+=4U;
00930       }
00931       /* Start the digest calculation */
00932       __HAL_HASH_START_DIGEST();
00933       /* Reset buffer counter */
00934       hhash->HashInCount = 0U;
00935       /* Call Input data transfer complete callback */
00936       HAL_HASH_InCpltCallback(hhash);
00937     }
00938   }
00939
00940   /* Process Unlocked */
00941   __HAL_UNLOCK(hhash);
00942
00943   /* Return function status */
00944   return HAL_OK;
00945 }
00946
00947 /**
00948   * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
00949   *         The digest is available in pOutBuffer.
00950   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00951   *         the configuration information for HASH module
00952   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00953   * @param  Size: Length of the input buffer in bytes.
00954   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00955   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00956   * @retval HAL status
00957   */
00958 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00959 {
00960   uint32_t inputaddr;
00961   uint32_t outputaddr;
00962   uint32_t buffercounter;
00963   uint32_t inputcounter;
00964
00965   /* Process Locked */
00966   __HAL_LOCK(hhash);
00967
00968   if(hhash->State == HAL_HASH_STATE_READY)
00969   {
00970     /* Change the HASH state */
00971     hhash->State = HAL_HASH_STATE_BUSY;
00972
00973     hhash->HashInCount = Size;
00974     hhash->pHashInBuffPtr = pInBuffer;
00975     hhash->pHashOutBuffPtr = pOutBuffer;
00976
00977     /* Check if initialization phase has already been performed */
00978     if(hhash->Phase == HAL_HASH_PHASE_READY)
00979     {
00980       /* Select the SHA1 mode */
00981       HASH->CR |= HASH_ALGOSELECTION_SHA1;
00982       /* Reset the HASH processor core, so that the HASH will be ready to compute
00983          the message digest of a new message */
00984       HASH->CR |= HASH_CR_INIT;
00985     }
00986     /* Reset interrupt counter */
00987     hhash->HashITCounter = 0U;
00988
00989     /* Set the phase */
00990     hhash->Phase = HAL_HASH_PHASE_PROCESS;
00991
00992     /* Process Unlocked */
00993     __HAL_UNLOCK(hhash);
00994
00995     /* Enable Interrupts */
00996     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
00997
00998     /* Return function status */
00999     return HAL_OK;
01000   }
01001   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
01002   {
01003     outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
01004     /* Read the Output block from the Output FIFO */
01005     *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
01006     outputaddr+=4U;
01007     *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
01008     outputaddr+=4U;
01009     *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
01010     outputaddr+=4U;
01011     *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
01012     outputaddr+=4U;
01013     *(uint32_t*)(outputaddr) = __REV(HASH->HR[4U]);
01014     if(hhash->HashInCount == 0U)
01015     {
01016       /* Disable Interrupts */
01017       HASH->IMR = 0U;
01018       /* Change the HASH state */
01019       hhash->State = HAL_HASH_STATE_READY;
01020       /* Call digest computation complete callback */
01021       HAL_HASH_DgstCpltCallback(hhash);
01022
01023       /* Process Unlocked */
01024       __HAL_UNLOCK(hhash);
01025
01026       /* Return function status */
01027       return HAL_OK;
01028     }
01029   }
01030   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01031   {
01032     if(hhash->HashInCount >= 68U)
01033     {
01034       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01035       /* Write the Input block in the Data IN register */
01036       for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
01037       {
01038         HASH->DIN = *(uint32_t*)inputaddr;
01039         inputaddr+=4U;
01040       }
01041       if(hhash->HashITCounter == 0U)
01042       {
01043         HASH->DIN = *(uint32_t*)inputaddr;
01044         if(hhash->HashInCount >= 68U)
01045         {
01046           /* Decrement buffer counter */
01047           hhash->HashInCount -= 68U;
01048           hhash->pHashInBuffPtr+= 68U;
01049         }
01050         else
01051         {
01052           hhash->HashInCount = 0U;
01053           hhash->pHashInBuffPtr+= hhash->HashInCount;
01054         }
01055         /* Set Interrupt counter */
01056         hhash->HashITCounter = 1U;
01057       }
01058       else
01059       {
01060         /* Decrement buffer counter */
01061         hhash->HashInCount -= 64U;
01062         hhash->pHashInBuffPtr+= 64U;
01063       }
01064     }
01065     else
01066     {
01067       /* Get the buffer address */
01068       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01069       /* Get the buffer counter */
01070       inputcounter = hhash->HashInCount;
01071       /* Disable Interrupts */
01072       HASH->IMR &= ~(HASH_IT_DINI);
01073       /* Configure the number of valid bits in last word of the message */
01074       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
01075
01076       if((inputcounter > 4U) && (inputcounter%4U))
01077       {
01078         inputcounter = (inputcounter+4U-inputcounter%4U);
01079       }
01080       else if ((inputcounter < 4U) && (inputcounter != 0U))
01081       {
01082         inputcounter = 4U;
01083       }
01084       /* Write the Input block in the Data IN register */
01085       for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
01086       {
01087         HASH->DIN = *(uint32_t*)inputaddr;
01088         inputaddr+=4U;
01089       }
01090       /* Start the digest calculation */
01091       __HAL_HASH_START_DIGEST();
01092       /* Reset buffer counter */
01093       hhash->HashInCount = 0U;
01094       /* Call Input data transfer complete callback */
01095       HAL_HASH_InCpltCallback(hhash);
01096     }
01097   }
01098
01099   /* Process Unlocked */
01100   __HAL_UNLOCK(hhash);
01101
01102   /* Return function status */
01103   return HAL_OK;
01104 }
01105
01106 /**
01107   * @brief This function handles HASH interrupt request.
01108   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01109   *         the configuration information for HASH module
01110   * @retval None
01111   */
01112 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
01113 {
01114   switch(HASH->CR & HASH_CR_ALGO)
01115   {
01116     case HASH_ALGOSELECTION_MD5:
01117        HAL_HASH_MD5_Start_IT(hhash, NULL, 0U, NULL);
01118     break;
01119
01120     case HASH_ALGOSELECTION_SHA1:
01121       HAL_HASH_SHA1_Start_IT(hhash, NULL, 0U, NULL);
01122     break;
01123
01124     default:
01125     break;
01126   }
01127 }
01128
01129 /**
01130   * @}
01131   */
01132
01133 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
01134  *  @brief   processing functions using DMA mode.
01135  *
01136 @verbatim
01137  ===============================================================================
01138               ##### HASH processing using DMA mode functions #####
01139  ===============================================================================
01140     [..]  This section provides functions allowing to calculate in DMA mode
01141           the hash value using one of the following algorithms:
01142       (+) MD5
01143       (+) SHA1
01144
01145 @endverbatim
01146   * @{
01147   */
01148
01149 /**
01150   * @brief  Initializes the HASH peripheral in MD5 mode then enables DMA to
01151             control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
01152   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01153   *         the configuration information for HASH module
01154   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01155   * @param  Size: Length of the input buffer in bytes.
01156   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01157   * @retval HAL status
01158   */
01159 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01160 {
01161   uint32_t inputaddr  = (uint32_t)pInBuffer;
01162
01163    /* Process Locked */
01164   __HAL_LOCK(hhash);
01165
01166   /* Change the HASH state */
01167   hhash->State = HAL_HASH_STATE_BUSY;
01168
01169   /* Check if initialization phase has already been performed */
01170   if(hhash->Phase == HAL_HASH_PHASE_READY)
01171   {
01172     /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
01173        the message digest of a new message */
01174     HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
01175   }
01176
01177   /* Configure the number of valid bits in last word of the message */
01178   __HAL_HASH_SET_NBVALIDBITS(Size);
01179
01180   /* Set the phase */
01181   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01182
01183   /* Set the HASH DMA transfer complete callback */
01184   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01185   /* Set the DMA error callback */
01186   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01187
01188   /* Enable the DMA In DMA Stream */
01189   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
01190
01191   /* Enable DMA requests */
01192   HASH->CR |= (HASH_CR_DMAE);
01193
01194    /* Process Unlocked */
01195   __HAL_UNLOCK(hhash);
01196
01197   /* Return function status */
01198   return HAL_OK;
01199 }
01200
01201 /**
01202   * @brief  Returns the computed digest in MD5 mode
01203   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01204   *         the configuration information for HASH module
01205   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
01206   * @param  Timeout: Timeout value
01207   * @retval HAL status
01208   */
01209 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01210 {
01211   uint32_t tickstart = 0U;
01212
01213    /* Process Locked */
01214   __HAL_LOCK(hhash);
01215
01216   /* Change HASH peripheral state */
01217   hhash->State = HAL_HASH_STATE_BUSY;
01218
01219   /* Get tick */
01220   tickstart = HAL_GetTick();
01221
01222   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01223   {
01224     /* Check for the Timeout */
01225     if(Timeout != HAL_MAX_DELAY)
01226     {
01227       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01228       {
01229         /* Change state */
01230         hhash->State = HAL_HASH_STATE_TIMEOUT;
01231
01232         /* Process Unlocked */
01233         __HAL_UNLOCK(hhash);
01234
01235         return HAL_TIMEOUT;
01236       }
01237     }
01238   }
01239
01240   /* Read the message digest */
01241   HASH_GetDigest(pOutBuffer, 16U);
01242
01243   /* Change HASH peripheral state */
01244   hhash->State = HAL_HASH_STATE_READY;
01245
01246    /* Process Unlocked */
01247   __HAL_UNLOCK(hhash);
01248
01249   /* Return function status */
01250   return HAL_OK;
01251 }
01252
01253 /**
01254   * @brief  Initializes the HASH peripheral in SHA1 mode then enables DMA to
01255             control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
01256   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01257   *         the configuration information for HASH module
01258   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01259   * @param  Size: Length of the input buffer in bytes.
01260   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01261   * @retval HAL status
01262   */
01263 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01264 {
01265   uint32_t inputaddr  = (uint32_t)pInBuffer;
01266
01267    /* Process Locked */
01268   __HAL_LOCK(hhash);
01269
01270   /* Change the HASH state */
01271   hhash->State = HAL_HASH_STATE_BUSY;
01272
01273   /* Check if initialization phase has already been performed */
01274   if(hhash->Phase == HAL_HASH_PHASE_READY)
01275   {
01276     /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
01277        the message digest of a new message */
01278     HASH->CR |= HASH_ALGOSELECTION_SHA1;
01279     HASH->CR |= HASH_CR_INIT;
01280   }
01281
01282   /* Configure the number of valid bits in last word of the message */
01283   __HAL_HASH_SET_NBVALIDBITS(Size);
01284
01285   /* Set the phase */
01286   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01287
01288   /* Set the HASH DMA transfer complete callback */
01289   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01290   /* Set the DMA error callback */
01291   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01292
01293   /* Enable the DMA In DMA Stream */
01294   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
01295
01296   /* Enable DMA requests */
01297   HASH->CR |= (HASH_CR_DMAE);
01298
01299    /* Process Unlocked */
01300   __HAL_UNLOCK(hhash);
01301
01302   /* Return function status */
01303   return HAL_OK;
01304 }
01305
01306 /**
01307   * @brief  Returns the computed digest in SHA1 mode.
01308   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01309   *         the configuration information for HASH module
01310   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01311   * @param  Timeout: Timeout value
01312   * @retval HAL status
01313   */
01314 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01315 {
01316   uint32_t tickstart = 0U;
01317
01318    /* Process Locked */
01319   __HAL_LOCK(hhash);
01320
01321   /* Change HASH peripheral state */
01322   hhash->State = HAL_HASH_STATE_BUSY;
01323
01324   /* Get tick */
01325   tickstart = HAL_GetTick();
01326   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01327   {
01328     /* Check for the Timeout */
01329     if(Timeout != HAL_MAX_DELAY)
01330     {
01331       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01332       {
01333         /* Change state */
01334         hhash->State = HAL_HASH_STATE_TIMEOUT;
01335
01336         /* Process Unlocked */
01337         __HAL_UNLOCK(hhash);
01338
01339         return HAL_TIMEOUT;
01340       }
01341     }
01342   }
01343
01344   /* Read the message digest */
01345   HASH_GetDigest(pOutBuffer, 20U);
01346
01347   /* Change HASH peripheral state */
01348   hhash->State = HAL_HASH_STATE_READY;
01349
01350    /* Process UnLock */
01351   __HAL_UNLOCK(hhash);
01352
01353   /* Return function status */
01354   return HAL_OK;
01355 }
01356
01357
01358 /**
01359   * @}
01360   */
01361
01362 /** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
01363  *  @brief   HMAC processing functions using polling mode .
01364  *
01365 @verbatim
01366  ===============================================================================
01367               ##### HMAC processing using polling mode functions #####
01368  ===============================================================================
01369     [..]  This section provides functions allowing to calculate in polling mode
01370           the HMAC value using one of the following algorithms:
01371       (+) MD5
01372       (+) SHA1
01373
01374 @endverbatim
01375   * @{
01376   */
01377
01378 /**
01379   * @brief  Initializes the HASH peripheral in HMAC MD5 mode
01380   *         then processes pInBuffer. The digest is available in pOutBuffer
01381   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01382   *         the configuration information for HASH module
01383   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01384   * @param  Size: Length of the input buffer in bytes.
01385   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01386   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01387   * @param  Timeout: Timeout value
01388   * @retval HAL status
01389   */
01390 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
01391 {
01392   uint32_t tickstart = 0U;
01393
01394    /* Process Locked */
01395   __HAL_LOCK(hhash);
01396
01397   /* Change the HASH state */
01398   hhash->State = HAL_HASH_STATE_BUSY;
01399
01400   /* Check if initialization phase has already been performed */
01401   if(hhash->Phase == HAL_HASH_PHASE_READY)
01402   {
01403     /* Check if key size is greater than 64 bytes */
01404     if(hhash->Init.KeySize > 64U)
01405     {
01406       /* Select the HMAC MD5 mode */
01407       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01408     }
01409     else
01410     {
01411       /* Select the HMAC MD5 mode */
01412       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01413     }
01414   }
01415
01416   /* Set the phase */
01417   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01418
01419   /************************** STEP 1 ******************************************/
01420   /* Configure the number of valid bits in last word of the message */
01421   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01422
01423   /* Write input buffer in data register */
01424   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01425
01426   /* Start the digest calculation */
01427   __HAL_HASH_START_DIGEST();
01428
01429   /* Get tick */
01430   tickstart = HAL_GetTick();
01431
01432   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01433   {
01434     /* Check for the Timeout */
01435     if(Timeout != HAL_MAX_DELAY)
01436     {
01437       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01438       {
01439         /* Change state */
01440         hhash->State = HAL_HASH_STATE_TIMEOUT;
01441
01442         /* Process Unlocked */
01443         __HAL_UNLOCK(hhash);
01444
01445         return HAL_TIMEOUT;
01446       }
01447     }
01448   }
01449   /************************** STEP 2 ******************************************/
01450   /* Configure the number of valid bits in last word of the message */
01451   __HAL_HASH_SET_NBVALIDBITS(Size);
01452
01453   /* Write input buffer in data register */
01454   HASH_WriteData(pInBuffer, Size);
01455
01456   /* Start the digest calculation */
01457   __HAL_HASH_START_DIGEST();
01458
01459   /* Get tick */
01460   tickstart = HAL_GetTick();
01461
01462   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01463   {
01464     /* Check for the Timeout */
01465     if(Timeout != HAL_MAX_DELAY)
01466     {
01467       if((HAL_GetTick() - tickstart ) > Timeout)
01468       {
01469         /* Change state */
01470         hhash->State = HAL_HASH_STATE_TIMEOUT;
01471
01472         /* Process Unlocked */
01473         __HAL_UNLOCK(hhash);
01474
01475         return HAL_TIMEOUT;
01476       }
01477     }
01478   }
01479   /************************** STEP 3 ******************************************/
01480   /* Configure the number of valid bits in last word of the message */
01481   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01482
01483   /* Write input buffer in data register */
01484   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01485
01486   /* Start the digest calculation */
01487   __HAL_HASH_START_DIGEST();
01488
01489   /* Get tick */
01490   tickstart = HAL_GetTick();
01491
01492   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01493   {
01494     /* Check for the Timeout */
01495     if(Timeout != HAL_MAX_DELAY)
01496     {
01497       if((HAL_GetTick() - tickstart ) > Timeout)
01498       {
01499         /* Change state */
01500         hhash->State = HAL_HASH_STATE_TIMEOUT;
01501
01502         /* Process Unlocked */
01503         __HAL_UNLOCK(hhash);
01504
01505         return HAL_TIMEOUT;
01506       }
01507     }
01508   }
01509
01510   /* Read the message digest */
01511   HASH_GetDigest(pOutBuffer, 16U);
01512
01513   /* Change the HASH state */
01514   hhash->State = HAL_HASH_STATE_READY;
01515
01516   /* Process Unlocked */
01517   __HAL_UNLOCK(hhash);
01518
01519   /* Return function status */
01520   return HAL_OK;
01521 }
01522
01523 /**
01524   * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
01525   *         then processes pInBuffer. The digest is available in pOutBuffer.
01526   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01527   *         the configuration information for HASH module
01528   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01529   * @param   Size: Length of the input buffer in bytes.
01530   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01531   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01532   * @param  Timeout: Timeout value
01533   * @retval HAL status
01534   */
01535 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
01536 {
01537   uint32_t tickstart = 0U;
01538
01539   /* Process Locked */
01540   __HAL_LOCK(hhash);
01541
01542   /* Change the HASH state */
01543   hhash->State = HAL_HASH_STATE_BUSY;
01544
01545   /* Check if initialization phase has already been performed */
01546   if(hhash->Phase == HAL_HASH_PHASE_READY)
01547   {
01548     /* Check if key size is greater than 64 bytes */
01549     if(hhash->Init.KeySize > 64U)
01550     {
01551       /* Select the HMAC SHA1 mode */
01552       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01553     }
01554     else
01555     {
01556       /* Select the HMAC SHA1 mode */
01557       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01558     }
01559   }
01560
01561   /* Set the phase */
01562   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01563
01564   /************************** STEP 1 ******************************************/
01565   /* Configure the number of valid bits in last word of the message */
01566   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01567
01568   /* Write input buffer in data register */
01569   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01570
01571   /* Start the digest calculation */
01572   __HAL_HASH_START_DIGEST();
01573
01574   /* Get tick */
01575   tickstart = HAL_GetTick();
01576
01577   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01578   {
01579     /* Check for the Timeout */
01580     if(Timeout != HAL_MAX_DELAY)
01581     {
01582       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01583       {
01584         /* Change state */
01585         hhash->State = HAL_HASH_STATE_TIMEOUT;
01586
01587         /* Process Unlocked */
01588         __HAL_UNLOCK(hhash);
01589
01590         return HAL_TIMEOUT;
01591       }
01592     }
01593   }
01594   /************************** STEP 2 ******************************************/
01595   /* Configure the number of valid bits in last word of the message */
01596   __HAL_HASH_SET_NBVALIDBITS(Size);
01597
01598   /* Write input buffer in data register */
01599   HASH_WriteData(pInBuffer, Size);
01600
01601   /* Start the digest calculation */
01602   __HAL_HASH_START_DIGEST();
01603
01604   /* Get tick */
01605   tickstart = HAL_GetTick();
01606
01607   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01608   {
01609     /* Check for the Timeout */
01610     if(Timeout != HAL_MAX_DELAY)
01611     {
01612       if((HAL_GetTick() - tickstart ) > Timeout)
01613       {
01614         /* Change state */
01615         hhash->State = HAL_HASH_STATE_TIMEOUT;
01616
01617         /* Process Unlocked */
01618         __HAL_UNLOCK(hhash);
01619
01620         return HAL_TIMEOUT;
01621       }
01622     }
01623   }
01624   /************************** STEP 3 ******************************************/
01625   /* Configure the number of valid bits in last word of the message */
01626   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01627
01628   /* Write input buffer in data register */
01629   HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
01630
01631   /* Start the digest calculation */
01632   __HAL_HASH_START_DIGEST();
01633
01634   /* Get tick */
01635   tickstart = HAL_GetTick();
01636
01637   while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
01638   {
01639     /* Check for the Timeout */
01640     if(Timeout != HAL_MAX_DELAY)
01641     {
01642       if((HAL_GetTick() - tickstart ) > Timeout)
01643       {
01644         /* Change state */
01645         hhash->State = HAL_HASH_STATE_TIMEOUT;
01646
01647         /* Process Unlocked */
01648         __HAL_UNLOCK(hhash);
01649
01650         return HAL_TIMEOUT;
01651       }
01652     }
01653   }
01654   /* Read the message digest */
01655   HASH_GetDigest(pOutBuffer, 20U);
01656
01657   /* Change the HASH state */
01658   hhash->State = HAL_HASH_STATE_READY;
01659
01660   /* Process Unlocked */
01661   __HAL_UNLOCK(hhash);
01662
01663   /* Return function status */
01664   return HAL_OK;
01665 }
01666
01667 /**
01668   * @}
01669   */
01670
01671 /** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
01672  *  @brief   HMAC processing functions using DMA mode .
01673  *
01674 @verbatim
01675  ===============================================================================
01676                 ##### HMAC processing using DMA mode functions #####
01677  ===============================================================================
01678     [..]  This section provides functions allowing to calculate in DMA mode
01679           the HMAC value using one of the following algorithms:
01680       (+) MD5
01681       (+) SHA1
01682
01683 @endverbatim
01684   * @{
01685   */
01686
01687 /**
01688   * @brief  Initializes the HASH peripheral in HMAC MD5 mode
01689   *         then enables DMA to control data transfer.
01690   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01691   *         the configuration information for HASH module
01692   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01693   * @param  Size: Length of the input buffer in bytes.
01694   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01695   * @retval HAL status
01696   */
01697 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01698 {
01699   uint32_t inputaddr  = 0U;
01700
01701    /* Process Locked */
01702   __HAL_LOCK(hhash);
01703
01704   /* Change the HASH state */
01705   hhash->State = HAL_HASH_STATE_BUSY;
01706
01707   /* Save buffer pointer and size in handle */
01708   hhash->pHashInBuffPtr = pInBuffer;
01709   hhash->HashBuffSize = Size;
01710   hhash->HashInCount = 0U;
01711
01712   /* Check if initialization phase has already been performed */
01713   if(hhash->Phase == HAL_HASH_PHASE_READY)
01714   {
01715     /* Check if key size is greater than 64 bytes */
01716     if(hhash->Init.KeySize > 64U)
01717     {
01718       /* Select the HMAC MD5 mode */
01719       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01720     }
01721     else
01722     {
01723       /* Select the HMAC MD5 mode */
01724       HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01725     }
01726   }
01727
01728   /* Set the phase */
01729   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01730
01731   /* Configure the number of valid bits in last word of the message */
01732   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01733
01734   /* Get the key address */
01735   inputaddr = (uint32_t)(hhash->Init.pKey);
01736
01737   /* Set the HASH DMA transfer complete callback */
01738   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01739   /* Set the DMA error callback */
01740   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01741
01742   /* Enable the DMA In DMA Stream */
01743   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
01744   /* Enable DMA requests */
01745   HASH->CR |= (HASH_CR_DMAE);
01746
01747   /* Process Unlocked */
01748   __HAL_UNLOCK(hhash);
01749
01750   /* Return function status */
01751   return HAL_OK;
01752 }
01753
01754 /**
01755   * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
01756   *         then enables DMA to control data transfer.
01757   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01758   *         the configuration information for HASH module
01759   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01760   * @param  Size: Length of the input buffer in bytes.
01761   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01762   * @retval HAL status
01763   */
01764 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01765 {
01766   uint32_t inputaddr  = 0U;
01767
01768   /* Process Locked */
01769   __HAL_LOCK(hhash);
01770
01771   /* Change the HASH state */
01772   hhash->State = HAL_HASH_STATE_BUSY;
01773
01774   /* Save buffer pointer and size in handle */
01775   hhash->pHashInBuffPtr = pInBuffer;
01776   hhash->HashBuffSize = Size;
01777   hhash->HashInCount = 0U;
01778
01779   /* Check if initialization phase has already been performed */
01780   if(hhash->Phase == HAL_HASH_PHASE_READY)
01781   {
01782     /* Check if key size is greater than 64 bytes */
01783     if(hhash->Init.KeySize > 64U)
01784     {
01785       /* Select the HMAC SHA1 mode */
01786       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01787     }
01788     else
01789     {
01790       /* Select the HMAC SHA1 mode */
01791       HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01792     }
01793   }
01794
01795   /* Set the phase */
01796   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01797
01798   /* Configure the number of valid bits in last word of the message */
01799   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01800
01801   /* Get the key address */
01802   inputaddr = (uint32_t)(hhash->Init.pKey);
01803
01804   /* Set the HASH DMA transfer complete callback */
01805   hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
01806   /* Set the DMA error callback */
01807   hhash->hdmain->XferErrorCallback = HASH_DMAError;
01808
01809   /* Enable the DMA In DMA Stream */
01810   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
01811   /* Enable DMA requests */
01812   HASH->CR |= (HASH_CR_DMAE);
01813
01814   /* Process Unlocked */
01815   __HAL_UNLOCK(hhash);
01816
01817   /* Return function status */
01818   return HAL_OK;
01819 }
01820
01821 /**
01822   * @}
01823   */
01824
01825 /** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
01826  *  @brief   Peripheral State functions.
01827  *
01828 @verbatim
01829  ===============================================================================
01830                       ##### Peripheral State functions #####
01831  ===============================================================================
01832     [..]
01833     This subsection permits to get in run-time the status of the peripheral.
01834
01835 @endverbatim
01836   * @{
01837   */
01838
01839 /**
01840   * @brief return the HASH state
01841   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01842   *         the configuration information for HASH module
01843   * @retval HAL state
01844   */
01845 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
01846 {
01847   return hhash->State;
01848 }
01849
01850 /**
01851   * @}
01852   */
01853
01854 /**
01855   * @}
01856   */
01857
01858 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
01859 #endif /* HAL_HASH_MODULE_ENABLED */
01860 /**
01861   * @}
01862   */
01863
01864 /**
01865   * @}
01866   */
01867
01868 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash.h Source File

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stm32f4xx_hal_hash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_hash.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of HASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_HASH_H
00040 #define __STM32F4xx_HAL_HASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f4xx_hal_def.h"
00050
00051 /** @addtogroup STM32F4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup HASH
00056   * @brief HASH HAL module driver
00057   *  @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup HASH_Exported_Types HASH Exported Types
00062   * @{
00063   */
00064
00065 /** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
00066   * @{
00067   */
00068
00069 typedef struct
00070 {
00071   uint32_t DataType;  /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00072                            This parameter can be a value of @ref HASH_Data_Type */
00073
00074   uint32_t KeySize;   /*!< The key size is used only in HMAC operation          */
00075
00076   uint8_t* pKey;      /*!< The key is used only in HMAC operation               */
00077 }HASH_InitTypeDef;
00078
00079 /**
00080   * @}
00081   */
00082
00083 /** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
00084   * @{
00085   */
00086
00087 typedef enum
00088 {
00089   HAL_HASH_STATE_RESET     = 0x00U,  /*!< HASH not yet initialized or disabled */
00090   HAL_HASH_STATE_READY     = 0x01U,  /*!< HASH initialized and ready for use   */
00091   HAL_HASH_STATE_BUSY      = 0x02U,  /*!< HASH internal process is ongoing     */
00092   HAL_HASH_STATE_TIMEOUT   = 0x03U,  /*!< HASH timeout state                   */
00093   HAL_HASH_STATE_ERROR     = 0x04U   /*!< HASH error state                     */
00094 }HAL_HASH_StateTypeDef;
00095
00096 /**
00097   * @}
00098   */
00099
00100 /** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
00101   * @{
00102   */
00103
00104 typedef enum
00105 {
00106   HAL_HASH_PHASE_READY     = 0x01U,  /*!< HASH peripheral is ready for initialization */
00107   HAL_HASH_PHASE_PROCESS   = 0x02U  /*!< HASH peripheral is in processing phase      */
00108 }HAL_HASH_PhaseTypeDef;
00109
00110 /**
00111   * @}
00112   */
00113
00114 /** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
00115   * @{
00116   */
00117
00118 typedef struct
00119 {
00120       HASH_InitTypeDef           Init;              /*!< HASH required parameters       */
00121
00122       uint8_t                    *pHashInBuffPtr;   /*!< Pointer to input buffer        */
00123
00124       uint8_t                    *pHashOutBuffPtr;  /*!< Pointer to input buffer        */
00125
00126      __IO uint32_t               HashBuffSize;      /*!< Size of buffer to be processed */
00127
00128      __IO uint32_t               HashInCount;       /*!< Counter of inputed data        */
00129
00130      __IO uint32_t               HashITCounter;     /*!< Counter of issued interrupts   */
00131
00132       HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */
00133
00134       HAL_HASH_PhaseTypeDef       Phase;             /*!< HASH peripheral phase          */
00135
00136       DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */
00137
00138       HAL_LockTypeDef            Lock;              /*!< HASH locking object            */
00139
00140      __IO HAL_HASH_StateTypeDef  State;             /*!< HASH peripheral state          */
00141 } HASH_HandleTypeDef;
00142
00143 /**
00144   * @}
00145   */
00146
00147
00148 /**
00149   * @}
00150   */
00151
00152 /* Exported constants --------------------------------------------------------*/
00153 /** @defgroup HASH_Exported_Constants HASH Exported Constants
00154   * @{
00155   */
00156
00157 /** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
00158   * @{
00159   */
00160 #define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x00000000U)  /*!< HASH function is SHA1   */
00161 #define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1      /*!< HASH function is SHA224 */
00162 #define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO        /*!< HASH function is SHA256 */
00163 #define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0      /*!< HASH function is MD5    */
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
00169   * @{
00170   */
00171 #define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000U)  /*!< Algorithm is HASH */
00172 #define HASH_ALGOMODE_HMAC         HASH_CR_MODE            /*!< Algorithm is HMAC */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup HASH_Data_Type HASH Data Type
00178   * @{
00179   */
00180 #define HASH_DATATYPE_32B          ((uint32_t)0x00000000U) /*!< 32-bit data. No swapping                     */
00181 #define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
00182 #define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
00183 #define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
00189   * @brief HASH HMAC Long key used only for HMAC mode
00190   * @{
00191   */
00192 #define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000U)  /*!< HMAC Key is <= 64 bytes */
00193 #define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY            /*!< HMAC Key is > 64 bytes  */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
00199   * @{
00200   */
00201 #define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
00202 #define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
00203 #define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
00204 #define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
00205 #define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
00211   * @{
00212   */
00213 #define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
00214 #define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
00215 /**
00216   * @}
00217   */
00218
00219 /**
00220   * @}
00221   */
00222
00223 /* Exported macro ------------------------------------------------------------*/
00224 /** @defgroup HASH_Exported_Macros HASH Exported Macros
00225   * @{
00226   */
00227
00228 /** @brief Reset HASH handle state
00229   * @param  __HANDLE__: specifies the HASH handle.
00230   * @retval None
00231   */
00232 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
00233
00234 /** @brief  Check whether the specified HASH flag is set or not.
00235   * @param  __FLAG__: specifies the flag to check.
00236   *         This parameter can be one of the following values:
00237   *            @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
00238   *            @arg HASH_FLAG_DCIS: Digest calculation complete
00239   *            @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
00240   *            @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
00241   *            @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
00242   * @retval The new state of __FLAG__ (TRUE or FALSE).
00243   */
00244 #define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
00245                                                            ((HASH->SR & (__FLAG__)) == (__FLAG__)))
00246
00247 /**
00248   * @brief  Enable the multiple DMA mode.
00249   *         This feature is available only in STM32F429x and STM32F439x devices.
00250   * @retval None
00251   */
00252 #define __HAL_HASH_SET_MDMAT()          HASH->CR |= HASH_CR_MDMAT
00253
00254 /**
00255   * @brief  Disable the multiple DMA mode.
00256   * @retval None
00257   */
00258 #define __HAL_HASH_RESET_MDMAT()        HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
00259
00260 /**
00261   * @brief  Start the digest computation
00262   * @retval None
00263   */
00264 #define __HAL_HASH_START_DIGEST()       HASH->STR |= HASH_STR_DCAL
00265
00266 /**
00267   * @brief Set the number of valid bits in last word written in Data register
00268   * @param  SIZE: size in byte of last data written in Data register.
00269   * @retval None
00270 */
00271 #define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
00272                                             HASH->STR |= 8U * ((SIZE) % 4U);\
00273                                            }while(0)
00274
00275 /**
00276   * @}
00277   */
00278
00279 /* Include HASH HAL Extension module */
00280 #include "stm32f4xx_hal_hash_ex.h"
00281 /* Exported functions --------------------------------------------------------*/
00282
00283 /** @defgroup HASH_Exported_Functions HASH Exported Functions
00284   * @{
00285   */
00286
00287 /** @addtogroup HASH_Exported_Functions_Group1
00288   * @{
00289   */
00290 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
00291 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
00292 /**
00293   * @}
00294   */
00295
00296 /** @addtogroup HASH_Exported_Functions_Group2
00297   * @{
00298   */
00299 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00300 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00301 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00302 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00303 /**
00304   * @}
00305   */
00306
00307 /** @addtogroup HASH_Exported_Functions_Group3
00308   * @{
00309   */
00310 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00311 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00312 /**
00313   * @}
00314   */
00315
00316 /** @addtogroup HASH_Exported_Functions_Group4
00317   * @{
00318   */
00319 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00320 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00321 /**
00322   * @}
00323   */
00324
00325 /** @addtogroup HASH_Exported_Functions_Group5
00326   * @{
00327   */
00328 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00329 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00330 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00331 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00332 /**
00333   * @}
00334   */
00335
00336 /** @addtogroup HASH_Exported_Functions_Group6
00337   * @{
00338   */
00339 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00340 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00341 /**
00342   * @}
00343   */
00344
00345 /** @addtogroup HASH_Exported_Functions_Group7
00346   * @{
00347   */
00348 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
00349 /**
00350   * @}
00351   */
00352
00353 /** @addtogroup HASH_Exported_Functions_Group8
00354   * @{
00355   */
00356 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
00357 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
00358 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
00359 void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
00360 void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
00361 void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
00362 /**
00363   * @}
00364   */
00365
00366  /**
00367   * @}
00368   */
00369
00370  /* Private types -------------------------------------------------------------*/
00371 /** @defgroup HASH_Private_Types HASH Private Types
00372   * @{
00373   */
00374
00375 /**
00376   * @}
00377   */
00378
00379 /* Private variables ---------------------------------------------------------*/
00380 /** @defgroup HASH_Private_Variables HASH Private Variables
00381   * @{
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 /* Private constants ---------------------------------------------------------*/
00389 /** @defgroup HASH_Private_Constants HASH Private Constants
00390   * @{
00391   */
00392
00393 /**
00394   * @}
00395   */
00396
00397 /* Private macros ------------------------------------------------------------*/
00398 /** @defgroup HASH_Private_Macros HASH Private Macros
00399   * @{
00400   */
00401 #define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1)   || \
00402                                                   ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
00403                                                   ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
00404                                                   ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
00405
00406
00407 #define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
00408                                         ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
00409
00410
00411 #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
00412                                         ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
00413                                         ((__DATATYPE__) == HASH_DATATYPE_8B) || \
00414                                         ((__DATATYPE__) == HASH_DATATYPE_1B))
00415
00416
00417 #define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
00418                                            ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
00419
00420 #define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0U)? 0U: 1U)
00421
00422 /**
00423   * @}
00424   */
00425
00426 /* Private functions ---------------------------------------------------------*/
00427 /** @defgroup HASH_Private_Functions HASH Private Functions
00428   * @{
00429   */
00430
00431 /**
00432   * @}
00433   */
00434
00435 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
00436 /**
00437   * @}
00438   */
00439
00440 /**
00441   * @}
00442   */
00443
00444 #ifdef __cplusplus
00445 }
00446 #endif
00447
00448
00449 #endif /* __STM32F4xx_HAL_HASH_H */
00450
00451 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash_ex.c Source File

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stm32f4xx_hal_hash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_hash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   HASH HAL Extension module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of HASH peripheral:
00010   *           + Extended HASH processing functions based on SHA224 Algorithm
00011   *           + Extended HASH processing functions based on SHA256 Algorithm
00012   *
00013   @verbatim
00014   ==============================================================================
00015                      ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018     The HASH HAL driver can be used as follows:
00019     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
00020         (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
00021         (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
00022             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
00023             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
00024             (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
00025         (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
00026             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
00027             (+++) Configure and enable one DMA stream one for managing data transfer from
00028                 memory to peripheral (input stream). Managing data transfer from
00029                 peripheral to memory can be performed only using CPU
00030             (+++) Associate the initialized DMA handle to the HASH DMA handle
00031                 using  __HAL_LINKDMA()
00032             (+++) Configure the priority and enable the NVIC for the transfer complete
00033                 interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00034     (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
00035         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
00036         (##) For HMAC, the encryption key.
00037         (##) For HMAC, the key size used for encryption.
00038     (#)Three processing functions are available:
00039         (##) Polling mode: processing APIs are blocking functions
00040              i.e. they process the data and wait till the digest computation is finished
00041              e.g. HAL_HASHEx_SHA224_Start()
00042         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00043                 i.e. they process the data under interrupt
00044                 e.g. HAL_HASHEx_SHA224_Start_IT()
00045         (##) DMA mode: processing APIs are not blocking functions and the CPU is
00046              not used for data transfer i.e. the data transfer is ensured by DMA
00047                 e.g. HAL_HASHEx_SHA224_Start_DMA()
00048     (#)When the processing function is called at first time after HAL_HASH_Init()
00049        the HASH peripheral is initialized and processes the buffer in input.
00050        After that, the digest computation is started.
00051        When processing multi-buffer use the accumulate function to write the
00052        data in the peripheral without starting the digest computation. In last
00053        buffer use the start function to input the last buffer ans start the digest
00054        computation.
00055        (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
00056        (##)  write (n-1)th data buffer in the peripheral without starting the digest computation
00057        (##)  HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
00058     (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
00059     (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
00060        After that, call the finish function in order to get the digest value
00061        e.g. HAL_HASHEx_SHA224_Finish()
00062     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
00063
00064   @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00069   *
00070   * Redistribution and use in source and binary forms, with or without modification,
00071   * are permitted provided that the following conditions are met:
00072   *   1. Redistributions of source code must retain the above copyright notice,
00073   *      this list of conditions and the following disclaimer.
00074   *   2. Redistributions in binary form must reproduce the above copyright notice,
00075   *      this list of conditions and the following disclaimer in the documentation
00076   *      and/or other materials provided with the distribution.
00077   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00078   *      may be used to endorse or promote products derived from this software
00079   *      without specific prior written permission.
00080   *
00081   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00082   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00083   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00084   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00085   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00086   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00087   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00088   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00089   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00090   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00091   *
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32f4xx_hal.h"
00097
00098 /** @addtogroup STM32F4xx_HAL_Driver
00099   * @{
00100   */
00101
00102 /** @defgroup HASHEx HASHEx
00103   * @brief HASH Extension HAL module driver.
00104   * @{
00105   */
00106
00107 #ifdef HAL_HASH_MODULE_ENABLED
00108
00109 #if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00110
00111 /* Private typedef -----------------------------------------------------------*/
00112 /* Private define ------------------------------------------------------------*/
00113 /* Private macro -------------------------------------------------------------*/
00114 /* Private variables ---------------------------------------------------------*/
00115 /* Private function prototypes -----------------------------------------------*/
00116 /** @addtogroup HASHEx_Private_Functions
00117   * @{
00118   */
00119 static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
00120 static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
00121 static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
00122 static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
00123 /**
00124   * @}
00125   */
00126
00127 /* Private functions ---------------------------------------------------------*/
00128
00129 /** @addtogroup HASHEx_Private_Functions
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  Writes the input buffer in data register.
00135   * @param  pInBuffer: Pointer to input buffer
00136   * @param  Size: The size of input buffer
00137   * @retval None
00138   */
00139 static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
00140 {
00141   uint32_t buffercounter;
00142   uint32_t inputaddr = (uint32_t) pInBuffer;
00143
00144   for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
00145   {
00146     HASH->DIN = *(uint32_t*)inputaddr;
00147     inputaddr+=4U;
00148   }
00149 }
00150
00151 /**
00152   * @brief  Provides the message digest result.
00153   * @param  pMsgDigest: Pointer to the message digest
00154   * @param  Size: The size of the message digest in bytes
00155   * @retval None
00156   */
00157 static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
00158 {
00159   uint32_t msgdigest = (uint32_t)pMsgDigest;
00160
00161   switch(Size)
00162   {
00163   case 16U:
00164     /* Read the message digest */
00165     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00166     msgdigest+=4U;
00167     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00168     msgdigest+=4U;
00169     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00170     msgdigest+=4U;
00171     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00172     break;
00173   case 20U:
00174     /* Read the message digest */
00175     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00176     msgdigest+=4U;
00177     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00178     msgdigest+=4U;
00179     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00180     msgdigest+=4U;
00181     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00182     msgdigest+=4U;
00183     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
00184     break;
00185   case 28U:
00186     /* Read the message digest */
00187     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00188     msgdigest+=4U;
00189     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00190     msgdigest+=4U;
00191     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00192     msgdigest+=4U;
00193     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00194     msgdigest+=4U;
00195     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
00196     msgdigest+=4U;
00197     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
00198     msgdigest+=4U;
00199     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
00200     break;
00201   case 32U:
00202     /* Read the message digest */
00203     *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
00204     msgdigest+=4U;
00205     *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
00206     msgdigest+=4U;
00207     *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
00208     msgdigest+=4U;
00209     *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
00210     msgdigest+=4U;
00211     *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
00212     msgdigest+=4U;
00213     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
00214     msgdigest+=4U;
00215     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
00216     msgdigest+=4U;
00217     *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7U]);
00218     break;
00219   default:
00220     break;
00221   }
00222 }
00223
00224 /**
00225   * @brief  DMA HASH Input Data complete callback.
00226   * @param  hdma: DMA handle
00227   * @retval None
00228   */
00229 static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
00230 {
00231   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00232   uint32_t inputaddr = 0U;
00233   uint32_t buffersize = 0U;
00234
00235   if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
00236   {
00237     /* Disable the DMA transfer */
00238     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00239
00240     /* Change HASH peripheral state */
00241     hhash->State = HAL_HASH_STATE_READY;
00242
00243     /* Call Input data transfer complete callback */
00244     HAL_HASH_InCpltCallback(hhash);
00245   }
00246   else
00247   {
00248     /* Increment Interrupt counter */
00249     hhash->HashInCount++;
00250     /* Disable the DMA transfer before starting the next transfer */
00251     HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00252
00253     if(hhash->HashInCount <= 2U)
00254     {
00255       /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
00256       if(hhash->HashInCount == 1U)
00257       {
00258         inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00259         buffersize = hhash->HashBuffSize;
00260       }
00261       /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
00262       else if(hhash->HashInCount == 2U)
00263       {
00264         inputaddr = (uint32_t)hhash->Init.pKey;
00265         buffersize = hhash->Init.KeySize;
00266       }
00267       /* Configure the number of valid bits in last word of the message */
00268       MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
00269
00270       /* Set the HASH DMA transfer complete */
00271       hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
00272
00273       /* Enable the DMA In DMA Stream */
00274       HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
00275
00276       /* Enable DMA requests */
00277       HASH->CR |= (HASH_CR_DMAE);
00278     }
00279     else
00280     {
00281       /* Disable the DMA transfer */
00282       HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
00283
00284       /* Reset the InCount */
00285       hhash->HashInCount = 0U;
00286
00287       /* Change HASH peripheral state */
00288       hhash->State = HAL_HASH_STATE_READY;
00289
00290       /* Call Input data transfer complete callback */
00291       HAL_HASH_InCpltCallback(hhash);
00292     }
00293   }
00294 }
00295
00296 /**
00297   * @brief  DMA HASH communication error callback.
00298   * @param  hdma: DMA handle
00299   * @retval None
00300   */
00301 static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
00302 {
00303   HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00304   hhash->State= HAL_HASH_STATE_READY;
00305   HAL_HASH_ErrorCallback(hhash);
00306 }
00307
00308  /**
00309   * @}
00310   */
00311
00312 /* Exported functions --------------------------------------------------------*/
00313 /** @addtogroup HASHEx_Exported_Functions
00314   * @{
00315   */
00316
00317 /** @defgroup  HASHEx_Group1 HASH processing functions
00318  *  @brief   processing functions using polling mode
00319  *
00320 @verbatim
00321  ===============================================================================
00322               ##### HASH processing using polling mode functions #####
00323  ===============================================================================
00324     [..]  This section provides functions allowing to calculate in polling mode
00325           the hash value using one of the following algorithms:
00326       (+) SHA224
00327       (+) SHA256
00328
00329 @endverbatim
00330   * @{
00331   */
00332
00333 /**
00334   * @brief  Initializes the HASH peripheral in SHA224 mode
00335   *         then processes pInBuffer. The digest is available in pOutBuffer
00336   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00337   *         the configuration information for HASH module
00338   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00339   * @param  Size: Length of the input buffer in bytes.
00340   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00341   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
00342   * @param  Timeout: Specify Timeout value
00343   * @retval HAL status
00344   */
00345 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00346 {
00347   uint32_t tickstart = 0U;
00348
00349   /* Process Locked */
00350   __HAL_LOCK(hhash);
00351
00352   /* Change the HASH state */
00353   hhash->State = HAL_HASH_STATE_BUSY;
00354
00355   /* Check if initialization phase has already been performed */
00356   if(hhash->Phase == HAL_HASH_PHASE_READY)
00357   {
00358     /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
00359        the message digest of a new message */
00360     HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
00361   }
00362
00363   /* Set the phase */
00364   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00365
00366   /* Configure the number of valid bits in last word of the message */
00367   __HAL_HASH_SET_NBVALIDBITS(Size);
00368
00369   /* Write input buffer in data register */
00370   HASHEx_WriteData(pInBuffer, Size);
00371
00372   /* Start the digest calculation */
00373   __HAL_HASH_START_DIGEST();
00374
00375   /* Get tick */
00376   tickstart = HAL_GetTick();
00377
00378   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00379   {
00380     /* Check for the Timeout */
00381     if(Timeout != HAL_MAX_DELAY)
00382     {
00383       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00384       {
00385         /* Change state */
00386         hhash->State = HAL_HASH_STATE_TIMEOUT;
00387
00388         /* Process Unlocked */
00389         __HAL_UNLOCK(hhash);
00390
00391         return HAL_TIMEOUT;
00392       }
00393     }
00394   }
00395
00396   /* Read the message digest */
00397   HASHEx_GetDigest(pOutBuffer, 28U);
00398
00399   /* Change the HASH state */
00400   hhash->State = HAL_HASH_STATE_READY;
00401
00402   /* Process Unlocked */
00403   __HAL_UNLOCK(hhash);
00404
00405   /* Return function status */
00406   return HAL_OK;
00407 }
00408
00409 /**
00410   * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
00411             The digest is available in pOutBuffer.
00412   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00413   *         the configuration information for HASH module
00414   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00415   * @param  Size: Length of the input buffer in bytes.
00416   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00417   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
00418   * @param  Timeout: Specify Timeout value
00419   * @retval HAL status
00420   */
00421 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00422 {
00423   uint32_t tickstart = 0U;
00424
00425   /* Process Locked */
00426   __HAL_LOCK(hhash);
00427
00428   /* Change the HASH state */
00429   hhash->State = HAL_HASH_STATE_BUSY;
00430
00431   /* Check if initialization phase has already been performed */
00432   if(hhash->Phase == HAL_HASH_PHASE_READY)
00433   {
00434     /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
00435        the message digest of a new message */
00436     HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
00437   }
00438
00439   /* Set the phase */
00440   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00441
00442   /* Configure the number of valid bits in last word of the message */
00443   __HAL_HASH_SET_NBVALIDBITS(Size);
00444
00445   /* Write input buffer in data register */
00446   HASHEx_WriteData(pInBuffer, Size);
00447
00448   /* Start the digest calculation */
00449   __HAL_HASH_START_DIGEST();
00450
00451   /* Get tick */
00452   tickstart = HAL_GetTick();
00453
00454   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00455   {
00456     /* Check for the Timeout */
00457     if(Timeout != HAL_MAX_DELAY)
00458     {
00459       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00460       {
00461         /* Change state */
00462         hhash->State = HAL_HASH_STATE_TIMEOUT;
00463
00464         /* Process Unlocked */
00465         __HAL_UNLOCK(hhash);
00466
00467         return HAL_TIMEOUT;
00468       }
00469     }
00470   }
00471
00472   /* Read the message digest */
00473   HASHEx_GetDigest(pOutBuffer, 32U);
00474
00475   /* Change the HASH state */
00476   hhash->State = HAL_HASH_STATE_READY;
00477
00478   /* Process Unlocked */
00479   __HAL_UNLOCK(hhash);
00480
00481   /* Return function status */
00482   return HAL_OK;
00483 }
00484
00485
00486 /**
00487   * @brief  Initializes the HASH peripheral in SHA224 mode
00488   *         then processes pInBuffer. The digest is available in pOutBuffer
00489   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00490   *         the configuration information for HASH module
00491   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00492   * @param  Size: Length of the input buffer in bytes.
00493   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00494   * @retval HAL status
00495   */
00496 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00497 {
00498   /* Process Locked */
00499   __HAL_LOCK(hhash);
00500
00501   /* Change the HASH state */
00502   hhash->State = HAL_HASH_STATE_BUSY;
00503
00504   /* Check if initialization phase has already been performed */
00505   if(hhash->Phase == HAL_HASH_PHASE_READY)
00506   {
00507     /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
00508        the message digest of a new message */
00509     HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
00510   }
00511
00512   /* Set the phase */
00513   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00514
00515   /* Configure the number of valid bits in last word of the message */
00516   __HAL_HASH_SET_NBVALIDBITS(Size);
00517
00518   /* Write input buffer in data register */
00519   HASHEx_WriteData(pInBuffer, Size);
00520
00521   /* Change the HASH state */
00522   hhash->State = HAL_HASH_STATE_READY;
00523
00524   /* Process Unlocked */
00525   __HAL_UNLOCK(hhash);
00526
00527   /* Return function status */
00528   return HAL_OK;
00529 }
00530
00531
00532 /**
00533   * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
00534             The digest is available in pOutBuffer.
00535   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00536   *         the configuration information for HASH module
00537   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00538   * @param  Size: Length of the input buffer in bytes.
00539   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00540   * @retval HAL status
00541   */
00542 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
00543 {
00544    /* Process Locked */
00545   __HAL_LOCK(hhash);
00546
00547   /* Change the HASH state */
00548   hhash->State = HAL_HASH_STATE_BUSY;
00549
00550   /* Check if initialization phase has already been performed */
00551   if(hhash->Phase == HAL_HASH_PHASE_READY)
00552   {
00553     /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
00554        the message digest of a new message */
00555     HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
00556   }
00557
00558   /* Set the phase */
00559   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00560
00561   /* Configure the number of valid bits in last word of the message */
00562   __HAL_HASH_SET_NBVALIDBITS(Size);
00563
00564   /* Write input buffer in data register */
00565   HASHEx_WriteData(pInBuffer, Size);
00566
00567   /* Change the HASH state */
00568   hhash->State = HAL_HASH_STATE_READY;
00569
00570   /* Process Unlocked */
00571   __HAL_UNLOCK(hhash);
00572
00573   /* Return function status */
00574   return HAL_OK;
00575 }
00576
00577
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
00583  *  @brief   HMAC processing functions using polling mode .
00584  *
00585 @verbatim
00586  ===============================================================================
00587             ##### HMAC processing using polling mode functions #####
00588  ===============================================================================
00589     [..]  This section provides functions allowing to calculate in polling mode
00590           the HMAC value using one of the following algorithms:
00591       (+) SHA224
00592       (+) SHA256
00593
00594 @endverbatim
00595   * @{
00596   */
00597
00598 /**
00599   * @brief  Initializes the HASH peripheral in HMAC SHA224 mode
00600   *         then processes pInBuffer. The digest is available in pOutBuffer.
00601   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00602   *         the configuration information for HASH module
00603   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00604   * @param  Size: Length of the input buffer in bytes.
00605   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00606   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00607   * @param  Timeout: Timeout value
00608   * @retval HAL status
00609   */
00610 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00611 {
00612   uint32_t tickstart = 0U;
00613
00614    /* Process Locked */
00615   __HAL_LOCK(hhash);
00616
00617   /* Change the HASH state */
00618   hhash->State = HAL_HASH_STATE_BUSY;
00619
00620   /* Check if initialization phase has already been performed */
00621   if(hhash->Phase == HAL_HASH_PHASE_READY)
00622   {
00623     /* Check if key size is greater than 64 bytes */
00624     if(hhash->Init.KeySize > 64U)
00625     {
00626       /* Select the HMAC SHA224 mode */
00627       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
00628     }
00629     else
00630     {
00631       /* Select the HMAC SHA224 mode */
00632       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
00633     }
00634   }
00635
00636   /* Set the phase */
00637   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00638
00639   /************************** STEP 1 ******************************************/
00640   /* Configure the number of valid bits in last word of the message */
00641   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00642
00643   /* Write input buffer in data register */
00644   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00645
00646   /* Start the digest calculation */
00647   __HAL_HASH_START_DIGEST();
00648
00649   /* Get tick */
00650   tickstart = HAL_GetTick();
00651
00652   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00653   {
00654     /* Check for the Timeout */
00655     if(Timeout != HAL_MAX_DELAY)
00656     {
00657       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00658       {
00659         /* Change state */
00660         hhash->State = HAL_HASH_STATE_TIMEOUT;
00661
00662         /* Process Unlocked */
00663         __HAL_UNLOCK(hhash);
00664
00665         return HAL_TIMEOUT;
00666       }
00667     }
00668   }
00669   /************************** STEP 2 ******************************************/
00670   /* Configure the number of valid bits in last word of the message */
00671   __HAL_HASH_SET_NBVALIDBITS(Size);
00672
00673   /* Write input buffer in data register */
00674   HASHEx_WriteData(pInBuffer, Size);
00675
00676   /* Start the digest calculation */
00677   __HAL_HASH_START_DIGEST();
00678
00679   /* Get tick */
00680   tickstart = HAL_GetTick();
00681
00682   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00683   {
00684     /* Check for the Timeout */
00685     if(Timeout != HAL_MAX_DELAY)
00686     {
00687       if((HAL_GetTick() - tickstart ) > Timeout)
00688       {
00689         /* Change state */
00690         hhash->State = HAL_HASH_STATE_TIMEOUT;
00691
00692         /* Process Unlocked */
00693         __HAL_UNLOCK(hhash);
00694
00695         return HAL_TIMEOUT;
00696       }
00697     }
00698   }
00699   /************************** STEP 3 ******************************************/
00700   /* Configure the number of valid bits in last word of the message */
00701   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00702
00703   /* Write input buffer in data register */
00704   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00705
00706   /* Start the digest calculation */
00707   __HAL_HASH_START_DIGEST();
00708
00709   /* Get tick */
00710   tickstart = HAL_GetTick();
00711
00712   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00713   {
00714     /* Check for the Timeout */
00715     if(Timeout != HAL_MAX_DELAY)
00716     {
00717       if((HAL_GetTick() - tickstart ) > Timeout)
00718       {
00719         /* Change state */
00720         hhash->State = HAL_HASH_STATE_TIMEOUT;
00721
00722         /* Process Unlocked */
00723         __HAL_UNLOCK(hhash);
00724
00725         return HAL_TIMEOUT;
00726       }
00727     }
00728   }
00729   /* Read the message digest */
00730   HASHEx_GetDigest(pOutBuffer, 28U);
00731
00732   /* Change the HASH state */
00733   hhash->State = HAL_HASH_STATE_READY;
00734
00735   /* Process Unlocked */
00736   __HAL_UNLOCK(hhash);
00737
00738   /* Return function status */
00739   return HAL_OK;
00740 }
00741
00742 /**
00743   * @brief  Initializes the HASH peripheral in HMAC SHA256 mode
00744   *         then processes pInBuffer. The digest is available in pOutBuffer
00745   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00746   *         the configuration information for HASH module
00747   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00748   * @param  Size: Length of the input buffer in bytes.
00749   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00750   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00751   * @param  Timeout: Timeout value
00752   * @retval HAL status
00753   */
00754 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
00755 {
00756   uint32_t tickstart = 0U;
00757
00758   /* Process Locked */
00759   __HAL_LOCK(hhash);
00760
00761   /* Change the HASH state */
00762   hhash->State = HAL_HASH_STATE_BUSY;
00763
00764   /* Check if initialization phase has already been performed */
00765   if(hhash->Phase == HAL_HASH_PHASE_READY)
00766   {
00767     /* Check if key size is greater than 64 bytes */
00768     if(hhash->Init.KeySize > 64U)
00769     {
00770       /* Select the HMAC SHA256 mode */
00771       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
00772     }
00773     else
00774     {
00775       /* Select the HMAC SHA256 mode */
00776       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
00777     }
00778     /* Reset the HASH processor core, so that the HASH will be ready to compute
00779        the message digest of a new message */
00780     HASH->CR |= HASH_CR_INIT;
00781   }
00782
00783   /* Set the phase */
00784   hhash->Phase = HAL_HASH_PHASE_PROCESS;
00785
00786   /************************** STEP 1 ******************************************/
00787   /* Configure the number of valid bits in last word of the message */
00788   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00789
00790   /* Write input buffer in data register */
00791   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00792
00793   /* Start the digest calculation */
00794   __HAL_HASH_START_DIGEST();
00795
00796   /* Get tick */
00797   tickstart = HAL_GetTick();
00798
00799   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00800   {
00801     /* Check for the Timeout */
00802     if(Timeout != HAL_MAX_DELAY)
00803     {
00804       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00805       {
00806         /* Change state */
00807         hhash->State = HAL_HASH_STATE_TIMEOUT;
00808
00809         /* Process Unlocked */
00810         __HAL_UNLOCK(hhash);
00811
00812         return HAL_TIMEOUT;
00813       }
00814     }
00815   }
00816   /************************** STEP 2 ******************************************/
00817   /* Configure the number of valid bits in last word of the message */
00818   __HAL_HASH_SET_NBVALIDBITS(Size);
00819
00820   /* Write input buffer in data register */
00821   HASHEx_WriteData(pInBuffer, Size);
00822
00823   /* Start the digest calculation */
00824   __HAL_HASH_START_DIGEST();
00825
00826   /* Get tick */
00827   tickstart = HAL_GetTick();
00828
00829   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00830   {
00831     /* Check for the Timeout */
00832     if(Timeout != HAL_MAX_DELAY)
00833     {
00834       if((HAL_GetTick() - tickstart ) > Timeout)
00835       {
00836         /* Change state */
00837         hhash->State = HAL_HASH_STATE_TIMEOUT;
00838
00839         /* Process Unlocked */
00840         __HAL_UNLOCK(hhash);
00841
00842         return HAL_TIMEOUT;
00843       }
00844     }
00845   }
00846   /************************** STEP 3 ******************************************/
00847   /* Configure the number of valid bits in last word of the message */
00848   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
00849
00850   /* Write input buffer in data register */
00851   HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
00852
00853   /* Start the digest calculation */
00854   __HAL_HASH_START_DIGEST();
00855
00856   /* Get tick */
00857   tickstart = HAL_GetTick();
00858
00859   while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
00860   {
00861     /* Check for the Timeout */
00862     if(Timeout != HAL_MAX_DELAY)
00863     {
00864       if((HAL_GetTick() - tickstart ) > Timeout)
00865       {
00866         /* Change state */
00867         hhash->State = HAL_HASH_STATE_TIMEOUT;
00868
00869         /* Process Unlocked */
00870         __HAL_UNLOCK(hhash);
00871
00872         return HAL_TIMEOUT;
00873       }
00874     }
00875   }
00876   /* Read the message digest */
00877   HASHEx_GetDigest(pOutBuffer, 32U);
00878
00879   /* Change the HASH state */
00880   hhash->State = HAL_HASH_STATE_READY;
00881
00882    /* Process Unlocked */
00883   __HAL_UNLOCK(hhash);
00884
00885   /* Return function status */
00886   return HAL_OK;
00887 }
00888
00889 /**
00890   * @}
00891   */
00892
00893 /** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
00894  *  @brief   processing functions using interrupt mode.
00895  *
00896 @verbatim
00897  ===============================================================================
00898               ##### HASH processing using interrupt functions #####
00899  ===============================================================================
00900     [..]  This section provides functions allowing to calculate in interrupt mode
00901           the hash value using one of the following algorithms:
00902       (+) SHA224
00903       (+) SHA256
00904
00905 @endverbatim
00906   * @{
00907   */
00908
00909 /**
00910   * @brief  Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
00911   *         The digest is available in pOutBuffer.
00912   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
00913   *         the configuration information for HASH module
00914   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
00915   * @param  Size: Length of the input buffer in bytes.
00916   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
00917   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
00918   * @retval HAL status
00919   */
00920 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
00921 {
00922   uint32_t inputaddr;
00923   uint32_t buffercounter;
00924   uint32_t inputcounter;
00925
00926   /* Process Locked */
00927   __HAL_LOCK(hhash);
00928
00929   if(hhash->State == HAL_HASH_STATE_READY)
00930   {
00931     /* Change the HASH state */
00932     hhash->State = HAL_HASH_STATE_BUSY;
00933
00934     hhash->HashInCount = Size;
00935     hhash->pHashInBuffPtr = pInBuffer;
00936     hhash->pHashOutBuffPtr = pOutBuffer;
00937
00938     /* Check if initialization phase has already been performed */
00939     if(hhash->Phase == HAL_HASH_PHASE_READY)
00940     {
00941       /* Select the SHA224 mode */
00942       HASH->CR |= HASH_ALGOSELECTION_SHA224;
00943       /* Reset the HASH processor core, so that the HASH will be ready to compute
00944          the message digest of a new message */
00945       HASH->CR |= HASH_CR_INIT;
00946     }
00947     /* Reset interrupt counter */
00948     hhash->HashITCounter = 0U;
00949
00950     /* Set the phase */
00951     hhash->Phase = HAL_HASH_PHASE_PROCESS;
00952
00953     /* Process Unlocked */
00954     __HAL_UNLOCK(hhash);
00955
00956     /* Enable Interrupts */
00957     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
00958
00959     /* Return function status */
00960     return HAL_OK;
00961   }
00962   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
00963   {
00964     /* Read the message digest */
00965     HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28U);
00966     if(hhash->HashInCount == 0U)
00967     {
00968       /* Disable Interrupts */
00969       HASH->IMR = 0U;
00970       /* Change the HASH state */
00971       hhash->State = HAL_HASH_STATE_READY;
00972       /* Call digest computation complete callback */
00973       HAL_HASH_DgstCpltCallback(hhash);
00974
00975       /* Process Unlocked */
00976       __HAL_UNLOCK(hhash);
00977
00978       /* Return function status */
00979       return HAL_OK;
00980     }
00981   }
00982   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
00983   {
00984     if(hhash->HashInCount >= 68U)
00985     {
00986       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
00987       /* Write the Input block in the Data IN register */
00988       for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
00989       {
00990         HASH->DIN = *(uint32_t*)inputaddr;
00991         inputaddr+=4U;
00992       }
00993       if(hhash->HashITCounter == 0U)
00994       {
00995         HASH->DIN = *(uint32_t*)inputaddr;
00996
00997         if(hhash->HashInCount >= 68U)
00998         {
00999           /* Decrement buffer counter */
01000           hhash->HashInCount -= 68U;
01001           hhash->pHashInBuffPtr+= 68U;
01002         }
01003         else
01004         {
01005           hhash->HashInCount = 0U;
01006           hhash->pHashInBuffPtr+= hhash->HashInCount;
01007         }
01008         /* Set Interrupt counter */
01009         hhash->HashITCounter = 1U;
01010       }
01011       else
01012       {
01013         /* Decrement buffer counter */
01014         hhash->HashInCount -= 64U;
01015         hhash->pHashInBuffPtr+= 64U;
01016       }
01017     }
01018     else
01019     {
01020       /* Get the buffer address */
01021       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01022       /* Get the buffer counter */
01023       inputcounter = hhash->HashInCount;
01024       /* Disable Interrupts */
01025       HASH->IMR &= ~(HASH_IT_DINI);
01026       /* Configure the number of valid bits in last word of the message */
01027       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
01028
01029       if((inputcounter > 4U) && (inputcounter%4U))
01030       {
01031         inputcounter = (inputcounter+4U-inputcounter%4U);
01032       }
01033       else if ((inputcounter < 4U) && (inputcounter != 0U))
01034       {
01035         inputcounter = 4U;
01036       }
01037       /* Write the Input block in the Data IN register */
01038       for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
01039       {
01040         HASH->DIN = *(uint32_t*)inputaddr;
01041         inputaddr+=4U;
01042       }
01043       /* Start the digest calculation */
01044       __HAL_HASH_START_DIGEST();
01045       /* Reset buffer counter */
01046       hhash->HashInCount = 0U;
01047       /* Call Input data transfer complete callback */
01048       HAL_HASH_InCpltCallback(hhash);
01049     }
01050   }
01051
01052   /* Process Unlocked */
01053   __HAL_UNLOCK(hhash);
01054
01055   /* Return function status */
01056   return HAL_OK;
01057 }
01058
01059
01060 /**
01061   * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
01062   *         The digest is available in pOutBuffer.
01063   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01064   *         the configuration information for HASH module
01065   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01066   * @param  Size: Length of the input buffer in bytes.
01067   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01068   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
01069   * @retval HAL status
01070   */
01071 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
01072 {
01073   uint32_t inputaddr;
01074   uint32_t buffercounter;
01075   uint32_t inputcounter;
01076
01077   /* Process Locked */
01078   __HAL_LOCK(hhash);
01079
01080   if(hhash->State == HAL_HASH_STATE_READY)
01081   {
01082     /* Change the HASH state */
01083     hhash->State = HAL_HASH_STATE_BUSY;
01084
01085     hhash->HashInCount = Size;
01086     hhash->pHashInBuffPtr = pInBuffer;
01087     hhash->pHashOutBuffPtr = pOutBuffer;
01088
01089     /* Check if initialization phase has already been performed */
01090     if(hhash->Phase == HAL_HASH_PHASE_READY)
01091     {
01092       /* Select the SHA256 mode */
01093       HASH->CR |= HASH_ALGOSELECTION_SHA256;
01094       /* Reset the HASH processor core, so that the HASH will be ready to compute
01095          the message digest of a new message */
01096       HASH->CR |= HASH_CR_INIT;
01097     }
01098     /* Reset interrupt counter */
01099     hhash->HashITCounter = 0U;
01100
01101     /* Set the phase */
01102     hhash->Phase = HAL_HASH_PHASE_PROCESS;
01103
01104     /* Process Unlocked */
01105     __HAL_UNLOCK(hhash);
01106
01107     /* Enable Interrupts */
01108     HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
01109
01110     /* Return function status */
01111     return HAL_OK;
01112   }
01113   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
01114   {
01115     /* Read the message digest */
01116     HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32U);
01117     if(hhash->HashInCount == 0U)
01118     {
01119       /* Disable Interrupts */
01120       HASH->IMR = 0U;
01121       /* Change the HASH state */
01122       hhash->State = HAL_HASH_STATE_READY;
01123       /* Call digest computation complete callback */
01124       HAL_HASH_DgstCpltCallback(hhash);
01125
01126       /* Process Unlocked */
01127       __HAL_UNLOCK(hhash);
01128
01129       /* Return function status */
01130       return HAL_OK;
01131     }
01132   }
01133   if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
01134   {
01135     if(hhash->HashInCount >= 68U)
01136     {
01137       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01138       /* Write the Input block in the Data IN register */
01139       for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
01140       {
01141         HASH->DIN = *(uint32_t*)inputaddr;
01142         inputaddr+=4U;
01143       }
01144       if(hhash->HashITCounter == 0U)
01145       {
01146         HASH->DIN = *(uint32_t*)inputaddr;
01147
01148         if(hhash->HashInCount >= 68U)
01149         {
01150           /* Decrement buffer counter */
01151           hhash->HashInCount -= 68U;
01152           hhash->pHashInBuffPtr+= 68U;
01153         }
01154         else
01155         {
01156           hhash->HashInCount = 0U;
01157           hhash->pHashInBuffPtr+= hhash->HashInCount;
01158         }
01159         /* Set Interrupt counter */
01160         hhash->HashITCounter = 1U;
01161       }
01162       else
01163       {
01164         /* Decrement buffer counter */
01165         hhash->HashInCount -= 64U;
01166         hhash->pHashInBuffPtr+= 64U;
01167       }
01168     }
01169     else
01170     {
01171       /* Get the buffer address */
01172       inputaddr = (uint32_t)hhash->pHashInBuffPtr;
01173       /* Get the buffer counter */
01174       inputcounter = hhash->HashInCount;
01175       /* Disable Interrupts */
01176       HASH->IMR &= ~(HASH_IT_DINI);
01177       /* Configure the number of valid bits in last word of the message */
01178       __HAL_HASH_SET_NBVALIDBITS(inputcounter);
01179
01180       if((inputcounter > 4U) && (inputcounter%4U))
01181       {
01182         inputcounter = (inputcounter+4U-inputcounter%4U);
01183       }
01184       else if ((inputcounter < 4U) && (inputcounter != 0U))
01185       {
01186         inputcounter = 4U;
01187       }
01188       /* Write the Input block in the Data IN register */
01189       for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
01190       {
01191         HASH->DIN = *(uint32_t*)inputaddr;
01192         inputaddr+=4U;
01193       }
01194       /* Start the digest calculation */
01195       __HAL_HASH_START_DIGEST();
01196       /* Reset buffer counter */
01197       hhash->HashInCount = 0U;
01198       /* Call Input data transfer complete callback */
01199       HAL_HASH_InCpltCallback(hhash);
01200     }
01201   }
01202
01203   /* Process Unlocked */
01204   __HAL_UNLOCK(hhash);
01205
01206   /* Return function status */
01207   return HAL_OK;
01208 }
01209
01210 /**
01211   * @brief This function handles HASH interrupt request.
01212   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01213   *         the configuration information for HASH module
01214   * @retval None
01215   */
01216 void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
01217 {
01218   switch(HASH->CR & HASH_CR_ALGO)
01219   {
01220
01221     case HASH_ALGOSELECTION_SHA224:
01222        HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0U, NULL);
01223     break;
01224
01225     case HASH_ALGOSELECTION_SHA256:
01226       HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0U, NULL);
01227     break;
01228
01229     default:
01230     break;
01231   }
01232 }
01233
01234 /**
01235   * @}
01236   */
01237
01238 /** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
01239  *  @brief   processing functions using DMA mode.
01240  *
01241 @verbatim
01242  ===============================================================================
01243                 ##### HASH processing using DMA functions #####
01244  ===============================================================================
01245     [..]  This section provides functions allowing to calculate in DMA mode
01246           the hash value using one of the following algorithms:
01247       (+) SHA224
01248       (+) SHA256
01249
01250 @endverbatim
01251   * @{
01252   */
01253
01254
01255 /**
01256   * @brief  Initializes the HASH peripheral in SHA224 mode then enables DMA to
01257             control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
01258   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01259   *         the configuration information for HASH module
01260   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01261   * @param  Size: Length of the input buffer in bytes.
01262   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01263   * @retval HAL status
01264   */
01265 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01266 {
01267   uint32_t inputaddr  = (uint32_t)pInBuffer;
01268
01269    /* Process Locked */
01270   __HAL_LOCK(hhash);
01271
01272   /* Change the HASH state */
01273   hhash->State = HAL_HASH_STATE_BUSY;
01274
01275   /* Check if initialization phase has already been performed */
01276   if(hhash->Phase == HAL_HASH_PHASE_READY)
01277   {
01278     /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
01279        the message digest of a new message */
01280     HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
01281   }
01282
01283   /* Configure the number of valid bits in last word of the message */
01284   __HAL_HASH_SET_NBVALIDBITS(Size);
01285
01286   /* Set the phase */
01287   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01288
01289   /* Set the HASH DMA transfer complete callback */
01290   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01291   /* Set the DMA error callback */
01292   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01293
01294   /* Enable the DMA In DMA Stream */
01295   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
01296
01297   /* Enable DMA requests */
01298   HASH->CR |= (HASH_CR_DMAE);
01299
01300    /* Process Unlocked */
01301   __HAL_UNLOCK(hhash);
01302
01303   /* Return function status */
01304   return HAL_OK;
01305 }
01306
01307 /**
01308   * @brief  Returns the computed digest in SHA224
01309   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01310   *         the configuration information for HASH module
01311   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
01312   * @param  Timeout: Timeout value
01313   * @retval HAL status
01314   */
01315 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01316 {
01317   uint32_t tickstart = 0U;
01318
01319   /* Process Locked */
01320   __HAL_LOCK(hhash);
01321
01322   /* Change HASH peripheral state */
01323   hhash->State = HAL_HASH_STATE_BUSY;
01324
01325   /* Get tick */
01326   tickstart = HAL_GetTick();
01327
01328   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01329   {
01330     /* Check for the Timeout */
01331     if(Timeout != HAL_MAX_DELAY)
01332     {
01333       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01334       {
01335         /* Change state */
01336         hhash->State = HAL_HASH_STATE_TIMEOUT;
01337
01338         /* Process Unlocked */
01339         __HAL_UNLOCK(hhash);
01340
01341         return HAL_TIMEOUT;
01342       }
01343     }
01344   }
01345
01346   /* Read the message digest */
01347   HASHEx_GetDigest(pOutBuffer, 28U);
01348
01349   /* Change HASH peripheral state */
01350   hhash->State = HAL_HASH_STATE_READY;
01351
01352    /* Process Unlocked */
01353   __HAL_UNLOCK(hhash);
01354
01355   /* Return function status */
01356   return HAL_OK;
01357 }
01358
01359 /**
01360   * @brief  Initializes the HASH peripheral in SHA256 mode then enables DMA to
01361             control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
01362   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01363   *         the configuration information for HASH module
01364   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01365   * @param  Size: Length of the input buffer in bytes.
01366   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01367   * @retval HAL status
01368   */
01369 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01370 {
01371   uint32_t inputaddr  = (uint32_t)pInBuffer;
01372
01373    /* Process Locked */
01374   __HAL_LOCK(hhash);
01375
01376   /* Change the HASH state */
01377   hhash->State = HAL_HASH_STATE_BUSY;
01378
01379   /* Check if initialization phase has already been performed */
01380   if(hhash->Phase == HAL_HASH_PHASE_READY)
01381   {
01382     /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
01383        the message digest of a new message */
01384     HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
01385   }
01386
01387   /* Configure the number of valid bits in last word of the message */
01388   __HAL_HASH_SET_NBVALIDBITS(Size);
01389
01390   /* Set the phase */
01391   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01392
01393   /* Set the HASH DMA transfer complete callback */
01394   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01395   /* Set the DMA error callback */
01396   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01397
01398   /* Enable the DMA In DMA Stream */
01399   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
01400
01401   /* Enable DMA requests */
01402   HASH->CR |= (HASH_CR_DMAE);
01403
01404    /* Process UnLock */
01405   __HAL_UNLOCK(hhash);
01406
01407   /* Return function status */
01408   return HAL_OK;
01409 }
01410
01411 /**
01412   * @brief  Returns the computed digest in SHA256.
01413   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01414   *         the configuration information for HASH module
01415   * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
01416   * @param  Timeout: Timeout value
01417   * @retval HAL status
01418   */
01419 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
01420 {
01421   uint32_t tickstart = 0U;
01422
01423    /* Process Locked */
01424   __HAL_LOCK(hhash);
01425
01426   /* Change HASH peripheral state */
01427   hhash->State = HAL_HASH_STATE_BUSY;
01428
01429   /* Get tick */
01430   tickstart = HAL_GetTick();
01431
01432   while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
01433   {
01434     /* Check for the Timeout */
01435     if(Timeout != HAL_MAX_DELAY)
01436     {
01437       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01438       {
01439         /* Change state */
01440         hhash->State = HAL_HASH_STATE_TIMEOUT;
01441
01442         /* Process Unlocked */
01443         __HAL_UNLOCK(hhash);
01444
01445         return HAL_TIMEOUT;
01446       }
01447     }
01448   }
01449
01450   /* Read the message digest */
01451   HASHEx_GetDigest(pOutBuffer, 32U);
01452
01453   /* Change HASH peripheral state */
01454   hhash->State = HAL_HASH_STATE_READY;
01455
01456    /* Process Unlocked */
01457   __HAL_UNLOCK(hhash);
01458
01459   /* Return function status */
01460   return HAL_OK;
01461 }
01462
01463
01464 /**
01465   * @}
01466   */
01467 /** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
01468  *  @brief   HMAC processing functions using DMA mode .
01469  *
01470 @verbatim
01471  ===============================================================================
01472                 ##### HMAC processing using DMA functions #####
01473  ===============================================================================
01474     [..]  This section provides functions allowing to calculate in DMA mode
01475           the HMAC value using one of the following algorithms:
01476       (+) SHA224
01477       (+) SHA256
01478
01479 @endverbatim
01480   * @{
01481   */
01482
01483 /**
01484   * @brief  Initializes the HASH peripheral in HMAC SHA224 mode
01485   *         then enables DMA to control data transfer.
01486   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01487   *         the configuration information for HASH module
01488   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01489   * @param  Size: Length of the input buffer in bytes.
01490   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01491   * @retval HAL status
01492   */
01493 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01494 {
01495   uint32_t inputaddr;
01496
01497   /* Process Locked */
01498   __HAL_LOCK(hhash);
01499
01500   /* Change the HASH state */
01501   hhash->State = HAL_HASH_STATE_BUSY;
01502
01503   /* Save buffer pointer and size in handle */
01504   hhash->pHashInBuffPtr = pInBuffer;
01505   hhash->HashBuffSize = Size;
01506   hhash->HashInCount = 0U;
01507
01508   /* Check if initialization phase has already been performed */
01509   if(hhash->Phase == HAL_HASH_PHASE_READY)
01510   {
01511     /* Check if key size is greater than 64 bytes */
01512     if(hhash->Init.KeySize > 64U)
01513     {
01514       /* Select the HMAC SHA224 mode */
01515       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
01516     }
01517     else
01518     {
01519       /* Select the HMAC SHA224 mode */
01520       HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
01521     }
01522   }
01523
01524   /* Set the phase */
01525   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01526
01527   /* Configure the number of valid bits in last word of the message */
01528   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01529
01530   /* Get the key address */
01531   inputaddr = (uint32_t)(hhash->Init.pKey);
01532
01533   /* Set the HASH DMA transfer complete callback */
01534   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01535   /* Set the DMA error callback */
01536   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01537
01538   /* Enable the DMA In DMA Stream */
01539   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
01540   /* Enable DMA requests */
01541   HASH->CR |= (HASH_CR_DMAE);
01542
01543   /* Process Unlocked */
01544   __HAL_UNLOCK(hhash);
01545
01546   /* Return function status */
01547   return HAL_OK;
01548 }
01549
01550 /**
01551   * @brief  Initializes the HASH peripheral in HMAC SHA256 mode
01552   *         then enables DMA to control data transfer.
01553   * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
01554   *         the configuration information for HASH module
01555   * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
01556   * @param  Size: Length of the input buffer in bytes.
01557   *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
01558   * @retval HAL status
01559   */
01560 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
01561 {
01562   uint32_t inputaddr;
01563
01564   /* Process Locked */
01565   __HAL_LOCK(hhash);
01566
01567   /* Change the HASH state */
01568   hhash->State = HAL_HASH_STATE_BUSY;
01569
01570   /* Save buffer pointer and size in handle */
01571   hhash->pHashInBuffPtr = pInBuffer;
01572   hhash->HashBuffSize = Size;
01573   hhash->HashInCount = 0U;
01574
01575   /* Check if initialization phase has already been performed */
01576   if(hhash->Phase == HAL_HASH_PHASE_READY)
01577   {
01578     /* Check if key size is greater than 64 bytes */
01579     if(hhash->Init.KeySize > 64U)
01580     {
01581       /* Select the HMAC SHA256 mode */
01582       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
01583     }
01584     else
01585     {
01586       /* Select the HMAC SHA256 mode */
01587       HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
01588     }
01589     /* Reset the HASH processor core, so that the HASH will be ready to compute
01590        the message digest of a new message */
01591     HASH->CR |= HASH_CR_INIT;
01592   }
01593
01594   /* Set the phase */
01595   hhash->Phase = HAL_HASH_PHASE_PROCESS;
01596
01597   /* Configure the number of valid bits in last word of the message */
01598   __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
01599
01600   /* Get the key address */
01601   inputaddr = (uint32_t)(hhash->Init.pKey);
01602
01603   /* Set the HASH DMA transfer complete callback */
01604   hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
01605   /* Set the DMA error callback */
01606   hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
01607
01608   /* Enable the DMA In DMA Stream */
01609   HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
01610   /* Enable DMA requests */
01611   HASH->CR |= (HASH_CR_DMAE);
01612
01613   /* Process Unlocked */
01614   __HAL_UNLOCK(hhash);
01615
01616   /* Return function status */
01617   return HAL_OK;
01618 }
01619
01620 /**
01621   * @}
01622   */
01623
01624 /**
01625   * @}
01626   */
01627 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
01628
01629 #endif /* HAL_HASH_MODULE_ENABLED */
01630 /**
01631   * @}
01632   */
01633
01634 /**
01635   * @}
01636   */
01637
01638 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hash_ex.h Source File

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stm32f4xx_hal_hash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_hash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of HASH HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_HASH_EX_H
00040 #define __STM32F4xx_HAL_HASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HASHEx
00055   * @brief HASHEx HAL Extension module driver
00056   *  @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /* Exported constants --------------------------------------------------------*/
00061 /* Exported macro ------------------------------------------------------------*/
00062 /* Exported functions --------------------------------------------------------*/
00063
00064 /** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions
00065   * @{
00066   */
00067
00068 /** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions
00069   * @{
00070   */
00071
00072 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00073 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00074 HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00075 HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions
00082   * @{
00083   */
00084
00085 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00086 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
00087
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using  functions
00093   * @{
00094   */
00095
00096 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00097 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
00098
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA
00104   * @{
00105   */
00106
00107 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00108 HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00109 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00110 HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
00111
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA
00117   * @{
00118   */
00119
00120 HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00121 HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
00122 /**
00123   * @}
00124   */
00125
00126 /** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions
00127   * @{
00128   */
00129
00130 void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
00131
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140  /* Private types -------------------------------------------------------------*/
00141 /** @defgroup HASHEx_Private_Types HASHEx Private Types
00142   * @{
00143   */
00144
00145 /**
00146   * @}
00147   */
00148
00149 /* Private variables ---------------------------------------------------------*/
00150 /** @defgroup HASHEx_Private_Variables HASHEx Private Variables
00151   * @{
00152   */
00153
00154 /**
00155   * @}
00156   */
00157
00158 /* Private constants ---------------------------------------------------------*/
00159 /** @defgroup HASHEx_Private_Constants HASHEx Private Constants
00160   * @{
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Private macros ------------------------------------------------------------*/
00168 /** @defgroup HASHEx_Private_Macros HASHEx Private Macros
00169   * @{
00170   */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Private functions ---------------------------------------------------------*/
00177 /** @defgroup HASHEx_Private_Functions HASHEx Private Functions
00178   * @{
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @}
00192   */
00193
00194 #ifdef __cplusplus
00195 }
00196 #endif
00197
00198 #endif /* __STM32F4xx_HAL_HASH_EX_H */
00199
00200 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hcd.c Source File

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stm32f4xx_hal_hcd.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_hcd.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   HCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     (#)Declare a HCD_HandleTypeDef handle structure, for example:
00021        HCD_HandleTypeDef  hhcd;
00022
00023     (#)Fill parameters of Init structure in HCD handle
00024
00025     (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
00026
00027     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
00028         (##) Enable the HCD/USB Low Level interface clock using the following macros
00029              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
00030              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
00031              (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
00032
00033         (##) Initialize the related GPIO clocks
00034         (##) Configure HCD pin-out
00035         (##) Configure HCD NVIC interrupt
00036
00037     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
00038         (##) hhcd.pData = phost;
00039
00040     (#)Enable HCD transmission and reception:
00041         (##) HAL_HCD_Start();
00042
00043   @endverbatim
00044   ******************************************************************************
00045   * @attention
00046   *
00047   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00048   *
00049   * Redistribution and use in source and binary forms, with or without modification,
00050   * are permitted provided that the following conditions are met:
00051   *   1. Redistributions of source code must retain the above copyright notice,
00052   *      this list of conditions and the following disclaimer.
00053   *   2. Redistributions in binary form must reproduce the above copyright notice,
00054   *      this list of conditions and the following disclaimer in the documentation
00055   *      and/or other materials provided with the distribution.
00056   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00057   *      may be used to endorse or promote products derived from this software
00058   *      without specific prior written permission.
00059   *
00060   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00061   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00062   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00063   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00064   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00065   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00066   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00067   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00068   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00069   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00070   *
00071   ******************************************************************************
00072   */
00073
00074 /* Includes ------------------------------------------------------------------*/
00075 #include "stm32f4xx_hal.h"
00076
00077 /** @addtogroup STM32F4xx_HAL_Driver
00078   * @{
00079   */
00080
00081 /** @defgroup HCD HCD
00082   * @brief HCD HAL module driver
00083   * @{
00084   */
00085
00086 #ifdef HAL_HCD_MODULE_ENABLED
00087 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00088     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00089     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00090     defined(STM32F469xx) || defined(STM32F479xx)
00091 /* Private typedef -----------------------------------------------------------*/
00092 /* Private define ------------------------------------------------------------*/
00093 /* Private macro -------------------------------------------------------------*/
00094 /* Private variables ---------------------------------------------------------*/
00095 /* Private function prototypes -----------------------------------------------*/
00096 /** @defgroup HCD_Private_Functions HCD Private Functions
00097   * @{
00098   */
00099 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00100 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00101 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
00102 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
00103 /**
00104   * @}
00105   */
00106
00107 /* Exported functions --------------------------------------------------------*/
00108 /** @defgroup HCD_Exported_Functions HCD Exported Functions
00109   * @{
00110   */
00111
00112 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00113  *  @brief    Initialization and Configuration functions
00114  *
00115 @verbatim
00116  ===============================================================================
00117           ##### Initialization and de-initialization functions #####
00118  ===============================================================================
00119     [..]  This section provides functions allowing to:
00120
00121 @endverbatim
00122   * @{
00123   */
00124
00125 /**
00126   * @brief  Initialize the host driver.
00127   * @param  hhcd: HCD handle
00128   * @retval HAL status
00129   */
00130 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
00131 {
00132   /* Check the HCD handle allocation */
00133   if(hhcd == NULL)
00134   {
00135     return HAL_ERROR;
00136   }
00137
00138   /* Check the parameters */
00139   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
00140
00141   hhcd->State = HAL_HCD_STATE_BUSY;
00142
00143   /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00144   HAL_HCD_MspInit(hhcd);
00145
00146   /* Disable the Interrupts */
00147   __HAL_HCD_DISABLE(hhcd);
00148
00149   /* Init the Core (common init.) */
00150   USB_CoreInit(hhcd->Instance, hhcd->Init);
00151
00152   /* Force Host Mode*/
00153   USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
00154
00155   /* Init Host */
00156   USB_HostInit(hhcd->Instance, hhcd->Init);
00157
00158   hhcd->State= HAL_HCD_STATE_READY;
00159
00160   return HAL_OK;
00161 }
00162
00163 /**
00164   * @brief  Initialize a host channel.
00165   * @param  hhcd: HCD handle
00166   * @param  ch_num: Channel number.
00167   *         This parameter can be a value from 1 to 15
00168   * @param  epnum: Endpoint number.
00169   *          This parameter can be a value from 1 to 15
00170   * @param  dev_address : Current device address
00171   *          This parameter can be a value from 0 to 255
00172   * @param  speed: Current device speed.
00173   *          This parameter can be one of these values:
00174   *            HCD_SPEED_HIGH: High speed mode,
00175   *            HCD_SPEED_FULL: Full speed mode,
00176   *            HCD_SPEED_LOW: Low speed mode
00177   * @param  ep_type: Endpoint Type.
00178   *          This parameter can be one of these values:
00179   *            EP_TYPE_CTRL: Control type,
00180   *            EP_TYPE_ISOC: Isochronous type,
00181   *            EP_TYPE_BULK: Bulk type,
00182   *            EP_TYPE_INTR: Interrupt type
00183   * @param  mps: Max Packet Size.
00184   *          This parameter can be a value from 0 to32K
00185   * @retval HAL status
00186   */
00187 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00188                                   uint8_t ch_num,
00189                                   uint8_t epnum,
00190                                   uint8_t dev_address,
00191                                   uint8_t speed,
00192                                   uint8_t ep_type,
00193                                   uint16_t mps)
00194 {
00195   HAL_StatusTypeDef status = HAL_OK;
00196
00197   __HAL_LOCK(hhcd);
00198
00199   hhcd->hc[ch_num].dev_addr = dev_address;
00200   hhcd->hc[ch_num].max_packet = mps;
00201   hhcd->hc[ch_num].ch_num = ch_num;
00202   hhcd->hc[ch_num].ep_type = ep_type;
00203   hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
00204   hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U);
00205   hhcd->hc[ch_num].speed = speed;
00206
00207   status =  USB_HC_Init(hhcd->Instance,
00208                         ch_num,
00209                         epnum,
00210                         dev_address,
00211                         speed,
00212                         ep_type,
00213                         mps);
00214   __HAL_UNLOCK(hhcd);
00215
00216   return status;
00217 }
00218
00219 /**
00220   * @brief  Halt a host channel.
00221   * @param  hhcd: HCD handle
00222   * @param  ch_num: Channel number.
00223   *         This parameter can be a value from 1 to 15
00224   * @retval HAL status
00225   */
00226 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
00227 {
00228   HAL_StatusTypeDef status = HAL_OK;
00229
00230   __HAL_LOCK(hhcd);
00231   USB_HC_Halt(hhcd->Instance, ch_num);
00232   __HAL_UNLOCK(hhcd);
00233
00234   return status;
00235 }
00236
00237 /**
00238   * @brief  DeInitialize the host driver.
00239   * @param  hhcd: HCD handle
00240   * @retval HAL status
00241   */
00242 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
00243 {
00244   /* Check the HCD handle allocation */
00245   if(hhcd == NULL)
00246   {
00247     return HAL_ERROR;
00248   }
00249
00250   hhcd->State = HAL_HCD_STATE_BUSY;
00251
00252   /* DeInit the low level hardware */
00253   HAL_HCD_MspDeInit(hhcd);
00254
00255   __HAL_HCD_DISABLE(hhcd);
00256
00257   hhcd->State = HAL_HCD_STATE_RESET;
00258
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @brief  Initialize the HCD MSP.
00264   * @param  hhcd: HCD handle
00265   * @retval None
00266   */
00267 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
00268 {
00269   /* Prevent unused argument(s) compilation warning */
00270   UNUSED(hhcd);
00271   /* NOTE : This function Should not be modified, when the callback is needed,
00272             the HAL_PCD_MspInit could be implemented in the user file
00273    */
00274 }
00275
00276 /**
00277   * @brief  DeInitialize the HCD MSP.
00278   * @param  hhcd: HCD handle
00279   * @retval None
00280   */
00281 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
00282 {
00283   /* Prevent unused argument(s) compilation warning */
00284   UNUSED(hhcd);
00285   /* NOTE : This function Should not be modified, when the callback is needed,
00286             the HAL_PCD_MspDeInit could be implemented in the user file
00287    */
00288 }
00289
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
00295   *  @brief   HCD IO operation functions
00296   *
00297 @verbatim
00298  ===============================================================================
00299                       ##### IO operation functions #####
00300  ===============================================================================
00301  [..] This subsection provides a set of functions allowing to manage the USB Host Data
00302     Transfer
00303
00304 @endverbatim
00305   * @{
00306   */
00307
00308 /**
00309   * @brief  Submit a new URB for processing.
00310   * @param  hhcd: HCD handle
00311   * @param  ch_num: Channel number.
00312   *         This parameter can be a value from 1 to 15
00313   * @param  direction: Channel number.
00314   *          This parameter can be one of these values:
00315   *           0 : Output / 1 : Input
00316   * @param  ep_type: Endpoint Type.
00317   *          This parameter can be one of these values:
00318   *            EP_TYPE_CTRL: Control type/
00319   *            EP_TYPE_ISOC: Isochronous type/
00320   *            EP_TYPE_BULK: Bulk type/
00321   *            EP_TYPE_INTR: Interrupt type/
00322   * @param  token: Endpoint Type.
00323   *          This parameter can be one of these values:
00324   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
00325   * @param  pbuff: pointer to URB data
00326   * @param  length: Length of URB data
00327   * @param  do_ping: activate do ping protocol (for high speed only).
00328   *          This parameter can be one of these values:
00329   *           0 : do ping inactive / 1 : do ping active
00330   * @retval HAL status
00331   */
00332 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00333                                            uint8_t ch_num,
00334                                            uint8_t direction,
00335                                            uint8_t ep_type,
00336                                            uint8_t token,
00337                                            uint8_t* pbuff,
00338                                            uint16_t length,
00339                                            uint8_t do_ping)
00340 {
00341   hhcd->hc[ch_num].ep_is_in = direction;
00342   hhcd->hc[ch_num].ep_type  = ep_type;
00343
00344   if(token == 0U)
00345   {
00346     hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
00347   }
00348   else
00349   {
00350     hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00351   }
00352
00353   /* Manage Data Toggle */
00354   switch(ep_type)
00355   {
00356   case EP_TYPE_CTRL:
00357     if((token == 1U) && (direction == 0U)) /*send data */
00358     {
00359       if (length == 0U)
00360       { /* For Status OUT stage, Length==0, Status Out PID = 1 */
00361         hhcd->hc[ch_num].toggle_out = 1U;
00362       }
00363
00364       /* Set the Data Toggle bit as per the Flag */
00365       if (hhcd->hc[ch_num].toggle_out == 0U)
00366       { /* Put the PID 0 */
00367         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00368       }
00369       else
00370       { /* Put the PID 1 */
00371         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00372       }
00373       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00374       {
00375         hhcd->hc[ch_num].do_ping = do_ping;
00376       }
00377     }
00378     break;
00379
00380   case EP_TYPE_BULK:
00381     if(direction == 0U)
00382     {
00383       /* Set the Data Toggle bit as per the Flag */
00384       if ( hhcd->hc[ch_num].toggle_out == 0U)
00385       { /* Put the PID 0 */
00386         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00387       }
00388       else
00389       { /* Put the PID 1 */
00390         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00391       }
00392       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00393       {
00394         hhcd->hc[ch_num].do_ping = do_ping;
00395       }
00396     }
00397     else
00398     {
00399       if( hhcd->hc[ch_num].toggle_in == 0U)
00400       {
00401         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00402       }
00403       else
00404       {
00405         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00406       }
00407     }
00408
00409     break;
00410   case EP_TYPE_INTR:
00411     if(direction == 0U)
00412     {
00413       /* Set the Data Toggle bit as per the Flag */
00414       if ( hhcd->hc[ch_num].toggle_out == 0U)
00415       { /* Put the PID 0 */
00416         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00417       }
00418       else
00419       { /* Put the PID 1 */
00420         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00421       }
00422     }
00423     else
00424     {
00425       if( hhcd->hc[ch_num].toggle_in == 0U)
00426       {
00427         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00428       }
00429       else
00430       {
00431         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00432       }
00433     }
00434     break;
00435
00436   case EP_TYPE_ISOC:
00437     hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00438     break;
00439   }
00440
00441   hhcd->hc[ch_num].xfer_buff = pbuff;
00442   hhcd->hc[ch_num].xfer_len  = length;
00443   hhcd->hc[ch_num].urb_state = URB_IDLE;
00444   hhcd->hc[ch_num].xfer_count = 0U;
00445   hhcd->hc[ch_num].ch_num = ch_num;
00446   hhcd->hc[ch_num].state = HC_IDLE;
00447
00448   return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
00449 }
00450
00451 /**
00452   * @brief  Handle HCD interrupt request.
00453   * @param  hhcd: HCD handle
00454   * @retval None
00455   */
00456 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
00457 {
00458   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00459   uint32_t i = 0U , interrupt = 0U;
00460
00461   /* Ensure that we are in device mode */
00462   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
00463   {
00464     /* Avoid spurious interrupt */
00465     if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
00466     {
00467       return;
00468     }
00469
00470     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00471     {
00472       /* Incorrect mode, acknowledge the interrupt */
00473       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00474     }
00475
00476     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
00477     {
00478       /* Incorrect mode, acknowledge the interrupt */
00479       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
00480     }
00481
00482     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
00483     {
00484       /* Incorrect mode, acknowledge the interrupt */
00485       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
00486     }
00487
00488     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
00489     {
00490       /* Incorrect mode, acknowledge the interrupt */
00491       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
00492     }
00493
00494     /* Handle Host Disconnect Interrupts */
00495     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
00496     {
00497
00498       /* Cleanup HPRT */
00499       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
00500         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
00501
00502       /* Handle Host Port Interrupts */
00503       HAL_HCD_Disconnect_Callback(hhcd);
00504       USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
00505       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
00506     }
00507
00508     /* Handle Host Port Interrupts */
00509     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
00510     {
00511       HCD_Port_IRQHandler (hhcd);
00512     }
00513
00514     /* Handle Host SOF Interrupts */
00515     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
00516     {
00517       HAL_HCD_SOF_Callback(hhcd);
00518       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
00519     }
00520
00521     /* Handle Host channel Interrupts */
00522     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
00523     {
00524       interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
00525       for (i = 0U; i < hhcd->Init.Host_channels; i++)
00526       {
00527         if (interrupt & (1U << i))
00528         {
00529           if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
00530           {
00531             HCD_HC_IN_IRQHandler(hhcd, i);
00532           }
00533           else
00534           {
00535             HCD_HC_OUT_IRQHandler (hhcd, i);
00536           }
00537         }
00538       }
00539       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
00540     }
00541
00542     /* Handle Rx Queue Level Interrupts */
00543     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
00544     {
00545       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00546
00547       HCD_RXQLVL_IRQHandler (hhcd);
00548
00549       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00550     }
00551   }
00552 }
00553
00554 /**
00555   * @brief  SOF callback.
00556   * @param  hhcd: HCD handle
00557   * @retval None
00558   */
00559 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
00560 {
00561   /* Prevent unused argument(s) compilation warning */
00562   UNUSED(hhcd);
00563   /* NOTE : This function Should not be modified, when the callback is needed,
00564             the HAL_HCD_SOF_Callback could be implemented in the user file
00565    */
00566 }
00567
00568 /**
00569   * @brief Connection Event callback.
00570   * @param  hhcd: HCD handle
00571   * @retval None
00572   */
00573 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
00574 {
00575   /* Prevent unused argument(s) compilation warning */
00576   UNUSED(hhcd);
00577   /* NOTE : This function Should not be modified, when the callback is needed,
00578             the HAL_HCD_Connect_Callback could be implemented in the user file
00579    */
00580 }
00581
00582 /**
00583   * @brief  Disconnection Event callback.
00584   * @param  hhcd: HCD handle
00585   * @retval None
00586   */
00587 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
00588 {
00589   /* Prevent unused argument(s) compilation warning */
00590   UNUSED(hhcd);
00591   /* NOTE : This function Should not be modified, when the callback is needed,
00592             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00593    */
00594 }
00595
00596 /**
00597   * @brief  Notify URB state change callback.
00598   * @param  hhcd: HCD handle
00599   * @param  chnum: Channel number.
00600   *         This parameter can be a value from 1 to 15
00601   * @param  urb_state:
00602   *          This parameter can be one of these values:
00603   *            URB_IDLE/
00604   *            URB_DONE/
00605   *            URB_NOTREADY/
00606   *            URB_NYET/
00607   *            URB_ERROR/
00608   *            URB_STALL/
00609   * @retval None
00610   */
00611 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
00612 {
00613   /* Prevent unused argument(s) compilation warning */
00614   UNUSED(hhcd);
00615   UNUSED(chnum);
00616   UNUSED(urb_state);
00617   /* NOTE : This function Should not be modified, when the callback is needed,
00618             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
00619    */
00620 }
00621
00622 /**
00623   * @}
00624   */
00625
00626 /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
00627  *  @brief   Management functions
00628  *
00629 @verbatim
00630  ===============================================================================
00631                       ##### Peripheral Control functions #####
00632  ===============================================================================
00633     [..]
00634     This subsection provides a set of functions allowing to control the HCD data
00635     transfers.
00636
00637 @endverbatim
00638   * @{
00639   */
00640
00641 /**
00642   * @brief  Start the host driver.
00643   * @param  hhcd: HCD handle
00644   * @retval HAL status
00645   */
00646 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
00647 {
00648   __HAL_LOCK(hhcd);
00649   __HAL_HCD_ENABLE(hhcd);
00650   USB_DriveVbus(hhcd->Instance, 1U);
00651   __HAL_UNLOCK(hhcd);
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @brief  Stop the host driver.
00657   * @param  hhcd: HCD handle
00658   * @retval HAL status
00659   */
00660
00661 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
00662 {
00663   __HAL_LOCK(hhcd);
00664   USB_StopHost(hhcd->Instance);
00665   __HAL_UNLOCK(hhcd);
00666   return HAL_OK;
00667 }
00668
00669 /**
00670   * @brief  Reset the host port.
00671   * @param  hhcd: HCD handle
00672   * @retval HAL status
00673   */
00674 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
00675 {
00676   return (USB_ResetPort(hhcd->Instance));
00677 }
00678
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
00684  *  @brief   Peripheral State functions
00685  *
00686 @verbatim
00687  ===============================================================================
00688                       ##### Peripheral State functions #####
00689  ===============================================================================
00690     [..]
00691     This subsection permits to get in run-time the status of the peripheral
00692     and the data flow.
00693
00694 @endverbatim
00695   * @{
00696   */
00697
00698 /**
00699   * @brief  Return the HCD handle state.
00700   * @param  hhcd: HCD handle
00701   * @retval HAL state
00702   */
00703 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
00704 {
00705   return hhcd->State;
00706 }
00707
00708 /**
00709   * @brief  Return  URB state for a channel.
00710   * @param  hhcd: HCD handle
00711   * @param  chnum: Channel number.
00712   *         This parameter can be a value from 1 to 15
00713   * @retval URB state.
00714   *          This parameter can be one of these values:
00715   *            URB_IDLE/
00716   *            URB_DONE/
00717   *            URB_NOTREADY/
00718   *            URB_NYET/
00719   *            URB_ERROR/
00720   *            URB_STALL
00721   */
00722 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00723 {
00724   return hhcd->hc[chnum].urb_state;
00725 }
00726
00727
00728 /**
00729   * @brief  Return the last host transfer size.
00730   * @param  hhcd: HCD handle
00731   * @param  chnum: Channel number.
00732   *         This parameter can be a value from 1 to 15
00733   * @retval last transfer size in byte
00734   */
00735 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00736 {
00737   return hhcd->hc[chnum].xfer_count;
00738 }
00739
00740 /**
00741   * @brief  Return the Host Channel state.
00742   * @param  hhcd: HCD handle
00743   * @param  chnum: Channel number.
00744   *         This parameter can be a value from 1 to 15
00745   * @retval Host channel state
00746   *          This parameter can be one of these values:
00747   *            HC_IDLE/
00748   *            HC_XFRC/
00749   *            HC_HALTED/
00750   *            HC_NYET/
00751   *            HC_NAK/
00752   *            HC_STALL/
00753   *            HC_XACTERR/
00754   *            HC_BBLERR/
00755   *            HC_DATATGLERR
00756   */
00757 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00758 {
00759   return hhcd->hc[chnum].state;
00760 }
00761
00762 /**
00763   * @brief  Return the current Host frame number.
00764   * @param  hhcd: HCD handle
00765   * @retval Current Host frame number
00766   */
00767 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
00768 {
00769   return (USB_GetCurrentFrame(hhcd->Instance));
00770 }
00771
00772 /**
00773   * @brief  Return the Host enumeration speed.
00774   * @param  hhcd: HCD handle
00775   * @retval Enumeration speed
00776   */
00777 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
00778 {
00779   return (USB_GetHostSpeed(hhcd->Instance));
00780 }
00781
00782 /**
00783   * @}
00784   */
00785
00786 /**
00787   * @}
00788   */
00789
00790 /** @addtogroup HCD_Private_Functions
00791   * @{
00792   */
00793 /**
00794   * @brief  Handle Host Channel IN interrupt requests.
00795   * @param  hhcd: HCD handle
00796   * @param  chnum: Channel number.
00797   *         This parameter can be a value from 1 to 15
00798   * @retval None
00799   */
00800 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00801 {
00802   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00803   uint32_t tmpreg = 0U;
00804
00805   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00806   {
00807     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00808     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00809   }
00810   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00811   {
00812     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00813   }
00814
00815   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00816   {
00817     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00818     hhcd->hc[chnum].state = HC_STALL;
00819     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00820     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00821     USB_HC_Halt(hhcd->Instance, chnum);
00822   }
00823   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
00824   {
00825     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00826     USB_HC_Halt(hhcd->Instance, chnum);
00827     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00828     hhcd->hc[chnum].state = HC_DATATGLERR;
00829     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
00830   }
00831
00832   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00833   {
00834     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00835     USB_HC_Halt(hhcd->Instance, chnum);
00836     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00837   }
00838
00839   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00840   {
00841
00842     if (hhcd->Init.dma_enable)
00843     {
00844       hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
00845         (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
00846     }
00847
00848     hhcd->hc[chnum].state = HC_XFRC;
00849     hhcd->hc[chnum].ErrCnt = 0U;
00850     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00851
00852
00853     if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00854         (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00855     {
00856       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00857       USB_HC_Halt(hhcd->Instance, chnum);
00858       __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00859
00860     }
00861     else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00862     {
00863       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
00864       hhcd->hc[chnum].urb_state = URB_DONE;
00865       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00866     }
00867     hhcd->hc[chnum].toggle_in ^= 1U;
00868
00869   }
00870   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
00871   {
00872     __HAL_HCD_MASK_HALT_HC_INT(chnum);
00873
00874     if(hhcd->hc[chnum].state == HC_XFRC)
00875     {
00876       hhcd->hc[chnum].urb_state  = URB_DONE;
00877     }
00878
00879     else if (hhcd->hc[chnum].state == HC_STALL)
00880     {
00881       hhcd->hc[chnum].urb_state  = URB_STALL;
00882     }
00883
00884     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
00885             (hhcd->hc[chnum].state == HC_DATATGLERR))
00886     {
00887       if(hhcd->hc[chnum].ErrCnt++ > 3U)
00888       {
00889         hhcd->hc[chnum].ErrCnt = 0U;
00890         hhcd->hc[chnum].urb_state = URB_ERROR;
00891       }
00892       else
00893       {
00894         hhcd->hc[chnum].urb_state = URB_NOTREADY;
00895       }
00896
00897       /* re-activate the channel  */
00898       tmpreg = USBx_HC(chnum)->HCCHAR;
00899       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
00900       tmpreg |= USB_OTG_HCCHAR_CHENA;
00901       USBx_HC(chnum)->HCCHAR = tmpreg;
00902     }
00903     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
00904     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00905   }
00906
00907   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
00908   {
00909     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00910     hhcd->hc[chnum].ErrCnt++;
00911     hhcd->hc[chnum].state = HC_XACTERR;
00912     USB_HC_Halt(hhcd->Instance, chnum);
00913     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
00914   }
00915   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
00916   {
00917     if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00918     {
00919       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00920       USB_HC_Halt(hhcd->Instance, chnum);
00921     }
00922     else if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00923               (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00924     {
00925       /* re-activate the channel */
00926       tmpreg = USBx_HC(chnum)->HCCHAR;
00927       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
00928       tmpreg |= USB_OTG_HCCHAR_CHENA;
00929       USBx_HC(chnum)->HCCHAR = tmpreg;
00930     }
00931     hhcd->hc[chnum].state = HC_NAK;
00932     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00933   }
00934 }
00935
00936 /**
00937   * @brief  Handle Host Channel OUT interrupt requests.
00938   * @param  hhcd: HCD handle
00939   * @param  chnum: Channel number.
00940   *         This parameter can be a value from 1 to 15
00941   * @retval None
00942   */
00943 static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00944 {
00945   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00946   uint32_t tmpreg = 0U;
00947
00948   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00949   {
00950     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00951     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00952   }
00953   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00954   {
00955     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00956
00957     if( hhcd->hc[chnum].do_ping == 1U)
00958     {
00959       hhcd->hc[chnum].state = HC_NYET;
00960       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00961       USB_HC_Halt(hhcd->Instance, chnum);
00962       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
00963     }
00964   }
00965
00966   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
00967   {
00968     hhcd->hc[chnum].state = HC_NYET;
00969     hhcd->hc[chnum].ErrCnt= 0U;
00970     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00971     USB_HC_Halt(hhcd->Instance, chnum);
00972     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
00973
00974   }
00975
00976   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00977   {
00978     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00979     USB_HC_Halt(hhcd->Instance, chnum);
00980     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00981   }
00982
00983   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00984   {
00985       hhcd->hc[chnum].ErrCnt = 0U;
00986     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00987     USB_HC_Halt(hhcd->Instance, chnum);
00988     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00989     hhcd->hc[chnum].state = HC_XFRC;
00990
00991   }
00992
00993   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00994   {
00995     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00996     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00997     USB_HC_Halt(hhcd->Instance, chnum);
00998     hhcd->hc[chnum].state = HC_STALL;
00999   }
01000
01001   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
01002   {
01003     hhcd->hc[chnum].ErrCnt = 0U;
01004     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01005     USB_HC_Halt(hhcd->Instance, chnum);
01006     hhcd->hc[chnum].state = HC_NAK;
01007     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
01008   }
01009
01010   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
01011   {
01012     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01013     USB_HC_Halt(hhcd->Instance, chnum);
01014     hhcd->hc[chnum].state = HC_XACTERR;
01015      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
01016   }
01017
01018   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
01019   {
01020     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01021     USB_HC_Halt(hhcd->Instance, chnum);
01022     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
01023     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
01024     hhcd->hc[chnum].state = HC_DATATGLERR;
01025   }
01026
01027
01028   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
01029   {
01030     __HAL_HCD_MASK_HALT_HC_INT(chnum);
01031
01032     if(hhcd->hc[chnum].state == HC_XFRC)
01033     {
01034       hhcd->hc[chnum].urb_state  = URB_DONE;
01035       if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
01036       {
01037         hhcd->hc[chnum].toggle_out ^= 1U;
01038       }
01039     }
01040     else if (hhcd->hc[chnum].state == HC_NAK)
01041     {
01042       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01043     }
01044
01045     else if (hhcd->hc[chnum].state == HC_NYET)
01046     {
01047       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01048       hhcd->hc[chnum].do_ping = 0U;
01049     }
01050
01051     else if (hhcd->hc[chnum].state == HC_STALL)
01052     {
01053       hhcd->hc[chnum].urb_state  = URB_STALL;
01054     }
01055
01056     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
01057             (hhcd->hc[chnum].state == HC_DATATGLERR))
01058     {
01059       if(hhcd->hc[chnum].ErrCnt++ > 3U)
01060       {
01061         hhcd->hc[chnum].ErrCnt = 0U;
01062         hhcd->hc[chnum].urb_state = URB_ERROR;
01063       }
01064       else
01065       {
01066         hhcd->hc[chnum].urb_state = URB_NOTREADY;
01067       }
01068
01069       /* re-activate the channel  */
01070       tmpreg = USBx_HC(chnum)->HCCHAR;
01071       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01072       tmpreg |= USB_OTG_HCCHAR_CHENA;
01073       USBx_HC(chnum)->HCCHAR = tmpreg;
01074     }
01075
01076     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
01077     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
01078   }
01079 }
01080
01081 /**
01082   * @brief  Handle Rx Queue Level interrupt requests.
01083   * @param  hhcd: HCD handle
01084   * @retval None
01085   */
01086 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
01087 {
01088   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01089   uint8_t  channelnum = 0U;
01090   uint32_t pktsts;
01091   uint32_t pktcnt;
01092   uint32_t temp = 0U;
01093   uint32_t tmpreg = 0U;
01094
01095   temp = hhcd->Instance->GRXSTSP;
01096   channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;
01097   pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17U;
01098   pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4U;
01099
01100   switch (pktsts)
01101   {
01102   case GRXSTS_PKTSTS_IN:
01103     /* Read the data into the host buffer. */
01104     if ((pktcnt > 0U) && (hhcd->hc[channelnum].xfer_buff != (void  *)0U))
01105     {
01106
01107       USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
01108
01109       /*manage multiple Xfer */
01110       hhcd->hc[channelnum].xfer_buff += pktcnt;
01111       hhcd->hc[channelnum].xfer_count  += pktcnt;
01112
01113       if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
01114       {
01115         /* re-activate the channel when more packets are expected */
01116         tmpreg = USBx_HC(channelnum)->HCCHAR;
01117         tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01118         tmpreg |= USB_OTG_HCCHAR_CHENA;
01119         USBx_HC(channelnum)->HCCHAR = tmpreg;
01120         hhcd->hc[channelnum].toggle_in ^= 1U;
01121       }
01122     }
01123     break;
01124
01125   case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
01126     break;
01127   case GRXSTS_PKTSTS_IN_XFER_COMP:
01128   case GRXSTS_PKTSTS_CH_HALTED:
01129   default:
01130     break;
01131   }
01132 }
01133
01134 /**
01135   * @brief  Handle Host Port interrupt requests.
01136   * @param  hhcd: HCD handle
01137   * @retval None
01138   */
01139 static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
01140 {
01141   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01142   __IO uint32_t hprt0, hprt0_dup;
01143
01144   /* Handle Host Port Interrupts */
01145   hprt0 = USBx_HPRT0;
01146   hprt0_dup = USBx_HPRT0;
01147
01148   hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01149                  USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01150
01151   /* Check whether Port Connect Detected */
01152   if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
01153   {
01154     if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
01155     {
01156       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01157       HAL_HCD_Connect_Callback(hhcd);
01158     }
01159     hprt0_dup  |= USB_OTG_HPRT_PCDET;
01160
01161   }
01162
01163   /* Check whether Port Enable Changed */
01164   if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
01165   {
01166     hprt0_dup |= USB_OTG_HPRT_PENCHNG;
01167
01168     if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
01169     {
01170       if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
01171       {
01172         if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U))
01173         {
01174           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
01175         }
01176         else
01177         {
01178           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
01179         }
01180       }
01181       else
01182       {
01183         if(hhcd->Init.speed == HCD_SPEED_FULL)
01184         {
01185           USBx_HOST->HFIR = (uint32_t)60000U;
01186         }
01187       }
01188       HAL_HCD_Connect_Callback(hhcd);
01189
01190       if(hhcd->Init.speed == HCD_SPEED_HIGH)
01191       {
01192         USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01193       }
01194     }
01195     else
01196     {
01197       /* Clean up HPRT */
01198       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01199         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01200
01201       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01202     }
01203   }
01204
01205   /* Check for an over current */
01206   if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
01207   {
01208     hprt0_dup |= USB_OTG_HPRT_POCCHNG;
01209   }
01210
01211   /* Clear Port Interrupts */
01212   USBx_HPRT0 = hprt0_dup;
01213 }
01214
01215 /**
01216   * @}
01217   */
01218 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
01219           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
01220 #endif /* HAL_HCD_MODULE_ENABLED */
01221 /**
01222   * @}
01223   */
01224
01225 /**
01226   * @}
01227   */
01228
01229 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_hcd.h Source File

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stm32f4xx_hal_hcd.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_hcd.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of HCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_HCD_H
00040 #define __STM32F4xx_HAL_HCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00046     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00047     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00048     defined(STM32F469xx) || defined(STM32F479xx)
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_ll_usb.h"
00051
00052 /** @addtogroup STM32F4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup HCD
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup HCD_Exported_Types HCD Exported Types
00062   * @{
00063   */
00064
00065 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
00066   * @{
00067   */
00068 typedef enum
00069 {
00070   HAL_HCD_STATE_RESET    = 0x00U,
00071   HAL_HCD_STATE_READY    = 0x01U,
00072   HAL_HCD_STATE_ERROR    = 0x02U,
00073   HAL_HCD_STATE_BUSY     = 0x03U,
00074   HAL_HCD_STATE_TIMEOUT  = 0x04U
00075 } HCD_StateTypeDef;
00076
00077 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
00078 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
00079 typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;
00080 typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
00081 typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
00087   * @{
00088   */
00089 typedef struct
00090 {
00091   HCD_TypeDef               *Instance;  /*!< Register base address    */
00092   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
00093   HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
00094   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
00095   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
00096   void                      *pData;     /*!< Pointer Stack Handler    */
00097 } HCD_HandleTypeDef;
00098 /**
00099   * @}
00100   */
00101
00102 /**
00103   * @}
00104   */
00105
00106 /* Exported constants --------------------------------------------------------*/
00107 /** @defgroup HCD_Exported_Constants HCD Exported Constants
00108   * @{
00109   */
00110
00111 /** @defgroup HCD_Speed HCD Speed
00112   * @{
00113   */
00114 #define HCD_SPEED_HIGH               0U
00115 #define HCD_SPEED_LOW                2U
00116 #define HCD_SPEED_FULL               3U
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup HCD_PHY_Module HCD PHY Module
00122   * @{
00123   */
00124 #define HCD_PHY_ULPI                 1U
00125 #define HCD_PHY_EMBEDDED             2U
00126 /**
00127   * @}
00128   */
00129
00130 /**
00131   * @}
00132   */
00133
00134 /* Exported macro ------------------------------------------------------------*/
00135 /** @defgroup HCD_Exported_Macros HCD Exported Macros
00136  *  @brief macros to handle interrupts and specific clock configurations
00137  * @{
00138  */
00139 #define __HAL_HCD_ENABLE(__HANDLE__)               USB_EnableGlobalInt ((__HANDLE__)->Instance)
00140 #define __HAL_HCD_DISABLE(__HANDLE__)              USB_DisableGlobalInt ((__HANDLE__)->Instance)
00141
00142 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00143 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00144 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
00145
00146 #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
00147 #define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
00148 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
00149 #define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
00150 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
00151 /**
00152   * @}
00153   */
00154
00155 /* Exported functions --------------------------------------------------------*/
00156 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
00157   * @{
00158   */
00159
00160 /* Initialization/de-initialization functions  ********************************/
00161 /** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00162   * @{
00163   */
00164 HAL_StatusTypeDef   HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
00165 HAL_StatusTypeDef   HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
00166 HAL_StatusTypeDef   HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00167                                     uint8_t ch_num,
00168                                     uint8_t epnum,
00169                                     uint8_t dev_address,
00170                                     uint8_t speed,
00171                                     uint8_t ep_type,
00172                                     uint16_t mps);
00173
00174 HAL_StatusTypeDef   HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
00175
00176 void                HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
00177 void                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
00178 /**
00179   * @}
00180   */
00181
00182 /* I/O operation functions  ***************************************************/
00183 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
00184   * @{
00185   */
00186 HAL_StatusTypeDef   HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00187                                              uint8_t pipe,
00188                                              uint8_t direction,
00189                                              uint8_t ep_type,
00190                                              uint8_t token,
00191                                              uint8_t* pbuff,
00192                                              uint16_t length,
00193                                              uint8_t do_ping);
00194
00195 /* Non-Blocking mode: Interrupt */
00196 void                HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
00197 void                HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
00198 void                HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
00199 void                HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
00200 void                HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
00201                                                         uint8_t chnum,
00202                                                         HCD_URBStateTypeDef urb_state);
00203 /**
00204   * @}
00205   */
00206
00207 /* Peripheral Control functions  **********************************************/
00208 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
00209   * @{
00210   */
00211 HAL_StatusTypeDef   HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
00212 HAL_StatusTypeDef   HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
00213 HAL_StatusTypeDef   HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
00214 /**
00215   * @}
00216   */
00217
00218 /* Peripheral State functions  ************************************************/
00219 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
00220   * @{
00221   */
00222 HCD_StateTypeDef    HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
00223 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00224 uint32_t            HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00225 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00226 uint32_t            HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
00227 uint32_t            HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
00228 /**
00229   * @}
00230   */
00231
00232 /**
00233   * @}
00234   */
00235
00236 /* Private macros ------------------------------------------------------------*/
00237 /** @defgroup HCD_Private_Macros HCD Private Macros
00238  * @{
00239  */
00240
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /**
00250   * @}
00251   */
00252 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00253           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00254 #ifdef __cplusplus
00255 }
00256 #endif
00257
00258 #endif /* __STM32F4xx_HAL_HCD_H */
00259
00260 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c.c Source File

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stm32f4xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   I2C HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     The I2C HAL driver can be used as follows:
00021
00022     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00023         I2C_HandleTypeDef  hi2c;
00024
00025     (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
00026         (##) Enable the I2Cx interface clock
00027         (##) I2C pins configuration
00028             (+++) Enable the clock for the I2C GPIOs
00029             (+++) Configure I2C pins as alternate function open-drain
00030         (##) NVIC configuration if you need to use interrupt process
00031             (+++) Configure the I2Cx interrupt priority
00032             (+++) Enable the NVIC I2C IRQ Channel
00033         (##) DMA Configuration if you need to use DMA process
00034             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
00035             (+++) Enable the DMAx interface clock using
00036             (+++) Configure the DMA handle parameters
00037             (+++) Configure the DMA Tx or Rx Stream
00038             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00039             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00040                   the DMA Tx or Rx Stream
00041
00042     (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
00043         Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
00044
00045     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00046         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00047
00048     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00049
00050     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00051
00052     *** Polling mode IO operation ***
00053     =================================
00054     [..]
00055       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00056       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00057       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00058       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00059
00060     *** Polling mode IO MEM operation ***
00061     =====================================
00062     [..]
00063       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00064       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00065
00066
00067     *** Interrupt mode IO operation ***
00068     ===================================
00069     [..]
00070       (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
00071       (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
00072            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
00073       (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
00074       (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
00075            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
00076       (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
00077       (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
00078            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
00079       (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
00080       (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
00081            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
00082       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00083            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00084
00085     *** Interrupt mode IO sequential operation ***
00086     ==============================================
00087     [..]
00088       (+@) These interfaces allow to manage a sequential transfer with a repeated start condition
00089           when a direction change during transfer
00090       (+) A specific option manage the different steps of a sequential transfer
00091       (+) Differents steps option I2C_XferOptions_definition are listed below :
00092       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00093       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a start condition with data to transfer without a final stop condition
00094       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
00095              manage only the new data to transfer if no direction change and without a final stop condition in both cases
00096       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a restart condition with new data to transfer if the direction change or
00097              manage only the new data to transfer if no direction change and with a final stop condition in both cases
00098
00099       (+) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
00100       (++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00101            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00102       (+) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
00103       (++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00104            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00105       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00106       (++) The associated previous transfer callback is called at the end of abort process
00107       (++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
00108       (++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
00109       (+) Enable/disable the Address listen mode in slave I2C mode
00110            using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
00111       (++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
00112            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00113       (++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
00114            add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00115       (+) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
00116       (++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00117            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00118       (+) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
00119       (++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00120            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00121
00122
00123     *** Interrupt mode IO MEM operation ***
00124     =======================================
00125     [..]
00126       (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
00127           HAL_I2C_Mem_Write_IT()
00128       (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
00129            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
00130       (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
00131           HAL_I2C_Mem_Read_IT()
00132       (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
00133            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
00134       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00135            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00136
00137     *** DMA mode IO operation ***
00138     ==============================
00139     [..]
00140       (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
00141           HAL_I2C_Master_Transmit_DMA()
00142       (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
00143            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
00144       (+) Receive in master mode an amount of data in non blocking mode (DMA) using
00145           HAL_I2C_Master_Receive_DMA()
00146       (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
00147            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
00148       (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
00149           HAL_I2C_Slave_Transmit_DMA()
00150       (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
00151            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
00152       (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
00153           HAL_I2C_Slave_Receive_DMA()
00154       (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
00155            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
00156       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00157            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00158
00159     *** DMA mode IO MEM operation ***
00160     =================================
00161     [..]
00162       (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
00163           HAL_I2C_Mem_Write_DMA()
00164       (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
00165            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
00166       (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
00167           HAL_I2C_Mem_Read_DMA()
00168       (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
00169            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
00170       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00171            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00172
00173
00174      *** I2C HAL driver macros list ***
00175      ==================================
00176      [..]
00177        Below the list of most used macros in I2C HAL driver.
00178
00179       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00180       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00181       (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
00182       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00183       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00184       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00185
00186      [..]
00187        (@) You can refer to the I2C HAL driver header file for more useful macros
00188
00189
00190   @endverbatim
00191   ******************************************************************************
00192   * @attention
00193   *
00194   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00195   *
00196   * Redistribution and use in source and binary forms, with or without modification,
00197   * are permitted provided that the following conditions are met:
00198   *   1. Redistributions of source code must retain the above copyright notice,
00199   *      this list of conditions and the following disclaimer.
00200   *   2. Redistributions in binary form must reproduce the above copyright notice,
00201   *      this list of conditions and the following disclaimer in the documentation
00202   *      and/or other materials provided with the distribution.
00203   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00204   *      may be used to endorse or promote products derived from this software
00205   *      without specific prior written permission.
00206   *
00207   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00208   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00209   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00210   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00211   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00212   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00213   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00214   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00215   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00216   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00217   *
00218   ******************************************************************************
00219   */
00220
00221 /* Includes ------------------------------------------------------------------*/
00222 #include "stm32f4xx_hal.h"
00223
00224 /** @addtogroup STM32F4xx_HAL_Driver
00225   * @{
00226   */
00227
00228 /** @defgroup I2C I2C
00229   * @brief I2C HAL module driver
00230   * @{
00231   */
00232
00233 #ifdef HAL_I2C_MODULE_ENABLED
00234
00235 /* Private typedef -----------------------------------------------------------*/
00236 /* Private define ------------------------------------------------------------*/
00237 /** @addtogroup I2C_Private_Constants
00238   * @{
00239   */
00240 #define I2C_TIMEOUT_FLAG          ((uint32_t)35U)         /*!< Timeout 35 ms             */
00241 #define I2C_TIMEOUT_ADDR_SLAVE    ((uint32_t)10000U)      /*!< Timeout 10 s              */
00242 #define I2C_TIMEOUT_BUSY_FLAG     ((uint32_t)10000U)      /*!< Timeout 10 s              */
00243 #define I2C_NO_OPTION_FRAME       ((uint32_t)0xFFFF0000U) /*!< XferOptions default value */
00244
00245 /* Private define for @ref PreviousState usage */
00246 #define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
00247 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00248 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00249 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00250 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00251 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00252
00253 /**
00254   * @}
00255   */
00256
00257 /* Private macro -------------------------------------------------------------*/
00258 /* Private variables ---------------------------------------------------------*/
00259 /* Private function prototypes -----------------------------------------------*/
00260 /** @addtogroup I2C_Private_Functions
00261   * @{
00262   */
00263 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00264 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00265 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00266 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00267 static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
00268 static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
00269 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00270
00271 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
00272 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
00273 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
00274 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
00275 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00276 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout);
00277 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00278 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00279 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00280 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
00281 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
00282
00283 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
00284 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
00285 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
00286 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
00287
00288 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
00289 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
00290 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
00291 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
00292 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
00293 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
00294 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
00295 /**
00296   * @}
00297   */
00298
00299 /* Exported functions --------------------------------------------------------*/
00300 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00301   * @{
00302   */
00303
00304 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00305  *  @brief    Initialization and Configuration functions
00306  *
00307 @verbatim
00308  ===============================================================================
00309               ##### Initialization and de-initialization functions #####
00310  ===============================================================================
00311     [..]  This subsection provides a set of functions allowing to initialize and
00312           de-initialize the I2Cx peripheral:
00313
00314       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00315           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
00316
00317       (+) Call the function HAL_I2C_Init() to configure the selected device with
00318           the selected configuration:
00319         (++) Communication Speed
00320         (++) Duty cycle
00321         (++) Addressing mode
00322         (++) Own Address 1
00323         (++) Dual Addressing mode
00324         (++) Own Address 2
00325         (++) General call mode
00326         (++) Nostretch mode
00327
00328       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00329           of the selected I2Cx peripheral.
00330
00331 @endverbatim
00332   * @{
00333   */
00334
00335 /**
00336   * @brief  Initializes the I2C according to the specified parameters
00337   *         in the I2C_InitTypeDef and create the associated handle.
00338   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00339   *         the configuration information for I2C module
00340   * @retval HAL status
00341   */
00342 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00343 {
00344   uint32_t freqrange = 0U;
00345   uint32_t pclk1 = 0U;
00346
00347   /* Check the I2C handle allocation */
00348   if(hi2c == NULL)
00349   {
00350     return HAL_ERROR;
00351   }
00352
00353   /* Check the parameters */
00354   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00355   assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
00356   assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
00357   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00358   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00359   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00360   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00361   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00362   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00363
00364   if(hi2c->State == HAL_I2C_STATE_RESET)
00365   {
00366     /* Allocate lock resource and initialize it */
00367     hi2c->Lock = HAL_UNLOCKED;
00368     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00369     HAL_I2C_MspInit(hi2c);
00370   }
00371
00372   hi2c->State = HAL_I2C_STATE_BUSY;
00373
00374   /* Disable the selected I2C peripheral */
00375   __HAL_I2C_DISABLE(hi2c);
00376
00377   /* Get PCLK1 frequency */
00378   pclk1 = HAL_RCC_GetPCLK1Freq();
00379
00380   /* Calculate frequency range */
00381   freqrange = I2C_FREQRANGE(pclk1);
00382
00383   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00384   /* Configure I2Cx: Frequency range */
00385   hi2c->Instance->CR2 = freqrange;
00386
00387   /*---------------------------- I2Cx TRISE Configuration --------------------*/
00388   /* Configure I2Cx: Rise Time */
00389   hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
00390
00391   /*---------------------------- I2Cx CCR Configuration ----------------------*/
00392   /* Configure I2Cx: Speed */
00393   hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
00394
00395   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00396   /* Configure I2Cx: Generalcall and NoStretch mode */
00397   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00398
00399   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00400   /* Configure I2Cx: Own Address1 and addressing mode */
00401   hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
00402
00403   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00404   /* Configure I2Cx: Dual mode and Own Address2 */
00405   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
00406
00407   /* Enable the selected I2C peripheral */
00408   __HAL_I2C_ENABLE(hi2c);
00409
00410   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00411   hi2c->State = HAL_I2C_STATE_READY;
00412   hi2c->PreviousState = I2C_STATE_NONE;
00413   hi2c->Mode = HAL_I2C_MODE_NONE;
00414
00415   return HAL_OK;
00416 }
00417
00418 /**
00419   * @brief  DeInitializes the I2C peripheral.
00420   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00421   *         the configuration information for I2C module
00422   * @retval HAL status
00423   */
00424 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00425 {
00426   /* Check the I2C handle allocation */
00427   if(hi2c == NULL)
00428   {
00429     return HAL_ERROR;
00430   }
00431
00432   /* Check the parameters */
00433   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00434
00435   hi2c->State = HAL_I2C_STATE_BUSY;
00436
00437   /* Disable the I2C Peripheral Clock */
00438   __HAL_I2C_DISABLE(hi2c);
00439
00440   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00441   HAL_I2C_MspDeInit(hi2c);
00442
00443   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00444   hi2c->State = HAL_I2C_STATE_RESET;
00445   hi2c->PreviousState = I2C_STATE_NONE;
00446   hi2c->Mode = HAL_I2C_MODE_NONE;
00447
00448   /* Release Lock */
00449   __HAL_UNLOCK(hi2c);
00450
00451   return HAL_OK;
00452 }
00453
00454 /**
00455   * @brief I2C MSP Init.
00456   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00457   *         the configuration information for I2C module
00458   * @retval None
00459   */
00460  __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00461 {
00462   /* Prevent unused argument(s) compilation warning */
00463   UNUSED(hi2c);
00464   /* NOTE : This function Should not be modified, when the callback is needed,
00465             the HAL_I2C_MspInit could be implemented in the user file
00466    */
00467 }
00468
00469 /**
00470   * @brief I2C MSP DeInit
00471   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00472   *         the configuration information for I2C module
00473   * @retval None
00474   */
00475  __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00476 {
00477   /* Prevent unused argument(s) compilation warning */
00478   UNUSED(hi2c);
00479   /* NOTE : This function Should not be modified, when the callback is needed,
00480             the HAL_I2C_MspDeInit could be implemented in the user file
00481    */
00482 }
00483
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup I2C_Exported_Functions_Group2 IO operation functions
00489  *  @brief   Data transfers functions
00490  *
00491 @verbatim
00492  ===============================================================================
00493                       ##### IO operation functions #####
00494  ===============================================================================
00495     [..]
00496     This subsection provides a set of functions allowing to manage the I2C data
00497     transfers.
00498
00499     (#) There are two modes of transfer:
00500        (++) Blocking mode : The communication is performed in the polling mode.
00501             The status of all data processing is returned by the same function
00502             after finishing transfer.
00503        (++) No-Blocking mode : The communication is performed using Interrupts
00504             or DMA. These functions return the status of the transfer startup.
00505             The end of the data processing will be indicated through the
00506             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00507             using DMA mode.
00508
00509     (#) Blocking mode functions are :
00510         (++) HAL_I2C_Master_Transmit()
00511         (++) HAL_I2C_Master_Receive()
00512         (++) HAL_I2C_Slave_Transmit()
00513         (++) HAL_I2C_Slave_Receive()
00514         (++) HAL_I2C_Mem_Write()
00515         (++) HAL_I2C_Mem_Read()
00516         (++) HAL_I2C_IsDeviceReady()
00517
00518     (#) No-Blocking mode functions with Interrupt are :
00519         (++) HAL_I2C_Master_Transmit_IT()
00520         (++) HAL_I2C_Master_Receive_IT()
00521         (++) HAL_I2C_Slave_Transmit_IT()
00522         (++) HAL_I2C_Slave_Receive_IT()
00523         (++) HAL_I2C_Mem_Write_IT()
00524         (++) HAL_I2C_Mem_Read_IT()
00525
00526     (#) No-Blocking mode functions with DMA are :
00527         (++) HAL_I2C_Master_Transmit_DMA()
00528         (++) HAL_I2C_Master_Receive_DMA()
00529         (++) HAL_I2C_Slave_Transmit_DMA()
00530         (++) HAL_I2C_Slave_Receive_DMA()
00531         (++) HAL_I2C_Mem_Write_DMA()
00532         (++) HAL_I2C_Mem_Read_DMA()
00533
00534     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00535         (++) HAL_I2C_MemTxCpltCallback()
00536         (++) HAL_I2C_MemRxCpltCallback()
00537         (++) HAL_I2C_MasterTxCpltCallback()
00538         (++) HAL_I2C_MasterRxCpltCallback()
00539         (++) HAL_I2C_SlaveTxCpltCallback()
00540         (++) HAL_I2C_SlaveRxCpltCallback()
00541         (++) HAL_I2C_ErrorCallback()
00542
00543 @endverbatim
00544   * @{
00545   */
00546
00547 /**
00548   * @brief  Transmits in master mode an amount of data in blocking mode.
00549   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00550   *         the configuration information for I2C module
00551   * @param  DevAddress Target device address
00552   * @param  pData Pointer to data buffer
00553   * @param  Size Amount of data to be sent
00554   * @param  Timeout Timeout duration
00555   * @retval HAL status
00556   */
00557 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00558 {
00559   if(hi2c->State == HAL_I2C_STATE_READY)
00560   {
00561     /* Wait until BUSY flag is reset */
00562     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
00563     {
00564       return HAL_BUSY;
00565     }
00566
00567     /* Process Locked */
00568     __HAL_LOCK(hi2c);
00569
00570     /* Disable Pos */
00571     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
00572
00573     hi2c->State = HAL_I2C_STATE_BUSY_TX;
00574     hi2c->Mode = HAL_I2C_MODE_MASTER;
00575     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00576     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
00577
00578     /* Send Slave Address */
00579     if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK)
00580     {
00581       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00582       {
00583         /* Process Unlocked */
00584         __HAL_UNLOCK(hi2c);
00585         return HAL_ERROR;
00586       }
00587       else
00588       {
00589         /* Process Unlocked */
00590         __HAL_UNLOCK(hi2c);
00591         return HAL_TIMEOUT;
00592       }
00593     }
00594
00595     /* Clear ADDR flag */
00596     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00597
00598     while(Size > 0U)
00599     {
00600       /* Wait until TXE flag is set */
00601       if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00602       {
00603         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00604         {
00605           /* Generate Stop */
00606           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00607           return HAL_ERROR;
00608         }
00609         else
00610         {
00611           return HAL_TIMEOUT;
00612         }
00613       }
00614
00615       /* Write data to DR */
00616       hi2c->Instance->DR = (*pData++);
00617       Size--;
00618
00619       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
00620       {
00621         /* Write data to DR */
00622         hi2c->Instance->DR = (*pData++);
00623         Size--;
00624       }
00625
00626       /* Wait until BTF flag is set */
00627       if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00628       {
00629         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00630         {
00631           /* Generate Stop */
00632           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00633           return HAL_ERROR;
00634         }
00635         else
00636         {
00637           return HAL_TIMEOUT;
00638         }
00639       }
00640     }
00641
00642     /* Generate Stop */
00643     hi2c->Instance->CR1 |= I2C_CR1_STOP;
00644
00645     hi2c->State = HAL_I2C_STATE_READY;
00646     hi2c->Mode = HAL_I2C_MODE_NONE;
00647
00648     /* Process Unlocked */
00649     __HAL_UNLOCK(hi2c);
00650
00651     return HAL_OK;
00652   }
00653   else
00654   {
00655     return HAL_BUSY;
00656   }
00657 }
00658
00659 /**
00660   * @brief  Receives in master mode an amount of data in blocking mode.
00661   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00662   *         the configuration information for I2C module
00663   * @param  DevAddress Target device address
00664   * @param  pData Pointer to data buffer
00665   * @param  Size Amount of data to be sent
00666   * @param  Timeout Timeout duration
00667   * @retval HAL status
00668   */
00669 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00670 {
00671   if(hi2c->State == HAL_I2C_STATE_READY)
00672   {
00673     /* Wait until BUSY flag is reset */
00674     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
00675     {
00676       return HAL_BUSY;
00677     }
00678
00679     /* Process Locked */
00680     __HAL_LOCK(hi2c);
00681
00682     /* Disable Pos */
00683     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
00684
00685     hi2c->State = HAL_I2C_STATE_BUSY_RX;
00686     hi2c->Mode = HAL_I2C_MODE_MASTER;
00687     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00688     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
00689
00690     /* Send Slave Address */
00691     if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK)
00692     {
00693       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00694       {
00695         /* Process Unlocked */
00696         __HAL_UNLOCK(hi2c);
00697         return HAL_ERROR;
00698       }
00699       else
00700       {
00701         /* Process Unlocked */
00702         __HAL_UNLOCK(hi2c);
00703         return HAL_TIMEOUT;
00704       }
00705     }
00706
00707     if(Size == 0U)
00708     {
00709       /* Clear ADDR flag */
00710       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00711
00712       /* Generate Stop */
00713       hi2c->Instance->CR1 |= I2C_CR1_STOP;
00714     }
00715     else if(Size == 1U)
00716     {
00717       /* Disable Acknowledge */
00718       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00719
00720       /* Clear ADDR flag */
00721       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00722
00723       /* Generate Stop */
00724       hi2c->Instance->CR1 |= I2C_CR1_STOP;
00725     }
00726     else if(Size == 2U)
00727     {
00728       /* Disable Acknowledge */
00729       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00730
00731       /* Enable Pos */
00732       hi2c->Instance->CR1 |= I2C_CR1_POS;
00733
00734       /* Clear ADDR flag */
00735       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00736     }
00737     else
00738     {
00739       /* Enable Acknowledge */
00740       hi2c->Instance->CR1 |= I2C_CR1_ACK;
00741
00742       /* Clear ADDR flag */
00743       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00744     }
00745
00746     while(Size > 0U)
00747     {
00748       if(Size <= 3U)
00749       {
00750         /* One byte */
00751         if(Size == 1U)
00752         {
00753           /* Wait until RXNE flag is set */
00754           if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00755           {
00756             if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
00757             {
00758               return HAL_TIMEOUT;
00759             }
00760             else
00761             {
00762               return HAL_ERROR;
00763             }
00764           }
00765
00766           /* Read data from DR */
00767           (*pData++) = hi2c->Instance->DR;
00768           Size--;
00769         }
00770         /* Two bytes */
00771         else if(Size == 2U)
00772         {
00773           /* Wait until BTF flag is set */
00774           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
00775           {
00776             return HAL_TIMEOUT;
00777           }
00778
00779           /* Generate Stop */
00780           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00781
00782           /* Read data from DR */
00783           (*pData++) = hi2c->Instance->DR;
00784           Size--;
00785
00786           /* Read data from DR */
00787           (*pData++) = hi2c->Instance->DR;
00788           Size--;
00789         }
00790         /* 3 Last bytes */
00791         else
00792         {
00793           /* Wait until BTF flag is set */
00794           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
00795           {
00796             return HAL_TIMEOUT;
00797           }
00798
00799           /* Disable Acknowledge */
00800           hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00801
00802           /* Read data from DR */
00803           (*pData++) = hi2c->Instance->DR;
00804           Size--;
00805
00806           /* Wait until BTF flag is set */
00807           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
00808           {
00809             return HAL_TIMEOUT;
00810           }
00811
00812           /* Generate Stop */
00813           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00814
00815           /* Read data from DR */
00816           (*pData++) = hi2c->Instance->DR;
00817           Size--;
00818
00819           /* Read data from DR */
00820           (*pData++) = hi2c->Instance->DR;
00821           Size--;
00822         }
00823       }
00824       else
00825       {
00826         /* Wait until RXNE flag is set */
00827         if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00828         {
00829           if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
00830           {
00831             return HAL_TIMEOUT;
00832           }
00833           else
00834           {
00835             return HAL_ERROR;
00836           }
00837         }
00838
00839         /* Read data from DR */
00840         (*pData++) = hi2c->Instance->DR;
00841         Size--;
00842
00843         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
00844         {
00845           /* Read data from DR */
00846           (*pData++) = hi2c->Instance->DR;
00847           Size--;
00848         }
00849       }
00850     }
00851
00852     hi2c->State = HAL_I2C_STATE_READY;
00853     hi2c->Mode = HAL_I2C_MODE_NONE;
00854
00855     /* Process Unlocked */
00856     __HAL_UNLOCK(hi2c);
00857
00858     return HAL_OK;
00859   }
00860   else
00861   {
00862     return HAL_BUSY;
00863   }
00864 }
00865
00866 /**
00867   * @brief  Transmits in slave mode an amount of data in blocking mode.
00868   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00869   *         the configuration information for I2C module
00870   * @param  pData Pointer to data buffer
00871   * @param  Size Amount of data to be sent
00872   * @param  Timeout Timeout duration
00873   * @retval HAL status
00874   */
00875 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00876 {
00877   if(hi2c->State == HAL_I2C_STATE_READY)
00878   {
00879     if((pData == NULL) || (Size == 0U))
00880     {
00881       return  HAL_ERROR;
00882     }
00883
00884     /* Wait until BUSY flag is reset */
00885     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
00886     {
00887       return HAL_BUSY;
00888     }
00889
00890     /* Process Locked */
00891     __HAL_LOCK(hi2c);
00892
00893     /* Disable Pos */
00894     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
00895
00896     hi2c->State = HAL_I2C_STATE_BUSY_TX;
00897     hi2c->Mode = HAL_I2C_MODE_SLAVE;
00898     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00899     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
00900
00901     /* Enable Address Acknowledge */
00902     hi2c->Instance->CR1 |= I2C_CR1_ACK;
00903
00904     /* Wait until ADDR flag is set */
00905     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00906     {
00907       return HAL_TIMEOUT;
00908     }
00909
00910     /* Clear ADDR flag */
00911     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00912
00913     /* If 10bit addressing mode is selected */
00914     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00915     {
00916       /* Wait until ADDR flag is set */
00917       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
00918       {
00919         return HAL_TIMEOUT;
00920       }
00921
00922       /* Clear ADDR flag */
00923       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00924     }
00925
00926     while(Size > 0U)
00927     {
00928       /* Wait until TXE flag is set */
00929       if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
00930       {
00931         /* Disable Address Acknowledge */
00932         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00933         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00934         {
00935           return HAL_ERROR;
00936         }
00937         else
00938         {
00939           return HAL_TIMEOUT;
00940         }
00941       }
00942
00943       /* Write data to DR */
00944       hi2c->Instance->DR = (*pData++);
00945       Size--;
00946
00947       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
00948       {
00949         /* Write data to DR */
00950         hi2c->Instance->DR = (*pData++);
00951         Size--;
00952       }
00953     }
00954
00955     /* Wait until AF flag is set */
00956     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK)
00957     {
00958       return HAL_TIMEOUT;
00959     }
00960
00961     /* Clear AF flag */
00962     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
00963
00964     /* Disable Address Acknowledge */
00965     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00966
00967     hi2c->State = HAL_I2C_STATE_READY;
00968     hi2c->Mode = HAL_I2C_MODE_NONE;
00969
00970     /* Process Unlocked */
00971     __HAL_UNLOCK(hi2c);
00972
00973     return HAL_OK;
00974   }
00975   else
00976   {
00977     return HAL_BUSY;
00978   }
00979 }
00980
00981 /**
00982   * @brief  Receive in slave mode an amount of data in blocking mode
00983   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00984   *         the configuration information for I2C module
00985   * @param  pData Pointer to data buffer
00986   * @param  Size Amount of data to be sent
00987   * @param  Timeout Timeout duration
00988   * @retval HAL status
00989   */
00990 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00991 {
00992   if(hi2c->State == HAL_I2C_STATE_READY)
00993   {
00994     if((pData == NULL) || (Size == 0U))
00995     {
00996       return  HAL_ERROR;
00997     }
00998
00999     /* Wait until BUSY flag is reset */
01000     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01001     {
01002       return HAL_BUSY;
01003     }
01004
01005     /* Process Locked */
01006     __HAL_LOCK(hi2c);
01007
01008     /* Disable Pos */
01009     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01010
01011     hi2c->State = HAL_I2C_STATE_BUSY_RX;
01012     hi2c->Mode = HAL_I2C_MODE_SLAVE;
01013     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01014     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01015
01016     /* Enable Address Acknowledge */
01017     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01018
01019     /* Wait until ADDR flag is set */
01020     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
01021     {
01022       return HAL_TIMEOUT;
01023     }
01024
01025     /* Clear ADDR flag */
01026     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01027
01028     while(Size > 0U)
01029     {
01030       /* Wait until RXNE flag is set */
01031       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
01032       {
01033         /* Disable Address Acknowledge */
01034         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01035         if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
01036         {
01037           return HAL_TIMEOUT;
01038         }
01039         else
01040         {
01041           return HAL_ERROR;
01042         }
01043       }
01044
01045       /* Read data from DR */
01046       (*pData++) = hi2c->Instance->DR;
01047       Size--;
01048
01049       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
01050       {
01051         /* Read data from DR */
01052         (*pData++) = hi2c->Instance->DR;
01053         Size--;
01054       }
01055     }
01056
01057     /* Wait until STOP flag is set */
01058     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK)
01059     {
01060       /* Disable Address Acknowledge */
01061       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01062
01063       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01064       {
01065         return HAL_ERROR;
01066       }
01067       else
01068       {
01069         return HAL_TIMEOUT;
01070       }
01071     }
01072
01073     /* Clear STOP flag */
01074     __HAL_I2C_CLEAR_STOPFLAG(hi2c);
01075
01076     /* Disable Address Acknowledge */
01077     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01078
01079     hi2c->State = HAL_I2C_STATE_READY;
01080     hi2c->Mode = HAL_I2C_MODE_NONE;
01081
01082     /* Process Unlocked */
01083     __HAL_UNLOCK(hi2c);
01084
01085     return HAL_OK;
01086   }
01087   else
01088   {
01089     return HAL_BUSY;
01090   }
01091 }
01092
01093 /**
01094   * @brief  Transmit in master mode an amount of data in no-blocking mode with Interrupt
01095   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01096   *         the configuration information for I2C module
01097   * @param  DevAddress Target device address
01098   * @param  pData Pointer to data buffer
01099   * @param  Size Amount of data to be sent
01100   * @retval HAL status
01101   */
01102 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01103 {
01104   if(hi2c->State == HAL_I2C_STATE_READY)
01105   {
01106     /* Wait until BUSY flag is reset */
01107     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01108     {
01109       return HAL_BUSY;
01110     }
01111
01112     /* Process Locked */
01113     __HAL_LOCK(hi2c);
01114
01115     /* Disable Pos */
01116     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01117
01118     hi2c->State = HAL_I2C_STATE_BUSY_TX;
01119     hi2c->Mode = HAL_I2C_MODE_MASTER;
01120     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01121
01122     hi2c->pBuffPtr = pData;
01123     hi2c->XferSize = Size;
01124     hi2c->XferCount = Size;
01125     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01126
01127     /* Send Slave Address */
01128     if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
01129     {
01130       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01131       {
01132         /* Process Unlocked */
01133         __HAL_UNLOCK(hi2c);
01134         return HAL_ERROR;
01135       }
01136       else
01137       {
01138         /* Process Unlocked */
01139         __HAL_UNLOCK(hi2c);
01140         return HAL_TIMEOUT;
01141       }
01142     }
01143
01144     /* Clear ADDR flag */
01145     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01146
01147     if(hi2c->XferSize > 0U)
01148     {
01149     /* Process Unlocked */
01150     __HAL_UNLOCK(hi2c);
01151
01152     /* Note : The I2C interrupts must be enabled after unlocking current process
01153               to avoid the risk of I2C interrupt handle execution before current
01154               process unlock */
01155     /* Enable EVT, BUF and ERR interrupt */
01156     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01157     }
01158     else
01159     {
01160       /* Wait until TXE flag is set */
01161       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
01162       {
01163         return HAL_TIMEOUT;
01164       }
01165
01166       /* Generate Stop */
01167       hi2c->Instance->CR1 |= I2C_CR1_STOP;
01168
01169       hi2c->State = HAL_I2C_STATE_READY;
01170
01171       /* Process Unlocked */
01172       __HAL_UNLOCK(hi2c);
01173     }
01174
01175     return HAL_OK;
01176   }
01177   else
01178   {
01179     return HAL_BUSY;
01180   }
01181 }
01182
01183 /**
01184   * @brief  Receive in master mode an amount of data in no-blocking mode with Interrupt
01185   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01186   *         the configuration information for I2C module
01187   * @param  DevAddress Target device address
01188   * @param  pData Pointer to data buffer
01189   * @param  Size Amount of data to be sent
01190   * @retval HAL status
01191   */
01192 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01193 {
01194   if(hi2c->State == HAL_I2C_STATE_READY)
01195   {
01196     /* Wait until BUSY flag is reset */
01197     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01198     {
01199       return HAL_BUSY;
01200     }
01201
01202     /* Process Locked */
01203     __HAL_LOCK(hi2c);
01204
01205     /* Disable Pos */
01206     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01207
01208     hi2c->State = HAL_I2C_STATE_BUSY_RX;
01209     hi2c->Mode = HAL_I2C_MODE_MASTER;
01210     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01211
01212     hi2c->pBuffPtr = pData;
01213     hi2c->XferSize = Size;
01214     hi2c->XferCount = Size;
01215     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01216
01217     /* Send Slave Address */
01218     if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
01219     {
01220       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01221       {
01222         /* Process Unlocked */
01223         __HAL_UNLOCK(hi2c);
01224         return HAL_ERROR;
01225       }
01226       else
01227       {
01228         /* Process Unlocked */
01229         __HAL_UNLOCK(hi2c);
01230         return HAL_TIMEOUT;
01231       }
01232     }
01233
01234     if(hi2c->XferCount == 0U)
01235     {
01236       /* Clear ADDR flag */
01237       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01238
01239       /* Generate Stop */
01240       hi2c->Instance->CR1 |= I2C_CR1_STOP;
01241     }
01242     else if(hi2c->XferCount == 1U)
01243     {
01244       /* Disable Acknowledge */
01245       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01246
01247       /* Clear ADDR flag */
01248       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01249
01250       /* Generate Stop */
01251       hi2c->Instance->CR1 |= I2C_CR1_STOP;
01252     }
01253     else if(hi2c->XferCount == 2U)
01254     {
01255       /* Disable Acknowledge */
01256       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01257
01258       /* Enable Pos */
01259       hi2c->Instance->CR1 |= I2C_CR1_POS;
01260
01261       /* Clear ADDR flag */
01262       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01263     }
01264     else
01265     {
01266       /* Enable Acknowledge */
01267       hi2c->Instance->CR1 |= I2C_CR1_ACK;
01268
01269       /* Clear ADDR flag */
01270       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01271     }
01272
01273     if(hi2c->XferCount == 0U)
01274     {
01275       hi2c->State = HAL_I2C_STATE_READY;
01276     }
01277
01278     /* Process Unlocked */
01279     __HAL_UNLOCK(hi2c);
01280
01281     if(hi2c->XferCount > 0U)
01282     {
01283     /* Note : The I2C interrupts must be enabled after unlocking current process
01284               to avoid the risk of I2C interrupt handle execution before current
01285               process unlock */
01286
01287     /* Enable EVT, BUF and ERR interrupt */
01288     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01289     }
01290     return HAL_OK;
01291   }
01292   else
01293   {
01294     return HAL_BUSY;
01295   }
01296 }
01297
01298 /**
01299   * @brief  Sequential transmit in master mode an amount of data in no-blocking mode with Interrupt
01300   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01301   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01302   *         the configuration information for I2C module
01303   * @param  DevAddress Target device address
01304   * @param  pData Pointer to data buffer
01305   * @param  Size Amount of data to be sent
01306   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01307   * @retval HAL status
01308   */
01309 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01310 {
01311   /* Check the parameters */
01312   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01313
01314   if(hi2c->State == HAL_I2C_STATE_READY)
01315   {
01316     /* Check Busy Flag only if FIRST call of Master interface */
01317     if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
01318     {
01319       /* Wait until BUSY flag is reset */
01320       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01321       {
01322         return HAL_BUSY;
01323       }
01324     }
01325
01326     /* Process Locked */
01327     __HAL_LOCK(hi2c);
01328
01329     /* Disable Pos */
01330     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01331
01332     hi2c->State = HAL_I2C_STATE_BUSY_TX;
01333     hi2c->Mode = HAL_I2C_MODE_MASTER;
01334     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01335
01336     hi2c->pBuffPtr = pData;
01337     hi2c->XferSize = Size;
01338     hi2c->XferCount = Size;
01339     hi2c->XferOptions = XferOptions;
01340
01341     if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) || (hi2c->PreviousState == I2C_STATE_NONE))
01342     {
01343       /* Send Slave Address */
01344       if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
01345       {
01346         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01347         {
01348           /* Process Unlocked */
01349           __HAL_UNLOCK(hi2c);
01350           return HAL_ERROR;
01351         }
01352         else
01353         {
01354           /* Process Unlocked */
01355           __HAL_UNLOCK(hi2c);
01356           return HAL_TIMEOUT;
01357         }
01358       }
01359
01360       /* Clear ADDR flag */
01361       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01362     }
01363
01364     if(hi2c->XferSize > 0U)
01365     {
01366     /* Process Unlocked */
01367     __HAL_UNLOCK(hi2c);
01368
01369     /* Note : The I2C interrupts must be enabled after unlocking current process
01370               to avoid the risk of I2C interrupt handle execution before current
01371               process unlock */
01372
01373     /* Enable EVT, BUF and ERR interrupt */
01374     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01375     }
01376     else
01377     {
01378       /* Wait until TXE flag is set */
01379       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
01380       {
01381         return HAL_TIMEOUT;
01382       }
01383
01384       /* Generate Stop */
01385       hi2c->Instance->CR1 |= I2C_CR1_STOP;
01386
01387       hi2c->State = HAL_I2C_STATE_READY;
01388       /* Process Unlocked */
01389       __HAL_UNLOCK(hi2c);
01390     }
01391
01392     return HAL_OK;
01393   }
01394   else
01395   {
01396     return HAL_BUSY;
01397   }
01398 }
01399
01400 /**
01401   * @brief  Sequential receive in master mode an amount of data in no-blocking mode with Interrupt
01402   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01403   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01404   *         the configuration information for I2C module
01405   * @param  DevAddress Target device address
01406   * @param  pData Pointer to data buffer
01407   * @param  Size Amount of data to be sent
01408   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01409   * @retval HAL status
01410   */
01411 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01412 {
01413   /* Check the parameters */
01414   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01415
01416   if(hi2c->State == HAL_I2C_STATE_READY)
01417   {
01418     /* Check Busy Flag only if FIRST call of Master interface */
01419     if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
01420     {
01421       /* Wait until BUSY flag is reset */
01422       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01423       {
01424         return HAL_BUSY;
01425       }
01426     }
01427
01428     /* Process Locked */
01429     __HAL_LOCK(hi2c);
01430
01431     /* Disable Pos */
01432     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01433
01434     hi2c->State = HAL_I2C_STATE_BUSY_RX;
01435     hi2c->Mode = HAL_I2C_MODE_MASTER;
01436     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01437
01438     hi2c->pBuffPtr = pData;
01439     hi2c->XferSize = Size;
01440     hi2c->XferCount = Size;
01441     hi2c->XferOptions = XferOptions;
01442
01443     if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
01444     {
01445       /* Send Slave Address */
01446       if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
01447       {
01448         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01449         {
01450           /* Process Unlocked */
01451           __HAL_UNLOCK(hi2c);
01452           return HAL_ERROR;
01453         }
01454         else
01455         {
01456           /* Process Unlocked */
01457           __HAL_UNLOCK(hi2c);
01458           return HAL_TIMEOUT;
01459         }
01460       }
01461     }
01462
01463     if(hi2c->XferCount == 0U)
01464     {
01465       /* Clear ADDR flag */
01466       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01467
01468       /* Generate Stop */
01469       hi2c->Instance->CR1 |= I2C_CR1_STOP;
01470
01471       hi2c->State = HAL_I2C_STATE_READY;
01472     }
01473     else if(hi2c->XferCount == 1U)
01474     {
01475       /* Prepare next transfer or stop current transfer */
01476       if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->PreviousState != I2C_STATE_MASTER_BUSY_RX))
01477       {
01478         if(hi2c->XferOptions != I2C_NEXT_FRAME)
01479         {
01480           /* Disable Acknowledge */
01481           hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01482         }
01483         else
01484         {
01485           /* Enable Acknowledge */
01486           hi2c->Instance->CR1 |= I2C_CR1_ACK;
01487         }
01488
01489         /* Clear ADDR flag */
01490         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01491       }
01492       else
01493       {
01494         /* Disable Acknowledge */
01495         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01496
01497         /* Clear ADDR flag */
01498         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01499
01500         /* Generate Stop */
01501         hi2c->Instance->CR1 |= I2C_CR1_STOP;
01502       }
01503     }
01504     else if(hi2c->XferCount == 2U)
01505     {
01506       if(hi2c->XferOptions != I2C_NEXT_FRAME)
01507       {
01508         /* Disable Acknowledge */
01509         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01510
01511         /* Enable Pos */
01512         hi2c->Instance->CR1 |= I2C_CR1_POS;
01513       }
01514       else
01515       {
01516         /* Enable Acknowledge */
01517         hi2c->Instance->CR1 |= I2C_CR1_ACK;
01518       }
01519
01520       /* Clear ADDR flag */
01521       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01522     }
01523     else
01524     {
01525       /* Enable Acknowledge */
01526       hi2c->Instance->CR1 |= I2C_CR1_ACK;
01527
01528       /* Clear ADDR flag */
01529       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01530     }
01531
01532     /* Process Unlocked */
01533     __HAL_UNLOCK(hi2c);
01534
01535     if(hi2c->XferCount > 0U)
01536     {
01537     /* Note : The I2C interrupts must be enabled after unlocking current process
01538               to avoid the risk of I2C interrupt handle execution before current
01539               process unlock */
01540
01541     /* Enable EVT, BUF and ERR interrupt */
01542     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01543     }
01544     return HAL_OK;
01545   }
01546   else
01547   {
01548     return HAL_BUSY;
01549   }
01550 }
01551
01552 /**
01553   * @brief  Transmit in slave mode an amount of data in no-blocking mode with Interrupt
01554   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01555   *         the configuration information for I2C module
01556   * @param  pData Pointer to data buffer
01557   * @param  Size Amount of data to be sent
01558   * @retval HAL status
01559   */
01560 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01561 {
01562   if(hi2c->State == HAL_I2C_STATE_READY)
01563   {
01564     if((pData == NULL) || (Size == 0U))
01565     {
01566       return  HAL_ERROR;
01567     }
01568
01569     /* Wait until BUSY flag is reset */
01570     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01571     {
01572       return HAL_BUSY;
01573     }
01574
01575     /* Process Locked */
01576     __HAL_LOCK(hi2c);
01577
01578     /* Disable Pos */
01579     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01580
01581     hi2c->State = HAL_I2C_STATE_BUSY_TX;
01582     hi2c->Mode = HAL_I2C_MODE_SLAVE;
01583     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01584
01585     hi2c->pBuffPtr = pData;
01586     hi2c->XferSize = Size;
01587     hi2c->XferCount = Size;
01588     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01589
01590     /* Enable Address Acknowledge */
01591     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01592
01593     /* Process Unlocked */
01594     __HAL_UNLOCK(hi2c);
01595
01596     /* Note : The I2C interrupts must be enabled after unlocking current process
01597               to avoid the risk of I2C interrupt handle execution before current
01598               process unlock */
01599
01600     /* Enable EVT, BUF and ERR interrupt */
01601     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01602
01603     return HAL_OK;
01604   }
01605   else
01606   {
01607     return HAL_BUSY;
01608   }
01609 }
01610
01611 /**
01612   * @brief  Receive in slave mode an amount of data in no-blocking mode with Interrupt
01613   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01614   *         the configuration information for I2C module
01615   * @param  pData Pointer to data buffer
01616   * @param  Size Amount of data to be sent
01617   * @retval HAL status
01618   */
01619 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01620 {
01621   if(hi2c->State == HAL_I2C_STATE_READY)
01622   {
01623     if((pData == NULL) || (Size == 0U))
01624     {
01625       return  HAL_ERROR;
01626     }
01627
01628     /* Wait until BUSY flag is reset */
01629     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01630     {
01631       return HAL_BUSY;
01632     }
01633
01634     /* Process Locked */
01635     __HAL_LOCK(hi2c);
01636
01637     /* Disable Pos */
01638     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01639
01640     hi2c->State = HAL_I2C_STATE_BUSY_RX;
01641     hi2c->Mode = HAL_I2C_MODE_SLAVE;
01642     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01643
01644     hi2c->pBuffPtr = pData;
01645     hi2c->XferSize = Size;
01646     hi2c->XferCount = Size;
01647     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01648
01649     /* Enable Address Acknowledge */
01650     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01651
01652     /* Process Unlocked */
01653     __HAL_UNLOCK(hi2c);
01654
01655     /* Note : The I2C interrupts must be enabled after unlocking current process
01656               to avoid the risk of I2C interrupt handle execution before current
01657               process unlock */
01658
01659     /* Enable EVT, BUF and ERR interrupt */
01660     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01661
01662     return HAL_OK;
01663   }
01664   else
01665   {
01666     return HAL_BUSY;
01667   }
01668 }
01669
01670 /**
01671   * @brief  Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
01672   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01673   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01674   *         the configuration information for I2C module
01675   * @param  pData Pointer to data buffer
01676   * @param  Size Amount of data to be sent
01677   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01678   * @retval HAL status
01679   */
01680 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01681 {
01682   /* Check the parameters */
01683   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01684
01685   if(hi2c->State == HAL_I2C_STATE_LISTEN)
01686   {
01687     if((pData == NULL) || (Size == 0U))
01688     {
01689       return  HAL_ERROR;
01690     }
01691
01692     /* Process Locked */
01693     __HAL_LOCK(hi2c);
01694
01695     /* Disable Pos */
01696     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01697
01698     hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
01699     hi2c->Mode = HAL_I2C_MODE_SLAVE;
01700     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01701
01702     hi2c->pBuffPtr = pData;
01703     hi2c->XferSize = Size;
01704     hi2c->XferCount = Size;
01705     hi2c->XferOptions = XferOptions;
01706
01707     /* Clear ADDR flag */
01708     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01709
01710     /* Process Unlocked */
01711     __HAL_UNLOCK(hi2c);
01712
01713     /* Note : The I2C interrupts must be enabled after unlocking current process
01714               to avoid the risk of I2C interrupt handle execution before current
01715               process unlock */
01716
01717     /* Enable EVT, BUF and ERR interrupt */
01718     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01719
01720     return HAL_OK;
01721   }
01722   else
01723   {
01724     return HAL_BUSY;
01725   }
01726 }
01727
01728 /**
01729   * @brief  Sequential receive in slave mode an amount of data in no-blocking mode with Interrupt
01730   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01731   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01732   *         the configuration information for I2C module
01733   * @param  pData Pointer to data buffer
01734   * @param  Size Amount of data to be sent
01735   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01736   * @retval HAL status
01737   */
01738 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01739 {
01740   /* Check the parameters */
01741   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01742
01743   if(hi2c->State == HAL_I2C_STATE_LISTEN)
01744   {
01745     if((pData == NULL) || (Size == 0U))
01746     {
01747       return  HAL_ERROR;
01748     }
01749
01750     /* Process Locked */
01751     __HAL_LOCK(hi2c);
01752
01753     /* Disable Pos */
01754     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01755
01756     hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
01757     hi2c->Mode = HAL_I2C_MODE_SLAVE;
01758     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01759
01760     hi2c->pBuffPtr = pData;
01761     hi2c->XferSize = Size;
01762     hi2c->XferCount = Size;
01763     hi2c->XferOptions = XferOptions;
01764
01765     /* Clear ADDR flag */
01766     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01767
01768     /* Process Unlocked */
01769     __HAL_UNLOCK(hi2c);
01770
01771     /* Note : The I2C interrupts must be enabled after unlocking current process
01772               to avoid the risk of I2C interrupt handle execution before current
01773               process unlock */
01774
01775     /* Enable EVT, BUF and ERR interrupt */
01776     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01777
01778     return HAL_OK;
01779   }
01780   else
01781   {
01782     return HAL_BUSY;
01783   }
01784 }
01785
01786 /**
01787   * @brief  Enable the Address listen mode with Interrupt.
01788   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01789   *                the configuration information for the specified I2C.
01790   * @retval HAL status
01791   */
01792 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
01793 {
01794   if(hi2c->State == HAL_I2C_STATE_READY)
01795   {
01796     hi2c->State = HAL_I2C_STATE_LISTEN;
01797
01798     /* Enable Address Acknowledge */
01799     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01800
01801     /* Enable EVT and ERR interrupt */
01802     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
01803
01804     return HAL_OK;
01805   }
01806   else
01807   {
01808     return HAL_BUSY;
01809   }
01810 }
01811
01812 /**
01813   * @brief  Disable the Address listen mode with Interrupt.
01814   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01815   *                the configuration information for the specified I2C.
01816   * @retval HAL status
01817   */
01818 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
01819 {
01820   /* Declaration of tmp to prevent undefined behavior of volatile usage */
01821   uint32_t tmp;
01822
01823   /* Disable Address listen mode only if a transfer is not ongoing */
01824   if(hi2c->State == HAL_I2C_STATE_LISTEN)
01825   {
01826     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
01827     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
01828     hi2c->State = HAL_I2C_STATE_READY;
01829     hi2c->Mode = HAL_I2C_MODE_NONE;
01830
01831     /* Disable Address Acknowledge */
01832     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01833
01834     /* Disable EVT and ERR interrupt */
01835     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
01836
01837     return HAL_OK;
01838   }
01839   else
01840   {
01841     return HAL_BUSY;
01842   }
01843 }
01844
01845 /**
01846   * @brief  Transmit in master mode an amount of data in no-blocking mode with DMA
01847   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01848   *         the configuration information for I2C module
01849   * @param  DevAddress Target device address
01850   * @param  pData Pointer to data buffer
01851   * @param  Size Amount of data to be sent
01852   * @retval HAL status
01853   */
01854 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01855 {
01856   if(hi2c->State == HAL_I2C_STATE_READY)
01857   {
01858     /* Wait until BUSY flag is reset */
01859     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01860     {
01861       return HAL_BUSY;
01862     }
01863
01864     /* Process Locked */
01865     __HAL_LOCK(hi2c);
01866
01867     /* Disable Pos */
01868     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01869
01870     hi2c->State = HAL_I2C_STATE_BUSY_TX;
01871     hi2c->Mode = HAL_I2C_MODE_MASTER;
01872     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01873
01874     hi2c->pBuffPtr = pData;
01875     hi2c->XferSize = Size;
01876     hi2c->XferCount = Size;
01877     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01878
01879     if(hi2c->XferSize > 0U)
01880     {
01881     /* Set the I2C DMA transfer complete callback */
01882     hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01883
01884     /* Set the DMA error callback */
01885     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01886
01887     /* Enable the DMA Stream */
01888     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
01889
01890     /* Send Slave Address */
01891     if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
01892     {
01893       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01894       {
01895         /* Process Unlocked */
01896         __HAL_UNLOCK(hi2c);
01897         return HAL_ERROR;
01898       }
01899       else
01900       {
01901         /* Process Unlocked */
01902         __HAL_UNLOCK(hi2c);
01903         return HAL_TIMEOUT;
01904       }
01905     }
01906
01907     /* Enable DMA Request */
01908     hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
01909
01910     /* Clear ADDR flag */
01911     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01912     }
01913     else
01914     {
01915       /* Send Slave Address */
01916       if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
01917       {
01918         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01919         {
01920           /* Process Unlocked */
01921           __HAL_UNLOCK(hi2c);
01922           return HAL_ERROR;
01923         }
01924         else
01925         {
01926           /* Process Unlocked */
01927           __HAL_UNLOCK(hi2c);
01928           return HAL_TIMEOUT;
01929         }
01930       }
01931
01932       /* Clear ADDR flag */
01933       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01934
01935       /* Wait until TXE flag is set */
01936       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
01937       {
01938         return HAL_TIMEOUT;
01939       }
01940
01941       /* Generate Stop */
01942       hi2c->Instance->CR1 |= I2C_CR1_STOP;
01943
01944       hi2c->State = HAL_I2C_STATE_READY;
01945     }
01946
01947     /* Process Unlocked */
01948     __HAL_UNLOCK(hi2c);
01949
01950     return HAL_OK;
01951   }
01952   else
01953   {
01954     return HAL_BUSY;
01955   }
01956 }
01957
01958 /**
01959   * @brief  Receive in master mode an amount of data in no-blocking mode with DMA
01960   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01961   *         the configuration information for I2C module
01962   * @param  DevAddress Target device address
01963   * @param  pData Pointer to data buffer
01964   * @param  Size Amount of data to be sent
01965   * @retval HAL status
01966   */
01967 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01968 {
01969   if(hi2c->State == HAL_I2C_STATE_READY)
01970   {
01971     /* Wait until BUSY flag is reset */
01972     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
01973     {
01974       return HAL_BUSY;
01975     }
01976
01977     /* Process Locked */
01978     __HAL_LOCK(hi2c);
01979
01980     /* Disable Pos */
01981     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01982
01983     hi2c->State = HAL_I2C_STATE_BUSY_RX;
01984     hi2c->Mode = HAL_I2C_MODE_MASTER;
01985     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01986
01987     hi2c->pBuffPtr = pData;
01988     hi2c->XferSize = Size;
01989     hi2c->XferCount = Size;
01990     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01991
01992     if(hi2c->XferSize > 0U)
01993     {
01994       /* Set the I2C DMA transfer complete callback */
01995       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01996
01997       /* Set the DMA error callback */
01998       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01999
02000       /* Enable the DMA Stream */
02001       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
02002
02003       /* Send Slave Address */
02004       if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
02005       {
02006         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02007         {
02008           /* Process Unlocked */
02009           __HAL_UNLOCK(hi2c);
02010           return HAL_ERROR;
02011         }
02012         else
02013         {
02014           /* Process Unlocked */
02015           __HAL_UNLOCK(hi2c);
02016           return HAL_TIMEOUT;
02017         }
02018       }
02019
02020       if(Size == 1U)
02021       {
02022         /* Disable Acknowledge */
02023         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02024       }
02025       else
02026       {
02027         /* Enable Last DMA bit */
02028         hi2c->Instance->CR2 |= I2C_CR2_LAST;
02029       }
02030
02031       /* Enable DMA Request */
02032       hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02033
02034       /* Clear ADDR flag */
02035       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02036     }
02037     else
02038     {
02039       /* Send Slave Address */
02040       if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
02041       {
02042         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02043         {
02044           /* Process Unlocked */
02045           __HAL_UNLOCK(hi2c);
02046           return HAL_ERROR;
02047         }
02048         else
02049         {
02050           /* Process Unlocked */
02051           __HAL_UNLOCK(hi2c);
02052           return HAL_TIMEOUT;
02053         }
02054       }
02055
02056       /* Clear ADDR flag */
02057       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02058
02059       /* Generate Stop */
02060       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02061
02062       hi2c->State = HAL_I2C_STATE_READY;
02063     }
02064
02065     /* Process Unlocked */
02066     __HAL_UNLOCK(hi2c);
02067
02068     return HAL_OK;
02069   }
02070   else
02071   {
02072     return HAL_BUSY;
02073   }
02074 }
02075
02076 /**
02077   * @brief  Abort a master I2C process communication with Interrupt.
02078   * @note   This abort can be called only if state is ready
02079   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02080   *                the configuration information for the specified I2C.
02081   * @param  DevAddress Target device address
02082   * @retval HAL status
02083   */
02084 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
02085 {
02086   /* Abort Master transfer during Receive or Transmit process    */
02087   /* Or after an error during during Receive or Transmit process */
02088   if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \
02089      ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) && ((hi2c->PreviousState & ((uint32_t)HAL_I2C_MODE_MASTER)) == HAL_I2C_MODE_MASTER)))
02090   {
02091     /* Process Locked */
02092     __HAL_LOCK(hi2c);
02093
02094     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02095
02096     /* Disable Acknowledge */
02097     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02098
02099     /* Generate Stop */
02100     hi2c->Instance->CR1 |= I2C_CR1_STOP;
02101
02102     hi2c->XferCount = 0U;
02103
02104     /* Disable EVT, BUF and ERR interrupt */
02105     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02106
02107     hi2c->PreviousState = I2C_STATE_NONE;
02108     hi2c->State = HAL_I2C_STATE_READY;
02109
02110     /* Process Unlocked */
02111     __HAL_UNLOCK(hi2c);
02112
02113     /* Call Complete Callback */
02114     return HAL_OK;
02115   }
02116   else
02117   {
02118     /* Wrong usage of abort function */
02119     /* This function should be used only in case of abort monitored by master device */
02120     return HAL_ERROR;
02121   }
02122 }
02123
02124 /**
02125   * @brief  Transmit in slave mode an amount of data in no-blocking mode with DMA
02126   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02127   *         the configuration information for I2C module
02128   * @param  pData Pointer to data buffer
02129   * @param  Size Amount of data to be sent
02130   * @retval HAL status
02131   */
02132 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02133 {
02134   if(hi2c->State == HAL_I2C_STATE_READY)
02135   {
02136     if((pData == NULL) || (Size == 0U))
02137     {
02138       return  HAL_ERROR;
02139     }
02140
02141     /* Wait until BUSY flag is reset */
02142     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02143     {
02144       return HAL_BUSY;
02145     }
02146
02147     /* Process Locked */
02148     __HAL_LOCK(hi2c);
02149
02150     /* Disable Pos */
02151     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02152
02153     hi2c->State = HAL_I2C_STATE_BUSY_TX;
02154     hi2c->Mode = HAL_I2C_MODE_SLAVE;
02155     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02156
02157     hi2c->pBuffPtr = pData;
02158     hi2c->XferSize = Size;
02159     hi2c->XferCount = Size;
02160     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02161
02162     /* Set the I2C DMA transfer complete callback */
02163     hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
02164
02165     /* Set the DMA error callback */
02166     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02167
02168     /* Enable the DMA Stream */
02169     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
02170
02171     /* Enable DMA Request */
02172     hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02173
02174     /* Enable Address Acknowledge */
02175     hi2c->Instance->CR1 |= I2C_CR1_ACK;
02176
02177     /* Wait until ADDR flag is set */
02178     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
02179     {
02180       return HAL_TIMEOUT;
02181     }
02182
02183     /* If 7bit addressing mode is selected */
02184     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
02185     {
02186       /* Clear ADDR flag */
02187       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02188     }
02189     else
02190     {
02191       /* Clear ADDR flag */
02192       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02193
02194       /* Wait until ADDR flag is set */
02195       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
02196       {
02197         return HAL_TIMEOUT;
02198       }
02199
02200       /* Clear ADDR flag */
02201       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02202     }
02203
02204     /* Process Unlocked */
02205     __HAL_UNLOCK(hi2c);
02206
02207     return HAL_OK;
02208   }
02209   else
02210   {
02211     return HAL_BUSY;
02212   }
02213 }
02214
02215 /**
02216   * @brief  Receive in slave mode an amount of data in no-blocking mode with DMA
02217   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02218   *         the configuration information for I2C module
02219   * @param  pData Pointer to data buffer
02220   * @param  Size Amount of data to be sent
02221   * @retval HAL status
02222   */
02223 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02224 {
02225   if(hi2c->State == HAL_I2C_STATE_READY)
02226   {
02227     if((pData == NULL) || (Size == 0U))
02228     {
02229       return  HAL_ERROR;
02230     }
02231
02232     /* Wait until BUSY flag is reset */
02233     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02234     {
02235       return HAL_BUSY;
02236     }
02237
02238     /* Process Locked */
02239     __HAL_LOCK(hi2c);
02240
02241     /* Disable Pos */
02242     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02243
02244     hi2c->State = HAL_I2C_STATE_BUSY_RX;
02245     hi2c->Mode = HAL_I2C_MODE_SLAVE;
02246     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02247
02248     hi2c->pBuffPtr = pData;
02249     hi2c->XferSize = Size;
02250     hi2c->XferCount = Size;
02251     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02252
02253     /* Set the I2C DMA transfer complete callback */
02254     hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
02255
02256     /* Set the DMA error callback */
02257     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02258
02259     /* Enable the DMA Stream */
02260     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
02261
02262     /* Enable DMA Request */
02263     hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02264
02265     /* Enable Address Acknowledge */
02266     hi2c->Instance->CR1 |= I2C_CR1_ACK;
02267
02268     /* Wait until ADDR flag is set */
02269     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
02270     {
02271       return HAL_TIMEOUT;
02272     }
02273
02274     /* Clear ADDR flag */
02275     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02276
02277     /* Process Unlocked */
02278     __HAL_UNLOCK(hi2c);
02279
02280     return HAL_OK;
02281   }
02282   else
02283   {
02284     return HAL_BUSY;
02285   }
02286 }
02287 /**
02288   * @brief  Write an amount of data in blocking mode to a specific memory address
02289   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02290   *         the configuration information for I2C module
02291   * @param  DevAddress Target device address
02292   * @param  MemAddress Internal memory address
02293   * @param  MemAddSize Size of internal memory address
02294   * @param  pData Pointer to data buffer
02295   * @param  Size Amount of data to be sent
02296   * @param  Timeout Timeout duration
02297   * @retval HAL status
02298   */
02299 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02300 {
02301   /* Check the parameters */
02302   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02303
02304   if(hi2c->State == HAL_I2C_STATE_READY)
02305   {
02306     /* Wait until BUSY flag is reset */
02307     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02308     {
02309       return HAL_BUSY;
02310     }
02311
02312     /* Process Locked */
02313     __HAL_LOCK(hi2c);
02314
02315     /* Disable Pos */
02316     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02317
02318     hi2c->State = HAL_I2C_STATE_BUSY_TX;
02319     hi2c->Mode = HAL_I2C_MODE_MEM;
02320     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02321     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02322
02323     /* Send Slave Address and Memory Address */
02324     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
02325     {
02326       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02327       {
02328         /* Process Unlocked */
02329         __HAL_UNLOCK(hi2c);
02330         return HAL_ERROR;
02331       }
02332       else
02333       {
02334         /* Process Unlocked */
02335         __HAL_UNLOCK(hi2c);
02336         return HAL_TIMEOUT;
02337       }
02338     }
02339
02340     while(Size > 0U)
02341     {
02342       /* Wait until TXE flag is set */
02343       if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
02344       {
02345         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02346         {
02347           /* Generate Stop */
02348           hi2c->Instance->CR1 |= I2C_CR1_STOP;
02349           return HAL_ERROR;
02350         }
02351         else
02352         {
02353           return HAL_TIMEOUT;
02354         }
02355       }
02356
02357       /* Write data to DR */
02358       hi2c->Instance->DR = (*pData++);
02359       Size--;
02360
02361       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
02362       {
02363         /* Write data to DR */
02364         hi2c->Instance->DR = (*pData++);
02365         Size--;
02366       }
02367     }
02368
02369     /* Wait until TXE flag is set */
02370     if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
02371     {
02372       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02373       {
02374         /* Generate Stop */
02375         hi2c->Instance->CR1 |= I2C_CR1_STOP;
02376         return HAL_ERROR;
02377       }
02378       else
02379       {
02380         return HAL_TIMEOUT;
02381       }
02382     }
02383
02384     /* Generate Stop */
02385     hi2c->Instance->CR1 |= I2C_CR1_STOP;
02386
02387     hi2c->State = HAL_I2C_STATE_READY;
02388     hi2c->Mode = HAL_I2C_MODE_NONE;
02389
02390     /* Process Unlocked */
02391     __HAL_UNLOCK(hi2c);
02392
02393     return HAL_OK;
02394   }
02395   else
02396   {
02397     return HAL_BUSY;
02398   }
02399 }
02400
02401 /**
02402   * @brief  Read an amount of data in blocking mode from a specific memory address
02403   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02404   *         the configuration information for I2C module
02405   * @param  DevAddress Target device address
02406   * @param  MemAddress Internal memory address
02407   * @param  MemAddSize Size of internal memory address
02408   * @param  pData Pointer to data buffer
02409   * @param  Size Amount of data to be sent
02410   * @param  Timeout Timeout duration
02411   * @retval HAL status
02412   */
02413 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02414 {
02415   /* Check the parameters */
02416   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02417
02418   if(hi2c->State == HAL_I2C_STATE_READY)
02419   {
02420     /* Wait until BUSY flag is reset */
02421     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02422     {
02423       return HAL_BUSY;
02424     }
02425
02426     /* Process Locked */
02427     __HAL_LOCK(hi2c);
02428
02429     /* Disable Pos */
02430     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02431
02432     hi2c->State = HAL_I2C_STATE_BUSY_RX;
02433     hi2c->Mode = HAL_I2C_MODE_MEM;
02434     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02435     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02436
02437     /* Send Slave Address and Memory Address */
02438     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
02439     {
02440       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02441       {
02442         /* Process Unlocked */
02443         __HAL_UNLOCK(hi2c);
02444         return HAL_ERROR;
02445       }
02446       else
02447       {
02448         /* Process Unlocked */
02449         __HAL_UNLOCK(hi2c);
02450         return HAL_TIMEOUT;
02451       }
02452     }
02453
02454     if(Size == 0U)
02455     {
02456       /* Clear ADDR flag */
02457       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02458
02459       /* Generate Stop */
02460       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02461     }
02462     else if(Size == 1U)
02463     {
02464       /* Disable Acknowledge */
02465       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02466
02467       /* Clear ADDR flag */
02468       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02469
02470       /* Generate Stop */
02471       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02472     }
02473     else if(Size == 2U)
02474     {
02475       /* Disable Acknowledge */
02476       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02477
02478       /* Enable Pos */
02479       hi2c->Instance->CR1 |= I2C_CR1_POS;
02480
02481       /* Clear ADDR flag */
02482       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02483     }
02484     else
02485     {
02486       /* Clear ADDR flag */
02487       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02488     }
02489
02490     while(Size > 0U)
02491     {
02492       if(Size <= 3U)
02493       {
02494         /* One byte */
02495         if(Size== 1U)
02496         {
02497           /* Wait until RXNE flag is set */
02498           if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
02499           {
02500             if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
02501             {
02502               return HAL_TIMEOUT;
02503             }
02504             else
02505             {
02506               return HAL_ERROR;
02507             }
02508           }
02509
02510           /* Read data from DR */
02511           (*pData++) = hi2c->Instance->DR;
02512           Size--;
02513         }
02514         /* Two bytes */
02515         else if(Size == 2U)
02516         {
02517           /* Wait until BTF flag is set */
02518           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
02519           {
02520             return HAL_TIMEOUT;
02521           }
02522
02523           /* Generate Stop */
02524           hi2c->Instance->CR1 |= I2C_CR1_STOP;
02525
02526           /* Read data from DR */
02527           (*pData++) = hi2c->Instance->DR;
02528           Size--;
02529
02530           /* Read data from DR */
02531           (*pData++) = hi2c->Instance->DR;
02532           Size--;
02533         }
02534         /* 3 Last bytes */
02535         else
02536         {
02537           /* Wait until BTF flag is set */
02538           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
02539           {
02540             return HAL_TIMEOUT;
02541           }
02542
02543           /* Disable Acknowledge */
02544           hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02545
02546           /* Read data from DR */
02547           (*pData++) = hi2c->Instance->DR;
02548           Size--;
02549
02550           /* Wait until BTF flag is set */
02551           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
02552           {
02553             return HAL_TIMEOUT;
02554           }
02555
02556           /* Generate Stop */
02557           hi2c->Instance->CR1 |= I2C_CR1_STOP;
02558
02559           /* Read data from DR */
02560           (*pData++) = hi2c->Instance->DR;
02561           Size--;
02562
02563           /* Read data from DR */
02564           (*pData++) = hi2c->Instance->DR;
02565           Size--;
02566         }
02567       }
02568       else
02569       {
02570         /* Wait until RXNE flag is set */
02571         if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
02572         {
02573           if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
02574           {
02575             return HAL_TIMEOUT;
02576           }
02577           else
02578           {
02579             return HAL_ERROR;
02580           }
02581         }
02582
02583         /* Read data from DR */
02584         (*pData++) = hi2c->Instance->DR;
02585         Size--;
02586
02587         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
02588         {
02589           /* Read data from DR */
02590           (*pData++) = hi2c->Instance->DR;
02591           Size--;
02592         }
02593       }
02594     }
02595
02596     hi2c->State = HAL_I2C_STATE_READY;
02597     hi2c->Mode = HAL_I2C_MODE_NONE;
02598
02599     /* Process Unlocked */
02600     __HAL_UNLOCK(hi2c);
02601
02602     return HAL_OK;
02603   }
02604   else
02605   {
02606     return HAL_BUSY;
02607   }
02608 }
02609 /**
02610   * @brief  Write an amount of data in no-blocking mode with Interrupt to a specific memory address
02611   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02612   *         the configuration information for I2C module
02613   * @param  DevAddress Target device address
02614   * @param  MemAddress Internal memory address
02615   * @param  MemAddSize Size of internal memory address
02616   * @param  pData Pointer to data buffer
02617   * @param  Size Amount of data to be sent
02618   * @retval HAL status
02619   */
02620 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02621 {
02622   /* Check the parameters */
02623   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02624
02625   if(hi2c->State == HAL_I2C_STATE_READY)
02626   {
02627     /* Wait until BUSY flag is reset */
02628     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02629     {
02630       return HAL_BUSY;
02631     }
02632
02633     /* Process Locked */
02634     __HAL_LOCK(hi2c);
02635
02636     /* Disable Pos */
02637     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02638
02639     hi2c->State = HAL_I2C_STATE_BUSY_TX;
02640     hi2c->Mode = HAL_I2C_MODE_MEM;
02641     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02642
02643     hi2c->pBuffPtr = pData;
02644     hi2c->XferSize = Size;
02645     hi2c->XferCount = Size;
02646     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02647
02648     /* Send Slave Address and Memory Address */
02649     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
02650     {
02651       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02652       {
02653         /* Process Unlocked */
02654         __HAL_UNLOCK(hi2c);
02655         return HAL_ERROR;
02656       }
02657       else
02658       {
02659         /* Process Unlocked */
02660         __HAL_UNLOCK(hi2c);
02661         return HAL_TIMEOUT;
02662       }
02663     }
02664
02665     if(hi2c->XferSize > 0U)
02666     {
02667       /* Process Unlocked */
02668       __HAL_UNLOCK(hi2c);
02669
02670       /* Note : The I2C interrupts must be enabled after unlocking current process
02671       to avoid the risk of I2C interrupt handle execution before current
02672       process unlock */
02673
02674       /* Enable EVT, BUF and ERR interrupt */
02675       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02676     }
02677     else
02678     {
02679       /* Wait until TXE flag is set */
02680       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
02681       {
02682         return HAL_TIMEOUT;
02683       }
02684
02685       /* Generate Stop */
02686       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02687
02688       hi2c->State = HAL_I2C_STATE_READY;
02689
02690       /* Process Unlocked */
02691       __HAL_UNLOCK(hi2c);
02692     }
02693     return HAL_OK;
02694   }
02695   else
02696   {
02697     return HAL_BUSY;
02698   }
02699 }
02700
02701 /**
02702   * @brief  Read an amount of data in no-blocking mode with Interrupt from a specific memory address
02703   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02704   *         the configuration information for I2C module
02705   * @param  DevAddress Target device address
02706   * @param  MemAddress Internal memory address
02707   * @param  MemAddSize Size of internal memory address
02708   * @param  pData Pointer to data buffer
02709   * @param  Size Amount of data to be sent
02710   * @retval HAL status
02711   */
02712 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02713 {
02714   /* Check the parameters */
02715   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02716
02717   if(hi2c->State == HAL_I2C_STATE_READY)
02718   {
02719     /* Wait until BUSY flag is reset */
02720     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02721     {
02722       return HAL_BUSY;
02723     }
02724
02725     /* Process Locked */
02726     __HAL_LOCK(hi2c);
02727
02728     /* Disable Pos */
02729     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02730
02731     hi2c->State = HAL_I2C_STATE_BUSY_RX;
02732     hi2c->Mode = HAL_I2C_MODE_MEM;
02733     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02734
02735     hi2c->pBuffPtr = pData;
02736     hi2c->XferSize = Size;
02737     hi2c->XferCount = Size;
02738     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02739
02740     /* Send Slave Address and Memory Address */
02741     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
02742     {
02743       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02744       {
02745         /* Process Unlocked */
02746         __HAL_UNLOCK(hi2c);
02747         return HAL_ERROR;
02748       }
02749       else
02750       {
02751         /* Process Unlocked */
02752         __HAL_UNLOCK(hi2c);
02753         return HAL_TIMEOUT;
02754       }
02755     }
02756
02757     if(hi2c->XferCount == 0U)
02758     {
02759       /* Clear ADDR flag */
02760       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02761
02762       /* Generate Stop */
02763       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02764     }
02765     else if(hi2c->XferCount == 1U)
02766     {
02767       /* Disable Acknowledge */
02768       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02769
02770       /* Clear ADDR flag */
02771       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02772
02773       /* Generate Stop */
02774       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02775     }
02776     else if(hi2c->XferCount == 2U)
02777     {
02778       /* Disable Acknowledge */
02779       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02780
02781       /* Enable Pos */
02782       hi2c->Instance->CR1 |= I2C_CR1_POS;
02783
02784       /* Clear ADDR flag */
02785       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02786     }
02787     else
02788     {
02789       /* Enable Acknowledge */
02790       hi2c->Instance->CR1 |= I2C_CR1_ACK;
02791
02792       /* Clear ADDR flag */
02793       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02794     }
02795
02796     if(hi2c->XferCount == 0U)
02797     {
02798       hi2c->State = HAL_I2C_STATE_READY;
02799     }
02800
02801     /* Process Unlocked */
02802     __HAL_UNLOCK(hi2c);
02803
02804     if(hi2c->XferCount > 0U)
02805     {
02806       /* Note : The I2C interrupts must be enabled after unlocking current process
02807       to avoid the risk of I2C interrupt handle execution before current
02808       process unlock */
02809
02810       /* Enable EVT, BUF and ERR interrupt */
02811       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02812     }
02813     return HAL_OK;
02814   }
02815   else
02816   {
02817     return HAL_BUSY;
02818   }
02819 }
02820 /**
02821   * @brief  Write an amount of data in no-blocking mode with DMA to a specific memory address
02822   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02823   *         the configuration information for I2C module
02824   * @param  DevAddress Target device address
02825   * @param  MemAddress Internal memory address
02826   * @param  MemAddSize Size of internal memory address
02827   * @param  pData Pointer to data buffer
02828   * @param  Size Amount of data to be sent
02829   * @retval HAL status
02830   */
02831 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02832 {
02833   /* Check the parameters */
02834   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02835
02836   if(hi2c->State == HAL_I2C_STATE_READY)
02837   {
02838     /* Wait until BUSY flag is reset */
02839     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02840     {
02841       return HAL_BUSY;
02842     }
02843
02844     /* Process Locked */
02845     __HAL_LOCK(hi2c);
02846
02847     /* Disable Pos */
02848     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02849
02850     hi2c->State = HAL_I2C_STATE_BUSY_TX;
02851     hi2c->Mode = HAL_I2C_MODE_MEM;
02852     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02853
02854     hi2c->pBuffPtr = pData;
02855     hi2c->XferSize = Size;
02856     hi2c->XferCount = Size;
02857     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02858
02859     if(hi2c->XferSize > 0U)
02860     {
02861       /* Set the I2C DMA transfer complete callback */
02862       hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
02863
02864       /* Set the DMA error callback */
02865       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02866
02867       /* Enable the DMA Stream */
02868       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
02869
02870       /* Send Slave Address and Memory Address */
02871       if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
02872       {
02873         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02874         {
02875           /* Process Unlocked */
02876           __HAL_UNLOCK(hi2c);
02877           return HAL_ERROR;
02878         }
02879         else
02880         {
02881           /* Process Unlocked */
02882           __HAL_UNLOCK(hi2c);
02883           return HAL_TIMEOUT;
02884         }
02885       }
02886
02887       /* Enable DMA Request */
02888       hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02889     }
02890     else
02891     {
02892       /* Send Slave Address and Memory Address */
02893       if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
02894       {
02895         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02896         {
02897           /* Process Unlocked */
02898           __HAL_UNLOCK(hi2c);
02899           return HAL_ERROR;
02900         }
02901         else
02902         {
02903           /* Process Unlocked */
02904           __HAL_UNLOCK(hi2c);
02905           return HAL_TIMEOUT;
02906         }
02907       }
02908
02909       /* Wait until TXE flag is set */
02910       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
02911       {
02912         return HAL_TIMEOUT;
02913       }
02914
02915       /* Generate Stop */
02916       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02917
02918       hi2c->State = HAL_I2C_STATE_READY;
02919     }
02920
02921
02922     /* Process Unlocked */
02923     __HAL_UNLOCK(hi2c);
02924
02925     return HAL_OK;
02926   }
02927   else
02928   {
02929     return HAL_BUSY;
02930   }
02931 }
02932
02933 /**
02934   * @brief  Reads an amount of data in no-blocking mode with DMA from a specific memory address.
02935   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02936   *         the configuration information for I2C module
02937   * @param  DevAddress Target device address
02938   * @param  MemAddress Internal memory address
02939   * @param  MemAddSize Size of internal memory address
02940   * @param  pData Pointer to data buffer
02941   * @param  Size Amount of data to be read
02942   * @retval HAL status
02943   */
02944 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02945 {
02946   /* Check the parameters */
02947   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02948
02949   if(hi2c->State == HAL_I2C_STATE_READY)
02950   {
02951     /* Wait until BUSY flag is reset */
02952     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
02953     {
02954       return HAL_BUSY;
02955     }
02956
02957     /* Process Locked */
02958     __HAL_LOCK(hi2c);
02959
02960     /* Disable Pos */
02961     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02962
02963     hi2c->State = HAL_I2C_STATE_BUSY_RX;
02964     hi2c->Mode = HAL_I2C_MODE_MEM;
02965     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02966
02967     hi2c->pBuffPtr = pData;
02968     hi2c->XferSize = Size;
02969     hi2c->XferCount = Size;
02970     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02971
02972     if(hi2c->XferSize > 0U)
02973     {
02974       /* Set the I2C DMA transfer complete callback */
02975       hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
02976
02977       /* Set the DMA error callback */
02978       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02979
02980       /* Enable the DMA Stream */
02981       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
02982
02983       /* Send Slave Address and Memory Address */
02984       if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
02985       {
02986         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02987         {
02988           /* Process Unlocked */
02989           __HAL_UNLOCK(hi2c);
02990           return HAL_ERROR;
02991         }
02992         else
02993         {
02994           /* Process Unlocked */
02995           __HAL_UNLOCK(hi2c);
02996           return HAL_TIMEOUT;
02997         }
02998       }
02999
03000       if(Size == 1U)
03001       {
03002         /* Disable Acknowledge */
03003         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
03004       }
03005       else
03006       {
03007         /* Enable Last DMA bit */
03008         hi2c->Instance->CR2 |= I2C_CR2_LAST;
03009       }
03010
03011       /* Enable DMA Request */
03012       hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
03013
03014       /* Clear ADDR flag */
03015       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
03016
03017     }
03018     else
03019     {
03020       /* Send Slave Address and Memory Address */
03021       if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
03022       {
03023         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03024         {
03025           /* Process Unlocked */
03026           __HAL_UNLOCK(hi2c);
03027           return HAL_ERROR;
03028         }
03029         else
03030         {
03031           /* Process Unlocked */
03032           __HAL_UNLOCK(hi2c);
03033           return HAL_TIMEOUT;
03034         }
03035       }
03036
03037       /* Clear ADDR flag */
03038       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
03039
03040       /* Generate Stop */
03041       hi2c->Instance->CR1 |= I2C_CR1_STOP;
03042
03043       hi2c->State = HAL_I2C_STATE_READY;
03044     }
03045
03046     /* Process Unlocked */
03047     __HAL_UNLOCK(hi2c);
03048
03049     return HAL_OK;
03050   }
03051   else
03052   {
03053     return HAL_BUSY;
03054   }
03055 }
03056
03057 /**
03058   * @brief  Checks if target device is ready for communication.
03059   * @note   This function is used with Memory devices
03060   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03061   *         the configuration information for I2C module
03062   * @param  DevAddress Target device address
03063   * @param  Trials Number of trials
03064   * @param  Timeout Timeout duration
03065   * @retval HAL status
03066   */
03067 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
03068 {
03069   uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
03070
03071   if(hi2c->State == HAL_I2C_STATE_READY)
03072   {
03073     /* Wait until BUSY flag is reset */
03074     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
03075     {
03076       return HAL_BUSY;
03077     }
03078
03079     /* Process Locked */
03080     __HAL_LOCK(hi2c);
03081
03082     /* Disable Pos */
03083     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
03084
03085     hi2c->State = HAL_I2C_STATE_BUSY;
03086     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03087     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
03088
03089     do
03090     {
03091       /* Generate Start */
03092       hi2c->Instance->CR1 |= I2C_CR1_START;
03093
03094       /* Wait until SB flag is set */
03095       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
03096       {
03097         return HAL_TIMEOUT;
03098       }
03099
03100       /* Send slave address */
03101       hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
03102
03103       /* Wait until ADDR or AF flag are set */
03104       /* Get tick */
03105       tickstart = HAL_GetTick();
03106
03107       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
03108       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03109       tmp3 = hi2c->State;
03110       while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
03111       {
03112         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
03113         {
03114           hi2c->State = HAL_I2C_STATE_TIMEOUT;
03115         }
03116         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
03117         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03118         tmp3 = hi2c->State;
03119       }
03120
03121       hi2c->State = HAL_I2C_STATE_READY;
03122
03123       /* Check if the ADDR flag has been set */
03124       if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
03125       {
03126         /* Generate Stop */
03127         hi2c->Instance->CR1 |= I2C_CR1_STOP;
03128
03129         /* Clear ADDR Flag */
03130         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
03131
03132         /* Wait until BUSY flag is reset */
03133         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
03134         {
03135           return HAL_TIMEOUT;
03136         }
03137
03138         hi2c->State = HAL_I2C_STATE_READY;
03139
03140         /* Process Unlocked */
03141         __HAL_UNLOCK(hi2c);
03142
03143         return HAL_OK;
03144       }
03145       else
03146       {
03147         /* Generate Stop */
03148         hi2c->Instance->CR1 |= I2C_CR1_STOP;
03149
03150         /* Clear AF Flag */
03151         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03152
03153         /* Wait until BUSY flag is reset */
03154         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
03155         {
03156           return HAL_TIMEOUT;
03157         }
03158       }
03159     }while(I2C_Trials++ < Trials);
03160
03161     hi2c->State = HAL_I2C_STATE_READY;
03162
03163     /* Process Unlocked */
03164     __HAL_UNLOCK(hi2c);
03165
03166     return HAL_ERROR;
03167   }
03168   else
03169   {
03170     return HAL_BUSY;
03171   }
03172 }
03173
03174 /**
03175   * @brief  This function handles I2C event interrupt request.
03176   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03177   *         the configuration information for I2C module
03178   * @retval HAL status
03179   */
03180 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
03181 {
03182   uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
03183   /* Master or Memory mode selected */
03184   if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \
03185      (hi2c->Mode == HAL_I2C_MODE_MEM))
03186   {
03187     /* I2C in mode Transmitter -----------------------------------------------*/
03188     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
03189     {
03190       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
03191       tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
03192       tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
03193       tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
03194       /* TXE set and BTF reset -----------------------------------------------*/
03195       if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
03196       {
03197         I2C_MasterTransmit_TXE(hi2c);
03198       }
03199       /* BTF set -------------------------------------------------------------*/
03200       else if((tmp3 == SET) && (tmp4 == SET))
03201       {
03202         I2C_MasterTransmit_BTF(hi2c);
03203       }
03204     }
03205     /* I2C in mode Receiver --------------------------------------------------*/
03206     else
03207     {
03208       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
03209       tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
03210       tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
03211       tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
03212       /* RXNE set and BTF reset -----------------------------------------------*/
03213       if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
03214       {
03215         I2C_MasterReceive_RXNE(hi2c);
03216       }
03217       /* BTF set -------------------------------------------------------------*/
03218       else if((tmp3 == SET) && (tmp4 == SET))
03219       {
03220         I2C_MasterReceive_BTF(hi2c);
03221       }
03222     }
03223   }
03224   /* Slave mode selected */
03225   else
03226   {
03227     tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
03228     tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT));
03229     tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03230     tmp4 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA);
03231     /* ADDR set --------------------------------------------------------------*/
03232     if((tmp1 == SET) && (tmp2 == SET))
03233     {
03234       I2C_Slave_ADDR(hi2c);
03235     }
03236     /* STOPF set --------------------------------------------------------------*/
03237     else if((tmp3 == SET) && (tmp2 == SET))
03238     {
03239       I2C_Slave_STOPF(hi2c);
03240     }
03241     /* I2C in mode Transmitter -----------------------------------------------*/
03242     else if(tmp4 == SET)
03243     {
03244       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
03245       tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
03246       tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
03247       tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
03248       /* TXE set and BTF reset -----------------------------------------------*/
03249       if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
03250       {
03251         I2C_SlaveTransmit_TXE(hi2c);
03252       }
03253       /* BTF set -------------------------------------------------------------*/
03254       else if((tmp3 == SET) && (tmp4 == SET))
03255       {
03256         I2C_SlaveTransmit_BTF(hi2c);
03257       }
03258     }
03259     /* I2C in mode Receiver --------------------------------------------------*/
03260     else
03261     {
03262       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
03263       tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
03264       tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
03265       tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
03266       /* RXNE set and BTF reset ----------------------------------------------*/
03267       if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
03268       {
03269         I2C_SlaveReceive_RXNE(hi2c);
03270       }
03271       /* BTF set -------------------------------------------------------------*/
03272       else if((tmp3 == SET) && (tmp4 == SET))
03273       {
03274         I2C_SlaveReceive_BTF(hi2c);
03275       }
03276     }
03277   }
03278 }
03279
03280 /**
03281   * @brief  This function handles I2C error interrupt request.
03282   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03283   *         the configuration information for I2C module
03284   * @retval HAL status
03285   */
03286 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
03287 {
03288   uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
03289
03290   tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR);
03291   tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
03292   /* I2C Bus error interrupt occurred ----------------------------------------*/
03293   if((tmp1 == SET) && (tmp2 == SET))
03294   {
03295     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
03296
03297     /* Clear BERR flag */
03298     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
03299   }
03300
03301   tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO);
03302   tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
03303   /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
03304   if((tmp1 == SET) && (tmp2 == SET))
03305   {
03306     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
03307
03308     /* Clear ARLO flag */
03309     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
03310   }
03311
03312   tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03313   tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
03314   /* I2C Acknowledge failure error interrupt occurred ------------------------*/
03315   if((tmp1 == SET) && (tmp2 == SET))
03316   {
03317     tmp1 = hi2c->Mode;
03318     tmp2 = hi2c->XferCount;
03319     tmp3 = hi2c->State;
03320     tmp4 = hi2c->PreviousState;
03321     if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
03322       ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
03323       ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
03324     {
03325       I2C_Slave_AF(hi2c);
03326     }
03327     else
03328     {
03329       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03330
03331       /* Generate Stop */
03332       SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
03333
03334       /* Clear AF flag */
03335       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03336     }
03337   }
03338
03339   tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR);
03340   tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
03341   /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
03342   if((tmp1 == SET) && (tmp2 == SET))
03343   {
03344     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
03345     /* Clear OVR flag */
03346     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
03347   }
03348
03349   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03350   {
03351     if((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
03352     {
03353       /* keep HAL_I2C_STATE_LISTEN */
03354       hi2c->PreviousState = I2C_STATE_NONE;
03355       hi2c->State = HAL_I2C_STATE_LISTEN;
03356     }
03357     else
03358     {
03359       hi2c->PreviousState = I2C_STATE_NONE;
03360       hi2c->State = HAL_I2C_STATE_READY;
03361     }
03362
03363     /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
03364     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
03365
03366     HAL_I2C_ErrorCallback(hi2c);
03367
03368     /* STOP Flag is not set after a NACK reception */
03369     /* So may inform upper layer that listen phase is stopped */
03370     /* during NACK error treatment */
03371     if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
03372     {
03373       hi2c->XferOptions = I2C_NO_OPTION_FRAME;
03374       hi2c->PreviousState = I2C_STATE_NONE;
03375       hi2c->State = HAL_I2C_STATE_READY;
03376       hi2c->Mode = HAL_I2C_MODE_NONE;
03377
03378       /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
03379       HAL_I2C_ListenCpltCallback(hi2c);
03380     }
03381   }
03382 }
03383
03384 /**
03385   * @brief  Master Tx Transfer completed callbacks.
03386   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03387   *         the configuration information for I2C module
03388   * @retval None
03389   */
03390 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
03391 {
03392   /* Prevent unused argument(s) compilation warning */
03393   UNUSED(hi2c);
03394   /* NOTE : This function should not be modified, when the callback is needed,
03395             the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
03396    */
03397 }
03398
03399 /**
03400   * @brief  Master Rx Transfer completed callbacks.
03401   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03402   *         the configuration information for I2C module
03403   * @retval None
03404   */
03405 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
03406 {
03407   /* Prevent unused argument(s) compilation warning */
03408   UNUSED(hi2c);
03409   /* NOTE : This function should not be modified, when the callback is needed,
03410             the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
03411    */
03412 }
03413
03414 /** @brief  Slave Tx Transfer completed callbacks.
03415   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03416   *         the configuration information for I2C module
03417   * @retval None
03418   */
03419 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
03420 {
03421   /* Prevent unused argument(s) compilation warning */
03422   UNUSED(hi2c);
03423   /* NOTE : This function should not be modified, when the callback is needed,
03424             the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
03425    */
03426 }
03427
03428 /**
03429   * @brief  Slave Rx Transfer completed callbacks.
03430   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03431   *         the configuration information for I2C module
03432   * @retval None
03433   */
03434 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
03435 {
03436   /* Prevent unused argument(s) compilation warning */
03437   UNUSED(hi2c);
03438   /* NOTE : This function should not be modified, when the callback is needed,
03439             the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
03440    */
03441 }
03442
03443 /**
03444   * @brief  Slave Address Match callback.
03445   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03446   *                the configuration information for the specified I2C.
03447   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
03448   * @param  AddrMatchCode Address Match Code
03449   * @retval None
03450   */
03451 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
03452 {
03453   /* Prevent unused argument(s) compilation warning */
03454   UNUSED(hi2c);
03455   UNUSED(TransferDirection);
03456   UNUSED(AddrMatchCode);
03457   /* NOTE : This function should not be modified, when the callback is needed,
03458             the HAL_I2C_AddrCallback can be implemented in the user file
03459    */
03460 }
03461
03462 /**
03463   * @brief  Listen Complete callback.
03464   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03465   *                the configuration information for the specified I2C.
03466   * @retval None
03467   */
03468 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
03469 {
03470   /* Prevent unused argument(s) compilation warning */
03471   UNUSED(hi2c);
03472     /* NOTE : This function should not be modified, when the callback is needed,
03473             the HAL_I2C_ListenCpltCallback can be implemented in the user file
03474    */
03475 }
03476
03477 /**
03478   * @brief  Memory Tx Transfer completed callbacks.
03479   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03480   *         the configuration information for I2C module
03481   * @retval None
03482   */
03483 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
03484 {
03485   /* Prevent unused argument(s) compilation warning */
03486   UNUSED(hi2c);
03487   /* NOTE : This function should not be modified, when the callback is needed,
03488             the HAL_I2C_MemTxCpltCallback can be implemented in the user file
03489    */
03490 }
03491
03492 /**
03493   * @brief  Memory Rx Transfer completed callbacks.
03494   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03495   *         the configuration information for I2C module
03496   * @retval None
03497   */
03498 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
03499 {
03500   /* Prevent unused argument(s) compilation warning */
03501   UNUSED(hi2c);
03502   /* NOTE : This function should not be modified, when the callback is needed,
03503             the HAL_I2C_MemRxCpltCallback can be implemented in the user file
03504    */
03505 }
03506
03507 /**
03508   * @brief  I2C error callbacks.
03509   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03510   *         the configuration information for I2C module
03511   * @retval None
03512   */
03513 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
03514 {
03515   /* Prevent unused argument(s) compilation warning */
03516   UNUSED(hi2c);
03517   /* NOTE : This function should not be modified, when the callback is needed,
03518             the HAL_I2C_ErrorCallback can be implemented in the user file
03519    */
03520 }
03521
03522 /**
03523   * @}
03524   */
03525
03526 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
03527   *  @brief   Peripheral State and Errors functions
03528   *
03529 @verbatim
03530  ===============================================================================
03531             ##### Peripheral State, Mode and Errors functions #####
03532  ===============================================================================
03533     [..]
03534     This subsection permits to get in run-time the status of the peripheral
03535     and the data flow.
03536
03537 @endverbatim
03538   * @{
03539   */
03540
03541 /**
03542   * @brief  Returns the I2C state.
03543   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03544   *         the configuration information for I2C module
03545   * @retval HAL state
03546   */
03547 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
03548 {
03549   return hi2c->State;
03550 }
03551
03552 /**
03553   * @brief  Returns the I2C Master, Slave, Memory or no mode.
03554   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03555   *         the configuration information for I2C module
03556   * @retval HAL mode
03557   */
03558 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
03559 {
03560   return hi2c->Mode;
03561 }
03562
03563 /**
03564   * @brief  Return the I2C error code
03565   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03566   *              the configuration information for the specified I2C.
03567   * @retval I2C Error Code
03568   */
03569 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
03570 {
03571   return hi2c->ErrorCode;
03572 }
03573
03574 /**
03575   * @}
03576   */
03577
03578 /**
03579   * @brief  Handle TXE flag for Master
03580   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03581   *         the configuration information for I2C module
03582   * @retval HAL status
03583   */
03584 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
03585 {
03586   if(hi2c->XferCount == 0U)
03587   {
03588     /* Disable BUF interrupt */
03589     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
03590   }
03591   else
03592   {
03593     /* Write data to DR */
03594     hi2c->Instance->DR = (*hi2c->pBuffPtr++);
03595     hi2c->XferCount--;
03596   }
03597
03598   return HAL_OK;
03599 }
03600
03601 /**
03602   * @brief  Handle BTF flag for Master transmitter
03603   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03604   *         the configuration information for I2C module
03605   * @retval HAL status
03606   */
03607 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
03608 {
03609   /* Declaration of tmp to prevent undefined behavior of volatile usage */
03610   uint32_t tmp;
03611
03612   if(hi2c->XferCount != 0U)
03613   {
03614     /* Write data to DR */
03615     hi2c->Instance->DR = (*hi2c->pBuffPtr++);
03616     hi2c->XferCount--;
03617   }
03618   else
03619   {
03620     /* Call TxCpltCallback() directly if no stop mode is set */
03621     if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
03622     {
03623       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03624
03625       tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
03626       hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
03627       hi2c->Mode = HAL_I2C_MODE_NONE;
03628       hi2c->State = HAL_I2C_STATE_READY;
03629
03630       HAL_I2C_MasterTxCpltCallback(hi2c);
03631     }
03632     else /* Generate Stop condition then Call TxCpltCallback() */
03633     {
03634       /* Disable EVT, BUF and ERR interrupt */
03635       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03636
03637       /* Generate Stop */
03638       hi2c->Instance->CR1 |= I2C_CR1_STOP;
03639
03640       if(hi2c->Mode == HAL_I2C_MODE_MEM)
03641       {
03642         hi2c->PreviousState = I2C_STATE_NONE;
03643         hi2c->State = HAL_I2C_STATE_READY;
03644         hi2c->Mode = HAL_I2C_MODE_NONE;
03645
03646         HAL_I2C_MemTxCpltCallback(hi2c);
03647       }
03648       else
03649       {
03650         hi2c->PreviousState = I2C_STATE_NONE;
03651         hi2c->State = HAL_I2C_STATE_READY;
03652         hi2c->Mode = HAL_I2C_MODE_NONE;
03653
03654         HAL_I2C_MasterTxCpltCallback(hi2c);
03655       }
03656     }
03657   }
03658   return HAL_OK;
03659 }
03660
03661 /**
03662   * @brief  Handle RXNE flag for Master
03663   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03664   *         the configuration information for I2C module
03665   * @retval HAL status
03666   */
03667 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
03668 {
03669   uint32_t tmp = 0U;
03670
03671   tmp = hi2c->XferCount;
03672   if(tmp > 3U)
03673   {
03674     /* Read data from DR */
03675     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03676     hi2c->XferCount--;
03677   }
03678   else if((tmp == 2U) || (tmp == 3U))
03679   {
03680     if(hi2c->XferOptions != I2C_NEXT_FRAME)
03681     {
03682       /* Disable Acknowledge */
03683       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
03684
03685       /* Enable Pos */
03686       hi2c->Instance->CR1 |= I2C_CR1_POS;
03687     }
03688     else
03689     {
03690       /* Enable Acknowledge */
03691       hi2c->Instance->CR1 |= I2C_CR1_ACK;
03692     }
03693
03694     /* Disable BUF interrupt */
03695     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
03696   }
03697   else
03698   {
03699     if(hi2c->XferOptions != I2C_NEXT_FRAME)
03700     {
03701       /* Disable Acknowledge */
03702       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
03703     }
03704     else
03705     {
03706       /* Enable Acknowledge */
03707       hi2c->Instance->CR1 |= I2C_CR1_ACK;
03708     }
03709
03710     /* Disable EVT, BUF and ERR interrupt */
03711     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03712
03713     /* Read data from DR */
03714     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03715     hi2c->XferCount--;
03716
03717     if(hi2c->Mode == HAL_I2C_MODE_MEM)
03718     {
03719       tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
03720       hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
03721       hi2c->State = HAL_I2C_STATE_READY;
03722       hi2c->Mode = HAL_I2C_MODE_NONE;
03723
03724       HAL_I2C_MemRxCpltCallback(hi2c);
03725     }
03726     else
03727     {
03728       tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
03729       hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
03730       hi2c->State = HAL_I2C_STATE_READY;
03731       hi2c->Mode = HAL_I2C_MODE_NONE;
03732
03733       HAL_I2C_MasterRxCpltCallback(hi2c);
03734     }
03735   }
03736   return HAL_OK;
03737 }
03738
03739 /**
03740   * @brief  Handle BTF flag for Master receiver
03741   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03742   *         the configuration information for I2C module
03743   * @retval HAL status
03744   */
03745 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
03746 {
03747   /* Declaration of tmp to prevent undefined behavior of volatile usage */
03748   uint32_t tmp;
03749
03750   if(hi2c->XferCount == 3U)
03751   {
03752     if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME) || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
03753     {
03754       if(hi2c->XferOptions != I2C_NEXT_FRAME)
03755       {
03756         /* Disable Acknowledge */
03757         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
03758       }
03759       else
03760       {
03761         /* Enable Acknowledge */
03762         hi2c->Instance->CR1 |= I2C_CR1_ACK;
03763       }
03764     }
03765
03766     /* Read data from DR */
03767     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03768     hi2c->XferCount--;
03769   }
03770   else if(hi2c->XferCount == 2U)
03771   {
03772     /* Prepare next transfer or stop current transfer */
03773     if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
03774     {
03775       if(hi2c->XferOptions != I2C_NEXT_FRAME)
03776       {
03777         /* Disable Acknowledge */
03778         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
03779       }
03780       else
03781       {
03782         /* Enable Acknowledge */
03783         hi2c->Instance->CR1 |= I2C_CR1_ACK;
03784       }
03785       tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
03786       hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
03787     }
03788     else
03789     {
03790       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
03791
03792       /* Generate Stop */
03793       hi2c->Instance->CR1 |= I2C_CR1_STOP;
03794     }
03795
03796     /* Read data from DR */
03797     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03798     hi2c->XferCount--;
03799
03800     /* Read data from DR */
03801     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03802     hi2c->XferCount--;
03803
03804     /* Disable EVT and ERR interrupt */
03805     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
03806
03807     if(hi2c->Mode == HAL_I2C_MODE_MEM)
03808     {
03809       hi2c->State = HAL_I2C_STATE_READY;
03810       hi2c->Mode = HAL_I2C_MODE_NONE;
03811
03812       HAL_I2C_MemRxCpltCallback(hi2c);
03813     }
03814     else
03815     {
03816       hi2c->State = HAL_I2C_STATE_READY;
03817       hi2c->Mode = HAL_I2C_MODE_NONE;
03818
03819       HAL_I2C_MasterRxCpltCallback(hi2c);
03820     }
03821   }
03822   else
03823   {
03824     /* Read data from DR */
03825     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03826     hi2c->XferCount--;
03827   }
03828   return HAL_OK;
03829 }
03830
03831 /**
03832   * @brief  Handle TXE flag for Slave
03833   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03834   *         the configuration information for I2C module
03835   * @retval HAL status
03836   */
03837 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
03838 {
03839   /* Declaration of tmp to prevent undefined behavior of volatile usage */
03840   uint32_t tmp;
03841
03842   if(hi2c->XferCount != 0U)
03843   {
03844     /* Write data to DR */
03845     hi2c->Instance->DR = (*hi2c->pBuffPtr++);
03846     hi2c->XferCount--;
03847
03848     if((hi2c->XferCount == 0U) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
03849     {
03850       /* Last Byte is received, disable Interrupt */
03851       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
03852
03853       /* Set state at HAL_I2C_STATE_LISTEN */
03854       tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
03855       hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
03856       hi2c->State = HAL_I2C_STATE_LISTEN;
03857
03858       /* Call the Tx complete callback to inform upper layer of the end of receive process */
03859       HAL_I2C_SlaveTxCpltCallback(hi2c);
03860     }
03861   }
03862   return HAL_OK;
03863 }
03864
03865 /**
03866   * @brief  Handle BTF flag for Slave transmitter
03867   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03868   *         the configuration information for I2C module
03869   * @retval HAL status
03870   */
03871 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
03872 {
03873   if(hi2c->XferCount != 0U)
03874   {
03875     /* Write data to DR */
03876     hi2c->Instance->DR = (*hi2c->pBuffPtr++);
03877     hi2c->XferCount--;
03878   }
03879   return HAL_OK;
03880 }
03881
03882 /**
03883   * @brief  Handle RXNE flag for Slave
03884   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03885   *         the configuration information for I2C module
03886   * @retval HAL status
03887   */
03888 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
03889 {
03890   /* Declaration of tmp to prevent undefined behavior of volatile usage */
03891   uint32_t tmp;
03892
03893   if(hi2c->XferCount != 0U)
03894   {
03895     /* Read data from DR */
03896     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03897     hi2c->XferCount--;
03898
03899     if((hi2c->XferCount == 0U) && (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
03900     {
03901       /* Last Byte is received, disable Interrupt */
03902       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
03903
03904       /* Set state at HAL_I2C_STATE_LISTEN */
03905       tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
03906       hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
03907       hi2c->State = HAL_I2C_STATE_LISTEN;
03908
03909       /* Call the Rx complete callback to inform upper layer of the end of receive process */
03910       HAL_I2C_SlaveRxCpltCallback(hi2c);
03911     }
03912   }
03913   return HAL_OK;
03914 }
03915
03916 /**
03917   * @brief  Handle BTF flag for Slave receiver
03918   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03919   *         the configuration information for I2C module
03920   * @retval HAL status
03921   */
03922 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
03923 {
03924   if(hi2c->XferCount != 0U)
03925   {
03926     /* Read data from DR */
03927     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
03928     hi2c->XferCount--;
03929   }
03930   return HAL_OK;
03931 }
03932
03933 /**
03934   * @brief  Handle ADD flag for Slave
03935   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03936   *         the configuration information for I2C module
03937   * @retval HAL status
03938   */
03939 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
03940 {
03941   uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
03942   uint16_t SlaveAddrCode = 0U;
03943
03944   /* Transfer Direction requested by Master */
03945   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
03946   {
03947     TransferDirection = I2C_DIRECTION_TRANSMIT;
03948   }
03949
03950   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
03951   {
03952     SlaveAddrCode = hi2c->Init.OwnAddress1;
03953   }
03954   else
03955   {
03956     SlaveAddrCode = hi2c->Init.OwnAddress2;
03957   }
03958
03959   /* Call Slave Addr callback */
03960   HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
03961
03962   return HAL_OK;
03963 }
03964
03965 /**
03966   * @brief  Handle STOPF flag for Slave
03967   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03968   *         the configuration information for I2C module
03969   * @retval HAL status
03970   */
03971 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
03972 {
03973   /* Disable EVT, BUF and ERR interrupt */
03974   __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03975
03976   /* Clear STOPF flag */
03977   __HAL_I2C_CLEAR_STOPFLAG(hi2c);
03978
03979   /* Disable Acknowledge */
03980   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
03981
03982   if((hi2c->State & HAL_I2C_STATE_LISTEN)== HAL_I2C_STATE_LISTEN)
03983   {
03984     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
03985     hi2c->PreviousState = I2C_STATE_NONE;
03986     hi2c->State = HAL_I2C_STATE_READY;
03987     hi2c->Mode = HAL_I2C_MODE_NONE;
03988
03989     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
03990     HAL_I2C_ListenCpltCallback(hi2c);
03991   }
03992   else
03993   {
03994     if((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || \
03995        (hi2c->State == HAL_I2C_STATE_BUSY_RX))
03996     {
03997       hi2c->PreviousState = I2C_STATE_NONE;
03998       hi2c->State = HAL_I2C_STATE_READY;
03999       hi2c->Mode = HAL_I2C_MODE_NONE;
04000
04001       HAL_I2C_SlaveRxCpltCallback(hi2c);
04002     }
04003   }
04004
04005   return HAL_OK;
04006 }
04007
04008 /**
04009   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04010   *         the configuration information for I2C module
04011   * @retval HAL status
04012   */
04013 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
04014 {
04015   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04016   uint32_t tmp;
04017
04018   if(((hi2c->XferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
04019           (hi2c->State == HAL_I2C_STATE_LISTEN))
04020   {
04021     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04022
04023     /* Disable EVT, BUF and ERR interrupt */
04024     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
04025
04026     /* Clear AF flag */
04027     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04028
04029     /* Disable Acknowledge */
04030     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04031
04032     hi2c->PreviousState = I2C_STATE_NONE;
04033     hi2c->State = HAL_I2C_STATE_READY;
04034     hi2c->Mode = HAL_I2C_MODE_NONE;
04035
04036     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04037     HAL_I2C_ListenCpltCallback(hi2c);
04038   }
04039   else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
04040   {
04041     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04042     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
04043     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
04044     hi2c->State = HAL_I2C_STATE_READY;
04045     hi2c->Mode = HAL_I2C_MODE_NONE;
04046
04047     /* Disable EVT, BUF and ERR interrupt */
04048     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
04049
04050     /* Clear AF flag */
04051     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04052
04053     /* Disable Acknowledge */
04054     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04055
04056     HAL_I2C_SlaveTxCpltCallback(hi2c);
04057   }
04058   else
04059   {
04060     /* Clear AF flag only */
04061     /* State Listen, but XferOptions == FIRST or NEXT */
04062     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04063   }
04064
04065   return HAL_OK;
04066 }
04067
04068 /**
04069   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04070   *         the configuration information for I2C module
04071   * @param  DevAddress Target device address
04072   * @param  Timeout Timeout duration
04073   * @retval HAL status
04074   */
04075 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
04076 {
04077   /* Generate Start condition if first transfer */
04078   if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME) || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
04079   {
04080     /* Generate Start */
04081     hi2c->Instance->CR1 |= I2C_CR1_START;
04082   }
04083   else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
04084   {
04085
04086     /* Generate ReStart */
04087     hi2c->Instance->CR1 |= I2C_CR1_START;
04088   }
04089
04090   /* Wait until SB flag is set */
04091   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
04092   {
04093     return HAL_TIMEOUT;
04094   }
04095
04096   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
04097   {
04098     /* Send slave address */
04099     hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
04100   }
04101   else
04102   {
04103     /* Send header of slave address */
04104     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
04105
04106     /* Wait until ADD10 flag is set */
04107     if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
04108     {
04109       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04110       {
04111         return HAL_ERROR;
04112       }
04113       else
04114       {
04115         return HAL_TIMEOUT;
04116       }
04117     }
04118
04119     /* Send slave address */
04120     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
04121   }
04122
04123   /* Wait until ADDR flag is set */
04124   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
04125   {
04126     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04127     {
04128       return HAL_ERROR;
04129     }
04130     else
04131     {
04132       return HAL_TIMEOUT;
04133     }
04134   }
04135
04136   return HAL_OK;
04137 }
04138
04139 /**
04140   * @brief  Master sends target device address for read request.
04141   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04142   *         the configuration information for I2C module
04143   * @param  DevAddress Target device address
04144   * @param  Timeout Timeout duration
04145   * @retval HAL status
04146   */
04147 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
04148 {
04149   /* Generate Start condition if first transfer */
04150   if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)  || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
04151   {
04152     /* Enable Acknowledge */
04153     hi2c->Instance->CR1 |= I2C_CR1_ACK;
04154
04155     /* Generate Start */
04156     hi2c->Instance->CR1 |= I2C_CR1_START;
04157   }
04158   else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
04159   {
04160     /* Enable Acknowledge */
04161     hi2c->Instance->CR1 |= I2C_CR1_ACK;
04162
04163     /* Generate ReStart */
04164     hi2c->Instance->CR1 |= I2C_CR1_START;
04165   }
04166
04167   /* Wait until SB flag is set */
04168   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
04169   {
04170     return HAL_TIMEOUT;
04171   }
04172
04173   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
04174   {
04175     /* Send slave address */
04176     hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
04177   }
04178   else
04179   {
04180     /* Send header of slave address */
04181     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
04182
04183     /* Wait until ADD10 flag is set */
04184     if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
04185     {
04186       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04187       {
04188         return HAL_ERROR;
04189       }
04190       else
04191       {
04192         return HAL_TIMEOUT;
04193       }
04194     }
04195
04196     /* Send slave address */
04197     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
04198
04199     /* Wait until ADDR flag is set */
04200     if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
04201     {
04202       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04203       {
04204         return HAL_ERROR;
04205       }
04206       else
04207       {
04208         return HAL_TIMEOUT;
04209       }
04210     }
04211
04212     /* Clear ADDR flag */
04213     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04214
04215     /* Generate Restart */
04216     hi2c->Instance->CR1 |= I2C_CR1_START;
04217
04218     /* Wait until SB flag is set */
04219     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
04220     {
04221       return HAL_TIMEOUT;
04222     }
04223
04224     /* Send header of slave address */
04225     hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
04226   }
04227
04228   /* Wait until ADDR flag is set */
04229   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
04230   {
04231     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04232     {
04233       return HAL_ERROR;
04234     }
04235     else
04236     {
04237       return HAL_TIMEOUT;
04238     }
04239   }
04240
04241   return HAL_OK;
04242 }
04243
04244 /**
04245   * @brief  Master sends target device address followed by internal memory address for write request.
04246   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04247   *         the configuration information for I2C module
04248   * @param  DevAddress Target device address
04249   * @param  MemAddress Internal memory address
04250   * @param  MemAddSize Size of internal memory address
04251   * @param  Timeout Timeout duration
04252   * @retval HAL status
04253   */
04254 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
04255 {
04256   /* Generate Start */
04257   hi2c->Instance->CR1 |= I2C_CR1_START;
04258
04259   /* Wait until SB flag is set */
04260   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
04261   {
04262     return HAL_TIMEOUT;
04263   }
04264
04265   /* Send slave address */
04266   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
04267
04268   /* Wait until ADDR flag is set */
04269   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
04270   {
04271     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04272     {
04273       return HAL_ERROR;
04274     }
04275     else
04276     {
04277       return HAL_TIMEOUT;
04278     }
04279   }
04280
04281   /* Clear ADDR flag */
04282   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04283
04284   /* Wait until TXE flag is set */
04285   if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
04286   {
04287     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04288     {
04289       /* Generate Stop */
04290       hi2c->Instance->CR1 |= I2C_CR1_STOP;
04291       return HAL_ERROR;
04292     }
04293     else
04294     {
04295       return HAL_TIMEOUT;
04296     }
04297   }
04298
04299   /* If Memory address size is 8Bit */
04300   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
04301   {
04302     /* Send Memory Address */
04303     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
04304   }
04305   /* If Memory address size is 16Bit */
04306   else
04307   {
04308     /* Send MSB of Memory Address */
04309     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
04310
04311     /* Wait until TXE flag is set */
04312     if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
04313     {
04314       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04315       {
04316         /* Generate Stop */
04317         hi2c->Instance->CR1 |= I2C_CR1_STOP;
04318         return HAL_ERROR;
04319       }
04320       else
04321       {
04322         return HAL_TIMEOUT;
04323       }
04324     }
04325
04326     /* Send LSB of Memory Address */
04327     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
04328   }
04329
04330   return HAL_OK;
04331 }
04332
04333 /**
04334   * @brief  Master sends target device address followed by internal memory address for read request.
04335   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04336   *         the configuration information for I2C module
04337   * @param  DevAddress Target device address
04338   * @param  MemAddress Internal memory address
04339   * @param  MemAddSize Size of internal memory address
04340   * @param  Timeout Timeout duration
04341   * @retval HAL status
04342   */
04343 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
04344 {
04345   /* Enable Acknowledge */
04346   hi2c->Instance->CR1 |= I2C_CR1_ACK;
04347
04348   /* Generate Start */
04349   hi2c->Instance->CR1 |= I2C_CR1_START;
04350
04351   /* Wait until SB flag is set */
04352   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
04353   {
04354     return HAL_TIMEOUT;
04355   }
04356
04357   /* Send slave address */
04358   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
04359
04360   /* Wait until ADDR flag is set */
04361   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
04362   {
04363     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04364     {
04365       return HAL_ERROR;
04366     }
04367     else
04368     {
04369       return HAL_TIMEOUT;
04370     }
04371   }
04372
04373   /* Clear ADDR flag */
04374   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04375
04376   /* Wait until TXE flag is set */
04377   if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
04378   {
04379     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04380     {
04381       /* Generate Stop */
04382       hi2c->Instance->CR1 |= I2C_CR1_STOP;
04383       return HAL_ERROR;
04384     }
04385     else
04386     {
04387       return HAL_TIMEOUT;
04388     }
04389   }
04390
04391   /* If Memory address size is 8Bit */
04392   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
04393   {
04394     /* Send Memory Address */
04395     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
04396   }
04397   /* If Memory address size is 16Bit */
04398   else
04399   {
04400     /* Send MSB of Memory Address */
04401     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
04402
04403     /* Wait until TXE flag is set */
04404     if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
04405     {
04406       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04407       {
04408         /* Generate Stop */
04409         hi2c->Instance->CR1 |= I2C_CR1_STOP;
04410         return HAL_ERROR;
04411       }
04412       else
04413       {
04414         return HAL_TIMEOUT;
04415       }
04416     }
04417
04418     /* Send LSB of Memory Address */
04419     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
04420   }
04421
04422   /* Wait until TXE flag is set */
04423   if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
04424   {
04425     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04426     {
04427       /* Generate Stop */
04428       hi2c->Instance->CR1 |= I2C_CR1_STOP;
04429       return HAL_ERROR;
04430     }
04431     else
04432     {
04433       return HAL_TIMEOUT;
04434     }
04435   }
04436
04437   /* Generate Restart */
04438   hi2c->Instance->CR1 |= I2C_CR1_START;
04439
04440   /* Wait until SB flag is set */
04441   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
04442   {
04443     return HAL_TIMEOUT;
04444   }
04445
04446   /* Send slave address */
04447   hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
04448
04449   /* Wait until ADDR flag is set */
04450   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
04451   {
04452     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04453     {
04454       return HAL_ERROR;
04455     }
04456     else
04457     {
04458       return HAL_TIMEOUT;
04459     }
04460   }
04461
04462   return HAL_OK;
04463 }
04464
04465 /**
04466   * @brief  DMA I2C master transmit process complete callback.
04467   * @param  hdma DMA handle
04468   * @retval None
04469   */
04470 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
04471 {
04472   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04473
04474   /* Wait until BTF flag is reset */
04475   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
04476   {
04477     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04478   }
04479
04480   /* Generate Stop */
04481   hi2c->Instance->CR1 |= I2C_CR1_STOP;
04482
04483   /* Disable DMA Request */
04484   hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
04485
04486   hi2c->XferCount = 0U;
04487
04488   hi2c->State = HAL_I2C_STATE_READY;
04489   hi2c->Mode = HAL_I2C_MODE_NONE;
04490
04491   /* Check if Errors has been detected during transfer */
04492   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04493   {
04494     HAL_I2C_ErrorCallback(hi2c);
04495   }
04496   else
04497   {
04498     HAL_I2C_MasterTxCpltCallback(hi2c);
04499   }
04500 }
04501
04502 /**
04503   * @brief  DMA I2C slave transmit process complete callback.
04504   * @param  hdma DMA handle
04505   * @retval None
04506   */
04507 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
04508 {
04509   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04510
04511   /* Wait until AF flag is reset */
04512   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
04513   {
04514     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04515   }
04516
04517   /* Clear AF flag */
04518   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04519
04520   /* Disable Address Acknowledge */
04521   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04522
04523   /* Disable DMA Request */
04524   hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
04525
04526   hi2c->XferCount = 0U;
04527
04528   hi2c->State = HAL_I2C_STATE_READY;
04529   hi2c->Mode = HAL_I2C_MODE_NONE;
04530
04531   /* Check if Errors has been detected during transfer */
04532   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04533   {
04534     HAL_I2C_ErrorCallback(hi2c);
04535   }
04536   else
04537   {
04538     HAL_I2C_SlaveTxCpltCallback(hi2c);
04539   }
04540 }
04541
04542 /**
04543   * @brief  DMA I2C master receive process complete callback
04544   * @param  hdma DMA handle
04545   * @retval None
04546   */
04547 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
04548 {
04549   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04550
04551   /* Disable Acknowledge */
04552   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04553
04554   /* Generate Stop */
04555   hi2c->Instance->CR1 |= I2C_CR1_STOP;
04556
04557   /* Disable Last DMA */
04558   hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
04559
04560   /* Disable DMA Request */
04561   hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
04562
04563   hi2c->XferCount = 0U;
04564
04565   hi2c->State = HAL_I2C_STATE_READY;
04566   hi2c->Mode = HAL_I2C_MODE_NONE;
04567
04568   /* Check if Errors has been detected during transfer */
04569   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04570   {
04571     HAL_I2C_ErrorCallback(hi2c);
04572   }
04573   else
04574   {
04575     HAL_I2C_MasterRxCpltCallback(hi2c);
04576   }
04577 }
04578
04579 /**
04580   * @brief  DMA I2C slave receive process complete callback.
04581   * @param  hdma DMA handle
04582   * @retval None
04583   */
04584 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
04585 {
04586   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04587
04588   /* Wait until STOPF flag is reset */
04589   if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK)
04590   {
04591     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04592     {
04593       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04594     }
04595     else
04596     {
04597       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04598     }
04599   }
04600
04601   /* Clear STOPF flag */
04602   __HAL_I2C_CLEAR_STOPFLAG(hi2c);
04603
04604   /* Disable Address Acknowledge */
04605   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04606
04607   /* Disable DMA Request */
04608   hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
04609
04610   hi2c->XferCount = 0U;
04611
04612   hi2c->State = HAL_I2C_STATE_READY;
04613   hi2c->Mode = HAL_I2C_MODE_NONE;
04614
04615   /* Check if Errors has been detected during transfer */
04616   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04617   {
04618     HAL_I2C_ErrorCallback(hi2c);
04619   }
04620   else
04621   {
04622     HAL_I2C_SlaveRxCpltCallback(hi2c);
04623   }
04624 }
04625
04626 /**
04627   * @brief  DMA I2C Memory Write process complete callback
04628   * @param  hdma DMA handle
04629   * @retval None
04630   */
04631 static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
04632 {
04633   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04634
04635   /* Wait until BTF flag is reset */
04636   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
04637   {
04638     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04639   }
04640
04641   /* Generate Stop */
04642   hi2c->Instance->CR1 |= I2C_CR1_STOP;
04643
04644   /* Disable DMA Request */
04645   hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
04646
04647   hi2c->XferCount = 0U;
04648
04649   hi2c->State = HAL_I2C_STATE_READY;
04650   hi2c->Mode = HAL_I2C_MODE_NONE;
04651
04652   /* Check if Errors has been detected during transfer */
04653   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04654   {
04655     HAL_I2C_ErrorCallback(hi2c);
04656   }
04657   else
04658   {
04659     HAL_I2C_MemTxCpltCallback(hi2c);
04660   }
04661 }
04662
04663 /**
04664   * @brief  DMA I2C Memory Read process complete callback
04665   * @param  hdma DMA handle
04666   * @retval None
04667   */
04668 static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
04669 {
04670   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04671
04672   /* Disable Acknowledge */
04673   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04674
04675   /* Generate Stop */
04676   hi2c->Instance->CR1 |= I2C_CR1_STOP;
04677
04678   /* Disable Last DMA */
04679   hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
04680
04681   /* Disable DMA Request */
04682   hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
04683
04684   hi2c->XferCount = 0U;
04685
04686   hi2c->State = HAL_I2C_STATE_READY;
04687   hi2c->Mode = HAL_I2C_MODE_NONE;
04688
04689   /* Check if Errors has been detected during transfer */
04690   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04691   {
04692     HAL_I2C_ErrorCallback(hi2c);
04693   }
04694   else
04695   {
04696     HAL_I2C_MemRxCpltCallback(hi2c);
04697   }
04698 }
04699
04700 /**
04701   * @brief  DMA I2C communication error callback.
04702   * @param  hdma DMA handle
04703   * @retval None
04704   */
04705 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
04706 {
04707   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04708
04709   /* Disable Acknowledge */
04710   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04711
04712   hi2c->XferCount = 0U;
04713
04714   hi2c->State = HAL_I2C_STATE_READY;
04715   hi2c->Mode = HAL_I2C_MODE_NONE;
04716
04717   hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
04718
04719   HAL_I2C_ErrorCallback(hi2c);
04720 }
04721
04722 /**
04723   * @brief  This function handles I2C Communication Timeout.
04724   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04725   *         the configuration information for I2C module
04726   * @param  Flag specifies the I2C flag to check.
04727   * @param  Status The new Flag status (SET or RESET).
04728   * @param  Timeout Timeout duration
04729   * @retval HAL status
04730   */
04731 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
04732 {
04733   uint32_t tickstart = 0U;
04734
04735   /* Get tick */
04736   tickstart = HAL_GetTick();
04737
04738   /* Wait until flag is set */
04739   if(Status == RESET)
04740   {
04741     while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
04742     {
04743       /* Check for the Timeout */
04744       if(Timeout != HAL_MAX_DELAY)
04745       {
04746         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
04747         {
04748           hi2c->PreviousState = I2C_STATE_NONE;
04749           hi2c->State= HAL_I2C_STATE_READY;
04750
04751           /* Process Unlocked */
04752           __HAL_UNLOCK(hi2c);
04753
04754           return HAL_TIMEOUT;
04755         }
04756       }
04757     }
04758   }
04759   else
04760   {
04761     while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
04762     {
04763       /* Check for the Timeout */
04764       if(Timeout != HAL_MAX_DELAY)
04765       {
04766         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
04767         {
04768           hi2c->PreviousState = I2C_STATE_NONE;
04769           hi2c->State= HAL_I2C_STATE_READY;
04770
04771           /* Process Unlocked */
04772           __HAL_UNLOCK(hi2c);
04773
04774           return HAL_TIMEOUT;
04775         }
04776       }
04777     }
04778   }
04779   return HAL_OK;
04780 }
04781
04782 /**
04783   * @brief  This function handles I2C Communication Timeout for Master addressing phase.
04784   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04785   *         the configuration information for I2C module
04786   * @param  Flag specifies the I2C flag to check.
04787   * @param  Timeout Timeout duration
04788   * @retval HAL status
04789   */
04790 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
04791 {
04792   uint32_t tickstart = 0U;
04793
04794   /* Get tick */
04795   tickstart = HAL_GetTick();
04796
04797   while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
04798   {
04799     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
04800     {
04801       /* Generate Stop */
04802       hi2c->Instance->CR1 |= I2C_CR1_STOP;
04803
04804       /* Clear AF Flag */
04805       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04806
04807       hi2c->ErrorCode = HAL_I2C_ERROR_AF;
04808       hi2c->PreviousState = I2C_STATE_NONE;
04809       hi2c->State= HAL_I2C_STATE_READY;
04810
04811       /* Process Unlocked */
04812       __HAL_UNLOCK(hi2c);
04813
04814       return HAL_ERROR;
04815     }
04816
04817     /* Check for the Timeout */
04818     if(Timeout != HAL_MAX_DELAY)
04819     {
04820       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
04821       {
04822         hi2c->PreviousState = I2C_STATE_NONE;
04823         hi2c->State= HAL_I2C_STATE_READY;
04824
04825         /* Process Unlocked */
04826         __HAL_UNLOCK(hi2c);
04827
04828         return HAL_TIMEOUT;
04829       }
04830     }
04831   }
04832   return HAL_OK;
04833 }
04834
04835 /**
04836   * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
04837   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04838   *                the configuration information for the specified I2C.
04839   * @param  Timeout Timeout duration
04840   * @retval HAL status
04841   */
04842 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
04843 {
04844   uint32_t tickstart = HAL_GetTick();
04845
04846   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
04847   {
04848     /* Check if a NACK is detected */
04849     if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
04850     {
04851       return HAL_ERROR;
04852     }
04853
04854     /* Check for the Timeout */
04855     if(Timeout != HAL_MAX_DELAY)
04856     {
04857       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04858       {
04859         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04860         hi2c->PreviousState = I2C_STATE_NONE;
04861         hi2c->State= HAL_I2C_STATE_READY;
04862
04863         /* Process Unlocked */
04864         __HAL_UNLOCK(hi2c);
04865
04866         return HAL_TIMEOUT;
04867       }
04868     }
04869   }
04870   return HAL_OK;
04871 }
04872
04873 /**
04874   * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
04875   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04876   *                the configuration information for the specified I2C.
04877   * @param  Timeout Timeout duration
04878   * @retval HAL status
04879   */
04880 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
04881 {
04882   uint32_t tickstart = HAL_GetTick();
04883
04884   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
04885   {
04886     /* Check if a NACK is detected */
04887     if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
04888     {
04889       return HAL_ERROR;
04890     }
04891
04892     /* Check for the Timeout */
04893     if(Timeout != HAL_MAX_DELAY)
04894     {
04895       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04896       {
04897         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04898         hi2c->PreviousState = I2C_STATE_NONE;
04899         hi2c->State= HAL_I2C_STATE_READY;
04900
04901         /* Process Unlocked */
04902         __HAL_UNLOCK(hi2c);
04903
04904         return HAL_TIMEOUT;
04905       }
04906     }
04907   }
04908   return HAL_OK;
04909 }
04910
04911 /**
04912   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
04913   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04914   *                the configuration information for the specified I2C.
04915   * @param  Timeout Timeout duration
04916   * @retval HAL status
04917   */
04918 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
04919 {
04920   uint32_t tickstart = 0x00U;
04921   tickstart = HAL_GetTick();
04922
04923   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04924   {
04925     /* Check if a NACK is detected */
04926     if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
04927     {
04928       return HAL_ERROR;
04929     }
04930
04931     /* Check for the Timeout */
04932     if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04933     {
04934       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04935       hi2c->PreviousState = I2C_STATE_NONE;
04936       hi2c->State= HAL_I2C_STATE_READY;
04937
04938       /* Process Unlocked */
04939       __HAL_UNLOCK(hi2c);
04940
04941       return HAL_TIMEOUT;
04942     }
04943   }
04944   return HAL_OK;
04945 }
04946
04947 /**
04948   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
04949   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04950   *                the configuration information for the specified I2C.
04951   * @param  Timeout Timeout duration
04952   * @retval HAL status
04953   */
04954 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
04955 {
04956   uint32_t tickstart = 0x00U;
04957   tickstart = HAL_GetTick();
04958
04959   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
04960   {
04961     /* Check if a STOPF is detected */
04962     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
04963     {
04964       /* Clear STOP Flag */
04965       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04966
04967       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04968       hi2c->PreviousState = I2C_STATE_NONE;
04969       hi2c->State= HAL_I2C_STATE_READY;
04970
04971       /* Process Unlocked */
04972       __HAL_UNLOCK(hi2c);
04973
04974       return HAL_ERROR;
04975     }
04976
04977     /* Check for the Timeout */
04978     if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
04979     {
04980       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04981       hi2c->State= HAL_I2C_STATE_READY;
04982
04983       /* Process Unlocked */
04984       __HAL_UNLOCK(hi2c);
04985
04986       return HAL_TIMEOUT;
04987     }
04988   }
04989   return HAL_OK;
04990 }
04991
04992 /**
04993   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
04994   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04995   *                the configuration information for the specified I2C.
04996   * @retval HAL status
04997   */
04998 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
04999 {
05000   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
05001   {
05002     /* Clear NACKF Flag */
05003     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05004
05005     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
05006     hi2c->PreviousState = I2C_STATE_NONE;
05007     hi2c->State= HAL_I2C_STATE_READY;
05008
05009     /* Process Unlocked */
05010     __HAL_UNLOCK(hi2c);
05011
05012     return HAL_ERROR;
05013   }
05014   return HAL_OK;
05015 }
05016 /**
05017   * @}
05018   */
05019
05020 #endif /* HAL_I2C_MODULE_ENABLED */
05021
05022 /**
05023   * @}
05024   */
05025
05026 /**
05027   * @}
05028   */
05029
05030 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c.h Source File

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stm32f4xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of I2C HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_I2C_H
00040 #define __STM32F4xx_HAL_I2C_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2C
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2C_Exported_Types I2C Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  I2C Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
00068                                   This parameter must be set to a value lower than 400kHz */
00069
00070   uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
00071                                   This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
00072
00073   uint32_t OwnAddress1;      /*!< Specifies the first device own address.
00074                                   This parameter can be a 7-bit or 10-bit address. */
00075
00076   uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00077                                   This parameter can be a value of @ref I2C_addressing_mode */
00078
00079   uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
00080                                   This parameter can be a value of @ref I2C_dual_addressing_mode */
00081
00082   uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
00083                                   This parameter can be a 7-bit address. */
00084
00085   uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
00086                                   This parameter can be a value of @ref I2C_general_call_addressing_mode */
00087
00088   uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
00089                                   This parameter can be a value of @ref I2C_nostretch_mode */
00090
00091 }I2C_InitTypeDef;
00092
00093 /**
00094   * @brief  HAL State structures definition
00095   */
00096 typedef enum
00097 {
00098   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00099   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00100   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00101   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00102   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00103   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00104   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00105                                                  process is ongoing                         */
00106   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00107                                                  process is ongoing                         */
00108   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00109   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00110
00111 }HAL_I2C_StateTypeDef;
00112
00113 /**
00114   * @brief  HAL State structures definition
00115   */
00116 typedef enum
00117 {
00118   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00119   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00120   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00121   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00122
00123 }HAL_I2C_ModeTypeDef;
00124
00125 /**
00126   * @brief  I2C handle Structure definition
00127   */
00128 typedef struct
00129 {
00130   I2C_TypeDef                *Instance;     /*!< I2C registers base address                */
00131
00132   I2C_InitTypeDef            Init;          /*!< I2C communication parameters              */
00133
00134   uint8_t                    *pBuffPtr;     /*!< Pointer to I2C transfer buffer            */
00135
00136   uint16_t                   XferSize;      /*!< I2C transfer size                         */
00137
00138   __IO uint16_t              XferCount;     /*!< I2C transfer counter                      */
00139
00140   __IO uint32_t              XferOptions;   /*!< I2C transfer options                      */
00141
00142   __IO uint32_t              PreviousState; /*!< I2C communication Previous state and mode
00143                                                  context for internal usage                */
00144
00145   DMA_HandleTypeDef          *hdmatx;       /*!< I2C Tx DMA handle parameters              */
00146
00147   DMA_HandleTypeDef          *hdmarx;       /*!< I2C Rx DMA handle parameters              */
00148
00149   HAL_LockTypeDef            Lock;          /*!< I2C locking object                        */
00150
00151   __IO HAL_I2C_StateTypeDef  State;         /*!< I2C communication state                   */
00152
00153   __IO HAL_I2C_ModeTypeDef   Mode;          /*!< I2C communication mode                    */
00154
00155   __IO uint32_t              ErrorCode;     /*!< I2C Error code                            */
00156
00157 }I2C_HandleTypeDef;
00158
00159 /**
00160   * @}
00161   */
00162
00163 /* Exported constants --------------------------------------------------------*/
00164 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00165   * @{
00166   */
00167
00168 /** @defgroup I2C_Error_Code I2C Error Code
00169   * @brief    I2C Error Code
00170   * @{
00171   */
00172 #define HAL_I2C_ERROR_NONE       ((uint32_t)0x00000000U)    /*!< No error           */
00173 #define HAL_I2C_ERROR_BERR       ((uint32_t)0x00000001U)    /*!< BERR error         */
00174 #define HAL_I2C_ERROR_ARLO       ((uint32_t)0x00000002U)    /*!< ARLO error         */
00175 #define HAL_I2C_ERROR_AF         ((uint32_t)0x00000004U)    /*!< AF error           */
00176 #define HAL_I2C_ERROR_OVR        ((uint32_t)0x00000008U)    /*!< OVR error          */
00177 #define HAL_I2C_ERROR_DMA        ((uint32_t)0x00000010U)    /*!< DMA transfer error */
00178 #define HAL_I2C_ERROR_TIMEOUT    ((uint32_t)0x00000020U)    /*!< Timeout Error      */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
00184   * @{
00185   */
00186 #define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000U)
00187 #define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup I2C_addressing_mode I2C addressing mode
00193   * @{
00194   */
00195 #define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000U)
00196 #define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
00202   * @{
00203   */
00204 #define I2C_DUALADDRESS_DISABLE        ((uint32_t)0x00000000U)
00205 #define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
00211   * @{
00212   */
00213 #define I2C_GENERALCALL_DISABLE        ((uint32_t)0x00000000U)
00214 #define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup I2C_nostretch_mode I2C nostretch mode
00220   * @{
00221   */
00222 #define I2C_NOSTRETCH_DISABLE          ((uint32_t)0x00000000U)
00223 #define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
00229   * @{
00230   */
00231 #define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)
00232 #define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010U)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup I2C_XferDirection_definition I2C XferDirection definition
00238   * @{
00239   */
00240 #define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000000U)
00241 #define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000001U)
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup I2C_XferOptions_definition I2C XferOptions definition
00247   * @{
00248   */
00249 #define  I2C_FIRST_FRAME                ((uint32_t)0x00000001U)
00250 #define  I2C_NEXT_FRAME                 ((uint32_t)0x00000002U)
00251 #define  I2C_FIRST_AND_LAST_FRAME       ((uint32_t)0x00000004U)
00252 #define  I2C_LAST_FRAME                 ((uint32_t)0x00000008U)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00258   * @{
00259   */
00260 #define I2C_IT_BUF                      I2C_CR2_ITBUFEN
00261 #define I2C_IT_EVT                      I2C_CR2_ITEVTEN
00262 #define I2C_IT_ERR                      I2C_CR2_ITERREN
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup I2C_Flag_definition I2C Flag definition
00268   * @{
00269   */
00270 #define I2C_FLAG_SMBALERT               ((uint32_t)0x00018000U)
00271 #define I2C_FLAG_TIMEOUT                ((uint32_t)0x00014000U)
00272 #define I2C_FLAG_PECERR                 ((uint32_t)0x00011000U)
00273 #define I2C_FLAG_OVR                    ((uint32_t)0x00010800U)
00274 #define I2C_FLAG_AF                     ((uint32_t)0x00010400U)
00275 #define I2C_FLAG_ARLO                   ((uint32_t)0x00010200U)
00276 #define I2C_FLAG_BERR                   ((uint32_t)0x00010100U)
00277 #define I2C_FLAG_TXE                    ((uint32_t)0x00010080U)
00278 #define I2C_FLAG_RXNE                   ((uint32_t)0x00010040U)
00279 #define I2C_FLAG_STOPF                  ((uint32_t)0x00010010U)
00280 #define I2C_FLAG_ADD10                  ((uint32_t)0x00010008U)
00281 #define I2C_FLAG_BTF                    ((uint32_t)0x00010004U)
00282 #define I2C_FLAG_ADDR                   ((uint32_t)0x00010002U)
00283 #define I2C_FLAG_SB                     ((uint32_t)0x00010001U)
00284 #define I2C_FLAG_DUALF                  ((uint32_t)0x00100080U)
00285 #define I2C_FLAG_SMBHOST                ((uint32_t)0x00100040U)
00286 #define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00100020U)
00287 #define I2C_FLAG_GENCALL                ((uint32_t)0x00100010U)
00288 #define I2C_FLAG_TRA                    ((uint32_t)0x00100004U)
00289 #define I2C_FLAG_BUSY                   ((uint32_t)0x00100002U)
00290 #define I2C_FLAG_MSL                    ((uint32_t)0x00100001U)
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
00299 /* Exported macro ------------------------------------------------------------*/
00300 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00301   * @{
00302   */
00303
00304 /** @brief Reset I2C handle state
00305   * @param  __HANDLE__: specifies the I2C Handle.
00306   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00307   * @retval None
00308   */
00309 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00310
00311 /** @brief  Enable or disable the specified I2C interrupts.
00312   * @param  __HANDLE__: specifies the I2C Handle.
00313   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00314   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00315   *         This parameter can be one of the following values:
00316   *            @arg I2C_IT_BUF: Buffer interrupt enable
00317   *            @arg I2C_IT_EVT: Event interrupt enable
00318   *            @arg I2C_IT_ERR: Error interrupt enable
00319   * @retval None
00320   */
00321 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00322 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
00323
00324 /** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
00325   * @param  __HANDLE__: specifies the I2C Handle.
00326   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00327   * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
00328   *          This parameter can be one of the following values:
00329   *            @arg I2C_IT_BUF: Buffer interrupt enable
00330   *            @arg I2C_IT_EVT: Event interrupt enable
00331   *            @arg I2C_IT_ERR: Error interrupt enable
00332   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00333   */
00334 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00335
00336 /** @brief  Checks whether the specified I2C flag is set or not.
00337   * @param  __HANDLE__: specifies the I2C Handle.
00338   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00339   * @param  __FLAG__: specifies the flag to check.
00340   *         This parameter can be one of the following values:
00341   *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
00342   *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
00343   *            @arg I2C_FLAG_PECERR: PEC error in reception flag
00344   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
00345   *            @arg I2C_FLAG_AF: Acknowledge failure flag
00346   *            @arg I2C_FLAG_ARLO: Arbitration lost flag
00347   *            @arg I2C_FLAG_BERR: Bus error flag
00348   *            @arg I2C_FLAG_TXE: Data register empty flag
00349   *            @arg I2C_FLAG_RXNE: Data register not empty flag
00350   *            @arg I2C_FLAG_STOPF: Stop detection flag
00351   *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
00352   *            @arg I2C_FLAG_BTF: Byte transfer finished flag
00353   *            @arg I2C_FLAG_ADDR: Address sent flag
00354   *                                Address matched flag
00355   *            @arg I2C_FLAG_SB: Start bit flag
00356   *            @arg I2C_FLAG_DUALF: Dual flag
00357   *            @arg I2C_FLAG_SMBHOST: SMBus host header
00358   *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
00359   *            @arg I2C_FLAG_GENCALL: General call header flag
00360   *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
00361   *            @arg I2C_FLAG_BUSY: Bus busy flag
00362   *            @arg I2C_FLAG_MSL: Master/Slave flag
00363   * @retval The new state of __FLAG__ (TRUE or FALSE).
00364   */
00365 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
00366                                                  ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
00367
00368 /** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
00369   * @param  __HANDLE__: specifies the I2C Handle.
00370   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00371   * @param  __FLAG__: specifies the flag to clear.
00372   *         This parameter can be any combination of the following values:
00373   *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
00374   *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
00375   *            @arg I2C_FLAG_PECERR: PEC error in reception flag
00376   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
00377   *            @arg I2C_FLAG_AF: Acknowledge failure flag
00378   *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
00379   *            @arg I2C_FLAG_BERR: Bus error flag
00380   * @retval None
00381   */
00382 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
00383
00384 /** @brief  Clears the I2C ADDR pending flag.
00385   * @param  __HANDLE__: specifies the I2C Handle.
00386   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00387   * @retval None
00388   */
00389 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
00390   do{                                           \
00391     __IO uint32_t tmpreg = 0x00U;               \
00392     tmpreg = (__HANDLE__)->Instance->SR1;       \
00393     tmpreg = (__HANDLE__)->Instance->SR2;       \
00394     UNUSED(tmpreg);                             \
00395   } while(0)
00396
00397 /** @brief  Clears the I2C STOPF pending flag.
00398   * @param  __HANDLE__: specifies the I2C Handle.
00399   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00400   * @retval None
00401   */
00402 #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)    \
00403   do{                                           \
00404     __IO uint32_t tmpreg = 0x00U;               \
00405     tmpreg = (__HANDLE__)->Instance->SR1;       \
00406     (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;  \
00407     UNUSED(tmpreg);                             \
00408   } while(0)
00409
00410 /** @brief  Enable the I2C peripheral.
00411   * @param  __HANDLE__: specifies the I2C Handle.
00412   *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
00413   * @retval None
00414   */
00415 #define __HAL_I2C_ENABLE(__HANDLE__)                             ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
00416
00417 /** @brief  Disable the I2C peripheral.
00418   * @param  __HANDLE__: specifies the I2C Handle.
00419   *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
00420   * @retval None
00421   */
00422 #define __HAL_I2C_DISABLE(__HANDLE__)                            ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
00423
00424 /**
00425   * @}
00426   */
00427
00428 /* Include I2C HAL Extension module */
00429 #include "stm32f4xx_hal_i2c_ex.h"
00430
00431 /* Exported functions --------------------------------------------------------*/
00432 /** @addtogroup I2C_Exported_Functions
00433   * @{
00434   */
00435
00436 /** @addtogroup I2C_Exported_Functions_Group1
00437   * @{
00438   */
00439 /* Initialization/de-initialization functions  **********************************/
00440 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00441 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
00442 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00443 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00444 /**
00445   * @}
00446   */
00447
00448 /** @addtogroup I2C_Exported_Functions_Group2
00449   * @{
00450   */
00451 /* I/O operation functions  *****************************************************/
00452 /******* Blocking mode: Polling */
00453 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00454 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00455 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00456 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00457 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00458 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00459 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00460
00461 /******* Non-Blocking mode: Interrupt */
00462 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00463 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00464 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00465 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00466 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00467 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00468
00469 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00470 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00471 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00472 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00473 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00474 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00475 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00476
00477 /******* Non-Blocking mode: DMA */
00478 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00479 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00480 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00481 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00482 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00483 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00484
00485 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00486 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00487 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00488 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00489 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00490 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00491 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00492 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00493 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00494 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00495 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00496 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00497 /**
00498   * @}
00499   */
00500
00501 /** @addtogroup I2C_Exported_Functions_Group3
00502   * @{
00503   */
00504 /* Peripheral State, Mode and Errors functions  *********************************/
00505 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00506 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00507 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00508
00509 /**
00510   * @}
00511   */
00512
00513 /**
00514   * @}
00515   */
00516 /* Private types -------------------------------------------------------------*/
00517 /* Private variables ---------------------------------------------------------*/
00518 /* Private constants ---------------------------------------------------------*/
00519 /** @defgroup I2C_Private_Constants I2C Private Constants
00520   * @{
00521   */
00522 #define I2C_FLAG_MASK  ((uint32_t)0x0000FFFFU)
00523 /**
00524   * @}
00525   */
00526
00527 /* Private macros ------------------------------------------------------------*/
00528 /** @defgroup I2C_Private_Macros I2C Private Macros
00529   * @{
00530   */
00531
00532 #define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
00533 #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
00534 #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
00535 #define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
00536 #define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
00537                                                                   ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
00538                                                                   ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
00539
00540 #define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
00541 #define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
00542
00543 #define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00544 #define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
00545 #define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
00546
00547 #define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00548 #define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00549
00550 /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
00551   * @{
00552   */
00553 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
00554                                   ((CYCLE) == I2C_DUTYCYCLE_16_9))
00555 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
00556                                          ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
00557 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00558                                       ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00559 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
00560                                    ((CALL) == I2C_GENERALCALL_ENABLE))
00561 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00562                                     ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00563 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00564                                   ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00565 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
00566 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
00567 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
00568 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
00569                                                        ((REQUEST) == I2C_NEXT_FRAME)               || \
00570                                                        ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
00571                                                        ((REQUEST) == I2C_LAST_FRAME))
00572 /**
00573   * @}
00574   */
00575
00576 /**
00577   * @}
00578   */
00579
00580 /* Private functions ---------------------------------------------------------*/
00581 /** @defgroup I2C_Private_Functions I2C Private Functions
00582   * @{
00583   */
00584
00585 /**
00586   * @}
00587   */
00588
00589 /**
00590   * @}
00591   */
00592
00593 /**
00594   * @}
00595   */
00596
00597 #ifdef __cplusplus
00598 }
00599 #endif
00600
00601
00602 #endif /* __STM32F4xx_HAL_I2C_H */
00603
00604 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c_ex.c Source File

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stm32f4xx_hal_i2c_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   I2C Extension HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of I2C extension peripheral:
00010   *           + Extension features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### I2C peripheral extension features  #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/
00018        429xx/439xx devices contains the following additional features :
00019
00020        (+) Possibility to disable or enable Analog Noise Filter
00021        (+) Use of a configured Digital Noise Filter
00022
00023                      ##### How to use this driver #####
00024   ==============================================================================
00025   [..] This driver provides functions to configure Noise Filter
00026     (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config()
00027     (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config()
00028
00029   @endverbatim
00030   ******************************************************************************
00031   * @attention
00032   *
00033   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00034   *
00035   * Redistribution and use in source and binary forms, with or without modification,
00036   * are permitted provided that the following conditions are met:
00037   *   1. Redistributions of source code must retain the above copyright notice,
00038   *      this list of conditions and the following disclaimer.
00039   *   2. Redistributions in binary form must reproduce the above copyright notice,
00040   *      this list of conditions and the following disclaimer in the documentation
00041   *      and/or other materials provided with the distribution.
00042   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00043   *      may be used to endorse or promote products derived from this software
00044   *      without specific prior written permission.
00045   *
00046   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00047   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00048   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00049   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00050   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00051   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00052   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00053   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00054   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00055   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00056   *
00057   ******************************************************************************
00058   */
00059
00060 /* Includes ------------------------------------------------------------------*/
00061 #include "stm32f4xx_hal.h"
00062
00063 /** @addtogroup STM32F4xx_HAL_Driver
00064   * @{
00065   */
00066
00067 /** @defgroup I2CEx I2CEx
00068   * @brief I2C HAL module driver
00069   * @{
00070   */
00071
00072 #ifdef HAL_I2C_MODULE_ENABLED
00073
00074 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00075     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
00076     defined(STM32F469xx) || defined(STM32F479xx)
00077 /* Private typedef -----------------------------------------------------------*/
00078 /* Private define ------------------------------------------------------------*/
00079 /* Private macro -------------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 /* Exported functions --------------------------------------------------------*/
00083 /** @defgroup I2CEx_Exported_Functions I2C Exported Functions
00084   * @{
00085   */
00086
00087
00088 /** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions
00089  *  @brief   Extension features functions
00090  *
00091 @verbatim
00092  ===============================================================================
00093                       ##### Extension features functions #####
00094  ===============================================================================
00095     [..] This section provides functions allowing to:
00096       (+) Configure Noise Filters
00097
00098 @endverbatim
00099   * @{
00100   */
00101
00102 /**
00103   * @brief  Configures I2C Analog noise filter.
00104   * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
00105   *                the configuration information for the specified I2Cx peripheral.
00106   * @param  AnalogFilter: new state of the Analog filter.
00107   * @retval HAL status
00108   */
00109 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00110 {
00111   /* Check the parameters */
00112   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00113   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00114
00115   if(hi2c->State == HAL_I2C_STATE_READY)
00116   {
00117     hi2c->State = HAL_I2C_STATE_BUSY;
00118
00119     /* Disable the selected I2C peripheral */
00120     __HAL_I2C_DISABLE(hi2c);
00121
00122     /* Reset I2Cx ANOFF bit */
00123     hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
00124
00125     /* Disable the analog filter */
00126     hi2c->Instance->FLTR |= AnalogFilter;
00127
00128     __HAL_I2C_ENABLE(hi2c);
00129
00130     hi2c->State = HAL_I2C_STATE_READY;
00131
00132     return HAL_OK;
00133   }
00134   else
00135   {
00136     return HAL_BUSY;
00137   }
00138 }
00139
00140 /**
00141   * @brief  Configures I2C Digital noise filter.
00142   * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
00143   *                the configuration information for the specified I2Cx peripheral.
00144   * @param  DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
00145   * @retval HAL status
00146   */
00147 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00148 {
00149   uint16_t tmpreg = 0U;
00150
00151   /* Check the parameters */
00152   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00153   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00154
00155   if(hi2c->State == HAL_I2C_STATE_READY)
00156   {
00157     hi2c->State = HAL_I2C_STATE_BUSY;
00158
00159     /* Disable the selected I2C peripheral */
00160     __HAL_I2C_DISABLE(hi2c);
00161
00162     /* Get the old register value */
00163     tmpreg = hi2c->Instance->FLTR;
00164
00165     /* Reset I2Cx DNF bit [3:0] */
00166     tmpreg &= ~(I2C_FLTR_DNF);
00167
00168     /* Set I2Cx DNF coefficient */
00169     tmpreg |= DigitalFilter;
00170
00171     /* Store the new register value */
00172     hi2c->Instance->FLTR = tmpreg;
00173
00174     __HAL_I2C_ENABLE(hi2c);
00175
00176     hi2c->State = HAL_I2C_STATE_READY;
00177
00178     return HAL_OK;
00179   }
00180   else
00181   {
00182     return HAL_BUSY;
00183   }
00184 }
00185
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @}
00192   */
00193 #endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
00194           STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx */
00195
00196 #endif /* HAL_I2C_MODULE_ENABLED */
00197 /**
00198   * @}
00199   */
00200
00201 /**
00202   * @}
00203   */
00204
00205 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2c_ex.h Source File

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stm32f4xx_hal_i2c_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of I2C HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_I2C_EX_H
00040 #define __STM32F4xx_HAL_I2C_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00047     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
00048     defined(STM32F469xx) || defined(STM32F479xx)
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_hal_def.h"
00051
00052 /** @addtogroup STM32F4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup I2CEx
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /* Exported constants --------------------------------------------------------*/
00062 /** @defgroup I2CEx_Exported_Constants I2C Exported Constants
00063   * @{
00064   */
00065
00066 /** @defgroup I2CEx_Analog_Filter I2C Analog Filter
00067   * @{
00068   */
00069 #define I2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000U)
00070 #define I2C_ANALOGFILTER_DISABLE       I2C_FLTR_ANOFF
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported macro ------------------------------------------------------------*/
00080 /* Exported functions --------------------------------------------------------*/
00081 /** @addtogroup I2CEx_Exported_Functions
00082   * @{
00083   */
00084
00085 /** @addtogroup I2CEx_Exported_Functions_Group1
00086   * @{
00087   */
00088 /* Peripheral Control functions  ************************************************/
00089 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00090 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098 /* Private types -------------------------------------------------------------*/
00099 /* Private variables ---------------------------------------------------------*/
00100 /* Private constants ---------------------------------------------------------*/
00101 /** @defgroup I2CEx_Private_Constants I2C Private Constants
00102   * @{
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /* Private macros ------------------------------------------------------------*/
00110 /** @defgroup I2CEx_Private_Macros I2C Private Macros
00111   * @{
00112   */
00113 #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00114                                       ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00115 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /**
00125   * @}
00126   */
00127
00128 #endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
00129           STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00130
00131 #ifdef __cplusplus
00132 }
00133 #endif
00134
00135 #endif /* __STM32F4xx_HAL_I2C_EX_H */
00136
00137
00138 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s.c Source File

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stm32f4xx_hal_i2s.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   I2S HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   @verbatim
00014  ===============================================================================
00015                   ##### How to use this driver #####
00016  ===============================================================================
00017  [..]
00018     The I2S HAL driver can be used as follow:
00019
00020     (#) Declare a I2S_HandleTypeDef handle structure.
00021     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00022         (##) Enable the SPIx interface clock.
00023         (##) I2S pins configuration:
00024             (+++) Enable the clock for the I2S GPIOs.
00025             (+++) Configure these I2S pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00027              and HAL_I2S_Receive_IT() APIs).
00028             (+++) Configure the I2Sx interrupt priority.
00029             (+++) Enable the NVIC I2S IRQ handle.
00030         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00031              and HAL_I2S_Receive_DMA() APIs:
00032             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00033             (+++) Enable the DMAx interface clock.
00034             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00035             (+++) Configure the DMA Tx/Rx Stream.
00036             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
00037             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00038                 DMA Tx/Rx Stream.
00039
00040    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00041        using HAL_I2S_Init() function.
00042
00043    -@- The specific I2S interrupts (Transmission complete interrupt,
00044        RXNE interrupt and Error Interrupts) will be managed using the macros
00045        __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
00046    -@- Make sure that either:
00047         (+@) I2S PLL is configured or
00048         (+@) External clock source is configured after setting correctly
00049              the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
00050
00051    (#) Three operation modes are available within this driver :
00052
00053    *** Polling mode IO operation ***
00054    =================================
00055    [..]
00056      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00057      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00058
00059    *** Interrupt mode IO operation ***
00060    ===================================
00061    [..]
00062      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00063      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00064          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00065      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00066          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00067      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00068      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00069          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00070      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00071          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00072      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00073          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00074
00075    *** DMA mode IO operation ***
00076    ==============================
00077    [..]
00078      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00079      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00080          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00081      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00082          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00083      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00084      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00085          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00086      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00087          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00088      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00089          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00090      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00091      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00092      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00093
00094    *** I2S HAL driver macros list ***
00095    =============================================
00096    [..]
00097      Below the list of most used macros in USART HAL driver.
00098
00099       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00100       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00101       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00102       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00103       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00104
00105     [..]
00106       (@) You can refer to the I2S HAL driver header file for more useful macros
00107
00108   @endverbatim
00109   ******************************************************************************
00110   * @attention
00111   *
00112   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00113   *
00114   * Redistribution and use in source and binary forms, with or without modification,
00115   * are permitted provided that the following conditions are met:
00116   *   1. Redistributions of source code must retain the above copyright notice,
00117   *      this list of conditions and the following disclaimer.
00118   *   2. Redistributions in binary form must reproduce the above copyright notice,
00119   *      this list of conditions and the following disclaimer in the documentation
00120   *      and/or other materials provided with the distribution.
00121   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00122   *      may be used to endorse or promote products derived from this software
00123   *      without specific prior written permission.
00124   *
00125   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00126   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00127   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00128   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00129   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00130   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00131   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00132   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00133   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00134   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00135   *
00136   ******************************************************************************
00137   */
00138
00139 /* Includes ------------------------------------------------------------------*/
00140 #include "stm32f4xx_hal.h"
00141
00142 /** @addtogroup STM32F4xx_HAL_Driver
00143   * @{
00144   */
00145
00146 /** @defgroup I2S I2S
00147   * @brief I2S HAL module driver
00148   * @{
00149   */
00150
00151 #ifdef HAL_I2S_MODULE_ENABLED
00152
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /* Private macro -------------------------------------------------------------*/
00156 /* Private variables ---------------------------------------------------------*/
00157 /* Private function prototypes -----------------------------------------------*/
00158 /** @addtogroup I2S_Private_Functions
00159   * @{
00160   */
00161
00162 /**
00163   * @}
00164   */
00165
00166 /* Exported functions --------------------------------------------------------*/
00167 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00168   * @{
00169   */
00170
00171 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00172  *  @brief    Initialization and Configuration functions
00173  *
00174 @verbatim
00175  ===============================================================================
00176               ##### Initialization and de-initialization functions #####
00177  ===============================================================================
00178     [..]  This subsection provides a set of functions allowing to initialize and
00179           de-initialize the I2Sx peripheral in simplex mode:
00180
00181       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00182           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00183
00184       (+) Call the function HAL_I2S_Init() to configure the selected device with
00185           the selected configuration:
00186         (++) Mode
00187         (++) Standard
00188         (++) Data Format
00189         (++) MCLK Output
00190         (++) Audio frequency
00191         (++) Polarity
00192
00193       (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00194           of the selected I2Sx peripheral.
00195 @endverbatim
00196   * @{
00197   */
00198
00199 /**
00200   * @brief Initializes the I2S according to the specified parameters
00201   *         in the I2S_InitTypeDef and create the associated handle.
00202   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00203   *         the configuration information for I2S module
00204   * @retval HAL status
00205   */
00206 __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00207 {
00208   uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
00209   uint32_t tmp = 0U, i2sclk = 0U;
00210
00211   /* Check the I2S handle allocation */
00212   if(hi2s == NULL)
00213   {
00214     return HAL_ERROR;
00215   }
00216
00217   /* Check the I2S parameters */
00218   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00219   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00220   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00221   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00222   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00223   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00224   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00225   assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
00226
00227   if(hi2s->State == HAL_I2S_STATE_RESET)
00228   {
00229     /* Allocate lock resource and initialize it */
00230     hi2s->Lock = HAL_UNLOCKED;
00231     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00232     HAL_I2S_MspInit(hi2s);
00233   }
00234
00235   hi2s->State = HAL_I2S_STATE_BUSY;
00236
00237   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
00238   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00239   hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00240                                SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00241                                SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
00242   hi2s->Instance->I2SPR = 0x0002U;
00243
00244   /* Get the I2SCFGR register value */
00245   tmpreg = hi2s->Instance->I2SCFGR;
00246
00247   /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
00248   /* If the requested audio frequency is not the default, compute the prescaler */
00249   if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
00250   {
00251     /* Check the frame length (For the Prescaler computing) *******************/
00252     if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00253     {
00254       /* Packet length is 32 bits */
00255       packetlength = 2U;
00256     }
00257
00258     /* Get I2S source Clock frequency  ****************************************/
00259     /* If an external I2S clock has to be used, the specific define should be set
00260     in the project configuration or in the stm32f4xx_conf.h file */
00261     i2sclk = I2S_GetInputClock(hi2s);
00262
00263     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00264     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00265     {
00266       /* MCLK output is enabled */
00267       tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00268     }
00269     else
00270     {
00271       /* MCLK output is disabled */
00272       tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U) / hi2s->Init.AudioFreq)) + 5U);
00273     }
00274
00275     /* Remove the flatting point */
00276     tmp = tmp / 10U;
00277
00278     /* Check the parity of the divider */
00279     i2sodd = (uint32_t)(tmp & (uint32_t)1U);
00280
00281     /* Compute the i2sdiv prescaler */
00282     i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
00283
00284     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00285     i2sodd = (uint32_t) (i2sodd << 8U);
00286   }
00287
00288   /* Test if the divider is 1 or 0 or greater than 0xFF */
00289   if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00290   {
00291     /* Set the default values */
00292     i2sdiv = 2U;
00293     i2sodd = 0U;
00294   }
00295
00296   /* Write to SPIx I2SPR register the computed value */
00297   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
00298
00299   /* Configure the I2S with the I2S_InitStruct values */
00300   tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
00301
00302 #if defined(SPI_I2SCFGR_ASTRTEN)
00303   if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
00304   {
00305   /* Write to SPIx I2SCFGR */
00306   hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
00307   }
00308   else
00309   {
00310   /* Write to SPIx I2SCFGR */
00311   hi2s->Instance->I2SCFGR = tmpreg;
00312   }
00313 #else
00314   /* Write to SPIx I2SCFGR */
00315   hi2s->Instance->I2SCFGR = tmpreg;
00316 #endif
00317
00318   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00319   hi2s->State= HAL_I2S_STATE_READY;
00320
00321   return HAL_OK;
00322 }
00323
00324 /**
00325   * @brief DeInitializes the I2S peripheral
00326   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00327   *         the configuration information for I2S module
00328   * @retval HAL status
00329   */
00330 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00331 {
00332   /* Check the I2S handle allocation */
00333   if(hi2s == NULL)
00334   {
00335     return HAL_ERROR;
00336   }
00337
00338   hi2s->State = HAL_I2S_STATE_BUSY;
00339
00340   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00341   HAL_I2S_MspDeInit(hi2s);
00342
00343   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00344   hi2s->State = HAL_I2S_STATE_RESET;
00345
00346   /* Release Lock */
00347   __HAL_UNLOCK(hi2s);
00348
00349   return HAL_OK;
00350 }
00351
00352 /**
00353   * @brief I2S MSP Init
00354   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00355   *         the configuration information for I2S module
00356   * @retval None
00357   */
00358  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00359 {
00360   /* Prevent unused argument(s) compilation warning */
00361   UNUSED(hi2s);
00362   /* NOTE : This function Should not be modified, when the callback is needed,
00363             the HAL_I2S_MspInit could be implemented in the user file
00364    */
00365 }
00366
00367 /**
00368   * @brief I2S MSP DeInit
00369   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00370   *         the configuration information for I2S module
00371   * @retval None
00372   */
00373  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00374 {
00375   /* Prevent unused argument(s) compilation warning */
00376   UNUSED(hi2s);
00377   /* NOTE : This function Should not be modified, when the callback is needed,
00378             the HAL_I2S_MspDeInit could be implemented in the user file
00379    */
00380 }
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00386  *  @brief    Data transfers functions
00387  *
00388 @verbatim
00389  ===============================================================================
00390                       ##### IO operation functions #####
00391  ===============================================================================
00392     [..]
00393     This subsection provides a set of functions allowing to manage the I2S data
00394     transfers.
00395
00396     (#) There are two modes of transfer:
00397        (++) Blocking mode : The communication is performed in the polling mode.
00398             The status of all data processing is returned by the same function
00399             after finishing transfer.
00400        (++) No-Blocking mode : The communication is performed using Interrupts
00401             or DMA. These functions return the status of the transfer startup.
00402             The end of the data processing will be indicated through the
00403             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00404             using DMA mode.
00405
00406     (#) Blocking mode functions are :
00407         (++) HAL_I2S_Transmit()
00408         (++) HAL_I2S_Receive()
00409
00410     (#) No-Blocking mode functions with Interrupt are :
00411         (++) HAL_I2S_Transmit_IT()
00412         (++) HAL_I2S_Receive_IT()
00413
00414     (#) No-Blocking mode functions with DMA are :
00415         (++) HAL_I2S_Transmit_DMA()
00416         (++) HAL_I2S_Receive_DMA()
00417
00418     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00419         (++) HAL_I2S_TxCpltCallback()
00420         (++) HAL_I2S_RxCpltCallback()
00421         (++) HAL_I2S_ErrorCallback()
00422
00423 @endverbatim
00424   * @{
00425   */
00426
00427 /**
00428   * @brief Transmit an amount of data in blocking mode
00429   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00430   *         the configuration information for I2S module
00431   * @param pData: a 16-bit pointer to data buffer.
00432   * @param Size: number of data sample to be sent:
00433   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00434   *       configuration phase, the Size parameter means the number of 16-bit data length
00435   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00436   *       the Size parameter means the number of 16-bit data length.
00437   * @param  Timeout: Timeout duration
00438   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00439   *       between Master and Slave(example: audio streaming).
00440   * @retval HAL status
00441   */
00442 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00443 {
00444   uint32_t tmp1 = 0U;
00445   if((pData == NULL ) || (Size == 0U))
00446   {
00447     return  HAL_ERROR;
00448   }
00449
00450   if(hi2s->State == HAL_I2S_STATE_READY)
00451   {
00452     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00453     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00454     {
00455       hi2s->TxXferSize = Size*2U;
00456       hi2s->TxXferCount = Size*2U;
00457     }
00458     else
00459     {
00460       hi2s->TxXferSize = Size;
00461       hi2s->TxXferCount = Size;
00462     }
00463
00464     /* Process Locked */
00465     __HAL_LOCK(hi2s);
00466
00467     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00468
00469     /* Check if the I2S is already enabled */
00470     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00471     {
00472       /* Enable I2S peripheral */
00473       __HAL_I2S_ENABLE(hi2s);
00474     }
00475
00476     while(hi2s->TxXferCount > 0U)
00477     {
00478       hi2s->Instance->DR = (*pData++);
00479       hi2s->TxXferCount--;
00480       /* Wait until TXE flag is set */
00481       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
00482       {
00483         return HAL_TIMEOUT;
00484       }
00485     }
00486     /* Check if Slave mode is selected */
00487     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
00488     {
00489       /* Wait until Busy flag is reset */
00490       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
00491       {
00492         return HAL_TIMEOUT;
00493       }
00494     }
00495     hi2s->State = HAL_I2S_STATE_READY;
00496
00497     /* Process Unlocked */
00498     __HAL_UNLOCK(hi2s);
00499
00500     return HAL_OK;
00501   }
00502   else
00503   {
00504     return HAL_BUSY;
00505   }
00506 }
00507
00508 /**
00509   * @brief Receive an amount of data in blocking mode
00510   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00511   *         the configuration information for I2S module
00512   * @param pData: a 16-bit pointer to data buffer.
00513   * @param Size: number of data sample to be sent:
00514   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00515   *       configuration phase, the Size parameter means the number of 16-bit data length
00516   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00517   *       the Size parameter means the number of 16-bit data length.
00518   * @param Timeout: Timeout duration
00519   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00520   *       between Master and Slave(example: audio streaming).
00521   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00522   *       in continuous way and as the I2S is not disabled at the end of the I2S transaction.
00523   * @retval HAL status
00524   */
00525 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00526 {
00527   uint32_t tmp1 = 0U;
00528   if((pData == NULL ) || (Size == 0U))
00529   {
00530     return  HAL_ERROR;
00531   }
00532
00533   if(hi2s->State == HAL_I2S_STATE_READY)
00534   {
00535     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00536     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00537     {
00538       hi2s->RxXferSize = Size*2U;
00539       hi2s->RxXferCount = Size*2U;
00540     }
00541     else
00542     {
00543       hi2s->RxXferSize = Size;
00544       hi2s->RxXferCount = Size;
00545     }
00546     /* Process Locked */
00547     __HAL_LOCK(hi2s);
00548
00549     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00550
00551     /* Check if the I2S is already enabled */
00552     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00553     {
00554       /* Enable I2S peripheral */
00555       __HAL_I2S_ENABLE(hi2s);
00556     }
00557
00558     /* Check if Master Receiver mode is selected */
00559     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00560     {
00561       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00562       access to the SPI_SR register. */
00563       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00564     }
00565
00566     /* Receive data */
00567     while(hi2s->RxXferCount > 0U)
00568     {
00569       /* Wait until RXNE flag is set */
00570       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00571       {
00572         return HAL_TIMEOUT;
00573       }
00574
00575       (*pData++) = hi2s->Instance->DR;
00576       hi2s->RxXferCount--;
00577     }
00578
00579     hi2s->State = HAL_I2S_STATE_READY;
00580
00581     /* Process Unlocked */
00582     __HAL_UNLOCK(hi2s);
00583
00584     return HAL_OK;
00585   }
00586   else
00587   {
00588     return HAL_BUSY;
00589   }
00590 }
00591
00592 /**
00593   * @brief Transmit an amount of data in non-blocking mode with Interrupt
00594   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00595   *         the configuration information for I2S module
00596   * @param pData: a 16-bit pointer to data buffer.
00597   * @param Size: number of data sample to be sent:
00598   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00599   *       configuration phase, the Size parameter means the number of 16-bit data length
00600   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00601   *       the Size parameter means the number of 16-bit data length.
00602   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00603   *       between Master and Slave(example: audio streaming).
00604   * @retval HAL status
00605   */
00606 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00607 {
00608   uint32_t tmp1 = 0U;
00609   if(hi2s->State == HAL_I2S_STATE_READY)
00610   {
00611     if((pData == NULL) || (Size == 0U))
00612     {
00613       return  HAL_ERROR;
00614     }
00615
00616     hi2s->pTxBuffPtr = pData;
00617     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00618     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00619     {
00620       hi2s->TxXferSize = Size*2U;
00621       hi2s->TxXferCount = Size*2U;
00622     }
00623     else
00624     {
00625       hi2s->TxXferSize = Size;
00626       hi2s->TxXferCount = Size;
00627     }
00628
00629     /* Process Locked */
00630     __HAL_LOCK(hi2s);
00631
00632     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00633     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00634
00635     /* Enable TXE and ERR interrupt */
00636     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00637
00638     /* Check if the I2S is already enabled */
00639     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00640     {
00641       /* Enable I2S peripheral */
00642       __HAL_I2S_ENABLE(hi2s);
00643     }
00644
00645     /* Process Unlocked */
00646     __HAL_UNLOCK(hi2s);
00647
00648     return HAL_OK;
00649   }
00650   else
00651   {
00652     return HAL_BUSY;
00653   }
00654 }
00655
00656 /**
00657   * @brief Receive an amount of data in non-blocking mode with Interrupt
00658   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00659   *         the configuration information for I2S module
00660   * @param pData: a 16-bit pointer to the Receive data buffer.
00661   * @param Size: number of data sample to be sent:
00662   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00663   *       configuration phase, the Size parameter means the number of 16-bit data length
00664   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00665   *       the Size parameter means the number of 16-bit data length.
00666   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00667   *       between Master and Slave(example: audio streaming).
00668   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
00669   * between Master and Slave otherwise the I2S interrupt should be optimized.
00670   * @retval HAL status
00671   */
00672 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00673 {
00674   uint32_t tmp1 = 0U;
00675   if(hi2s->State == HAL_I2S_STATE_READY)
00676   {
00677     if((pData == NULL) || (Size == 0U))
00678     {
00679       return  HAL_ERROR;
00680     }
00681
00682     hi2s->pRxBuffPtr = pData;
00683     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00684     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00685     {
00686       hi2s->RxXferSize = Size*2U;
00687       hi2s->RxXferCount = Size*2U;
00688     }
00689     else
00690     {
00691       hi2s->RxXferSize = Size;
00692       hi2s->RxXferCount = Size;
00693     }
00694     /* Process Locked */
00695     __HAL_LOCK(hi2s);
00696
00697     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00698     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00699
00700     /* Enable TXE and ERR interrupt */
00701     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00702
00703     /* Check if the I2S is already enabled */
00704     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00705     {
00706       /* Enable I2S peripheral */
00707       __HAL_I2S_ENABLE(hi2s);
00708     }
00709
00710     /* Process Unlocked */
00711     __HAL_UNLOCK(hi2s);
00712
00713     return HAL_OK;
00714   }
00715
00716   else
00717   {
00718     return HAL_BUSY;
00719   }
00720 }
00721
00722 /**
00723   * @brief Transmit an amount of data in non-blocking mode with DMA
00724   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00725   *         the configuration information for I2S module
00726   * @param pData: a 16-bit pointer to the Transmit data buffer.
00727   * @param Size: number of data sample to be sent:
00728   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00729   *       configuration phase, the Size parameter means the number of 16-bit data length
00730   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00731   *       the Size parameter means the number of 16-bit data length.
00732   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00733   *       between Master and Slave(example: audio streaming).
00734   * @retval HAL status
00735   */
00736 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00737 {
00738   uint32_t *tmp;
00739   uint32_t tmp1 = 0U;
00740
00741   if((pData == NULL) || (Size == 0U))
00742   {
00743     return  HAL_ERROR;
00744   }
00745
00746   if(hi2s->State == HAL_I2S_STATE_READY)
00747   {
00748     hi2s->pTxBuffPtr = pData;
00749     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00750     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00751     {
00752       hi2s->TxXferSize = Size*2U;
00753       hi2s->TxXferCount = Size*2U;
00754     }
00755     else
00756     {
00757       hi2s->TxXferSize = Size;
00758       hi2s->TxXferCount = Size;
00759     }
00760
00761     /* Process Locked */
00762     __HAL_LOCK(hi2s);
00763
00764     hi2s->State = HAL_I2S_STATE_BUSY_TX;
00765     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00766
00767     /* Set the I2S Tx DMA Half transfer complete callback */
00768     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
00769
00770     /* Set the I2S Tx DMA transfer complete callback */
00771     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
00772
00773     /* Set the DMA error callback */
00774     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
00775
00776     /* Enable the Tx DMA Stream */
00777     tmp = (uint32_t*)&pData;
00778     HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
00779
00780     /* Check if the I2S is already enabled */
00781     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00782     {
00783       /* Enable I2S peripheral */
00784       __HAL_I2S_ENABLE(hi2s);
00785     }
00786
00787      /* Check if the I2S Tx request is already enabled */
00788     if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
00789     {
00790       /* Enable Tx DMA Request */
00791       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00792     }
00793
00794     /* Process Unlocked */
00795     __HAL_UNLOCK(hi2s);
00796
00797     return HAL_OK;
00798   }
00799   else
00800   {
00801     return HAL_BUSY;
00802   }
00803 }
00804
00805 /**
00806   * @brief Receive an amount of data in non-blocking mode with DMA
00807   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00808   *         the configuration information for I2S module
00809   * @param pData: a 16-bit pointer to the Receive data buffer.
00810   * @param Size: number of data sample to be sent:
00811   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00812   *       configuration phase, the Size parameter means the number of 16-bit data length
00813   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00814   *       the Size parameter means the number of 16-bit data length.
00815   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00816   *       between Master and Slave(example: audio streaming).
00817   * @retval HAL status
00818   */
00819 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00820 {
00821   uint32_t *tmp;
00822   uint32_t tmp1 = 0U;
00823
00824   if((pData == NULL) || (Size == 0U))
00825   {
00826     return  HAL_ERROR;
00827   }
00828
00829   if(hi2s->State == HAL_I2S_STATE_READY)
00830   {
00831     hi2s->pRxBuffPtr = pData;
00832     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00833     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00834     {
00835       hi2s->RxXferSize = Size*2U;
00836       hi2s->RxXferCount = Size*2U;
00837     }
00838     else
00839     {
00840       hi2s->RxXferSize = Size;
00841       hi2s->RxXferCount = Size;
00842     }
00843     /* Process Locked */
00844     __HAL_LOCK(hi2s);
00845
00846     hi2s->State = HAL_I2S_STATE_BUSY_RX;
00847     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00848
00849     /* Set the I2S Rx DMA Half transfer complete callback */
00850     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
00851
00852     /* Set the I2S Rx DMA transfer complete callback */
00853     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
00854
00855     /* Set the DMA error callback */
00856     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
00857
00858     /* Check if Master Receiver mode is selected */
00859     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00860     {
00861       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
00862       access to the SPI_SR register. */
00863       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00864     }
00865
00866     /* Enable the Rx DMA Stream */
00867     tmp = (uint32_t*)&pData;
00868     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
00869
00870     /* Check if the I2S is already enabled */
00871     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00872     {
00873       /* Enable I2S peripheral */
00874       __HAL_I2S_ENABLE(hi2s);
00875     }
00876
00877      /* Check if the I2S Rx request is already enabled */
00878     if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
00879     {
00880       /* Enable Rx DMA Request */
00881       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00882     }
00883
00884     /* Process Unlocked */
00885     __HAL_UNLOCK(hi2s);
00886
00887     return HAL_OK;
00888   }
00889   else
00890   {
00891     return HAL_BUSY;
00892   }
00893 }
00894
00895 /**
00896   * @brief Pauses the audio stream playing from the Media.
00897   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00898   *         the configuration information for I2S module
00899   * @retval HAL status
00900   */
00901 __weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
00902 {
00903   /* Process Locked */
00904   __HAL_LOCK(hi2s);
00905
00906   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00907   {
00908     /* Disable the I2S DMA Tx request */
00909     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00910   }
00911   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00912   {
00913     /* Disable the I2S DMA Rx request */
00914     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00915   }
00916   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00917   {
00918     if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
00919     {
00920       /* Disable the I2S DMA Tx request */
00921       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00922     }
00923     else
00924     {
00925       /* Disable the I2S DMA Rx request */
00926       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00927     }
00928   }
00929
00930   /* Process Unlocked */
00931   __HAL_UNLOCK(hi2s);
00932
00933   return HAL_OK;
00934 }
00935
00936 /**
00937   * @brief Resumes the audio stream playing from the Media.
00938   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00939   *         the configuration information for I2S module
00940   * @retval HAL status
00941   */
00942 __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
00943 {
00944   /* Process Locked */
00945   __HAL_LOCK(hi2s);
00946
00947   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00948   {
00949     /* Enable the I2S DMA Tx request */
00950     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00951   }
00952   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00953   {
00954     /* Enable the I2S DMA Rx request */
00955     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00956   }
00957   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00958   {
00959     if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
00960     {
00961       /* Enable the I2S DMA Tx request */
00962       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00963     }
00964     else
00965     {
00966       /* Enable the I2S DMA Rx request */
00967       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00968     }
00969   }
00970
00971   /* If the I2S peripheral is still not enabled, enable it */
00972   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
00973   {
00974     /* Enable I2S peripheral */
00975     __HAL_I2S_ENABLE(hi2s);
00976   }
00977
00978   /* Process Unlocked */
00979   __HAL_UNLOCK(hi2s);
00980
00981   return HAL_OK;
00982 }
00983
00984 /**
00985   * @brief Resumes the audio stream playing from the Media.
00986   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00987   *         the configuration information for I2S module
00988   * @retval HAL status
00989   */
00990 __weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
00991 {
00992   /* Process Locked */
00993   __HAL_LOCK(hi2s);
00994
00995   /* Disable the I2S Tx/Rx DMA requests */
00996   hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
00997   hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
00998
00999   /* Abort the I2S DMA Stream tx */
01000   if(hi2s->hdmatx != NULL)
01001   {
01002     HAL_DMA_Abort(hi2s->hdmatx);
01003   }
01004   /* Abort the I2S DMA Stream rx */
01005   if(hi2s->hdmarx != NULL)
01006   {
01007     HAL_DMA_Abort(hi2s->hdmarx);
01008   }
01009
01010   /* Disable I2S peripheral */
01011   __HAL_I2S_DISABLE(hi2s);
01012
01013   hi2s->State = HAL_I2S_STATE_READY;
01014
01015   /* Process Unlocked */
01016   __HAL_UNLOCK(hi2s);
01017
01018   return HAL_OK;
01019 }
01020
01021 /**
01022   * @brief  This function handles I2S interrupt request.
01023   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01024   *         the configuration information for I2S module
01025   * @retval None
01026   */
01027 __weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01028 {
01029   uint32_t tmp1 = 0U, tmp2 = 0U;
01030
01031     if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
01032     {
01033       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
01034       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
01035       /* I2S in mode Receiver ------------------------------------------------*/
01036       if((tmp1 != RESET) && (tmp2 != RESET))
01037       {
01038         I2S_Receive_IT(hi2s);
01039       }
01040
01041       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
01042       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
01043       /* I2S Overrun error interrupt occurred ---------------------------------*/
01044       if((tmp1 != RESET) && (tmp2 != RESET))
01045       {
01046         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01047         hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
01048       }
01049     }
01050
01051     if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
01052     {
01053       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
01054       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
01055       /* I2S in mode Transmitter -----------------------------------------------*/
01056       if((tmp1 != RESET) && (tmp2 != RESET))
01057       {
01058         I2S_Transmit_IT(hi2s);
01059       }
01060
01061       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
01062       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
01063       /* I2S Underrun error interrupt occurred --------------------------------*/
01064       if((tmp1 != RESET) && (tmp2 != RESET))
01065       {
01066         __HAL_I2S_CLEAR_UDRFLAG(hi2s);
01067         hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
01068     }
01069   }
01070
01071   /* Call the Error call Back in case of Errors */
01072   if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
01073   {
01074     /* Set the I2S state ready to be able to start again the process */
01075     hi2s->State= HAL_I2S_STATE_READY;
01076     HAL_I2S_ErrorCallback(hi2s);
01077   }
01078 }
01079
01080 /**
01081   * @brief Tx Transfer Half completed callbacks
01082   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01083   *         the configuration information for I2S module
01084   * @retval None
01085   */
01086  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01087 {
01088   /* Prevent unused argument(s) compilation warning */
01089   UNUSED(hi2s);
01090   /* NOTE : This function Should not be modified, when the callback is needed,
01091             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01092    */
01093 }
01094
01095 /**
01096   * @brief Tx Transfer completed callbacks
01097   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01098   *         the configuration information for I2S module
01099   * @retval None
01100   */
01101  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01102 {
01103   /* Prevent unused argument(s) compilation warning */
01104   UNUSED(hi2s);
01105   /* NOTE : This function Should not be modified, when the callback is needed,
01106             the HAL_I2S_TxCpltCallback could be implemented in the user file
01107    */
01108 }
01109
01110 /**
01111   * @brief Rx Transfer half completed callbacks
01112   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01113   *         the configuration information for I2S module
01114   * @retval None
01115   */
01116 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01117 {
01118   /* Prevent unused argument(s) compilation warning */
01119   UNUSED(hi2s);
01120   /* NOTE : This function Should not be modified, when the callback is needed,
01121             the HAL_I2S_RxCpltCallback could be implemented in the user file
01122    */
01123 }
01124
01125 /**
01126   * @brief Rx Transfer completed callbacks
01127   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01128   *         the configuration information for I2S module
01129   * @retval None
01130   */
01131 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01132 {
01133   /* Prevent unused argument(s) compilation warning */
01134   UNUSED(hi2s);
01135   /* NOTE : This function Should not be modified, when the callback is needed,
01136             the HAL_I2S_RxCpltCallback could be implemented in the user file
01137    */
01138 }
01139
01140 /**
01141   * @brief I2S error callbacks
01142   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01143   *         the configuration information for I2S module
01144   * @retval None
01145   */
01146  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01147 {
01148   /* Prevent unused argument(s) compilation warning */
01149   UNUSED(hi2s);
01150   /* NOTE : This function Should not be modified, when the callback is needed,
01151             the HAL_I2S_ErrorCallback could be implemented in the user file
01152    */
01153 }
01154
01155 /**
01156   * @}
01157   */
01158
01159 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01160   *  @brief   Peripheral State functions
01161 @verbatim
01162  ===============================================================================
01163                       ##### Peripheral State and Errors functions #####
01164  ===============================================================================
01165     [..]
01166     This subsection permits to get in run-time the status of the peripheral
01167     and the data flow.
01168
01169 @endverbatim
01170   * @{
01171   */
01172
01173 /**
01174   * @brief  Return the I2S state
01175   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01176   *         the configuration information for I2S module
01177   * @retval HAL state
01178   */
01179 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01180 {
01181   return hi2s->State;
01182 }
01183
01184 /**
01185   * @brief  Return the I2S error code
01186   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01187   *         the configuration information for I2S module
01188   * @retval I2S Error Code
01189   */
01190 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01191 {
01192   return hi2s->ErrorCode;
01193 }
01194 /**
01195   * @}
01196   */
01197
01198 /**
01199   * @brief DMA I2S transmit process half complete callback
01200   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01201   *                the configuration information for the specified DMA module.
01202   * @retval None
01203   */
01204  void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01205 {
01206   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01207
01208   HAL_I2S_TxHalfCpltCallback(hi2s);
01209 }
01210
01211 /**
01212   * @brief DMA I2S receive process half complete callback
01213   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01214   *                the configuration information for the specified DMA module.
01215   * @retval None
01216   */
01217 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01218 {
01219   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01220
01221   HAL_I2S_RxHalfCpltCallback(hi2s);
01222 }
01223
01224 /**
01225   * @brief DMA I2S communication error callback
01226   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01227   *                the configuration information for the specified DMA module.
01228   * @retval None
01229   */
01230 void I2S_DMAError(DMA_HandleTypeDef *hdma)
01231 {
01232   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01233
01234   hi2s->TxXferCount = 0U;
01235   hi2s->RxXferCount = 0U;
01236
01237   hi2s->State= HAL_I2S_STATE_READY;
01238
01239   hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
01240   HAL_I2S_ErrorCallback(hi2s);
01241 }
01242
01243 /**
01244   * @brief Transmit an amount of data in non-blocking mode with Interrupt
01245   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01246   *         the configuration information for I2S module
01247   * @retval HAL status
01248   */
01249 HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
01250 {
01251  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
01252   {
01253     /* Process Locked */
01254     __HAL_LOCK(hi2s);
01255
01256     /* Transmit data */
01257     hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
01258
01259     hi2s->TxXferCount--;
01260
01261     if(hi2s->TxXferCount == 0U)
01262     {
01263       /* Disable TXE and ERR interrupt */
01264       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01265
01266       hi2s->State = HAL_I2S_STATE_READY;
01267
01268       /* Process Unlocked */
01269       __HAL_UNLOCK(hi2s);
01270       HAL_I2S_TxCpltCallback(hi2s);
01271     }
01272     else
01273     {
01274       /* Process Unlocked */
01275       __HAL_UNLOCK(hi2s);
01276     }
01277
01278     return HAL_OK;
01279   }
01280
01281   else
01282   {
01283     return HAL_BUSY;
01284   }
01285 }
01286
01287 /**
01288   * @brief Receive an amount of data in non-blocking mode with Interrupt
01289   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01290   *         the configuration information for I2S module
01291   * @retval HAL status
01292   */
01293 HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
01294 {
01295   if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
01296   {
01297     /* Process Locked */
01298     __HAL_LOCK(hi2s);
01299
01300     /* Receive data */
01301     (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
01302
01303     hi2s->RxXferCount--;
01304
01305     /* Check if Master Receiver mode is selected */
01306     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
01307     {
01308       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
01309       access to the SPI_SR register. */
01310       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01311     }
01312
01313     if(hi2s->RxXferCount == 0U)
01314     {
01315       /* Disable RXNE and ERR interrupt */
01316       __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
01317
01318       hi2s->State = HAL_I2S_STATE_READY;
01319
01320       /* Process Unlocked */
01321       __HAL_UNLOCK(hi2s);
01322
01323       HAL_I2S_RxCpltCallback(hi2s);
01324     }
01325     else
01326     {
01327       /* Process Unlocked */
01328       __HAL_UNLOCK(hi2s);
01329     }
01330
01331     return HAL_OK;
01332   }
01333   else
01334   {
01335     return HAL_BUSY;
01336   }
01337 }
01338
01339 /**
01340   * @brief This function handles I2S Communication Timeout.
01341   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01342   *         the configuration information for I2S module
01343   * @param Flag: Flag checked
01344   * @param Status: Value of the flag expected
01345   * @param Timeout: Duration of the timeout
01346   * @retval HAL status
01347   */
01348 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
01349 {
01350   uint32_t tickstart = 0U;
01351
01352   /* Get tick */
01353   tickstart = HAL_GetTick();
01354
01355   /* Wait until flag is set */
01356   if(Status == RESET)
01357   {
01358     while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
01359     {
01360       if(Timeout != HAL_MAX_DELAY)
01361       {
01362         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01363         {
01364           /* Set the I2S State ready */
01365           hi2s->State= HAL_I2S_STATE_READY;
01366
01367           /* Process Unlocked */
01368           __HAL_UNLOCK(hi2s);
01369
01370           return HAL_TIMEOUT;
01371         }
01372       }
01373     }
01374   }
01375   else
01376   {
01377     while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
01378     {
01379       if(Timeout != HAL_MAX_DELAY)
01380       {
01381         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01382         {
01383           /* Set the I2S State ready */
01384           hi2s->State= HAL_I2S_STATE_READY;
01385
01386           /* Process Unlocked */
01387           __HAL_UNLOCK(hi2s);
01388
01389           return HAL_TIMEOUT;
01390         }
01391       }
01392     }
01393   }
01394   return HAL_OK;
01395 }
01396
01397 /**
01398   * @}
01399   */
01400
01401 #endif /* HAL_I2S_MODULE_ENABLED */
01402 /**
01403   * @}
01404   */
01405
01406 /**
01407   * @}
01408   */
01409
01410 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s.h Source File

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stm32f4xx_hal_i2s.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of I2S HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_I2S_H
00040 #define __STM32F4xx_HAL_I2S_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2S
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2S_Exported_Types I2S Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief I2S Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Mode;         /*!< Specifies the I2S operating mode.
00068                               This parameter can be a value of @ref I2S_Mode */
00069
00070   uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
00071                               This parameter can be a value of @ref I2S_Standard */
00072
00073   uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
00074                               This parameter can be a value of @ref I2S_Data_Format */
00075
00076   uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
00077                               This parameter can be a value of @ref I2S_MCLK_Output */
00078
00079   uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
00080                               This parameter can be a value of @ref I2S_Audio_Frequency */
00081
00082   uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
00083                               This parameter can be a value of @ref I2S_Clock_Polarity */
00084
00085   uint32_t ClockSource;  /*!< Specifies the I2S Clock Source.
00086                               This parameter can be a value of @ref I2S_Clock_Source */
00087
00088   uint32_t FullDuplexMode;  /*!< Specifies the I2S FullDuplex mode.
00089                                  This parameter can be a value of @ref I2S_FullDuplex_Mode */
00090
00091 }I2S_InitTypeDef;
00092
00093 /**
00094   * @brief  HAL State structures definition
00095   */
00096 typedef enum
00097 {
00098   HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
00099   HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
00100   HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
00101   HAL_I2S_STATE_BUSY_TX    = 0x12U,  /*!< Data Transmission process is ongoing               */
00102   HAL_I2S_STATE_BUSY_RX    = 0x22U,  /*!< Data Reception process is ongoing                  */
00103   HAL_I2S_STATE_BUSY_TX_RX = 0x32U,  /*!< Data Transmission and Reception process is ongoing */
00104   HAL_I2S_STATE_TIMEOUT    = 0x03U,  /*!< I2S timeout state                                  */
00105   HAL_I2S_STATE_ERROR      = 0x04U   /*!< I2S error state                                    */
00106
00107 }HAL_I2S_StateTypeDef;
00108
00109 /**
00110   * @brief I2S handle Structure definition
00111   */
00112 typedef struct
00113 {
00114   SPI_TypeDef                *Instance;    /* I2S registers base address        */
00115
00116   I2S_InitTypeDef            Init;         /* I2S communication parameters      */
00117
00118   uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
00119
00120   __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
00121
00122   __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
00123
00124   uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
00125
00126   __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
00127
00128   __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter           */
00129
00130   DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
00131
00132   DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
00133
00134   __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
00135
00136   __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
00137
00138   __IO uint32_t              ErrorCode;    /* I2S Error code                    */
00139
00140 }I2S_HandleTypeDef;
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported constants --------------------------------------------------------*/
00146 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00147   * @{
00148   */
00149
00150 /** @defgroup I2S_Error_Code I2S Error Code
00151   * @brief    I2S Error Code
00152   * @{
00153   */
00154 #define HAL_I2S_ERROR_NONE          ((uint32_t)0x00000000U)    /*!< No error                    */
00155 #define HAL_I2S_ERROR_UDR           ((uint32_t)0x00000001U)    /*!< I2S Underrun error          */
00156 #define HAL_I2S_ERROR_OVR           ((uint32_t)0x00000002U)    /*!< I2S Overrun error           */
00157 #define HAL_I2SEX_ERROR_UDR         ((uint32_t)0x00000004U)    /*!< I2S extended Underrun error */
00158 #define HAL_I2SEX_ERROR_OVR         ((uint32_t)0x00000008U)    /*!< I2S extended Overrun error  */
00159 #define HAL_I2S_ERROR_FRE           ((uint32_t)0x00000010U)    /*!< I2S Frame format error      */
00160 #define HAL_I2S_ERROR_DMA           ((uint32_t)0x00000020U)    /*!< DMA transfer error          */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup I2S_Mode I2S Mode
00166   * @{
00167   */
00168 #define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000U)
00169 #define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100U)
00170 #define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200U)
00171 #define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300U)
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup I2S_Standard I2S Standard
00177   * @{
00178   */
00179 #define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000U)
00180 #define I2S_STANDARD_MSB                 ((uint32_t)0x00000010U)
00181 #define I2S_STANDARD_LSB                 ((uint32_t)0x00000020U)
00182 #define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030U)
00183 #define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0U)
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup I2S_Data_Format I2S Data Format
00189   * @{
00190   */
00191 #define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000U)
00192 #define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001U)
00193 #define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003U)
00194 #define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005U)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup I2S_MCLK_Output I2S Mclk Output
00200   * @{
00201   */
00202 #define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
00203 #define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000U)
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00209   * @{
00210   */
00211 #define I2S_AUDIOFREQ_192K               ((uint32_t)192000U)
00212 #define I2S_AUDIOFREQ_96K                ((uint32_t)96000U)
00213 #define I2S_AUDIOFREQ_48K                ((uint32_t)48000U)
00214 #define I2S_AUDIOFREQ_44K                ((uint32_t)44100U)
00215 #define I2S_AUDIOFREQ_32K                ((uint32_t)32000U)
00216 #define I2S_AUDIOFREQ_22K                ((uint32_t)22050U)
00217 #define I2S_AUDIOFREQ_16K                ((uint32_t)16000U)
00218 #define I2S_AUDIOFREQ_11K                ((uint32_t)11025U)
00219 #define I2S_AUDIOFREQ_8K                 ((uint32_t)8000U)
00220 #define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2U)
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
00226   * @{
00227   */
00228 #define I2S_FULLDUPLEXMODE_DISABLE                   ((uint32_t)0x00000000U)
00229 #define I2S_FULLDUPLEXMODE_ENABLE                    ((uint32_t)0x00000001U)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup I2S_Clock_Polarity  I2S Clock Polarity
00235   * @{
00236   */
00237 #define I2S_CPOL_LOW                    ((uint32_t)0x00000000U)
00238 #define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
00244   * @{
00245   */
00246 #define I2S_IT_TXE                      SPI_CR2_TXEIE
00247 #define I2S_IT_RXNE                     SPI_CR2_RXNEIE
00248 #define I2S_IT_ERR                      SPI_CR2_ERRIE
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup I2S_Flags_Definition I2S Flags Definition
00254   * @{
00255   */
00256 #define I2S_FLAG_TXE                    SPI_SR_TXE
00257 #define I2S_FLAG_RXNE                   SPI_SR_RXNE
00258
00259 #define I2S_FLAG_UDR                    SPI_SR_UDR
00260 #define I2S_FLAG_OVR                    SPI_SR_OVR
00261 #define I2S_FLAG_FRE                    SPI_SR_FRE
00262
00263 #define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
00264 #define I2S_FLAG_BSY                    SPI_SR_BSY
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /* Exported macro ------------------------------------------------------------*/
00274 /** @defgroup I2S_Exported_Macros I2S Exported Macros
00275   * @{
00276   */
00277
00278 /** @brief Reset I2S handle state
00279   * @param  __HANDLE__: specifies the I2S Handle.
00280   * @retval None
00281   */
00282 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00283
00284 /** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
00285   * @param  __HANDLE__: specifies the I2S Handle.
00286   * @retval None
00287   */
00288 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
00289 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
00290
00291 /** @brief  Enable or disable the specified I2S interrupts.
00292   * @param  __HANDLE__: specifies the I2S Handle.
00293   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00294   *         This parameter can be one of the following values:
00295   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00296   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00297   *            @arg I2S_IT_ERR: Error interrupt enable
00298   * @retval None
00299   */
00300 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00301 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
00302
00303 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
00304   * @param  __HANDLE__: specifies the I2S Handle.
00305   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00306   * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
00307   *          This parameter can be one of the following values:
00308   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00309   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00310   *            @arg I2S_IT_ERR: Error interrupt enable
00311   * @retval The new state of __IT__ (TRUE or FALSE).
00312   */
00313 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00314
00315 /** @brief  Checks whether the specified I2S flag is set or not.
00316   * @param  __HANDLE__: specifies the I2S Handle.
00317   * @param  __FLAG__: specifies the flag to check.
00318   *         This parameter can be one of the following values:
00319   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00320   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00321   *            @arg I2S_FLAG_UDR: Underrun flag
00322   *            @arg I2S_FLAG_OVR: Overrun flag
00323   *            @arg I2S_FLAG_FRE: Frame error flag
00324   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00325   *            @arg I2S_FLAG_BSY: Busy flag
00326   * @retval The new state of __FLAG__ (TRUE or FALSE).
00327   */
00328 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00329
00330 /** @brief Clears the I2S OVR pending flag.
00331   * @param  __HANDLE__: specifies the I2S Handle.
00332   * @retval None
00333   */
00334 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
00335   do{                                           \
00336     __IO uint32_t tmpreg = 0x00U;               \
00337     tmpreg = (__HANDLE__)->Instance->DR;        \
00338     tmpreg = (__HANDLE__)->Instance->SR;        \
00339     UNUSED(tmpreg);                             \
00340   } while(0)
00341
00342 /** @brief Clears the I2S UDR pending flag.
00343   * @param  __HANDLE__: specifies the I2S Handle.
00344   * @retval None
00345   */
00346 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
00347   do{                                           \
00348   __IO uint32_t tmpreg = 0x00U;                 \
00349   tmpreg = (__HANDLE__)->Instance->SR;          \
00350   UNUSED(tmpreg);                               \
00351   } while(0)
00352 /**
00353   * @}
00354   */
00355
00356 /* Include I2S Extension module */
00357 #include "stm32f4xx_hal_i2s_ex.h"
00358
00359 /* Exported functions --------------------------------------------------------*/
00360 /** @addtogroup I2S_Exported_Functions
00361   * @{
00362   */
00363
00364 /** @addtogroup I2S_Exported_Functions_Group1
00365   * @{
00366   */
00367 /* Initialization/de-initialization functions  **********************************/
00368 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00369 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
00370 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00371 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00372 /**
00373   * @}
00374   */
00375
00376 /** @addtogroup I2S_Exported_Functions_Group2
00377   * @{
00378   */
00379 /* I/O operation functions  *****************************************************/
00380 /* Blocking mode: Polling */
00381 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00382 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00383
00384  /* Non-Blocking mode: Interrupt */
00385 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00386 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00387 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00388
00389 /* Non-Blocking mode: DMA */
00390 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00391 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00392
00393 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00394 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00395 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00396
00397 /* Peripheral Control and State functions  **************************************/
00398 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00399 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00400
00401 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00402 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00403 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00404 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00405 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00406 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00407 /**
00408   * @}
00409   */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /* Private types -------------------------------------------------------------*/
00416 /* Private variables ---------------------------------------------------------*/
00417 /* Private constants ---------------------------------------------------------*/
00418 /** @defgroup I2S_Private_Constants I2S Private Constants
00419   * @{
00420   */
00421
00422 /**
00423   * @}
00424   */
00425
00426 /* Private macros ------------------------------------------------------------*/
00427 /** @defgroup I2S_Private_Macros I2S Private Macros
00428   * @{
00429   */
00430 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
00431                            ((MODE) == I2S_MODE_SLAVE_RX)  || \
00432                            ((MODE) == I2S_MODE_MASTER_TX) || \
00433                            ((MODE) == I2S_MODE_MASTER_RX))
00434
00435 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
00436                                    ((STANDARD) == I2S_STANDARD_MSB)       || \
00437                                    ((STANDARD) == I2S_STANDARD_LSB)       || \
00438                                    ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
00439                                    ((STANDARD) == I2S_STANDARD_PCM_LONG))
00440
00441 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
00442                                     ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
00443                                     ((FORMAT) == I2S_DATAFORMAT_24B)          || \
00444                                     ((FORMAT) == I2S_DATAFORMAT_32B))
00445
00446 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
00447                                     ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
00448
00449 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
00450                                   ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
00451                                   ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
00452
00453 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
00454                                       ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
00455
00456 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
00457                            ((CPOL) == I2S_CPOL_HIGH))
00458
00459 /**
00460   * @}
00461   */
00462
00463 /* Private functions ---------------------------------------------------------*/
00464 /** @defgroup I2S_Private_Functions I2S Private Functions
00465   * @{
00466   */
00467 void              I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00468 void              I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00469 void              I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00470 void              I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00471 void              I2S_DMAError(DMA_HandleTypeDef *hdma);
00472 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
00473 HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
00474 HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @}
00485   */
00486
00487 #ifdef __cplusplus
00488 }
00489 #endif
00490
00491
00492 #endif /* __STM32F4xx_HAL_I2S_H */
00493
00494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s_ex.c Source File

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stm32f4xx_hal_i2s_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2s_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   I2S HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of I2S extension peripheral:
00010   *           + Extension features Functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                     ##### I2S Extension features #####
00015   ==============================================================================
00016   [..]
00017      (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
00018          data simultaneously using two data lines. Each SPI peripheral has an extended block
00019          called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
00020      (#) The extension block is not a full SPI IP, it is used only as I2S slave to
00021          implement full duplex mode. The extension block uses the same clock sources
00022          as its master.
00023
00024      (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
00025
00026      [..]
00027        (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
00028          I2Sx can be I2S2 or I2S3.
00029
00030                   ##### How to use this driver #####
00031  ===============================================================================
00032  [..]
00033    Three operation modes are available within this driver :
00034
00035    *** Polling mode IO operation ***
00036    =================================
00037    [..]
00038      (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
00039
00040    *** Interrupt mode IO operation ***
00041    ===================================
00042    [..]
00043      (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
00044      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00045          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00046      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00047          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00048      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00049          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00050      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00051          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00052      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00053          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00054
00055    *** DMA mode IO operation ***
00056    ==============================
00057    [..]
00058      (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
00059      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00060          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00061      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00062          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00063      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00064          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00065      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00066          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00067      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00068          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00069      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00070      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00071      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00072
00073   @endverbatim
00074   ******************************************************************************
00075   * @attention
00076   *
00077   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00078   *
00079   * Redistribution and use in source and binary forms, with or without modification,
00080   * are permitted provided that the following conditions are met:
00081   *   1. Redistributions of source code must retain the above copyright notice,
00082   *      this list of conditions and the following disclaimer.
00083   *   2. Redistributions in binary form must reproduce the above copyright notice,
00084   *      this list of conditions and the following disclaimer in the documentation
00085   *      and/or other materials provided with the distribution.
00086   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00087   *      may be used to endorse or promote products derived from this software
00088   *      without specific prior written permission.
00089   *
00090   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00091   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00092   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00093   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00094   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00095   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00096   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00097   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00098   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00099   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00100   *
00101   ******************************************************************************
00102   */
00103
00104 /* Includes ------------------------------------------------------------------*/
00105 #include "stm32f4xx_hal.h"
00106
00107 /** @addtogroup STM32F4xx_HAL_Driver
00108   * @{
00109   */
00110
00111 /** @defgroup I2SEx I2SEx
00112   * @brief I2S HAL module driver
00113   * @{
00114   */
00115
00116 #ifdef HAL_I2S_MODULE_ENABLED
00117 /* Private typedef -----------------------------------------------------------*/
00118 /* Private define ------------------------------------------------------------*/
00119 /* Private macro -------------------------------------------------------------*/
00120 /* Private variables ---------------------------------------------------------*/
00121 /* Private function prototypes -----------------------------------------------*/
00122 /* Private functions ---------------------------------------------------------*/
00123 /** @addtogroup I2SEx_Private_Functions
00124   * @{
00125   */
00126 /**
00127   * @}
00128   */
00129
00130 /* Exported functions --------------------------------------------------------*/
00131 /** @defgroup I2SEx_Exported_Functions I2S Exported Functions
00132   * @{
00133   */
00134
00135 /** @defgroup I2SEx_Group1 Extension features functions
00136   *  @brief   Extension features functions
00137   *
00138 @verbatim
00139  ===============================================================================
00140                        ##### Extension features Functions #####
00141  ===============================================================================
00142     [..]
00143     This subsection provides a set of functions allowing to manage the I2S data
00144     transfers.
00145
00146     (#) There are two modes of transfer:
00147        (++) Blocking mode : The communication is performed in the polling mode.
00148             The status of all data processing is returned by the same function
00149             after finishing transfer.
00150        (++) No-Blocking mode : The communication is performed using Interrupts
00151             or DMA. These functions return the status of the transfer startup.
00152             The end of the data processing will be indicated through the
00153             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00154             using DMA mode.
00155
00156     (#) Blocking mode functions are :
00157         (++) HAL_I2S_TransmitReceive()
00158
00159     (#) No-Blocking mode functions with Interrupt are :
00160         (++) HAL_I2S_TransmitReceive_IT()
00161
00162     (#) No-Blocking mode functions with DMA are :
00163         (++) HAL_I2S_TransmitReceive_DMA()
00164
00165     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00166         (++) HAL_I2S_TxCpltCallback()
00167         (++) HAL_I2S_RxCpltCallback()
00168         (++) HAL_I2S_ErrorCallback()
00169
00170 @endverbatim
00171   * @{
00172   */
00173 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00174     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00175     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
00176     defined(STM32F479xx)
00177 /**
00178   * @brief Initializes the I2S according to the specified parameters
00179   *         in the I2S_InitTypeDef and create the associated handle.
00180   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00181   *         the configuration information for I2S module
00182   * @retval HAL status
00183   */
00184 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00185 {
00186   uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
00187   uint32_t tmp = 0U, i2sclk = 0U;
00188
00189   /* Check the I2S handle allocation */
00190   if(hi2s == NULL)
00191   {
00192     return HAL_ERROR;
00193   }
00194
00195   /* Check the I2S parameters */
00196   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00197   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00198   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00199   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00200   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00201   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00202   assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
00203
00204   if(hi2s->State == HAL_I2S_STATE_RESET)
00205   {
00206     /* Allocate lock resource and initialize it */
00207     hi2s->Lock = HAL_UNLOCKED;
00208     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00209     HAL_I2S_MspInit(hi2s);
00210   }
00211
00212   hi2s->State = HAL_I2S_STATE_BUSY;
00213
00214   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
00215   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00216   hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00217                                SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00218                                SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
00219   hi2s->Instance->I2SPR = 0x0002U;
00220
00221   /* Get the I2SCFGR register value */
00222   tmpreg = hi2s->Instance->I2SCFGR;
00223
00224   /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
00225   /* If the requested audio frequency is not the default, compute the prescaler */
00226   if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
00227   {
00228     /* Check the frame length (For the Prescaler computing) *******************/
00229     if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00230     {
00231       /* Packet length is 32 bits */
00232       packetlength = 2U;
00233     }
00234
00235     /* Get I2S source Clock frequency  ****************************************/
00236     i2sclk = I2S_GetInputClock(hi2s);
00237
00238     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00239     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00240     {
00241       /* MCLK output is enabled */
00242       tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00243     }
00244     else
00245     {
00246       /* MCLK output is disabled */
00247       tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
00248     }
00249
00250     /* Remove the flatting point */
00251     tmp = tmp / 10U;
00252
00253     /* Check the parity of the divider */
00254     i2sodd = (uint32_t)(tmp & (uint32_t)1U);
00255
00256     /* Compute the i2sdiv prescaler */
00257     i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
00258
00259     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00260     i2sodd = (uint32_t) (i2sodd << 8U);
00261   }
00262
00263   /* Test if the divider is 1 or 0 or greater than 0xFF */
00264   if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00265   {
00266     /* Set the default values */
00267     i2sdiv = 2U;
00268     i2sodd = 0U;
00269   }
00270
00271   /* Write to SPIx I2SPR register the computed value */
00272   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
00273
00274   /* Configure the I2S with the I2S_InitStruct values */
00275   tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
00276
00277 #if defined(SPI_I2SCFGR_ASTRTEN)
00278   if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
00279   {
00280   /* Write to SPIx I2SCFGR */
00281   hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
00282   }
00283   else
00284   {
00285   /* Write to SPIx I2SCFGR */
00286   hi2s->Instance->I2SCFGR = tmpreg;
00287   }
00288 #else
00289   /* Write to SPIx I2SCFGR */
00290   hi2s->Instance->I2SCFGR = tmpreg;
00291 #endif
00292
00293   /* Configure the I2S extended if the full duplex mode is enabled */
00294   assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
00295   if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
00296   {
00297     /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00298     I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00299                                           SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00300                                           SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
00301     I2SxEXT(hi2s->Instance)->I2SPR = 2U;
00302
00303     /* Get the I2SCFGR register value */
00304     tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
00305
00306     /* Get the mode to be configured for the extended I2S */
00307     if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
00308     {
00309       tmp = I2S_MODE_SLAVE_RX;
00310     }
00311     else
00312     {
00313       if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
00314       {
00315         tmp = I2S_MODE_SLAVE_TX;
00316       }
00317     }
00318
00319     /* Configure the I2S Slave with the I2S Master parameter values */
00320     tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
00321
00322     /* Write to SPIx I2SCFGR */
00323     I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
00324   }
00325
00326   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00327   hi2s->State= HAL_I2S_STATE_READY;
00328
00329   return HAL_OK;
00330 }
00331
00332 /**
00333   * @brief Full-Duplex Transmit/Receive data in blocking mode.
00334   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00335   *         the configuration information for I2S module
00336   * @param pTxData: a 16-bit pointer to the Transmit data buffer.
00337   * @param pRxData: a 16-bit pointer to the Receive data buffer.
00338   * @param Size: number of data sample to be sent:
00339   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00340   *       configuration phase, the Size parameter means the number of 16-bit data length
00341   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00342   *       the Size parameter means the number of 16-bit data length.
00343   * @param Timeout: Timeout duration
00344   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00345   *       between Master and Slave(example: audio streaming).
00346   * @retval HAL status
00347   */
00348 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
00349 {
00350   uint32_t tickstart = 0U;
00351   uint32_t tmp1 = 0U;
00352
00353   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
00354   {
00355     return  HAL_ERROR;
00356   }
00357
00358   /* Check the I2S State */
00359   if(hi2s->State == HAL_I2S_STATE_READY)
00360   {
00361     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00362     /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
00363        is selected during the I2S configuration phase, the Size parameter means the number
00364        of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
00365        frame is selected the Size parameter means the number of 16-bit data length. */
00366     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00367     {
00368       hi2s->TxXferSize = Size*2U;
00369       hi2s->TxXferCount = Size*2U;
00370       hi2s->RxXferSize = Size*2U;
00371       hi2s->RxXferCount = Size*2U;
00372     }
00373     else
00374     {
00375       hi2s->TxXferSize = Size;
00376       hi2s->TxXferCount = Size;
00377       hi2s->RxXferSize = Size;
00378       hi2s->RxXferCount = Size;
00379     }
00380
00381     /* Process Locked */
00382     __HAL_LOCK(hi2s);
00383
00384     /* Set the I2S State busy TX/RX */
00385     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
00386
00387     tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
00388     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00389     if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
00390     {
00391       /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
00392       to avoid the clock de-synchronization between Master and Slave. */
00393       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00394       {
00395         /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
00396         I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
00397
00398         /* Enable I2Sx peripheral */
00399         __HAL_I2S_ENABLE(hi2s);
00400       }
00401
00402       while(hi2s->TxXferCount > 0U)
00403       {
00404         /* Wait until TXE flag is set */
00405         if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
00406         {
00407           return HAL_TIMEOUT;
00408         }
00409         hi2s->Instance->DR = (*pTxData++);
00410
00411         /* Get tick */
00412         tickstart = HAL_GetTick();
00413
00414         /* Wait until RXNE flag is set */
00415         while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
00416         {
00417           if(Timeout != HAL_MAX_DELAY)
00418           {
00419             if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00420             {
00421               /* Process Unlocked */
00422               __HAL_UNLOCK(hi2s);
00423
00424               return HAL_TIMEOUT;
00425             }
00426           }
00427         }
00428         (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
00429
00430         hi2s->TxXferCount--;
00431         hi2s->RxXferCount--;
00432       }
00433     }
00434     /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
00435     else
00436     {
00437       /* Check if the I2S is already enabled */
00438       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00439       {
00440         /* Enable I2S peripheral before the I2Sext*/
00441         __HAL_I2S_ENABLE(hi2s);
00442
00443         /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
00444         I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
00445       }
00446       else
00447       {
00448         /* Check if Master Receiver mode is selected */
00449         if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00450         {
00451           /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00452           access to the SPI_SR register. */
00453           __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00454         }
00455       }
00456       while(hi2s->TxXferCount > 0U)
00457       {
00458         /* Get tick */
00459         tickstart = HAL_GetTick();
00460
00461         /* Wait until TXE flag is set */
00462         while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
00463         {
00464           if(Timeout != HAL_MAX_DELAY)
00465           {
00466             if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00467             {
00468               /* Process Unlocked */
00469               __HAL_UNLOCK(hi2s);
00470
00471               return HAL_TIMEOUT;
00472             }
00473           }
00474         }
00475         I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
00476
00477         /* Wait until RXNE flag is set */
00478         if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00479         {
00480           return HAL_TIMEOUT;
00481         }
00482         (*pRxData++) = hi2s->Instance->DR;
00483
00484         hi2s->TxXferCount--;
00485         hi2s->RxXferCount--;
00486       }
00487     }
00488
00489     /* Set the I2S State ready */
00490     hi2s->State = HAL_I2S_STATE_READY;
00491
00492     /* Process Unlocked */
00493     __HAL_UNLOCK(hi2s);
00494
00495     return HAL_OK;
00496   }
00497   else
00498   {
00499     return HAL_BUSY;
00500   }
00501 }
00502
00503 /**
00504   * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
00505   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00506   *         the configuration information for I2S module
00507   * @param pTxData: a 16-bit pointer to the Transmit data buffer.
00508   * @param pRxData: a 16-bit pointer to the Receive data buffer.
00509   * @param Size: number of data sample to be sent:
00510   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00511   *       configuration phase, the Size parameter means the number of 16-bit data length
00512   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00513   *       the Size parameter means the number of 16-bit data length.
00514   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00515   *       between Master and Slave(example: audio streaming).
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
00519 {
00520   uint32_t tmp1 = 0U;
00521
00522   if(hi2s->State == HAL_I2S_STATE_READY)
00523   {
00524     if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
00525     {
00526       return  HAL_ERROR;
00527     }
00528
00529     hi2s->pTxBuffPtr = pTxData;
00530     hi2s->pRxBuffPtr = pRxData;
00531
00532     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00533     /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
00534        is selected during the I2S configuration phase, the Size parameter means the number
00535        of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
00536        frame is selected the Size parameter means the number of 16-bit data length. */
00537     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00538     {
00539       hi2s->TxXferSize = Size*2U;
00540       hi2s->TxXferCount = Size*2U;
00541       hi2s->RxXferSize = Size*2U;
00542       hi2s->RxXferCount = Size*2U;
00543     }
00544     else
00545     {
00546       hi2s->TxXferSize = Size;
00547       hi2s->TxXferCount = Size;
00548       hi2s->RxXferSize = Size;
00549       hi2s->RxXferCount = Size;
00550     }
00551
00552     /* Process Locked */
00553     __HAL_LOCK(hi2s);
00554
00555     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
00556     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00557
00558     tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
00559     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00560     if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
00561     {
00562       /* Enable I2Sext RXNE and ERR interrupts */
00563       I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
00564
00565       /* Enable I2Sx TXE and ERR interrupts */
00566       __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00567
00568       /* Check if the I2S is already enabled */
00569       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00570       {
00571         /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
00572         I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
00573
00574         /* Enable I2Sx peripheral */
00575         __HAL_I2S_ENABLE(hi2s);
00576       }
00577     }
00578     /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
00579     else
00580     {
00581       /* Enable I2Sext TXE and ERR interrupts */
00582       I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
00583
00584       /* Enable I2Sext RXNE and ERR interrupts */
00585       __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00586
00587       /* Check if the I2S is already enabled */
00588       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00589       {
00590         /* Check if the I2S_MODE_MASTER_RX is selected */
00591         if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00592         {
00593           /* Prepare the First Data before enabling the I2S */
00594           if(hi2s->TxXferCount != 0U)
00595           {
00596             /* Transmit First data */
00597             I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
00598             hi2s->TxXferCount--;
00599
00600             if(hi2s->TxXferCount == 0U)
00601             {
00602               /* Disable I2Sext TXE interrupt */
00603               I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
00604             }
00605           }
00606         }
00607         /* Enable I2S peripheral */
00608         __HAL_I2S_ENABLE(hi2s);
00609
00610         /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
00611         I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
00612       }
00613     }
00614     /* Process Unlocked */
00615     __HAL_UNLOCK(hi2s);
00616
00617     return HAL_OK;
00618   }
00619   else
00620   {
00621     return HAL_BUSY;
00622   }
00623 }
00624
00625 /**
00626   * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
00627   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00628   *         the configuration information for I2S module
00629   * @param pTxData: a 16-bit pointer to the Transmit data buffer.
00630   * @param pRxData: a 16-bit pointer to the Receive data buffer.
00631   * @param Size: number of data sample to be sent:
00632   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00633   *       configuration phase, the Size parameter means the number of 16-bit data length
00634   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00635   *       the Size parameter means the number of 16-bit data length.
00636   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00637   *       between Master and Slave(example: audio streaming).
00638   * @retval HAL status
00639   */
00640 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
00641 {
00642   uint32_t *tmp;
00643   uint32_t tmp1 = 0U;
00644
00645   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
00646   {
00647     return  HAL_ERROR;
00648   }
00649
00650   if(hi2s->State == HAL_I2S_STATE_READY)
00651   {
00652     hi2s->pTxBuffPtr = pTxData;
00653     hi2s->pRxBuffPtr = pRxData;
00654
00655     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00656     /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
00657        is selected during the I2S configuration phase, the Size parameter means the number
00658        of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
00659        frame is selected the Size parameter means the number of 16-bit data length. */
00660     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00661     {
00662       hi2s->TxXferSize = Size*2U;
00663       hi2s->TxXferCount = Size*2U;
00664       hi2s->RxXferSize = Size*2U;
00665       hi2s->RxXferCount = Size*2U;
00666     }
00667     else
00668     {
00669       hi2s->TxXferSize = Size;
00670       hi2s->TxXferCount = Size;
00671       hi2s->RxXferSize = Size;
00672       hi2s->RxXferCount = Size;
00673     }
00674
00675     /* Process Locked */
00676     __HAL_LOCK(hi2s);
00677
00678     hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
00679     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00680
00681     /* Set the I2S Rx DMA Half transfer complete callback */
00682     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
00683
00684     /* Set the I2S Rx DMA transfer complete callback */
00685     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
00686
00687     /* Set the I2S Rx DMA error callback */
00688     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
00689
00690     /* Set the I2S Tx DMA Half transfer complete callback */
00691     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
00692
00693     /* Set the I2S Tx DMA transfer complete callback */
00694     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
00695
00696     /* Set the I2S Tx DMA error callback */
00697     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
00698
00699     tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
00700     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00701     if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
00702     {
00703       /* Enable the Rx DMA Stream */
00704       tmp = (uint32_t*)&pRxData;
00705       HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
00706
00707       /* Enable Rx DMA Request */
00708       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
00709
00710       /* Enable the Tx DMA Stream */
00711       tmp = (uint32_t*)&pTxData;
00712       HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
00713
00714       /* Enable Tx DMA Request */
00715       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00716
00717       /* Check if the I2S is already enabled */
00718       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00719       {
00720         /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
00721         I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
00722
00723         /* Enable I2S peripheral after the I2Sext */
00724         __HAL_I2S_ENABLE(hi2s);
00725       }
00726     }
00727     else
00728     {
00729       /* Enable the Tx DMA Stream */
00730       tmp = (uint32_t*)&pTxData;
00731       HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
00732
00733       /* Enable Tx DMA Request */
00734       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
00735
00736       /* Enable the Rx DMA Stream */
00737       tmp = (uint32_t*)&pRxData;
00738       HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
00739
00740       /* Enable Rx DMA Request */
00741       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00742
00743       /* Check if the I2S is already enabled */
00744       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00745       {
00746         /* Enable I2S peripheral before the I2Sext */
00747         __HAL_I2S_ENABLE(hi2s);
00748
00749         /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
00750         I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
00751       }
00752       else
00753       {
00754         /* Check if Master Receiver mode is selected */
00755         if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00756         {
00757           /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00758           access to the SPI_SR register. */
00759           __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00760         }
00761       }
00762     }
00763
00764     /* Process Unlocked */
00765     __HAL_UNLOCK(hi2s);
00766
00767     return HAL_OK;
00768   }
00769   else
00770   {
00771     return HAL_BUSY;
00772   }
00773 }
00774
00775 /**
00776   * @brief Pauses the audio stream playing from the Media.
00777   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00778   *         the configuration information for I2S module
00779   * @retval HAL status
00780   */
00781 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
00782 {
00783   /* Process Locked */
00784   __HAL_LOCK(hi2s);
00785
00786   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00787   {
00788     /* Disable the I2S DMA Tx request */
00789     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00790   }
00791   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00792   {
00793     /* Disable the I2S DMA Rx request */
00794     hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00795   }
00796   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00797   {
00798     if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
00799     {
00800       /* Disable the I2S DMA Tx request */
00801       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00802       /* Disable the I2SEx Rx DMA Request */
00803       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00804     }
00805     else
00806     {
00807       /* Disable the I2S DMA Rx request */
00808       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00809       /* Disable the I2SEx Tx DMA Request */
00810       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00811     }
00812   }
00813
00814   /* Process Unlocked */
00815   __HAL_UNLOCK(hi2s);
00816
00817   return HAL_OK;
00818 }
00819
00820 /**
00821   * @brief Resumes the audio stream playing from the Media.
00822   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00823   *         the configuration information for I2S module
00824   * @retval HAL status
00825   */
00826 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
00827 {
00828   /* Process Locked */
00829   __HAL_LOCK(hi2s);
00830
00831   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00832   {
00833     /* Enable the I2S DMA Tx request */
00834     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00835   }
00836   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00837   {
00838     /* Enable the I2S DMA Rx request */
00839     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00840   }
00841   else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
00842   {
00843     if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
00844     {
00845       /* Enable the I2S DMA Tx request */
00846       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
00847       /* Disable the I2SEx Rx DMA Request */
00848       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
00849     }
00850     else
00851     {
00852       /* Enable the I2S DMA Rx request */
00853       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
00854       /* Enable the I2SEx Tx DMA Request */
00855       I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
00856     }
00857   }
00858
00859   /* If the I2S peripheral is still not enabled, enable it */
00860   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
00861   {
00862     /* Enable I2S peripheral */
00863     __HAL_I2S_ENABLE(hi2s);
00864   }
00865
00866   /* Process Unlocked */
00867   __HAL_UNLOCK(hi2s);
00868
00869   return HAL_OK;
00870 }
00871
00872 /**
00873   * @brief Resumes the audio stream playing from the Media.
00874   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00875   *         the configuration information for I2S module
00876   * @retval HAL status
00877   */
00878 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
00879 {
00880   /* Process Locked */
00881   __HAL_LOCK(hi2s);
00882
00883   /* Disable the I2S Tx/Rx DMA requests */
00884   hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
00885   hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
00886
00887   if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
00888   {
00889     /* Disable the I2S extended Tx/Rx DMA requests */
00890     I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
00891     I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
00892   }
00893
00894   /* Abort the I2S DMA Stream tx */
00895   if(hi2s->hdmatx != NULL)
00896   {
00897     HAL_DMA_Abort(hi2s->hdmatx);
00898   }
00899   /* Abort the I2S DMA Stream rx */
00900   if(hi2s->hdmarx != NULL)
00901   {
00902     HAL_DMA_Abort(hi2s->hdmarx);
00903   }
00904
00905   /* Disable I2S peripheral */
00906   __HAL_I2S_DISABLE(hi2s);
00907
00908   if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
00909   {
00910     /* Disable the I2Sext peripheral */
00911     I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
00912   }
00913   hi2s->State = HAL_I2S_STATE_READY;
00914
00915   /* Process Unlocked */
00916   __HAL_UNLOCK(hi2s);
00917
00918   return HAL_OK;
00919 }
00920
00921 /**
00922   * @brief  This function handles I2S interrupt request.
00923   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00924   *         the configuration information for I2S module
00925   * @retval None
00926   */
00927 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
00928 {
00929   uint32_t tmp1 = 0U, tmp2 = 0U;
00930   __IO uint32_t tmpreg1 = 0U;
00931   if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
00932   {
00933     if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00934     {
00935       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
00936       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
00937       /* I2S in mode Receiver ------------------------------------------------*/
00938       if((tmp1 != RESET) && (tmp2 != RESET))
00939       {
00940         I2S_Receive_IT(hi2s);
00941       }
00942
00943       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
00944       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
00945       /* I2S Overrun error interrupt occurred ---------------------------------*/
00946       if((tmp1 != RESET) && (tmp2 != RESET))
00947       {
00948         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00949         hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
00950       }
00951     }
00952
00953     if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00954     {
00955       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
00956       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
00957       /* I2S in mode Tramitter -----------------------------------------------*/
00958       if((tmp1 != RESET) && (tmp2 != RESET))
00959       {
00960         I2S_Transmit_IT(hi2s);
00961       }
00962
00963       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
00964       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
00965       /* I2S Underrun error interrupt occurred --------------------------------*/
00966       if((tmp1 != RESET) && (tmp2 != RESET))
00967       {
00968         __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00969         hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
00970       }
00971     }
00972   }
00973   else
00974   {
00975     tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
00976     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
00977     if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
00978     {
00979       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
00980       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
00981       /* I2Sext in mode Receiver ---------------------------------------------*/
00982       if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
00983       {
00984         /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
00985         the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
00986         I2SEx_TransmitReceive_IT(hi2s);
00987       }
00988
00989       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
00990       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
00991       /* I2Sext Overrun error interrupt occurred -----------------------------*/
00992       if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
00993       {
00994         /* Clear I2Sext OVR Flag */
00995         tmpreg1 = I2SxEXT(hi2s->Instance)->DR;
00996         tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
00997         hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
00998         UNUSED(tmpreg1);
00999       }
01000
01001       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
01002       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
01003       /* I2S in mode Tramitter -----------------------------------------------*/
01004       if((tmp1 != RESET) && (tmp2 != RESET))
01005       {
01006         /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
01007         the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
01008         I2SEx_TransmitReceive_IT(hi2s);
01009       }
01010
01011       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
01012       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
01013       /* I2S Underrun error interrupt occurred -------------------------------*/
01014       if((tmp1 != RESET) && (tmp2 != RESET))
01015       {
01016         __HAL_I2S_CLEAR_UDRFLAG(hi2s);
01017         hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
01018       }
01019     }
01020     /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
01021     else
01022     {
01023       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
01024       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
01025       /* I2S in mode Receiver ------------------------------------------------*/
01026       if((tmp1 != RESET) && (tmp2 != RESET))
01027       {
01028         /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
01029         the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
01030         I2SEx_TransmitReceive_IT(hi2s);
01031       }
01032
01033       tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
01034       tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
01035       /* I2S Overrun error interrupt occurred --------------------------------*/
01036       if((tmp1 != RESET) && (tmp2 != RESET))
01037       {
01038         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01039         hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
01040       }
01041
01042       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
01043       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
01044       /* I2Sext in mode Tramitter --------------------------------------------*/
01045       if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
01046       {
01047         /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
01048         the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
01049         I2SEx_TransmitReceive_IT(hi2s);
01050       }
01051
01052       tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
01053       tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
01054       /* I2Sext Underrun error interrupt occurred ----------------------------*/
01055       if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
01056       {
01057         /* Clear I2Sext UDR Flag */
01058         tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
01059         hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
01060         UNUSED(tmpreg1);
01061       }
01062     }
01063   }
01064
01065   /* Call the Error call Back in case of Errors */
01066   if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
01067   {
01068     /* Set the I2S state ready to be able to start again the process */
01069     hi2s->State= HAL_I2S_STATE_READY;
01070     HAL_I2S_ErrorCallback(hi2s);
01071   }
01072 }
01073
01074 /**
01075   * @}
01076   */
01077
01078 /**
01079   * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
01080   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01081   *         the configuration information for I2S module
01082   * @retval HAL status
01083   */
01084 HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
01085 {
01086   uint32_t tmp1 = 0U, tmp2 = 0U;
01087
01088   if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
01089   {
01090     /* Process Locked */
01091     __HAL_LOCK(hi2s);
01092
01093     tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
01094     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
01095     if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
01096     {
01097       if(hi2s->TxXferCount != 0U)
01098       {
01099         if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
01100         {
01101           /* Transmit data */
01102           hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
01103           hi2s->TxXferCount--;
01104
01105           if(hi2s->TxXferCount == 0U)
01106           {
01107             /* Disable TXE interrupt */
01108             __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
01109           }
01110         }
01111       }
01112
01113       if(hi2s->RxXferCount != 0U)
01114       {
01115         if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
01116         {
01117           /* Receive data */
01118           (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
01119           hi2s->RxXferCount--;
01120
01121           if(hi2s->RxXferCount == 0U)
01122           {
01123             /* Disable I2Sext RXNE interrupt */
01124             I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
01125           }
01126         }
01127       }
01128     }
01129     /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
01130     else
01131     {
01132       if(hi2s->TxXferCount != 0U)
01133       {
01134         if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
01135         {
01136           /* Transmit data */
01137           I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
01138           hi2s->TxXferCount--;
01139
01140           if(hi2s->TxXferCount == 0U)
01141           {
01142             /* Disable I2Sext TXE interrupt */
01143             I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
01144
01145             HAL_I2S_TxCpltCallback(hi2s);
01146           }
01147         }
01148       }
01149       if(hi2s->RxXferCount != 0U)
01150       {
01151         if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
01152         {
01153           /* Receive data */
01154           (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
01155           hi2s->RxXferCount--;
01156
01157           if(hi2s->RxXferCount == 0U)
01158           {
01159             /* Disable RXNE interrupt */
01160             __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
01161
01162             HAL_I2S_RxCpltCallback(hi2s);
01163           }
01164         }
01165       }
01166     }
01167
01168     tmp1 = hi2s->RxXferCount;
01169     tmp2 = hi2s->TxXferCount;
01170     if((tmp1 == 0U) && (tmp2 == 0U))
01171     {
01172       /* Disable I2Sx ERR interrupt */
01173       __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
01174       /* Disable I2Sext ERR interrupt */
01175       I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
01176
01177       hi2s->State = HAL_I2S_STATE_READY;
01178     }
01179
01180     /* Process Unlocked */
01181     __HAL_UNLOCK(hi2s);
01182
01183     return HAL_OK;
01184   }
01185   else
01186   {
01187     return HAL_BUSY;
01188   }
01189 }
01190 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx ||\
01191           STM32F411xx || STM32F469xx || STM32F479xx */
01192 /**
01193   * @brief DMA I2S transmit process complete callback
01194   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01195   *                the configuration information for the specified DMA module.
01196   * @retval None
01197   */
01198 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01199 {
01200   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01201
01202   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01203   {
01204     if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
01205     {
01206        hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01207     }
01208 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
01209     defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
01210     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
01211     defined(STM32F479xx)
01212    /* FullDuplexMode feature enabled */
01213     else
01214     {
01215       if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
01216       {
01217         /* Disable Tx DMA Request for the I2S Master*/
01218         hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01219       }
01220       else
01221       {
01222         /* Disable Tx DMA Request for the I2SEx Slave */
01223         I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
01224       }
01225     }
01226 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
01227           STM32F469xx || STM32F479xx */
01228
01229     hi2s->TxXferCount = 0U;
01230     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
01231     {
01232       if(hi2s->RxXferCount == 0U)
01233       {
01234         hi2s->State = HAL_I2S_STATE_READY;
01235       }
01236     }
01237     else
01238     {
01239       hi2s->State = HAL_I2S_STATE_READY;
01240     }
01241   }
01242   HAL_I2S_TxCpltCallback(hi2s);
01243 }
01244
01245 /**
01246   * @brief DMA I2S receive process complete callback
01247   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01248   *                the configuration information for the specified DMA module.
01249   * @retval None
01250   */
01251 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01252 {
01253   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01254
01255   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01256   {
01257     if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
01258     {
01259        hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01260     }
01261 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
01262     defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
01263     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
01264     defined(STM32F479xx)
01265    /* FullDuplexMode feature enabled */
01266     else
01267     {
01268       if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
01269       {
01270         /* Disable Rx DMA Request for the I2SEx Slave */
01271         I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01272       }
01273       else
01274       {
01275         /* Disable Rx DMA Request for the I2S Master*/
01276         hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
01277       }
01278     }
01279 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
01280           STM32F469xx || STM32F479xx */
01281
01282     hi2s->RxXferCount = 0U;
01283     if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
01284     {
01285       if(hi2s->TxXferCount == 0U)
01286       {
01287         hi2s->State = HAL_I2S_STATE_READY;
01288       }
01289     }
01290     else
01291     {
01292       hi2s->State = HAL_I2S_STATE_READY;
01293     }
01294   }
01295   HAL_I2S_RxCpltCallback(hi2s);
01296 }
01297
01298 /**
01299   * @brief  Get I2S clock Input based on Source clock selection in RCC
01300   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01301   *         the configuration information for I2S module
01302   * @retval I2S Clock Input
01303   */
01304 uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
01305 {
01306   /* This variable used to store the VCO Input (value in Hz) */
01307   uint32_t vcoinput = 0U;
01308   /* This variable used to store the VCO Output (value in Hz) */
01309   uint32_t vcooutput = 0U;
01310   /* This variable used to store the I2S_CK_x (value in Hz) */
01311   uint32_t i2ssourceclock = 0U;
01312
01313   /* Configure 12S Clock based on I2S source clock selection */
01314 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
01315   switch(hi2s->Init.ClockSource)
01316   {
01317     case I2S_CLOCK_EXTERNAL :
01318     {
01319       /* Set the I2S clock to the external clock  value */
01320       i2ssourceclock = EXTERNAL_CLOCK_VALUE;
01321       break;
01322     }
01323 #if defined(STM32F446xx)
01324     case I2S_CLOCK_PLL :
01325     {
01326       /* Configure the PLLI2S division factor */
01327       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
01328       if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
01329       {
01330         /* Get the I2S source clock value */
01331         vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
01332       }
01333       else
01334       {
01335         /* Get the I2S source clock value */
01336         vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
01337       }
01338
01339       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
01340       vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
01341       /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
01342       i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
01343       break;
01344     }
01345 #endif /* STM32F446xx */
01346     case I2S_CLOCK_PLLR :
01347     {
01348       /* Configure the PLLI2S division factor */
01349       /* PLL_VCO Input  = PLL_SOURCE/PLLM */
01350       if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
01351       {
01352         /* Get the I2S source clock value */
01353         vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
01354       }
01355       else
01356       {
01357         /* Get the I2S source clock value */
01358         vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
01359       }
01360
01361       /* PLL_VCO Output = PLL_VCO Input * PLLN */
01362       vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
01363       /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
01364       i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
01365       break;
01366     }
01367     case I2S_CLOCK_PLLSRC :
01368     {
01369       /* Configure the PLLI2S division factor */
01370       /* PLL_VCO Input  = PLL_SOURCE/PLLM */
01371       if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
01372       {
01373         /* Get the I2S source clock value */
01374         i2ssourceclock = (uint32_t)(HSE_VALUE);
01375       }
01376       else
01377       {
01378         /* Get the I2S source clock value */
01379         i2ssourceclock = (uint32_t)(HSI_VALUE);
01380       }
01381       break;
01382     }
01383     default :
01384     {
01385       break;
01386     }
01387   }
01388 #endif /* STM32F410xx || STM32F446xx */
01389
01390 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
01391     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
01392     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F469xx) || defined(STM32F479xx)
01393
01394   /* If an external I2S clock has to be used, the specific define should be set
01395   in the project configuration or in the stm32f4xx_conf.h file */
01396   if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
01397   {
01398     __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
01399     /* Set the I2S clock to the external clock  value */
01400     i2ssourceclock = EXTERNAL_CLOCK_VALUE;
01401   }
01402   else
01403   {
01404     /* Configure the PLLI2S division factor */
01405     /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
01406     if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
01407     {
01408       /* Get the I2S source clock value */
01409       vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
01410     }
01411     else
01412     {
01413       /* Get the I2S source clock value */
01414       vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
01415     }
01416
01417     /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
01418     vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
01419     /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
01420     i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
01421   }
01422 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
01423
01424 #if defined(STM32F411xE)
01425
01426   /* If an external I2S clock has to be used, the specific define should be set
01427   in the project configuration or in the stm32f4xx_conf.h file */
01428   if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
01429   {
01430     __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
01431     /* Set the I2S clock to the external clock  value */
01432     i2ssourceclock = EXTERNAL_CLOCK_VALUE;
01433   }
01434   else
01435   {
01436     /* Configure the PLLI2S division factor */
01437     /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
01438     if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
01439     {
01440       /* Get the I2S source clock value */
01441       vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
01442     }
01443     else
01444     {
01445       /* Get the I2S source clock value */
01446       vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
01447     }
01448
01449     /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
01450     vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
01451     /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
01452     i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
01453   }
01454 #endif /* STM32F411xE */
01455
01456   /* the return result is the value of SAI clock */
01457   return i2ssourceclock;
01458 }
01459 /**
01460   * @}
01461   */
01462
01463 /**
01464   * @}
01465   */
01466
01467 #endif /* HAL_I2S_MODULE_ENABLED */
01468 /**
01469   * @}
01470   */
01471
01472 /**
01473   * @}
01474   */
01475
01476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_i2s_ex.h Source File

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stm32f4xx_hal_i2s_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_i2s_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of I2S HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_I2S_EX_H
00040 #define __STM32F4xx_HAL_I2S_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2SEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2SEx_Exported_Types I2S Exported Types
00059   * @{
00060   */
00061 /**
00062   * @}
00063   */
00064
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup I2SEx_Exported_Constants I2S Exported Constants
00067   * @{
00068   */
00069
00070 /** @defgroup I2S_Clock_Source I2S Clock Source
00071   * @{
00072   */
00073
00074 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00075     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00076     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
00077     defined(STM32F479xx)
00078 #define I2S_CLOCK_PLL                     ((uint32_t)0x00000000U)
00079 #define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U)
00080 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00081           STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
00082
00083 #if defined(STM32F446xx)
00084 #define I2S_CLOCK_PLL                     ((uint32_t)0x00000000U)
00085 #define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U)
00086 #define I2S_CLOCK_PLLR                    ((uint32_t)0x00000002U)
00087 #define I2S_CLOCK_PLLSRC                  ((uint32_t)0x00000003U)
00088 #endif /* STM32F446xx */
00089
00090 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00091 #define I2S_CLOCK_PLLSRC                  ((uint32_t)0x00000000U)
00092 #define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U)
00093 #define I2S_CLOCK_PLLR                    ((uint32_t)0x00000002U)
00094 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported macro ------------------------------------------------------------*/
00104 /** @defgroup I2SEx_Exported_Macros I2S Exported Macros
00105   * @{
00106   */
00107
00108 /**
00109   * @}
00110   */
00111
00112 /* Exported functions --------------------------------------------------------*/
00113 /** @addtogroup I2SEx_Exported_Functions
00114   * @{
00115   */
00116
00117 /** @addtogroup I2SEx_Exported_Functions_Group1
00118   * @{
00119   */
00120
00121 /* Extended features functions **************************************************/
00122 /* Blocking mode: Polling */
00123 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
00124 /* Non-Blocking mode: Interrupt */
00125 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
00126 /* Non-Blocking mode: DMA */
00127 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
00128 /**
00129   * @}
00130   */
00131
00132 /**
00133   * @}
00134   */
00135 /* Private types -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private constants ---------------------------------------------------------*/
00138 /** @defgroup I2SEx_Private_Constants I2S Private Constants
00139   * @{
00140   */
00141 /**
00142   * @}
00143   */
00144
00145 /* Private macros ------------------------------------------------------------*/
00146 /** @defgroup I2SEx_Private_Macros I2S Private Macros
00147   * @{
00148   */
00149 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00150     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00151     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
00152     defined(STM32F479xx)
00153 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
00154                                    ((CLOCK) == I2S_CLOCK_PLL))
00155 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00156           STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
00157
00158 #if defined(STM32F446xx)
00159 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
00160                                    ((CLOCK) == I2S_CLOCK_PLL)      ||\
00161                                    ((CLOCK) == I2S_CLOCK_PLLSRC)   ||\
00162                                    ((CLOCK) == I2S_CLOCK_PLLR))
00163 #endif /* STM32F446xx */
00164
00165 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00166 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
00167                                    ((CLOCK) == I2S_CLOCK_PLLSRC)     ||\
00168                                    ((CLOCK) == I2S_CLOCK_PLLR))
00169 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00170
00171 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00172     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00173     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Cx) || defined(STM32F410Rx) || \
00174     defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00175 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
00176 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00177           STM32F401xC || STM32F401xE || STM32F410Cx || STM32F410Rx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Private functions ---------------------------------------------------------*/
00184 /** @defgroup I2SEx_Private_Functions I2S Private Functions
00185   * @{
00186   */
00187 HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s);
00188 uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s);
00189 /**
00190   * @}
00191   */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /**
00198   * @}
00199   */
00200
00201 #ifdef __cplusplus
00202 }
00203 #endif
00204
00205
00206 #endif /* __STM32F4xx_HAL_I2S_EX_H */
00207
00208 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_irda.c Source File

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stm32f4xx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   IRDA HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the IrDA SIR ENDEC block (IrDA):
00010   *           + Initialization and de-initialization methods
00011   *           + IO operation methods
00012   *           + Peripheral Control methods
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The IRDA HAL driver can be used as follows:
00020
00021     (#) Declare a IRDA_HandleTypeDef handle structure.
00022     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
00023         (##) Enable the USARTx interface clock.
00024         (##) IRDA pins configuration:
00025             (+++) Enable the clock for the IRDA GPIOs.
00026             (+++) Configure these IRDA pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00028              and HAL_IRDA_Receive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031         (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00032              and HAL_IRDA_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036             (+++) Configure the DMA Tx/Rx Stream.
00037             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
00039
00040     (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
00041         and Mode(Receiver/Transmitter) in the hirda Init structure.
00042
00043     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00044         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00045             by calling the customized HAL_IRDA_MspInit() API.
00046     -@@- The specific IRDA interrupts (Transmission complete interrupt,
00047         RXNE interrupt and Error Interrupts) will be managed using the macros
00048         __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00049
00050     (#) Three operation modes are available within this driver :
00051
00052     *** Polling mode IO operation ***
00053     =================================
00054     [..]
00055       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00056       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00057
00058     *** Interrupt mode IO operation ***
00059     ===================================
00060     [..]
00061       (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
00062       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
00063            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
00064       (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
00065       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
00066            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
00067       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00068            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
00069
00070     *** DMA mode IO operation ***
00071     =============================
00072     [..]
00073       (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00074       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
00075            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
00076       (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00077       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
00078            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
00079       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00080            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
00081
00082     *** IRDA HAL driver macros list ***
00083     ===================================
00084     [..]
00085       Below the list of most used macros in IRDA HAL driver.
00086
00087      (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00088      (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00089      (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
00090      (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
00091      (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
00092      (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
00093
00094      (@) You can refer to the IRDA HAL driver header file for more useful macros
00095
00096   @endverbatim
00097   ******************************************************************************
00098   * @attention
00099   *
00100   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00101   *
00102   * Redistribution and use in source and binary forms, with or without modification,
00103   * are permitted provided that the following conditions are met:
00104   *   1. Redistributions of source code must retain the above copyright notice,
00105   *      this list of conditions and the following disclaimer.
00106   *   2. Redistributions in binary form must reproduce the above copyright notice,
00107   *      this list of conditions and the following disclaimer in the documentation
00108   *      and/or other materials provided with the distribution.
00109   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00110   *      may be used to endorse or promote products derived from this software
00111   *      without specific prior written permission.
00112   *
00113   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00114   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00115   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00116   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00117   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00118   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00119   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00120   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00121   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00122   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00123   *
00124   ******************************************************************************
00125   */
00126
00127 /* Includes ------------------------------------------------------------------*/
00128 #include "stm32f4xx_hal.h"
00129
00130 /** @addtogroup STM32F4xx_HAL_Driver
00131   * @{
00132   */
00133
00134 /** @defgroup IRDA IRDA
00135   * @brief HAL IRDA module driver
00136   * @{
00137   */
00138
00139 #ifdef HAL_IRDA_MODULE_ENABLED
00140
00141 /* Private typedef -----------------------------------------------------------*/
00142 /* Private define ------------------------------------------------------------*/
00143 /** @addtogroup IRDA_Private_Constants
00144   * @{
00145   */
00146 /**
00147   * @}
00148   */
00149 /* Private macro -------------------------------------------------------------*/
00150 /* Private variables ---------------------------------------------------------*/
00151 /* Private function prototypes -----------------------------------------------*/
00152 /** @addtogroup IRDA_Private_Functions
00153   * @{
00154   */
00155 static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
00156 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00157 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00158 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00159 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00160 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00161 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00162 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00163 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00164 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00165 /**
00166   * @}
00167   */
00168 /* Exported functions --------------------------------------------------------*/
00169 /** @defgroup IRDA_Exported_Functions IrDA Exported Functions
00170   * @{
00171   */
00172
00173 /** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
00174   *  @brief    Initialization and Configuration functions
00175   *
00176 @verbatim
00177
00178 ===============================================================================
00179             ##### Initialization and Configuration functions #####
00180  ===============================================================================
00181     [..]
00182     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00183     in IrDA mode.
00184       (+) For the asynchronous mode only these parameters can be configured:
00185         (++) BaudRate
00186         (++) WordLength
00187         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00188              in the data register is transmitted but is changed by the parity bit.
00189              Depending on the frame length defined by the M bit (8-bits or 9-bits),
00190              please refer to Reference manual for possible IRDA frame formats.
00191         (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
00192              not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
00193              specification specifies a minimum of 10 ms delay between transmission and
00194              reception (IrDA is a half duplex protocol).
00195         (++) Mode: Receiver/transmitter modes
00196         (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
00197     [..]
00198     The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
00199     are available in reference manual).
00200
00201 @endverbatim
00202   * @{
00203   */
00204
00205 /**
00206   * @brief  Initializes the IRDA mode according to the specified
00207   *         parameters in the IRDA_InitTypeDef and create the associated handle.
00208   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00209   *                the configuration information for the specified IRDA module.
00210   * @retval HAL status
00211   */
00212 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00213 {
00214   /* Check the IRDA handle allocation */
00215   if(hirda == NULL)
00216   {
00217     return HAL_ERROR;
00218   }
00219
00220   /* Check the IRDA instance parameters */
00221   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00222   /* Check the IRDA mode parameter in the IRDA handle */
00223   assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
00224
00225   if(hirda->gState == HAL_IRDA_STATE_RESET)
00226   {
00227     /* Allocate lock resource and initialize it */
00228     hirda->Lock = HAL_UNLOCKED;
00229     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00230     HAL_IRDA_MspInit(hirda);
00231   }
00232
00233   hirda->gState = HAL_IRDA_STATE_BUSY;
00234
00235   /* Disable the IRDA peripheral */
00236   __HAL_IRDA_DISABLE(hirda);
00237
00238   /* Set the IRDA communication parameters */
00239   IRDA_SetConfig(hirda);
00240
00241   /* In IrDA mode, the following bits must be kept cleared:
00242      - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00243      - SCEN and HDSEL bits in the USART_CR3 register.*/
00244   hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
00245   hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
00246
00247   /* Enable the IRDA peripheral */
00248   __HAL_IRDA_ENABLE(hirda);
00249
00250   /* Set the prescaler */
00251   MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
00252
00253   /* Configure the IrDA mode */
00254   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
00255
00256   /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00257   hirda->Instance->CR3 |= USART_CR3_IREN;
00258
00259   /* Initialize the IRDA state*/
00260   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00261   hirda->gState= HAL_IRDA_STATE_READY;
00262   hirda->RxState= HAL_IRDA_STATE_READY;
00263
00264   return HAL_OK;
00265 }
00266
00267 /**
00268   * @brief  DeInitializes the IRDA peripheral
00269   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00270   *                the configuration information for the specified IRDA module.
00271   * @retval HAL status
00272   */
00273 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00274 {
00275   /* Check the IRDA handle allocation */
00276   if(hirda == NULL)
00277   {
00278     return HAL_ERROR;
00279   }
00280
00281   /* Check the parameters */
00282   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00283
00284   hirda->gState = HAL_IRDA_STATE_BUSY;
00285
00286   /* Disable the Peripheral */
00287   __HAL_IRDA_DISABLE(hirda);
00288
00289   /* DeInit the low level hardware */
00290   HAL_IRDA_MspDeInit(hirda);
00291
00292   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00293
00294   hirda->gState = HAL_IRDA_STATE_RESET;
00295   hirda->RxState = HAL_IRDA_STATE_RESET;
00296
00297   /* Release Lock */
00298   __HAL_UNLOCK(hirda);
00299
00300   return HAL_OK;
00301 }
00302
00303 /**
00304   * @brief  IRDA MSP Init.
00305   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00306   *                the configuration information for the specified IRDA module.
00307   * @retval None
00308   */
00309  __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00310 {
00311   /* Prevent unused argument(s) compilation warning */
00312   UNUSED(hirda);
00313   /* NOTE : This function Should not be modified, when the callback is needed,
00314             the HAL_IRDA_MspInit could be implemented in the user file
00315    */
00316 }
00317
00318 /**
00319   * @brief  IRDA MSP DeInit.
00320   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00321   *                the configuration information for the specified IRDA module.
00322   * @retval None
00323   */
00324  __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00325 {
00326   /* Prevent unused argument(s) compilation warning */
00327   UNUSED(hirda);
00328   /* NOTE : This function Should not be modified, when the callback is needed,
00329             the HAL_IRDA_MspDeInit could be implemented in the user file
00330    */
00331 }
00332
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00338   *  @brief   IRDA Transmit/Receive functions
00339   *
00340 @verbatim
00341  ===============================================================================
00342                       ##### IO operation functions #####
00343  ===============================================================================
00344     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00345     [..]
00346     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00347     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00348     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00349     While receiving data, transmission should be avoided as the data to be transmitted
00350     could be corrupted.
00351
00352     (#) There are two modes of transfer:
00353        (++) Blocking mode: The communication is performed in polling mode.
00354             The HAL status of all data processing is returned by the same function
00355             after finishing transfer.
00356        (++) No-Blocking mode: The communication is performed using Interrupts
00357            or DMA, These APIs return the HAL status.
00358            The end of the data processing will be indicated through the
00359            dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00360            using DMA mode.
00361            The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00362            will be executed respectively at the end of the transmit or Receive process
00363            The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00364
00365     (#) Blocking mode API's are :
00366         (++) HAL_IRDA_Transmit()
00367         (++) HAL_IRDA_Receive()
00368
00369     (#) Non Blocking mode APIs with Interrupt are :
00370         (++) HAL_IRDA_Transmit_IT()
00371         (++) HAL_IRDA_Receive_IT()
00372         (++) HAL_IRDA_IRQHandler()
00373
00374     (#) Non Blocking mode functions with DMA are :
00375         (++) HAL_IRDA_Transmit_DMA()
00376         (++) HAL_IRDA_Receive_DMA()
00377
00378     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00379         (++) HAL_IRDA_TxCpltCallback()
00380         (++) HAL_IRDA_RxCpltCallback()
00381         (++) HAL_IRDA_ErrorCallback()
00382
00383 @endverbatim
00384   * @{
00385   */
00386
00387 /**
00388   * @brief  Sends an amount of data in blocking mode.
00389   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00390   *                the configuration information for the specified IRDA module.
00391   * @param  pData: Pointer to data buffer
00392   * @param  Size: Amount of data to be sent
00393   * @param  Timeout: Specify timeout value
00394   * @retval HAL status
00395   */
00396 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00397 {
00398   uint16_t* tmp;
00399
00400   /* Check that a Tx process is not already ongoing */
00401   if(hirda->gState == HAL_IRDA_STATE_READY)
00402   {
00403     if((pData == NULL) || (Size == 0U))
00404     {
00405       return  HAL_ERROR;
00406     }
00407
00408     /* Process Locked */
00409     __HAL_LOCK(hirda);
00410
00411     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00412     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00413
00414     hirda->TxXferSize = Size;
00415     hirda->TxXferCount = Size;
00416     while(hirda->TxXferCount > 0U)
00417     {
00418       hirda->TxXferCount--;
00419       if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
00420       {
00421         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
00422         {
00423           return HAL_TIMEOUT;
00424         }
00425         tmp = (uint16_t*) pData;
00426         hirda->Instance->DR = (*tmp & (uint16_t)0x01FFU);
00427         if(hirda->Init.Parity == IRDA_PARITY_NONE)
00428         {
00429           pData +=2U;
00430         }
00431         else
00432         {
00433           pData +=1U;
00434         }
00435       }
00436       else
00437       {
00438         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
00439         {
00440           return HAL_TIMEOUT;
00441         }
00442         hirda->Instance->DR = (*pData++ & (uint8_t)0xFFU);
00443       }
00444     }
00445
00446     if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
00447     {
00448       return HAL_TIMEOUT;
00449     }
00450
00451         /* At end of Tx process, restore hirda->gState to Ready */
00452     hirda->gState = HAL_IRDA_STATE_READY;
00453
00454     /* Process Unlocked */
00455     __HAL_UNLOCK(hirda);
00456
00457     return HAL_OK;
00458   }
00459   else
00460   {
00461     return HAL_BUSY;
00462   }
00463 }
00464
00465 /**
00466   * @brief  Receive an amount of data in blocking mode.
00467   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00468   *                the configuration information for the specified IRDA module.
00469   * @param  pData: Pointer to data buffer
00470   * @param  Size: Amount of data to be received
00471   * @param  Timeout: Specify timeout value
00472   * @retval HAL status
00473   */
00474 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00475 {
00476   uint16_t* tmp;
00477
00478   /* Check that a Rx process is not already ongoing */
00479   if(hirda->RxState == HAL_IRDA_STATE_READY)
00480   {
00481     if((pData == NULL) || (Size == 0U))
00482     {
00483       return  HAL_ERROR;
00484     }
00485
00486     /* Process Locked */
00487     __HAL_LOCK(hirda);
00488
00489     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00490     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00491
00492     hirda->RxXferSize = Size;
00493     hirda->RxXferCount = Size;
00494     /* Check the remain data to be received */
00495     while(hirda->RxXferCount > 0U)
00496     {
00497       hirda->RxXferCount--;
00498       if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
00499       {
00500         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00501         {
00502           return HAL_TIMEOUT;
00503         }
00504         tmp = (uint16_t*) pData ;
00505         if(hirda->Init.Parity == IRDA_PARITY_NONE)
00506         {
00507           *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FFU);
00508            pData +=2U;
00509         }
00510         else
00511         {
00512           *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FFU);
00513           pData +=1U;
00514         }
00515       }
00516       else
00517       {
00518         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00519         {
00520           return HAL_TIMEOUT;
00521         }
00522         if(hirda->Init.Parity == IRDA_PARITY_NONE)
00523         {
00524           *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FFU);
00525         }
00526         else
00527         {
00528           *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007FU);
00529         }
00530       }
00531     }
00532
00533         /* At end of Rx process, restore hirda->RxState to Ready */
00534     hirda->RxState = HAL_IRDA_STATE_READY;
00535
00536     /* Process Unlocked */
00537     __HAL_UNLOCK(hirda);
00538
00539     return HAL_OK;
00540   }
00541   else
00542   {
00543     return HAL_BUSY;
00544   }
00545 }
00546
00547 /**
00548   * @brief  Send an amount of data in non blocking mode.
00549   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00550   *                the configuration information for the specified IRDA module.
00551   * @param  pData: Pointer to data buffer
00552   * @param  Size: Amount of data to be sent
00553   * @retval HAL status
00554   */
00555 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00556 {
00557   /* Check that a Tx process is not already ongoing */
00558   if(hirda->gState == HAL_IRDA_STATE_READY)
00559   {
00560     if((pData == NULL) || (Size == 0U))
00561     {
00562       return HAL_ERROR;
00563     }
00564     /* Process Locked */
00565     __HAL_LOCK(hirda);
00566
00567     hirda->pTxBuffPtr = pData;
00568     hirda->TxXferSize = Size;
00569     hirda->TxXferCount = Size;
00570     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00571     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00572
00573    /* Process Unlocked */
00574     __HAL_UNLOCK(hirda);
00575
00576     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00577     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
00578
00579     /* Enable the IRDA Transmit Data Register Empty Interrupt */
00580     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
00581
00582     return HAL_OK;
00583   }
00584   else
00585   {
00586     return HAL_BUSY;
00587   }
00588 }
00589
00590 /**
00591   * @brief  Receives an amount of data in non blocking mode.
00592   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00593   *                the configuration information for the specified IRDA module.
00594   * @param  pData: Pointer to data buffer
00595   * @param  Size: Amount of data to be received
00596   * @retval HAL status
00597   */
00598 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00599 {
00600   /* Check that a Rx process is not already ongoing */
00601   if(hirda->RxState == HAL_IRDA_STATE_READY)
00602   {
00603     if((pData == NULL) || (Size == 0U))
00604     {
00605       return HAL_ERROR;
00606     }
00607
00608     /* Process Locked */
00609     __HAL_LOCK(hirda);
00610
00611     hirda->pRxBuffPtr = pData;
00612     hirda->RxXferSize = Size;
00613     hirda->RxXferCount = Size;
00614     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00615     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00616
00617     /* Process Unlocked */
00618     __HAL_UNLOCK(hirda);
00619
00620     /* Enable the IRDA Data Register not empty Interrupt */
00621     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
00622
00623     /* Enable the IRDA Parity Error Interrupt */
00624     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
00625
00626     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00627     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
00628
00629     return HAL_OK;
00630   }
00631   else
00632   {
00633     return HAL_BUSY;
00634   }
00635 }
00636
00637 /**
00638   * @brief  Sends an amount of data in non blocking mode.
00639   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00640   *                the configuration information for the specified IRDA module.
00641   * @param  pData: Pointer to data buffer
00642   * @param  Size: Amount of data to be sent
00643   * @retval HAL status
00644   */
00645 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00646 {
00647   uint32_t *tmp;
00648
00649   /* Check that a Tx process is not already ongoing */
00650   if(hirda->gState == HAL_IRDA_STATE_READY)
00651   {
00652     if((pData == NULL) || (Size == 0U))
00653     {
00654       return HAL_ERROR;
00655     }
00656
00657     /* Process Locked */
00658     __HAL_LOCK(hirda);
00659
00660     hirda->pTxBuffPtr = pData;
00661     hirda->TxXferSize = Size;
00662     hirda->TxXferCount = Size;
00663     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00664     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00665
00666     /* Set the IRDA DMA transfer complete callback */
00667     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
00668
00669     /* Set the IRDA DMA half transfer complete callback */
00670     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
00671
00672     /* Set the DMA error callback */
00673     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
00674
00675     /* Enable the IRDA transmit DMA Stream */
00676     tmp = (uint32_t*)&pData;
00677     HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
00678
00679     /* Clear the TC flag in the SR register by writing 0 to it */
00680     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
00681
00682     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00683        in the USART CR3 register */
00684     hirda->Instance->CR3 |= USART_CR3_DMAT;
00685
00686     /* Process Unlocked */
00687     __HAL_UNLOCK(hirda);
00688
00689     return HAL_OK;
00690   }
00691   else
00692   {
00693     return HAL_BUSY;
00694   }
00695 }
00696
00697 /**
00698   * @brief  Receives an amount of data in non blocking mode.
00699   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00700   *                the configuration information for the specified IRDA module.
00701   * @param  pData: Pointer to data buffer
00702   * @param  Size: Amount of data to be received
00703   * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
00704   * @retval HAL status
00705   */
00706 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00707 {
00708   uint32_t *tmp;
00709
00710   /* Check that a Rx process is not already ongoing */
00711   if(hirda->RxState == HAL_IRDA_STATE_READY)
00712   {
00713     if((pData == NULL) || (Size == 0U))
00714     {
00715       return HAL_ERROR;
00716     }
00717
00718     /* Process Locked */
00719     __HAL_LOCK(hirda);
00720
00721     hirda->pRxBuffPtr = pData;
00722     hirda->RxXferSize = Size;
00723     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00724     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00725
00726     /* Set the IRDA DMA transfer complete callback */
00727     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
00728
00729     /* Set the IRDA DMA half transfer complete callback */
00730     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
00731
00732     /* Set the DMA error callback */
00733     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
00734
00735     /* Enable the DMA Stream */
00736     tmp = (uint32_t*)&pData;
00737     HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
00738
00739     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00740        in the USART CR3 register */
00741     hirda->Instance->CR3 |= USART_CR3_DMAR;
00742
00743     /* Process Unlocked */
00744     __HAL_UNLOCK(hirda);
00745
00746     return HAL_OK;
00747   }
00748   else
00749   {
00750     return HAL_BUSY;
00751   }
00752 }
00753
00754 /**
00755   * @brief Pauses the DMA Transfer.
00756   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00757   *                the configuration information for the specified IRDA module.
00758   * @retval HAL status
00759   */
00760 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
00761 {
00762   /* Process Locked */
00763   __HAL_LOCK(hirda);
00764
00765   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
00766   {
00767     /* Disable the UART DMA Tx request */
00768     hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
00769   }
00770   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
00771   {
00772     /* Disable the UART DMA Rx request */
00773     hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
00774   }
00775
00776   /* Process Unlocked */
00777   __HAL_UNLOCK(hirda);
00778
00779   return HAL_OK;
00780 }
00781
00782 /**
00783   * @brief Resumes the DMA Transfer.
00784   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00785   *                the configuration information for the specified UART module.
00786   * @retval HAL status
00787   */
00788 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
00789 {
00790   /* Process Locked */
00791   __HAL_LOCK(hirda);
00792
00793   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
00794   {
00795     /* Enable the UART DMA Tx request */
00796     hirda->Instance->CR3 |= USART_CR3_DMAT;
00797   }
00798   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
00799   {
00800     /* Clear the Overrun flag before resuming the Rx transfer */
00801     __HAL_IRDA_CLEAR_OREFLAG(hirda);
00802     /* Enable the UART DMA Rx request */
00803     hirda->Instance->CR3 |= USART_CR3_DMAR;
00804   }
00805
00806   /* Process Unlocked */
00807   __HAL_UNLOCK(hirda);
00808
00809   return HAL_OK;
00810 }
00811
00812 /**
00813   * @brief Stops the DMA Transfer.
00814   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00815   *                the configuration information for the specified UART module.
00816   * @retval HAL status
00817   */
00818 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
00819 {
00820   /* The Lock is not implemented on this API to allow the user application
00821      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
00822      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
00823      and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
00824      */
00825
00826   /* Disable the UART Tx/Rx DMA requests */
00827   hirda->Instance->CR3 &= ~USART_CR3_DMAT;
00828   hirda->Instance->CR3 &= ~USART_CR3_DMAR;
00829
00830   /* Abort the UART DMA tx Stream */
00831   if(hirda->hdmatx != NULL)
00832   {
00833     HAL_DMA_Abort(hirda->hdmatx);
00834   }
00835   /* Abort the UART DMA rx Stream */
00836   if(hirda->hdmarx != NULL)
00837   {
00838     HAL_DMA_Abort(hirda->hdmarx);
00839   }
00840
00841   hirda->gState = HAL_IRDA_STATE_READY;
00842   hirda->RxState = HAL_IRDA_STATE_READY;
00843
00844   return HAL_OK;
00845 }
00846
00847 /**
00848   * @brief  This function handles IRDA interrupt request.
00849   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00850   *                the configuration information for the specified IRDA module.
00851   * @retval None
00852   */
00853 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
00854 {
00855   uint32_t  tmp1 = 0U, tmp2 = 0U;
00856
00857   tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
00858   tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
00859   /* IRDA parity error interrupt occurred -------------------------------------*/
00860   if((tmp1 != RESET) && (tmp2 != RESET))
00861   {
00862     __HAL_IRDA_CLEAR_PEFLAG(hirda);
00863     hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
00864   }
00865
00866   tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
00867   tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
00868   /* IRDA frame error interrupt occurred --------------------------------------*/
00869   if((tmp1 != RESET) && (tmp2 != RESET))
00870   {
00871     __HAL_IRDA_CLEAR_FEFLAG(hirda);
00872     hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
00873   }
00874
00875   tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
00876   tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
00877   /* IRDA noise error interrupt occurred --------------------------------------*/
00878   if((tmp1 != RESET) && (tmp2 != RESET))
00879   {
00880     __HAL_IRDA_CLEAR_NEFLAG(hirda);
00881     hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
00882   }
00883
00884   tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
00885   tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
00886   /* IRDA Over-Run interrupt occurred -----------------------------------------*/
00887   if((tmp1 != RESET) && (tmp2 != RESET))
00888   {
00889     __HAL_IRDA_CLEAR_OREFLAG(hirda);
00890     hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
00891   }
00892
00893   /* Call the Error call Back in case of Errors */
00894   if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
00895   {
00896     /* Set the IRDA state ready to be able to start again the process */
00897     hirda->gState = HAL_IRDA_STATE_READY;
00898         hirda->RxState = HAL_IRDA_STATE_READY;
00899     HAL_IRDA_ErrorCallback(hirda);
00900   }
00901
00902   tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE);
00903   tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE);
00904   /* IRDA in mode Receiver ---------------------------------------------------*/
00905   if((tmp1 != RESET) && (tmp2 != RESET))
00906   {
00907     IRDA_Receive_IT(hirda);
00908   }
00909
00910   tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE);
00911   tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE);
00912   /* IRDA in mode Transmitter ------------------------------------------------*/
00913   if((tmp1 != RESET) &&(tmp2 != RESET))
00914   {
00915     IRDA_Transmit_IT(hirda);
00916   }
00917
00918   tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
00919   tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
00920   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
00921   if((tmp1 != RESET) && (tmp2 != RESET))
00922   {
00923     IRDA_EndTransmit_IT(hirda);
00924   }
00925 }
00926
00927 /**
00928   * @brief  Tx Transfer complete callbacks.
00929   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00930   *                the configuration information for the specified IRDA module.
00931   * @retval None
00932   */
00933  __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
00934 {
00935   /* Prevent unused argument(s) compilation warning */
00936   UNUSED(hirda);
00937   /* NOTE : This function Should not be modified, when the callback is needed,
00938             the HAL_IRDA_TxCpltCallback could be implemented in the user file
00939    */
00940 }
00941
00942 /**
00943   * @brief  Tx Half Transfer completed callbacks.
00944   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00945   *                the configuration information for the specified USART module.
00946   * @retval None
00947   */
00948  __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
00949 {
00950   /* Prevent unused argument(s) compilation warning */
00951   UNUSED(hirda);
00952   /* NOTE: This function Should not be modified, when the callback is needed,
00953            the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
00954    */
00955 }
00956
00957 /**
00958   * @brief  Rx Transfer complete callbacks.
00959   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00960   *                the configuration information for the specified IRDA module.
00961   * @retval None
00962   */
00963 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
00964 {
00965   /* Prevent unused argument(s) compilation warning */
00966   UNUSED(hirda);
00967   /* NOTE : This function Should not be modified, when the callback is needed,
00968             the HAL_IRDA_RxCpltCallback could be implemented in the user file
00969    */
00970 }
00971
00972 /**
00973   * @brief  Rx Half Transfer complete callbacks.
00974   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00975   *                the configuration information for the specified IRDA module.
00976   * @retval None
00977   */
00978 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
00979 {
00980   /* Prevent unused argument(s) compilation warning */
00981   UNUSED(hirda);
00982   /* NOTE : This function Should not be modified, when the callback is needed,
00983             the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
00984    */
00985 }
00986
00987 /**
00988   * @brief IRDA error callbacks.
00989   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
00990   *                the configuration information for the specified IRDA module.
00991   * @retval None
00992   */
00993  __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
00994 {
00995   /* Prevent unused argument(s) compilation warning */
00996   UNUSED(hirda);
00997   /* NOTE : This function Should not be modified, when the callback is needed,
00998             the HAL_IRDA_ErrorCallback could be implemented in the user file
00999    */
01000 }
01001
01002 /**
01003   * @}
01004   */
01005
01006 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
01007   *  @brief   IRDA State and Errors functions
01008   *
01009 @verbatim
01010   ==============================================================================
01011                   ##### Peripheral State and Errors functions #####
01012   ==============================================================================
01013   [..]
01014     This subsection provides a set of functions allowing to return the State of IrDA
01015     communication process and also return Peripheral Errors occurred during communication process
01016      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
01017      (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
01018
01019 @endverbatim
01020   * @{
01021   */
01022
01023 /**
01024   * @brief  Returns the IRDA state.
01025   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01026   *                the configuration information for the specified IRDA module.
01027   * @retval HAL state
01028   */
01029 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
01030 {
01031   uint32_t temp1 = 0x00U, temp2 = 0x00U;
01032   temp1 = hirda->gState;
01033   temp2 = hirda->RxState;
01034
01035   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
01036 }
01037
01038 /**
01039   * @brief  Return the IARDA error code
01040   * @param  hirda : pointer to a IRDA_HandleTypeDef structure that contains
01041   *              the configuration information for the specified IRDA.
01042   * @retval IRDA Error Code
01043   */
01044 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
01045 {
01046   return hirda->ErrorCode;
01047 }
01048
01049 /**
01050   * @}
01051   */
01052
01053 /**
01054   * @brief  DMA IRDA transmit process complete callback.
01055   * @param  hdma : DMA handle
01056   * @retval None
01057   */
01058 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01059 {
01060   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01061   /* DMA Normal mode */
01062   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01063   {
01064     hirda->TxXferCount = 0U;
01065
01066     /* Disable the DMA transfer for transmit request by setting the DMAT bit
01067        in the IRDA CR3 register */
01068     hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
01069
01070     /* Enable the IRDA Transmit Complete Interrupt */
01071     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
01072   }
01073   /* DMA Circular mode */
01074   else
01075   {
01076     HAL_IRDA_TxCpltCallback(hirda);
01077   }
01078 }
01079
01080 /**
01081   * @brief DMA IRDA receive process half complete callback
01082   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01083   *                the configuration information for the specified DMA module.
01084   * @retval None
01085   */
01086 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
01087 {
01088   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01089
01090   HAL_IRDA_TxHalfCpltCallback(hirda);
01091 }
01092
01093 /**
01094   * @brief  DMA IRDA receive process complete callback.
01095   * @param  hdma: DMA handle
01096   * @retval None
01097   */
01098 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01099 {
01100   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01101   /* DMA Normal mode */
01102   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01103   {
01104     hirda->RxXferCount = 0U;
01105
01106     /* Disable the DMA transfer for the receiver request by setting the DMAR bit
01107        in the IRDA CR3 register */
01108     hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
01109
01110         /* At end of Rx process, restore hirda->RxState to Ready */
01111     hirda->RxState = HAL_IRDA_STATE_READY;
01112   }
01113
01114   HAL_IRDA_RxCpltCallback(hirda);
01115 }
01116
01117 /**
01118   * @brief DMA IRDA receive process half complete callback
01119   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01120   *                the configuration information for the specified DMA module.
01121   * @retval None
01122   */
01123 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
01124 {
01125   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01126
01127   HAL_IRDA_RxHalfCpltCallback(hirda);
01128 }
01129
01130 /**
01131   * @brief  DMA IRDA communication error callback.
01132   * @param  hdma: DMA handle
01133   * @retval None
01134   */
01135 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
01136 {
01137   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01138
01139   hirda->RxXferCount = 0U;
01140   hirda->TxXferCount = 0U;
01141   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
01142   hirda->gState= HAL_IRDA_STATE_READY;
01143   hirda->RxState= HAL_IRDA_STATE_READY;
01144
01145   HAL_IRDA_ErrorCallback(hirda);
01146 }
01147
01148 /**
01149   * @brief  This function handles IRDA Communication Timeout.
01150   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01151   *                the configuration information for the specified IRDA module.
01152   * @param  Flag: specifies the IRDA flag to check.
01153   * @param  Status: The new Flag status (SET or RESET).
01154   * @param  Timeout: Timeout duration
01155   * @retval HAL status
01156   */
01157 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01158 {
01159   uint32_t tickstart = 0U;
01160
01161   /* Get tick */
01162   tickstart = HAL_GetTick();
01163
01164   /* Wait until flag is set */
01165   if(Status == RESET)
01166   {
01167     while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
01168     {
01169       /* Check for the Timeout */
01170       if(Timeout != HAL_MAX_DELAY)
01171       {
01172         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01173         {
01174           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01175           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
01176           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
01177           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
01178           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01179
01180           hirda->gState= HAL_IRDA_STATE_READY;
01181                   hirda->RxState= HAL_IRDA_STATE_READY;
01182
01183           /* Process Unlocked */
01184           __HAL_UNLOCK(hirda);
01185
01186           return HAL_TIMEOUT;
01187         }
01188       }
01189     }
01190   }
01191   else
01192   {
01193     while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
01194     {
01195       /* Check for the Timeout */
01196       if(Timeout != HAL_MAX_DELAY)
01197       {
01198         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01199         {
01200           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01201           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
01202           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
01203           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
01204           __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01205
01206           hirda->gState= HAL_IRDA_STATE_READY;
01207                   hirda->RxState= HAL_IRDA_STATE_READY;
01208
01209           /* Process Unlocked */
01210           __HAL_UNLOCK(hirda);
01211
01212           return HAL_TIMEOUT;
01213         }
01214       }
01215     }
01216   }
01217   return HAL_OK;
01218 }
01219
01220  /**
01221   * @brief  Send an amount of data in non blocking mode.
01222   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01223   *                the configuration information for the specified IRDA module.
01224   * @retval HAL status
01225   */
01226 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
01227 {
01228   uint16_t* tmp;
01229
01230   /* Check that a Tx process is ongoing */
01231   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01232   {
01233     if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
01234     {
01235       tmp = (uint16_t*) hirda->pTxBuffPtr;
01236       hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
01237       if(hirda->Init.Parity == IRDA_PARITY_NONE)
01238       {
01239         hirda->pTxBuffPtr += 2U;
01240       }
01241       else
01242       {
01243         hirda->pTxBuffPtr += 1U;
01244       }
01245     }
01246     else
01247     {
01248       hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU);
01249     }
01250
01251     if(--hirda->TxXferCount == 0U)
01252     {
01253       /* Disable the IRDA Transmit Data Register Empty Interrupt */
01254       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
01255
01256       /* Enable the IRDA Transmit Complete Interrupt */
01257       __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
01258     }
01259
01260     return HAL_OK;
01261   }
01262   else
01263   {
01264     return HAL_BUSY;
01265   }
01266 }
01267
01268 /**
01269   * @brief  Wraps up transmission in non blocking mode.
01270   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01271   *                the configuration information for the specified IRDA module.
01272   * @retval HAL status
01273   */
01274 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
01275 {
01276   /* Disable the IRDA Transmit Complete Interrupt */
01277   __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
01278
01279   /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01280   __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01281
01282   /* Tx process is ended, restore hirda->gState to Ready */
01283   hirda->gState = HAL_IRDA_STATE_READY;
01284
01285   HAL_IRDA_TxCpltCallback(hirda);
01286
01287   return HAL_OK;
01288 }
01289
01290 /**
01291   * @brief  Receives an amount of data in non blocking mode.
01292   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01293   *                the configuration information for the specified IRDA module.
01294   * @retval HAL status
01295   */
01296 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
01297 {
01298   uint16_t* tmp;
01299
01300   /* Check that a Rx process is ongoing */
01301   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01302   {
01303     if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
01304     {
01305       tmp = (uint16_t*) hirda->pRxBuffPtr;
01306       if(hirda->Init.Parity == IRDA_PARITY_NONE)
01307       {
01308         *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FFU);
01309         hirda->pRxBuffPtr += 2U;
01310       }
01311       else
01312       {
01313         *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FFU);
01314         hirda->pRxBuffPtr += 1U;
01315       }
01316     }
01317     else
01318     {
01319       if(hirda->Init.Parity == IRDA_PARITY_NONE)
01320       {
01321         *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FFU);
01322       }
01323       else
01324       {
01325         *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007FU);
01326       }
01327     }
01328
01329     if(--hirda->RxXferCount == 0U)
01330     {
01331
01332       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
01333
01334       /* Disable the IRDA Parity Error Interrupt */
01335       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
01336
01337       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01338       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01339
01340           /* Rx process is completed, restore hirda->RxState to Ready */
01341       hirda->RxState = HAL_IRDA_STATE_READY;
01342
01343       HAL_IRDA_RxCpltCallback(hirda);
01344
01345       return HAL_OK;
01346     }
01347     return HAL_OK;
01348   }
01349   else
01350   {
01351     return HAL_BUSY;
01352   }
01353 }
01354
01355 /**
01356   * @brief  Configures the IRDA peripheral.
01357   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01358   *                the configuration information for the specified IRDA module.
01359   * @retval None
01360   */
01361 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
01362 {
01363   uint32_t tmpreg = 0x00U;
01364
01365   /* Check the parameters */
01366   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
01367   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
01368   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
01369   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
01370   assert_param(IS_IRDA_MODE(hirda->Init.Mode));
01371
01372   /*-------------------------- IRDA CR2 Configuration ------------------------*/
01373   /* Clear STOP[13:12] bits */
01374   hirda->Instance->CR2 &= (uint32_t)~((uint32_t)USART_CR2_STOP);
01375
01376   /*-------------------------- USART CR1 Configuration -----------------------*/
01377   tmpreg = hirda->Instance->CR1;
01378
01379   /* Clear M, PCE, PS, TE and RE bits */
01380   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
01381     USART_CR1_RE));
01382
01383   /* Configure the USART Word Length, Parity and mode:
01384      Set the M bits according to hirda->Init.WordLength value
01385      Set PCE and PS bits according to hirda->Init.Parity value
01386      Set TE and RE bits according to hirda->Init.Mode value */
01387   tmpreg |= (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode;
01388
01389   /* Write to USART CR1 */
01390   hirda->Instance->CR1 = (uint32_t)tmpreg;
01391
01392   /*-------------------------- USART CR3 Configuration -----------------------*/
01393   /* Clear CTSE and RTSE bits */
01394   hirda->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
01395
01396   /*-------------------------- USART BRR Configuration -----------------------*/
01397   if((hirda->Instance == USART1) || (hirda->Instance == USART6))
01398   {
01399     hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
01400   }
01401   else
01402   {
01403     hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
01404   }
01405 }
01406 /**
01407   * @}
01408   */
01409
01410 #endif /* HAL_IRDA_MODULE_ENABLED */
01411 /**
01412   * @}
01413   */
01414
01415 /**
01416   * @}
01417   */
01418
01419 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_irda.h Source File

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stm32f4xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of IRDA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_IRDA_H
00040 #define __STM32F4xx_HAL_IRDA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief IRDA Init Structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00067                                            The baud rate is computed using the following formula:
00068                                            - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
00069                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter can be a value of @ref IRDA_Word_Length */
00073
00074   uint32_t Parity;                   /*!< Specifies the parity mode.
00075                                            This parameter can be a value of @ref IRDA_Parity
00076                                            @note When parity is enabled, the computed parity is inserted
00077                                                  at the MSB position of the transmitted data (9th bit when
00078                                                  the word length is set to 9 data bits; 8th bit when the
00079                                                  word length is set to 8 data bits). */
00080
00081   uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
00082                                            This parameter can be a value of @ref IRDA_Mode */
00083
00084   uint8_t  Prescaler;                 /*!< Specifies the Prescaler */
00085
00086   uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
00087                                            This parameter can be a value of @ref IRDA_Low_Power */
00088 }IRDA_InitTypeDef;
00089
00090 /**
00091   * @brief HAL IRDA State structures definition
00092   * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
00093   *        - gState contains IRDA state information related to global Handle management
00094   *          and also information related to Tx operations.
00095   *          gState value coding follow below described bitmap :
00096   *          b7-b6  Error information
00097   *             00 : No Error
00098   *             01 : (Not Used)
00099   *             10 : Timeout
00100   *             11 : Error
00101   *          b5     IP initilisation status
00102   *             0  : Reset (IP not initialized)
00103   *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
00104   *          b4-b3  (not used)
00105   *             xx : Should be set to 00
00106   *          b2     Intrinsic process state
00107   *             0  : Ready
00108   *             1  : Busy (IP busy with some configuration or internal operations)
00109   *          b1     (not used)
00110   *             x  : Should be set to 0
00111   *          b0     Tx state
00112   *             0  : Ready (no Tx operation ongoing)
00113   *             1  : Busy (Tx operation ongoing)
00114   *        - RxState contains information related to Rx operations.
00115   *          RxState value coding follow below described bitmap :
00116   *          b7-b6  (not used)
00117   *             xx : Should be set to 00
00118   *          b5     IP initilisation status
00119   *             0  : Reset (IP not initialized)
00120   *             1  : Init done (IP not initialized)
00121   *          b4-b2  (not used)
00122   *            xxx : Should be set to 000
00123   *          b1     Rx state
00124   *             0  : Ready (no Rx operation ongoing)
00125   *             1  : Busy (Rx operation ongoing)
00126   *          b0     (not used)
00127   *             x  : Should be set to 0.
00128   */
00129 typedef enum
00130 {
00131   HAL_IRDA_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00132                                                    Value is allowed for gState and RxState */
00133   HAL_IRDA_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00134                                                    Value is allowed for gState and RxState */
00135   HAL_IRDA_STATE_BUSY              = 0x24U,    /*!< An internal process is ongoing
00136                                                    Value is allowed for gState only */
00137   HAL_IRDA_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00138                                                    Value is allowed for gState only */
00139   HAL_IRDA_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00140                                                    Value is allowed for RxState only */
00141   HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
00142                                                    Not to be used for neither gState nor RxState.
00143                                                    Value is result of combination (Or) between gState and RxState values */
00144   HAL_IRDA_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
00145                                                    Value is allowed for gState only */
00146   HAL_IRDA_STATE_ERROR             = 0xE0U     /*!< Error
00147                                                    Value is allowed for gState only */
00148 }HAL_IRDA_StateTypeDef;
00149
00150 /**
00151   * @brief IRDA handle Structure definition
00152   */
00153 typedef struct
00154 {
00155   USART_TypeDef               *Instance;        /* USART registers base address       */
00156
00157   IRDA_InitTypeDef            Init;             /* IRDA communication parameters      */
00158
00159   uint8_t                     *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */
00160
00161   uint16_t                    TxXferSize;       /* IRDA Tx Transfer size              */
00162
00163   uint16_t                    TxXferCount;      /* IRDA Tx Transfer Counter           */
00164
00165   uint8_t                     *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */
00166
00167   uint16_t                    RxXferSize;       /* IRDA Rx Transfer size              */
00168
00169   uint16_t                    RxXferCount;      /* IRDA Rx Transfer Counter           */
00170
00171   DMA_HandleTypeDef           *hdmatx;          /* IRDA Tx DMA Handle parameters      */
00172
00173   DMA_HandleTypeDef           *hdmarx;          /* IRDA Rx DMA Handle parameters      */
00174
00175   HAL_LockTypeDef             Lock;             /* Locking object                     */
00176
00177   __IO HAL_IRDA_StateTypeDef  gState;           /* IRDA state information related to global Handle management
00178                                                    and also related to Tx operations.
00179                                                    This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00180
00181   __IO HAL_IRDA_StateTypeDef  RxState;          /* IRDA state information related to Rx operations.
00182                                                    This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00183
00184   __IO uint32_t               ErrorCode;        /* IRDA Error code                    */
00185
00186 }IRDA_HandleTypeDef;
00187 /**
00188   * @}
00189   */
00190
00191 /* Exported constants --------------------------------------------------------*/
00192 /** @defgroup IRDA_Exported_Constants IRDA Exported constants
00193   * @{
00194   */
00195 /** @defgroup IRDA_Error_Code IRDA Error Code
00196   * @brief    IRDA Error Code
00197   * @{
00198   */
00199 #define HAL_IRDA_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
00200 #define HAL_IRDA_ERROR_PE           ((uint32_t)0x00000001U)   /*!< Parity error        */
00201 #define HAL_IRDA_ERROR_NE           ((uint32_t)0x00000002U)   /*!< Noise error         */
00202 #define HAL_IRDA_ERROR_FE           ((uint32_t)0x00000004U)   /*!< Frame error         */
00203 #define HAL_IRDA_ERROR_ORE          ((uint32_t)0x00000008U)   /*!< Overrun error       */
00204 #define HAL_IRDA_ERROR_DMA          ((uint32_t)0x00000010U)   /*!< DMA transfer error  */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup IRDA_Word_Length IRDA Word Length
00210   * @{
00211   */
00212 #define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000U)
00213 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup IRDA_Parity  IRDA Parity
00219   * @{
00220   */
00221 #define IRDA_PARITY_NONE                    ((uint32_t)0x00000000U)
00222 #define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00223 #define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup IRDA_Mode IRDA Transfer Mode
00229   * @{
00230   */
00231 #define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
00232 #define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
00233 #define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup IRDA_Low_Power IRDA Low Power
00239   * @{
00240   */
00241 #define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)
00242 #define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x00000000U)
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup IRDA_Flags IRDA Flags
00248   *        Elements values convention: 0xXXXX
00249   *           - 0xXXXX  : Flag mask in the SR register
00250   * @{
00251   */
00252 #define IRDA_FLAG_TXE                       ((uint32_t)0x00000080U)
00253 #define IRDA_FLAG_TC                        ((uint32_t)0x00000040U)
00254 #define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020U)
00255 #define IRDA_FLAG_IDLE                      ((uint32_t)0x00000010U)
00256 #define IRDA_FLAG_ORE                       ((uint32_t)0x00000008U)
00257 #define IRDA_FLAG_NE                        ((uint32_t)0x00000004U)
00258 #define IRDA_FLAG_FE                        ((uint32_t)0x00000002U)
00259 #define IRDA_FLAG_PE                        ((uint32_t)0x00000001U)
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
00265   *        Elements values convention: 0xY000XXXX
00266   *           - XXXX  : Interrupt mask in the XX register
00267   *           - Y  : Interrupt source register (2bits)
00268   *                 - 01: CR1 register
00269   *                 - 10: CR2 register
00270   *                 - 11: CR3 register
00271   * @{
00272   */
00273 #define IRDA_IT_PE                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00274 #define IRDA_IT_TXE                         ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00275 #define IRDA_IT_TC                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00276 #define IRDA_IT_RXNE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00277 #define IRDA_IT_IDLE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00278
00279 #define IRDA_IT_LBD                         ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
00280
00281 #define IRDA_IT_CTS                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
00282 #define IRDA_IT_ERR                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00283 /**
00284   * @}
00285   */
00286
00287 /**
00288   * @}
00289   */
00290
00291 /* Exported macro ------------------------------------------------------------*/
00292 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00293   * @{
00294   */
00295
00296 /** @brief Reset IRDA handle gstate & RxState
00297   * @param  __HANDLE__: specifies the USART Handle.
00298   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00299   *         UART peripheral.
00300   * @retval None
00301   */
00302 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00303                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00304                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00305                                                      } while(0)
00306
00307 /** @brief  Flushs the IRDA DR register
00308   * @param  __HANDLE__: specifies the USART Handle.
00309   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00310   *         UART peripheral.
00311   */
00312 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
00313
00314 /** @brief  Checks whether the specified IRDA flag is set or not.
00315   * @param  __HANDLE__: specifies the USART Handle.
00316   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00317   *         UART peripheral.
00318   * @param  __FLAG__: specifies the flag to check.
00319   *        This parameter can be one of the following values:
00320   *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
00321   *            @arg IRDA_FLAG_TC:   Transmission Complete flag
00322   *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag
00323   *            @arg IRDA_FLAG_IDLE: Idle Line detection flag
00324   *            @arg IRDA_FLAG_ORE:  OverRun Error flag
00325   *            @arg IRDA_FLAG_NE:   Noise Error flag
00326   *            @arg IRDA_FLAG_FE:   Framing Error flag
00327   *            @arg IRDA_FLAG_PE:   Parity Error flag
00328   * @retval The new state of __FLAG__ (TRUE or FALSE).
00329   */
00330 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00331
00332 /** @brief  Clears the specified IRDA pending flag.
00333   * @param  __HANDLE__: specifies the USART Handle.
00334   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00335   *         UART peripheral.
00336   * @param  __FLAG__: specifies the flag to check.
00337   *          This parameter can be any combination of the following values:
00338   *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
00339   *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
00340   *
00341   * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
00342   *          error) and IDLE (Idle line detected) flags are cleared by software
00343   *          sequence: a read operation to USART_SR register followed by a read
00344   *          operation to USART_DR register.
00345   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00346   * @note   TC flag can be also cleared by software sequence: a read operation to
00347   *          USART_SR register followed by a write operation to USART_DR register.
00348   * @note   TXE flag is cleared only by a write to the USART_DR register.
00349   *
00350   * @retval None
00351   */
00352 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00353
00354 /** @brief  Clear the IRDA PE pending flag.
00355   * @param  __HANDLE__: specifies the USART Handle.
00356   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00357   *         UART peripheral.
00358   * @retval None
00359   */
00360 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)     \
00361   do{                                           \
00362     __IO uint32_t tmpreg = 0x00U;               \
00363     tmpreg = (__HANDLE__)->Instance->SR;        \
00364     UNUSED(tmpreg);                             \
00365   } while(0)
00366
00367 /** @brief  Clear the IRDA FE pending flag.
00368   * @param  __HANDLE__: specifies the USART Handle.
00369   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00370   *         UART peripheral.
00371   * @retval None
00372   */
00373 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00374
00375 /** @brief  Clear the IRDA NE pending flag.
00376   * @param  __HANDLE__: specifies the USART Handle.
00377   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00378   *         UART peripheral.
00379   * @retval None
00380   */
00381 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00382
00383 /** @brief  Clear the IRDA ORE pending flag.
00384   * @param  __HANDLE__: specifies the USART Handle.
00385   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00386   *         UART peripheral.
00387   * @retval None
00388   */
00389 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00390
00391 /** @brief  Clear the IRDA IDLE pending flag.
00392   * @param  __HANDLE__: specifies the USART Handle.
00393   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00394   *         UART peripheral.
00395   * @retval None
00396   */
00397 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00398
00399 /** @brief  Enables or disables the specified IRDA interrupt.
00400   * @param  __HANDLE__: specifies the USART Handle.
00401   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00402   *         UART peripheral.
00403   * @param  __INTERRUPT__: specifies the IRDA interrupt source to check.
00404   *          This parameter can be one of the following values:
00405   *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
00406   *            @arg IRDA_IT_TC:   Transmission complete interrupt
00407   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00408   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00409   *            @arg IRDA_IT_PE:   Parity Error interrupt
00410   *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00411   * @retval None
00412   */
00413 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
00414                                                            (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
00415                                                         ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
00416 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
00417                                                            (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
00418                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
00419
00420 /** @brief  Checks whether the specified IRDA interrupt has occurred or not.
00421   * @param  __HANDLE__: specifies the USART Handle.
00422   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00423   *         UART peripheral.
00424   * @param  __IT__: specifies the IRDA interrupt source to check.
00425   *          This parameter can be one of the following values:
00426   *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
00427   *            @arg IRDA_IT_TC:  Transmission complete interrupt
00428   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00429   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00430   *            @arg USART_IT_ERR: Error interrupt
00431   *            @arg IRDA_IT_PE: Parity Error interrupt
00432   * @retval The new state of __IT__ (TRUE or FALSE).
00433   */
00434 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
00435                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
00436
00437 /** @brief  Macro to enable the IRDA's one bit sample method
00438   * @param  __HANDLE__: specifies the IRDA Handle.
00439   * @retval None
00440   */
00441 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00442
00443 /** @brief  Macro to disable the IRDA's one bit sample method
00444   * @param  __HANDLE__: specifies the IRDA Handle.
00445   * @retval None
00446   */
00447 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
00448
00449 /** @brief  Enable UART/USART associated to IRDA Handle
00450   * @param  __HANDLE__: specifies the IRDA Handle.
00451   *         IRDA Handle selects the USARTx or UARTy peripheral
00452   *         (USART,UART availability and x,y values depending on device).
00453   * @retval None
00454   */
00455 #define __HAL_IRDA_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00456
00457 /** @brief  Disable UART/USART associated to IRDA Handle
00458   * @param  __HANDLE__: specifies the IRDA Handle.
00459   *         IRDA Handle selects the USARTx or UARTy peripheral
00460   *         (USART,UART availability and x,y values depending on device).
00461   * @retval None
00462   */
00463 #define __HAL_IRDA_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00464
00465 /**
00466   * @}
00467   */
00468
00469 /* Exported functions --------------------------------------------------------*/
00470 /** @addtogroup IRDA_Exported_Functions
00471   * @{
00472   */
00473
00474 /** @addtogroup IRDA_Exported_Functions_Group1
00475   * @{
00476   */
00477 /* Initialization/de-initialization functions  **********************************/
00478 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00479 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00480 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00481 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00482 /**
00483   * @}
00484   */
00485
00486 /** @addtogroup IRDA_Exported_Functions_Group2
00487   * @{
00488   */
00489 /* IO operation functions *******************************************************/
00490 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00491 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00492 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00493 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00494 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00495 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00496 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00497 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00498 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00499 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00500 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00501 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00502 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00503 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00504 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00505 /**
00506   * @}
00507   */
00508
00509 /** @addtogroup IRDA_Exported_Functions_Group3
00510   * @{
00511   */
00512 /* Peripheral State functions  **************************************************/
00513 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00514 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00515 /**
00516   * @}
00517   */
00518
00519 /**
00520   * @}
00521   */
00522
00523 /* Private types -------------------------------------------------------------*/
00524 /* Private variables ---------------------------------------------------------*/
00525 /* Private constants ---------------------------------------------------------*/
00526 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00527   * @{
00528   */
00529
00530 /** @brief IRDA interruptions flag mask
00531   *
00532   */
00533 #define IRDA_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
00534                                   USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
00535
00536 #define IRDA_CR1_REG_INDEX                  1U
00537 #define IRDA_CR2_REG_INDEX                  2U
00538 #define IRDA_CR3_REG_INDEX                  3U
00539 /**
00540   * @}
00541   */
00542
00543 /* Private macros --------------------------------------------------------*/
00544 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
00545   * @{
00546   */
00547 #define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
00548                                      ((LENGTH) == IRDA_WORDLENGTH_9B))
00549 #define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
00550                                 ((PARITY) == IRDA_PARITY_EVEN) || \
00551                                 ((PARITY) == IRDA_PARITY_ODD))
00552 #define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00000000U))
00553 #define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
00554                                  ((MODE) == IRDA_POWERMODE_NORMAL))
00555 #define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
00556
00557 #define IRDA_DIV(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
00558 #define IRDA_DIVMANT(_PCLK_, _BAUD_)        (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
00559 #define IRDA_DIVFRAQ(_PCLK_, _BAUD_)        (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00560 /* UART BRR = mantissa + overflow + fraction
00561             = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
00562 #define IRDA_BRR(_PCLK_, _BAUD_)            (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
00563                                              (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
00564                                              (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
00565
00566 /**
00567   * @}
00568   */
00569
00570 /* Private functions ---------------------------------------------------------*/
00571 /** @defgroup IRDA_Private_Functions IRDA Private Functions
00572   * @{
00573   */
00574
00575 /**
00576   * @}
00577   */
00578
00579 /**
00580   * @}
00581   */
00582
00583 /**
00584   * @}
00585   */
00586
00587 #ifdef __cplusplus
00588 }
00589 #endif
00590
00591 #endif /* __STM32F4xx_HAL_IRDA_H */
00592
00593 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_iwdg.c Source File

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stm32f4xx_hal_iwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   IWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00010   *           + Initialization and Configuration functions
00011   *           + IO operation functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                     ##### IWDG Specific features #####
00017   ==============================================================================
00018     [..]
00019     (+) The IWDG can be started by either software or hardware (configurable
00020          through option byte).
00021
00022     (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
00023          thus stays active even if the main clock fails.
00024          Once the IWDG is started, the LSI is forced ON and cannot be disabled
00025          (LSI cannot be disabled too), and the counter starts counting down from
00026          the reset value of 0xFFF. When it reaches the end of count value (0x000)
00027          a system reset is generated.
00028
00029     (+) The IWDG counter should be refreshed at regular intervals, otherwise the
00030          watchdog generates an MCU reset when the counter reaches 0.
00031
00032     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00033          in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00034          IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00035          reset occurs.
00036
00037     (+) Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00038          The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
00039          devices provide the capability to measure the LSI frequency (LSI clock
00040          connected internally to TIM5 CH4 input capture). The measured value
00041          can be used to have an IWDG timeout with an acceptable accuracy.
00042
00043
00044                      ##### How to use this driver #####
00045   ==============================================================================
00046     [..]
00047     If Window option is disabled
00048       (+) Use IWDG using HAL_IWDG_Init() function to :
00049          (++) Enable write access to IWDG_PR, IWDG_RLR.
00050          (++) Configure the IWDG prescaler, counter reload value.
00051               This reload value will be loaded in the IWDG counter each time the counter
00052               is reloaded, then the IWDG will start counting down from this value.
00053     [..]
00054       (+) Use IWDG using HAL_IWDG_Start() function to:
00055           (++) Reload IWDG counter with value defined in the IWDG_RLR register.
00056           (++) Start the IWDG, when the IWDG is used in software mode (no need
00057                to enable the LSI, it will be enabled by hardware).
00058       (+) Then the application program must refresh the IWDG counter at regular
00059           intervals during normal operation to prevent an MCU reset, using
00060           HAL_IWDG_Refresh() function.
00061     [..]
00062     if Window option is enabled:
00063
00064       (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
00065       (+) Use IWDG using HAL_IWDG_Init() function to :
00066          (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00067          (++) Configure the IWDG prescaler, reload value and window value.
00068       (+) Then the application program must refresh the IWDG counter at regular
00069           intervals during normal operation to prevent an MCU reset, using
00070           HAL_IWDG_Refresh() function.
00071
00072      *** IWDG HAL driver macros list ***
00073      ====================================
00074      [..]
00075        Below the list of most used macros in IWDG HAL driver.
00076
00077       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00078       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
00079       (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
00080
00081   @endverbatim
00082   ******************************************************************************
00083   * @attention
00084   *
00085   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00086   *
00087   * Redistribution and use in source and binary forms, with or without modification,
00088   * are permitted provided that the following conditions are met:
00089   *   1. Redistributions of source code must retain the above copyright notice,
00090   *      this list of conditions and the following disclaimer.
00091   *   2. Redistributions in binary form must reproduce the above copyright notice,
00092   *      this list of conditions and the following disclaimer in the documentation
00093   *      and/or other materials provided with the distribution.
00094   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00095   *      may be used to endorse or promote products derived from this software
00096   *      without specific prior written permission.
00097   *
00098   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00099   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00100   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00101   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00102   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00103   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00104   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00105   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00106   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00107   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00108   *
00109   ******************************************************************************
00110   */
00111
00112 /* Includes ------------------------------------------------------------------*/
00113 #include "stm32f4xx_hal.h"
00114
00115 /** @addtogroup STM32F4xx_HAL_Driver
00116   * @{
00117   */
00118
00119 /** @defgroup IWDG IWDG
00120   * @brief IWDG HAL module driver.
00121   * @{
00122   */
00123
00124 #ifdef HAL_IWDG_MODULE_ENABLED
00125
00126 /* Private typedef -----------------------------------------------------------*/
00127 /* Private define ------------------------------------------------------------*/
00128  /** @addtogroup IWDG_Private_Constants
00129   * @{
00130   */
00131 #define IWDG_TIMEOUT_FLAG          ((uint32_t)1000U)     /* 1 s */
00132 /**
00133   * @}
00134   */
00135 /* Private macro -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private function prototypes -----------------------------------------------*/
00138 /* Private functions ---------------------------------------------------------*/
00139 /* Exported functions --------------------------------------------------------*/
00140 /** @defgroup IWDG_Exported_Functions IWDG Exported Functions
00141   * @{
00142   */
00143
00144 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
00145  *  @brief    Initialization and Configuration functions.
00146  *
00147 @verbatim
00148  ===============================================================================
00149           ##### Initialization and de-initialization functions #####
00150  ===============================================================================
00151     [..]  This section provides functions allowing to:
00152       (+) Initialize the IWDG according to the specified parameters
00153           in the IWDG_InitTypeDef and create the associated handle
00154       (+) Initialize the IWDG MSP
00155       (+) DeInitialize IWDG MSP
00156
00157 @endverbatim
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Initializes the IWDG according to the specified
00163   *         parameters in the IWDG_InitTypeDef and creates the associated handle.
00164   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00165   *                the configuration information for the specified IWDG module.
00166   * @retval HAL status
00167   */
00168 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00169 {
00170   /* Check the IWDG handle allocation */
00171   if(hiwdg == NULL)
00172   {
00173     return HAL_ERROR;
00174   }
00175
00176   /* Check the parameters */
00177   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00178   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00179   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00180
00181   if(hiwdg->State == HAL_IWDG_STATE_RESET)
00182   {
00183     /* Allocate lock resource and initialize it */
00184     hiwdg->Lock = HAL_UNLOCKED;
00185     /* Init the low level hardware */
00186     HAL_IWDG_MspInit(hiwdg);
00187   }
00188
00189   /* Change IWDG peripheral state */
00190   hiwdg->State = HAL_IWDG_STATE_BUSY;
00191
00192   /* Enable write access to IWDG_PR and IWDG_RLR registers */
00193   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00194
00195   /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
00196   MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
00197   MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
00198
00199   /* Change IWDG peripheral state */
00200   hiwdg->State = HAL_IWDG_STATE_READY;
00201
00202   /* Return function status */
00203   return HAL_OK;
00204 }
00205
00206 /**
00207   * @brief  Initializes the IWDG MSP.
00208   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00209   *                the configuration information for the specified IWDG module.
00210   * @retval None
00211   */
00212 __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
00213 {
00214   /* Prevent unused argument(s) compilation warning */
00215   UNUSED(hiwdg);
00216   /* NOTE : This function Should not be modified, when the callback is needed,
00217             the HAL_IWDG_MspInit could be implemented in the user file
00218    */
00219 }
00220
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00226  *  @brief   IO operation functions
00227  *
00228 @verbatim
00229  ===============================================================================
00230                       ##### IO operation functions #####
00231  ===============================================================================
00232     [..]  This section provides functions allowing to:
00233       (+) Start the IWDG.
00234       (+) Refresh the IWDG.
00235
00236 @endverbatim
00237   * @{
00238   */
00239
00240 /**
00241   * @brief  Starts the IWDG.
00242   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00243   *                the configuration information for the specified IWDG module.
00244   * @retval HAL status
00245   */
00246 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
00247 {
00248   /* Process Locked */
00249   __HAL_LOCK(hiwdg);
00250
00251     /* Change IWDG peripheral state */
00252   hiwdg->State = HAL_IWDG_STATE_BUSY;
00253
00254   /* Start the IWDG peripheral */
00255   __HAL_IWDG_START(hiwdg);
00256
00257     /* Reload IWDG counter with value defined in the RLR register */
00258   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00259
00260   /* Change IWDG peripheral state */
00261   hiwdg->State = HAL_IWDG_STATE_READY;
00262
00263   /* Process Unlocked */
00264   __HAL_UNLOCK(hiwdg);
00265
00266   /* Return function status */
00267   return HAL_OK;
00268 }
00269
00270 /**
00271   * @brief  Refreshes the IWDG.
00272   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00273   *                the configuration information for the specified IWDG module.
00274   * @retval HAL status
00275   */
00276 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00277 {
00278   uint32_t tickstart = 0U;
00279
00280   /* Process Locked */
00281   __HAL_LOCK(hiwdg);
00282
00283     /* Change IWDG peripheral state */
00284   hiwdg->State = HAL_IWDG_STATE_BUSY;
00285
00286   tickstart = HAL_GetTick();
00287
00288   /* Wait until RVU flag is RESET */
00289   while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
00290   {
00291     if((HAL_GetTick() - tickstart ) > IWDG_TIMEOUT_FLAG)
00292     {
00293       /* Set IWDG state */
00294       hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
00295
00296        /* Process unlocked */
00297       __HAL_UNLOCK(hiwdg);
00298
00299       return HAL_TIMEOUT;
00300     }
00301   }
00302
00303   /* Reload IWDG counter with value defined in the reload register */
00304   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00305
00306   /* Change IWDG peripheral state */
00307   hiwdg->State = HAL_IWDG_STATE_READY;
00308
00309   /* Process Unlocked */
00310   __HAL_UNLOCK(hiwdg);
00311
00312   /* Return function status */
00313   return HAL_OK;
00314 }
00315
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
00321  *  @brief    Peripheral State functions.
00322  *
00323 @verbatim
00324  ===============================================================================
00325                       ##### Peripheral State functions #####
00326  ===============================================================================
00327     [..]
00328     This subsection permits to get in run-time the status of the peripheral
00329     and the data flow.
00330
00331 @endverbatim
00332   * @{
00333   */
00334
00335 /**
00336   * @brief  Returns the IWDG state.
00337   * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
00338   *                the configuration information for the specified IWDG module.
00339   * @retval HAL state
00340   */
00341 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
00342 {
00343   return hiwdg->State;
00344 }
00345
00346 /**
00347   * @}
00348   */
00349
00350 /**
00351   * @}
00352   */
00353
00354 #endif /* HAL_IWDG_MODULE_ENABLED */
00355 /**
00356   * @}
00357   */
00358
00359 /**
00360   * @}
00361   */
00362
00363 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_iwdg.h Source File

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stm32f4xx_hal_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of IWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_IWDG_H
00040 #define __STM32F4xx_HAL_IWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  IWDG HAL State Structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_IWDG_STATE_RESET     = 0x00U,  /*!< IWDG not yet initialized or disabled */
00068   HAL_IWDG_STATE_READY     = 0x01U,  /*!< IWDG initialized and ready for use   */
00069   HAL_IWDG_STATE_BUSY      = 0x02U,  /*!< IWDG internal process is ongoing     */
00070   HAL_IWDG_STATE_TIMEOUT   = 0x03U,  /*!< IWDG timeout state                   */
00071   HAL_IWDG_STATE_ERROR     = 0x04U   /*!< IWDG error state                     */
00072 }HAL_IWDG_StateTypeDef;
00073
00074 /**
00075   * @brief  IWDG Init structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00080                             This parameter can be a value of @ref IWDG_Prescaler */
00081
00082   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00083                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
00084 }IWDG_InitTypeDef;
00085
00086 /**
00087   * @brief  IWDG Handle Structure definition
00088   */
00089 typedef struct
00090 {
00091   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00092
00093   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00094
00095   HAL_LockTypeDef              Lock;       /*!< IWDG Locking object      */
00096
00097   __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
00098 }IWDG_HandleTypeDef;
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00106   * @{
00107   */
00108
00109 /** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
00110   * @brief IWDG registers bit mask
00111   * @{
00112   */
00113 /* --- KR Register ---*/
00114 /* KR register bit mask */
00115 #define IWDG_KEY_RELOAD                            ((uint32_t)0xAAAAU)  /*!< IWDG Reload Counter Enable   */
00116 #define IWDG_KEY_ENABLE                            ((uint32_t)0xCCCCU)  /*!< IWDG Peripheral Enable       */
00117 #define IWDG_KEY_WRITE_ACCESS_ENABLE               ((uint32_t)0x5555U)  /*!< IWDG KR Write Access Enable  */
00118 #define IWDG_KEY_WRITE_ACCESS_DISABLE              ((uint32_t)0x0000U)  /*!< IWDG KR Write Access Disable */
00119 /**
00120   * @}
00121   */
00122
00123 /** @defgroup IWDG_Flag_definition IWDG Flag definition
00124   * @{
00125   */
00126 #define IWDG_FLAG_PVU   ((uint32_t)IWDG_SR_PVU)  /*!< Watchdog counter prescaler value update Flag */
00127 #define IWDG_FLAG_RVU   ((uint32_t)IWDG_SR_RVU)  /*!< Watchdog counter reload value update Flag    */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup IWDG_Prescaler IWDG Prescaler
00133   * @{
00134   */
00135 #define IWDG_PRESCALER_4     ((uint8_t)0x00U)  /*!< IWDG prescaler set to 4   */
00136 #define IWDG_PRESCALER_8     ((uint8_t)(IWDG_PR_PR_0))                  /*!< IWDG prescaler set to 8   */
00137 #define IWDG_PRESCALER_16    ((uint8_t)(IWDG_PR_PR_1))                  /*!< IWDG prescaler set to 16  */
00138 #define IWDG_PRESCALER_32    ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 32  */
00139 #define IWDG_PRESCALER_64    ((uint8_t)(IWDG_PR_PR_2))                  /*!< IWDG prescaler set to 64  */
00140 #define IWDG_PRESCALER_128   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 128 */
00141 #define IWDG_PRESCALER_256   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))   /*!< IWDG prescaler set to 256 */
00142 /**
00143   * @}
00144   */
00145
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported macros -----------------------------------------------------------*/
00151 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00152   * @{
00153   */
00154
00155 /** @brief Reset IWDG handle state
00156   * @param  __HANDLE__: IWDG handle.
00157   * @retval None
00158   */
00159 #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
00160
00161 /**
00162   * @brief  Enables the IWDG peripheral.
00163   * @param  __HANDLE__: IWDG handle
00164   * @retval None
00165   */
00166 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00167
00168 /**
00169   * @brief  Reloads IWDG counter with value defined in the reload register
00170   *         (write access to IWDG_PR and IWDG_RLR registers disabled).
00171   * @param  __HANDLE__: IWDG handle
00172   * @retval None
00173   */
00174 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00175
00176 /**
00177   * @brief  Gets the selected IWDG's flag status.
00178   * @param  __HANDLE__: IWDG handle
00179   * @param  __FLAG__: specifies the flag to check.
00180   *         This parameter can be one of the following values:
00181   *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
00182   *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
00183   * @retval The new state of __FLAG__ (TRUE or FALSE).
00184   */
00185 #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00186
00187 /**
00188   * @}
00189   */
00190
00191 /* Exported functions --------------------------------------------------------*/
00192 /** @addtogroup IWDG_Exported_Functions
00193   * @{
00194   */
00195
00196 /** @addtogroup IWDG_Exported_Functions_Group1
00197   * @{
00198   */
00199 /* Initialization/de-initialization functions  ********************************/
00200 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00201 void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
00202 /**
00203   * @}
00204   */
00205
00206 /** @addtogroup IWDG_Exported_Functions_Group2
00207   * @{
00208   */
00209 /* I/O operation functions ****************************************************/
00210 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
00211 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00212 /**
00213   * @}
00214   */
00215
00216 /** @addtogroup IWDG_Exported_Functions_Group3
00217   * @{
00218   */
00219 /* Peripheral State functions  ************************************************/
00220 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
00221
00222 /**
00223   * @}
00224   */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /* Private macro -------------------------------------------------------------*/
00231 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  Enables write access to IWDG_PR and IWDG_RLR registers.
00237   * @param  __HANDLE__: IWDG handle
00238   * @retval None
00239   */
00240 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00241
00242 /**
00243   * @brief  Disables write access to IWDG_PR and IWDG_RLR registers.
00244   * @param  __HANDLE__: IWDG handle
00245   * @retval None
00246   */
00247 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00248
00249
00250 #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00251                                           ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00252                                           ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00253                                           ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00254                                           ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00255                                           ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00256                                           ((__PRESCALER__) == IWDG_PRESCALER_256))
00257
00258
00259 #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU)
00260
00261 /**
00262   * @}
00263   */
00264
00265 /* Private define ------------------------------------------------------------*/
00266  /** @defgroup IWDG_Private_Constants IWDG Private Constants
00267   * @{
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 #ifdef __cplusplus
00283 }
00284 #endif
00285
00286 #endif /* __STM32F4xx_HAL_IWDG_H */
00287
00288 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_lptim.c Source File

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stm32f4xx_hal_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   LPTIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00010   *           + Initialization and de-initialization functions.
00011   *           + Start/Stop operation functions in polling mode.
00012   *           + Start/Stop operation functions in interrupt mode.
00013   *           + Reading operation functions.
00014   *           + Peripheral State functions.
00015   *
00016   @verbatim
00017   ==============================================================================
00018                      ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021       The LPTIM HAL driver can be used as follows:
00022
00023       (#)Initialize the LPTIM low level resources by implementing the
00024         HAL_LPTIM_MspInit():
00025          (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
00026          (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00027              (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00028              (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00029              (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00030
00031       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00032          configures mainly:
00033          (##) The instance: LPTIM1.
00034          (##) Clock: the counter clock.
00035              (+++) Source   : it can be either the ULPTIM input (IN1) or one of
00036                               the internal clock; (APB, LSE, LSI or MSI).
00037              (+++) Prescaler: select the clock divider.
00038          (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00039                as counter clock source.
00040              (+++) Polarity:   polarity of the active edge for the counter unit
00041                                if the ULPTIM input is selected.
00042              (+++) SampleTime: clock sampling time to configure the clock glitch
00043                                filter.
00044          (##) Trigger: How the counter start.
00045              (+++) Source: trigger can be software or one of the hardware triggers.
00046              (+++) ActiveEdge : only for hardware trigger.
00047              (+++) SampleTime : trigger sampling time to configure the trigger
00048                                 glitch filter.
00049          (##) OutputPolarity : 2 opposite polarities are possibles.
00050          (##) UpdateMode: specifies whether the update of the autoreload and
00051               the compare values is done immediately or after the end of current
00052               period.
00053
00054       (#)Six modes are available:
00055
00056          (##) PWM Mode: To generate a PWM signal with specified period and pulse,
00057          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00058          mode.
00059
00060          (##) One Pulse Mode: To generate pulse with specified width in response
00061          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00062          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00063
00064          (##) Set once Mode: In this mode, the output changes the level (from
00065          low level to high level if the output polarity is configured high, else
00066          the opposite) when a compare match occurs. To start this mode, call
00067          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00068          interruption mode.
00069
00070          (##) Encoder Mode: To use the encoder interface call
00071          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00072          interruption mode.
00073
00074          (##) Time out Mode: an active edge on one selected trigger input rests
00075          the counter. The first trigger event will start the timer, any
00076          successive trigger event will reset the counter and the timer will
00077          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00078          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00079
00080          (##) Counter Mode: counter can be used to count external events on
00081          the LPTIM Input1 or it can be used to count internal clock cycles.
00082          To start this mode, call HAL_LPTIM_Counter_Start() or
00083          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00084
00085       (#) User can stop any process by calling the corresponding API:
00086           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00087           already started in interruption mode.
00088
00089        (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
00090
00091   @endverbatim
00092   ******************************************************************************
00093   * @attention
00094   *
00095   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00096   *
00097   * Redistribution and use in source and binary forms, with or without modification,
00098   * are permitted provided that the following conditions are met:
00099   *   1. Redistributions of source code must retain the above copyright notice,
00100   *      this list of conditions and the following disclaimer.
00101   *   2. Redistributions in binary form must reproduce the above copyright notice,
00102   *      this list of conditions and the following disclaimer in the documentation
00103   *      and/or other materials provided with the distribution.
00104   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00105   *      may be used to endorse or promote products derived from this software
00106   *      without specific prior written permission.
00107   *
00108   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00109   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00110   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00111   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00112   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00113   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00114   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00115   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00116   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00117   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00118   *
00119   ******************************************************************************
00120   */
00121
00122 /* Includes ------------------------------------------------------------------*/
00123 #include "stm32f4xx_hal.h"
00124
00125 /** @addtogroup STM32F4xx_HAL_Driver
00126   * @{
00127   */
00128
00129 /** @defgroup LPTIM LPTIM
00130   * @brief LPTIM HAL module driver.
00131   * @{
00132   */
00133
00134 #ifdef HAL_LPTIM_MODULE_ENABLED
00135 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00136 /* Private types -------------------------------------------------------------*/
00137 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00138   * @{
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /* Private defines -----------------------------------------------------------*/
00146 /** @defgroup LPTIM_Private_Defines LPTIM Private Defines
00147   * @{
00148   */
00149
00150 /**
00151   * @}
00152   */
00153
00154 /* Private variables ---------------------------------------------------------*/
00155 /** @addtogroup LPTIM_Private_Variables LPTIM Private Variables
00156   * @{
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /* Private constants ---------------------------------------------------------*/
00164 /** @addtogroup LPTIM_Private_Constants LPTIM Private Constants
00165   * @{
00166   */
00167
00168 /**
00169   * @}
00170   */
00171
00172 /* Private macros ------------------------------------------------------------*/
00173 /** @addtogroup LPTIM_Private_Macros LPTIM Private Macros
00174   * @{
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /* Private function prototypes -----------------------------------------------*/
00182 /** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes
00183   * @{
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Private functions ---------------------------------------------------------*/
00191 /** @addtogroup LPTIM_Private_Functions LPTIM Private Functions
00192   * @{
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported functions ---------------------------------------------------------*/
00200 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00201   * @{
00202   */
00203
00204 /** @defgroup LPTIM_Group1 Initialization/de-initialization functions
00205  *  @brief    Initialization and Configuration functions.
00206  *
00207 @verbatim
00208   ==============================================================================
00209               ##### Initialization and de-initialization functions #####
00210   ==============================================================================
00211     [..]  This section provides functions allowing to:
00212       (+) Initialize the LPTIM according to the specified parameters in the
00213           LPTIM_InitTypeDef and creates the associated handle.
00214       (+) DeInitialize the LPTIM peripheral.
00215       (+) Initialize the LPTIM MSP.
00216       (+) DeInitialize LPTIM MSP.
00217
00218 @endverbatim
00219   * @{
00220   */
00221
00222 /**
00223   * @brief  Initializes the LPTIM according to the specified parameters in the
00224   *         LPTIM_InitTypeDef and creates the associated handle.
00225   * @param  hlptim: LPTIM handle
00226   * @retval HAL status
00227   */
00228 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00229 {
00230   uint32_t tmpcfgr = 0U;
00231
00232   /* Check the LPTIM handle allocation */
00233   if(hlptim == NULL)
00234   {
00235     return HAL_ERROR;
00236   }
00237
00238   /* Check the parameters */
00239   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00240
00241   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00242   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00243   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00244   {
00245     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00246     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00247   }
00248   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00249   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00250   {
00251     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00252     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00253   }
00254   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00255   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00256   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00257
00258   if(hlptim->State == HAL_LPTIM_STATE_RESET)
00259   {
00260     /* Allocate lock resource and initialize it */
00261     hlptim->Lock = HAL_UNLOCKED;
00262     /* Init the low level hardware */
00263     HAL_LPTIM_MspInit(hlptim);
00264   }
00265
00266   /* Change the LPTIM state */
00267   hlptim->State = HAL_LPTIM_STATE_BUSY;
00268
00269   /* Get the LPTIMx CFGR value */
00270   tmpcfgr = hlptim->Instance->CFGR;
00271
00272   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00273   {
00274     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00275   }
00276   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00277   {
00278     tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00279   }
00280
00281   /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00282   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00283                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
00284
00285   /* Set initialization parameters */
00286   tmpcfgr |= (hlptim->Init.Clock.Source    |
00287               hlptim->Init.Clock.Prescaler |
00288               hlptim->Init.OutputPolarity  |
00289               hlptim->Init.UpdateMode      |
00290               hlptim->Init.CounterSource);
00291
00292   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00293   {
00294     tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |
00295                 hlptim->Init.UltraLowPowerClock.SampleTime);
00296   }
00297
00298   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00299   {
00300     /* Enable External trigger and set the trigger source */
00301     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00302                 hlptim->Init.Trigger.ActiveEdge |
00303                 hlptim->Init.Trigger.SampleTime);
00304   }
00305
00306   /* Write to LPTIMx CFGR */
00307   hlptim->Instance->CFGR = tmpcfgr;
00308
00309   /* Change the LPTIM state */
00310   hlptim->State = HAL_LPTIM_STATE_READY;
00311
00312   /* Return function status */
00313   return HAL_OK;
00314 }
00315
00316 /**
00317   * @brief  DeInitializes the LPTIM peripheral.
00318   * @param  hlptim: LPTIM handle
00319   * @retval HAL status
00320   */
00321 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00322 {
00323   /* Check the LPTIM handle allocation */
00324   if(hlptim == NULL)
00325   {
00326     return HAL_ERROR;
00327   }
00328
00329   /* Change the LPTIM state */
00330   hlptim->State = HAL_LPTIM_STATE_BUSY;
00331
00332   /* Disable the LPTIM Peripheral Clock */
00333   __HAL_LPTIM_DISABLE(hlptim);
00334
00335   /* DeInit the low level hardware: CLOCK, NVIC.*/
00336   HAL_LPTIM_MspDeInit(hlptim);
00337
00338   /* Change the LPTIM state */
00339   hlptim->State = HAL_LPTIM_STATE_RESET;
00340
00341   /* Release Lock */
00342   __HAL_UNLOCK(hlptim);
00343
00344   /* Return function status */
00345   return HAL_OK;
00346 }
00347
00348 /**
00349   * @brief  Initializes the LPTIM MSP.
00350   * @param  hlptim: LPTIM handle
00351   * @retval None
00352   */
00353 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hlptim);
00357   /* NOTE : This function Should not be modified, when the callback is needed,
00358             the HAL_LPTIM_MspInit could be implemented in the user file
00359    */
00360 }
00361
00362 /**
00363   * @brief  DeInitializes LPTIM MSP.
00364   * @param  hlptim: LPTIM handle
00365   * @retval None
00366   */
00367 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00368 {
00369   /* Prevent unused argument(s) compilation warning */
00370   UNUSED(hlptim);
00371   /* NOTE : This function Should not be modified, when the callback is needed,
00372             the HAL_LPTIM_MspDeInit could be implemented in the user file
00373    */
00374 }
00375
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions
00381  *  @brief   Start-Stop operation functions.
00382  *
00383 @verbatim
00384   ==============================================================================
00385                 ##### LPTIM Start Stop operation functions #####
00386   ==============================================================================
00387     [..]  This section provides functions allowing to:
00388       (+) Start the PWM mode.
00389       (+) Stop the PWM mode.
00390       (+) Start the One pulse mode.
00391       (+) Stop the One pulse mode.
00392       (+) Start the Set once mode.
00393       (+) Stop the Set once mode.
00394       (+) Start the Encoder mode.
00395       (+) Stop the Encoder mode.
00396       (+) Start the Timeout mode.
00397       (+) Stop the Timeout mode.
00398       (+) Start the Counter mode.
00399       (+) Stop the Counter mode.
00400
00401
00402 @endverbatim
00403   * @{
00404   */
00405
00406 /**
00407   * @brief  Starts the LPTIM PWM generation.
00408   * @param  hlptim : LPTIM handle
00409   * @param  Period : Specifies the Autoreload value.
00410   *         This parameter must be a value between 0x0000 and 0xFFFF.
00411   * @param  Pulse : Specifies the compare value.
00412   *         This parameter must be a value between 0x0000 and 0xFFFF.
00413   * @retval HAL status
00414   */
00415 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00416 {
00417   /* Check the parameters */
00418   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00419   assert_param(IS_LPTIM_PERIOD(Period));
00420   assert_param(IS_LPTIM_PULSE(Pulse));
00421
00422   /* Set the LPTIM state */
00423   hlptim->State= HAL_LPTIM_STATE_BUSY;
00424
00425   /* Reset WAVE bit to set PWM mode */
00426   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00427
00428   /* Enable the Peripheral */
00429   __HAL_LPTIM_ENABLE(hlptim);
00430
00431   /* Load the period value in the autoreload register */
00432   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00433
00434   /* Load the pulse value in the compare register */
00435   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00436
00437   /* Start timer in continuous mode */
00438   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00439
00440   /* Change the TIM state*/
00441   hlptim->State= HAL_LPTIM_STATE_READY;
00442
00443   /* Return function status */
00444   return HAL_OK;
00445 }
00446
00447 /**
00448   * @brief  Stops the LPTIM PWM generation.
00449   * @param  hlptim : LPTIM handle
00450   * @retval HAL status
00451   */
00452 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00453 {
00454   /* Check the parameters */
00455   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00456
00457   /* Set the LPTIM state */
00458   hlptim->State= HAL_LPTIM_STATE_BUSY;
00459
00460   /* Disable the Peripheral */
00461   __HAL_LPTIM_DISABLE(hlptim);
00462
00463   /* Change the TIM state*/
00464   hlptim->State= HAL_LPTIM_STATE_READY;
00465
00466   /* Return function status */
00467   return HAL_OK;
00468 }
00469
00470 /**
00471   * @brief  Starts the LPTIM PWM generation in interrupt mode.
00472   * @param  hlptim : LPTIM handle
00473   * @param  Period : Specifies the Autoreload value.
00474   *         This parameter must be a value between 0x0000 and 0xFFFF
00475   * @param  Pulse : Specifies the compare value.
00476   *         This parameter must be a value between 0x0000 and 0xFFFF
00477   * @retval HAL status
00478   */
00479 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00480 {
00481   /* Check the parameters */
00482   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00483   assert_param(IS_LPTIM_PERIOD(Period));
00484   assert_param(IS_LPTIM_PULSE(Pulse));
00485
00486   /* Set the LPTIM state */
00487   hlptim->State= HAL_LPTIM_STATE_BUSY;
00488
00489   /* Reset WAVE bit to set PWM mode */
00490   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00491
00492   /* Enable Autoreload write complete interrupt */
00493   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00494
00495   /* Enable Compare write complete interrupt */
00496   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00497
00498   /* Enable Autoreload match interrupt */
00499   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00500
00501   /* Enable Compare match interrupt */
00502   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00503
00504   /* If external trigger source is used, then enable external trigger interrupt */
00505   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00506   {
00507     /* Enable external trigger interrupt */
00508     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00509   }
00510
00511   /* Enable the Peripheral */
00512   __HAL_LPTIM_ENABLE(hlptim);
00513
00514   /* Load the period value in the autoreload register */
00515   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00516
00517   /* Load the pulse value in the compare register */
00518   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00519
00520   /* Start timer in continuous mode */
00521   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00522
00523   /* Change the TIM state*/
00524   hlptim->State= HAL_LPTIM_STATE_READY;
00525
00526   /* Return function status */
00527   return HAL_OK;
00528 }
00529
00530 /**
00531   * @brief  Stops the LPTIM PWM generation in interrupt mode.
00532   * @param  hlptim : LPTIM handle
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00536 {
00537   /* Check the parameters */
00538   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00539
00540   /* Set the LPTIM state */
00541   hlptim->State= HAL_LPTIM_STATE_BUSY;
00542
00543   /* Disable the Peripheral */
00544   __HAL_LPTIM_DISABLE(hlptim);
00545
00546     /* Disable Autoreload write complete interrupt */
00547   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00548
00549   /* Disable Compare write complete interrupt */
00550   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00551
00552   /* Disable Autoreload match interrupt */
00553   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00554
00555   /* Disable Compare match interrupt */
00556   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00557
00558   /* If external trigger source is used, then disable external trigger interrupt */
00559   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00560   {
00561     /* Disable external trigger interrupt */
00562     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00563   }
00564
00565   /* Change the TIM state*/
00566   hlptim->State= HAL_LPTIM_STATE_READY;
00567
00568   /* Return function status */
00569   return HAL_OK;
00570 }
00571
00572 /**
00573   * @brief  Starts the LPTIM One pulse generation.
00574   * @param  hlptim : LPTIM handle
00575   * @param  Period : Specifies the Autoreload value.
00576   *         This parameter must be a value between 0x0000 and 0xFFFF.
00577   * @param  Pulse : Specifies the compare value.
00578   *         This parameter must be a value between 0x0000 and 0xFFFF.
00579   * @retval HAL status
00580   */
00581 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00582 {
00583   /* Check the parameters */
00584   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00585   assert_param(IS_LPTIM_PERIOD(Period));
00586   assert_param(IS_LPTIM_PULSE(Pulse));
00587
00588   /* Set the LPTIM state */
00589   hlptim->State= HAL_LPTIM_STATE_BUSY;
00590
00591   /* Reset WAVE bit to set one pulse mode */
00592   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00593
00594   /* Enable the Peripheral */
00595   __HAL_LPTIM_ENABLE(hlptim);
00596
00597   /* Load the period value in the autoreload register */
00598   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00599
00600   /* Load the pulse value in the compare register */
00601   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00602
00603   /* Start timer in continuous mode */
00604   __HAL_LPTIM_START_SINGLE(hlptim);
00605
00606   /* Change the TIM state*/
00607   hlptim->State= HAL_LPTIM_STATE_READY;
00608
00609   /* Return function status */
00610   return HAL_OK;
00611 }
00612
00613 /**
00614   * @brief  Stops the LPTIM One pulse generation.
00615   * @param  hlptim : LPTIM handle
00616   * @retval HAL status
00617   */
00618 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00619 {
00620   /* Check the parameters */
00621   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00622
00623   /* Set the LPTIM state */
00624   hlptim->State= HAL_LPTIM_STATE_BUSY;
00625
00626   /* Disable the Peripheral */
00627   __HAL_LPTIM_DISABLE(hlptim);
00628
00629   /* Change the TIM state*/
00630   hlptim->State= HAL_LPTIM_STATE_READY;
00631
00632   /* Return function status */
00633   return HAL_OK;
00634 }
00635
00636 /**
00637   * @brief  Starts the LPTIM One pulse generation in interrupt mode.
00638   * @param  hlptim : LPTIM handle
00639   * @param  Period : Specifies the Autoreload value.
00640   *         This parameter must be a value between 0x0000 and 0xFFFF.
00641   * @param  Pulse : Specifies the compare value.
00642   *         This parameter must be a value between 0x0000 and 0xFFFF.
00643   * @retval HAL status
00644   */
00645 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00646 {
00647   /* Check the parameters */
00648   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00649   assert_param(IS_LPTIM_PERIOD(Period));
00650   assert_param(IS_LPTIM_PULSE(Pulse));
00651
00652   /* Set the LPTIM state */
00653   hlptim->State= HAL_LPTIM_STATE_BUSY;
00654
00655   /* Reset WAVE bit to set one pulse mode */
00656   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00657
00658   /* Enable Autoreload write complete interrupt */
00659   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00660
00661   /* Enable Compare write complete interrupt */
00662   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00663
00664   /* Enable Autoreload match interrupt */
00665   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00666
00667   /* Enable Compare match interrupt */
00668   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00669
00670   /* If external trigger source is used, then enable external trigger interrupt */
00671   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00672   {
00673     /* Enable external trigger interrupt */
00674     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00675   }
00676
00677   /* Enable the Peripheral */
00678   __HAL_LPTIM_ENABLE(hlptim);
00679
00680   /* Load the period value in the autoreload register */
00681   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00682
00683   /* Load the pulse value in the compare register */
00684   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00685
00686   /* Start timer in continuous mode */
00687   __HAL_LPTIM_START_SINGLE(hlptim);
00688
00689   /* Change the TIM state*/
00690   hlptim->State= HAL_LPTIM_STATE_READY;
00691
00692   /* Return function status */
00693   return HAL_OK;
00694 }
00695
00696 /**
00697   * @brief  Stops the LPTIM One pulse generation in interrupt mode.
00698   * @param  hlptim : LPTIM handle
00699   * @retval HAL status
00700   */
00701 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00702 {
00703   /* Check the parameters */
00704   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00705
00706   /* Set the LPTIM state */
00707   hlptim->State= HAL_LPTIM_STATE_BUSY;
00708
00709   /* Disable the Peripheral */
00710   __HAL_LPTIM_DISABLE(hlptim);
00711
00712   /* Disable Autoreload write complete interrupt */
00713   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00714
00715   /* Disable Compare write complete interrupt */
00716   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00717
00718   /* Disable Autoreload match interrupt */
00719   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00720
00721   /* Disable Compare match interrupt */
00722   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00723
00724   /* If external trigger source is used, then disable external trigger interrupt */
00725   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00726   {
00727     /* Disable external trigger interrupt */
00728     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00729   }
00730
00731   /* Change the TIM state*/
00732   hlptim->State= HAL_LPTIM_STATE_READY;
00733
00734   /* Return function status */
00735   return HAL_OK;
00736 }
00737
00738 /**
00739   * @brief  Starts the LPTIM in Set once mode.
00740   * @param  hlptim : LPTIM handle
00741   * @param  Period : Specifies the Autoreload value.
00742   *         This parameter must be a value between 0x0000 and 0xFFFF.
00743   * @param  Pulse : Specifies the compare value.
00744   *         This parameter must be a value between 0x0000 and 0xFFFF.
00745   * @retval HAL status
00746   */
00747 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00748 {
00749   /* Check the parameters */
00750   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00751   assert_param(IS_LPTIM_PERIOD(Period));
00752   assert_param(IS_LPTIM_PULSE(Pulse));
00753
00754   /* Set the LPTIM state */
00755   hlptim->State= HAL_LPTIM_STATE_BUSY;
00756
00757   /* Set WAVE bit to enable the set once mode */
00758   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00759
00760   /* Enable the Peripheral */
00761   __HAL_LPTIM_ENABLE(hlptim);
00762
00763   /* Load the period value in the autoreload register */
00764   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00765
00766   /* Load the pulse value in the compare register */
00767   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00768
00769   /* Start timer in single mode */
00770   __HAL_LPTIM_START_SINGLE(hlptim);
00771
00772   /* Change the TIM state*/
00773   hlptim->State= HAL_LPTIM_STATE_READY;
00774
00775   /* Return function status */
00776   return HAL_OK;
00777 }
00778
00779 /**
00780   * @brief  Stops the LPTIM Set once mode.
00781   * @param  hlptim : LPTIM handle
00782   * @retval HAL status
00783   */
00784 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00785 {
00786   /* Check the parameters */
00787   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00788
00789   /* Set the LPTIM state */
00790   hlptim->State= HAL_LPTIM_STATE_BUSY;
00791
00792   /* Disable the Peripheral */
00793   __HAL_LPTIM_DISABLE(hlptim);
00794
00795   /* Change the TIM state*/
00796   hlptim->State= HAL_LPTIM_STATE_READY;
00797
00798   /* Return function status */
00799   return HAL_OK;
00800 }
00801
00802 /**
00803   * @brief  Starts the LPTIM Set once mode in interrupt mode.
00804   * @param  hlptim : LPTIM handle
00805   * @param  Period : Specifies the Autoreload value.
00806   *         This parameter must be a value between 0x0000 and 0xFFFF.
00807   * @param  Pulse : Specifies the compare value.
00808   *         This parameter must be a value between 0x0000 and 0xFFFF.
00809   * @retval HAL status
00810   */
00811 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00812 {
00813   /* Check the parameters */
00814   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00815   assert_param(IS_LPTIM_PERIOD(Period));
00816   assert_param(IS_LPTIM_PULSE(Pulse));
00817
00818   /* Set the LPTIM state */
00819   hlptim->State= HAL_LPTIM_STATE_BUSY;
00820
00821   /* Set WAVE bit to enable the set once mode */
00822   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00823
00824   /* Enable Autoreload write complete interrupt */
00825   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00826
00827   /* Enable Compare write complete interrupt */
00828   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00829
00830   /* Enable Autoreload match interrupt */
00831   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00832
00833   /* Enable Compare match interrupt */
00834   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00835
00836   /* If external trigger source is used, then enable external trigger interrupt */
00837   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00838   {
00839     /* Enable external trigger interrupt */
00840     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00841   }
00842
00843   /* Enable the Peripheral */
00844   __HAL_LPTIM_ENABLE(hlptim);
00845
00846   /* Load the period value in the autoreload register */
00847   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00848
00849   /* Load the pulse value in the compare register */
00850   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00851
00852   /* Start timer in single mode */
00853   __HAL_LPTIM_START_SINGLE(hlptim);
00854
00855   /* Change the TIM state*/
00856   hlptim->State= HAL_LPTIM_STATE_READY;
00857
00858   /* Return function status */
00859   return HAL_OK;
00860 }
00861
00862 /**
00863   * @brief  Stops the LPTIM Set once mode in interrupt mode.
00864   * @param  hlptim : LPTIM handle
00865   * @retval HAL status
00866   */
00867 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00868 {
00869   /* Check the parameters */
00870   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00871
00872   /* Set the LPTIM state */
00873   hlptim->State= HAL_LPTIM_STATE_BUSY;
00874
00875   /* Disable the Peripheral */
00876   __HAL_LPTIM_DISABLE(hlptim);
00877
00878   /* Disable Autoreload write complete interrupt */
00879   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00880
00881   /* Disable Compare write complete interrupt */
00882   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00883
00884   /* Disable Autoreload match interrupt */
00885   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00886
00887   /* Disable Compare match interrupt */
00888   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00889
00890   /* If external trigger source is used, then disable external trigger interrupt */
00891   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00892   {
00893     /* Disable external trigger interrupt */
00894     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00895   }
00896
00897   /* Change the TIM state*/
00898   hlptim->State= HAL_LPTIM_STATE_READY;
00899
00900   /* Return function status */
00901   return HAL_OK;
00902 }
00903
00904 /**
00905   * @brief  Starts the Encoder interface.
00906   * @param  hlptim : LPTIM handle
00907   * @param  Period : Specifies the Autoreload value.
00908   *         This parameter must be a value between 0x0000 and 0xFFFF.
00909   * @retval HAL status
00910   */
00911 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00912 {
00913   uint32_t tmpcfgr = 0U;
00914
00915   /* Check the parameters */
00916   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00917   assert_param(IS_LPTIM_PERIOD(Period));
00918   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00919   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
00920   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00921
00922   /* Set the LPTIM state */
00923   hlptim->State= HAL_LPTIM_STATE_BUSY;
00924
00925   /* Get the LPTIMx CFGR value */
00926   tmpcfgr = hlptim->Instance->CFGR;
00927
00928   /* Clear CKPOL bits */
00929   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
00930
00931   /* Set Input polarity */
00932   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
00933
00934   /* Write to LPTIMx CFGR */
00935   hlptim->Instance->CFGR = tmpcfgr;
00936
00937   /* Set ENC bit to enable the encoder interface */
00938   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
00939
00940   /* Enable the Peripheral */
00941   __HAL_LPTIM_ENABLE(hlptim);
00942
00943   /* Load the period value in the autoreload register */
00944   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00945
00946   /* Start timer in continuous mode */
00947   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00948
00949   /* Change the TIM state*/
00950   hlptim->State= HAL_LPTIM_STATE_READY;
00951
00952   /* Return function status */
00953   return HAL_OK;
00954 }
00955
00956 /**
00957   * @brief  Stops the Encoder interface.
00958   * @param  hlptim : LPTIM handle
00959   * @retval HAL status
00960   */
00961 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
00962 {
00963   /* Check the parameters */
00964   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00965
00966   /* Set the LPTIM state */
00967   hlptim->State= HAL_LPTIM_STATE_BUSY;
00968
00969   /* Disable the Peripheral */
00970   __HAL_LPTIM_DISABLE(hlptim);
00971
00972   /* Reset ENC bit to disable the encoder interface */
00973   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
00974
00975   /* Change the TIM state*/
00976   hlptim->State= HAL_LPTIM_STATE_READY;
00977
00978   /* Return function status */
00979   return HAL_OK;
00980 }
00981
00982 /**
00983   * @brief  Starts the Encoder interface in interrupt mode.
00984   * @param  hlptim : LPTIM handle
00985   * @param  Period : Specifies the Autoreload value.
00986   *         This parameter must be a value between 0x0000 and 0xFFFF.
00987   * @retval HAL status
00988   */
00989 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00990 {
00991   uint32_t tmpcfgr = 0U;
00992
00993   /* Check the parameters */
00994   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00995   assert_param(IS_LPTIM_PERIOD(Period));
00996   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00997   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
00998   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00999
01000   /* Set the LPTIM state */
01001   hlptim->State= HAL_LPTIM_STATE_BUSY;
01002
01003   /* Configure edge sensitivity for encoder mode */
01004   /* Get the LPTIMx CFGR value */
01005   tmpcfgr = hlptim->Instance->CFGR;
01006
01007   /* Clear CKPOL bits */
01008   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01009
01010   /* Set Input polarity */
01011   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01012
01013   /* Write to LPTIMx CFGR */
01014   hlptim->Instance->CFGR = tmpcfgr;
01015
01016   /* Set ENC bit to enable the encoder interface */
01017   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01018
01019   /* Enable "switch to down direction" interrupt */
01020   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01021
01022   /* Enable "switch to up direction" interrupt */
01023   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01024
01025   /* Enable the Peripheral */
01026   __HAL_LPTIM_ENABLE(hlptim);
01027
01028   /* Load the period value in the autoreload register */
01029   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01030
01031   /* Start timer in continuous mode */
01032   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01033
01034   /* Change the TIM state*/
01035   hlptim->State= HAL_LPTIM_STATE_READY;
01036
01037   /* Return function status */
01038   return HAL_OK;
01039 }
01040
01041 /**
01042   * @brief  Stops the Encoder interface in interrupt mode.
01043   * @param  hlptim : LPTIM handle
01044   * @retval HAL status
01045   */
01046 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01047 {
01048   /* Check the parameters */
01049   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01050
01051   /* Set the LPTIM state */
01052   hlptim->State= HAL_LPTIM_STATE_BUSY;
01053
01054   /* Disable the Peripheral */
01055   __HAL_LPTIM_DISABLE(hlptim);
01056
01057   /* Reset ENC bit to disable the encoder interface */
01058   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01059
01060   /* Disable "switch to down direction" interrupt */
01061   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01062
01063   /* Disable "switch to up direction" interrupt */
01064   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01065
01066   /* Change the TIM state*/
01067   hlptim->State= HAL_LPTIM_STATE_READY;
01068
01069   /* Return function status */
01070   return HAL_OK;
01071 }
01072
01073 /**
01074   * @brief  Starts the Timeout function. The first trigger event will start the
01075   *         timer, any successive trigger event will reset the counter and
01076   *         the timer restarts.
01077   * @param  hlptim : LPTIM handle
01078   * @param  Period : Specifies the Autoreload value.
01079   *         This parameter must be a value between 0x0000 and 0xFFFF.
01080   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01081   *         This parameter must be a value between 0x0000 and 0xFFFF.
01082   * @retval HAL status
01083   */
01084 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01085 {
01086   /* Check the parameters */
01087   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01088   assert_param(IS_LPTIM_PERIOD(Period));
01089   assert_param(IS_LPTIM_PULSE(Timeout));
01090
01091   /* Set the LPTIM state */
01092   hlptim->State= HAL_LPTIM_STATE_BUSY;
01093
01094   /* Set TIMOUT bit to enable the timeout function */
01095   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01096
01097   /* Enable the Peripheral */
01098   __HAL_LPTIM_ENABLE(hlptim);
01099
01100   /* Load the period value in the autoreload register */
01101   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01102
01103   /* Load the Timeout value in the compare register */
01104   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01105
01106   /* Start timer in continuous mode */
01107   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01108
01109   /* Change the TIM state*/
01110   hlptim->State= HAL_LPTIM_STATE_READY;
01111
01112   /* Return function status */
01113   return HAL_OK;
01114 }
01115
01116 /**
01117   * @brief  Stops the Timeout function.
01118   * @param  hlptim : LPTIM handle
01119   * @retval HAL status
01120   */
01121 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01122 {
01123   /* Check the parameters */
01124   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01125
01126   /* Set the LPTIM state */
01127   hlptim->State= HAL_LPTIM_STATE_BUSY;
01128
01129   /* Disable the Peripheral */
01130   __HAL_LPTIM_DISABLE(hlptim);
01131
01132   /* Reset TIMOUT bit to enable the timeout function */
01133   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01134
01135   /* Change the TIM state*/
01136   hlptim->State= HAL_LPTIM_STATE_READY;
01137
01138   /* Return function status */
01139   return HAL_OK;
01140 }
01141
01142 /**
01143   * @brief  Starts the Timeout function in interrupt mode. The first trigger
01144   *         event will start the timer, any successive trigger event will reset
01145   *         the counter and the timer restarts.
01146   * @param  hlptim : LPTIM handle
01147   * @param  Period : Specifies the Autoreload value.
01148   *         This parameter must be a value between 0x0000 and 0xFFFF.
01149   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01150   *         This parameter must be a value between 0x0000 and 0xFFFF.
01151   * @retval HAL status
01152   */
01153 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01154 {
01155   /* Check the parameters */
01156   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01157   assert_param(IS_LPTIM_PERIOD(Period));
01158   assert_param(IS_LPTIM_PULSE(Timeout));
01159
01160   /* Set the LPTIM state */
01161   hlptim->State= HAL_LPTIM_STATE_BUSY;
01162
01163   /* Set TIMOUT bit to enable the timeout function */
01164   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01165
01166   /* Enable Compare match interrupt */
01167   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01168
01169   /* Enable the Peripheral */
01170   __HAL_LPTIM_ENABLE(hlptim);
01171
01172   /* Load the period value in the autoreload register */
01173   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01174
01175   /* Load the Timeout value in the compare register */
01176   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01177
01178   /* Start timer in continuous mode */
01179   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01180
01181   /* Change the TIM state*/
01182   hlptim->State= HAL_LPTIM_STATE_READY;
01183
01184   /* Return function status */
01185   return HAL_OK;
01186 }
01187
01188 /**
01189   * @brief  Stops the Timeout function in interrupt mode.
01190   * @param  hlptim : LPTIM handle
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01194 {
01195   /* Check the parameters */
01196   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01197
01198   /* Set the LPTIM state */
01199   hlptim->State= HAL_LPTIM_STATE_BUSY;
01200
01201   /* Disable the Peripheral */
01202   __HAL_LPTIM_DISABLE(hlptim);
01203
01204   /* Reset TIMOUT bit to enable the timeout function */
01205   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01206
01207   /* Disable Compare match interrupt */
01208   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01209
01210   /* Change the TIM state*/
01211   hlptim->State= HAL_LPTIM_STATE_READY;
01212
01213   /* Return function status */
01214   return HAL_OK;
01215 }
01216
01217 /**
01218   * @brief  Starts the Counter mode.
01219   * @param  hlptim : LPTIM handle
01220   * @param  Period : Specifies the Autoreload value.
01221   *         This parameter must be a value between 0x0000 and 0xFFFF.
01222   * @retval HAL status
01223   */
01224 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01225 {
01226   /* Check the parameters */
01227   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01228   assert_param(IS_LPTIM_PERIOD(Period));
01229
01230   /* Set the LPTIM state */
01231   hlptim->State= HAL_LPTIM_STATE_BUSY;
01232
01233   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01234   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01235   {
01236     /* Check if clock is prescaled */
01237     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01238     /* Set clock prescaler to 0 */
01239     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01240   }
01241
01242   /* Enable the Peripheral */
01243   __HAL_LPTIM_ENABLE(hlptim);
01244
01245   /* Load the period value in the autoreload register */
01246   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01247
01248   /* Start timer in continuous mode */
01249   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01250
01251   /* Change the TIM state*/
01252   hlptim->State= HAL_LPTIM_STATE_READY;
01253
01254   /* Return function status */
01255   return HAL_OK;
01256 }
01257
01258 /**
01259   * @brief  Stops the Counter mode.
01260   * @param  hlptim : LPTIM handle
01261   * @retval HAL status
01262   */
01263 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01264 {
01265   /* Check the parameters */
01266   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01267
01268   /* Set the LPTIM state */
01269   hlptim->State= HAL_LPTIM_STATE_BUSY;
01270
01271   /* Disable the Peripheral */
01272   __HAL_LPTIM_DISABLE(hlptim);
01273
01274   /* Change the TIM state*/
01275   hlptim->State= HAL_LPTIM_STATE_READY;
01276
01277   /* Return function status */
01278   return HAL_OK;
01279 }
01280
01281 /**
01282   * @brief  Starts the Counter mode in interrupt mode.
01283   * @param  hlptim : LPTIM handle
01284   * @param  Period : Specifies the Autoreload value.
01285   *         This parameter must be a value between 0x0000 and 0xFFFF.
01286   * @retval HAL status
01287   */
01288 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01289 {
01290   /* Check the parameters */
01291   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01292   assert_param(IS_LPTIM_PERIOD(Period));
01293
01294   /* Set the LPTIM state */
01295   hlptim->State= HAL_LPTIM_STATE_BUSY;
01296
01297   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01298   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01299   {
01300     /* Check if clock is prescaled */
01301     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01302     /* Set clock prescaler to 0 */
01303     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01304   }
01305
01306   /* Enable Autoreload write complete interrupt */
01307   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01308
01309   /* Enable Autoreload match interrupt */
01310   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01311
01312   /* Enable the Peripheral */
01313   __HAL_LPTIM_ENABLE(hlptim);
01314
01315   /* Load the period value in the autoreload register */
01316   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01317
01318   /* Start timer in continuous mode */
01319   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01320
01321   /* Change the TIM state*/
01322   hlptim->State= HAL_LPTIM_STATE_READY;
01323
01324   /* Return function status */
01325   return HAL_OK;
01326 }
01327
01328 /**
01329   * @brief  Stops the Counter mode in interrupt mode.
01330   * @param  hlptim : LPTIM handle
01331   * @retval HAL status
01332   */
01333 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01334 {
01335   /* Check the parameters */
01336   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01337
01338   /* Set the LPTIM state */
01339   hlptim->State= HAL_LPTIM_STATE_BUSY;
01340
01341   /* Disable the Peripheral */
01342   __HAL_LPTIM_DISABLE(hlptim);
01343
01344   /* Disable Autoreload write complete interrupt */
01345   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01346
01347   /* Disable Autoreload match interrupt */
01348   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01349
01350   /* Change the TIM state*/
01351   hlptim->State= HAL_LPTIM_STATE_READY;
01352
01353   /* Return function status */
01354   return HAL_OK;
01355 }
01356
01357 /**
01358   * @}
01359   */
01360
01361 /** @defgroup LPTIM_Group3 LPTIM Read operation functions
01362  *  @brief  Read operation functions.
01363  *
01364 @verbatim
01365   ==============================================================================
01366                   ##### LPTIM Read operation functions #####
01367   ==============================================================================
01368 [..]  This section provides LPTIM Reading functions.
01369       (+) Read the counter value.
01370       (+) Read the period (Auto-reload) value.
01371       (+) Read the pulse (Compare)value.
01372 @endverbatim
01373   * @{
01374   */
01375
01376 /**
01377   * @brief  This function returns the current counter value.
01378   * @param  hlptim: LPTIM handle
01379   * @retval Counter value.
01380   */
01381 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
01382 {
01383     /* Check the parameters */
01384   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01385
01386   return (hlptim->Instance->CNT);
01387 }
01388
01389 /**
01390   * @brief  This function return the current Autoreload (Period) value.
01391   * @param  hlptim: LPTIM handle
01392   * @retval Autoreload value.
01393   */
01394 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
01395 {
01396     /* Check the parameters */
01397   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01398
01399   return (hlptim->Instance->ARR);
01400 }
01401
01402 /**
01403   * @brief  This function return the current Compare (Pulse) value.
01404   * @param  hlptim: LPTIM handle
01405   * @retval Compare value.
01406   */
01407 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
01408 {
01409     /* Check the parameters */
01410   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01411
01412   return (hlptim->Instance->CMP);
01413 }
01414
01415 /**
01416   * @}
01417   */
01418
01419
01420
01421 /** @defgroup LPTIM_Group4 LPTIM IRQ handler
01422  *  @brief  LPTIM  IRQ handler.
01423  *
01424 @verbatim
01425   ==============================================================================
01426                       ##### LPTIM IRQ handler  #####
01427   ==============================================================================
01428 [..]  This section provides LPTIM IRQ handler function.
01429
01430 @endverbatim
01431   * @{
01432   */
01433
01434 /**
01435   * @brief  This function handles LPTIM interrupt request.
01436   * @param  hlptim: LPTIM handle
01437   * @retval None
01438   */
01439 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01440 {
01441   /* Compare match interrupt */
01442   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01443         {
01444     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
01445                 {
01446       /* Clear Compare match flag */
01447       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01448       /* Compare match Callback */
01449       HAL_LPTIM_CompareMatchCallback(hlptim);
01450     }
01451   }
01452
01453   /* Autoreload match interrupt */
01454   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01455         {
01456     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
01457                 {
01458       /* Clear Autoreload match flag */
01459       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01460       /* Autoreload match Callback */
01461       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01462     }
01463   }
01464
01465   /* Trigger detected interrupt */
01466   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01467         {
01468     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
01469                 {
01470       /* Clear Trigger detected flag */
01471       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01472       /* Trigger detected callback */
01473       HAL_LPTIM_TriggerCallback(hlptim);
01474     }
01475   }
01476
01477   /* Compare write interrupt */
01478   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01479         {
01480     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)
01481                 {
01482       /* Clear Compare write flag */
01483       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01484       /* Compare write Callback */
01485       HAL_LPTIM_CompareWriteCallback(hlptim);
01486     }
01487   }
01488
01489   /* Autoreload write interrupt */
01490   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01491         {
01492     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
01493                 {
01494       /* Clear Autoreload write flag */
01495       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01496       /* Autoreload write Callback */
01497       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01498     }
01499   }
01500
01501   /* Direction counter changed from Down to Up interrupt */
01502   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01503         {
01504     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
01505                 {
01506       /* Clear Direction counter changed from Down to Up flag */
01507       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01508       /* Direction counter changed from Down to Up Callback */
01509       HAL_LPTIM_DirectionUpCallback(hlptim);
01510     }
01511   }
01512
01513   /* Direction counter changed from Up to Down interrupt */
01514   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01515         {
01516     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
01517                 {
01518       /* Clear Direction counter changed from Up to Down flag */
01519       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01520       /* Direction counter changed from Up to Down Callback */
01521       HAL_LPTIM_DirectionDownCallback(hlptim);
01522     }
01523   }
01524   __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
01525 }
01526
01527 /**
01528   * @brief  Compare match callback in non blocking mode
01529   * @param  hlptim : LPTIM handle
01530   * @retval None
01531   */
01532 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01533 {
01534   /* Prevent unused argument(s) compilation warning */
01535   UNUSED(hlptim);
01536   /* NOTE : This function Should not be modified, when the callback is needed,
01537             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01538    */
01539 }
01540
01541 /**
01542   * @brief  Autoreload match callback in non blocking mode
01543   * @param  hlptim : LPTIM handle
01544   * @retval None
01545   */
01546 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01547 {
01548   /* Prevent unused argument(s) compilation warning */
01549   UNUSED(hlptim);
01550   /* NOTE : This function Should not be modified, when the callback is needed,
01551             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01552    */
01553 }
01554
01555 /**
01556   * @brief  Trigger detected callback in non blocking mode
01557   * @param  hlptim : LPTIM handle
01558   * @retval None
01559   */
01560 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
01561 {
01562   /* Prevent unused argument(s) compilation warning */
01563   UNUSED(hlptim);
01564   /* NOTE : This function Should not be modified, when the callback is needed,
01565             the HAL_LPTIM_TriggerCallback could be implemented in the user file
01566    */
01567 }
01568
01569 /**
01570   * @brief  Compare write callback in non blocking mode
01571   * @param  hlptim : LPTIM handle
01572   * @retval None
01573   */
01574 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
01575 {
01576   /* Prevent unused argument(s) compilation warning */
01577   UNUSED(hlptim);
01578   /* NOTE : This function Should not be modified, when the callback is needed,
01579             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
01580    */
01581 }
01582
01583 /**
01584   * @brief  Autoreload write callback in non blocking mode
01585   * @param  hlptim : LPTIM handle
01586   * @retval None
01587   */
01588 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
01589 {
01590   /* Prevent unused argument(s) compilation warning */
01591   UNUSED(hlptim);
01592   /* NOTE : This function Should not be modified, when the callback is needed,
01593             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
01594    */
01595 }
01596
01597 /**
01598   * @brief  Direction counter changed from Down to Up callback in non blocking mode
01599   * @param  hlptim : LPTIM handle
01600   * @retval None
01601   */
01602 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
01603 {
01604   /* Prevent unused argument(s) compilation warning */
01605   UNUSED(hlptim);
01606   /* NOTE : This function Should not be modified, when the callback is needed,
01607             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
01608    */
01609 }
01610
01611 /**
01612   * @brief  Direction counter changed from Up to Down callback in non blocking mode
01613   * @param  hlptim : LPTIM handle
01614   * @retval None
01615   */
01616 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
01617 {
01618   /* Prevent unused argument(s) compilation warning */
01619   UNUSED(hlptim);
01620   /* NOTE : This function Should not be modified, when the callback is needed,
01621             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
01622    */
01623 }
01624
01625 /**
01626   * @}
01627   */
01628
01629 /** @defgroup LPTIM_Group5 Peripheral State functions
01630  *  @brief   Peripheral State functions.
01631  *
01632 @verbatim
01633   ==============================================================================
01634                       ##### Peripheral State functions #####
01635   ==============================================================================
01636     [..]
01637     This subsection permits to get in run-time the status of the peripheral.
01638
01639 @endverbatim
01640   * @{
01641   */
01642
01643 /**
01644   * @brief  Returns the LPTIM state.
01645   * @param  hlptim: LPTIM handle
01646   * @retval HAL state
01647   */
01648 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
01649 {
01650   return hlptim->State;
01651 }
01652
01653 /**
01654   * @}
01655   */
01656
01657
01658 /**
01659   * @}
01660   */
01661
01662 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
01663 #endif /* HAL_LPTIM_MODULE_ENABLED */
01664 /**
01665   * @}
01666   */
01667
01668 /**
01669   * @}
01670   */
01671
01672 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_lptim.h Source File

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stm32f4xx_hal_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of LPTIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_LPTIM_H
00040 #define __STM32F4xx_HAL_LPTIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @defgroup LPTIM LPTIM
00055   * @brief LPTIM HAL module driver
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
00065   * @{
00066   */
00067 #define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT  ((uint32_t)EXTI_IMR_MR23)  /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
00068 /**
00069   * @}
00070   */
00071
00072 /**
00073   * @brief  LPTIM Clock configuration definition
00074   */
00075 typedef struct
00076 {
00077   uint32_t Source;         /*!< Selects the clock source.
00078                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00079
00080   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00081                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00082
00083 }LPTIM_ClockConfigTypeDef;
00084
00085 /**
00086   * @brief  LPTIM Clock configuration definition
00087   */
00088 typedef struct
00089 {
00090   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00091                            if the ULPTIM input is selected.
00092                            Note: This parameter is used only when Ultra low power clock source is used.
00093                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00094                            (one of the Low power oscillator) must be active.
00095                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00096
00097   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00098                            Note: This parameter is used only when Ultra low power clock source is used.
00099                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00100
00101 }LPTIM_ULPClockConfigTypeDef;
00102
00103 /**
00104   * @brief  LPTIM Trigger configuration definition
00105   */
00106 typedef struct
00107 {
00108   uint32_t Source;        /*!< Selects the Trigger source.
00109                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00110
00111   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00112                           Note: This parameter is used only when an external trigger is used.
00113                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00114
00115   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00116                           Note: This parameter is used only when an external trigger is used.
00117                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00118 }LPTIM_TriggerConfigTypeDef;
00119
00120 /**
00121   * @brief  LPTIM Initialization Structure definition
00122   */
00123 typedef struct
00124 {
00125   LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
00126
00127   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
00128
00129   LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
00130
00131   uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
00132                                                     This parameter can be a value of @ref LPTIM_Output_Polarity */
00133
00134   uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autorelaod and the compare
00135                                                     values is done immediately or after the end of current period.
00136                                                     This parameter can be a value of @ref LPTIM_Updating_Mode */
00137
00138   uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
00139                                                     or each external event.
00140                                                     This parameter can be a value of @ref LPTIM_Counter_Source */
00141
00142 }LPTIM_InitTypeDef;
00143
00144 /**
00145   * @brief  HAL LPTIM State structure definition
00146   */
00147 typedef enum __HAL_LPTIM_StateTypeDef
00148 {
00149   HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00150   HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00151   HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
00152   HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
00153   HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
00154 }HAL_LPTIM_StateTypeDef;
00155
00156 /**
00157   * @brief  LPTIM handle Structure definition
00158   */
00159 typedef struct
00160 {
00161       LPTIM_TypeDef              *Instance;         /*!< Register base address     */
00162
00163       LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
00164
00165       HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */
00166
00167       HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
00168
00169    __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00170
00171 }LPTIM_HandleTypeDef;
00172
00173 /**
00174   * @}
00175   */
00176
00177 /* Exported constants --------------------------------------------------------*/
00178 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00179   * @{
00180   */
00181
00182 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00183   * @{
00184   */
00185 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00U)
00186 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00192   * @{
00193   */
00194 #define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x00000000U)
00195 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00196 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00197 #define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
00198 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00199 #define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
00200 #define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
00201 #define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00207   * @{
00208   */
00209
00210 #define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000U)
00211 #define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00217   * @{
00218   */
00219 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
00220 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS     LPTIM_CFGR_CKFLT_0
00221 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS     LPTIM_CFGR_CKFLT_1
00222 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS     LPTIM_CFGR_CKFLT
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00228   * @{
00229   */
00230
00231 #define LPTIM_CLOCKPOLARITY_RISING                ((uint32_t)0x00000000U)
00232 #define LPTIM_CLOCKPOLARITY_FALLING               LPTIM_CFGR_CKPOL_0
00233 #define LPTIM_CLOCKPOLARITY_RISING_FALLING        LPTIM_CFGR_CKPOL_1
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00239   * @{
00240   */
00241 #define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFFU)
00242 #define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000U)
00243 #define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
00244 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00245 #define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00246 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00247 #define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00253   * @{
00254   */
00255 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00256 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00257 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00263   * @{
00264   */
00265 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000U)
00266 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00267 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00268 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00274   * @{
00275   */
00276
00277 #define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000U)
00278 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00284   * @{
00285   */
00286
00287 #define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000U)
00288 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
00294   * @{
00295   */
00296
00297 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00298 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00299 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00300 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00301 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00302 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00303 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00309   * @{
00310   */
00311
00312 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00313 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00314 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00315 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00316 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00317 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00318 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup LPTIM_Option Register Definition
00324   * @{
00325   */
00326 #define LPTIM_OP_PAD_AF                          ((uint32_t)0x00000000U)
00327 #define LPTIM_OP_PAD_PA4                         LPTIM_OR_OR_0
00328 #define LPTIM_OP_PAD_PB9                         LPTIM_OR_OR_1
00329 #define LPTIM_OP_TIM_DAC                         LPTIM_OR_OR
00330
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 /* Exported macro ------------------------------------------------------------*/
00340 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00341   * @{
00342   */
00343
00344 /** @brief Reset LPTIM handle state
00345   * @param  __HANDLE__: LPTIM handle
00346   * @retval None
00347   */
00348 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00349
00350 /**
00351   * @brief  Enable/Disable the LPTIM peripheral.
00352   * @param  __HANDLE__: LPTIM handle
00353   * @retval None
00354   */
00355 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
00356 #define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))
00357
00358 /**
00359   * @brief  Starts the LPTIM peripheral in Continuous or in single mode.
00360   * @param  __HANDLE__: DMA handle
00361   * @retval None
00362   */
00363 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00364 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00365
00366
00367 /**
00368   * @brief  Writes the passed parameter in the Autoreload register.
00369   * @param  __HANDLE__: LPTIM handle
00370   * @param  __VALUE__ : Autoreload value
00371   * @retval None
00372   */
00373 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00374
00375 /**
00376   * @brief  Writes the passed parameter in the Compare register.
00377   * @param  __HANDLE__: LPTIM handle
00378   * @param  __VALUE__ : Compare value
00379   * @retval None
00380   */
00381 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00382
00383 /**
00384   * @brief  Checks whether the specified LPTIM flag is set or not.
00385   * @param  __HANDLE__: LPTIM handle
00386   * @param  __FLAG__  : LPTIM flag to check
00387   *            This parameter can be a value of:
00388   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00389   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00390   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00391   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00392   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00393   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00394   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00395   * @retval The state of the specified flag (SET or RESET).
00396   */
00397 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00398
00399 /**
00400   * @brief  Clears the specified LPTIM flag.
00401   * @param  __HANDLE__: LPTIM handle.
00402   * @param  __FLAG__  : LPTIM flag to clear.
00403   *            This parameter can be a value of:
00404   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00405   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00406   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00407   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00408   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00409   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00410   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00411   * @retval None.
00412   */
00413 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00414
00415 /**
00416   * @brief  Enable the specified LPTIM interrupt.
00417   * @param  __HANDLE__    : LPTIM handle.
00418   * @param  __INTERRUPT__ : LPTIM interrupt to set.
00419   *            This parameter can be a value of:
00420   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00421   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00422   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00423   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00424   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00425   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00426   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00427   * @retval None.
00428   */
00429 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00430
00431  /**
00432   * @brief  Disable the specified LPTIM interrupt.
00433   * @param  __HANDLE__    : LPTIM handle.
00434   * @param  __INTERRUPT__ : LPTIM interrupt to set.
00435   *            This parameter can be a value of:
00436   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00437   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00438   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00439   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00440   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00441   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00442   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00443   * @retval None.
00444   */
00445 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00446
00447     /**
00448   * @brief  Checks whether the specified LPTIM interrupt is set or not.
00449   * @param  __HANDLE__    : LPTIM handle.
00450   * @param  __INTERRUPT__ : LPTIM interrupt to check.
00451   *            This parameter can be a value of:
00452   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00453   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00454   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00455   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00456   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00457   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00458   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00459   * @retval Interrupt status.
00460   */
00461
00462 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00463
00464 /** @brief  LPTIM Option Register
00465   * @param  __HANDLE__: LPTIM handle
00466   * @param   __VALUE__: This parameter can be a value of :
00467   *            @arg  LPTIM_OP_PAD_AF
00468   *            @arg  LPTIM_OP_PAD_PA4
00469   *            @arg  LPTIM_OP_PAD_PB9
00470   *            @arg  LPTIM_OP_TIM_DAC
00471   * @retval None
00472   */
00473 #define __HAL_LPTIM_OPTR_CONFIG(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->OR  =  (__VALUE__))
00474
00475 /**
00476   * @brief  Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
00477   * @retval None
00478   */
00479 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00480
00481 /**
00482   * @brief  Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
00483   * @retval None
00484   */
00485 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
00486
00487 /**
00488   * @brief  Enable event on the LPTIM Wake-up Timer associated Exti line.
00489   * @retval None.
00490   */
00491 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00492
00493 /**
00494   * @brief  Disable event on the LPTIM Wake-up Timer associated Exti line.
00495   * @retval None.
00496   */
00497 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
00498
00499 /**
00500   * @brief  Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
00501   * @retval None.
00502   */
00503 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00504
00505 /**
00506   * @brief  Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
00507   * @retval None.
00508   */
00509 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
00510
00511 /**
00512   * @brief  Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
00513   * @retval None.
00514   */
00515 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00516
00517 /**
00518   * @brief  Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
00519   * @retval None.
00520   */
00521 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
00522
00523 /**
00524   * @brief  Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
00525   * @retval None.
00526   */
00527 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
00528                                                                      __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
00529                                                                     }while(0)
00530
00531 /**
00532   * @brief  Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
00533   * This parameter can be:
00534   * @retval None.
00535   */
00536 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
00537                                                                       __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
00538                                                                      }while(0)
00539
00540 /**
00541   * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
00542   * @retval Line Status.
00543   */
00544 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00545
00546 /**
00547   * @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
00548   * @retval None.
00549   */
00550 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00551
00552 /**
00553   * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
00554   * @retval None.
00555   */
00556 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
00557
00558 /**
00559   * @}
00560   */
00561 /* Exported functions --------------------------------------------------------*/
00562 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00563   * @{
00564   */
00565
00566 /* Initialization/de-initialization functions  ********************************/
00567 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00568 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00569
00570 /* MSP functions  *************************************************************/
00571 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00572 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00573
00574 /* Start/Stop operation functions  *********************************************/
00575 /* ################################# PWM Mode ################################*/
00576 /* Blocking mode: Polling */
00577 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00578 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00579 /* Non-Blocking mode: Interrupt */
00580 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00581 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00582
00583 /* ############################# One Pulse Mode ##############################*/
00584 /* Blocking mode: Polling */
00585 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00586 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00587 /* Non-Blocking mode: Interrupt */
00588 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00589 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00590
00591 /* ############################## Set once Mode ##############################*/
00592 /* Blocking mode: Polling */
00593 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00594 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00595 /* Non-Blocking mode: Interrupt */
00596 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00597 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00598
00599 /* ############################### Encoder Mode ##############################*/
00600 /* Blocking mode: Polling */
00601 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00602 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00603 /* Non-Blocking mode: Interrupt */
00604 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00605 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00606
00607 /* ############################# Time out  Mode ##############################*/
00608 /* Blocking mode: Polling */
00609 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00610 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00611 /* Non-Blocking mode: Interrupt */
00612 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00613 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00614
00615 /* ############################## Counter Mode ###############################*/
00616 /* Blocking mode: Polling */
00617 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00618 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00619 /* Non-Blocking mode: Interrupt */
00620 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00621 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00622
00623 /* Reading operation functions ************************************************/
00624 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
00625 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
00626 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
00627
00628 /* LPTIM IRQ functions  *******************************************************/
00629 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00630
00631 /* CallBack functions  ********************************************************/
00632 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00633 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00634 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00635 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00636 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00637 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00638 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00639
00640 /* Peripheral State functions  ************************************************/
00641 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
00642
00643 /**
00644   * @}
00645   */
00646
00647 /* Private types -------------------------------------------------------------*/
00648 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00649   * @{
00650   */
00651
00652 /**
00653   * @}
00654   */
00655
00656 /* Private variables ---------------------------------------------------------*/
00657 /** @defgroup LPTIM_Private_Variables LPTIM Private Variables
00658   * @{
00659   */
00660
00661 /**
00662   * @}
00663   */
00664
00665 /* Private constants ---------------------------------------------------------*/
00666 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00667   * @{
00668   */
00669
00670 /**
00671   * @}
00672   */
00673
00674 /* Private macros ------------------------------------------------------------*/
00675 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00676   * @{
00677   */
00678
00679 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)           (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00680                                                      ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00681
00682 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)     (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00683                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00684                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00685                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00686                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00687                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00688                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00689                                                      ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00690 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00691
00692 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)      (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00693                                                      ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00694
00695 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)  (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00696                                                      ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00697                                                      ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00698                                                      ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00699
00700 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)       (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00701                                                      ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00702                                                      ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00703
00704 #define IS_LPTIM_TRG_SOURCE(__TRIG__)               (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00705                                                      ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00706                                                      ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00707                                                      ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00708                                                      ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00709                                                      ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00710                                                      ((__TRIG__) == LPTIM_TRIGSOURCE_5))
00711
00712 #define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)        (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00713                                                      ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00714                                                      ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00715
00716 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)   (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00717                                                      ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00718                                                      ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00719                                                      ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00720
00721 #define IS_LPTIM_UPDATE_MODE(__MODE__)              (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00722                                                      ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00723
00724 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)         (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00725                                                      ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00726
00727 #define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)         ((__AUTORELOAD__) <= 0x0000FFFFU)
00728
00729 #define IS_LPTIM_COMPARE(__COMPARE__)               ((__COMPARE__) <= 0x0000FFFFU)
00730
00731 #define IS_LPTIM_PERIOD(PERIOD)               ((PERIOD) <= 0x0000FFFFU)
00732
00733 #define IS_LPTIM_PULSE(PULSE)                 ((PULSE) <= 0x0000FFFFU)
00734
00735 /**
00736   * @}
00737   */
00738
00739 /* Private functions ---------------------------------------------------------*/
00740 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00741   * @{
00742   */
00743
00744 /**
00745   * @}
00746   */
00747
00748 /**
00749   * @}
00750   */
00751
00752 /**
00753   * @}
00754   */
00755
00756 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00757 #ifdef __cplusplus
00758 }
00759 #endif
00760
00761 #endif /* __STM32F4xx_HAL_LPTIM_H */
00762
00763 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:51 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc.c Source File

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stm32f4xx_hal_ltdc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_ltdc.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   LTDC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the LTDC peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020      (#) Program the required configuration through the following parameters:
00021          the LTDC timing, the horizontal and vertical polarity,
00022          the pixel clock polarity, Data Enable polarity and the LTDC background color value
00023          using HAL_LTDC_Init() function
00024
00025      (#) Program the required configuration through the following parameters:
00026          the pixel format, the blending factors, input alpha value, the window size
00027          and the image size using HAL_LTDC_ConfigLayer() function for foreground
00028          or/and background layer.
00029
00030      (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
00031          HAL_LTDC_EnableCLUT functions.
00032
00033      (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
00034
00035      (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
00036          and HAL_LTDC_EnableColorKeying functions.
00037
00038      (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
00039          function
00040
00041      (#) If needed, reconfigure and change the pixel format value, the alpha value
00042          value, the window size, the window position and the layer start address
00043          for foreground or/and background layer using respectively the following
00044          functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
00045          HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
00046
00047      (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
00048
00049      *** LTDC HAL driver macros list ***
00050      =============================================
00051      [..]
00052        Below the list of most used macros in LTDC HAL driver.
00053
00054       (+) __HAL_LTDC_ENABLE: Enable the LTDC.
00055       (+) __HAL_LTDC_DISABLE: Disable the LTDC.
00056       (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.
00057       (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.
00058       (+) __HAL_LTDC_RELOAD_CONFIG: Reload  Layer Configuration.
00059       (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
00060       (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
00061       (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
00062       (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
00063       (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
00064
00065      [..]
00066        (@) You can refer to the LTDC HAL driver header file for more useful macros
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097   */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f4xx_hal.h"
00101
00102 /** @addtogroup STM32F4xx_HAL_Driver
00103   * @{
00104   */
00105 /** @defgroup LTDC LTDC
00106   * @brief LTDC HAL module driver
00107   * @{
00108   */
00109
00110 #ifdef HAL_LTDC_MODULE_ENABLED
00111
00112 #if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00120 /* Private functions ---------------------------------------------------------*/
00121
00122 /** @defgroup LTDC_Exported_Functions LTDC Exported Functions
00123   * @{
00124   */
00125
00126 /** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
00127  *  @brief   Initialization and Configuration functions
00128  *
00129 @verbatim
00130  ===============================================================================
00131                 ##### Initialization and Configuration functions #####
00132  ===============================================================================
00133     [..]  This section provides functions allowing to:
00134       (+) Initialize and configure the LTDC
00135       (+) De-initialize the LTDC
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141 /**
00142   * @brief  Initializes the LTDC according to the specified
00143   *         parameters in the LTDC_InitTypeDef and create the associated handle.
00144   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00145   *                the configuration information for the LTDC.
00146   * @retval HAL status
00147   */
00148 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
00149 {
00150   uint32_t tmp = 0U, tmp1 = 0U;
00151
00152   /* Check the LTDC peripheral state */
00153   if(hltdc == NULL)
00154   {
00155     return HAL_ERROR;
00156   }
00157
00158   /* Check function parameters */
00159   assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
00160   assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
00161   assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
00162   assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
00163   assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
00164   assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
00165   assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
00166   assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
00167   assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
00168   assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
00169   assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
00170   assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
00171   assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
00172
00173   if(hltdc->State == HAL_LTDC_STATE_RESET)
00174   {
00175     /* Allocate lock resource and initialize it */
00176     hltdc->Lock = HAL_UNLOCKED;
00177     /* Init the low level hardware */
00178     HAL_LTDC_MspInit(hltdc);
00179   }
00180
00181   /* Change LTDC peripheral state */
00182   hltdc->State = HAL_LTDC_STATE_BUSY;
00183
00184   /* Configures the HS, VS, DE and PC polarity */
00185   hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
00186   hltdc->Instance->GCR |=  (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
00187   hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
00188
00189   /* Sets Synchronization size */
00190   hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
00191   tmp = (hltdc->Init.HorizontalSync << 16U);
00192   hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
00193
00194   /* Sets Accumulated Back porch */
00195   hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
00196   tmp = (hltdc->Init.AccumulatedHBP << 16U);
00197   hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
00198
00199   /* Sets Accumulated Active Width */
00200   hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
00201   tmp = (hltdc->Init.AccumulatedActiveW << 16U);
00202   hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
00203
00204   /* Sets Total Width */
00205   hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
00206   tmp = (hltdc->Init.TotalWidth << 16U);
00207   hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
00208
00209   /* Sets the background color value */
00210   tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
00211   tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
00212   hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
00213   hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
00214
00215   /* Enable the transfer Error interrupt */
00216   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);
00217
00218   /* Enable the FIFO underrun interrupt */
00219   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);
00220
00221   /* Enable LTDC by setting LTDCEN bit */
00222   __HAL_LTDC_ENABLE(hltdc);
00223
00224   /* Initialize the error code */
00225   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00226
00227   /* Initialize the LTDC state*/
00228   hltdc->State = HAL_LTDC_STATE_READY;
00229
00230   return HAL_OK;
00231 }
00232
00233 /**
00234   * @brief  Deinitializes the LTDC peripheral registers to their default reset
00235   *         values.
00236   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00237   *                the configuration information for the LTDC.
00238   * @retval None
00239   */
00240
00241 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
00242 {
00243   /* DeInit the low level hardware */
00244   HAL_LTDC_MspDeInit(hltdc);
00245
00246   /* Initialize the error code */
00247   hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
00248
00249   /* Initialize the LTDC state*/
00250   hltdc->State = HAL_LTDC_STATE_RESET;
00251
00252   /* Release Lock */
00253   __HAL_UNLOCK(hltdc);
00254
00255   return HAL_OK;
00256 }
00257
00258 /**
00259   * @brief  Initializes the LTDC MSP.
00260   * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
00261   *                the configuration information for the LTDC.
00262   * @retval None
00263   */
00264 __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(hltdc);
00268   /* NOTE : This function Should not be modified, when the callback is needed,
00269             the HAL_LTDC_MspInit could be implemented in the user file
00270    */
00271 }
00272
00273 /**
00274   * @brief  DeInitializes the LTDC MSP.
00275   * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
00276   *                the configuration information for the LTDC.
00277   * @retval None
00278   */
00279 __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
00280 {
00281   /* Prevent unused argument(s) compilation warning */
00282   UNUSED(hltdc);
00283   /* NOTE : This function Should not be modified, when the callback is needed,
00284             the HAL_LTDC_MspDeInit could be implemented in the user file
00285    */
00286 }
00287
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
00293  *  @brief   IO operation functions
00294  *
00295 @verbatim
00296  ===============================================================================
00297                       #####  IO operation functions  #####
00298  ===============================================================================
00299     [..]  This section provides function allowing to:
00300       (+) Handle LTDC interrupt request
00301
00302 @endverbatim
00303   * @{
00304   */
00305 /**
00306   * @brief  Handles LTDC interrupt request.
00307   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00308   *                the configuration information for the LTDC.
00309   * @retval HAL status
00310   */
00311 void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
00312 {
00313   /* Transfer Error Interrupt management ***************************************/
00314   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)
00315   {
00316     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)
00317     {
00318       /* Disable the transfer Error interrupt */
00319       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
00320
00321       /* Clear the transfer error flag */
00322       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
00323
00324       /* Update error code */
00325       hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
00326
00327       /* Change LTDC state */
00328       hltdc->State = HAL_LTDC_STATE_ERROR;
00329
00330       /* Process unlocked */
00331       __HAL_UNLOCK(hltdc);
00332
00333       /* Transfer error Callback */
00334       HAL_LTDC_ErrorCallback(hltdc);
00335     }
00336   }
00337   /* FIFO underrun Interrupt management ***************************************/
00338   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)
00339   {
00340     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)
00341     {
00342       /* Disable the FIFO underrun interrupt */
00343       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
00344
00345       /* Clear the FIFO underrun flag */
00346       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
00347
00348       /* Update error code */
00349       hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
00350
00351       /* Change LTDC state */
00352       hltdc->State = HAL_LTDC_STATE_ERROR;
00353
00354       /* Process unlocked */
00355       __HAL_UNLOCK(hltdc);
00356
00357       /* Transfer error Callback */
00358       HAL_LTDC_ErrorCallback(hltdc);
00359     }
00360   }
00361   /* Line Interrupt management ************************************************/
00362   if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)
00363   {
00364     if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)
00365     {
00366       /* Disable the Line interrupt */
00367       __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
00368
00369       /* Clear the Line interrupt flag */
00370       __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
00371
00372       /* Change LTDC state */
00373       hltdc->State = HAL_LTDC_STATE_READY;
00374
00375       /* Process unlocked */
00376       __HAL_UNLOCK(hltdc);
00377
00378       /* Line interrupt Callback */
00379       HAL_LTDC_LineEventCallback(hltdc);
00380     }
00381   }
00382 }
00383
00384 /**
00385   * @brief  Error LTDC callback.
00386   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00387   *                the configuration information for the LTDC.
00388   * @retval None
00389   */
00390 __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
00391 {
00392   /* Prevent unused argument(s) compilation warning */
00393   UNUSED(hltdc);
00394   /* NOTE : This function Should not be modified, when the callback is needed,
00395             the HAL_LTDC_ErrorCallback could be implemented in the user file
00396    */
00397 }
00398
00399 /**
00400   * @brief  Line Event callback.
00401   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00402   *                the configuration information for the LTDC.
00403   * @retval None
00404   */
00405 __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
00406 {
00407   /* Prevent unused argument(s) compilation warning */
00408   UNUSED(hltdc);
00409   /* NOTE : This function Should not be modified, when the callback is needed,
00410             the HAL_LTDC_LineEventCallback could be implemented in the user file
00411    */
00412 }
00413
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
00419  *  @brief    Peripheral Control functions
00420  *
00421 @verbatim
00422  ===============================================================================
00423                     ##### Peripheral Control functions #####
00424  ===============================================================================
00425     [..]  This section provides functions allowing to:
00426       (+) Configure the LTDC foreground or/and background parameters.
00427       (+) Set the active layer.
00428       (+) Configure the color keying.
00429       (+) Configure the C-LUT.
00430       (+) Enable / Disable the color keying.
00431       (+) Enable / Disable the C-LUT.
00432       (+) Update the layer position.
00433       (+) Update the layer size.
00434       (+) Update pixel format on the fly.
00435       (+) Update transparency on the fly.
00436       (+) Update address on the fly.
00437
00438 @endverbatim
00439   * @{
00440   */
00441
00442 /**
00443   * @brief  Configure the LTDC Layer according to the specified
00444   *         parameters in the LTDC_InitTypeDef and create the associated handle.
00445   * @param  hltdc:     pointer to a LTDC_HandleTypeDef structure that contains
00446   *                    the configuration information for the LTDC.
00447   * @param  pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
00448   *                    the configuration information for the Layer.
00449   * @param  LayerIdx:  LTDC Layer index.
00450   *                    This parameter can be one of the following values:
00451   *                    0 or 1
00452   * @retval HAL status
00453   */
00454 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
00455 {
00456   /* Process locked */
00457   __HAL_LOCK(hltdc);
00458
00459   /* Change LTDC peripheral state */
00460   hltdc->State = HAL_LTDC_STATE_BUSY;
00461
00462   /* Check the parameters */
00463   assert_param(IS_LTDC_LAYER(LayerIdx));
00464   assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
00465   assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
00466   assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
00467   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00468   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00469   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00470   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00471   assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
00472   assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
00473   assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
00474
00475   /* Copy new layer configuration into handle structure */
00476   hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
00477
00478   /* Configure the LTDC Layer */
00479   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00480
00481   /* Sets the Reload type */
00482   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00483
00484   /* Initialize the LTDC state*/
00485   hltdc->State  = HAL_LTDC_STATE_READY;
00486
00487   /* Process unlocked */
00488   __HAL_UNLOCK(hltdc);
00489
00490   return HAL_OK;
00491 }
00492
00493 /**
00494   * @brief  Configure the color keying.
00495   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00496   *                   the configuration information for the LTDC.
00497   * @param  RGBValue: the color key value
00498   * @param  LayerIdx:  LTDC Layer index.
00499   *                   This parameter can be one of the following values:
00500   *                   0 or 1
00501   * @retval HAL status
00502   */
00503 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
00504 {
00505   /* Process locked */
00506   __HAL_LOCK(hltdc);
00507
00508   /* Change LTDC peripheral state */
00509   hltdc->State = HAL_LTDC_STATE_BUSY;
00510
00511   /* Check the parameters */
00512   assert_param(IS_LTDC_LAYER(LayerIdx));
00513
00514   /* Configures the default color values */
00515   LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
00516   LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
00517
00518   /* Sets the Reload type */
00519   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00520
00521   /* Change the LTDC state*/
00522   hltdc->State = HAL_LTDC_STATE_READY;
00523
00524   /* Process unlocked */
00525   __HAL_UNLOCK(hltdc);
00526
00527   return HAL_OK;
00528 }
00529
00530 /**
00531   * @brief  Load the color lookup table.
00532   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00533   *                   the configuration information for the LTDC.
00534   * @param  pCLUT:    pointer to the color lookup table address.
00535   * @param  CLUTSize: the color lookup table size.
00536   * @param  LayerIdx:  LTDC Layer index.
00537   *                   This parameter can be one of the following values:
00538   *                   0 or 1
00539   * @retval HAL status
00540   */
00541 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
00542 {
00543   uint32_t tmp = 0U;
00544   uint32_t counter = 0U;
00545   uint32_t pcounter = 0U;
00546
00547   /* Process locked */
00548   __HAL_LOCK(hltdc);
00549
00550   /* Change LTDC peripheral state */
00551   hltdc->State = HAL_LTDC_STATE_BUSY;
00552
00553   /* Check the parameters */
00554   assert_param(IS_LTDC_LAYER(LayerIdx));
00555
00556   for(counter = 0U; (counter < CLUTSize); counter++)
00557   {
00558     if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
00559     {
00560       tmp  = (((counter + 16U*counter) << 24U) | ((uint32_t)(*pCLUT) & 0xFFU) | ((uint32_t)(*pCLUT) & 0xFF00U) | ((uint32_t)(*pCLUT) & 0xFF0000U));
00561     }
00562     else
00563     {
00564       tmp  = ((counter << 24U) | ((uint32_t)(*pCLUT) & 0xFFU) | ((uint32_t)(*pCLUT) & 0xFF00U) | ((uint32_t)(*pCLUT) & 0xFF0000U));
00565     }
00566     pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
00567     pCLUT = (uint32_t *)pcounter;
00568
00569     /* Specifies the C-LUT address and RGB value */
00570     LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
00571   }
00572
00573   /* Change the LTDC state*/
00574   hltdc->State = HAL_LTDC_STATE_READY;
00575
00576   /* Process unlocked */
00577   __HAL_UNLOCK(hltdc);
00578
00579   return HAL_OK;
00580 }
00581
00582 /**
00583   * @brief  Enable the color keying.
00584   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00585   *                   the configuration information for the LTDC.
00586   * @param  LayerIdx:  LTDC Layer index.
00587   *                   This parameter can be one of the following values:
00588   *                   0 or 1
00589   * @retval  HAL status
00590   */
00591 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00592 {
00593   /* Process locked */
00594   __HAL_LOCK(hltdc);
00595
00596   /* Change LTDC peripheral state */
00597   hltdc->State = HAL_LTDC_STATE_BUSY;
00598
00599   /* Check the parameters */
00600   assert_param(IS_LTDC_LAYER(LayerIdx));
00601
00602   /* Enable LTDC color keying by setting COLKEN bit */
00603   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
00604
00605   /* Sets the Reload type */
00606   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00607
00608   /* Change the LTDC state*/
00609   hltdc->State = HAL_LTDC_STATE_READY;
00610
00611   /* Process unlocked */
00612   __HAL_UNLOCK(hltdc);
00613
00614   return HAL_OK;
00615 }
00616
00617 /**
00618   * @brief  Disable the color keying.
00619   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00620   *                   the configuration information for the LTDC.
00621   * @param  LayerIdx:  LTDC Layer index.
00622   *                   This parameter can be one of the following values:
00623   *                   0 or 1
00624   * @retval  HAL status
00625   */
00626 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00627 {
00628   /* Process locked */
00629   __HAL_LOCK(hltdc);
00630
00631   /* Change LTDC peripheral state */
00632   hltdc->State = HAL_LTDC_STATE_BUSY;
00633
00634   /* Check the parameters */
00635   assert_param(IS_LTDC_LAYER(LayerIdx));
00636
00637   /* Disable LTDC color keying by setting COLKEN bit */
00638   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
00639
00640   /* Sets the Reload type */
00641   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00642
00643   /* Change the LTDC state*/
00644   hltdc->State = HAL_LTDC_STATE_READY;
00645
00646   /* Process unlocked */
00647   __HAL_UNLOCK(hltdc);
00648
00649   return HAL_OK;
00650 }
00651
00652 /**
00653   * @brief  Enable the color lookup table.
00654   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00655   *                   the configuration information for the LTDC.
00656   * @param  LayerIdx:  LTDC Layer index.
00657   *                   This parameter can be one of the following values:
00658   *                   0 or 1
00659   * @retval  HAL status
00660   */
00661 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00662 {
00663
00664   /* Process locked */
00665   __HAL_LOCK(hltdc);
00666
00667   /* Change LTDC peripheral state */
00668   hltdc->State = HAL_LTDC_STATE_BUSY;
00669
00670   /* Check the parameters */
00671   assert_param(IS_LTDC_LAYER(LayerIdx));
00672
00673   /* Disable LTDC color lookup table by setting CLUTEN bit */
00674   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
00675
00676   /* Sets the Reload type */
00677   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00678
00679   /* Change the LTDC state*/
00680   hltdc->State = HAL_LTDC_STATE_READY;
00681
00682   /* Process unlocked */
00683   __HAL_UNLOCK(hltdc);
00684
00685   return HAL_OK;
00686 }
00687
00688 /**
00689   * @brief  Disable the color lookup table.
00690   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00691   *                   the configuration information for the LTDC.
00692   * @param  LayerIdx:  LTDC Layer index.
00693   *                   This parameter can be one of the following values:
00694   *                   0 or 1
00695   * @retval  HAL status
00696   */
00697 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
00698 {
00699
00700   /* Process locked */
00701   __HAL_LOCK(hltdc);
00702
00703   /* Change LTDC peripheral state */
00704   hltdc->State = HAL_LTDC_STATE_BUSY;
00705
00706   /* Check the parameters */
00707   assert_param(IS_LTDC_LAYER(LayerIdx));
00708
00709   /* Disable LTDC color lookup table by setting CLUTEN bit */
00710   LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
00711
00712   /* Sets the Reload type */
00713   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00714
00715   /* Change the LTDC state*/
00716   hltdc->State = HAL_LTDC_STATE_READY;
00717
00718   /* Process unlocked */
00719   __HAL_UNLOCK(hltdc);
00720
00721   return HAL_OK;
00722 }
00723
00724 /**
00725   * @brief  Enables Dither.
00726   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00727   *                the configuration information for the LTDC.
00728   * @retval  HAL status
00729   */
00730
00731 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
00732 {
00733   /* Process locked */
00734   __HAL_LOCK(hltdc);
00735
00736   /* Change LTDC peripheral state */
00737   hltdc->State = HAL_LTDC_STATE_BUSY;
00738
00739   /* Enable Dither by setting DTEN bit */
00740   LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN;
00741
00742   /* Change the LTDC state*/
00743   hltdc->State = HAL_LTDC_STATE_READY;
00744
00745   /* Process unlocked */
00746   __HAL_UNLOCK(hltdc);
00747
00748   return HAL_OK;
00749 }
00750
00751 /**
00752   * @brief  Disables Dither.
00753   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00754   *                the configuration information for the LTDC.
00755   * @retval  HAL status
00756   */
00757
00758 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
00759 {
00760   /* Process locked */
00761   __HAL_LOCK(hltdc);
00762
00763   /* Change LTDC peripheral state */
00764   hltdc->State = HAL_LTDC_STATE_BUSY;
00765
00766   /* Disable Dither by setting DTEN bit */
00767   LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN;
00768
00769   /* Change the LTDC state*/
00770   hltdc->State = HAL_LTDC_STATE_READY;
00771
00772   /* Process unlocked */
00773   __HAL_UNLOCK(hltdc);
00774
00775   return HAL_OK;
00776 }
00777
00778 /**
00779   * @brief  Set the LTDC window size.
00780   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00781   *                   the configuration information for the LTDC.
00782   * @param  XSize:    LTDC Pixel per line
00783   * @param  YSize:    LTDC Line number
00784   * @param  LayerIdx:  LTDC Layer index.
00785   *                   This parameter can be one of the following values:
00786   *                   0 or 1
00787   * @retval  HAL status
00788   */
00789 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
00790 {
00791   LTDC_LayerCfgTypeDef *pLayerCfg;
00792
00793   /* Process locked */
00794   __HAL_LOCK(hltdc);
00795
00796   /* Change LTDC peripheral state */
00797   hltdc->State = HAL_LTDC_STATE_BUSY;
00798
00799   /* Get layer configuration from handle structure */
00800   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00801
00802   /* Check the parameters (Layers parameters)*/
00803   assert_param(IS_LTDC_LAYER(LayerIdx));
00804   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00805   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00806   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00807   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00808   assert_param(IS_LTDC_CFBLL(XSize));
00809   assert_param(IS_LTDC_CFBLNBR(YSize));
00810
00811   /* update horizontal start/stop */
00812   pLayerCfg->WindowX0 = 0U;
00813   pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
00814
00815   /* update vertical start/stop */
00816   pLayerCfg->WindowY0 = 0U;
00817   pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
00818
00819   /* Reconfigures the color frame buffer pitch in byte */
00820   pLayerCfg->ImageWidth = XSize;
00821
00822   /* Reconfigures the frame buffer line number */
00823   pLayerCfg->ImageHeight = YSize;
00824
00825   /* Set LTDC parameters */
00826   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00827
00828   /* Sets the Reload type */
00829   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00830
00831   /* Change the LTDC state*/
00832   hltdc->State = HAL_LTDC_STATE_READY;
00833
00834   /* Process unlocked */
00835   __HAL_UNLOCK(hltdc);
00836
00837   return HAL_OK;
00838 }
00839
00840 /**
00841   * @brief  Set the LTDC window position.
00842   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00843   *                   the configuration information for the LTDC.
00844   * @param  X0:       LTDC window X offset
00845   * @param  Y0:       LTDC window Y offset
00846   * @param  LayerIdx:  LTDC Layer index.
00847   *                         This parameter can be one of the following values:
00848   *                         0 or 1
00849   * @retval  HAL status
00850   */
00851 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
00852 {
00853   LTDC_LayerCfgTypeDef *pLayerCfg;
00854
00855   /* Process locked */
00856   __HAL_LOCK(hltdc);
00857
00858   /* Change LTDC peripheral state */
00859   hltdc->State = HAL_LTDC_STATE_BUSY;
00860
00861   /* Get layer configuration from handle structure */
00862   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00863
00864   /* Check the parameters */
00865   assert_param(IS_LTDC_LAYER(LayerIdx));
00866   assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
00867   assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
00868   assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
00869   assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
00870
00871   /* update horizontal start/stop */
00872   pLayerCfg->WindowX0 = X0;
00873   pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
00874
00875   /* update vertical start/stop */
00876   pLayerCfg->WindowY0 = Y0;
00877   pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
00878
00879   /* Set LTDC parameters */
00880   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00881
00882   /* Sets the Reload type */
00883   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00884
00885   /* Change the LTDC state*/
00886   hltdc->State = HAL_LTDC_STATE_READY;
00887
00888   /* Process unlocked */
00889   __HAL_UNLOCK(hltdc);
00890
00891   return HAL_OK;
00892 }
00893
00894 /**
00895   * @brief  Reconfigure the pixel format.
00896   * @param  hltdc:       pointer to a LTDC_HandleTypeDef structure that contains
00897   *                      the configuration information for the LTDC.
00898   * @param  Pixelformat: new pixel format value.
00899   * @param  LayerIdx:    LTDC Layer index.
00900   *                      This parameter can be one of the following values:
00901   *                      0 or 1.
00902   * @retval  HAL status
00903   */
00904 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
00905 {
00906   LTDC_LayerCfgTypeDef *pLayerCfg;
00907
00908   /* Process locked */
00909   __HAL_LOCK(hltdc);
00910
00911   /* Change LTDC peripheral state */
00912   hltdc->State = HAL_LTDC_STATE_BUSY;
00913
00914   /* Check the parameters */
00915   assert_param(IS_LTDC_LAYER(LayerIdx));
00916   assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
00917
00918   /* Get layer configuration from handle structure */
00919   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00920
00921   /* Reconfigure the pixel format */
00922   pLayerCfg->PixelFormat = Pixelformat;
00923
00924   /* Set LTDC parameters */
00925   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00926
00927   /* Sets the Reload type */
00928   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00929
00930   /* Change the LTDC state*/
00931   hltdc->State = HAL_LTDC_STATE_READY;
00932
00933   /* Process unlocked */
00934   __HAL_UNLOCK(hltdc);
00935
00936   return HAL_OK;
00937 }
00938
00939 /**
00940   * @brief  Reconfigure the layer alpha value.
00941   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00942   *                   the configuration information for the LTDC.
00943   * @param  Alpha:    new alpha value.
00944   * @param  LayerIdx:  LTDC Layer index.
00945   *                   This parameter can be one of the following values:
00946   *                   0 or 1
00947   * @retval  HAL status
00948   */
00949 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
00950 {
00951   LTDC_LayerCfgTypeDef *pLayerCfg;
00952
00953   /* Process locked */
00954   __HAL_LOCK(hltdc);
00955
00956   /* Change LTDC peripheral state */
00957   hltdc->State = HAL_LTDC_STATE_BUSY;
00958
00959   /* Check the parameters */
00960   assert_param(IS_LTDC_ALPHA(Alpha));
00961   assert_param(IS_LTDC_LAYER(LayerIdx));
00962
00963   /* Get layer configuration from handle structure */
00964   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
00965
00966   /* Reconfigure the Alpha value */
00967   pLayerCfg->Alpha = Alpha;
00968
00969   /* Set LTDC parameters */
00970   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
00971
00972   /* Sets the Reload type */
00973   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
00974
00975   /* Change the LTDC state*/
00976   hltdc->State = HAL_LTDC_STATE_READY;
00977
00978   /* Process unlocked */
00979   __HAL_UNLOCK(hltdc);
00980
00981   return HAL_OK;
00982 }
00983 /**
00984   * @brief  Reconfigure the frame buffer Address.
00985   * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
00986   *                   the configuration information for the LTDC.
00987   * @param  Address:  new address value.
00988   * @param  LayerIdx: LTDC Layer index.
00989   *                   This parameter can be one of the following values:
00990   *                   0 or 1.
00991   * @retval  HAL status
00992   */
00993 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
00994 {
00995   LTDC_LayerCfgTypeDef *pLayerCfg;
00996
00997   /* Process locked */
00998   __HAL_LOCK(hltdc);
00999
01000   /* Change LTDC peripheral state */
01001   hltdc->State = HAL_LTDC_STATE_BUSY;
01002
01003   /* Check the parameters */
01004   assert_param(IS_LTDC_LAYER(LayerIdx));
01005
01006   /* Get layer configuration from handle structure */
01007   pLayerCfg = &hltdc->LayerCfg[LayerIdx];
01008
01009   /* Reconfigure the Address */
01010   pLayerCfg->FBStartAdress = Address;
01011
01012   /* Set LTDC parameters */
01013   LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
01014
01015   /* Sets the Reload type */
01016   hltdc->Instance->SRCR = LTDC_SRCR_IMR;
01017
01018   /* Change the LTDC state*/
01019   hltdc->State = HAL_LTDC_STATE_READY;
01020
01021   /* Process unlocked */
01022   __HAL_UNLOCK(hltdc);
01023
01024   return HAL_OK;
01025 }
01026
01027 /**
01028   * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
01029   *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
01030   *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
01031   *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
01032   *         Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
01033   *                configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
01034   * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains
01035   *                            the configuration information for the LTDC.
01036   * @param  LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
01037   * @param  LayerIdx:          LTDC layer index concerned by the modification of line pitch.
01038   * @retval HAL status
01039   */
01040 HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
01041 {
01042   uint32_t tmp = 0U;
01043   uint32_t pitchUpdate = 0U;
01044   uint32_t pixelFormat = 0U;
01045
01046   /* Process locked */
01047   __HAL_LOCK(hltdc);
01048
01049   /* Change LTDC peripheral state */
01050   hltdc->State = HAL_LTDC_STATE_BUSY;
01051
01052   /* Check the parameters */
01053   assert_param(IS_LTDC_LAYER(LayerIdx));
01054
01055   /* get LayerIdx used pixel format */
01056   pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
01057
01058   if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01059   {
01060     tmp = 4U;
01061   }
01062   else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01063   {
01064     tmp = 3U;
01065   }
01066   else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01067           (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01068           (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01069          (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
01070   {
01071     tmp = 2U;
01072   }
01073   else
01074   {
01075     tmp = 1U;
01076   }
01077
01078   pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
01079
01080   /* Clear previously set standard pitch */
01081   LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
01082
01083   /* Sets the Reload type as immediate update of LTDC pitch configured above */
01084   LTDC->SRCR |= LTDC_SRCR_IMR;
01085
01086   /* Set new line pitch value */
01087   LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
01088
01089   /* Sets the Reload type as immediate update of LTDC pitch configured above */
01090   LTDC->SRCR |= LTDC_SRCR_IMR;
01091
01092   /* Change the LTDC state*/
01093   hltdc->State = HAL_LTDC_STATE_READY;
01094
01095   /* Process unlocked */
01096   __HAL_UNLOCK(hltdc);
01097
01098   return HAL_OK;
01099 }
01100
01101 /**
01102   * @brief  Define the position of the line interrupt .
01103   * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains
01104   *                            the configuration information for the LTDC.
01105   * @param  Line:   Line Interrupt Position.
01106   * @retval  HAL status
01107   */
01108 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
01109 {
01110   /* Process locked */
01111   __HAL_LOCK(hltdc);
01112
01113   /* Change LTDC peripheral state */
01114   hltdc->State = HAL_LTDC_STATE_BUSY;
01115
01116   /* Check the parameters */
01117   assert_param(IS_LTDC_LIPOS(Line));
01118
01119   /* Enable the Line interrupt */
01120   __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
01121
01122   /* Sets the Line Interrupt position */
01123   LTDC->LIPCR = (uint32_t)Line;
01124
01125   /* Change the LTDC state*/
01126   hltdc->State = HAL_LTDC_STATE_READY;
01127
01128   /* Process unlocked */
01129   __HAL_UNLOCK(hltdc);
01130
01131   return HAL_OK;
01132 }
01133
01134 /**
01135   * @}
01136   */
01137
01138 /** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
01139  *  @brief    Peripheral State and Errors functions
01140  *
01141 @verbatim
01142  ===============================================================================
01143                   ##### Peripheral State and Errors functions #####
01144  ===============================================================================
01145     [..]
01146     This subsection provides functions allowing to
01147       (+) Check the LTDC state.
01148       (+) Get error code.
01149
01150 @endverbatim
01151   * @{
01152   */
01153
01154 /**
01155   * @brief  Return the LTDC state
01156   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
01157   *                the configuration information for the LTDC.
01158   * @retval HAL state
01159   */
01160 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
01161 {
01162   return hltdc->State;
01163 }
01164
01165 /**
01166 * @brief  Return the LTDC error code
01167 * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
01168   *               the configuration information for the LTDC.
01169 * @retval LTDC Error Code
01170 */
01171 uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
01172 {
01173   return hltdc->ErrorCode;
01174 }
01175
01176 /**
01177   * @}
01178   */
01179
01180 /**
01181   * @brief  Configures the LTDC peripheral
01182   * @param  hltdc   :  Pointer to a LTDC_HandleTypeDef structure that contains
01183   *                   the configuration information for the LTDC.
01184   * @param  pLayerCfg: Pointer LTDC Layer Configuration structure
01185   * @param  LayerIdx:  LTDC Layer index.
01186   *                    This parameter can be one of the following values: 0 or 1
01187   * @retval None
01188   */
01189 static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
01190 {
01191   uint32_t tmp = 0U;
01192   uint32_t tmp1 = 0U;
01193   uint32_t tmp2 = 0U;
01194
01195   /* Configures the horizontal start and stop position */
01196   tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
01197   LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
01198   LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
01199
01200   /* Configures the vertical start and stop position */
01201   tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
01202   LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
01203   LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
01204
01205   /* Specifies the pixel format */
01206   LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
01207   LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
01208
01209   /* Configures the default color values */
01210   tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
01211   tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
01212   tmp2 = (pLayerCfg->Alpha0 << 24U);
01213   LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
01214   LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
01215
01216   /* Specifies the constant alpha value */
01217   LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
01218   LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
01219
01220   /* Specifies the blending factors */
01221   LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
01222   LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
01223
01224   /* Configures the color frame buffer start address */
01225   LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
01226   LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
01227
01228   if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
01229   {
01230     tmp = 4U;
01231   }
01232   else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
01233   {
01234     tmp = 3U;
01235   }
01236   else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
01237     (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
01238       (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
01239         (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
01240   {
01241     tmp = 2U;
01242   }
01243   else
01244   {
01245     tmp = 1U;
01246   }
01247
01248   /* Configures the color frame buffer pitch in byte */
01249   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
01250   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 3U));
01251
01252   /* Configures the frame buffer line number */
01253   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);
01254   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);
01255
01256   /* Enable LTDC_Layer by setting LEN bit */
01257   LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
01258 }
01259
01260 /**
01261   * @}
01262   */
01263 #endif /* STM32F429xx || STM32F439xx  || STM32F469xx || STM32F479xx */
01264 #endif /* HAL_LTDC_MODULE_ENABLED */
01265 /**
01266   * @}
01267   */
01268
01269 /**
01270   * @}
01271   */
01272
01273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc.h Source File

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stm32f4xx_hal_ltdc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_ltdc.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of LTDC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_LTDC_H
00040 #define __STM32F4xx_HAL_LTDC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @defgroup LTDC LTDC
00055   * @brief LTDC HAL module driver
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup LTDC_Exported_Types LTDC Exported Types
00061   * @{
00062   */
00063 #define MAX_LAYER  2
00064
00065 /**
00066   * @brief  LTDC color structure definition
00067   */
00068 typedef struct
00069 {
00070   uint8_t Blue;                    /*!< Configures the blue value.
00071                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00072
00073   uint8_t Green;                   /*!< Configures the green value.
00074                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00075
00076   uint8_t Red;                     /*!< Configures the red value.
00077                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00078
00079   uint8_t Reserved;                /*!< Reserved 0xFF */
00080 } LTDC_ColorTypeDef;
00081
00082 /**
00083   * @brief  LTDC Init structure definition
00084   */
00085 typedef struct
00086 {
00087   uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.
00088                                                       This parameter can be one value of @ref LTDC_HS_POLARITY */
00089
00090   uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.
00091                                                       This parameter can be one value of @ref LTDC_VS_POLARITY */
00092
00093   uint32_t            DEPolarity;                /*!< configures the data enable polarity.
00094                                                       This parameter can be one of value of @ref LTDC_DE_POLARITY */
00095
00096   uint32_t            PCPolarity;                /*!< configures the pixel clock polarity.
00097                                                       This parameter can be one of value of @ref LTDC_PC_POLARITY */
00098
00099   uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
00100                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00101
00102   uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.
00103                                                       This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00104
00105   uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
00106                                                       This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
00107
00108   uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.
00109                                                       This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
00110
00111   uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.
00112                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
00113
00114   uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.
00115                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
00116
00117   uint32_t            TotalWidth;                /*!< configures the total width.
00118                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
00119
00120   uint32_t            TotalHeigh;                /*!< configures the total height.
00121                                                       This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
00122
00123   LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
00124 } LTDC_InitTypeDef;
00125
00126 /**
00127   * @brief  LTDC Layer structure definition
00128   */
00129 typedef struct
00130 {
00131   uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
00132                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00133
00134   uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
00135                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00136
00137   uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
00138                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00139
00140   uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
00141                                             This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
00142
00143   uint32_t PixelFormat;                /*!< Specifies the pixel format.
00144                                             This parameter can be one of value of @ref LTDC_Pixelformat */
00145
00146   uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
00147                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00148
00149   uint32_t Alpha0;                     /*!< Configures the default alpha value.
00150                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
00151
00152   uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
00153                                             This parameter can be one of value of @ref LTDC_BlendingFactor1 */
00154
00155   uint32_t BlendingFactor2;            /*!< Select the blending factor 2.
00156                                             This parameter can be one of value of @ref LTDC_BlendingFactor2 */
00157
00158   uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
00159
00160   uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
00161                                             This parameter must be a number between Min_Data = 0x0000U and Max_Data = 0x1FFF. */
00162
00163   uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
00164                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
00165
00166   LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
00167 } LTDC_LayerCfgTypeDef;
00168
00169 /**
00170   * @brief  HAL LTDC State structures definition
00171   */
00172 typedef enum
00173 {
00174   HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */
00175   HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */
00176   HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */
00177   HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */
00178   HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */
00179 }HAL_LTDC_StateTypeDef;
00180
00181 /**
00182   * @brief  LTDC handle Structure definition
00183   */
00184 typedef struct
00185 {
00186   LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
00187
00188   LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
00189
00190   LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
00191
00192   HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
00193
00194   __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
00195
00196   __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
00197
00198 } LTDC_HandleTypeDef;
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported constants --------------------------------------------------------*/
00204 /** @defgroup LTDC_Exported_Constants LTDC Exported Constants
00205   * @{
00206   */
00207
00208 /** @defgroup LTDC_Error_Code LTDC Error Code
00209   * @{
00210   */
00211 #define HAL_LTDC_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< LTDC No error             */
00212 #define HAL_LTDC_ERROR_TE        ((uint32_t)0x00000001U)    /*!< LTDC Transfer error       */
00213 #define HAL_LTDC_ERROR_FU        ((uint32_t)0x00000002U)    /*!< LTDC FIFO Underrun        */
00214 #define HAL_LTDC_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< LTDC Timeout error        */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
00220   * @{
00221   */
00222 #define LTDC_HSPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Horizontal Synchronization is active low. */
00223 #define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL                        /*!< Horizontal Synchronization is active high. */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
00229   * @{
00230   */
00231 #define LTDC_VSPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Vertical Synchronization is active low. */
00232 #define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL                        /*!< Vertical Synchronization is active high. */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
00238   * @{
00239   */
00240 #define LTDC_DEPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Data Enable, is active low. */
00241 #define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL                        /*!< Data Enable, is active high. */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
00247   * @{
00248   */
00249 #define LTDC_PCPOLARITY_IPC               ((uint32_t)0x00000000U)                /*!< input pixel clock. */
00250 #define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL                        /*!< inverted input pixel clock. */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup LTDC_SYNC LTDC SYNC
00256   * @{
00257   */
00258 #define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16U)                 /*!< Horizontal synchronization width. */
00259 #define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH                         /*!< Vertical synchronization height. */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
00265   * @{
00266   */
00267 #define LTDC_COLOR                   ((uint32_t)0x000000FFU)                     /*!< Color mask */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
00273   * @{
00274   */
00275 #define LTDC_BLENDING_FACTOR1_CA                       ((uint32_t)0x00000400U)   /*!< Blending factor : Cte Alpha */
00276 #define LTDC_BLENDING_FACTOR1_PAxCA                    ((uint32_t)0x00000600U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
00282   * @{
00283   */
00284 #define LTDC_BLENDING_FACTOR2_CA                       ((uint32_t)0x00000005U)   /*!< Blending factor : Cte Alpha */
00285 #define LTDC_BLENDING_FACTOR2_PAxCA                    ((uint32_t)0x00000007U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup LTDC_Pixelformat LTDC Pixel format
00291   * @{
00292   */
00293 #define LTDC_PIXEL_FORMAT_ARGB8888                  ((uint32_t)0x00000000U)      /*!< ARGB8888 LTDC pixel format */
00294 #define LTDC_PIXEL_FORMAT_RGB888                    ((uint32_t)0x00000001U)      /*!< RGB888 LTDC pixel format   */
00295 #define LTDC_PIXEL_FORMAT_RGB565                    ((uint32_t)0x00000002U)      /*!< RGB565 LTDC pixel format   */
00296 #define LTDC_PIXEL_FORMAT_ARGB1555                  ((uint32_t)0x00000003U)      /*!< ARGB1555 LTDC pixel format */
00297 #define LTDC_PIXEL_FORMAT_ARGB4444                  ((uint32_t)0x00000004U)      /*!< ARGB4444 LTDC pixel format */
00298 #define LTDC_PIXEL_FORMAT_L8                        ((uint32_t)0x00000005U)      /*!< L8 LTDC pixel format       */
00299 #define LTDC_PIXEL_FORMAT_AL44                      ((uint32_t)0x00000006U)      /*!< AL44 LTDC pixel format     */
00300 #define LTDC_PIXEL_FORMAT_AL88                      ((uint32_t)0x00000007U)      /*!< AL88 LTDC pixel format     */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup LTDC_Alpha LTDC Alpha
00306   * @{
00307   */
00308 #define LTDC_ALPHA               LTDC_LxCACR_CONSTA                             /*!< LTDC Cte Alpha mask */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup LTDC_LAYER_Config LTDC LAYER Config
00314   * @{
00315   */
00316 #define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16U)          /*!< LTDC Layer stop position  */
00317 #define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS                  /*!< LTDC Layer start position */
00318
00319 #define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL                    /*!< LTDC Layer Line length    */
00320 #define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR                 /*!< LTDC Layer Line number    */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup LTDC_Interrupts LTDC Interrupts
00326   * @{
00327   */
00328 #define LTDC_IT_LI                      LTDC_IER_LIE
00329 #define LTDC_IT_FU                      LTDC_IER_FUIE
00330 #define LTDC_IT_TE                      LTDC_IER_TERRIE
00331 #define LTDC_IT_RR                      LTDC_IER_RRIE
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup LTDC_Flag LTDC Flag
00337   * @{
00338   */
00339 #define LTDC_FLAG_LI                     LTDC_ISR_LIF
00340 #define LTDC_FLAG_FU                     LTDC_ISR_FUIF
00341 #define LTDC_FLAG_TE                     LTDC_ISR_TERRIF
00342 #define LTDC_FLAG_RR                     LTDC_ISR_RRIF
00343 /**
00344   * @}
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /* Exported macro ------------------------------------------------------------*/
00352 /** @defgroup LTDC_Exported_Macros LTDC Exported Macros
00353   * @{
00354   */
00355
00356 /** @brief Reset LTDC handle state
00357   * @param  __HANDLE__: specifies the LTDC handle.
00358   * @retval None
00359   */
00360 #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
00361
00362 /**
00363   * @brief  Enable the LTDC.
00364   * @param  __HANDLE__: LTDC handle
00365   * @retval None.
00366   */
00367 #define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
00368
00369 /**
00370   * @brief  Disable the LTDC.
00371   * @param  __HANDLE__: LTDC handle
00372   * @retval None.
00373   */
00374 #define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
00375
00376 /**
00377   * @brief  Enable the LTDC Layer.
00378   * @param  __HANDLE__: LTDC handle
00379   * @param  __LAYER__: Specify the layer to be enabled
00380   *                     This parameter can be 0 or 1
00381   * @retval None.
00382   */
00383 #define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
00384
00385 /**
00386   * @brief  Disable the LTDC Layer.
00387   * @param  __HANDLE__: LTDC handle
00388   * @param  __LAYER__: Specify the layer to be disabled
00389   *                     This parameter can be 0 or 1
00390   * @retval None.
00391   */
00392 #define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
00393
00394 /**
00395   * @brief  Reload  Layer Configuration.
00396   * @param  __HANDLE__: LTDC handle
00397   * @retval None.
00398   */
00399 #define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__)   ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
00400
00401 /* Interrupt & Flag management */
00402 /**
00403   * @brief  Get the LTDC pending flags.
00404   * @param  __HANDLE__: LTDC handle
00405   * @param  __FLAG__: Get the specified flag.
00406   *          This parameter can be any combination of the following values:
00407   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00408   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00409   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00410   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00411   * @retval The state of FLAG (SET or RESET).
00412   */
00413 #define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
00414
00415 /**
00416   * @brief  Clears the LTDC pending flags.
00417   * @param  __HANDLE__: LTDC handle
00418   * @param  __FLAG__: specifies the flag to clear.
00419   *          This parameter can be any combination of the following values:
00420   *            @arg LTDC_FLAG_LI: Line Interrupt flag
00421   *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
00422   *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
00423   *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
00424   * @retval None
00425   */
00426 #define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00427
00428 /**
00429   * @brief  Enables the specified LTDC interrupts.
00430   * @param  __HANDLE__: LTDC handle
00431   * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
00432   *          This parameter can be any combination of the following values:
00433   *            @arg LTDC_IT_LI: Line Interrupt flag
00434   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00435   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00436   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00437   * @retval None
00438   */
00439 #define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00440
00441 /**
00442   * @brief  Disables the specified LTDC interrupts.
00443   * @param  __HANDLE__: LTDC handle
00444   * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
00445   *          This parameter can be any combination of the following values:
00446   *            @arg LTDC_IT_LI: Line Interrupt flag
00447   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00448   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00449   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00450   * @retval None
00451   */
00452 #define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
00453
00454 /**
00455   * @brief  Checks whether the specified LTDC interrupt has occurred or not.
00456   * @param  __HANDLE__: LTDC handle
00457   * @param  __INTERRUPT__: specifies the LTDC interrupt source to check.
00458   *          This parameter can be one of the following values:
00459   *            @arg LTDC_IT_LI: Line Interrupt flag
00460   *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
00461   *            @arg LTDC_IT_TE: Transfer Error interrupt flag
00462   *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
00463   * @retval The state of INTERRUPT (SET or RESET).
00464   */
00465 #define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
00466 /**
00467   * @}
00468   */
00469
00470 /* Include LTDC HAL Extension module */
00471 #include "stm32f4xx_hal_ltdc_ex.h"
00472
00473 /* Exported functions --------------------------------------------------------*/
00474 /** @addtogroup LTDC_Exported_Functions
00475   * @{
00476   */
00477 /** @addtogroup LTDC_Exported_Functions_Group1
00478   * @{
00479   */
00480 /* Initialization and de-initialization functions *****************************/
00481 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
00482 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
00483 void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
00484 void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
00485 void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
00486 void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
00487 /**
00488   * @}
00489   */
00490
00491 /** @addtogroup LTDC_Exported_Functions_Group2
00492   * @{
00493   */
00494 /* IO operation functions *****************************************************/
00495 void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
00496 /**
00497   * @}
00498   */
00499
00500 /** @addtogroup LTDC_Exported_Functions_Group3
00501   * @{
00502   */
00503 /* Peripheral Control functions ***********************************************/
00504 HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
00505 HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
00506 HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
00507 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
00508 HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
00509 HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
00510 HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
00511 HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
00512 HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
00513 HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00514 HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00515 HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00516 HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
00517 HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
00518 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
00519 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
00520 /**
00521   * @}
00522   */
00523
00524 /** @addtogroup LTDC_Exported_Functions_Group4
00525   * @{
00526   */
00527 /* Peripheral State functions *************************************************/
00528 HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
00529 uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
00530 /**
00531   * @}
00532   */
00533
00534 /**
00535   * @}
00536   */
00537 /* Private types -------------------------------------------------------------*/
00538 /** @defgroup LTDC_Private_Types LTDC Private Types
00539   * @{
00540   */
00541
00542 /**
00543   * @}
00544   */
00545
00546 /* Private variables ---------------------------------------------------------*/
00547 /** @defgroup LTDC_Private_Variables LTDC Private Variables
00548   * @{
00549   */
00550
00551 /**
00552   * @}
00553   */
00554
00555 /* Private constants ---------------------------------------------------------*/
00556 /** @defgroup LTDC_Private_Constants LTDC Private Constants
00557   * @{
00558   */
00559
00560 /**
00561   * @}
00562   */
00563
00564 /* Private macros ------------------------------------------------------------*/
00565 /** @defgroup LTDC_Private_Macros LTDC Private Macros
00566   * @{
00567   */
00568 #define LTDC_LAYER(__HANDLE__, __LAYER__)         ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U * (__LAYER__)))))
00569 #define IS_LTDC_LAYER(LAYER)                      ((LAYER) <= MAX_LAYER)
00570 #define IS_LTDC_HSPOL(HSPOL)                      (((HSPOL) == LTDC_HSPOLARITY_AL) || \
00571                                                    ((HSPOL) == LTDC_HSPOLARITY_AH))
00572 #define IS_LTDC_VSPOL(VSPOL)                      (((VSPOL) == LTDC_VSPOLARITY_AL) || \
00573                                                    ((VSPOL) == LTDC_VSPOLARITY_AH))
00574 #define IS_LTDC_DEPOL(DEPOL)                      (((DEPOL) ==  LTDC_DEPOLARITY_AL) || \
00575                                                    ((DEPOL) ==  LTDC_DEPOLARITY_AH))
00576 #define IS_LTDC_PCPOL(PCPOL)                      (((PCPOL) ==  LTDC_PCPOLARITY_IPC) || \
00577                                                    ((PCPOL) ==  LTDC_PCPOLARITY_IIPC))
00578 #define IS_LTDC_HSYNC(HSYNC)                      ((HSYNC)  <= LTDC_HORIZONTALSYNC)
00579 #define IS_LTDC_VSYNC(VSYNC)                      ((VSYNC)  <= LTDC_VERTICALSYNC)
00580 #define IS_LTDC_AHBP(AHBP)                        ((AHBP)   <= LTDC_HORIZONTALSYNC)
00581 #define IS_LTDC_AVBP(AVBP)                        ((AVBP)   <= LTDC_VERTICALSYNC)
00582 #define IS_LTDC_AAW(AAW)                          ((AAW)    <= LTDC_HORIZONTALSYNC)
00583 #define IS_LTDC_AAH(AAH)                          ((AAH)    <= LTDC_VERTICALSYNC)
00584 #define IS_LTDC_TOTALW(TOTALW)                    ((TOTALW) <= LTDC_HORIZONTALSYNC)
00585 #define IS_LTDC_TOTALH(TOTALH)                    ((TOTALH) <= LTDC_VERTICALSYNC)
00586 #define IS_LTDC_BLUEVALUE(BBLUE)                  ((BBLUE)  <= LTDC_COLOR)
00587 #define IS_LTDC_GREENVALUE(BGREEN)                ((BGREEN) <= LTDC_COLOR)
00588 #define IS_LTDC_REDVALUE(BRED)                    ((BRED)   <= LTDC_COLOR)
00589 #define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
00590                                                    ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
00591 #define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
00592                                                    ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
00593 #define IS_LTDC_PIXEL_FORMAT(Pixelformat)         (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888)   || \
00594                                                    ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565)   || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
00595                                                    ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8)       || \
00596                                                    ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44)     || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
00597 #define IS_LTDC_ALPHA(ALPHA)                      ((ALPHA) <= LTDC_ALPHA)
00598 #define IS_LTDC_HCONFIGST(HCONFIGST)              ((HCONFIGST) <= LTDC_STARTPOSITION)
00599 #define IS_LTDC_HCONFIGSP(HCONFIGSP)              ((HCONFIGSP) <= LTDC_STOPPOSITION)
00600 #define IS_LTDC_VCONFIGST(VCONFIGST)              ((VCONFIGST) <= LTDC_STARTPOSITION)
00601 #define IS_LTDC_VCONFIGSP(VCONFIGSP)              ((VCONFIGSP) <= LTDC_STOPPOSITION)
00602 #define IS_LTDC_CFBP(CFBP)                        ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
00603 #define IS_LTDC_CFBLL(CFBLL)                      ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
00604 #define IS_LTDC_CFBLNBR(CFBLNBR)                  ((CFBLNBR) <= LTDC_LINE_NUMBER)
00605 #define IS_LTDC_LIPOS(LIPOS)                      ((LIPOS) <= 0x7FFU)
00606 /**
00607   * @}
00608   */
00609
00610 /* Private functions ---------------------------------------------------------*/
00611 /** @defgroup LTDC_Private_Functions LTDC Private Functions
00612   * @{
00613   */
00614
00615 /**
00616   * @}
00617   */
00618
00619 /**
00620   * @}
00621   */
00622
00623 /**
00624   * @}
00625   */
00626
00627 #endif /* STM32F429xx || STM32F439xx  || STM32F469xx || STM32F479xx */
00628
00629 #ifdef __cplusplus
00630 }
00631 #endif
00632
00633 #endif /* __STM32F4xx_HAL_LTDC_H */
00634
00635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc_ex.c Source File

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stm32f4xx_hal_ltdc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_ltdc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   LTDC Extension HAL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Includes ------------------------------------------------------------------*/
00039 #include "stm32f4xx_hal.h"
00040
00041 /** @addtogroup STM32F4xx_HAL_Driver
00042   * @{
00043   */
00044 /** @defgroup LTDCEx LTDCEx
00045   * @brief LTDC HAL module driver
00046   * @{
00047   */
00048
00049 #ifdef HAL_LTDC_MODULE_ENABLED
00050
00051 /* Private typedef -----------------------------------------------------------*/
00052 /* Private define ------------------------------------------------------------*/
00053 /* Private macro -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055 /* Private function prototypes -----------------------------------------------*/
00056 /* Exported functions --------------------------------------------------------*/
00057
00058 /** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
00059   * @{
00060   */
00061
00062 /** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
00063  *  @brief   Initialization and Configuration functions
00064  *
00065 @verbatim
00066  ===============================================================================
00067                 ##### Initialization and Configuration functions #####
00068  ===============================================================================
00069     [..]  This section provides functions allowing to:
00070       (+) Initialize and configure the LTDC
00071
00072 @endverbatim
00073   * @{
00074   */
00075 #if defined(STM32F469xx) || defined(STM32F479xx)
00076 /**
00077   * @brief  Retrieve common parameters from DSI Video mode configuration structure
00078   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00079   *                the configuration information for the LTDC.
00080   * @param  VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
00081   *                 the DSI video mode configuration parameters
00082   * @note   The implementation of this function is taking into account the LTDC
00083   *         polarities inversion as described in the current LTDC specification
00084   * @retval HAL status
00085   */
00086 HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)
00087 {
00088   /* Retrieve signal polarities from DSI */
00089
00090   /* The following polarities are inverted:
00091                      LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
00092                            LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
00093                            LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
00094
00095   /* Note 1 : Code in line w/ Current LTDC specification */
00096   hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
00097   hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
00098   hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
00099
00100   /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
00101   /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
00102      hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
00103      hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
00104
00105   /* Retrieve vertical timing parameters from DSI */
00106   hltdc->Init.VerticalSync       = VidCfg->VerticalSyncActive - 1U;
00107   hltdc->Init.AccumulatedVBP     = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
00108   hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
00109   hltdc->Init.TotalHeigh         = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
00110
00111   return HAL_OK;
00112 }
00113
00114 /**
00115   * @brief  Retrieve common parameters from DSI Adapted command mode configuration structure
00116   * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
00117   *                the configuration information for the LTDC.
00118   * @param  CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
00119   *                 the DSI command mode configuration parameters
00120   * @note   The implementation of this function is taking into account the LTDC
00121   *         polarities inversion as described in the current LTDC specification
00122   * @retval HAL status
00123   */
00124 HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)
00125 {
00126   /* Retrieve signal polarities from DSI */
00127
00128   /* The following polarities are inverted:
00129                      LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
00130                            LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
00131                            LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
00132
00133   /* Note 1 : Code in line w/ Current LTDC specification */
00134   hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
00135   hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
00136   hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
00137
00138   /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
00139   /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
00140      hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
00141      hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
00142
00143   return HAL_OK;
00144 }
00145 #endif /* STM32F469xx || STM32F479xx */
00146
00147 /**
00148   * @}
00149   */
00150
00151 /**
00152   * @}
00153   */
00154
00155 #endif /* HAL_DCMI_MODULE_ENABLED */
00156 /**
00157   * @}
00158   */
00159
00160 /**
00161   * @}
00162   */
00163
00164 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_ltdc_ex.h Source File

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stm32f4xx_hal_ltdc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_ltdc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of LTDC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_LTDC_EX_H
00040 #define __STM32F4xx_HAL_LTDC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F469xx) || defined(STM32F479xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049 #include "stm32f4xx_hal_dsi.h"
00050
00051 /** @addtogroup STM32F4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup LTDCEx
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /* Exported constants --------------------------------------------------------*/
00061
00062 /** @defgroup LTDCEx_Exported_Constants   LTDCEx Exported Constants
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070 /* Exported macro ------------------------------------------------------------*/
00071 /** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros
00072   * @{
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported functions --------------------------------------------------------*/
00080 /** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
00081   * @{
00082   */
00083 HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);
00084 HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);
00085 /**
00086   * @}
00087   */
00088
00089
00090  /* Private types -------------------------------------------------------------*/
00091 /** @defgroup LTDCEx_Private_Types LTDCEx Private Types
00092   * @{
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Private variables ---------------------------------------------------------*/
00100 /** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables
00101   * @{
00102   */
00103
00104 /**
00105   * @}
00106   */
00107
00108 /* Private constants ---------------------------------------------------------*/
00109 /** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants
00110   * @{
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Private macros ------------------------------------------------------------*/
00118 /** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros
00119   * @{
00120   */
00121
00122  /**
00123   * @}
00124   */
00125
00126 /* Private functions ---------------------------------------------------------*/
00127 /** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions
00128   * @{
00129   */
00130
00131 /**
00132   * @}
00133   */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 #endif /* STM32F469xx || STM32F479xx */
00144
00145 #ifdef __cplusplus
00146 }
00147 #endif
00148
00149 #endif /* __STM32F4xx_HAL_LTDC_EX_H */
00150
00151 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_nand.c Source File

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stm32f4xx_hal_nand.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   NAND HAL module driver.
00008   *          This file provides a generic firmware to drive NAND memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                          ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NAND flash memories. It uses the FMC/FSMC layer functions to interface
00018       with NAND devices. This driver is used as follows:
00019
00020       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00021           with control and timing parameters for both common and attribute spaces.
00022
00023       (+) Read NAND flash memory maker and device IDs using the function
00024           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NAND flash memory by read/write operations using the functions
00028           HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
00029           to read/write page(s)/spare area(s). These functions use specific device
00030           information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
00031           structure. The read/write address information is contained by the Nand_Address_Typedef
00032           structure passed as parameter.
00033
00034       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00035
00036       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00037           The erase block address information is contained in the Nand_Address_Typedef
00038           structure passed as parameter.
00039
00040       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00041
00042       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00043           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00044           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00045
00046       (+) You can monitor the NAND device HAL state by calling the function
00047           HAL_NAND_GetState()
00048
00049     [..]
00050       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00051           If a NAND flash device contains different operations and/or implementations,
00052           it should be implemented separately.
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32f4xx_hal.h"
00087
00088 /** @addtogroup STM32F4xx_HAL_Driver
00089   * @{
00090   */
00091
00092
00093 #ifdef HAL_NAND_MODULE_ENABLED
00094
00095 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00096     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00097     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00098
00099 /** @defgroup NAND NAND
00100   * @brief NAND HAL module driver
00101   * @{
00102   */
00103
00104 /* Private typedef -----------------------------------------------------------*/
00105 /* Private define ------------------------------------------------------------*/
00106 /** @defgroup NAND_Private_Constants NAND Private Constants
00107   * @{
00108   */
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Private macro -------------------------------------------------------------*/
00115 /** @defgroup NAND_Private_Macros NAND Private Macros
00116   * @{
00117   */
00118
00119 /**
00120   * @}
00121   */
00122 /* Private variables ---------------------------------------------------------*/
00123 /* Private function prototypes -----------------------------------------------*/
00124 /* Exported functions --------------------------------------------------------*/
00125 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00126   * @{
00127   */
00128
00129 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00130   * @brief    Initialization and Configuration functions
00131   *
00132   @verbatim
00133   ==============================================================================
00134             ##### NAND Initialization and de-initialization functions #####
00135   ==============================================================================
00136   [..]
00137     This section provides functions allowing to initialize/de-initialize
00138     the NAND memory
00139
00140 @endverbatim
00141   * @{
00142   */
00143
00144 /**
00145   * @brief  Perform NAND memory Initialization sequence
00146   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00147   *                the configuration information for NAND module.
00148   * @param  ComSpace_Timing: pointer to Common space timing structure
00149   * @param  AttSpace_Timing: pointer to Attribute space timing structure
00150   * @retval HAL status
00151   */
00152 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00153 {
00154   /* Check the NAND handle state */
00155   if(hnand == NULL)
00156   {
00157      return HAL_ERROR;
00158   }
00159
00160   if(hnand->State == HAL_NAND_STATE_RESET)
00161   {
00162     /* Allocate lock resource and initialize it */
00163     hnand->Lock = HAL_UNLOCKED;
00164     /* Initialize the low level hardware (MSP) */
00165     HAL_NAND_MspInit(hnand);
00166   }
00167
00168   /* Initialize NAND control Interface */
00169   FMC_NAND_Init(hnand->Instance, &(hnand->Init));
00170
00171   /* Initialize NAND common space timing Interface */
00172   FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00173
00174   /* Initialize NAND attribute space timing Interface */
00175   FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00176
00177   /* Enable the NAND device */
00178   __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
00179
00180   /* Update the NAND controller state */
00181   hnand->State = HAL_NAND_STATE_READY;
00182
00183   return HAL_OK;
00184 }
00185
00186 /**
00187   * @brief  Perform NAND memory De-Initialization sequence
00188   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00189   *                the configuration information for NAND module.
00190   * @retval HAL status
00191   */
00192 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00193 {
00194   /* Initialize the low level hardware (MSP) */
00195   HAL_NAND_MspDeInit(hnand);
00196
00197   /* Configure the NAND registers with their reset values */
00198   FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00199
00200   /* Reset the NAND controller state */
00201   hnand->State = HAL_NAND_STATE_RESET;
00202
00203   /* Release Lock */
00204   __HAL_UNLOCK(hnand);
00205
00206   return HAL_OK;
00207 }
00208
00209 /**
00210   * @brief  NAND MSP Init
00211   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00212   *                the configuration information for NAND module.
00213   * @retval None
00214   */
00215 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00216 {
00217   /* Prevent unused argument(s) compilation warning */
00218   UNUSED(hnand);
00219   /* NOTE : This function Should not be modified, when the callback is needed,
00220             the HAL_NAND_MspInit could be implemented in the user file
00221    */
00222 }
00223
00224 /**
00225   * @brief  NAND MSP DeInit
00226   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00227   *                the configuration information for NAND module.
00228   * @retval None
00229   */
00230 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00231 {
00232   /* Prevent unused argument(s) compilation warning */
00233   UNUSED(hnand);
00234   /* NOTE : This function Should not be modified, when the callback is needed,
00235             the HAL_NAND_MspDeInit could be implemented in the user file
00236    */
00237 }
00238
00239
00240 /**
00241   * @brief  This function handles NAND device interrupt request.
00242   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00243   *                the configuration information for NAND module.
00244   * @retval HAL status
00245 */
00246 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00247 {
00248   /* Check NAND interrupt Rising edge flag */
00249   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
00250   {
00251     /* NAND interrupt callback*/
00252     HAL_NAND_ITCallback(hnand);
00253
00254     /* Clear NAND interrupt Rising edge pending bit */
00255     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
00256   }
00257
00258   /* Check NAND interrupt Level flag */
00259   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
00260   {
00261     /* NAND interrupt callback*/
00262     HAL_NAND_ITCallback(hnand);
00263
00264     /* Clear NAND interrupt Level pending bit */
00265     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
00266   }
00267
00268   /* Check NAND interrupt Falling edge flag */
00269   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
00270   {
00271     /* NAND interrupt callback*/
00272     HAL_NAND_ITCallback(hnand);
00273
00274     /* Clear NAND interrupt Falling edge pending bit */
00275     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
00276   }
00277
00278   /* Check NAND interrupt FIFO empty flag */
00279   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
00280   {
00281     /* NAND interrupt callback*/
00282     HAL_NAND_ITCallback(hnand);
00283
00284     /* Clear NAND interrupt FIFO empty pending bit */
00285     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
00286   }
00287
00288 }
00289
00290 /**
00291   * @brief  NAND interrupt feature callback
00292   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00293   *                the configuration information for NAND module.
00294   * @retval None
00295   */
00296 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00297 {
00298   /* Prevent unused argument(s) compilation warning */
00299   UNUSED(hnand);
00300   /* NOTE : This function Should not be modified, when the callback is needed,
00301             the HAL_NAND_ITCallback could be implemented in the user file
00302    */
00303 }
00304
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00310   * @brief    Input Output and memory control functions
00311   *
00312   @verbatim
00313   ==============================================================================
00314                     ##### NAND Input and Output functions #####
00315   ==============================================================================
00316   [..]
00317     This section provides functions allowing to use and control the NAND
00318     memory
00319
00320 @endverbatim
00321   * @{
00322   */
00323
00324 /**
00325   * @brief  Read the NAND memory electronic signature
00326   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00327   *                the configuration information for NAND module.
00328   * @param  pNAND_ID: NAND ID structure
00329   * @retval HAL status
00330   */
00331 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00332 {
00333   __IO uint32_t data = 0U;
00334   uint32_t deviceaddress = 0U;
00335
00336   /* Process Locked */
00337   __HAL_LOCK(hnand);
00338
00339   /* Check the NAND controller state */
00340   if(hnand->State == HAL_NAND_STATE_BUSY)
00341   {
00342      return HAL_BUSY;
00343   }
00344
00345   /* Identify the device address */
00346   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00347   {
00348     deviceaddress = NAND_DEVICE1;
00349   }
00350   else
00351   {
00352     deviceaddress = NAND_DEVICE2;
00353   }
00354
00355   /* Update the NAND controller state */
00356   hnand->State = HAL_NAND_STATE_BUSY;
00357
00358   /* Send Read ID command sequence */
00359   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
00360   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00361
00362   /* Read the electronic signature from NAND flash */
00363   data = *(__IO uint32_t *)deviceaddress;
00364
00365   /* Return the data read */
00366   pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00367   pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00368   pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00369   pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00370
00371   /* Update the NAND controller state */
00372   hnand->State = HAL_NAND_STATE_READY;
00373
00374   /* Process unlocked */
00375   __HAL_UNLOCK(hnand);
00376
00377   return HAL_OK;
00378 }
00379
00380 /**
00381   * @brief  NAND memory reset
00382   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00383   *                the configuration information for NAND module.
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00387 {
00388   uint32_t deviceaddress = 0U;
00389
00390   /* Process Locked */
00391   __HAL_LOCK(hnand);
00392
00393   /* Check the NAND controller state */
00394   if(hnand->State == HAL_NAND_STATE_BUSY)
00395   {
00396      return HAL_BUSY;
00397   }
00398
00399   /* Identify the device address */
00400   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00401   {
00402     deviceaddress = NAND_DEVICE1;
00403   }
00404   else
00405   {
00406     deviceaddress = NAND_DEVICE2;
00407   }
00408
00409   /* Update the NAND controller state */
00410   hnand->State = HAL_NAND_STATE_BUSY;
00411
00412   /* Send NAND reset command */
00413   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFFU;
00414
00415
00416   /* Update the NAND controller state */
00417   hnand->State = HAL_NAND_STATE_READY;
00418
00419   /* Process unlocked */
00420   __HAL_UNLOCK(hnand);
00421
00422   return HAL_OK;
00423
00424 }
00425
00426 /**
00427   * @brief  Read Page(s) from NAND memory block
00428   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00429   *                the configuration information for NAND module.
00430   * @param  pAddress : pointer to NAND address structure
00431   * @param  pBuffer : pointer to destination read buffer
00432   * @param  NumPageToRead : number of pages to read from block
00433   * @retval HAL status
00434   */
00435 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
00436 {
00437   __IO uint32_t index  = 0U;
00438   uint32_t deviceaddress = 0U, size = 0U, numpagesread = 0U, addressstatus = NAND_VALID_ADDRESS;
00439   NAND_AddressTypeDef nandaddress;
00440   uint32_t addressoffset = 0U;
00441
00442   /* Process Locked */
00443   __HAL_LOCK(hnand);
00444
00445   /* Check the NAND controller state */
00446   if(hnand->State == HAL_NAND_STATE_BUSY)
00447   {
00448      return HAL_BUSY;
00449   }
00450
00451   /* Identify the device address */
00452   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00453   {
00454     deviceaddress = NAND_DEVICE1;
00455   }
00456   else
00457   {
00458     deviceaddress = NAND_DEVICE2;
00459   }
00460
00461   /* Update the NAND controller state */
00462   hnand->State = HAL_NAND_STATE_BUSY;
00463
00464   /* Save the content of pAddress as it will be modified */
00465   nandaddress.Block     = pAddress->Block;
00466   nandaddress.Page      = pAddress->Page;
00467   nandaddress.Zone      = pAddress->Zone;
00468
00469   /* Page(s) read loop */
00470   while((NumPageToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
00471   {
00472     /* update the buffer size */
00473     size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
00474
00475     /* Get the address offset */
00476     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00477
00478     /* Send read page command sequence */
00479     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00480
00481     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00482     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00483     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00484     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00485
00486     /* for 512 and 1 GB devices, 4th cycle is required */
00487     if(hnand->Info.BlockNbr >= 1024U)
00488     {
00489       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00490     }
00491
00492     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00493
00494     /* Get Data into Buffer */
00495     for(; index < size; index++)
00496     {
00497       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
00498     }
00499
00500     /* Increment read pages number */
00501     numpagesread++;
00502
00503     /* Decrement pages to read */
00504     NumPageToRead--;
00505
00506     /* Increment the NAND address */
00507     addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
00508   }
00509
00510   /* Update the NAND controller state */
00511   hnand->State = HAL_NAND_STATE_READY;
00512
00513   /* Process unlocked */
00514   __HAL_UNLOCK(hnand);
00515
00516   return HAL_OK;
00517
00518 }
00519
00520 /**
00521   * @brief  Write Page(s) to NAND memory block
00522   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00523   *                the configuration information for NAND module.
00524   * @param  pAddress : pointer to NAND address structure
00525   * @param  pBuffer : pointer to source buffer to write
00526   * @param  NumPageToWrite  : number of pages to write to block
00527   * @retval HAL status
00528   */
00529 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
00530 {
00531   __IO uint32_t index   = 0U;
00532   uint32_t tickstart = 0U;
00533   uint32_t deviceaddress = 0U , size = 0U, numpageswritten = 0U, addressstatus = NAND_VALID_ADDRESS;
00534   NAND_AddressTypeDef nandaddress;
00535   uint32_t addressoffset = 0U;
00536
00537   /* Process Locked */
00538   __HAL_LOCK(hnand);
00539
00540   /* Check the NAND controller state */
00541   if(hnand->State == HAL_NAND_STATE_BUSY)
00542   {
00543      return HAL_BUSY;
00544   }
00545
00546   /* Identify the device address */
00547   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00548   {
00549     deviceaddress = NAND_DEVICE1;
00550   }
00551   else
00552   {
00553     deviceaddress = NAND_DEVICE2;
00554   }
00555
00556   /* Update the NAND controller state */
00557   hnand->State = HAL_NAND_STATE_BUSY;
00558
00559   /* Save the content of pAddress as it will be modified */
00560   nandaddress.Block     = pAddress->Block;
00561   nandaddress.Page      = pAddress->Page;
00562   nandaddress.Zone      = pAddress->Zone;
00563
00564   /* Page(s) write loop */
00565   while((NumPageToWrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
00566   {
00567     /* update the buffer size */
00568     size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
00569
00570     /* Get the address offset */
00571     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00572
00573     /* Send write page command sequence */
00574     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00575     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00576
00577     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00578     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00579     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00580     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00581
00582     /* for 512 and 1 GB devices, 4th cycle is required */
00583     if(hnand->Info.BlockNbr >= 1024U)
00584     {
00585       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00586     }
00587
00588     /* Write data to memory */
00589     for(; index < size; index++)
00590     {
00591       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
00592     }
00593
00594     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00595
00596     /* Get tick */
00597     tickstart = HAL_GetTick();
00598
00599     /* Read status until NAND is ready */
00600     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00601     {
00602       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00603       {
00604         return HAL_TIMEOUT;
00605       }
00606     }
00607
00608     /* Increment written pages number */
00609     numpageswritten++;
00610
00611     /* Decrement pages to write */
00612     NumPageToWrite--;
00613
00614     /* Increment the NAND address */
00615     addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
00616   }
00617
00618   /* Update the NAND controller state */
00619   hnand->State = HAL_NAND_STATE_READY;
00620
00621   /* Process unlocked */
00622   __HAL_UNLOCK(hnand);
00623
00624   return HAL_OK;
00625 }
00626
00627 /**
00628   * @brief  Read Spare area(s) from NAND memory
00629   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00630   *                the configuration information for NAND module.
00631   * @param  pAddress : pointer to NAND address structure
00632   * @param  pBuffer: pointer to source buffer to write
00633   * @param  NumSpareAreaToRead: Number of spare area to read
00634   * @retval HAL status
00635 */
00636 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
00637 {
00638   __IO uint32_t index   = 0U;
00639   uint32_t deviceaddress = 0U, size = 0U, num_spare_area_read = 0U, addressstatus = NAND_VALID_ADDRESS;
00640   NAND_AddressTypeDef nandaddress;
00641   uint32_t addressoffset = 0U;
00642
00643   /* Process Locked */
00644   __HAL_LOCK(hnand);
00645
00646   /* Check the NAND controller state */
00647   if(hnand->State == HAL_NAND_STATE_BUSY)
00648   {
00649      return HAL_BUSY;
00650   }
00651
00652   /* Identify the device address */
00653   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00654   {
00655     deviceaddress = NAND_DEVICE1;
00656   }
00657   else
00658   {
00659     deviceaddress = NAND_DEVICE2;
00660   }
00661
00662   /* Update the NAND controller state */
00663   hnand->State = HAL_NAND_STATE_BUSY;
00664
00665   /* Save the content of pAddress as it will be modified */
00666   nandaddress.Block     = pAddress->Block;
00667   nandaddress.Page      = pAddress->Page;
00668   nandaddress.Zone      = pAddress->Zone;
00669
00670   /* Spare area(s) read loop */
00671   while((NumSpareAreaToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
00672   {
00673     /* update the buffer size */
00674     size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
00675
00676     /* Get the address offset */
00677     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00678
00679     /* Send read spare area command sequence */
00680     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
00681
00682     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00683     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00684     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00685     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00686
00687     /* for 512 and 1 GB devices, 4th cycle is required */
00688     if(hnand->Info.BlockNbr >= 1024U)
00689     {
00690       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00691     }
00692
00693     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
00694
00695     /* Get Data into Buffer */
00696     for(; index < size; index++)
00697     {
00698       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
00699     }
00700
00701     /* Increment read spare areas number */
00702     num_spare_area_read++;
00703
00704     /* Decrement spare areas to read */
00705     NumSpareAreaToRead--;
00706
00707     /* Increment the NAND address */
00708     addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
00709   }
00710
00711   /* Update the NAND controller state */
00712   hnand->State = HAL_NAND_STATE_READY;
00713
00714   /* Process unlocked */
00715   __HAL_UNLOCK(hnand);
00716
00717   return HAL_OK;
00718 }
00719
00720 /**
00721   * @brief  Write Spare area(s) to NAND memory
00722   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00723   *                the configuration information for NAND module.
00724   * @param  pAddress : pointer to NAND address structure
00725   * @param  pBuffer : pointer to source buffer to write
00726   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
00727   * @retval HAL status
00728   */
00729 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
00730 {
00731   __IO uint32_t index = 0U;
00732   uint32_t tickstart = 0U;
00733   uint32_t deviceaddress = 0U, size = 0U, num_spare_area_written = 0U, addressstatus = NAND_VALID_ADDRESS;
00734   NAND_AddressTypeDef nandaddress;
00735   uint32_t addressoffset = 0U;
00736
00737   /* Process Locked */
00738   __HAL_LOCK(hnand);
00739
00740   /* Check the NAND controller state */
00741   if(hnand->State == HAL_NAND_STATE_BUSY)
00742   {
00743      return HAL_BUSY;
00744   }
00745
00746   /* Identify the device address */
00747   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00748   {
00749     deviceaddress = NAND_DEVICE1;
00750   }
00751   else
00752   {
00753     deviceaddress = NAND_DEVICE2;
00754   }
00755
00756   /* Update the FMC_NAND controller state */
00757   hnand->State = HAL_NAND_STATE_BUSY;
00758
00759   /* Save the content of pAddress as it will be modified */
00760   nandaddress.Block     = pAddress->Block;
00761   nandaddress.Page      = pAddress->Page;
00762   nandaddress.Zone      = pAddress->Zone;
00763
00764   /* Spare area(s) write loop */
00765   while((NumSpareAreaTowrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
00766   {
00767     /* update the buffer size */
00768     size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
00769
00770     /* Get the address offset */
00771     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00772
00773     /* Send write Spare area command sequence */
00774     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
00775     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00776
00777     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
00778     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00779     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00780     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00781
00782     /* for 512 and 1 GB devices, 4th cycle is required */
00783     if(hnand->Info.BlockNbr >= 1024U)
00784     {
00785       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00786     }
00787
00788     /* Write data to memory */
00789     for(; index < size; index++)
00790     {
00791       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
00792     }
00793
00794     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00795
00796     /* Get tick */
00797     tickstart = HAL_GetTick();
00798
00799     /* Read status until NAND is ready */
00800     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00801     {
00802       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00803       {
00804         return HAL_TIMEOUT;
00805       }
00806     }
00807
00808     /* Increment written spare areas number */
00809     num_spare_area_written++;
00810
00811     /* Decrement spare areas to write */
00812     NumSpareAreaTowrite--;
00813
00814     /* Increment the NAND address */
00815     addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
00816   }
00817
00818   /* Update the NAND controller state */
00819   hnand->State = HAL_NAND_STATE_READY;
00820
00821   /* Process unlocked */
00822   __HAL_UNLOCK(hnand);
00823
00824   return HAL_OK;
00825 }
00826
00827 /**
00828   * @brief  NAND memory Block erase
00829   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00830   *                the configuration information for NAND module.
00831   * @param  pAddress : pointer to NAND address structure
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
00835 {
00836   uint32_t deviceaddress = 0U;
00837   uint32_t tickstart = 0U;
00838
00839   /* Process Locked */
00840   __HAL_LOCK(hnand);
00841
00842   /* Check the NAND controller state */
00843   if(hnand->State == HAL_NAND_STATE_BUSY)
00844   {
00845      return HAL_BUSY;
00846   }
00847
00848   /* Identify the device address */
00849   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00850   {
00851     deviceaddress = NAND_DEVICE1;
00852   }
00853   else
00854   {
00855     deviceaddress = NAND_DEVICE2;
00856   }
00857
00858   /* Update the NAND controller state */
00859   hnand->State = HAL_NAND_STATE_BUSY;
00860
00861   /* Send Erase block command sequence */
00862   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
00863
00864   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00865   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00866   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00867
00868   /* for 512 and 1 GB devices, 4th cycle is required */
00869   if(hnand->Info.BlockNbr >= 1024U)
00870   {
00871     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00872   }
00873
00874   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
00875
00876   /* Update the NAND controller state */
00877   hnand->State = HAL_NAND_STATE_READY;
00878
00879   /* Get tick */
00880   tickstart = HAL_GetTick();
00881
00882   /* Read status until NAND is ready */
00883   while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00884   {
00885     if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00886     {
00887       /* Process unlocked */
00888       __HAL_UNLOCK(hnand);
00889
00890       return HAL_TIMEOUT;
00891     }
00892   }
00893
00894   /* Process unlocked */
00895   __HAL_UNLOCK(hnand);
00896
00897   return HAL_OK;
00898 }
00899
00900 /**
00901   * @brief  NAND memory read status
00902   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00903   *                the configuration information for NAND module.
00904   * @retval NAND status
00905   */
00906 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
00907 {
00908   uint32_t data = 0U;
00909   uint32_t deviceaddress = 0U;
00910
00911   /* Identify the device address */
00912   if(hnand->Init.NandBank == FMC_NAND_BANK2)
00913   {
00914     deviceaddress = NAND_DEVICE1;
00915   }
00916   else
00917   {
00918     deviceaddress = NAND_DEVICE2;
00919   }
00920
00921   /* Send Read status operation command */
00922   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
00923
00924   /* Read status register data */
00925   data = *(__IO uint8_t *)deviceaddress;
00926
00927   /* Return the status */
00928   if((data & NAND_ERROR) == NAND_ERROR)
00929   {
00930     return NAND_ERROR;
00931   }
00932   else if((data & NAND_READY) == NAND_READY)
00933   {
00934     return NAND_READY;
00935   }
00936
00937   return NAND_BUSY;
00938 }
00939
00940 /**
00941   * @brief  Increment the NAND memory address
00942   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00943   *                the configuration information for NAND module.
00944   * @param pAddress: pointer to NAND address structure
00945   * @retval The new status of the increment address operation. It can be:
00946   *           - NAND_VALID_ADDRESS: When the new address is valid address
00947   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
00948   */
00949 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
00950 {
00951   uint32_t status = NAND_VALID_ADDRESS;
00952
00953   /* Increment page address */
00954   pAddress->Page++;
00955
00956   /* Check NAND address is valid */
00957   if(pAddress->Page == hnand->Info.BlockSize)
00958   {
00959     pAddress->Page = 0U;
00960     pAddress->Block++;
00961
00962     if(pAddress->Block == hnand->Info.ZoneSize)
00963     {
00964       pAddress->Block = 0U;
00965       pAddress->Zone++;
00966
00967       if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
00968       {
00969         status = NAND_INVALID_ADDRESS;
00970       }
00971     }
00972   }
00973
00974   return (status);
00975 }
00976 /**
00977   * @}
00978   */
00979
00980 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
00981  *  @brief   management functions
00982  *
00983 @verbatim
00984   ==============================================================================
00985                          ##### NAND Control functions #####
00986   ==============================================================================
00987   [..]
00988     This subsection provides a set of functions allowing to control dynamically
00989     the NAND interface.
00990
00991 @endverbatim
00992   * @{
00993   */
00994
00995
00996 /**
00997   * @brief  Enables dynamically NAND ECC feature.
00998   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00999   *                the configuration information for NAND module.
01000   * @retval HAL status
01001   */
01002 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
01003 {
01004   /* Check the NAND controller state */
01005   if(hnand->State == HAL_NAND_STATE_BUSY)
01006   {
01007      return HAL_BUSY;
01008   }
01009
01010   /* Update the NAND state */
01011   hnand->State = HAL_NAND_STATE_BUSY;
01012
01013   /* Enable ECC feature */
01014   FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
01015
01016   /* Update the NAND state */
01017   hnand->State = HAL_NAND_STATE_READY;
01018
01019   return HAL_OK;
01020 }
01021
01022 /**
01023   * @brief  Disables dynamically FMC_NAND ECC feature.
01024   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01025   *                the configuration information for NAND module.
01026   * @retval HAL status
01027   */
01028 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
01029 {
01030   /* Check the NAND controller state */
01031   if(hnand->State == HAL_NAND_STATE_BUSY)
01032   {
01033      return HAL_BUSY;
01034   }
01035
01036   /* Update the NAND state */
01037   hnand->State = HAL_NAND_STATE_BUSY;
01038
01039   /* Disable ECC feature */
01040   FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
01041
01042   /* Update the NAND state */
01043   hnand->State = HAL_NAND_STATE_READY;
01044
01045   return HAL_OK;
01046 }
01047
01048 /**
01049   * @brief  Disables dynamically NAND ECC feature.
01050   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01051   *                the configuration information for NAND module.
01052   * @param  ECCval: pointer to ECC value
01053   * @param  Timeout: maximum timeout to wait
01054   * @retval HAL status
01055   */
01056 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
01057 {
01058   HAL_StatusTypeDef status = HAL_OK;
01059
01060   /* Check the NAND controller state */
01061   if(hnand->State == HAL_NAND_STATE_BUSY)
01062   {
01063      return HAL_BUSY;
01064   }
01065
01066   /* Update the NAND state */
01067   hnand->State = HAL_NAND_STATE_BUSY;
01068
01069   /* Get NAND ECC value */
01070   status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
01071
01072   /* Update the NAND state */
01073   hnand->State = HAL_NAND_STATE_READY;
01074
01075   return status;
01076 }
01077
01078 /**
01079   * @}
01080   */
01081
01082
01083 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
01084  *  @brief   Peripheral State functions
01085  *
01086 @verbatim
01087   ==============================================================================
01088                          ##### NAND State functions #####
01089   ==============================================================================
01090   [..]
01091     This subsection permits to get in run-time the status of the NAND controller
01092     and the data flow.
01093
01094 @endverbatim
01095   * @{
01096   */
01097
01098 /**
01099   * @brief  return the NAND state
01100   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01101   *                the configuration information for NAND module.
01102   * @retval HAL state
01103   */
01104 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
01105 {
01106   return hnand->State;
01107 }
01108
01109 /**
01110   * @}
01111   */
01112
01113 /**
01114   * @}
01115   */
01116
01117 /**
01118   * @}
01119   */
01120
01121 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
01122           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
01123           STM32F446xx || STM32F469xx || STM32F479xx */
01124 #endif /* HAL_NAND_MODULE_ENABLED  */
01125
01126 /**
01127   * @}
01128   */
01129
01130 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_nand.h Source File

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stm32f4xx_hal_nand.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of NAND HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_NAND_H
00040 #define __STM32F4xx_HAL_NAND_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00048   #include "stm32f4xx_ll_fsmc.h"
00049 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00050
00051 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00052     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00053   #include "stm32f4xx_ll_fmc.h"
00054 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
00055           STM32F479xx */
00056
00057 /** @addtogroup STM32F4xx_HAL_Driver
00058   * @{
00059   */
00060
00061 /** @addtogroup NAND
00062   * @{
00063   */
00064
00065 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00066     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00067         defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00068
00069 /* Exported typedef ----------------------------------------------------------*/
00070 /* Exported types ------------------------------------------------------------*/
00071 /** @defgroup NAND_Exported_Types NAND Exported Types
00072   * @{
00073   */
00074
00075 /**
00076   * @brief  HAL NAND State structures definition
00077   */
00078 typedef enum
00079 {
00080   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
00081   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
00082   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
00083   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
00084 }HAL_NAND_StateTypeDef;
00085
00086 /**
00087   * @brief  NAND Memory electronic signature Structure definition
00088   */
00089 typedef struct
00090 {
00091   /*<! NAND memory electronic signature maker and device IDs */
00092
00093   uint8_t Maker_Id;
00094
00095   uint8_t Device_Id;
00096
00097   uint8_t Third_Id;
00098
00099   uint8_t Fourth_Id;
00100 }NAND_IDTypeDef;
00101
00102 /**
00103   * @brief  NAND Memory address Structure definition
00104   */
00105 typedef struct
00106 {
00107   uint16_t Page;   /*!< NAND memory Page address  */
00108
00109   uint16_t Zone;   /*!< NAND memory Zone address  */
00110
00111   uint16_t Block;  /*!< NAND memory Block address */
00112
00113 }NAND_AddressTypeDef;
00114
00115 /**
00116   * @brief  NAND Memory info Structure definition
00117   */
00118 typedef struct
00119 {
00120   uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
00121
00122   uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
00123
00124   uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
00125
00126   uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
00127
00128   uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
00129 }NAND_InfoTypeDef;
00130
00131 /**
00132   * @brief  NAND handle Structure definition
00133   */
00134 typedef struct
00135 {
00136   FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
00137
00138   FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
00139
00140   HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
00141
00142   __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
00143
00144   NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
00145 }NAND_HandleTypeDef;
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /* Exported macros ------------------------------------------------------------*/
00152 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00153  * @{
00154  */
00155
00156 /** @brief Reset NAND handle state
00157   * @param  __HANDLE__: specifies the NAND handle.
00158   * @retval None
00159   */
00160 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00161
00162 /**
00163   * @}
00164   */
00165
00166 /* Exported functions --------------------------------------------------------*/
00167 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00168   * @{
00169   */
00170
00171 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00172   * @{
00173   */
00174
00175 /* Initialization/de-initialization functions  ********************************/
00176 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00177 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00178 void        HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00179 void        HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00180 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00181 void        HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00188   * @{
00189   */
00190
00191 /* IO operation functions  ****************************************************/
00192 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00193 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00194 HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
00195 HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
00196 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00197 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00198 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00199 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00200 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00201
00202 /**
00203   * @}
00204   */
00205
00206 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00207   * @{
00208   */
00209
00210 /* NAND Control functions  ****************************************************/
00211 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00212 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00213 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
00220   * @{
00221   */
00222 /* NAND State functions *******************************************************/
00223 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
00224 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /* Private types -------------------------------------------------------------*/
00234 /* Private variables ---------------------------------------------------------*/
00235 /* Private constants ---------------------------------------------------------*/
00236 /** @defgroup NAND_Private_Constants NAND Private Constants
00237   * @{
00238   */
00239 #define NAND_DEVICE1               ((uint32_t)0x70000000U)
00240 #define NAND_DEVICE2               ((uint32_t)0x80000000U)
00241 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
00242
00243 #define CMD_AREA                   ((uint32_t)(1U<<16U))  /* A16 = CLE high */
00244 #define ADDR_AREA                  ((uint32_t)(1U<<17U))  /* A17 = ALE high */
00245
00246 #define NAND_CMD_AREA_A            ((uint8_t)0x00U)
00247 #define NAND_CMD_AREA_B            ((uint8_t)0x01U)
00248 #define NAND_CMD_AREA_C            ((uint8_t)0x50U)
00249 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
00250
00251 #define NAND_CMD_WRITE0            ((uint8_t)0x80U)
00252 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
00253 #define NAND_CMD_ERASE0            ((uint8_t)0x60U)
00254 #define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
00255 #define NAND_CMD_READID            ((uint8_t)0x90U)
00256 #define NAND_CMD_STATUS            ((uint8_t)0x70U)
00257 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
00258 #define NAND_CMD_RESET             ((uint8_t)0xFFU)
00259
00260 /* NAND memory status */
00261 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
00262 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
00263 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
00264 #define NAND_BUSY                  ((uint32_t)0x00000000U)
00265 #define NAND_ERROR                 ((uint32_t)0x00000001U)
00266 #define NAND_READY                 ((uint32_t)0x00000040U)
00267 /**
00268   * @}
00269   */
00270
00271 /* Private macros ------------------------------------------------------------*/
00272 /** @defgroup NAND_Private_Macros NAND Private Macros
00273   * @{
00274   */
00275
00276 /**
00277   * @brief  NAND memory address computation.
00278   * @param  __ADDRESS__: NAND memory address.
00279   * @param  __HANDLE__: NAND handle.
00280   * @retval NAND Raw address value
00281   */
00282 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
00283                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
00284
00285 /**
00286   * @brief  NAND memory address cycling.
00287   * @param  __ADDRESS__: NAND memory address.
00288   * @retval NAND address cycling value.
00289   */
00290 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)               /* 1st addressing cycle */
00291 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)       /* 2nd addressing cycle */
00292 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16U)      /* 3rd addressing cycle */
00293 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24U)      /* 4th addressing cycle */
00294 /**
00295   * @}
00296   */
00297 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00298           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
00299           STM32F446xx || STM32F469xx || STM32F479xx */
00300
00301 /**
00302   * @}
00303   */
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 #ifdef __cplusplus
00313 }
00314 #endif
00315
00316 #endif /* __STM32F4xx_HAL_NAND_H */
00317
00318 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_nor.c Source File

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stm32f4xx_hal_nor.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   NOR HAL module driver.
00008   *          This file provides a generic firmware to drive NOR memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                      ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NOR flash memories. It uses the FMC/FSMC layer functions to interface
00018       with NOR devices. This driver is used as follows:
00019
00020       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00021           with control and timing parameters for both normal and extended mode.
00022
00023       (+) Read NOR flash memory manufacturer code and device IDs using the function
00024           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NOR flash memory by read/write data unit operations using the functions
00028           HAL_NOR_Read(), HAL_NOR_Program().
00029
00030       (+) Perform NOR flash erase block/chip operations using the functions
00031           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00032
00033       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00034           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00035           structure declared by the function caller.
00036
00037       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00038           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00039
00040       (+) You can monitor the NOR device HAL state by calling the function
00041           HAL_NOR_GetState()
00042     [..]
00043      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00044          If a NOR flash device contains different operations and/or implementations,
00045          it should be implemented separately.
00046
00047      *** NOR HAL driver macros list ***
00048      =============================================
00049      [..]
00050        Below the list of most used macros in NOR HAL driver.
00051
00052       (+) NOR_WRITE : NOR memory write data to specified address
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32f4xx_hal.h"
00087
00088 /** @addtogroup STM32F4xx_HAL_Driver
00089   * @{
00090   */
00091
00092 /** @defgroup NOR NOR
00093   * @brief NOR driver modules
00094   * @{
00095   */
00096 #ifdef HAL_NOR_MODULE_ENABLED
00097 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00098     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00099     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00100 /* Private typedef -----------------------------------------------------------*/
00101 /* Private define ------------------------------------------------------------*/
00102
00103 /** @defgroup NOR_Private_Defines NOR Private Defines
00104   * @{
00105   */
00106
00107 /* Constants to define address to set to write a command */
00108 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555U
00109 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055U
00110 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AAU
00111 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555U
00112 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555U
00113 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AAU
00114 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555U
00115
00116 /* Constants to define data to program a command */
00117 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0U
00118 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AAU
00119 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055U
00120 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090U
00121 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0U
00122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080U
00123 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AAU
00124 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055U
00125 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010U
00126 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098U
00127
00128 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25U
00129 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29U
00130 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30U
00131
00132 /* Mask on NOR STATUS REGISTER */
00133 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020U
00134 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040U
00135
00136 /**
00137   * @}
00138   */
00139
00140 /* Private macro -------------------------------------------------------------*/
00141 /* Private variables ---------------------------------------------------------*/
00142 /* Private functions ---------------------------------------------------------*/
00143 /* Exported functions --------------------------------------------------------*/
00144 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00145   * @{
00146   */
00147
00148 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00149   * @brief    Initialization and Configuration functions
00150   *
00151   @verbatim
00152   ==============================================================================
00153            ##### NOR Initialization and de_initialization functions #####
00154   ==============================================================================
00155   [..]
00156     This section provides functions allowing to initialize/de-initialize
00157     the NOR memory
00158
00159 @endverbatim
00160   * @{
00161   */
00162
00163 /**
00164   * @brief  Perform the NOR memory Initialization sequence
00165   * @param  hnor: pointer to the NOR handle
00166   * @param  Timing: pointer to NOR control timing structure
00167   * @param  ExtTiming: pointer to NOR extended mode timing structure
00168   * @retval HAL status
00169   */
00170 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00171 {
00172   /* Check the NOR handle parameter */
00173   if(hnor == NULL)
00174   {
00175      return HAL_ERROR;
00176   }
00177
00178   if(hnor->State == HAL_NOR_STATE_RESET)
00179   {
00180     /* Allocate lock resource and initialize it */
00181     hnor->Lock = HAL_UNLOCKED;
00182     /* Initialize the low level hardware (MSP) */
00183     HAL_NOR_MspInit(hnor);
00184   }
00185
00186   /* Initialize NOR control Interface */
00187   FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00188
00189   /* Initialize NOR timing Interface */
00190   FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00191
00192   /* Initialize NOR extended mode timing Interface */
00193   FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
00194
00195   /* Enable the NORSRAM device */
00196   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00197
00198   /* Check the NOR controller state */
00199   hnor->State = HAL_NOR_STATE_READY;
00200
00201   return HAL_OK;
00202 }
00203
00204 /**
00205   * @brief  Perform NOR memory De-Initialization sequence
00206   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00207   *                the configuration information for NOR module.
00208   * @retval HAL status
00209   */
00210 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00211 {
00212   /* De-Initialize the low level hardware (MSP) */
00213   HAL_NOR_MspDeInit(hnor);
00214
00215   /* Configure the NOR registers with their reset values */
00216   FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00217
00218   /* Update the NOR controller state */
00219   hnor->State = HAL_NOR_STATE_RESET;
00220
00221   /* Release Lock */
00222   __HAL_UNLOCK(hnor);
00223
00224   return HAL_OK;
00225 }
00226
00227 /**
00228   * @brief  NOR MSP Init
00229   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00230   *                the configuration information for NOR module.
00231   * @retval None
00232   */
00233 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00234 {
00235   /* Prevent unused argument(s) compilation warning */
00236   UNUSED(hnor);
00237   /* NOTE : This function Should not be modified, when the callback is needed,
00238             the HAL_NOR_MspInit could be implemented in the user file
00239    */
00240 }
00241
00242 /**
00243   * @brief  NOR MSP DeInit
00244   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00245   *                the configuration information for NOR module.
00246   * @retval None
00247   */
00248 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00249 {
00250   /* Prevent unused argument(s) compilation warning */
00251   UNUSED(hnor);
00252   /* NOTE : This function Should not be modified, when the callback is needed,
00253             the HAL_NOR_MspDeInit could be implemented in the user file
00254    */
00255 }
00256
00257 /**
00258   * @brief  NOR BSP Wait for Ready/Busy signal
00259   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00260   *                the configuration information for NOR module.
00261   * @param  Timeout: Maximum timeout value
00262   * @retval None
00263   */
00264 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(hnor);
00268   /* NOTE : This function Should not be modified, when the callback is needed,
00269             the HAL_NOR_BspWait could be implemented in the user file
00270    */
00271 }
00272
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00278   * @brief    Input Output and memory control functions
00279   *
00280   @verbatim
00281   ==============================================================================
00282                 ##### NOR Input and Output functions #####
00283   ==============================================================================
00284   [..]
00285     This section provides functions allowing to use and control the NOR memory
00286
00287 @endverbatim
00288   * @{
00289   */
00290
00291 /**
00292   * @brief  Read NOR flash IDs
00293   * @param  hnor: pointer to the NOR handle
00294   * @param  pNOR_ID : pointer to NOR ID structure
00295   * @retval HAL status
00296   */
00297 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00298 {
00299   uint32_t deviceaddress = 0U;
00300
00301   /* Process Locked */
00302   __HAL_LOCK(hnor);
00303
00304   /* Check the NOR controller state */
00305   if(hnor->State == HAL_NOR_STATE_BUSY)
00306   {
00307      return HAL_BUSY;
00308   }
00309
00310   /* Select the NOR device address */
00311   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00312   {
00313     deviceaddress = NOR_MEMORY_ADRESS1;
00314   }
00315   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00316   {
00317     deviceaddress = NOR_MEMORY_ADRESS2;
00318   }
00319   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00320   {
00321     deviceaddress = NOR_MEMORY_ADRESS3;
00322   }
00323   else /* FMC_NORSRAM_BANK4 */
00324   {
00325     deviceaddress = NOR_MEMORY_ADRESS4;
00326   }
00327
00328   /* Update the NOR controller state */
00329   hnor->State = HAL_NOR_STATE_BUSY;
00330
00331   /* Send read ID command */
00332   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00333   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00334   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
00335
00336   /* Read the NOR IDs */
00337   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
00338   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
00339   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
00340   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
00341
00342   /* Check the NOR controller state */
00343   hnor->State = HAL_NOR_STATE_READY;
00344
00345   /* Process unlocked */
00346   __HAL_UNLOCK(hnor);
00347
00348   return HAL_OK;
00349 }
00350
00351 /**
00352   * @brief  Returns the NOR memory to Read mode.
00353   * @param  hnor: pointer to the NOR handle
00354   * @retval HAL status
00355   */
00356 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00357 {
00358   uint32_t deviceaddress = 0U;
00359
00360   /* Process Locked */
00361   __HAL_LOCK(hnor);
00362
00363   /* Check the NOR controller state */
00364   if(hnor->State == HAL_NOR_STATE_BUSY)
00365   {
00366      return HAL_BUSY;
00367   }
00368
00369   /* Select the NOR device address */
00370   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00371   {
00372     deviceaddress = NOR_MEMORY_ADRESS1;
00373   }
00374   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00375   {
00376     deviceaddress = NOR_MEMORY_ADRESS2;
00377   }
00378   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00379   {
00380     deviceaddress = NOR_MEMORY_ADRESS3;
00381   }
00382   else /* FMC_NORSRAM_BANK4 */
00383   {
00384     deviceaddress = NOR_MEMORY_ADRESS4;
00385   }
00386
00387   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00388
00389   /* Check the NOR controller state */
00390   hnor->State = HAL_NOR_STATE_READY;
00391
00392   /* Process unlocked */
00393   __HAL_UNLOCK(hnor);
00394
00395   return HAL_OK;
00396 }
00397
00398 /**
00399   * @brief  Read data from NOR memory
00400   * @param  hnor: pointer to the NOR handle
00401   * @param  pAddress: pointer to Device address
00402   * @param  pData : pointer to read data
00403   * @retval HAL status
00404   */
00405 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00406 {
00407   uint32_t deviceaddress = 0U;
00408
00409   /* Process Locked */
00410   __HAL_LOCK(hnor);
00411
00412   /* Check the NOR controller state */
00413   if(hnor->State == HAL_NOR_STATE_BUSY)
00414   {
00415      return HAL_BUSY;
00416   }
00417
00418   /* Select the NOR device address */
00419   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00420   {
00421     deviceaddress = NOR_MEMORY_ADRESS1;
00422   }
00423   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00424   {
00425     deviceaddress = NOR_MEMORY_ADRESS2;
00426   }
00427   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00428   {
00429     deviceaddress = NOR_MEMORY_ADRESS3;
00430   }
00431   else /* FMC_NORSRAM_BANK4 */
00432   {
00433     deviceaddress = NOR_MEMORY_ADRESS4;
00434   }
00435
00436   /* Update the NOR controller state */
00437   hnor->State = HAL_NOR_STATE_BUSY;
00438
00439   /* Send read data command */
00440   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00441   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00442   NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
00443
00444   /* Read the data */
00445  *pData = *(__IO uint32_t *)(uint32_t)pAddress;
00446
00447   /* Check the NOR controller state */
00448   hnor->State = HAL_NOR_STATE_READY;
00449
00450   /* Process unlocked */
00451   __HAL_UNLOCK(hnor);
00452
00453   return HAL_OK;
00454 }
00455
00456 /**
00457   * @brief  Program data to NOR memory
00458   * @param  hnor: pointer to the NOR handle
00459   * @param  pAddress: Device address
00460   * @param  pData : pointer to the data to write
00461   * @retval HAL status
00462   */
00463 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00464 {
00465   uint32_t deviceaddress = 0U;
00466
00467   /* Process Locked */
00468   __HAL_LOCK(hnor);
00469
00470   /* Check the NOR controller state */
00471   if(hnor->State == HAL_NOR_STATE_BUSY)
00472   {
00473      return HAL_BUSY;
00474   }
00475
00476   /* Select the NOR device address */
00477   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00478   {
00479     deviceaddress = NOR_MEMORY_ADRESS1;
00480   }
00481   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00482   {
00483     deviceaddress = NOR_MEMORY_ADRESS2;
00484   }
00485   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00486   {
00487     deviceaddress = NOR_MEMORY_ADRESS3;
00488   }
00489   else /* FMC_NORSRAM_BANK4 */
00490   {
00491     deviceaddress = NOR_MEMORY_ADRESS4;
00492   }
00493
00494   /* Update the NOR controller state */
00495   hnor->State = HAL_NOR_STATE_BUSY;
00496
00497   /* Send program data command */
00498   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00499   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00500   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00501
00502   /* Write the data */
00503   NOR_WRITE(pAddress, *pData);
00504
00505   /* Check the NOR controller state */
00506   hnor->State = HAL_NOR_STATE_READY;
00507
00508   /* Process unlocked */
00509   __HAL_UNLOCK(hnor);
00510
00511   return HAL_OK;
00512 }
00513
00514 /**
00515   * @brief  Reads a half-word buffer from the NOR memory.
00516   * @param  hnor: pointer to the NOR handle
00517   * @param  uwAddress: NOR memory internal address to read from.
00518   * @param  pData: pointer to the buffer that receives the data read from the
00519   *         NOR memory.
00520   * @param  uwBufferSize : number of Half word to read.
00521   * @retval HAL status
00522   */
00523 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00524 {
00525   uint32_t deviceaddress = 0U;
00526
00527   /* Process Locked */
00528   __HAL_LOCK(hnor);
00529
00530   /* Check the NOR controller state */
00531   if(hnor->State == HAL_NOR_STATE_BUSY)
00532   {
00533      return HAL_BUSY;
00534   }
00535
00536   /* Select the NOR device address */
00537   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00538   {
00539     deviceaddress = NOR_MEMORY_ADRESS1;
00540   }
00541   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00542   {
00543     deviceaddress = NOR_MEMORY_ADRESS2;
00544   }
00545   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00546   {
00547     deviceaddress = NOR_MEMORY_ADRESS3;
00548   }
00549   else /* FMC_NORSRAM_BANK4 */
00550   {
00551     deviceaddress = NOR_MEMORY_ADRESS4;
00552   }
00553
00554   /* Update the NOR controller state */
00555   hnor->State = HAL_NOR_STATE_BUSY;
00556
00557   /* Send read data command */
00558   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00559   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00560   NOR_WRITE(uwAddress, 0x00F0U);
00561
00562   /* Read buffer */
00563   while( uwBufferSize > 0U)
00564   {
00565     *pData++ = *(__IO uint16_t *)uwAddress;
00566     uwAddress += 2U;
00567     uwBufferSize--;
00568   }
00569
00570   /* Check the NOR controller state */
00571   hnor->State = HAL_NOR_STATE_READY;
00572
00573   /* Process unlocked */
00574   __HAL_UNLOCK(hnor);
00575
00576   return HAL_OK;
00577 }
00578
00579 /**
00580   * @brief  Writes a half-word buffer to the NOR memory. This function must be used
00581             only with S29GL128P NOR memory.
00582   * @param  hnor: pointer to the NOR handle
00583   * @param  uwAddress: NOR memory internal start write address
00584   * @param  pData: pointer to source data buffer.
00585   * @param  uwBufferSize: Size of the buffer to write
00586   * @retval HAL status
00587   */
00588 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00589 {
00590   uint16_t * p_currentaddress = (uint16_t *)NULL;
00591   uint16_t * p_endaddress = (uint16_t *)NULL;
00592   uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
00593
00594   /* Process Locked */
00595   __HAL_LOCK(hnor);
00596
00597   /* Check the NOR controller state */
00598   if(hnor->State == HAL_NOR_STATE_BUSY)
00599   {
00600      return HAL_BUSY;
00601   }
00602
00603   /* Select the NOR device address */
00604   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00605   {
00606     deviceaddress = NOR_MEMORY_ADRESS1;
00607   }
00608   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00609   {
00610     deviceaddress = NOR_MEMORY_ADRESS2;
00611   }
00612   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00613   {
00614     deviceaddress = NOR_MEMORY_ADRESS3;
00615   }
00616   else /* FMC_NORSRAM_BANK4 */
00617   {
00618     deviceaddress = NOR_MEMORY_ADRESS4;
00619   }
00620
00621   /* Update the NOR controller state */
00622   hnor->State = HAL_NOR_STATE_BUSY;
00623
00624   /* Initialize variables */
00625   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
00626   p_endaddress      = p_currentaddress + (uwBufferSize-1U);
00627   lastloadedaddress = (uint32_t)(uwAddress);
00628
00629   /* Issue unlock command sequence */
00630   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00631   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00632
00633   /* Write Buffer Load Command */
00634   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00635   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1U));
00636
00637   /* Load Data into NOR Buffer */
00638   while(p_currentaddress <= p_endaddress)
00639   {
00640     /* Store last loaded address & data value (for polling) */
00641      lastloadedaddress = (uint32_t)p_currentaddress;
00642
00643     NOR_WRITE(p_currentaddress, *pData++);
00644
00645     p_currentaddress ++;
00646   }
00647
00648   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
00649
00650   /* Check the NOR controller state */
00651   hnor->State = HAL_NOR_STATE_READY;
00652
00653   /* Process unlocked */
00654   __HAL_UNLOCK(hnor);
00655
00656   return HAL_OK;
00657
00658 }
00659
00660 /**
00661   * @brief  Erase the specified block of the NOR memory
00662   * @param  hnor: pointer to the NOR handle
00663   * @param  BlockAddress : Block to erase address
00664   * @param  Address: Device address
00665   * @retval HAL status
00666   */
00667 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
00668 {
00669   uint32_t deviceaddress = 0U;
00670
00671   /* Process Locked */
00672   __HAL_LOCK(hnor);
00673
00674   /* Check the NOR controller state */
00675   if(hnor->State == HAL_NOR_STATE_BUSY)
00676   {
00677      return HAL_BUSY;
00678   }
00679
00680   /* Select the NOR device address */
00681   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00682   {
00683     deviceaddress = NOR_MEMORY_ADRESS1;
00684   }
00685   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00686   {
00687     deviceaddress = NOR_MEMORY_ADRESS2;
00688   }
00689   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00690   {
00691     deviceaddress = NOR_MEMORY_ADRESS3;
00692   }
00693   else /* FMC_NORSRAM_BANK4 */
00694   {
00695     deviceaddress = NOR_MEMORY_ADRESS4;
00696   }
00697
00698   /* Update the NOR controller state */
00699   hnor->State = HAL_NOR_STATE_BUSY;
00700
00701   /* Send block erase command sequence */
00702   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00703   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00704   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00705   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00706   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00707   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
00708
00709   /* Check the NOR memory status and update the controller state */
00710   hnor->State = HAL_NOR_STATE_READY;
00711
00712   /* Process unlocked */
00713   __HAL_UNLOCK(hnor);
00714
00715   return HAL_OK;
00716
00717 }
00718
00719 /**
00720   * @brief  Erase the entire NOR chip.
00721   * @param  hnor: pointer to the NOR handle
00722   * @param  Address : Device address
00723   * @retval HAL status
00724   */
00725 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
00726 {
00727   uint32_t deviceaddress = 0U;
00728
00729   /* Process Locked */
00730   __HAL_LOCK(hnor);
00731
00732   /* Check the NOR controller state */
00733   if(hnor->State == HAL_NOR_STATE_BUSY)
00734   {
00735      return HAL_BUSY;
00736   }
00737
00738   /* Select the NOR device address */
00739   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00740   {
00741     deviceaddress = NOR_MEMORY_ADRESS1;
00742   }
00743   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00744   {
00745     deviceaddress = NOR_MEMORY_ADRESS2;
00746   }
00747   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00748   {
00749     deviceaddress = NOR_MEMORY_ADRESS3;
00750   }
00751   else /* FMC_NORSRAM_BANK4 */
00752   {
00753     deviceaddress = NOR_MEMORY_ADRESS4;
00754   }
00755
00756   /* Update the NOR controller state */
00757   hnor->State = HAL_NOR_STATE_BUSY;
00758
00759   /* Send NOR chip erase command sequence */
00760   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00761   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00762   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00763   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00764   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00765   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
00766
00767   /* Check the NOR memory status and update the controller state */
00768   hnor->State = HAL_NOR_STATE_READY;
00769
00770   /* Process unlocked */
00771   __HAL_UNLOCK(hnor);
00772
00773   return HAL_OK;
00774 }
00775
00776 /**
00777   * @brief  Read NOR flash CFI IDs
00778   * @param  hnor: pointer to the NOR handle
00779   * @param  pNOR_CFI : pointer to NOR CFI IDs structure
00780   * @retval HAL status
00781   */
00782 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
00783 {
00784   uint32_t deviceaddress = 0U;
00785
00786   /* Process Locked */
00787   __HAL_LOCK(hnor);
00788
00789   /* Check the NOR controller state */
00790   if(hnor->State == HAL_NOR_STATE_BUSY)
00791   {
00792      return HAL_BUSY;
00793   }
00794
00795   /* Select the NOR device address */
00796   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00797   {
00798     deviceaddress = NOR_MEMORY_ADRESS1;
00799   }
00800   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00801   {
00802     deviceaddress = NOR_MEMORY_ADRESS2;
00803   }
00804   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00805   {
00806     deviceaddress = NOR_MEMORY_ADRESS3;
00807   }
00808   else /* FMC_NORSRAM_BANK4 */
00809   {
00810     deviceaddress = NOR_MEMORY_ADRESS4;
00811   }
00812
00813   /* Update the NOR controller state */
00814   hnor->State = HAL_NOR_STATE_BUSY;
00815
00816   /* Send read CFI query command */
00817   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00818
00819   /* read the NOR CFI information */
00820   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
00821   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
00822   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
00823   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
00824
00825   /* Check the NOR controller state */
00826   hnor->State = HAL_NOR_STATE_READY;
00827
00828   /* Process unlocked */
00829   __HAL_UNLOCK(hnor);
00830
00831   return HAL_OK;
00832 }
00833
00834 /**
00835   * @}
00836   */
00837
00838 /** @defgroup NOR_Exported_Functions_Group3 Control functions
00839  *  @brief   management functions
00840  *
00841 @verbatim
00842   ==============================================================================
00843                         ##### NOR Control functions #####
00844   ==============================================================================
00845   [..]
00846     This subsection provides a set of functions allowing to control dynamically
00847     the NOR interface.
00848
00849 @endverbatim
00850   * @{
00851   */
00852
00853 /**
00854   * @brief  Enables dynamically NOR write operation.
00855   * @param  hnor: pointer to the NOR handle
00856   * @retval HAL status
00857   */
00858 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
00859 {
00860   /* Process Locked */
00861   __HAL_LOCK(hnor);
00862
00863   /* Enable write operation */
00864   FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
00865
00866   /* Update the NOR controller state */
00867   hnor->State = HAL_NOR_STATE_READY;
00868
00869   /* Process unlocked */
00870   __HAL_UNLOCK(hnor);
00871
00872   return HAL_OK;
00873 }
00874
00875 /**
00876   * @brief  Disables dynamically NOR write operation.
00877   * @param  hnor: pointer to the NOR handle
00878   * @retval HAL status
00879   */
00880 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
00881 {
00882   /* Process Locked */
00883   __HAL_LOCK(hnor);
00884
00885   /* Update the SRAM controller state */
00886   hnor->State = HAL_NOR_STATE_BUSY;
00887
00888   /* Disable write operation */
00889   FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
00890
00891   /* Update the NOR controller state */
00892   hnor->State = HAL_NOR_STATE_PROTECTED;
00893
00894   /* Process unlocked */
00895   __HAL_UNLOCK(hnor);
00896
00897   return HAL_OK;
00898 }
00899
00900 /**
00901   * @}
00902   */
00903
00904 /** @defgroup NOR_Exported_Functions_Group4 State functions
00905  *  @brief   Peripheral State functions
00906  *
00907 @verbatim
00908   ==============================================================================
00909                       ##### NOR State functions #####
00910   ==============================================================================
00911   [..]
00912     This subsection permits to get in run-time the status of the NOR controller
00913     and the data flow.
00914
00915 @endverbatim
00916   * @{
00917   */
00918
00919 /**
00920   * @brief  return the NOR controller state
00921   * @param  hnor: pointer to the NOR handle
00922   * @retval NOR controller state
00923   */
00924 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
00925 {
00926   return hnor->State;
00927 }
00928
00929 /**
00930   * @brief  Returns the NOR operation status.
00931   * @param  hnor: pointer to the NOR handle
00932   * @param  Address: Device address
00933   * @param  Timeout: NOR programming Timeout
00934   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
00935   *         or HAL_NOR_STATUS_TIMEOUT
00936   */
00937 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
00938 {
00939   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
00940   uint16_t tmpSR1 = 0U, tmpSR2 = 0U;
00941   uint32_t tickstart = 0U;
00942
00943   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
00944   HAL_NOR_MspWait(hnor, Timeout);
00945
00946   /* Get the NOR memory operation status -------------------------------------*/
00947
00948   /* Get tick */
00949   tickstart = HAL_GetTick();
00950   while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
00951   {
00952     /* Check for the Timeout */
00953     if(Timeout != HAL_MAX_DELAY)
00954     {
00955       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00956       {
00957         status = HAL_NOR_STATUS_TIMEOUT;
00958       }
00959     }
00960
00961     /* Read NOR status register (DQ6 and DQ5) */
00962     tmpSR1 = *(__IO uint16_t *)Address;
00963     tmpSR2 = *(__IO uint16_t *)Address;
00964
00965     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
00966     if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
00967     {
00968       return HAL_NOR_STATUS_SUCCESS ;
00969     }
00970
00971     if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
00972     {
00973       status = HAL_NOR_STATUS_ONGOING;
00974     }
00975
00976     tmpSR1 = *(__IO uint16_t *)Address;
00977     tmpSR2 = *(__IO uint16_t *)Address;
00978
00979     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
00980     if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
00981     {
00982       return HAL_NOR_STATUS_SUCCESS;
00983     }
00984     if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
00985     {
00986       return HAL_NOR_STATUS_ERROR;
00987     }
00988   }
00989
00990   /* Return the operation status */
00991   return status;
00992 }
00993
00994 /**
00995   * @}
00996   */
00997
00998
00999 /**
01000   * @}
01001   */
01002 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
01003           STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
01004           STM32F479xx */
01005 #endif /* HAL_NOR_MODULE_ENABLED */
01006 /**
01007   * @}
01008   */
01009
01010 /**
01011   * @}
01012   */
01013
01014 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_nor.h Source File

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stm32f4xx_hal_nor.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of NOR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_NOR_H
00040 #define __STM32F4xx_HAL_NOR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00048   #include "stm32f4xx_ll_fsmc.h"
00049 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00050
00051 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00052     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00053   #include "stm32f4xx_ll_fmc.h"
00054 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00055
00056 /** @addtogroup STM32F4xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @addtogroup NOR
00061   * @{
00062   */
00063
00064 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00065     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00066     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00067
00068 /* Exported typedef ----------------------------------------------------------*/
00069 /** @defgroup NOR_Exported_Types NOR Exported Types
00070   * @{
00071   */
00072
00073 /**
00074   * @brief  HAL SRAM State structures definition
00075   */
00076 typedef enum
00077 {
00078   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
00079   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
00080   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
00081   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
00082   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
00083 }HAL_NOR_StateTypeDef;
00084
00085 /**
00086   * @brief  FMC NOR Status typedef
00087   */
00088 typedef enum
00089 {
00090   HAL_NOR_STATUS_SUCCESS  = 0U,
00091   HAL_NOR_STATUS_ONGOING,
00092   HAL_NOR_STATUS_ERROR,
00093   HAL_NOR_STATUS_TIMEOUT
00094 }HAL_NOR_StatusTypeDef;
00095
00096 /**
00097   * @brief  FMC NOR ID typedef
00098   */
00099 typedef struct
00100 {
00101   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00102
00103   uint16_t Device_Code1;
00104
00105   uint16_t Device_Code2;
00106
00107   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00108                                     These codes can be accessed by performing read operations with specific
00109                                     control signals and addresses set.They can also be accessed by issuing
00110                                     an Auto Select command                                                   */
00111 }NOR_IDTypeDef;
00112
00113 /**
00114   * @brief  FMC NOR CFI typedef
00115   */
00116 typedef struct
00117 {
00118   /*!< Defines the information stored in the memory's Common flash interface
00119        which contains a description of various electrical and timing parameters,
00120        density information and functions supported by the memory                   */
00121
00122   uint16_t CFI_1;
00123
00124   uint16_t CFI_2;
00125
00126   uint16_t CFI_3;
00127
00128   uint16_t CFI_4;
00129 }NOR_CFITypeDef;
00130
00131 /**
00132   * @brief  NOR handle Structure definition
00133   */
00134 typedef struct
00135 {
00136   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00137
00138   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00139
00140   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00141
00142   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00143
00144   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00145
00146 }NOR_HandleTypeDef;
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported constants --------------------------------------------------------*/
00152 /* Exported macros ------------------------------------------------------------*/
00153 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00154   * @{
00155   */
00156 /** @brief Reset NOR handle state
00157   * @param  __HANDLE__: specifies the NOR handle.
00158   * @retval None
00159   */
00160 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00161 /**
00162   * @}
00163   */
00164
00165 /* Exported functions --------------------------------------------------------*/
00166 /** @addtogroup NOR_Exported_Functions
00167  *  @{
00168  */
00169
00170 /** @addtogroup NOR_Exported_Functions_Group1
00171  *  @{
00172  */
00173 /* Initialization/de-initialization functions  ********************************/
00174 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00175 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00176 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00177 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00178 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00179 /**
00180   * @}
00181   */
00182
00183 /** @addtogroup NOR_Exported_Functions_Group2
00184  *  @{
00185  */
00186 /* I/O operation functions  ***************************************************/
00187 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00188 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00189 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00190 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00191
00192 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00193 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00194
00195 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00196 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00197 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00198 /**
00199   * @}
00200   */
00201
00202 /** @addtogroup NOR_Exported_Functions_Group3
00203  *  @{
00204  */
00205 /* NOR Control functions  *****************************************************/
00206 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00207 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00208 /**
00209   * @}
00210   */
00211
00212 /** @addtogroup NOR_Exported_Functions_Group4
00213  *  @{
00214  */
00215 /* NOR State functions ********************************************************/
00216 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00217 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /* Private types -------------------------------------------------------------*/
00227 /* Private variables ---------------------------------------------------------*/
00228 /* Private constants ---------------------------------------------------------*/
00229 /** @defgroup NOR_Private_Constants NOR Private Constants
00230   * @{
00231   */
00232 /* NOR device IDs addresses */
00233 #define MC_ADDRESS               ((uint16_t)0x0000U)
00234 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
00235 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
00236 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
00237
00238 /* NOR CFI IDs addresses */
00239 #define CFI1_ADDRESS             ((uint16_t)0x0061U)
00240 #define CFI2_ADDRESS             ((uint16_t)0x0062U)
00241 #define CFI3_ADDRESS             ((uint16_t)0x0063U)
00242 #define CFI4_ADDRESS             ((uint16_t)0x0064U)
00243
00244 /* NOR operation wait timeout */
00245 #define NOR_TMEOUT               ((uint16_t)0xFFFFU)
00246
00247 /* NOR memory data width */
00248 #define NOR_MEMORY_8B            ((uint8_t)0x00U)
00249 #define NOR_MEMORY_16B           ((uint8_t)0x01U)
00250
00251 /* NOR memory device read/write start address */
00252 #define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)
00253 #define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)
00254 #define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)
00255 #define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)
00256 /**
00257   * @}
00258   */
00259
00260 /* Private macros ------------------------------------------------------------*/
00261 /** @defgroup NOR_Private_Macros NOR Private Macros
00262   * @{
00263   */
00264 /**
00265   * @brief  NOR memory address shifting.
00266   * @param  __NOR_ADDRESS__: NOR base address
00267   * @param  NOR_MEMORY_WIDTH: NOR memory width
00268   * @param  ADDRESS: NOR memory address
00269   * @retval NOR shifted address value
00270   */
00271 #define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS)    (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
00272                                                                                  ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
00273
00274 /**
00275   * @brief  NOR memory write data to specified address.
00276   * @param  ADDRESS: NOR memory address
00277   * @param  DATA: Data to write
00278   * @retval None
00279   */
00280 #define NOR_WRITE(ADDRESS, DATA)  (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
00281
00282 /**
00283   * @}
00284   */
00285 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00286           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
00287           STM32F446xx || STM32F469xx || STM32F479xx */
00288 /**
00289   * @}
00290   */
00291
00292 /**
00293   * @}
00294   */
00295
00296 #ifdef __cplusplus
00297 }
00298 #endif
00299
00300 #endif /* __STM32F4xx_HAL_NOR_H */
00301
00302 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pccard.c Source File

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stm32f4xx_hal_pccard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pccard.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   PCCARD HAL module driver.
00008   *          This file provides a generic firmware to drive PCCARD memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012  ===============================================================================
00013                         ##### How to use this driver #####
00014  ===============================================================================
00015    [..]
00016      This driver is a generic layered driver which contains a set of APIs used to
00017      control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions
00018      to interface with PCCARD devices. This driver is used for:
00019
00020     (+) PCCARD/Compact Flash memory configuration sequence using the function
00021         HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
00022         both common and attribute spaces.
00023
00024     (+) Read PCCARD/Compact Flash memory maker and device IDs using the function
00025         HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
00026         the CompactFlash_ID structure declared by the function caller.
00027
00028     (+) Access PCCARD/Compact Flash memory by read/write operations using the functions
00029         HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
00030         HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
00031
00032     (+) Perform PCCARD/Compact Flash Reset chip operation using the function
00033         HAL_PCCARD_Reset()/HAL_CF_Reset.
00034
00035     (+) Perform PCCARD/Compact Flash erase sector operation using the function
00036         HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
00037
00038     (+) Read the PCCARD/Compact Flash status operation using the function
00039         HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
00040
00041     (+) You can monitor the PCCARD/Compact Flash  device HAL state by calling
00042         the function HAL_PCCARD_GetState()/HAL_CF_GetState()
00043
00044    [..]
00045      (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
00046          operations. If a PCCARD/Compact Flash device contains different operations
00047          and/or implementations, it should be implemented separately.
00048
00049   @endverbatim
00050   ******************************************************************************
00051   * @attention
00052   *
00053   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00054   *
00055   * Redistribution and use in source and binary forms, with or without modification,
00056   * are permitted provided that the following conditions are met:
00057   *   1. Redistributions of source code must retain the above copyright notice,
00058   *      this list of conditions and the following disclaimer.
00059   *   2. Redistributions in binary form must reproduce the above copyright notice,
00060   *      this list of conditions and the following disclaimer in the documentation
00061   *      and/or other materials provided with the distribution.
00062   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00063   *      may be used to endorse or promote products derived from this software
00064   *      without specific prior written permission.
00065   *
00066   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00067   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00068   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00069   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00070   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00071   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00072   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00073   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00074   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00075   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00076   *
00077   ******************************************************************************
00078   */
00079
00080 /* Includes ------------------------------------------------------------------*/
00081 #include "stm32f4xx_hal.h"
00082
00083 /** @addtogroup STM32F4xx_HAL_Driver
00084   * @{
00085   */
00086
00087 #ifdef HAL_PCCARD_MODULE_ENABLED
00088 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00089     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
00090 /** @defgroup PCCARD PCCARD
00091   * @brief PCCARD HAL module driver
00092   * @{
00093   */
00094 /* Private typedef -----------------------------------------------------------*/
00095 /* Private define ------------------------------------------------------------*/
00096
00097 /** @defgroup PCCARD_Private_Defines PCCARD Private Defines
00098   * @{
00099   */
00100 #define PCCARD_TIMEOUT_READ_ID                 (uint32_t)0x0000FFFFU
00101 #define PCCARD_TIMEOUT_READ_WRITE_SECTOR       (uint32_t)0x0000FFFFU
00102 #define PCCARD_TIMEOUT_ERASE_SECTOR            (uint32_t)0x00000400U
00103 #define PCCARD_TIMEOUT_STATUS                  (uint32_t)0x01000000U
00104
00105 #define PCCARD_STATUS_OK                       (uint8_t)0x58U
00106 #define PCCARD_STATUS_WRITE_OK                 (uint8_t)0x50U
00107 /**
00108   * @}
00109   */
00110
00111 /* Private macro -------------------------------------------------------------*/
00112 /* Private variables ---------------------------------------------------------*/
00113 /* Private function ----------------------------------------------------------*/
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
00116   * @{
00117   */
00118
00119 /** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00120   * @brief    Initialization and Configuration functions
00121   *
00122   @verbatim
00123   ==============================================================================
00124           ##### PCCARD Initialization and de-initialization functions #####
00125   ==============================================================================
00126   [..]
00127     This section provides functions allowing to initialize/de-initialize
00128     the PCCARD memory
00129
00130 @endverbatim
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  Perform the PCCARD memory Initialization sequence
00136   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00137   *                the configuration information for PCCARD module.
00138   * @param  ComSpaceTiming: Common space timing structure
00139   * @param  AttSpaceTiming: Attribute space timing structure
00140   * @param  IOSpaceTiming: IO space timing structure
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
00144 {
00145   /* Check the PCCARD controller state */
00146   if(hpccard == NULL)
00147   {
00148      return HAL_ERROR;
00149   }
00150
00151   if(hpccard->State == HAL_PCCARD_STATE_RESET)
00152   {
00153     /* Allocate lock resource and initialize it */
00154     hpccard->Lock = HAL_UNLOCKED;
00155     /* Initialize the low level hardware (MSP) */
00156     HAL_PCCARD_MspInit(hpccard);
00157   }
00158
00159   /* Initialize the PCCARD state */
00160   hpccard->State = HAL_PCCARD_STATE_BUSY;
00161
00162   /* Initialize PCCARD control Interface */
00163   FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
00164
00165   /* Init PCCARD common space timing Interface */
00166   FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
00167
00168   /* Init PCCARD attribute space timing Interface */
00169   FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
00170
00171   /* Init PCCARD IO space timing Interface */
00172   FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
00173
00174   /* Enable the PCCARD device */
00175   __FMC_PCCARD_ENABLE(hpccard->Instance);
00176
00177   /* Update the PCCARD state */
00178   hpccard->State = HAL_PCCARD_STATE_READY;
00179
00180   return HAL_OK;
00181
00182 }
00183
00184 /**
00185   * @brief  Perform the PCCARD memory De-initialization sequence
00186   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00187   *                the configuration information for PCCARD module.
00188   * @retval HAL status
00189   */
00190 HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
00191 {
00192   /* De-Initialize the low level hardware (MSP) */
00193   HAL_PCCARD_MspDeInit(hpccard);
00194
00195   /* Configure the PCCARD registers with their reset values */
00196   FMC_PCCARD_DeInit(hpccard->Instance);
00197
00198   /* Update the PCCARD controller state */
00199   hpccard->State = HAL_PCCARD_STATE_RESET;
00200
00201   /* Release Lock */
00202   __HAL_UNLOCK(hpccard);
00203
00204   return HAL_OK;
00205 }
00206
00207 /**
00208   * @brief  PCCARD MSP Init
00209   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00210   *                the configuration information for PCCARD module.
00211   * @retval None
00212   */
00213 __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
00214 {
00215   /* Prevent unused argument(s) compilation warning */
00216   UNUSED(hpccard);
00217   /* NOTE : This function Should not be modified, when the callback is needed,
00218             the HAL_PCCARD_MspInit could be implemented in the user file
00219    */
00220 }
00221
00222 /**
00223   * @brief  PCCARD MSP DeInit
00224   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00225   *                the configuration information for PCCARD module.
00226   * @retval None
00227   */
00228 __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
00229 {
00230   /* Prevent unused argument(s) compilation warning */
00231   UNUSED(hpccard);
00232   /* NOTE : This function Should not be modified, when the callback is needed,
00233             the HAL_PCCARD_MspDeInit could be implemented in the user file
00234    */
00235 }
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
00242   * @brief    Input Output and memory control functions
00243   *
00244   @verbatim
00245   ==============================================================================
00246                     ##### PCCARD Input and Output functions #####
00247   ==============================================================================
00248   [..]
00249     This section provides functions allowing to use and control the PCCARD memory
00250
00251 @endverbatim
00252   * @{
00253   */
00254
00255 /**
00256   * @brief  Read Compact Flash's ID.
00257   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00258   *                the configuration information for PCCARD module.
00259   * @param  CompactFlash_ID: Compact flash ID structure.
00260   * @param  pStatus: pointer to compact flash status
00261   * @retval HAL status
00262   *
00263   */
00264 HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
00265 {
00266   uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
00267   uint8_t status = 0U;
00268
00269   /* Process Locked */
00270   __HAL_LOCK(hpccard);
00271
00272   /* Check the PCCARD controller state */
00273   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00274   {
00275      return HAL_BUSY;
00276   }
00277
00278   /* Update the PCCARD controller state */
00279   hpccard->State = HAL_PCCARD_STATE_BUSY;
00280
00281   /* Initialize the PCCARD status */
00282   *pStatus = PCCARD_READY;
00283
00284   /* Send the Identify Command */
00285   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)  = 0xECECU;
00286
00287   /* Read PCCARD IDs and timeout treatment */
00288   do
00289   {
00290      /* Read the PCCARD status */
00291      status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00292
00293      timeout--;
00294   }while((status != PCCARD_STATUS_OK) && timeout);
00295
00296   if(timeout == 0U)
00297   {
00298     *pStatus = PCCARD_TIMEOUT_ERROR;
00299   }
00300   else
00301   {
00302      /* Read PCCARD ID bytes */
00303     for(index = 0U; index < 16U; index++)
00304     {
00305       CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
00306     }
00307   }
00308
00309   /* Update the PCCARD controller state */
00310   hpccard->State = HAL_PCCARD_STATE_READY;
00311
00312   /* Process unlocked */
00313   __HAL_UNLOCK(hpccard);
00314
00315   return HAL_OK;
00316 }
00317
00318 /**
00319   * @brief  Read sector from PCCARD memory
00320   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00321   *                the configuration information for PCCARD module.
00322   * @param  pBuffer: pointer to destination read buffer
00323   * @param  SectorAddress: Sector address to read
00324   * @param  pStatus: pointer to PCCARD status
00325   * @retval HAL status
00326   */
00327 HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
00328 {
00329   uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
00330   uint8_t status = 0U;
00331
00332   /* Process Locked */
00333   __HAL_LOCK(hpccard);
00334
00335   /* Check the PCCARD controller state */
00336   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00337   {
00338      return HAL_BUSY;
00339   }
00340
00341   /* Update the PCCARD controller state */
00342   hpccard->State = HAL_PCCARD_STATE_BUSY;
00343
00344   /* Initialize PCCARD status */
00345   *pStatus = PCCARD_READY;
00346
00347   /* Set the parameters to write a sector */
00348   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00U;
00349   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100U ) | ((uint16_t)SectorAddress);
00350   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0xE4A0U;
00351
00352   do
00353   {
00354     /* wait till the Status = 0x80 */
00355     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00356     timeout--;
00357   }while((status == 0x80U) && timeout);
00358
00359   if(timeout == 0U)
00360   {
00361     *pStatus = PCCARD_TIMEOUT_ERROR;
00362   }
00363
00364   timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
00365
00366   do
00367   {
00368     /* wait till the Status = PCCARD_STATUS_OK */
00369     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00370     timeout--;
00371   }while((status != PCCARD_STATUS_OK) && timeout);
00372
00373   if(timeout == 0U)
00374   {
00375     *pStatus = PCCARD_TIMEOUT_ERROR;
00376   }
00377
00378   /* Read bytes */
00379   for(; index < PCCARD_SECTOR_SIZE; index++)
00380   {
00381     *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
00382   }
00383
00384   /* Update the PCCARD controller state */
00385   hpccard->State = HAL_PCCARD_STATE_READY;
00386
00387   /* Process unlocked */
00388   __HAL_UNLOCK(hpccard);
00389
00390   return HAL_OK;
00391 }
00392
00393
00394 /**
00395   * @brief  Write sector to PCCARD memory
00396   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00397   *                the configuration information for PCCARD module.
00398   * @param  pBuffer: pointer to source write buffer
00399   * @param  SectorAddress: Sector address to write
00400   * @param  pStatus: pointer to PCCARD status
00401   * @retval HAL status
00402   */
00403 HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus)
00404 {
00405   uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
00406   uint8_t status = 0U;
00407
00408   /* Process Locked */
00409   __HAL_LOCK(hpccard);
00410
00411   /* Check the PCCARD controller state */
00412   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00413   {
00414      return HAL_BUSY;
00415   }
00416
00417   /* Update the PCCARD controller state */
00418   hpccard->State = HAL_PCCARD_STATE_BUSY;
00419
00420   /* Initialize PCCARD status */
00421   *pStatus = PCCARD_READY;
00422
00423   /* Set the parameters to write a sector */
00424   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00U;
00425   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100U ) | ((uint16_t)SectorAddress);
00426   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0x30A0U;
00427
00428   do
00429   {
00430     /* Wait till the Status = PCCARD_STATUS_OK */
00431     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00432     timeout--;
00433   }while((status != PCCARD_STATUS_OK) && timeout);
00434
00435   if(timeout == 0U)
00436   {
00437     *pStatus = PCCARD_TIMEOUT_ERROR;
00438   }
00439
00440   /* Write bytes */
00441   for(; index < PCCARD_SECTOR_SIZE; index++)
00442   {
00443     *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
00444   }
00445
00446   do
00447   {
00448     /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
00449     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00450     timeout--;
00451   }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
00452
00453   if(timeout == 0U)
00454   {
00455     *pStatus = PCCARD_TIMEOUT_ERROR;
00456   }
00457
00458   /* Update the PCCARD controller state */
00459   hpccard->State = HAL_PCCARD_STATE_READY;
00460
00461   /* Process unlocked */
00462   __HAL_UNLOCK(hpccard);
00463
00464   return HAL_OK;
00465 }
00466
00467
00468 /**
00469   * @brief  Erase sector from PCCARD memory
00470   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00471   *                the configuration information for PCCARD module.
00472   * @param  SectorAddress: Sector address to erase
00473   * @param  pStatus: pointer to PCCARD status
00474   * @retval HAL status
00475   */
00476 HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
00477 {
00478   uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
00479   uint8_t status = 0U;
00480
00481   /* Process Locked */
00482   __HAL_LOCK(hpccard);
00483
00484   /* Check the PCCARD controller state */
00485   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00486   {
00487      return HAL_BUSY;
00488   }
00489
00490   /* Update the PCCARD controller state */
00491   hpccard->State = HAL_PCCARD_STATE_BUSY;
00492
00493   /* Initialize PCCARD status */
00494   *pStatus = PCCARD_READY;
00495
00496   /* Set the parameters to write a sector */
00497   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW)  = 0x00U;
00498   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00U;
00499   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
00500   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = 0x01U;
00501   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD)     = 0xA0U;
00502   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = ATA_ERASE_SECTOR_CMD;
00503
00504   /* wait till the PCCARD is ready */
00505   status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00506
00507   while((status != PCCARD_STATUS_WRITE_OK) && timeout)
00508   {
00509     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00510     timeout--;
00511   }
00512
00513   if(timeout == 0U)
00514   {
00515     *pStatus = PCCARD_TIMEOUT_ERROR;
00516   }
00517
00518   /* Check the PCCARD controller state */
00519   hpccard->State = HAL_PCCARD_STATE_READY;
00520
00521   /* Process unlocked */
00522   __HAL_UNLOCK(hpccard);
00523
00524   return HAL_OK;
00525 }
00526
00527 /**
00528   * @brief  Reset the PCCARD memory
00529   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00530   *                the configuration information for PCCARD module.
00531   * @retval HAL status
00532   */
00533 HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
00534 {
00535   /* Process Locked */
00536   __HAL_LOCK(hpccard);
00537
00538   /* Check the PCCARD controller state */
00539   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00540   {
00541      return HAL_BUSY;
00542   }
00543
00544   /* Provide a SW reset and Read and verify the:
00545    - PCCard Configuration Option Register at address 0x98000200 --> 0x80
00546    - Card Configuration and Status Register at address 0x98000202 --> 0x00
00547    - Pin Replacement Register at address 0x98000204 --> 0x0C
00548    - Socket and Copy Register at address 0x98000206 --> 0x00
00549   */
00550
00551   /* Check the PCCARD controller state */
00552   hpccard->State = HAL_PCCARD_STATE_BUSY;
00553
00554   *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01U;
00555
00556   /* Check the PCCARD controller state */
00557   hpccard->State = HAL_PCCARD_STATE_READY;
00558
00559   /* Process unlocked */
00560   __HAL_UNLOCK(hpccard);
00561
00562   return HAL_OK;
00563 }
00564
00565 /**
00566   * @brief  This function handles PCCARD device interrupt request.
00567   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00568   *                the configuration information for PCCARD module.
00569   * @retval HAL status
00570 */
00571 void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
00572 {
00573   /* Check PCCARD interrupt Rising edge flag */
00574   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
00575   {
00576     /* PCCARD interrupt callback*/
00577     HAL_PCCARD_ITCallback(hpccard);
00578
00579     /* Clear PCCARD interrupt Rising edge pending bit */
00580     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
00581   }
00582
00583   /* Check PCCARD interrupt Level flag */
00584   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
00585   {
00586     /* PCCARD interrupt callback*/
00587     HAL_PCCARD_ITCallback(hpccard);
00588
00589     /* Clear PCCARD interrupt Level pending bit */
00590     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
00591   }
00592
00593   /* Check PCCARD interrupt Falling edge flag */
00594   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
00595   {
00596     /* PCCARD interrupt callback*/
00597     HAL_PCCARD_ITCallback(hpccard);
00598
00599     /* Clear PCCARD interrupt Falling edge pending bit */
00600     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
00601   }
00602
00603   /* Check PCCARD interrupt FIFO empty flag */
00604   if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
00605   {
00606     /* PCCARD interrupt callback*/
00607     HAL_PCCARD_ITCallback(hpccard);
00608
00609     /* Clear PCCARD interrupt FIFO empty pending bit */
00610     __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
00611   }
00612 }
00613
00614 /**
00615   * @brief  PCCARD interrupt feature callback
00616   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00617   *                the configuration information for PCCARD module.
00618   * @retval None
00619   */
00620 __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
00621 {
00622   /* Prevent unused argument(s) compilation warning */
00623   UNUSED(hpccard);
00624   /* NOTE : This function Should not be modified, when the callback is needed,
00625             the HAL_PCCARD_ITCallback could be implemented in the user file
00626    */
00627 }
00628
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup PCCARD_Exported_Functions_Group3 State functions
00634  *  @brief   Peripheral State functions
00635  *
00636 @verbatim
00637   ==============================================================================
00638                       ##### PCCARD State functions #####
00639   ==============================================================================
00640   [..]
00641     This subsection permits to get in run-time the status of the PCCARD controller
00642     and the data flow.
00643
00644 @endverbatim
00645   * @{
00646   */
00647
00648 /**
00649   * @brief  return the PCCARD controller state
00650   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00651   *                the configuration information for PCCARD module.
00652   * @retval HAL state
00653   */
00654 HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
00655 {
00656   return hpccard->State;
00657 }
00658
00659 /**
00660   * @brief  Get the compact flash memory status
00661   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00662   *                the configuration information for PCCARD module.
00663   * @retval New status of the PCCARD operation. This parameter can be:
00664   *          - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
00665   *            a Timeout error
00666   *          - CompactFlash_READY: when memory is ready for the next operation
00667   */
00668 HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
00669 {
00670   uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U;
00671
00672   /* Check the PCCARD controller state */
00673   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00674   {
00675      return HAL_PCCARD_STATUS_ONGOING;
00676   }
00677
00678   status_pccard =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00679
00680   while((status_pccard == PCCARD_BUSY) && timeout)
00681   {
00682     status_pccard =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00683     timeout--;
00684   }
00685
00686   if(timeout == 0U)
00687   {
00688     status_pccard =  PCCARD_TIMEOUT_ERROR;
00689   }
00690
00691   /* Return the operation status */
00692   return (HAL_PCCARD_StatusTypeDef) status_pccard;
00693 }
00694
00695 /**
00696   * @brief  Reads the Compact Flash memory status using the Read status command
00697   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00698   *                the configuration information for PCCARD module.
00699   * @retval The status of the Compact Flash memory. This parameter can be:
00700   *          - CompactFlash_BUSY: when memory is busy
00701   *          - CompactFlash_READY: when memory is ready for the next operation
00702   *          - CompactFlash_ERROR: when the previous operation generates error
00703   */
00704 HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
00705 {
00706   uint8_t data = 0U, status_pccard = PCCARD_BUSY;
00707
00708   /* Check the PCCARD controller state */
00709   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00710   {
00711      return HAL_PCCARD_STATUS_ONGOING;
00712   }
00713
00714   /* Read status operation */
00715   data =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00716
00717   if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
00718   {
00719     status_pccard = PCCARD_TIMEOUT_ERROR;
00720   }
00721   else if((data & PCCARD_READY) == PCCARD_READY)
00722   {
00723     status_pccard = PCCARD_READY;
00724   }
00725
00726   return (HAL_PCCARD_StatusTypeDef) status_pccard;
00727 }
00728
00729 /**
00730   * @}
00731   */
00732
00733 /**
00734   * @}
00735   */
00736 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00737           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
00738 #endif /* HAL_PCCARD_MODULE_ENABLED */
00739
00740 /**
00741   * @}
00742   */
00743
00744 /**
00745   * @}
00746   */
00747
00748 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pccard.h Source File

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stm32f4xx_hal_pccard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pccard.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of PCCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_PCCARD_H
00040 #define __STM32F4xx_HAL_PCCARD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00048   #include "stm32f4xx_ll_fsmc.h"
00049 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00050
00051 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
00052   #include "stm32f4xx_ll_fmc.h"
00053 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
00054
00055 /** @addtogroup STM32F4xx_HAL_Driver
00056   * @{
00057   */
00058
00059 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00060     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
00061
00062 /** @addtogroup PCCARD
00063   * @{
00064   */
00065
00066 /* Exported typedef ----------------------------------------------------------*/
00067 /** @defgroup PCCARD_Exported_Types PCCARD Exported Types
00068   * @{
00069   */
00070
00071 /**
00072   * @brief  HAL PCCARD State structures definition
00073   */
00074 typedef enum
00075 {
00076   HAL_PCCARD_STATE_RESET     = 0x00U,    /*!< PCCARD peripheral not yet initialized or disabled */
00077   HAL_PCCARD_STATE_READY     = 0x01U,    /*!< PCCARD peripheral ready                           */
00078   HAL_PCCARD_STATE_BUSY      = 0x02U,    /*!< PCCARD peripheral busy                            */
00079   HAL_PCCARD_STATE_ERROR     = 0x04U     /*!< PCCARD peripheral error                           */
00080 }HAL_PCCARD_StateTypeDef;
00081
00082 typedef enum
00083 {
00084   HAL_PCCARD_STATUS_SUCCESS = 0U,
00085   HAL_PCCARD_STATUS_ONGOING,
00086   HAL_PCCARD_STATUS_ERROR,
00087   HAL_PCCARD_STATUS_TIMEOUT
00088 }HAL_PCCARD_StatusTypeDef;
00089
00090 /**
00091   * @brief  FMC_PCCARD handle Structure definition
00092   */
00093 typedef struct
00094 {
00095   FMC_PCCARD_TypeDef           *Instance;              /*!< Register base address for PCCARD device          */
00096
00097   FMC_PCCARD_InitTypeDef       Init;                   /*!< PCCARD device control configuration parameters   */
00098
00099   __IO HAL_PCCARD_StateTypeDef State;                  /*!< PCCARD device access state                       */
00100
00101   HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */
00102
00103 }PCCARD_HandleTypeDef;
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported constants --------------------------------------------------------*/
00109 /* Exported macro ------------------------------------------------------------*/
00110 /** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
00111   * @{
00112   */
00113 /** @brief Reset PCCARD handle state
00114   * @param  __HANDLE__: specifies the PCCARD handle.
00115   * @retval None
00116   */
00117 #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
00118 /**
00119   * @}
00120   */
00121
00122 /* Exported functions --------------------------------------------------------*/
00123 /** @addtogroup PCCARD_Exported_Functions
00124   * @{
00125   */
00126
00127 /** @addtogroup PCCARD_Exported_Functions_Group1
00128   * @{
00129   */
00130 /* Initialization/de-initialization functions  **********************************/
00131 HAL_StatusTypeDef  HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
00132 HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
00133 void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
00134 void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
00135 /**
00136   * @}
00137   */
00138
00139 /** @addtogroup PCCARD_Exported_Functions_Group2
00140   * @{
00141   */
00142 /* IO operation functions  *****************************************************/
00143 HAL_StatusTypeDef  HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
00144 HAL_StatusTypeDef  HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus);
00145 HAL_StatusTypeDef  HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
00146 HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
00147 HAL_StatusTypeDef  HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
00148 void               HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
00149 void               HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
00150
00151 /**
00152   * @}
00153   */
00154
00155 /** @addtogroup PCCARD_Exported_Functions_Group3
00156   * @{
00157   */
00158 /* PCCARD State functions *******************************************************/
00159 HAL_PCCARD_StateTypeDef  HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
00160 HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
00161 HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
00162 /**
00163   * @}
00164   */
00165
00166 /**
00167   * @}
00168   */
00169 /* Private types -------------------------------------------------------------*/
00170 /* Private variables ---------------------------------------------------------*/
00171 /* Private constants ---------------------------------------------------------*/
00172 /** @defgroup PCCARD_Private_Constants PCCARD Private Constants
00173   * @{
00174   */
00175 #define PCCARD_DEVICE_ADDRESS             ((uint32_t)0x90000000U)
00176 #define PCCARD_ATTRIBUTE_SPACE_ADDRESS    ((uint32_t)0x98000000U)   /* Attribute space size to @0x9BFF FFFF */
00177 #define PCCARD_COMMON_SPACE_ADDRESS       PCCARD_DEVICE_ADDRESS    /* Common space size to @0x93FF FFFF    */
00178 #define PCCARD_IO_SPACE_ADDRESS           ((uint32_t)0x9C000000U)   /* IO space size to @0x9FFF FFFF        */
00179 #define PCCARD_IO_SPACE_PRIMARY_ADDR      ((uint32_t)0x9C0001F0U)   /* IO space size to @0x9FFF FFFF        */
00180
00181 /* Flash-ATA registers description */
00182 #define ATA_DATA                       ((uint8_t)0x00U)    /* Data register */
00183 #define ATA_SECTOR_COUNT               ((uint8_t)0x02U)    /* Sector Count register */
00184 #define ATA_SECTOR_NUMBER              ((uint8_t)0x03U)    /* Sector Number register */
00185 #define ATA_CYLINDER_LOW               ((uint8_t)0x04U)    /* Cylinder low register */
00186 #define ATA_CYLINDER_HIGH              ((uint8_t)0x05U)    /* Cylinder high register */
00187 #define ATA_CARD_HEAD                  ((uint8_t)0x06U)    /* Card/Head register */
00188 #define ATA_STATUS_CMD                 ((uint8_t)0x07U)    /* Status(read)/Command(write) register */
00189 #define ATA_STATUS_CMD_ALTERNATE       ((uint8_t)0x0EU)    /* Alternate Status(read)/Command(write) register */
00190 #define ATA_COMMON_DATA_AREA           ((uint16_t)0x0400U) /* Start of data area (for Common access only!) */
00191 #define ATA_CARD_CONFIGURATION         ((uint16_t)0x0202U) /* Card Configuration and Status Register */
00192
00193 /* Flash-ATA commands */
00194 #define ATA_READ_SECTOR_CMD            ((uint8_t)0x20U)
00195 #define ATA_WRITE_SECTOR_CMD           ((uint8_t)0x30U)
00196 #define ATA_ERASE_SECTOR_CMD           ((uint8_t)0xC0)
00197 #define ATA_IDENTIFY_CMD               ((uint8_t)0xEC)
00198
00199 /* PC Card/Compact Flash status */
00200 #define PCCARD_TIMEOUT_ERROR           ((uint8_t)0x60U)
00201 #define PCCARD_BUSY                    ((uint8_t)0x80U)
00202 #define PCCARD_PROGR                   ((uint8_t)0x01U)
00203 #define PCCARD_READY                   ((uint8_t)0x40U)
00204
00205 #define PCCARD_SECTOR_SIZE             ((uint32_t)255U)    /* In half words */
00206
00207 /**
00208   * @}
00209   */
00210 /* Compact Flash redefinition */
00211 #define HAL_CF_Init                 HAL_PCCARD_Init
00212 #define HAL_CF_DeInit               HAL_PCCARD_DeInit
00213 #define HAL_CF_MspInit              HAL_PCCARD_MspInit
00214 #define HAL_CF_MspDeInit            HAL_PCCARD_MspDeInit
00215
00216 #define HAL_CF_Read_ID              HAL_PCCARD_Read_ID
00217 #define HAL_CF_Write_Sector         HAL_PCCARD_Write_Sector
00218 #define HAL_CF_Read_Sector          HAL_PCCARD_Read_Sector
00219 #define HAL_CF_Erase_Sector         HAL_PCCARD_Erase_Sector
00220 #define HAL_CF_Reset                HAL_PCCARD_Reset
00221 #define HAL_CF_IRQHandler           HAL_PCCARD_IRQHandler
00222 #define HAL_CF_ITCallback           HAL_PCCARD_ITCallback
00223
00224 #define HAL_CF_GetState             HAL_PCCARD_GetState
00225 #define HAL_CF_GetStatus            HAL_PCCARD_GetStatus
00226 #define HAL_CF_ReadStatus           HAL_PCCARD_ReadStatus
00227
00228 #define HAL_CF_STATUS_SUCCESS       HAL_PCCARD_STATUS_SUCCESS
00229 #define HAL_CF_STATUS_ONGOING       HAL_PCCARD_STATUS_ONGOING
00230 #define HAL_CF_STATUS_ERROR         HAL_PCCARD_STATUS_ERROR
00231 #define HAL_CF_STATUS_TIMEOUT       HAL_PCCARD_STATUS_TIMEOUT
00232 #define HAL_CF_StatusTypeDef        HAL_PCCARD_StatusTypeDef
00233
00234 #define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS
00235 #define CF_ATTRIBUTE_SPACE_ADDRESS  PCCARD_ATTRIBUTE_SPACE_ADDRESS
00236 #define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS
00237 #define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS
00238 #define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR
00239
00240 #define CF_TIMEOUT_ERROR            PCCARD_TIMEOUT_ERROR
00241 #define CF_BUSY                     PCCARD_BUSY
00242 #define CF_PROGR                    PCCARD_PROGR
00243 #define CF_READY                    PCCARD_READY
00244
00245 #define CF_SECTOR_SIZE              PCCARD_SECTOR_SIZE
00246
00247 /* Private macros ------------------------------------------------------------*/
00248 /**
00249   * @}
00250   */
00251
00252 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
00253           STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
00254
00255
00256 /**
00257   * @}
00258   */
00259
00260 #ifdef __cplusplus
00261 }
00262 #endif
00263
00264 #endif /* __STM32F4xx_HAL_PCCARD_H */
00265
00266 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd.c Source File

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stm32f4xx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The PCD HAL driver can be used as follows:
00021
00022      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00023          PCD_HandleTypeDef  hpcd;
00024
00025      (#) Fill parameters of Init structure in HCD handle
00026
00027      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
00028
00029      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00030          (##) Enable the PCD/USB Low Level interface clock using
00031               (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
00032               (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
00033
00034          (##) Initialize the related GPIO clocks
00035          (##) Configure PCD pin-out
00036          (##) Configure PCD NVIC interrupt
00037
00038      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00039          (##) hpcd.pData = pdev;
00040
00041      (#)Enable PCD transmission and reception:
00042          (##) HAL_PCD_Start();
00043
00044   @endverbatim
00045   ******************************************************************************
00046   * @attention
00047   *
00048   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00049   *
00050   * Redistribution and use in source and binary forms, with or without modification,
00051   * are permitted provided that the following conditions are met:
00052   *   1. Redistributions of source code must retain the above copyright notice,
00053   *      this list of conditions and the following disclaimer.
00054   *   2. Redistributions in binary form must reproduce the above copyright notice,
00055   *      this list of conditions and the following disclaimer in the documentation
00056   *      and/or other materials provided with the distribution.
00057   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00058   *      may be used to endorse or promote products derived from this software
00059   *      without specific prior written permission.
00060   *
00061   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00062   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00063   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00064   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00065   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00066   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00067   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00068   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00069   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00070   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00071   *
00072   ******************************************************************************
00073   */
00074
00075 /* Includes ------------------------------------------------------------------*/
00076 #include "stm32f4xx_hal.h"
00077
00078 /** @addtogroup STM32F4xx_HAL_Driver
00079   * @{
00080   */
00081
00082 /** @defgroup PCD PCD
00083   * @brief PCD HAL module driver
00084   * @{
00085   */
00086
00087 #ifdef HAL_PCD_MODULE_ENABLED
00088 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00089     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00090     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00091     defined(STM32F469xx) || defined(STM32F479xx)
00092 /* Private types -------------------------------------------------------------*/
00093 /* Private variables ---------------------------------------------------------*/
00094 /* Private constants ---------------------------------------------------------*/
00095 /* Private macros ------------------------------------------------------------*/
00096 /** @defgroup PCD_Private_Macros PCD Private Macros
00097   * @{
00098   */
00099 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00100 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00101 /**
00102   * @}
00103   */
00104
00105 /* Private functions prototypes ----------------------------------------------*/
00106 /** @defgroup PCD_Private_Functions PCD Private Functions
00107   * @{
00108   */
00109 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00116   * @{
00117   */
00118
00119 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00120  *  @brief    Initialization and Configuration functions
00121  *
00122 @verbatim
00123  ===============================================================================
00124             ##### Initialization and de-initialization functions #####
00125  ===============================================================================
00126     [..]  This section provides functions allowing to:
00127
00128 @endverbatim
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  Initializes the PCD according to the specified
00134   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
00135   * @param  hpcd: PCD handle
00136   * @retval HAL status
00137   */
00138 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00139 {
00140   uint32_t i = 0U;
00141
00142   /* Check the PCD handle allocation */
00143   if(hpcd == NULL)
00144   {
00145     return HAL_ERROR;
00146   }
00147
00148   /* Check the parameters */
00149   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00150
00151   hpcd->State = HAL_PCD_STATE_BUSY;
00152
00153   /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00154   HAL_PCD_MspInit(hpcd);
00155
00156   /* Disable the Interrupts */
00157  __HAL_PCD_DISABLE(hpcd);
00158
00159  /*Init the Core (common init.) */
00160  USB_CoreInit(hpcd->Instance, hpcd->Init);
00161
00162  /* Force Device Mode*/
00163  USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
00164
00165  /* Init endpoints structures */
00166  for (i = 0U; i < 15U; i++)
00167  {
00168    /* Init ep structure */
00169    hpcd->IN_ep[i].is_in = 1U;
00170    hpcd->IN_ep[i].num = i;
00171    hpcd->IN_ep[i].tx_fifo_num = i;
00172    /* Control until ep is activated */
00173    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
00174    hpcd->IN_ep[i].maxpacket = 0U;
00175    hpcd->IN_ep[i].xfer_buff = 0U;
00176    hpcd->IN_ep[i].xfer_len = 0U;
00177  }
00178
00179  for (i = 0U; i < 15U; i++)
00180  {
00181    hpcd->OUT_ep[i].is_in = 0U;
00182    hpcd->OUT_ep[i].num = i;
00183    hpcd->IN_ep[i].tx_fifo_num = i;
00184    /* Control until ep is activated */
00185    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
00186    hpcd->OUT_ep[i].maxpacket = 0U;
00187    hpcd->OUT_ep[i].xfer_buff = 0U;
00188    hpcd->OUT_ep[i].xfer_len = 0U;
00189
00190    hpcd->Instance->DIEPTXF[i] = 0U;
00191  }
00192
00193  /* Init Device */
00194  USB_DevInit(hpcd->Instance, hpcd->Init);
00195
00196  hpcd->State= HAL_PCD_STATE_READY;
00197
00198 #ifdef USB_OTG_GLPMCFG_LPMEN
00199  /* Activate LPM */
00200  if (hpcd->Init.lpm_enable == 1U)
00201  {
00202    HAL_PCDEx_ActivateLPM(hpcd);
00203  }
00204 #endif /* USB_OTG_GLPMCFG_LPMEN */
00205
00206 #ifdef USB_OTG_GCCFG_BCDEN
00207  /* Activate Battery charging */
00208  if (hpcd->Init.battery_charging_enable == 1U)
00209  {
00210    HAL_PCDEx_ActivateBCD(hpcd);
00211  }
00212 #endif /* USB_OTG_GCCFG_BCDEN */
00213
00214  USB_DevDisconnect (hpcd->Instance);
00215  return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  DeInitializes the PCD peripheral.
00220   * @param  hpcd: PCD handle
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00224 {
00225   /* Check the PCD handle allocation */
00226   if(hpcd == NULL)
00227   {
00228     return HAL_ERROR;
00229   }
00230
00231   hpcd->State = HAL_PCD_STATE_BUSY;
00232
00233   /* Stop Device */
00234   HAL_PCD_Stop(hpcd);
00235
00236   /* DeInit the low level hardware */
00237   HAL_PCD_MspDeInit(hpcd);
00238
00239   hpcd->State = HAL_PCD_STATE_RESET;
00240
00241   return HAL_OK;
00242 }
00243
00244 /**
00245   * @brief  Initializes the PCD MSP.
00246   * @param  hpcd: PCD handle
00247   * @retval None
00248   */
00249 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00250 {
00251   /* Prevent unused argument(s) compilation warning */
00252   UNUSED(hpcd);
00253   /* NOTE : This function Should not be modified, when the callback is needed,
00254             the HAL_PCD_MspInit could be implemented in the user file
00255    */
00256 }
00257
00258 /**
00259   * @brief  DeInitializes PCD MSP.
00260   * @param  hpcd: PCD handle
00261   * @retval None
00262   */
00263 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00264 {
00265   /* Prevent unused argument(s) compilation warning */
00266   UNUSED(hpcd);
00267   /* NOTE : This function Should not be modified, when the callback is needed,
00268             the HAL_PCD_MspDeInit could be implemented in the user file
00269    */
00270 }
00271
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
00277  *  @brief   Data transfers functions
00278  *
00279 @verbatim
00280  ===============================================================================
00281                       ##### IO operation functions #####
00282  ===============================================================================
00283     [..]
00284     This subsection provides a set of functions allowing to manage the PCD data
00285     transfers.
00286
00287 @endverbatim
00288   * @{
00289   */
00290
00291 /**
00292   * @brief  Start The USB OTG Device.
00293   * @param  hpcd: PCD handle
00294   * @retval HAL status
00295   */
00296 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00297 {
00298   __HAL_LOCK(hpcd);
00299   USB_DevConnect (hpcd->Instance);
00300   __HAL_PCD_ENABLE(hpcd);
00301   __HAL_UNLOCK(hpcd);
00302   return HAL_OK;
00303 }
00304
00305 /**
00306   * @brief  Stop The USB OTG Device.
00307   * @param  hpcd: PCD handle
00308   * @retval HAL status
00309   */
00310 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00311 {
00312   __HAL_LOCK(hpcd);
00313   __HAL_PCD_DISABLE(hpcd);
00314   USB_StopDevice(hpcd->Instance);
00315   USB_DevDisconnect(hpcd->Instance);
00316   __HAL_UNLOCK(hpcd);
00317   return HAL_OK;
00318 }
00319
00320 /**
00321   * @brief  Handles PCD interrupt request.
00322   * @param  hpcd: PCD handle
00323   * @retval HAL status
00324   */
00325 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00326 {
00327   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00328   uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
00329   uint32_t fifoemptymsk = 0U, temp = 0U;
00330   USB_OTG_EPTypeDef *ep;
00331
00332   /* ensure that we are in device mode */
00333   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
00334   {
00335     /* avoid spurious interrupt */
00336     if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
00337     {
00338       return;
00339     }
00340
00341     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
00342     {
00343      /* incorrect mode, acknowledge the interrupt */
00344       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
00345     }
00346
00347     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
00348     {
00349       epnum = 0U;
00350
00351       /* Read in the device interrupt bits */
00352       ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
00353
00354       while ( ep_intr )
00355       {
00356         if (ep_intr & 0x1U)
00357         {
00358           epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
00359
00360           if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
00361           {
00362             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
00363
00364             if(hpcd->Init.dma_enable == 1U)
00365             {
00366               hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
00367               hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
00368             }
00369
00370             HAL_PCD_DataOutStageCallback(hpcd, epnum);
00371             if(hpcd->Init.dma_enable == 1U)
00372             {
00373               if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
00374               {
00375                  /* this is ZLP, so prepare EP0 for next setup */
00376                 USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
00377               }
00378             }
00379           }
00380
00381           if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
00382           {
00383             /* Inform the upper layer that a setup packet is available */
00384             HAL_PCD_SetupStageCallback(hpcd);
00385             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
00386           }
00387
00388           if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
00389           {
00390             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
00391           }
00392
00393 #ifdef USB_OTG_DOEPINT_OTEPSPR
00394           /* Clear Status Phase Received interrupt */
00395           if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
00396           {
00397             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
00398           }
00399 #endif /* USB_OTG_DOEPINT_OTEPSPR */
00400         }
00401         epnum++;
00402         ep_intr >>= 1U;
00403       }
00404     }
00405
00406     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
00407     {
00408       /* Read in the device interrupt bits */
00409       ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
00410
00411       epnum = 0U;
00412
00413       while ( ep_intr )
00414       {
00415         if (ep_intr & 0x1U) /* In ITR */
00416         {
00417           epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
00418
00419            if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
00420           {
00421             fifoemptymsk = 0x1U << epnum;
00422             USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
00423
00424             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
00425
00426             if (hpcd->Init.dma_enable == 1U)
00427             {
00428               hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
00429             }
00430
00431             HAL_PCD_DataInStageCallback(hpcd, epnum);
00432
00433             if (hpcd->Init.dma_enable == 1U)
00434             {
00435               /* this is ZLP, so prepare EP0 for next setup */
00436               if((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
00437               {
00438                 /* prepare to rx more setup packets */
00439                 USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
00440               }
00441             }
00442           }
00443            if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
00444           {
00445             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
00446           }
00447           if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
00448           {
00449             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
00450           }
00451           if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
00452           {
00453             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
00454           }
00455           if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
00456           {
00457             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
00458           }
00459           if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
00460           {
00461             PCD_WriteEmptyTxFifo(hpcd , epnum);
00462           }
00463         }
00464         epnum++;
00465         ep_intr >>= 1U;
00466       }
00467     }
00468
00469     /* Handle Resume Interrupt */
00470     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
00471     {
00472       /* Clear the Remote Wake-up Signaling */
00473       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00474
00475 #ifdef USB_OTG_GLPMCFG_LPMEN
00476       if(hpcd->LPM_State == LPM_L1)
00477       {
00478         hpcd->LPM_State = LPM_L0;
00479         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
00480       }
00481       else
00482 #endif /* USB_OTG_GLPMCFG_LPMEN */
00483       {
00484         HAL_PCD_ResumeCallback(hpcd);
00485       }
00486
00487       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
00488     }
00489
00490     /* Handle Suspend Interrupt */
00491     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
00492     {
00493       if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
00494       {
00495
00496         HAL_PCD_SuspendCallback(hpcd);
00497       }
00498       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
00499     }
00500
00501 #ifdef USB_OTG_GLPMCFG_LPMEN
00502     /* Handle LPM Interrupt */
00503     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
00504     {
00505       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
00506       if( hpcd->LPM_State == LPM_L0)
00507       {
00508         hpcd->LPM_State = LPM_L1;
00509         hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
00510         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
00511       }
00512       else
00513       {
00514         HAL_PCD_SuspendCallback(hpcd);
00515       }
00516     }
00517 #endif /* USB_OTG_GLPMCFG_LPMEN */
00518
00519     /* Handle Reset Interrupt */
00520     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
00521     {
00522       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00523       USB_FlushTxFifo(hpcd->Instance , 0U);
00524
00525       for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00526       {
00527         USBx_INEP(i)->DIEPINT = 0xFFU;
00528         USBx_OUTEP(i)->DOEPINT = 0xFFU;
00529       }
00530       USBx_DEVICE->DAINT = 0xFFFFFFFFU;
00531       USBx_DEVICE->DAINTMSK |= 0x10001U;
00532
00533       if(hpcd->Init.use_dedicated_ep1)
00534       {
00535         USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00536         USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00537       }
00538       else
00539       {
00540 #ifdef USB_OTG_DOEPINT_OTEPSPR
00541         USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
00542 #else
00543         USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00544 #endif /* USB_OTG_DOEPINT_OTEPSPR */
00545         USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00546       }
00547
00548       /* Set Default Address to 0 */
00549       USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
00550
00551       /* setup EP0 to receive SETUP packets */
00552       USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
00553
00554       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
00555     }
00556
00557     /* Handle Enumeration done Interrupt */
00558     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
00559     {
00560       USB_ActivateSetup(hpcd->Instance);
00561       hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
00562
00563       if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
00564       {
00565         hpcd->Init.speed            = USB_OTG_SPEED_HIGH;
00566         hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;
00567         hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
00568       }
00569       else
00570       {
00571         hpcd->Init.speed            = USB_OTG_SPEED_FULL;
00572         hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;
00573         hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
00574       }
00575
00576       HAL_PCD_ResetCallback(hpcd);
00577
00578       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
00579     }
00580
00581     /* Handle RxQLevel Interrupt */
00582     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
00583     {
00584       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00585
00586       temp = USBx->GRXSTSP;
00587
00588       ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
00589
00590       if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) ==  STS_DATA_UPDT)
00591       {
00592         if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
00593         {
00594           USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
00595           ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
00596           ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
00597         }
00598       }
00599       else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) ==  STS_SETUP_UPDT)
00600       {
00601         USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
00602         ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
00603       }
00604       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00605     }
00606
00607     /* Handle SOF Interrupt */
00608     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
00609     {
00610       HAL_PCD_SOFCallback(hpcd);
00611       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
00612     }
00613
00614     /* Handle Incomplete ISO IN Interrupt */
00615     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
00616     {
00617       HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
00618       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
00619     }
00620
00621     /* Handle Incomplete ISO OUT Interrupt */
00622     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00623     {
00624       HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
00625       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00626     }
00627
00628     /* Handle Connection event Interrupt */
00629     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
00630     {
00631       HAL_PCD_ConnectCallback(hpcd);
00632       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
00633     }
00634
00635     /* Handle Disconnection event Interrupt */
00636     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
00637     {
00638       temp = hpcd->Instance->GOTGINT;
00639
00640       if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
00641       {
00642         HAL_PCD_DisconnectCallback(hpcd);
00643       }
00644       hpcd->Instance->GOTGINT |= temp;
00645     }
00646   }
00647 }
00648
00649 /**
00650   * @brief  Data OUT stage callback.
00651   * @param  hpcd: PCD handle
00652   * @param  epnum: endpoint number
00653   * @retval None
00654   */
00655  __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00656 {
00657   /* Prevent unused argument(s) compilation warning */
00658   UNUSED(hpcd);
00659   UNUSED(epnum);
00660   /* NOTE : This function Should not be modified, when the callback is needed,
00661             the HAL_PCD_DataOutStageCallback could be implemented in the user file
00662    */
00663 }
00664
00665 /**
00666   * @brief  Data IN stage callback.
00667   * @param  hpcd: PCD handle
00668   * @param  epnum: endpoint number
00669   * @retval None
00670   */
00671  __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00672 {
00673   /* Prevent unused argument(s) compilation warning */
00674   UNUSED(hpcd);
00675   UNUSED(epnum);
00676   /* NOTE : This function Should not be modified, when the callback is needed,
00677             the HAL_PCD_DataInStageCallback could be implemented in the user file
00678    */
00679 }
00680 /**
00681   * @brief  Setup stage callback.
00682   * @param  hpcd: PCD handle
00683   * @retval None
00684   */
00685  __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
00686 {
00687   /* Prevent unused argument(s) compilation warning */
00688   UNUSED(hpcd);
00689   /* NOTE : This function Should not be modified, when the callback is needed,
00690             the HAL_PCD_SetupStageCallback could be implemented in the user file
00691    */
00692 }
00693
00694 /**
00695   * @brief  USB Start Of Frame callback.
00696   * @param  hpcd: PCD handle
00697   * @retval None
00698   */
00699  __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
00700 {
00701   /* Prevent unused argument(s) compilation warning */
00702   UNUSED(hpcd);
00703   /* NOTE : This function Should not be modified, when the callback is needed,
00704             the HAL_PCD_SOFCallback could be implemented in the user file
00705    */
00706 }
00707
00708 /**
00709   * @brief  USB Reset callback.
00710   * @param  hpcd: PCD handle
00711   * @retval None
00712   */
00713  __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
00714 {
00715   /* Prevent unused argument(s) compilation warning */
00716   UNUSED(hpcd);
00717   /* NOTE : This function Should not be modified, when the callback is needed,
00718             the HAL_PCD_ResetCallback could be implemented in the user file
00719    */
00720 }
00721
00722 /**
00723   * @brief  Suspend event callback.
00724   * @param  hpcd: PCD handle
00725   * @retval None
00726   */
00727  __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
00728 {
00729   /* Prevent unused argument(s) compilation warning */
00730   UNUSED(hpcd);
00731   /* NOTE : This function Should not be modified, when the callback is needed,
00732             the HAL_PCD_SuspendCallback could be implemented in the user file
00733    */
00734 }
00735
00736 /**
00737   * @brief  Resume event callback.
00738   * @param  hpcd: PCD handle
00739   * @retval None
00740   */
00741  __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
00742 {
00743   /* Prevent unused argument(s) compilation warning */
00744   UNUSED(hpcd);
00745   /* NOTE : This function Should not be modified, when the callback is needed,
00746             the HAL_PCD_ResumeCallback could be implemented in the user file
00747    */
00748 }
00749
00750 /**
00751   * @brief  Incomplete ISO OUT callback.
00752   * @param  hpcd: PCD handle
00753   * @param  epnum: endpoint number
00754   * @retval None
00755   */
00756  __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00757 {
00758   /* Prevent unused argument(s) compilation warning */
00759   UNUSED(hpcd);
00760   UNUSED(epnum);
00761   /* NOTE : This function Should not be modified, when the callback is needed,
00762             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
00763    */
00764 }
00765
00766 /**
00767   * @brief  Incomplete ISO IN callback.
00768   * @param  hpcd: PCD handle
00769   * @param  epnum: endpoint number
00770   * @retval None
00771   */
00772  __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00773 {
00774   /* Prevent unused argument(s) compilation warning */
00775   UNUSED(hpcd);
00776   UNUSED(epnum);
00777   /* NOTE : This function Should not be modified, when the callback is needed,
00778             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
00779    */
00780 }
00781
00782 /**
00783   * @brief  Connection event callback.
00784   * @param  hpcd: PCD handle
00785   * @retval None
00786   */
00787  __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
00788 {
00789   /* Prevent unused argument(s) compilation warning */
00790   UNUSED(hpcd);
00791   /* NOTE : This function Should not be modified, when the callback is needed,
00792             the HAL_PCD_ConnectCallback could be implemented in the user file
00793    */
00794 }
00795
00796 /**
00797   * @brief  Disconnection event callback.
00798   * @param  hpcd: PCD handle
00799   * @retval None
00800   */
00801  __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
00802 {
00803   /* Prevent unused argument(s) compilation warning */
00804   UNUSED(hpcd);
00805   /* NOTE : This function Should not be modified, when the callback is needed,
00806             the HAL_PCD_DisconnectCallback could be implemented in the user file
00807    */
00808 }
00809
00810 /**
00811   * @}
00812   */
00813
00814 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
00815  *  @brief   management functions
00816  *
00817 @verbatim
00818  ===============================================================================
00819                       ##### Peripheral Control functions #####
00820  ===============================================================================
00821     [..]
00822     This subsection provides a set of functions allowing to control the PCD data
00823     transfers.
00824
00825 @endverbatim
00826   * @{
00827   */
00828
00829 /**
00830   * @brief  Connect the USB device.
00831   * @param  hpcd: PCD handle
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
00835 {
00836   __HAL_LOCK(hpcd);
00837   USB_DevConnect(hpcd->Instance);
00838   __HAL_UNLOCK(hpcd);
00839   return HAL_OK;
00840 }
00841
00842 /**
00843   * @brief  Disconnect the USB device.
00844   * @param  hpcd: PCD handle
00845   * @retval HAL status
00846   */
00847 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
00848 {
00849   __HAL_LOCK(hpcd);
00850   USB_DevDisconnect(hpcd->Instance);
00851   __HAL_UNLOCK(hpcd);
00852   return HAL_OK;
00853 }
00854
00855 /**
00856   * @brief  Set the USB Device address.
00857   * @param  hpcd: PCD handle
00858   * @param  address: new device address
00859   * @retval HAL status
00860   */
00861 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
00862 {
00863   __HAL_LOCK(hpcd);
00864   USB_SetDevAddress(hpcd->Instance, address);
00865   __HAL_UNLOCK(hpcd);
00866   return HAL_OK;
00867 }
00868 /**
00869   * @brief  Open and configure an endpoint.
00870   * @param  hpcd: PCD handle
00871   * @param  ep_addr: endpoint address
00872   * @param  ep_mps: endpoint max packet size
00873   * @param  ep_type: endpoint type
00874   * @retval HAL status
00875   */
00876 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
00877 {
00878   HAL_StatusTypeDef  ret = HAL_OK;
00879   USB_OTG_EPTypeDef *ep;
00880
00881   if ((ep_addr & 0x80U) == 0x80U)
00882   {
00883     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00884   }
00885   else
00886   {
00887     ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
00888   }
00889   ep->num   = ep_addr & 0x7FU;
00890
00891   ep->is_in = (0x80U & ep_addr) != 0U;
00892   ep->maxpacket = ep_mps;
00893   ep->type = ep_type;
00894   if (ep->is_in)
00895   {
00896     /* Assign a Tx FIFO */
00897     ep->tx_fifo_num = ep->num;
00898   }
00899   /* Set initial data PID. */
00900   if (ep_type == EP_TYPE_BULK )
00901   {
00902     ep->data_pid_start = 0U;
00903   }
00904
00905   __HAL_LOCK(hpcd);
00906   USB_ActivateEndpoint(hpcd->Instance , ep);
00907   __HAL_UNLOCK(hpcd);
00908   return ret;
00909 }
00910
00911
00912 /**
00913   * @brief  Deactivate an endpoint.
00914   * @param  hpcd: PCD handle
00915   * @param  ep_addr: endpoint address
00916   * @retval HAL status
00917   */
00918 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00919 {
00920   USB_OTG_EPTypeDef *ep;
00921
00922   if ((ep_addr & 0x80U) == 0x80U)
00923   {
00924     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00925   }
00926   else
00927   {
00928     ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
00929   }
00930   ep->num   = ep_addr & 0x7FU;
00931
00932   ep->is_in = (0x80U & ep_addr) != 0U;
00933
00934   __HAL_LOCK(hpcd);
00935   USB_DeactivateEndpoint(hpcd->Instance , ep);
00936   __HAL_UNLOCK(hpcd);
00937   return HAL_OK;
00938 }
00939
00940
00941 /**
00942   * @brief  Receive an amount of data.
00943   * @param  hpcd: PCD handle
00944   * @param  ep_addr: endpoint address
00945   * @param  pBuf: pointer to the reception buffer
00946   * @param  len: amount of data to be received
00947   * @retval HAL status
00948   */
00949 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
00950 {
00951   USB_OTG_EPTypeDef *ep;
00952
00953   ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
00954
00955   /*setup and start the Xfer */
00956   ep->xfer_buff = pBuf;
00957   ep->xfer_len = len;
00958   ep->xfer_count = 0U;
00959   ep->is_in = 0U;
00960   ep->num = ep_addr & 0x7FU;
00961
00962   if (hpcd->Init.dma_enable == 1U)
00963   {
00964     ep->dma_addr = (uint32_t)pBuf;
00965   }
00966
00967   __HAL_LOCK(hpcd);
00968
00969   if ((ep_addr & 0x7FU) == 0U)
00970   {
00971     USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00972   }
00973   else
00974   {
00975     USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
00976   }
00977   __HAL_UNLOCK(hpcd);
00978
00979   return HAL_OK;
00980 }
00981
00982 /**
00983   * @brief  Get Received Data Size.
00984   * @param  hpcd: PCD handle
00985   * @param  ep_addr: endpoint address
00986   * @retval Data Size
00987   */
00988 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00989 {
00990   return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
00991 }
00992 /**
00993   * @brief  Send an amount of data.
00994   * @param  hpcd: PCD handle
00995   * @param  ep_addr: endpoint address
00996   * @param  pBuf: pointer to the transmission buffer
00997   * @param  len: amount of data to be sent
00998   * @retval HAL status
00999   */
01000 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01001 {
01002   USB_OTG_EPTypeDef *ep;
01003
01004   ep = &hpcd->IN_ep[ep_addr & 0x7FU];
01005
01006   /*setup and start the Xfer */
01007   ep->xfer_buff = pBuf;
01008   ep->xfer_len = len;
01009   ep->xfer_count = 0U;
01010   ep->is_in = 1U;
01011   ep->num = ep_addr & 0x7FU;
01012
01013   if (hpcd->Init.dma_enable == 1U)
01014   {
01015     ep->dma_addr = (uint32_t)pBuf;
01016   }
01017
01018   __HAL_LOCK(hpcd);
01019
01020   if ((ep_addr & 0x7FU) == 0U)
01021   {
01022     USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
01023   }
01024   else
01025   {
01026     USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
01027   }
01028
01029   __HAL_UNLOCK(hpcd);
01030
01031   return HAL_OK;
01032 }
01033
01034 /**
01035   * @brief  Set a STALL condition over an endpoint.
01036   * @param  hpcd: PCD handle
01037   * @param  ep_addr: endpoint address
01038   * @retval HAL status
01039   */
01040 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01041 {
01042   USB_OTG_EPTypeDef *ep;
01043
01044   if ((0x80U & ep_addr) == 0x80U)
01045   {
01046     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
01047   }
01048   else
01049   {
01050     ep = &hpcd->OUT_ep[ep_addr];
01051   }
01052
01053   ep->is_stall = 1U;
01054   ep->num   = ep_addr & 0x7FU;
01055   ep->is_in = ((ep_addr & 0x80U) == 0x80U);
01056
01057
01058   __HAL_LOCK(hpcd);
01059   USB_EPSetStall(hpcd->Instance , ep);
01060   if((ep_addr & 0x7FU) == 0U)
01061   {
01062     USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
01063   }
01064   __HAL_UNLOCK(hpcd);
01065
01066   return HAL_OK;
01067 }
01068
01069 /**
01070   * @brief  Clear a STALL condition over in an endpoint.
01071   * @param  hpcd: PCD handle
01072   * @param  ep_addr: endpoint address
01073   * @retval HAL status
01074   */
01075 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01076 {
01077   USB_OTG_EPTypeDef *ep;
01078
01079   if ((0x80U & ep_addr) == 0x80U)
01080   {
01081     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
01082   }
01083   else
01084   {
01085     ep = &hpcd->OUT_ep[ep_addr];
01086   }
01087
01088   ep->is_stall = 0U;
01089   ep->num   = ep_addr & 0x7FU;
01090   ep->is_in = ((ep_addr & 0x80U) == 0x80U);
01091
01092   __HAL_LOCK(hpcd);
01093   USB_EPClearStall(hpcd->Instance , ep);
01094   __HAL_UNLOCK(hpcd);
01095
01096   return HAL_OK;
01097 }
01098
01099 /**
01100   * @brief  Flush an endpoint.
01101   * @param  hpcd: PCD handle
01102   * @param  ep_addr: endpoint address
01103   * @retval HAL status
01104   */
01105 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01106 {
01107   __HAL_LOCK(hpcd);
01108
01109   if ((ep_addr & 0x80U) == 0x80U)
01110   {
01111     USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
01112   }
01113   else
01114   {
01115     USB_FlushRxFifo(hpcd->Instance);
01116   }
01117
01118   __HAL_UNLOCK(hpcd);
01119
01120   return HAL_OK;
01121 }
01122
01123 /**
01124   * @brief  Activate remote wakeup signalling.
01125   * @param  hpcd: PCD handle
01126   * @retval HAL status
01127   */
01128 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01129 {
01130   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01131
01132   if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
01133   {
01134     /* Activate Remote wakeup signaling */
01135     USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
01136   }
01137   return HAL_OK;
01138 }
01139
01140 /**
01141   * @brief  De-activate remote wakeup signalling.
01142   * @param  hpcd: PCD handle
01143   * @retval HAL status
01144   */
01145 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01146 {
01147   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01148
01149   /* De-activate Remote wakeup signaling */
01150   USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
01151   return HAL_OK;
01152 }
01153 /**
01154   * @}
01155   */
01156
01157 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01158  *  @brief   Peripheral State functions
01159  *
01160 @verbatim
01161  ===============================================================================
01162                       ##### Peripheral State functions #####
01163  ===============================================================================
01164     [..]
01165     This subsection permits to get in run-time the status of the peripheral
01166     and the data flow.
01167
01168 @endverbatim
01169   * @{
01170   */
01171
01172 /**
01173   * @brief  Return the PCD handle state.
01174   * @param  hpcd: PCD handle
01175   * @retval HAL state
01176   */
01177 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01178 {
01179   return hpcd->State;
01180 }
01181 /**
01182   * @}
01183   */
01184
01185 /**
01186   * @}
01187   */
01188
01189 /* Private functions ---------------------------------------------------------*/
01190 /** @addtogroup PCD_Private_Functions
01191   * @{
01192   */
01193
01194 /**
01195   * @brief  Check FIFO for the next packet to be loaded.
01196   * @param  hpcd: PCD handle
01197   * @param  epnum : endpoint number
01198   * @retval HAL status
01199   */
01200 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
01201 {
01202   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01203   USB_OTG_EPTypeDef *ep;
01204   int32_t len = 0U;
01205   uint32_t len32b;
01206   uint32_t fifoemptymsk = 0U;
01207
01208   ep = &hpcd->IN_ep[epnum];
01209   len = ep->xfer_len - ep->xfer_count;
01210
01211   if (len > ep->maxpacket)
01212   {
01213     len = ep->maxpacket;
01214   }
01215
01216
01217   len32b = (len + 3U) / 4U;
01218
01219   while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
01220           ep->xfer_count < ep->xfer_len &&
01221             ep->xfer_len != 0U)
01222   {
01223     /* Write the FIFO */
01224     len = ep->xfer_len - ep->xfer_count;
01225
01226     if (len > ep->maxpacket)
01227     {
01228       len = ep->maxpacket;
01229     }
01230     len32b = (len + 3U) / 4U;
01231
01232     USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
01233
01234     ep->xfer_buff  += len;
01235     ep->xfer_count += len;
01236   }
01237
01238   if(len <= 0U)
01239   {
01240     fifoemptymsk = 0x1U << epnum;
01241     USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
01242
01243   }
01244
01245   return HAL_OK;
01246 }
01247
01248 /**
01249   * @}
01250   */
01251 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
01252           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
01253 #endif /* HAL_PCD_MODULE_ENABLED */
01254 /**
01255   * @}
01256   */
01257
01258 /**
01259   * @}
01260   */
01261
01262 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd.h Source File

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stm32f4xx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_PCD_H
00040 #define __STM32F4xx_HAL_PCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00046     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00047     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00048     defined(STM32F469xx) || defined(STM32F479xx)
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_ll_usb.h"
00051
00052 /** @addtogroup STM32F4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup PCD
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup PCD_Exported_Types PCD Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  PCD State structure definition
00067   */
00068 typedef enum
00069 {
00070   HAL_PCD_STATE_RESET   = 0x00U,
00071   HAL_PCD_STATE_READY   = 0x01U,
00072   HAL_PCD_STATE_ERROR   = 0x02U,
00073   HAL_PCD_STATE_BUSY    = 0x03U,
00074   HAL_PCD_STATE_TIMEOUT = 0x04U
00075 } PCD_StateTypeDef;
00076
00077 #ifdef USB_OTG_GLPMCFG_LPMEN
00078 /* Device LPM suspend state */
00079 typedef enum
00080 {
00081   LPM_L0 = 0x00U, /* on */
00082   LPM_L1 = 0x01U, /* LPM L1 sleep */
00083   LPM_L2 = 0x02U, /* suspend */
00084   LPM_L3 = 0x03U /* off */
00085 }PCD_LPM_StateTypeDef;
00086 #endif /* USB_OTG_GLPMCFG_LPMEN */
00087
00088 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
00089 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
00090 typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;
00091
00092 /**
00093   * @brief  PCD Handle Structure definition
00094   */
00095 typedef struct
00096 {
00097   PCD_TypeDef             *Instance;    /*!< Register base address              */
00098   PCD_InitTypeDef         Init;         /*!< PCD required parameters            */
00099   PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
00100   PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */
00101   HAL_LockTypeDef         Lock;         /*!< PCD peripheral status              */
00102   __IO PCD_StateTypeDef   State;        /*!< PCD communication state            */
00103   uint32_t                Setup[12];    /*!< Setup packet buffer                */
00104 #ifdef USB_OTG_GLPMCFG_LPMEN
00105   PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
00106   uint32_t                BESL;
00107   uint32_t                lpm_active;   /*!< Enable or disable the Link Power Management .
00108                                         This parameter can be set to ENABLE or DISABLE */
00109 #endif /* USB_OTG_GLPMCFG_LPMEN */
00110 #ifdef USB_OTG_GCCFG_BCDEN
00111   uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.
00112                                         This parameter can be set to ENABLE or DISABLE */
00113 #endif /* USB_OTG_GCCFG_BCDEN */
00114   void                    *pData;       /*!< Pointer to upper stack Handler */
00115 } PCD_HandleTypeDef;
00116
00117 /**
00118   * @}
00119   */
00120
00121 /* Include PCD HAL Extension module */
00122 #include "stm32f4xx_hal_pcd_ex.h"
00123
00124 /* Exported constants --------------------------------------------------------*/
00125 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00126   * @{
00127   */
00128
00129 /** @defgroup PCD_Speed PCD Speed
00130   * @{
00131   */
00132 #define PCD_SPEED_HIGH               0U
00133 #define PCD_SPEED_HIGH_IN_FULL       1U
00134 #define PCD_SPEED_FULL               2U
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup PCD_PHY_Module PCD PHY Module
00140   * @{
00141   */
00142 #define PCD_PHY_ULPI                 1U
00143 #define PCD_PHY_EMBEDDED             2U
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
00149   * @{
00150   */
00151 #ifndef USBD_HS_TRDT_VALUE
00152  #define USBD_HS_TRDT_VALUE           9U
00153 #endif /* USBD_HS_TRDT_VALUE */
00154 #ifndef USBD_FS_TRDT_VALUE
00155  #define USBD_FS_TRDT_VALUE           5U
00156 #endif /* USBD_FS_TRDT_VALUE */
00157 /**
00158   * @}
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /* Exported macros -----------------------------------------------------------*/
00166 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00167  *  @brief macros to handle interrupts and specific clock configurations
00168  * @{
00169  */
00170 #define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
00171 #define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
00172
00173 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00174 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
00175 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
00176
00177 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
00178                                                            ~(USB_OTG_PCGCCTL_STOPCLK)
00179
00180 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
00181
00182 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
00183
00184 #define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U)
00185 #define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU)
00186 #define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U)
00187
00188 #define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U)
00189 #define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU)
00190 #define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U)
00191
00192 #define USB_OTG_HS_WAKEUP_EXTI_LINE              ((uint32_t)0x00100000U)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
00193 #define USB_OTG_FS_WAKEUP_EXTI_LINE              ((uint32_t)0x00040000U)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
00194
00195 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
00196 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
00197 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
00198 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
00199
00200 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00201                                                              EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
00202                                                             }while(0)
00203
00204 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
00205                                                               EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00206                                                              }while(0)
00207
00208 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00209                                                                      EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
00210                                                                      EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
00211                                                                      EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
00212                                                                     }while(0)
00213
00214 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
00215
00216 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
00217 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00218 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
00219 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
00220
00221 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00222                                                              EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00223                                                             }while(0)
00224
00225 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
00226                                                                EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00227                                                               }while(0)
00228
00229 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00230                                                                       EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00231                                                                       EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00232                                                                       EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00233                                                                      }while(0)
00234
00235 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
00236 /**
00237   * @}
00238   */
00239
00240 /* Exported functions --------------------------------------------------------*/
00241 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00242   * @{
00243   */
00244
00245 /* Initialization/de-initialization functions  ********************************/
00246 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00247   * @{
00248   */
00249 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00250 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
00251 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00252 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00253 /**
00254   * @}
00255   */
00256
00257 /* I/O operation functions  ***************************************************/
00258 /* Non-Blocking mode: Interrupt */
00259 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
00260   * @{
00261   */
00262 /* Non-Blocking mode: Interrupt */
00263 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00264 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00265 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00266
00267 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00268 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00269 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00270 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00271 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00272 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00273 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00274 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00275 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00276 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00277 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00278 /**
00279   * @}
00280   */
00281
00282 /* Peripheral Control functions  **********************************************/
00283 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00284   * @{
00285   */
00286 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00287 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00288 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00289 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00290 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00291 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00292 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00293 uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00294 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00295 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00296 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00297 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00298 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00299 /**
00300   * @}
00301   */
00302
00303 /* Peripheral State functions  ************************************************/
00304 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00305   * @{
00306   */
00307 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /* Private macros ------------------------------------------------------------*/
00317 /** @defgroup PCD_Private_Macros PCD Private Macros
00318  * @{
00319  */
00320
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00333           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00334 #ifdef __cplusplus
00335 }
00336 #endif
00337
00338
00339 #endif /* __STM32F4xx_HAL_PCD_H */
00340
00341 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd_ex.c Source File

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stm32f4xx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Extended features functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f4xx_hal.h"
00044
00045 /** @addtogroup STM32F4xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup PCDEx PCDEx
00050   * @brief PCD Extended HAL module driver
00051   * @{
00052   */
00053 #ifdef HAL_PCD_MODULE_ENABLED
00054 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00055     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00056     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00057     defined(STM32F469xx) || defined(STM32F479xx)
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062 /* Private functions ---------------------------------------------------------*/
00063 /* Exported functions --------------------------------------------------------*/
00064
00065 /** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
00066   * @{
00067   */
00068
00069 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00070   * @brief    PCDEx control functions
00071   *
00072 @verbatim
00073  ===============================================================================
00074                  ##### Extended features functions #####
00075  ===============================================================================
00076     [..]  This section provides functions allowing to:
00077       (+) Update FIFO configuration
00078
00079 @endverbatim
00080   * @{
00081   */
00082
00083 /**
00084   * @brief  Set Tx FIFO
00085   * @param  hpcd: PCD handle
00086   * @param  fifo: The number of Tx fifo
00087   * @param  size: Fifo size
00088   * @retval HAL status
00089   */
00090 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
00091 {
00092   uint8_t i = 0U;
00093   uint32_t Tx_Offset = 0U;
00094
00095   /*  TXn min size = 16 words. (n  : Transmit FIFO index)
00096       When a TxFIFO is not used, the Configuration should be as follows:
00097           case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00098          --> Txm can use the space allocated for Txn.
00099          case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00100          --> Txn should be configured with the minimum space of 16 words
00101      The FIFO is used optimally when used TxFIFOs are allocated in the top
00102          of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
00103      When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
00104
00105   Tx_Offset = hpcd->Instance->GRXFSIZ;
00106
00107   if(fifo == 0U)
00108   {
00109     hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
00110   }
00111   else
00112   {
00113     Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
00114     for (i = 0U; i < (fifo - 1U); i++)
00115     {
00116       Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
00117     }
00118
00119     /* Multiply Tx_Size by 2 to get higher performance */
00120     hpcd->Instance->DIEPTXF[fifo - 1U] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
00121   }
00122
00123   return HAL_OK;
00124 }
00125
00126 /**
00127   * @brief  Set Rx FIFO
00128   * @param  hpcd: PCD handle
00129   * @param  size: Size of Rx fifo
00130   * @retval HAL status
00131   */
00132 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
00133 {
00134   hpcd->Instance->GRXFSIZ = size;
00135
00136   return HAL_OK;
00137 }
00138
00139 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00140 /**
00141   * @brief  Activate LPM feature
00142   * @param  hpcd: PCD handle
00143   * @retval HAL status
00144   */
00145 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00146 {
00147   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00148
00149   hpcd->lpm_active = ENABLE;
00150   hpcd->LPM_State = LPM_L0;
00151   USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
00152   USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00153
00154   return HAL_OK;
00155 }
00156
00157 /**
00158   * @brief  Deactivate LPM feature.
00159   * @param  hpcd: PCD handle
00160   * @retval HAL status
00161   */
00162 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00163 {
00164   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00165
00166   hpcd->lpm_active = DISABLE;
00167   USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
00168   USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00169
00170   return HAL_OK;
00171 }
00172
00173 /**
00174   * @brief  Send LPM message to user layer callback.
00175   * @param  hpcd: PCD handle
00176   * @param  msg: LPM message
00177   * @retval HAL status
00178   */
00179 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00180 {
00181   /* Prevent unused argument(s) compilation warning */
00182   UNUSED(hpcd);
00183   UNUSED(msg);
00184 }
00185 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00186
00187 /**
00188   * @}
00189   */
00190
00191 /**
00192   * @}
00193   */
00194
00195 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00196           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00197 #endif /* HAL_PCD_MODULE_ENABLED */
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205
00206 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pcd_ex.h Source File

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stm32f4xx_hal_pcd_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_PCD_EX_H
00040 #define __STM32F4xx_HAL_PCD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00046     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00047     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00048     defined(STM32F469xx) || defined(STM32F479xx)
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_hal_def.h"
00051
00052 /** @addtogroup STM32F4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup PCDEx
00057   * @{
00058   */
00059 /* Exported types ------------------------------------------------------------*/
00060 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00061 typedef enum
00062 {
00063   PCD_LPM_L0_ACTIVE = 0x00U, /* on */
00064   PCD_LPM_L1_ACTIVE = 0x01U /* LPM L1 sleep */
00065 }PCD_LPM_MsgTypeDef;
00066 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00067
00068 /* Exported constants --------------------------------------------------------*/
00069 /* Exported macros -----------------------------------------------------------*/
00070 /* Exported functions --------------------------------------------------------*/
00071 /** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
00072   * @{
00073   */
00074 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00075   * @{
00076   */
00077 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
00078 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
00079 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00080 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00081 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00082 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00083 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00084
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 /**
00098   * @}
00099   */
00100 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00101           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00102 #ifdef __cplusplus
00103 }
00104 #endif
00105
00106
00107 #endif /* __STM32F4xx_HAL_PCD_EX_H */
00108
00109 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr.c Source File

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stm32f4xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Power Controller (PWR) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32f4xx_hal.h"
00045
00046 /** @addtogroup STM32F4xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup PWR PWR
00051   * @brief PWR HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_PWR_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @addtogroup PWR_Private_Constants
00060   * @{
00061   */
00062
00063 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00064   * @{
00065   */
00066 #define PVD_MODE_IT               ((uint32_t)0x00010000U)
00067 #define PVD_MODE_EVT              ((uint32_t)0x00020000U)
00068 #define PVD_RISING_EDGE           ((uint32_t)0x00000001U)
00069 #define PVD_FALLING_EDGE          ((uint32_t)0x00000002U)
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077 /* Private macro -------------------------------------------------------------*/
00078 /* Private variables ---------------------------------------------------------*/
00079 /* Private function prototypes -----------------------------------------------*/
00080 /* Private functions ---------------------------------------------------------*/
00081
00082 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00083   * @{
00084   */
00085
00086 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00087   *  @brief    Initialization and de-initialization functions
00088   *
00089 @verbatim
00090  ===============================================================================
00091               ##### Initialization and de-initialization functions #####
00092  ===============================================================================
00093     [..]
00094       After reset, the backup domain (RTC registers, RTC backup data
00095       registers and backup SRAM) is protected against possible unwanted
00096       write accesses.
00097       To enable access to the RTC Domain and RTC registers, proceed as follows:
00098         (+) Enable the Power Controller (PWR) APB1 interface clock using the
00099             __HAL_RCC_PWR_CLK_ENABLE() macro.
00100         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00101
00102 @endverbatim
00103   * @{
00104   */
00105
00106 /**
00107   * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
00108   * @retval None
00109   */
00110 void HAL_PWR_DeInit(void)
00111 {
00112   __HAL_RCC_PWR_FORCE_RESET();
00113   __HAL_RCC_PWR_RELEASE_RESET();
00114 }
00115
00116 /**
00117   * @brief Enables access to the backup domain (RTC registers, RTC
00118   *         backup data registers and backup SRAM).
00119   * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00120   *         Backup Domain Access should be kept enabled.
00121   * @retval None
00122   */
00123 void HAL_PWR_EnableBkUpAccess(void)
00124 {
00125   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
00126 }
00127
00128 /**
00129   * @brief Disables access to the backup domain (RTC registers, RTC
00130   *         backup data registers and backup SRAM).
00131   * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
00132   *         Backup Domain Access should be kept enabled.
00133   * @retval None
00134   */
00135 void HAL_PWR_DisableBkUpAccess(void)
00136 {
00137   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
00138 }
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00145   *  @brief Low Power modes configuration functions
00146   *
00147 @verbatim
00148
00149  ===============================================================================
00150                  ##### Peripheral Control functions #####
00151  ===============================================================================
00152
00153     *** PVD configuration ***
00154     =========================
00155     [..]
00156       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00157           threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
00158       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
00159           than the PVD threshold. This event is internally connected to the EXTI
00160           line16 and can generate an interrupt if enabled. This is done through
00161           __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
00162       (+) The PVD is stopped in Standby mode.
00163
00164     *** Wake-up pin configuration ***
00165     ================================
00166     [..]
00167       (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
00168           forced in input pull-down configuration and is active on rising edges.
00169       (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
00170          (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
00171          (++) For STM32F410xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
00172
00173     *** Low Power modes configuration ***
00174     =====================================
00175     [..]
00176       The devices feature 3 low-power modes:
00177       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
00178       (+) Stop mode: all clocks are stopped, regulator running, regulator
00179           in low power mode
00180       (+) Standby mode: 1.2V domain powered off.
00181
00182    *** Sleep mode ***
00183    ==================
00184     [..]
00185       (+) Entry:
00186         The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
00187               functions with
00188           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00189           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00190
00191       -@@- The Regulator parameter is not used for the STM32F4 family
00192               and is kept as parameter just to maintain compatibility with the
00193               lower power families (STM32L).
00194       (+) Exit:
00195         Any peripheral interrupt acknowledged by the nested vectored interrupt
00196               controller (NVIC) can wake up the device from Sleep mode.
00197
00198    *** Stop mode ***
00199    =================
00200     [..]
00201       In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
00202       and the HSE RC oscillators are disabled. Internal SRAM and register contents
00203       are preserved.
00204       The voltage regulator can be configured either in normal or low-power mode.
00205       To minimize the consumption In Stop mode, FLASH can be powered off before
00206       entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
00207       It can be switched on again by software after exiting the Stop mode using
00208       the HAL_PWREx_DisableFlashPowerDown() function.
00209
00210       (+) Entry:
00211          The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
00212              function with:
00213           (++) Main regulator ON.
00214           (++) Low Power regulator ON.
00215       (+) Exit:
00216         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
00217
00218    *** Standby mode ***
00219    ====================
00220     [..]
00221     (+)
00222       The Standby mode allows to achieve the lowest power consumption. It is based
00223       on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
00224       The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
00225       the HSE oscillator are also switched off. SRAM and register contents are lost
00226       except for the RTC registers, RTC backup registers, backup SRAM and Standby
00227       circuitry.
00228
00229       The voltage regulator is OFF.
00230
00231       (++) Entry:
00232         (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
00233       (++) Exit:
00234         (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
00235              tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
00236
00237    *** Auto-wake-up (AWU) from low-power mode ***
00238    =============================================
00239     [..]
00240
00241      (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00242       Wake-up event, a tamper event or a time-stamp event, without depending on
00243       an external interrupt (Auto-wake-up mode).
00244
00245       (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
00246
00247         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00248               configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00249
00250         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00251              is necessary to configure the RTC to detect the tamper or time stamp event using the
00252                 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00253
00254         (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
00255               configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00256
00257 @endverbatim
00258   * @{
00259   */
00260
00261 /**
00262   * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
00263   * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
00264   *        information for the PVD.
00265   * @note Refer to the electrical characteristics of your device datasheet for
00266   *         more details about the voltage threshold corresponding to each
00267   *         detection level.
00268   * @retval None
00269   */
00270 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00271 {
00272   /* Check the parameters */
00273   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00274   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00275
00276   /* Set PLS[7:5] bits according to PVDLevel value */
00277   MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
00278
00279   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00280   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00281   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00282   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00283   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00284
00285   /* Configure interrupt mode */
00286   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00287   {
00288     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00289   }
00290
00291   /* Configure event mode */
00292   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00293   {
00294     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00295   }
00296
00297   /* Configure the edge */
00298   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00299   {
00300     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00301   }
00302
00303   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00304   {
00305     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00306   }
00307 }
00308
00309 /**
00310   * @brief Enables the Power Voltage Detector(PVD).
00311   * @retval None
00312   */
00313 void HAL_PWR_EnablePVD(void)
00314 {
00315   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
00316 }
00317
00318 /**
00319   * @brief Disables the Power Voltage Detector(PVD).
00320   * @retval None
00321   */
00322 void HAL_PWR_DisablePVD(void)
00323 {
00324   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
00325 }
00326
00327 /**
00328   * @brief Enables the Wake-up PINx functionality.
00329   * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
00330   *         This parameter can be one of the following values:
00331   *           @arg PWR_WAKEUP_PIN1
00332   *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
00333   *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
00334   * @retval None
00335   */
00336 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
00337 {
00338   /* Check the parameter */
00339   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00340
00341   /* Enable the wake up pin */
00342   SET_BIT(PWR->CSR, WakeUpPinx);
00343 }
00344
00345 /**
00346   * @brief Disables the Wake-up PINx functionality.
00347   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00348   *         This parameter can be one of the following values:
00349   *           @arg PWR_WAKEUP_PIN1
00350   *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices
00351   *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices
00352   * @retval None
00353   */
00354 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00355 {
00356   /* Check the parameter */
00357   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00358
00359   /* Disable the wake up pin */
00360   CLEAR_BIT(PWR->CSR, WakeUpPinx);
00361 }
00362
00363 /**
00364   * @brief Enters Sleep mode.
00365   *
00366   * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
00367   *
00368   * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
00369   *       systick interrupt when used as time base for Timeout
00370   *
00371   * @param Regulator: Specifies the regulator state in SLEEP mode.
00372   *            This parameter can be one of the following values:
00373   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
00374   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
00375   * @note This parameter is not used for the STM32F4 family and is kept as parameter
00376   *       just to maintain compatibility with the lower power families.
00377   * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
00378   *          This parameter can be one of the following values:
00379   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00380   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00381   * @retval None
00382   */
00383 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00384 {
00385   /* Check the parameters */
00386   assert_param(IS_PWR_REGULATOR(Regulator));
00387   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00388
00389   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00390   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00391
00392   /* Select SLEEP mode entry -------------------------------------------------*/
00393   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00394   {
00395     /* Request Wait For Interrupt */
00396     __WFI();
00397   }
00398   else
00399   {
00400     /* Request Wait For Event */
00401     __SEV();
00402     __WFE();
00403     __WFE();
00404   }
00405 }
00406
00407 /**
00408   * @brief Enters Stop mode.
00409   * @note In Stop mode, all I/O pins keep the same state as in Run mode.
00410   * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
00411   *         the HSI RC oscillator is selected as system clock.
00412   * @note When the voltage regulator operates in low power mode, an additional
00413   *         startup delay is incurred when waking up from Stop mode.
00414   *         By keeping the internal regulator ON during Stop mode, the consumption
00415   *         is higher although the startup time is reduced.
00416   * @param Regulator: Specifies the regulator state in Stop mode.
00417   *          This parameter can be one of the following values:
00418   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
00419   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
00420   * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
00421   *          This parameter can be one of the following values:
00422   *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
00423   *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
00424   * @retval None
00425   */
00426 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00427 {
00428   /* Check the parameters */
00429   assert_param(IS_PWR_REGULATOR(Regulator));
00430   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00431
00432   /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
00433   MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
00434
00435   /* Set SLEEPDEEP bit of Cortex System Control Register */
00436   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00437
00438   /* Select Stop mode entry --------------------------------------------------*/
00439   if(STOPEntry == PWR_STOPENTRY_WFI)
00440   {
00441     /* Request Wait For Interrupt */
00442     __WFI();
00443   }
00444   else
00445   {
00446     /* Request Wait For Event */
00447     __SEV();
00448     __WFE();
00449     __WFE();
00450   }
00451   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00452   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00453 }
00454
00455 /**
00456   * @brief Enters Standby mode.
00457   * @note In Standby mode, all I/O pins are high impedance except for:
00458   *          - Reset pad (still available)
00459   *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
00460   *            Alarm out, or RTC clock calibration out.
00461   *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
00462   *          - WKUP pin 1 (PA0) if enabled.
00463   * @retval None
00464   */
00465 void HAL_PWR_EnterSTANDBYMode(void)
00466 {
00467   /* Select Standby mode */
00468   SET_BIT(PWR->CR, PWR_CR_PDDS);
00469
00470   /* Set SLEEPDEEP bit of Cortex System Control Register */
00471   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00472
00473   /* This option is used to ensure that store operations are completed */
00474 #if defined ( __CC_ARM)
00475   __force_stores();
00476 #endif
00477   /* Request Wait For Interrupt */
00478   __WFI();
00479 }
00480
00481 /**
00482   * @brief This function handles the PWR PVD interrupt request.
00483   * @note This API should be called under the PVD_IRQHandler().
00484   * @retval None
00485   */
00486 void HAL_PWR_PVD_IRQHandler(void)
00487 {
00488   /* Check PWR Exti flag */
00489   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
00490   {
00491     /* PWR PVD interrupt user callback */
00492     HAL_PWR_PVDCallback();
00493
00494     /* Clear PWR Exti pending bit */
00495     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
00496   }
00497 }
00498
00499 /**
00500   * @brief  PWR PVD interrupt callback
00501   * @retval None
00502   */
00503 __weak void HAL_PWR_PVDCallback(void)
00504 {
00505   /* NOTE : This function Should not be modified, when the callback is needed,
00506             the HAL_PWR_PVDCallback could be implemented in the user file
00507    */
00508 }
00509
00510 /**
00511   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
00512   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00513   *       re-enters SLEEP mode when an interruption handling is over.
00514   *       Setting this bit is useful when the processor is expected to run only on
00515   *       interruptions handling.
00516   * @retval None
00517   */
00518 void HAL_PWR_EnableSleepOnExit(void)
00519 {
00520   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00521   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00522 }
00523
00524 /**
00525   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00526   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00527   *       re-enters SLEEP mode when an interruption handling is over.
00528   * @retval None
00529   */
00530 void HAL_PWR_DisableSleepOnExit(void)
00531 {
00532   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00533   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00534 }
00535
00536 /**
00537   * @brief Enables CORTEX M4 SEVONPEND bit.
00538   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
00539   *       WFE to wake up when an interrupt moves from inactive to pended.
00540   * @retval None
00541   */
00542 void HAL_PWR_EnableSEVOnPend(void)
00543 {
00544   /* Set SEVONPEND bit of Cortex System Control Register */
00545   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00546 }
00547
00548 /**
00549   * @brief Disables CORTEX M4 SEVONPEND bit.
00550   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
00551   *       WFE to wake up when an interrupt moves from inactive to pended.
00552   * @retval None
00553   */
00554 void HAL_PWR_DisableSEVOnPend(void)
00555 {
00556   /* Clear SEVONPEND bit of Cortex System Control Register */
00557   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00558 }
00559
00560 /**
00561   * @}
00562   */
00563
00564 /**
00565   * @}
00566   */
00567
00568 #endif /* HAL_PWR_MODULE_ENABLED */
00569 /**
00570   * @}
00571   */
00572
00573 /**
00574   * @}
00575   */
00576
00577 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr.h Source File

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stm32f4xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of PWR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_PWR_H
00040 #define __STM32F4xx_HAL_PWR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWR
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup PWR_Exported_Types PWR Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  PWR PVD configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
00069                             This parameter can be a value of @ref PWR_PVD_detection_level */
00070
00071   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00072                            This parameter can be a value of @ref PWR_PVD_Mode */
00073 }PWR_PVDTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
00085   * @{
00086   */
00087 #define PWR_WAKEUP_PIN1                 ((uint32_t)0x00000100U)
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
00093   * @{
00094   */
00095 #define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
00096 #define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
00097 #define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
00098 #define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
00099 #define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
00100 #define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
00101 #define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
00102 #define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7/* External input analog voltage
00103                                                           (Compare internally to VREFINT) */
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup PWR_PVD_Mode PWR PVD Mode
00109   * @{
00110   */
00111 #define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< basic mode is used */
00112 #define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
00113 #define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
00114 #define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00115 #define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
00116 #define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
00117 #define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
00118 /**
00119   * @}
00120   */
00121
00122
00123 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
00124   * @{
00125   */
00126 #define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000U)
00127 #define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
00133   * @{
00134   */
00135 #define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01U)
00136 #define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02U)
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
00142   * @{
00143   */
00144 #define PWR_STOPENTRY_WFI               ((uint8_t)0x01U)
00145 #define PWR_STOPENTRY_WFE               ((uint8_t)0x02U)
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup PWR_Flag PWR Flag
00151   * @{
00152   */
00153 #define PWR_FLAG_WU                     PWR_CSR_WUF
00154 #define PWR_FLAG_SB                     PWR_CSR_SBF
00155 #define PWR_FLAG_PVDO                   PWR_CSR_PVDO
00156 #define PWR_FLAG_BRR                    PWR_CSR_BRR
00157 #define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
00158 /**
00159   * @}
00160   */
00161
00162 /**
00163   * @}
00164   */
00165
00166 /* Exported macro ------------------------------------------------------------*/
00167 /** @defgroup PWR_Exported_Macro PWR Exported Macro
00168   * @{
00169   */
00170
00171 /** @brief  Check PWR flag is set or not.
00172   * @param  __FLAG__: specifies the flag to check.
00173   *           This parameter can be one of the following values:
00174   *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
00175   *                  was received from the WKUP pin or from the RTC alarm (Alarm A
00176   *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
00177   *                  An additional wakeup event is detected if the WKUP pin is enabled
00178   *                  (by setting the EWUP bit) when the WKUP pin level is already high.
00179   *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
00180   *                  resumed from StandBy mode.
00181   *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
00182   *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
00183   *                  For this reason, this bit is equal to 0 after Standby or reset
00184   *                  until the PVDE bit is set.
00185   *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
00186   *                  when the device wakes up from Standby mode or by a system reset
00187   *                  or power reset.
00188   *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
00189   *                 scaling output selection is ready.
00190   * @retval The new state of __FLAG__ (TRUE or FALSE).
00191   */
00192 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
00193
00194 /** @brief  Clear the PWR's pending flags.
00195   * @param  __FLAG__: specifies the flag to clear.
00196   *          This parameter can be one of the following values:
00197   *            @arg PWR_FLAG_WU: Wake Up flag
00198   *            @arg PWR_FLAG_SB: StandBy flag
00199   */
00200 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
00201
00202 /**
00203   * @brief Enable the PVD Exti Line 16.
00204   * @retval None.
00205   */
00206 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
00207
00208 /**
00209   * @brief Disable the PVD EXTI Line 16.
00210   * @retval None.
00211   */
00212 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
00213
00214 /**
00215   * @brief Enable event on PVD Exti Line 16.
00216   * @retval None.
00217   */
00218 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
00219
00220 /**
00221   * @brief Disable event on PVD Exti Line 16.
00222   * @retval None.
00223   */
00224 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
00225
00226 /**
00227   * @brief Enable the PVD Extended Interrupt Rising Trigger.
00228   * @retval None.
00229   */
00230 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
00231
00232 /**
00233   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00234   * @retval None.
00235   */
00236 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
00237
00238 /**
00239   * @brief Enable the PVD Extended Interrupt Falling Trigger.
00240   * @retval None.
00241   */
00242 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
00243
00244
00245 /**
00246   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00247   * @retval None.
00248   */
00249 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
00250
00251
00252 /**
00253   * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
00254   * @retval None.
00255   */
00256 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
00257                                                              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
00258                                                             }while(0)
00259
00260 /**
00261   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00262   * This parameter can be:
00263   * @retval None.
00264   */
00265 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
00266                                                              __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
00267                                                             }while(0)
00268
00269 /**
00270   * @brief checks whether the specified PVD Exti interrupt flag is set or not.
00271   * @retval EXTI PVD Line Status.
00272   */
00273 #define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
00274
00275 /**
00276   * @brief Clear the PVD Exti flag.
00277   * @retval None.
00278   */
00279 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
00280
00281 /**
00282   * @brief  Generates a Software interrupt on PVD EXTI line.
00283   * @retval None
00284   */
00285 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
00286
00287 /**
00288   * @}
00289   */
00290
00291 /* Include PWR HAL Extension module */
00292 #include "stm32f4xx_hal_pwr_ex.h"
00293
00294 /* Exported functions --------------------------------------------------------*/
00295 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00296   * @{
00297   */
00298
00299 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00300   * @{
00301   */
00302 /* Initialization and de-initialization functions *****************************/
00303 void HAL_PWR_DeInit(void);
00304 void HAL_PWR_EnableBkUpAccess(void);
00305 void HAL_PWR_DisableBkUpAccess(void);
00306 /**
00307   * @}
00308   */
00309
00310 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00311   * @{
00312   */
00313 /* Peripheral Control functions  **********************************************/
00314 /* PVD configuration */
00315 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00316 void HAL_PWR_EnablePVD(void);
00317 void HAL_PWR_DisablePVD(void);
00318
00319 /* WakeUp pins configuration */
00320 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
00321 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00322
00323 /* Low Power modes entry */
00324 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00325 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00326 void HAL_PWR_EnterSTANDBYMode(void);
00327
00328 /* Power PVD IRQ Handler */
00329 void HAL_PWR_PVD_IRQHandler(void);
00330 void HAL_PWR_PVDCallback(void);
00331
00332 /* Cortex System Control functions  *******************************************/
00333 void HAL_PWR_EnableSleepOnExit(void);
00334 void HAL_PWR_DisableSleepOnExit(void);
00335 void HAL_PWR_EnableSEVOnPend(void);
00336 void HAL_PWR_DisableSEVOnPend(void);
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /* Private types -------------------------------------------------------------*/
00346 /* Private variables ---------------------------------------------------------*/
00347 /* Private constants ---------------------------------------------------------*/
00348 /** @defgroup PWR_Private_Constants PWR Private Constants
00349   * @{
00350   */
00351
00352 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
00353   * @{
00354   */
00355 #define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_MR16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup PWR_register_alias_address PWR Register alias address
00361   * @{
00362   */
00363 /* ------------- PWR registers bit address in the alias region ---------------*/
00364 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
00365 #define PWR_CR_OFFSET            0x00U
00366 #define PWR_CSR_OFFSET           0x04U
00367 #define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
00368 #define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
00374   * @{
00375   */
00376 /* --- CR Register ---*/
00377 /* Alias word address of DBP bit */
00378 #define DBP_BIT_NUMBER   POSITION_VAL(PWR_CR_DBP)
00379 #define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
00380
00381 /* Alias word address of PVDE bit */
00382 #define PVDE_BIT_NUMBER  POSITION_VAL(PWR_CR_PVDE)
00383 #define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
00384
00385 /* Alias word address of PMODE bit */
00386 #define PMODE_BIT_NUMBER  POSITION_VAL(PWR_CR_PMODE)
00387 #define CR_PMODE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
00393   * @{
00394   */
00395 /* --- CSR Register ---*/
00396 /* Alias word address of EWUP bit */
00397 #define EWUP_BIT_NUMBER  POSITION_VAL(PWR_CSR_EWUP)
00398 #define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
00399 /**
00400   * @}
00401   */
00402
00403 /**
00404   * @}
00405   */
00406 /* Private macros ------------------------------------------------------------*/
00407 /** @defgroup PWR_Private_Macros PWR Private Macros
00408   * @{
00409   */
00410
00411 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
00412   * @{
00413   */
00414 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00415                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00416                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00417                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00418 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
00419                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
00420                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
00421                               ((MODE) == PWR_PVD_MODE_NORMAL))
00422 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00423                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00424 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
00425 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
00426 /**
00427   * @}
00428   */
00429
00430 /**
00431   * @}
00432   */
00433
00434 /**
00435   * @}
00436   */
00437
00438 /**
00439   * @}
00440   */
00441
00442 #ifdef __cplusplus
00443 }
00444 #endif
00445
00446
00447 #endif /* __STM32F4xx_HAL_PWR_H */
00448
00449 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr_ex.c Source File

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stm32f4xx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Extended PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of PWR extension peripheral:
00010   *           + Peripheral Extended features functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f4xx_hal.h"
00044
00045 /** @addtogroup STM32F4xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup PWREx PWREx
00050   * @brief PWR HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_PWR_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @addtogroup PWREx_Private_Constants
00059   * @{
00060   */
00061 #define PWR_OVERDRIVE_TIMEOUT_VALUE  1000U
00062 #define PWR_UDERDRIVE_TIMEOUT_VALUE  1000U
00063 #define PWR_BKPREG_TIMEOUT_VALUE     1000U
00064 #define PWR_VOSRDY_TIMEOUT_VALUE     1000U
00065 /**
00066   * @}
00067   */
00068
00069
00070 /* Private macro -------------------------------------------------------------*/
00071 /* Private variables ---------------------------------------------------------*/
00072 /* Private function prototypes -----------------------------------------------*/
00073 /* Private functions ---------------------------------------------------------*/
00074 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
00075   *  @{
00076   */
00077
00078 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
00079   *  @brief Peripheral Extended features functions
00080   *
00081 @verbatim
00082
00083  ===============================================================================
00084                  ##### Peripheral extended features functions #####
00085  ===============================================================================
00086
00087     *** Main and Backup Regulators configuration ***
00088     ================================================
00089     [..]
00090       (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
00091           the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
00092           retained even in Standby or VBAT mode when the low power backup regulator
00093           is enabled. It can be considered as an internal EEPROM when VBAT is
00094           always present. You can use the HAL_PWREx_EnableBkUpReg() function to
00095           enable the low power backup regulator.
00096
00097       (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
00098           the backup SRAM is powered from VDD which replaces the VBAT power supply to
00099           save battery life.
00100
00101       (+) The backup SRAM is not mass erased by a tamper event. It is read
00102           protected to prevent confidential data, such as cryptographic private
00103           key, from being accessed. The backup SRAM can be erased only through
00104           the Flash interface when a protection level change from level 1 to
00105           level 0 is requested.
00106       -@- Refer to the description of Read protection (RDP) in the Flash
00107           programming manual.
00108
00109       (+) The main internal regulator can be configured to have a tradeoff between
00110           performance and power consumption when the device does not operate at
00111           the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
00112           macro which configure VOS bit in PWR_CR register
00113
00114         Refer to the product datasheets for more details.
00115
00116     *** FLASH Power Down configuration ****
00117     =======================================
00118     [..]
00119       (+) By setting the FPDS bit in the PWR_CR register by using the
00120           HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
00121           down mode when the device enters Stop mode. When the Flash memory
00122           is in power down mode, an additional startup delay is incurred when
00123           waking up from Stop mode.
00124
00125            (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
00126            is OFF and the HSI or HSE clock source is selected as system clock.
00127            The new value programmed is active only when the PLL is ON.
00128            When the PLL is OFF, the voltage scale 3 is automatically selected.
00129         Refer to the datasheets for more details.
00130
00131     *** Over-Drive and Under-Drive configuration ****
00132     =================================================
00133     [..]
00134        (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
00135            2 operating modes available:
00136         (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
00137              voltage scaling (scale 1, scale 2 or scale 3)
00138         (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
00139             higher frequency than the normal mode for a given voltage scaling (scale 1,
00140             scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
00141             disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
00142             the sequence described in Reference manual.
00143
00144        (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
00145            supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
00146            and internal SRAM. 2 operating modes are available:
00147          (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
00148               available when the main regulator or the low power regulator is used in Scale 3 or
00149               low voltage mode.
00150          (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
00151               available when the main regulator or the low power regulator is in low voltage mode.
00152
00153 @endverbatim
00154   * @{
00155   */
00156
00157 /**
00158   * @brief Enables the Backup Regulator.
00159   * @retval HAL status
00160   */
00161 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
00162 {
00163   uint32_t tickstart = 0U;
00164
00165   *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
00166
00167   /* Get tick */
00168   tickstart = HAL_GetTick();
00169
00170   /* Wait till Backup regulator ready flag is set */
00171   while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
00172   {
00173     if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
00174     {
00175       return HAL_TIMEOUT;
00176     }
00177   }
00178   return HAL_OK;
00179 }
00180
00181 /**
00182   * @brief Disables the Backup Regulator.
00183   * @retval HAL status
00184   */
00185 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
00186 {
00187   uint32_t tickstart = 0U;
00188
00189   *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
00190
00191   /* Get tick */
00192   tickstart = HAL_GetTick();
00193
00194   /* Wait till Backup regulator ready flag is set */
00195   while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
00196   {
00197     if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
00198     {
00199       return HAL_TIMEOUT;
00200     }
00201   }
00202   return HAL_OK;
00203 }
00204
00205 /**
00206   * @brief Enables the Flash Power Down in Stop mode.
00207   * @retval None
00208   */
00209 void HAL_PWREx_EnableFlashPowerDown(void)
00210 {
00211   *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
00212 }
00213
00214 /**
00215   * @brief Disables the Flash Power Down in Stop mode.
00216   * @retval None
00217   */
00218 void HAL_PWREx_DisableFlashPowerDown(void)
00219 {
00220   *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
00221 }
00222
00223 /**
00224   * @brief Return Voltage Scaling Range.
00225   * @retval The configured scale for the regulator voltage(VOS bit field).
00226   *         The returned value can be one of the following:
00227   *            - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
00228   *            - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
00229   *            - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
00230   */
00231 uint32_t HAL_PWREx_GetVoltageRange(void)
00232 {
00233   return (PWR->CR & PWR_CR_VOS);
00234 }
00235
00236 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
00237 /**
00238   * @brief Configures the main internal regulator output voltage.
00239   * @param  VoltageScaling: specifies the regulator output voltage to achieve
00240   *         a tradeoff between performance and power consumption.
00241   *          This parameter can be one of the following values:
00242   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
00243   *                                               the maximum value of fHCLK = 168 MHz.
00244   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
00245   *                                               the maximum value of fHCLK = 144 MHz.
00246   * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
00247   *        a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
00248   *        When moving from Range 2 to Range 1, the system frequency can be increased to
00249   *        a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
00250   * @retval HAL Status
00251   */
00252 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00253 {
00254   uint32_t tickstart = 0U;
00255
00256   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
00257
00258   /* Enable PWR RCC Clock Peripheral */
00259   __HAL_RCC_PWR_CLK_ENABLE();
00260
00261   /* Set Range */
00262   __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
00263
00264   /* Get Start Tick*/
00265   tickstart = HAL_GetTick();
00266   while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
00267   {
00268     if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
00269     {
00270       return HAL_TIMEOUT;
00271     }
00272   }
00273
00274   return HAL_OK;
00275 }
00276
00277 #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00278       defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
00279       defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
00280       defined(STM32F479xx)
00281 /**
00282   * @brief Configures the main internal regulator output voltage.
00283   * @param  VoltageScaling: specifies the regulator output voltage to achieve
00284   *         a tradeoff between performance and power consumption.
00285   *          This parameter can be one of the following values:
00286   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
00287   *                                               the maximum value of fHCLK is 168 MHz. It can be extended to
00288   *                                               180 MHz by activating the over-drive mode.
00289   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
00290   *                                               the maximum value of fHCLK is 144 MHz. It can be extended to,
00291   *                                               168 MHz by activating the over-drive mode.
00292   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
00293   *                                               the maximum value of fHCLK is 120 MHz.
00294   * @note To update the system clock frequency(SYSCLK):
00295   *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
00296   *        - Call the HAL_RCC_OscConfig() to configure the PLL.
00297   *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
00298   *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
00299   * @note The scale can be modified only when the HSI or HSE clock source is selected
00300   *        as system clock source, otherwise the API returns HAL_ERROR.
00301   * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
00302   *       value in the PWR_CR1 register are not taken in account.
00303   * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
00304   * @note The new voltage scale is active only when the PLL is ON.
00305   * @retval HAL Status
00306   */
00307 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00308 {
00309   uint32_t tickstart = 0U;
00310
00311   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
00312
00313   /* Enable PWR RCC Clock Peripheral */
00314   __HAL_RCC_PWR_CLK_ENABLE();
00315
00316   /* Check if the PLL is used as system clock or not */
00317   if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
00318   {
00319     /* Disable the main PLL */
00320     __HAL_RCC_PLL_DISABLE();
00321
00322     /* Get Start Tick */
00323     tickstart = HAL_GetTick();
00324     /* Wait till PLL is disabled */
00325     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00326     {
00327       if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00328       {
00329         return HAL_TIMEOUT;
00330       }
00331     }
00332
00333     /* Set Range */
00334     __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
00335
00336     /* Enable the main PLL */
00337     __HAL_RCC_PLL_ENABLE();
00338
00339     /* Get Start Tick */
00340     tickstart = HAL_GetTick();
00341     /* Wait till PLL is ready */
00342     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00343     {
00344       if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00345       {
00346         return HAL_TIMEOUT;
00347       }
00348     }
00349
00350     /* Get Start Tick */
00351     tickstart = HAL_GetTick();
00352     while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
00353     {
00354       if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
00355       {
00356         return HAL_TIMEOUT;
00357       }
00358     }
00359   }
00360   else
00361   {
00362     return HAL_ERROR;
00363   }
00364
00365   return HAL_OK;
00366 }
00367 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00368
00369 #if defined(STM32F469xx) || defined(STM32F479xx)
00370 /**
00371   * @brief Enables Wakeup Pin Detection on high level (rising edge).
00372   * @retval None
00373   */
00374 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
00375 {
00376   *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
00377 }
00378
00379 /**
00380   * @brief Enables Wakeup Pin Detection on low level (falling edge).
00381   * @retval None
00382   */
00383 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
00384 {
00385   *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
00386 }
00387 #endif /* STM32F469xx || STM32F479xx */
00388
00389 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
00390     defined(STM32F411xE)
00391 /**
00392   * @brief Enables Main Regulator low voltage mode.
00393   * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
00394   * @retval None
00395   */
00396 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
00397 {
00398   *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
00399 }
00400
00401 /**
00402   * @brief Disables Main Regulator low voltage mode.
00403   * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
00404   * @retval None
00405   */
00406 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
00407 {
00408   *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
00409 }
00410
00411 /**
00412   * @brief Enables Low Power Regulator low voltage mode.
00413   * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
00414   * @retval None
00415   */
00416 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
00417 {
00418   *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
00419 }
00420
00421 /**
00422   * @brief Disables Low Power Regulator low voltage mode.
00423   * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
00424   * @retval None
00425   */
00426 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
00427 {
00428   *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
00429 }
00430
00431 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
00432
00433 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00434     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00435 /**
00436   * @brief  Activates the Over-Drive mode.
00437   * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
00438   *         This mode allows the CPU and the core logic to operate at a higher frequency
00439   *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
00440   * @note   It is recommended to enter or exit Over-drive mode when the application is not running
00441   *         critical tasks and when the system clock source is either HSI or HSE.
00442   *         During the Over-drive switch activation, no peripheral clocks should be enabled.
00443   *         The peripheral clocks must be enabled once the Over-drive mode is activated.
00444   * @retval HAL status
00445   */
00446 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
00447 {
00448   uint32_t tickstart = 0U;
00449
00450   __HAL_RCC_PWR_CLK_ENABLE();
00451
00452   /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
00453   __HAL_PWR_OVERDRIVE_ENABLE();
00454
00455   /* Get tick */
00456   tickstart = HAL_GetTick();
00457
00458   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
00459   {
00460     if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00461     {
00462       return HAL_TIMEOUT;
00463     }
00464   }
00465
00466   /* Enable the Over-drive switch */
00467   __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
00468
00469   /* Get tick */
00470   tickstart = HAL_GetTick();
00471
00472   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
00473   {
00474     if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00475     {
00476       return HAL_TIMEOUT;
00477     }
00478   }
00479   return HAL_OK;
00480 }
00481
00482 /**
00483   * @brief  Deactivates the Over-Drive mode.
00484   * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
00485   *         This mode allows the CPU and the core logic to operate at a higher frequency
00486   *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
00487   * @note   It is recommended to enter or exit Over-drive mode when the application is not running
00488   *         critical tasks and when the system clock source is either HSI or HSE.
00489   *         During the Over-drive switch activation, no peripheral clocks should be enabled.
00490   *         The peripheral clocks must be enabled once the Over-drive mode is activated.
00491   * @retval HAL status
00492   */
00493 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
00494 {
00495   uint32_t tickstart = 0U;
00496
00497   __HAL_RCC_PWR_CLK_ENABLE();
00498
00499   /* Disable the Over-drive switch */
00500   __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
00501
00502   /* Get tick */
00503   tickstart = HAL_GetTick();
00504
00505   while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
00506   {
00507     if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00508     {
00509       return HAL_TIMEOUT;
00510     }
00511   }
00512
00513   /* Disable the Over-drive */
00514   __HAL_PWR_OVERDRIVE_DISABLE();
00515
00516   /* Get tick */
00517   tickstart = HAL_GetTick();
00518
00519   while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
00520   {
00521     if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
00522     {
00523       return HAL_TIMEOUT;
00524     }
00525   }
00526
00527   return HAL_OK;
00528 }
00529
00530 /**
00531   * @brief  Enters in Under-Drive STOP mode.
00532   *
00533   * @note   This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
00534   *
00535   * @note    This mode can be selected only when the Under-Drive is already active
00536   *
00537   * @note    This mode is enabled only with STOP low power mode.
00538   *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This
00539   *          mode is only available when the main regulator or the low power regulator
00540   *          is in low voltage mode
00541   *
00542   * @note   If the Under-drive mode was enabled, it is automatically disabled after
00543   *         exiting Stop mode.
00544   *         When the voltage regulator operates in Under-drive mode, an additional
00545   *         startup delay is induced when waking up from Stop mode.
00546   *
00547   * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
00548   *
00549   * @note   When exiting Stop mode by issuing an interrupt or a wake-up event,
00550   *         the HSI RC oscillator is selected as system clock.
00551   *
00552   * @note   When the voltage regulator operates in low power mode, an additional
00553   *         startup delay is incurred when waking up from Stop mode.
00554   *         By keeping the internal regulator ON during Stop mode, the consumption
00555   *         is higher although the startup time is reduced.
00556   *
00557   * @param  Regulator: specifies the regulator state in STOP mode.
00558   *          This parameter can be one of the following values:
00559   *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode
00560   *                 and Flash memory in power-down when the device is in Stop under-drive mode
00561   *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode
00562   *                and Flash memory in power-down when the device is in Stop under-drive mode
00563   * @param  STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
00564   *          This parameter can be one of the following values:
00565   *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
00566   *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
00567   * @retval None
00568   */
00569 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00570 {
00571   uint32_t tmpreg1 = 0U;
00572   uint32_t tickstart = 0U;
00573
00574   /* Check the parameters */
00575   assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
00576   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00577
00578   /* Enable Power ctrl clock */
00579   __HAL_RCC_PWR_CLK_ENABLE();
00580   /* Enable the Under-drive Mode ---------------------------------------------*/
00581   /* Clear Under-drive flag */
00582   __HAL_PWR_CLEAR_ODRUDR_FLAG();
00583
00584   /* Enable the Under-drive */
00585   __HAL_PWR_UNDERDRIVE_ENABLE();
00586
00587   /* Get tick */
00588   tickstart = HAL_GetTick();
00589
00590   /* Wait for UnderDrive mode is ready */
00591   while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
00592   {
00593     if((HAL_GetTick() - tickstart) > PWR_UDERDRIVE_TIMEOUT_VALUE)
00594     {
00595       return HAL_TIMEOUT;
00596     }
00597   }
00598
00599   /* Select the regulator state in STOP mode ---------------------------------*/
00600   tmpreg1 = PWR->CR;
00601   /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
00602   tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
00603
00604   /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
00605   tmpreg1 |= Regulator;
00606
00607   /* Store the new value */
00608   PWR->CR = tmpreg1;
00609
00610   /* Set SLEEPDEEP bit of Cortex System Control Register */
00611   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00612
00613   /* Select STOP mode entry --------------------------------------------------*/
00614   if(STOPEntry == PWR_SLEEPENTRY_WFI)
00615   {
00616     /* Request Wait For Interrupt */
00617     __WFI();
00618   }
00619   else
00620   {
00621     /* Request Wait For Event */
00622     __WFE();
00623   }
00624   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00625   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
00626
00627   return HAL_OK;
00628 }
00629
00630 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00631 /**
00632   * @}
00633   */
00634
00635 /**
00636   * @}
00637   */
00638
00639 #endif /* HAL_PWR_MODULE_ENABLED */
00640 /**
00641   * @}
00642   */
00643
00644 /**
00645   * @}
00646   */
00647
00648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_pwr_ex.h Source File

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stm32f4xx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of PWR HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_PWR_EX_H
00040 #define __STM32F4xx_HAL_PWR_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWREx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
00060   * @{
00061   */
00062 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00063     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00064
00065 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
00066   * @{
00067   */
00068 #define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR_MRUDS
00069 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
00075   * @{
00076   */
00077 #define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
00078 #define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
00079 #define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
00080 /**
00081   * @}
00082   */
00083 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00084
00085 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
00086   * @{
00087   */
00088 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
00089 #define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
00090 #define PWR_REGULATOR_VOLTAGE_SCALE2         ((uint32_t)0x00000000U) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
00091 #else
00092 #define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
00093                                                                        180 MHz by activating the over-drive mode. */
00094 #define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR_VOS_1           /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
00095                                                                        168 MHz by activating the over-drive mode. */
00096 #define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR_VOS_0           /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
00097 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
00098 /**
00099   * @}
00100   */
00101 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
00102 /** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
00103   * @{
00104   */
00105 #define PWR_WAKEUP_PIN2                 ((uint32_t)0x00000080U)
00106 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00107 #define PWR_WAKEUP_PIN3                 ((uint32_t)0x00000040U)
00108 #endif /* STM32F410xx */
00109 /**
00110   * @}
00111   */
00112 #endif /* STM32F410xx || STM32F446xx */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /* Exported macro ------------------------------------------------------------*/
00119 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
00120   *  @{
00121   */
00122
00123 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
00124 /** @brief  macros configure the main internal regulator output voltage.
00125   * @param  __REGULATOR__: specifies the regulator output voltage to achieve
00126   *         a tradeoff between performance and power consumption when the device does
00127   *         not operate at the maximum frequency (refer to the datasheets for more details).
00128   *          This parameter can be one of the following values:
00129   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
00130   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
00131   * @retval None
00132   */
00133 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
00134                                                             __IO uint32_t tmpreg = 0x00U;                        \
00135                                                             MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
00136                                                             /* Delay after an RCC peripheral clock enabling */  \
00137                                                             tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
00138                                                             UNUSED(tmpreg);                                     \
00139                                                           } while(0)
00140 #else
00141 /** @brief  macros configure the main internal regulator output voltage.
00142   * @param  __REGULATOR__: specifies the regulator output voltage to achieve
00143   *         a tradeoff between performance and power consumption when the device does
00144   *         not operate at the maximum frequency (refer to the datasheets for more details).
00145   *          This parameter can be one of the following values:
00146   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
00147   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
00148   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
00149   * @retval None
00150   */
00151 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
00152                                                             __IO uint32_t tmpreg = 0x00U;                        \
00153                                                             MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
00154                                                             /* Delay after an RCC peripheral clock enabling */  \
00155                                                             tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
00156                                                             UNUSED(tmpreg);                                     \
00157                                                           } while(0)
00158 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
00159
00160 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00161     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00162 /** @brief Macros to enable or disable the Over drive mode.
00163   * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
00164   */
00165 #define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
00166 #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
00167
00168 /** @brief Macros to enable or disable the Over drive switching.
00169   * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
00170   */
00171 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
00172 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
00173
00174 /** @brief Macros to enable or disable the Under drive mode.
00175   * @note  This mode is enabled only with STOP low power mode.
00176   *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This
00177   *        mode is only available when the main regulator or the low power regulator
00178   *        is in low voltage mode.
00179   * @note  If the Under-drive mode was enabled, it is automatically disabled after
00180   *        exiting Stop mode.
00181   *        When the voltage regulator operates in Under-drive mode, an additional
00182   *        startup delay is induced when waking up from Stop mode.
00183   */
00184 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
00185 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
00186
00187 /** @brief  Check PWR flag is set or not.
00188   * @note   These macros can be used only for STM32F42xx/STM3243xx devices.
00189   * @param  __FLAG__: specifies the flag to check.
00190   *         This parameter can be one of the following values:
00191   *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
00192   *                                 is ready
00193   *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
00194   *                                   switching is ready
00195   *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
00196   *                                 is enabled in Stop mode
00197   * @retval The new state of __FLAG__ (TRUE or FALSE).
00198   */
00199 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
00200
00201 /** @brief Clear the Under-Drive Ready flag.
00202   * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
00203   */
00204 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
00205
00206 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported functions --------------------------------------------------------*/
00212 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
00213   *  @{
00214   */
00215
00216 /** @addtogroup PWREx_Exported_Functions_Group1
00217   * @{
00218   */
00219 void HAL_PWREx_EnableFlashPowerDown(void);
00220 void HAL_PWREx_DisableFlashPowerDown(void);
00221 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
00222 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
00223 uint32_t HAL_PWREx_GetVoltageRange(void);
00224 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00225
00226 #if defined(STM32F469xx) || defined(STM32F479xx)
00227 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
00228 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
00229 #endif /* STM32F469xx || STM32F479xx */
00230
00231 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
00232     defined(STM32F401xE) || defined(STM32F411xE)
00233 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
00234 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
00235 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
00236 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
00237 #endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE */
00238
00239 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
00240     defined(STM32F469xx) || defined(STM32F479xx)
00241 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
00242 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
00243 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00244 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00245
00246 /**
00247   * @}
00248   */
00249
00250 /**
00251   * @}
00252   */
00253 /* Private types -------------------------------------------------------------*/
00254 /* Private variables ---------------------------------------------------------*/
00255 /* Private constants ---------------------------------------------------------*/
00256 /** @defgroup PWREx_Private_Constants PWREx Private Constants
00257   * @{
00258   */
00259
00260 /** @defgroup PWREx_register_alias_address PWREx Register alias address
00261   * @{
00262   */
00263 /* ------------- PWR registers bit address in the alias region ---------------*/
00264 /* --- CR Register ---*/
00265 /* Alias word address of FPDS bit */
00266 #define FPDS_BIT_NUMBER          POSITION_VAL(PWR_CR_FPDS)
00267 #define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
00268
00269 /* Alias word address of ODEN bit   */
00270 #define ODEN_BIT_NUMBER          POSITION_VAL(PWR_CR_ODEN)
00271 #define CR_ODEN_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
00272
00273 /* Alias word address of ODSWEN bit */
00274 #define ODSWEN_BIT_NUMBER        POSITION_VAL(PWR_CR_ODSWEN)
00275 #define CR_ODSWEN_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
00276
00277 /* Alias word address of MRLVDS bit */
00278 #define MRLVDS_BIT_NUMBER        POSITION_VAL(PWR_CR_MRLVDS)
00279 #define CR_MRLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
00280
00281 /* Alias word address of LPLVDS bit */
00282 #define LPLVDS_BIT_NUMBER        POSITION_VAL(PWR_CR_LPLVDS)
00283 #define CR_LPLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
00284
00285  /**
00286   * @}
00287   */
00288
00289 /** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
00290   * @{
00291   */
00292 /* --- CSR Register ---*/
00293 /* Alias word address of BRE bit */
00294 #define BRE_BIT_NUMBER   POSITION_VAL(PWR_CSR_BRE)
00295 #define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
00296
00297 #if defined(STM32F469xx) || defined(STM32F479xx)
00298 /* Alias word address of WUPP bit */
00299 #define WUPP_BIT_NUMBER   POSITION_VAL(PWR_CSR_WUPP)
00300 #define CSR_WUPP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
00301 #endif /* STM32F469xx || STM32F479xx */
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /* Private macros ------------------------------------------------------------*/
00311 /** @defgroup PWREx_Private_Macros PWREx Private Macros
00312   * @{
00313   */
00314
00315 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
00316   * @{
00317   */
00318 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00319     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00320 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
00321                                                 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
00322 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00323
00324 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
00325 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00326                                                ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
00327 #else
00328 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00329                                                ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
00330                                                ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
00331 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
00332
00333 #if defined(STM32F446xx)
00334 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
00335 #elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00336 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
00337                                 ((PIN) == PWR_WAKEUP_PIN3))
00338 #else
00339 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
00340 #endif /* STM32F446xx */
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /**
00350   * @}
00351   */
00352
00353 /**
00354   * @}
00355   */
00356
00357 #ifdef __cplusplus
00358 }
00359 #endif
00360
00361
00362 #endif /* __STM32F4xx_HAL_PWR_EX_H */
00363
00364 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_qspi.c Source File

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stm32f4xx_hal_qspi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_qspi.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   QSPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the QuadSPI interface (QSPI).
00010   *           + Initialization and de-initialization functions
00011   *           + Indirect functional mode management
00012   *           + Memory-mapped functional mode management
00013   *           + Auto-polling functional mode management
00014   *           + Interrupts and flags management
00015   *           + DMA channel configuration for indirect functional mode
00016   *           + Errors management and abort functionality
00017   *
00018   @verbatim
00019  ===============================================================================
00020                         ##### How to use this driver #####
00021  ===============================================================================
00022   [..]
00023     *** Initialization ***
00024     ======================
00025     [..]
00026       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
00027         (##) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
00028         (##) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
00029         (##) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00030         (##) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
00031         (##) If interrupt mode is used, enable and configure QuadSPI global
00032             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00033         (##) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
00034             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
00035             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
00036             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00037       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
00038           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
00039
00040     *** Indirect functional mode ***
00041     ================================
00042     [..]
00043       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
00044           functions :
00045          (##) Instruction phase : the mode used and if present the instruction opcode.
00046          (##) Address phase : the mode used and if present the size and the address value.
00047          (##) Alternate-bytes phase : the mode used and if present the size and the alternate
00048              bytes values.
00049          (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00050          (##) Data phase : the mode used and if present the number of bytes.
00051          (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00052              if activated.
00053          (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00054       (#) If no data is required for the command, it is sent directly to the memory :
00055          (##) In polling mode, the output of the function is done when the transfer is complete.
00056          (##) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
00057       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
00058           HAL_QSPI_Transmit_IT() after the command configuration :
00059          (##) In polling mode, the output of the function is done when the transfer is complete.
00060          (##) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00061              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00062          (##) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
00063              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00064       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
00065           HAL_QSPI_Receive_IT() after the command configuration :
00066          (##) In polling mode, the output of the function is done when the transfer is complete.
00067          (##) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00068              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00069          (##) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
00070              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00071
00072     *** Auto-polling functional mode ***
00073     ====================================
00074     [..]
00075       (#) Configure the command sequence and the auto-polling functional mode using the
00076           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
00077          (##) Instruction phase : the mode used and if present the instruction opcode.
00078          (##) Address phase : the mode used and if present the size and the address value.
00079          (##) Alternate-bytes phase : the mode used and if present the size and the alternate
00080              bytes values.
00081          (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00082          (##) Data phase : the mode used.
00083          (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00084              if activated.
00085          (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00086          (##) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00087              the polling interval and the automatic stop activation.
00088       (#) After the configuration :
00089          (##) In polling mode, the output of the function is done when the status match is reached. The
00090              automatic stop is activated to avoid an infinite loop.
00091          (##) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
00092
00093     *** Memory-mapped functional mode ***
00094     =====================================
00095     [..]
00096       (#) Configure the command sequence and the memory-mapped functional mode using the
00097           HAL_QSPI_MemoryMapped() functions :
00098          (##) Instruction phase : the mode used and if present the instruction opcode.
00099          (##) Address phase : the mode used and the size.
00100          (##) Alternate-bytes phase : the mode used and if present the size and the alternate
00101              bytes values.
00102          (##) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00103          (##) Data phase : the mode used.
00104          (##) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00105              if activated.
00106          (##) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00107          (##) The timeout activation and the timeout period.
00108       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
00109           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
00110
00111     *** Errors management and abort functionality ***
00112     ==================================================
00113     [..]
00114       (#) HAL_QSPI_GetError() function gives the error rised during the last operation.
00115       (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
00116       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
00117
00118     *** Workarounds linked to Silicon Limitation ***
00119     ====================================================
00120     [..]
00121       (#) Workarounds Implemented inside HAL Driver
00122          (++) Extra data written in the FIFO at the end of a read transfer
00123
00124   @endverbatim
00125   ******************************************************************************
00126   * @attention
00127   *
00128   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00129   *
00130   * Redistribution and use in source and binary forms, with or without modification,
00131   * are permitted provided that the following conditions are met:
00132   *   1. Redistributions of source code must retain the above copyright notice,
00133   *      this list of conditions and the following disclaimer.
00134   *   2. Redistributions in binary form must reproduce the above copyright notice,
00135   *      this list of conditions and the following disclaimer in the documentation
00136   *      and/or other materials provided with the distribution.
00137   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00138   *      may be used to endorse or promote products derived from this software
00139   *      without specific prior written permission.
00140   *
00141   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00142   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00143   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00144   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00145   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00146   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00147   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00148   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00149   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00150   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00151   *
00152   ******************************************************************************
00153   */
00154
00155 /* Includes ------------------------------------------------------------------*/
00156 #include "stm32f4xx_hal.h"
00157
00158 /** @addtogroup STM32F4xx_HAL_Driver
00159   * @{
00160   */
00161
00162 /** @defgroup QSPI QSPI
00163   * @brief HAL QSPI module driver
00164   * @{
00165   */
00166 #ifdef HAL_QSPI_MODULE_ENABLED
00167
00168 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00169
00170 /* Private typedef -----------------------------------------------------------*/
00171 /* Private define ------------------------------------------------------------*/
00172 /** @addtogroup QSPI_Private_Constants
00173   * @{
00174   */
00175 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U)          /*!<Indirect write mode*/
00176 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
00177 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
00178 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
00179 /**
00180   * @}
00181   */
00182
00183 /* Private macro -------------------------------------------------------------*/
00184 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
00185   * @{
00186   */
00187 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00188                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00189                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00190                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00191 /**
00192   * @}
00193   */
00194
00195 /* Private variables ---------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
00198   * @{
00199   */
00200 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
00201 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
00202 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00203 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00204 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
00205 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
00206 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported functions ---------------------------------------------------------*/
00212
00213 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
00214   * @{
00215   */
00216
00217 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00218   *  @brief    Initialization and Configuration functions
00219   *
00220 @verbatim
00221 ===============================================================================
00222             ##### Initialization and Configuration functions #####
00223  ===============================================================================
00224     [..]
00225     This subsection provides a set of functions allowing to :
00226       (+) Initialize the QuadSPI.
00227       (+) De-initialize the QuadSPI.
00228
00229 @endverbatim
00230   * @{
00231   */
00232
00233 /**
00234   * @brief Initializes the QSPI mode according to the specified parameters
00235   *        in the QSPI_InitTypeDef and creates the associated handle.
00236   * @param hqspi: qspi handle
00237   * @retval HAL status
00238   */
00239 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
00240 {
00241   HAL_StatusTypeDef status = HAL_ERROR;
00242
00243   /* Check the QSPI handle allocation */
00244   if(hqspi == NULL)
00245   {
00246     return HAL_ERROR;
00247   }
00248
00249   /* Check the parameters */
00250   assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
00251   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
00252   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
00253   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
00254   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
00255   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
00256   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
00257   assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
00258
00259   if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
00260   {
00261     assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
00262   }
00263
00264   /* Process locked */
00265   __HAL_LOCK(hqspi);
00266
00267   if(hqspi->State == HAL_QSPI_STATE_RESET)
00268   {
00269     /* Allocate lock resource and initialize it */
00270     hqspi->Lock = HAL_UNLOCKED;
00271
00272     /* Init the low level hardware : GPIO, CLOCK */
00273     HAL_QSPI_MspInit(hqspi);
00274
00275     /* Configure the default timeout for the QSPI memory access */
00276     HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
00277   }
00278
00279   /* Configure QSPI FIFO Threshold */
00280   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U));
00281
00282   /* Wait till BUSY flag reset */
00283   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
00284
00285   if(status == HAL_OK)
00286   {
00287
00288     /* Configure QSPI Clock Prescaler and Sample Shift */
00289     MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
00290
00291     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
00292     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
00293                ((hqspi->Init.FlashSize << 16U) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
00294
00295     /* Enable the QSPI peripheral */
00296     __HAL_QSPI_ENABLE(hqspi);
00297
00298     /* Set QSPI error code to none */
00299     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00300
00301     /* Initialize the QSPI state */
00302     hqspi->State = HAL_QSPI_STATE_READY;
00303   }
00304
00305   /* Release Lock */
00306   __HAL_UNLOCK(hqspi);
00307
00308   /* Return function status */
00309   return status;
00310 }
00311
00312 /**
00313   * @brief DeInitializes the QSPI peripheral
00314   * @param hqspi: qspi handle
00315   * @retval HAL status
00316   */
00317 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
00318 {
00319   /* Check the QSPI handle allocation */
00320   if(hqspi == NULL)
00321   {
00322     return HAL_ERROR;
00323   }
00324
00325   /* Process locked */
00326   __HAL_LOCK(hqspi);
00327
00328   /* Disable the QSPI Peripheral Clock */
00329   __HAL_QSPI_DISABLE(hqspi);
00330
00331   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00332   HAL_QSPI_MspDeInit(hqspi);
00333
00334   /* Set QSPI error code to none */
00335   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00336
00337   /* Initialize the QSPI state */
00338   hqspi->State = HAL_QSPI_STATE_RESET;
00339
00340   /* Release Lock */
00341   __HAL_UNLOCK(hqspi);
00342
00343   return HAL_OK;
00344 }
00345
00346 /**
00347   * @brief QSPI MSP Init
00348   * @param hqspi: QSPI handle
00349   * @retval None
00350   */
00351 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
00352 {
00353   /* Prevent unused argument(s) compilation warning */
00354   UNUSED(hqspi);
00355   /* NOTE : This function should not be modified, when the callback is needed,
00356             the HAL_QSPI_MspInit can be implemented in the user file
00357    */
00358 }
00359
00360 /**
00361   * @brief QSPI MSP DeInit
00362   * @param hqspi: QSPI handle
00363   * @retval None
00364   */
00365 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
00366 {
00367   /* Prevent unused argument(s) compilation warning */
00368   UNUSED(hqspi);
00369   /* NOTE : This function should not be modified, when the callback is needed,
00370             the HAL_QSPI_MspDeInit can be implemented in the user file
00371    */
00372 }
00373
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
00379   *  @brief QSPI Transmit/Receive functions
00380   *
00381 @verbatim
00382  ===============================================================================
00383                       ##### IO operation functions #####
00384  ===============================================================================
00385        [..]
00386     This subsection provides a set of functions allowing to :
00387       (+) Handle the interrupts.
00388       (+) Handle the command sequence.
00389       (+) Transmit data in blocking, interrupt or DMA mode.
00390       (+) Receive data in blocking, interrupt or DMA mode.
00391       (+) Manage the auto-polling functional mode.
00392       (+) Manage the memory-mapped functional mode.
00393
00394 @endverbatim
00395   * @{
00396   */
00397
00398 /**
00399   * @brief This function handles QSPI interrupt request.
00400   * @param hqspi: QSPI handle
00401   * @retval None.
00402   */
00403 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
00404 {
00405   __IO uint32_t *data_reg;
00406   uint32_t flag = 0U, itsource = 0U;
00407
00408   /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
00409   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
00410   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
00411
00412   if((flag != RESET) && (itsource != RESET))
00413   {
00414     data_reg = &hqspi->Instance->DR;
00415
00416     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00417     {
00418       /* Transmission process */
00419       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
00420       {
00421         if (hqspi->TxXferCount > 0U)
00422         {
00423           /* Fill the FIFO until it is full */
00424           *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00425           hqspi->TxXferCount--;
00426         }
00427         else
00428         {
00429           /* No more data available for the transfer */
00430           break;
00431         }
00432       }
00433     }
00434     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00435     {
00436       /* Receiving Process */
00437       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
00438       {
00439         if (hqspi->RxXferCount > 0U)
00440         {
00441           /* Read the FIFO until it is empty */
00442           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00443           hqspi->RxXferCount--;
00444         }
00445         else
00446         {
00447           /* All data have been received for the transfer */
00448           break;
00449         }
00450       }
00451     }
00452
00453     /* FIFO Threshold callback */
00454     HAL_QSPI_FifoThresholdCallback(hqspi);
00455   }
00456
00457   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
00458   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
00459   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
00460
00461   if((flag != RESET) && (itsource != RESET))
00462   {
00463     /* Clear interrupt */
00464     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00465
00466     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
00467     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00468
00469     /* Transfer complete callback */
00470     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00471     {
00472       /* Clear Busy bit */
00473       HAL_QSPI_Abort(hqspi);
00474
00475       /* TX Complete callback */
00476       HAL_QSPI_TxCpltCallback(hqspi);
00477     }
00478     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00479     {
00480       data_reg = &hqspi->Instance->DR;
00481       while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
00482       {
00483         if (hqspi->RxXferCount > 0U)
00484         {
00485           /* Read the last data received in the FIFO until it is empty */
00486           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00487           hqspi->RxXferCount--;
00488         }
00489         else
00490         {
00491           /* All data have been received for the transfer */
00492           break;
00493         }
00494       }
00495
00496       /* Workaround - Extra data written in the FIFO at the end of a read transfer */
00497       HAL_QSPI_Abort(hqspi);
00498
00499       /* RX Complete callback */
00500       HAL_QSPI_RxCpltCallback(hqspi);
00501     }
00502     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
00503     {
00504       /* Command Complete callback */
00505       HAL_QSPI_CmdCpltCallback(hqspi);
00506     }
00507
00508     /* Change state of QSPI */
00509     hqspi->State = HAL_QSPI_STATE_READY;
00510   }
00511
00512   /* QSPI Status Match interrupt occurred ------------------------------------*/
00513   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
00514   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
00515
00516   if((flag != RESET) && (itsource != RESET))
00517   {
00518     /* Clear interrupt */
00519     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
00520
00521     /* Check if the automatic poll mode stop is activated */
00522     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
00523     {
00524       /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
00525       __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
00526
00527       /* Change state of QSPI */
00528       hqspi->State = HAL_QSPI_STATE_READY;
00529     }
00530
00531     /* Status match callback */
00532     HAL_QSPI_StatusMatchCallback(hqspi);
00533   }
00534
00535   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
00536   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
00537   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
00538
00539   if((flag != RESET) && (itsource != RESET))
00540   {
00541     /* Clear interrupt */
00542     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
00543
00544     /* Disable all the QSPI Interrupts */
00545     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00546
00547     /* Set error code */
00548     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
00549
00550     /* Change state of QSPI */
00551     hqspi->State = HAL_QSPI_STATE_ERROR;
00552
00553     /* Error callback */
00554     HAL_QSPI_ErrorCallback(hqspi);
00555   }
00556
00557   /* QSPI Time out interrupt occurred -----------------------------------------*/
00558   flag     = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
00559   itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
00560
00561   if((flag != RESET) && (itsource != RESET))
00562   {
00563     /* Clear interrupt */
00564     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
00565
00566     /* Time out callback */
00567     HAL_QSPI_TimeOutCallback(hqspi);
00568   }
00569 }
00570
00571 /**
00572   * @brief Sets the command configuration.
00573   * @param hqspi: QSPI handle
00574   * @param cmd : structure that contains the command configuration information
00575   * @param Timeout : Time out duration
00576   * @note   This function is used only in Indirect Read or Write Modes
00577   * @retval HAL status
00578   */
00579 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
00580 {
00581   HAL_StatusTypeDef status = HAL_ERROR;
00582
00583   /* Check the parameters */
00584   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00585   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00586   {
00587     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00588   }
00589
00590   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00591   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00592   {
00593     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00594   }
00595
00596   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00597   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00598   {
00599     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00600   }
00601
00602   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00603   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00604
00605   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00606   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00607   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00608
00609   /* Process locked */
00610   __HAL_LOCK(hqspi);
00611
00612  if(hqspi->State == HAL_QSPI_STATE_READY)
00613   {
00614     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00615
00616     /* Update QSPI state */
00617     hqspi->State = HAL_QSPI_STATE_BUSY;
00618
00619     /* Wait till BUSY flag reset */
00620     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
00621
00622     if (status == HAL_OK)
00623     {
00624       /* Call the configuration function */
00625       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00626
00627       if (cmd->DataMode == QSPI_DATA_NONE)
00628       {
00629         /* When there is no data phase, the transfer start as soon as the configuration is done
00630         so wait until TC flag is set to go back in idle state */
00631         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
00632         {
00633           status = HAL_TIMEOUT;
00634         }
00635         else
00636         {
00637           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00638
00639           /* Update QSPI state */
00640           hqspi->State = HAL_QSPI_STATE_READY;
00641         }
00642
00643       }
00644       else
00645       {
00646         /* Update QSPI state */
00647         hqspi->State = HAL_QSPI_STATE_READY;
00648       }
00649     }
00650   }
00651   else
00652   {
00653     status = HAL_BUSY;
00654   }
00655
00656   /* Process unlocked */
00657   __HAL_UNLOCK(hqspi);
00658
00659   /* Return function status */
00660   return status;
00661 }
00662
00663 /**
00664   * @brief Sets the command configuration in interrupt mode.
00665   * @param hqspi: QSPI handle
00666   * @param cmd : structure that contains the command configuration information
00667   * @note   This function is used only in Indirect Read or Write Modes
00668   * @retval HAL status
00669   */
00670 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
00671 {
00672   HAL_StatusTypeDef status = HAL_ERROR;
00673
00674   /* Check the parameters */
00675   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00676   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00677   {
00678     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00679   }
00680
00681   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00682   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00683   {
00684     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00685   }
00686
00687   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00688   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00689   {
00690     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00691   }
00692
00693   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00694   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00695
00696   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00697   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00698   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00699
00700   /* Process locked */
00701   __HAL_LOCK(hqspi);
00702
00703    if(hqspi->State == HAL_QSPI_STATE_READY)
00704   {
00705     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00706
00707     /* Update QSPI state */
00708     hqspi->State = HAL_QSPI_STATE_BUSY;
00709
00710     /* Wait till BUSY flag reset */
00711     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
00712
00713     if (status == HAL_OK)
00714     {
00715       if (cmd->DataMode == QSPI_DATA_NONE)
00716       {
00717         /* When there is no data phase, the transfer start as soon as the configuration is done
00718         so activate TC and TE interrupts */
00719         /* Enable the QSPI Transfer Error Interrupt */
00720         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
00721       }
00722
00723       /* Call the configuration function */
00724       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00725
00726       if (cmd->DataMode != QSPI_DATA_NONE)
00727       {
00728         /* Update QSPI state */
00729         hqspi->State = HAL_QSPI_STATE_READY;
00730       }
00731     }
00732   }
00733   else
00734   {
00735     status = HAL_BUSY;
00736   }
00737
00738   /* Process unlocked */
00739   __HAL_UNLOCK(hqspi);
00740
00741   /* Return function status */
00742   return status;
00743 }
00744
00745 /**
00746   * @brief Transmit an amount of data in blocking mode.
00747   * @param hqspi: QSPI handle
00748   * @param pData: pointer to data buffer
00749   * @param Timeout : Time out duration
00750   * @note   This function is used only in Indirect Write Mode
00751   * @retval HAL status
00752   */
00753 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00754 {
00755   HAL_StatusTypeDef status = HAL_OK;
00756   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00757
00758   /* Process locked */
00759   __HAL_LOCK(hqspi);
00760
00761   if(hqspi->State == HAL_QSPI_STATE_READY)
00762   {
00763     if(pData != NULL )
00764     {
00765       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00766
00767       /* Update state */
00768       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00769
00770       /* Configure counters and size of the handle */
00771       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
00772       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
00773       hqspi->pTxBuffPtr = pData;
00774
00775       /* Configure QSPI: CCR register with functional as indirect write */
00776       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00777
00778       while(hqspi->TxXferCount > 0U)
00779       {
00780         /* Wait until FT flag is set to send data */
00781         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
00782         {
00783           status = HAL_TIMEOUT;
00784           break;
00785         }
00786
00787         *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00788         hqspi->TxXferCount--;
00789       }
00790
00791       if (status == HAL_OK)
00792       {
00793         /* Wait until TC flag is set to go back in idle state */
00794         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
00795         {
00796           status = HAL_TIMEOUT;
00797         }
00798         else
00799         {
00800           /* Clear Transfer Complete bit */
00801           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00802
00803           /* Clear Busy bit */
00804           status = HAL_QSPI_Abort(hqspi);
00805         }
00806       }
00807
00808       /* Update QSPI state */
00809       hqspi->State = HAL_QSPI_STATE_READY;
00810     }
00811     else
00812     {
00813       status = HAL_ERROR;
00814     }
00815   }
00816   else
00817   {
00818     status = HAL_BUSY;
00819   }
00820
00821   /* Process unlocked */
00822   __HAL_UNLOCK(hqspi);
00823
00824   return status;
00825 }
00826
00827
00828 /**
00829   * @brief Receive an amount of data in blocking mode
00830   * @param hqspi: QSPI handle
00831   * @param pData: pointer to data buffer
00832   * @param Timeout : Time out duration
00833   * @note   This function is used only in Indirect Read Mode
00834   * @retval HAL status
00835   */
00836 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00837 {
00838   HAL_StatusTypeDef status = HAL_OK;
00839   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
00840   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00841
00842   /* Process locked */
00843   __HAL_LOCK(hqspi);
00844
00845   if(hqspi->State == HAL_QSPI_STATE_READY)
00846   {
00847     if(pData != NULL )
00848     {
00849       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00850
00851       /* Update state */
00852       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
00853
00854       /* Configure counters and size of the handle */
00855       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
00856       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
00857       hqspi->pRxBuffPtr = pData;
00858
00859       /* Configure QSPI: CCR register with functional as indirect read */
00860       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
00861
00862       /* Start the transfer by re-writing the address in AR register */
00863       WRITE_REG(hqspi->Instance->AR, addr_reg);
00864
00865       while(hqspi->RxXferCount > 0U)
00866       {
00867         /* Wait until FT or TC flag is set to read received data */
00868         if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
00869         {
00870           status = HAL_TIMEOUT;
00871           break;
00872         }
00873
00874         *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00875         hqspi->RxXferCount--;
00876       }
00877
00878       if (status == HAL_OK)
00879       {
00880         /* Wait until TC flag is set to go back in idle state */
00881         if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
00882         {
00883           status = HAL_TIMEOUT;
00884         }
00885         else
00886         {
00887           /* Clear Transfer Complete bit */
00888           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00889
00890           /* Workaround - Extra data written in the FIFO at the end of a read transfer */
00891           status = HAL_QSPI_Abort(hqspi);
00892         }
00893       }
00894
00895       /* Update QSPI state */
00896       hqspi->State = HAL_QSPI_STATE_READY;
00897     }
00898     else
00899     {
00900       status = HAL_ERROR;
00901     }
00902   }
00903   else
00904   {
00905     status = HAL_BUSY;
00906   }
00907
00908   /* Process unlocked */
00909   __HAL_UNLOCK(hqspi);
00910
00911   return status;
00912 }
00913
00914 /**
00915   * @brief  Send an amount of data in interrupt mode
00916   * @param  hqspi: QSPI handle
00917   * @param  pData: pointer to data buffer
00918   * @note   This function is used only in Indirect Write Mode
00919   * @retval HAL status
00920   */
00921 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
00922 {
00923   HAL_StatusTypeDef status = HAL_OK;
00924
00925   /* Process locked */
00926   __HAL_LOCK(hqspi);
00927
00928   if(hqspi->State == HAL_QSPI_STATE_READY)
00929   {
00930     if(pData != NULL )
00931     {
00932       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00933
00934       /* Update state */
00935       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00936
00937       /* Configure counters and size of the handle */
00938       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
00939       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
00940       hqspi->pTxBuffPtr = pData;
00941
00942       /* Configure QSPI: CCR register with functional as indirect write */
00943       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00944
00945       /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
00946       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
00947
00948     }
00949     else
00950     {
00951       status = HAL_ERROR;
00952     }
00953   }
00954   else
00955   {
00956     status = HAL_BUSY;
00957   }
00958
00959   /* Process unlocked */
00960   __HAL_UNLOCK(hqspi);
00961
00962   return status;
00963 }
00964
00965 /**
00966   * @brief  Receive an amount of data in no-blocking mode with Interrupt
00967   * @param  hqspi: QSPI handle
00968   * @param  pData: pointer to data buffer
00969   * @note   This function is used only in Indirect Read Mode
00970   * @retval HAL status
00971   */
00972 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
00973 {
00974   HAL_StatusTypeDef status = HAL_OK;
00975   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
00976
00977   /* Process locked */
00978   __HAL_LOCK(hqspi);
00979
00980   if(hqspi->State == HAL_QSPI_STATE_READY)
00981   {
00982     if(pData != NULL )
00983     {
00984       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00985
00986       /* Update state */
00987       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
00988
00989       /* Configure counters and size of the handle */
00990       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
00991       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
00992       hqspi->pRxBuffPtr = pData;
00993
00994       /* Configure QSPI: CCR register with functional as indirect read */
00995       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
00996
00997       /* Start the transfer by re-writing the address in AR register */
00998       WRITE_REG(hqspi->Instance->AR, addr_reg);
00999
01000       /* Enable the QSPI transfer error, FIFO threshold and transfert complete Interrupts */
01001       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01002     }
01003     else
01004     {
01005       status = HAL_ERROR;
01006     }
01007   }
01008   else
01009   {
01010     status = HAL_BUSY;
01011   }
01012
01013   /* Process unlocked */
01014   __HAL_UNLOCK(hqspi);
01015
01016   return status;
01017 }
01018
01019 /**
01020   * @brief  Sends an amount of data in non blocking mode with DMA.
01021   * @param  hqspi: QSPI handle
01022   * @param  pData: pointer to data buffer
01023   * @note   This function is used only in Indirect Write Mode
01024   * @retval HAL status
01025   */
01026 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01027 {
01028   HAL_StatusTypeDef status = HAL_OK;
01029   uint32_t *tmp;
01030
01031   /* Process locked */
01032   __HAL_LOCK(hqspi);
01033
01034   if(hqspi->State == HAL_QSPI_STATE_READY)
01035   {
01036     if(pData != NULL )
01037     {
01038       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01039
01040       /* Update state */
01041       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01042
01043       /* Configure counters and size of the handle */
01044       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01045       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01046       hqspi->pTxBuffPtr = pData;
01047
01048       /* Configure QSPI: CCR register with functional mode as indirect write */
01049       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01050
01051       /* Set the QSPI DMA transfer complete callback */
01052       hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
01053
01054       /* Set the QSPI DMA Half transfer complete callback */
01055       hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
01056
01057       /* Set the DMA error callback */
01058       hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01059
01060       /* Configure the direction of the DMA */
01061       hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
01062       MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
01063
01064       /* Enable the QSPI transmit DMA Channel */
01065       tmp = (uint32_t*)&pData;
01066       HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
01067
01068       /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01069       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01070     }
01071     else
01072     {
01073       status = HAL_OK;
01074     }
01075   }
01076   else
01077   {
01078     status = HAL_BUSY;
01079   }
01080
01081   /* Process unlocked */
01082   __HAL_UNLOCK(hqspi);
01083
01084   return status;
01085 }
01086
01087 /**
01088   * @brief  Receives an amount of data in non blocking mode with DMA.
01089   * @param  hqspi: QSPI handle
01090   * @param  pData: pointer to data buffer.
01091   * @note   This function is used only in Indirect Read Mode
01092   * @retval HAL status
01093   */
01094 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01095 {
01096   HAL_StatusTypeDef status = HAL_OK;
01097   uint32_t *tmp;
01098   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01099
01100   /* Process locked */
01101   __HAL_LOCK(hqspi);
01102
01103   if(hqspi->State == HAL_QSPI_STATE_READY)
01104   {
01105     if(pData != NULL )
01106     {
01107       hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01108
01109       /* Update state */
01110       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01111
01112       /* Configure counters and size of the handle */
01113       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01114       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01115       hqspi->pRxBuffPtr = pData;
01116
01117       /* Set the QSPI DMA transfer complete callback */
01118       hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
01119
01120       /* Set the QSPI DMA Half transfer complete callback */
01121       hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
01122
01123       /* Set the DMA error callback */
01124       hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01125
01126       /* Configure the direction of the DMA */
01127       hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
01128       MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
01129
01130       /* Enable the DMA Channel */
01131       tmp = (uint32_t*)&pData;
01132       HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
01133
01134       /* Configure QSPI: CCR register with functional as indirect read */
01135       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01136
01137       /* Start the transfer by re-writing the address in AR register */
01138       WRITE_REG(hqspi->Instance->AR, addr_reg);
01139
01140       /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01141       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01142     }
01143     else
01144     {
01145       status = HAL_ERROR;
01146     }
01147   }
01148   else
01149   {
01150     status = HAL_BUSY;
01151   }
01152
01153   /* Process unlocked */
01154   __HAL_UNLOCK(hqspi);
01155
01156   return status;
01157 }
01158
01159 /**
01160   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
01161   * @param  hqspi: QSPI handle
01162   * @param  cmd: structure that contains the command configuration information.
01163   * @param  cfg: structure that contains the polling configuration information.
01164   * @param  Timeout : Time out duration
01165   * @note   This function is used only in Automatic Polling Mode
01166   * @retval HAL status
01167   */
01168 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01169 {
01170   HAL_StatusTypeDef status = HAL_ERROR;
01171
01172   /* Check the parameters */
01173   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01174   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01175   {
01176   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01177   }
01178
01179   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01180   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01181   {
01182     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01183   }
01184
01185   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01186   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01187   {
01188     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01189   }
01190
01191   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01192   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01193
01194   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01195   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01196   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01197
01198   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01199   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01200   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01201
01202   /* Process locked */
01203   __HAL_LOCK(hqspi);
01204
01205   if(hqspi->State == HAL_QSPI_STATE_READY)
01206   {
01207
01208   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01209
01210   /* Update state */
01211   hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01212
01213   /* Wait till BUSY flag reset */
01214   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
01215
01216   if (status == HAL_OK)
01217   {
01218     /* Configure QSPI: PSMAR register with the status match value */
01219     WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01220
01221     /* Configure QSPI: PSMKR register with the status mask value */
01222     WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01223
01224     /* Configure QSPI: PIR register with the interval value */
01225     WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01226
01227     /* Configure QSPI: CR register with Match mode and Automatic stop enabled
01228        (otherwise there will be an infinite loop in blocking mode) */
01229     MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01230                (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
01231
01232     /* Call the configuration function */
01233     cmd->NbData = cfg->StatusBytesSize;
01234     QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01235
01236     /* Wait until SM flag is set to go back in idle state */
01237     if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
01238     {
01239       status = HAL_TIMEOUT;
01240     }
01241     else
01242     {
01243       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
01244
01245       /* Update state */
01246       hqspi->State = HAL_QSPI_STATE_READY;
01247     }
01248   }
01249   }
01250   else
01251   {
01252     status = HAL_BUSY;
01253   }
01254   /* Process unlocked */
01255   __HAL_UNLOCK(hqspi);
01256
01257   /* Return function status */
01258   return status;
01259 }
01260
01261 /**
01262   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
01263   * @param  hqspi: QSPI handle
01264   * @param  cmd: structure that contains the command configuration information.
01265   * @param  cfg: structure that contains the polling configuration information.
01266   * @note   This function is used only in Automatic Polling Mode
01267   * @retval HAL status
01268   */
01269 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
01270 {
01271   HAL_StatusTypeDef status = HAL_ERROR;
01272
01273   /* Check the parameters */
01274   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01275   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01276   {
01277     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01278   }
01279
01280   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01281   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01282   {
01283     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01284   }
01285
01286   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01287   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01288   {
01289     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01290   }
01291
01292   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01293   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01294
01295   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01296   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01297   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01298
01299   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01300   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01301   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01302   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
01303
01304   /* Process locked */
01305   __HAL_LOCK(hqspi);
01306
01307 if(hqspi->State == HAL_QSPI_STATE_READY)
01308   {
01309     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01310
01311     /* Update state */
01312     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01313
01314     /* Wait till BUSY flag reset */
01315     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
01316
01317     if (status == HAL_OK)
01318     {
01319       /* Configure QSPI: PSMAR register with the status match value */
01320       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01321
01322       /* Configure QSPI: PSMKR register with the status mask value */
01323       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01324
01325       /* Configure QSPI: PIR register with the interval value */
01326       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01327
01328       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
01329       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01330                (cfg->MatchMode | cfg->AutomaticStop));
01331
01332       /* Clear interrupt */
01333       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
01334
01335       /* Enable the QSPI Transfer Error and status match Interrupt */
01336       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
01337
01338       /* Call the configuration function */
01339       cmd->NbData = cfg->StatusBytesSize;
01340       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01341     }
01342   }
01343   else
01344   {
01345     status = HAL_BUSY;
01346   }
01347
01348   /* Process unlocked */
01349   __HAL_UNLOCK(hqspi);
01350
01351   /* Return function status */
01352   return status;
01353 }
01354
01355 /**
01356   * @brief  Configure the Memory Mapped mode.
01357   * @param  hqspi: QSPI handle
01358   * @param  cmd: structure that contains the command configuration information.
01359   * @param  cfg: structure that contains the memory mapped configuration information.
01360   * @note   This function is used only in Memory mapped Mode
01361   * @retval HAL status
01362   */
01363 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
01364 {
01365   HAL_StatusTypeDef status = HAL_ERROR;
01366
01367   /* Check the parameters */
01368   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01369   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01370   {
01371   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01372   }
01373
01374   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01375   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01376   {
01377     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01378   }
01379
01380   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01381   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01382   {
01383     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01384   }
01385
01386   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01387   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01388
01389   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01390   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01391   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01392
01393   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01394
01395   /* Process locked */
01396   __HAL_LOCK(hqspi);
01397
01398   if(hqspi->State == HAL_QSPI_STATE_READY)
01399   {
01400     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01401
01402     /* Update state */
01403     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
01404
01405     /* Wait till BUSY flag reset */
01406     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
01407
01408   if (status == HAL_OK)
01409   {
01410     /* Configure QSPI: CR register with time out counter enable */
01411     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
01412
01413     if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
01414     {
01415       assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01416
01417       /* Configure QSPI: LPTR register with the low-power time out value */
01418       WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
01419
01420       /* Enable the QSPI TimeOut Interrupt */
01421       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
01422     }
01423
01424     /* Call the configuration function */
01425     QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
01426
01427     }
01428   }
01429   else
01430   {
01431     status = HAL_BUSY;
01432
01433   }
01434
01435   /* Process unlocked */
01436   __HAL_UNLOCK(hqspi);
01437
01438   /* Return function status */
01439   return status;
01440 }
01441
01442 /**
01443   * @brief  Transfer Error callbacks
01444   * @param  hqspi: QSPI handle
01445   * @retval None
01446   */
01447 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
01448 {
01449   /* Prevent unused argument(s) compilation warning */
01450   UNUSED(hqspi);
01451   /* NOTE : This function Should not be modified, when the callback is needed,
01452             the HAL_QSPI_ErrorCallback could be implemented in the user file
01453    */
01454 }
01455
01456 /**
01457   * @brief  Command completed callbacks.
01458   * @param  hqspi: QSPI handle
01459   * @retval None
01460   */
01461 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
01462 {
01463   /* Prevent unused argument(s) compilation warning */
01464   UNUSED(hqspi);
01465   /* NOTE: This function Should not be modified, when the callback is needed,
01466            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
01467    */
01468 }
01469
01470 /**
01471   * @brief  Rx Transfer completed callbacks.
01472   * @param  hqspi: QSPI handle
01473   * @retval None
01474   */
01475 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
01476 {
01477   /* Prevent unused argument(s) compilation warning */
01478   UNUSED(hqspi);
01479   /* NOTE: This function Should not be modified, when the callback is needed,
01480            the HAL_QSPI_RxCpltCallback could be implemented in the user file
01481    */
01482 }
01483
01484 /**
01485   * @brief  Tx Transfer completed callbacks.
01486   * @param  hqspi: QSPI handle
01487   * @retval None
01488   */
01489 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
01490 {
01491   /* Prevent unused argument(s) compilation warning */
01492   UNUSED(hqspi);
01493   /* NOTE: This function Should not be modified, when the callback is needed,
01494            the HAL_QSPI_TxCpltCallback could be implemented in the user file
01495    */
01496 }
01497
01498 /**
01499   * @brief  Rx Half Transfer completed callbacks.
01500   * @param  hqspi: QSPI handle
01501   * @retval None
01502   */
01503 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01504 {
01505   /* Prevent unused argument(s) compilation warning */
01506   UNUSED(hqspi);
01507   /* NOTE: This function Should not be modified, when the callback is needed,
01508            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
01509    */
01510 }
01511
01512 /**
01513   * @brief  Tx Half Transfer completed callbacks.
01514   * @param  hqspi: QSPI handle
01515   * @retval None
01516   */
01517 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01518 {
01519   /* Prevent unused argument(s) compilation warning */
01520   UNUSED(hqspi);
01521   /* NOTE: This function Should not be modified, when the callback is needed,
01522            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
01523    */
01524 }
01525
01526 /**
01527   * @brief  FIFO Threshold callbacks
01528   * @param  hqspi: QSPI handle
01529   * @retval None
01530   */
01531 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
01532 {
01533   /* Prevent unused argument(s) compilation warning */
01534   UNUSED(hqspi);
01535   /* NOTE : This function Should not be modified, when the callback is needed,
01536             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
01537    */
01538 }
01539
01540 /**
01541   * @brief  Status Match callbacks
01542   * @param  hqspi: QSPI handle
01543   * @retval None
01544   */
01545 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
01546 {
01547   /* Prevent unused argument(s) compilation warning */
01548   UNUSED(hqspi);
01549   /* NOTE : This function Should not be modified, when the callback is needed,
01550             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
01551    */
01552 }
01553
01554 /**
01555   * @brief  Timeout callbacks
01556   * @param  hqspi: QSPI handle
01557   * @retval None
01558   */
01559 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
01560 {
01561   /* Prevent unused argument(s) compilation warning */
01562   UNUSED(hqspi);
01563   /* NOTE : This function Should not be modified, when the callback is needed,
01564             the HAL_QSPI_TimeOutCallback could be implemented in the user file
01565    */
01566 }
01567
01568 /**
01569   * @}
01570   */
01571
01572 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
01573   *  @brief   QSPI control and State functions
01574   *
01575 @verbatim
01576  ===============================================================================
01577                   ##### Peripheral Control and State functions #####
01578  ===============================================================================
01579     [..]
01580     This subsection provides a set of functions allowing to :
01581       (+) Check in run-time the state of the driver.
01582       (+) Check the error code set during last operation.
01583       (+) Abort any operation.
01584 .....
01585 @endverbatim
01586   * @{
01587   */
01588
01589 /**
01590   * @brief  Return the QSPI state.
01591   * @param  hqspi: QSPI handle
01592   * @retval HAL state
01593   */
01594 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
01595 {
01596   return hqspi->State;
01597 }
01598
01599 /**
01600 * @brief  Return the QSPI error code
01601 * @param  hqspi: QSPI handle
01602 * @retval QSPI Error Code
01603 */
01604 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
01605 {
01606   return hqspi->ErrorCode;
01607 }
01608
01609 /**
01610 * @brief  Abort the current transmission
01611 * @param  hqspi: QSPI handle
01612 * @retval HAL status
01613 */
01614 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
01615 {
01616   HAL_StatusTypeDef status = HAL_ERROR;
01617
01618   /* Configure QSPI: CR register with Abort request */
01619   SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
01620
01621   /* Wait until TC flag is set to go back in idle state */
01622   if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
01623   {
01624     status = HAL_TIMEOUT;
01625   }
01626   else
01627   {
01628     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01629
01630     /* Wait until BUSY flag is reset */
01631     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
01632
01633     /* Update state */
01634     hqspi->State = HAL_QSPI_STATE_READY;
01635   }
01636
01637   return status;
01638 }
01639
01640 /** @brief Set QSPI timeout
01641   * @param  hqspi: QSPI handle.
01642   * @param  Timeout: Timeout for the QSPI memory access.
01643   * @retval None
01644   */
01645 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
01646 {
01647   hqspi->Timeout = Timeout;
01648 }
01649
01650 /**
01651 * @}
01652 */
01653
01654 /* Private functions ---------------------------------------------------------*/
01655
01656 /**
01657   * @brief  DMA QSPI receive process complete callback.
01658   * @param  hdma: DMA handle
01659   * @retval None
01660   */
01661 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
01662 {
01663   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01664   hqspi->RxXferCount = 0U;
01665
01666   /* Wait for QSPI TC Flag */
01667   if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
01668   {
01669     /* Time out Occurred */
01670     HAL_QSPI_ErrorCallback(hqspi);
01671   }
01672   else
01673   {
01674     /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01675     CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01676
01677     /* Disable the DMA channel */
01678     HAL_DMA_Abort(hdma);
01679
01680     /* Clear Transfer Complete bit */
01681     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01682
01683     /* Workaround - Extra data written in the FIFO at the end of a read transfer */
01684     HAL_QSPI_Abort(hqspi);
01685
01686     /* Update state */
01687     hqspi->State = HAL_QSPI_STATE_READY;
01688
01689     HAL_QSPI_RxCpltCallback(hqspi);
01690   }
01691 }
01692
01693 /**
01694   * @brief  DMA QSPI transmit process complete callback.
01695   * @param  hdma: DMA handle
01696   * @retval None
01697   */
01698 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
01699 {
01700   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01701   hqspi->TxXferCount = 0U;
01702
01703   /* Wait for QSPI TC Flag */
01704   if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
01705   {
01706     /* Time out Occurred */
01707     HAL_QSPI_ErrorCallback(hqspi);
01708   }
01709   else
01710   {
01711     /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01712     CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01713
01714     /* Disable the DMA channel */
01715     HAL_DMA_Abort(hdma);
01716
01717     /* Clear Transfer Complete bit */
01718     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01719
01720     /* Clear Busy bit */
01721     HAL_QSPI_Abort(hqspi);
01722
01723     /* Update state */
01724     hqspi->State = HAL_QSPI_STATE_READY;
01725
01726     HAL_QSPI_TxCpltCallback(hqspi);
01727   }
01728 }
01729
01730 /**
01731   * @brief  DMA QSPI receive process half complete callback
01732   * @param  hdma : DMA handle
01733   * @retval None
01734   */
01735 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01736 {
01737   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01738
01739   HAL_QSPI_RxHalfCpltCallback(hqspi);
01740 }
01741
01742 /**
01743   * @brief  DMA QSPI transmit process half complete callback
01744   * @param  hdma : DMA handle
01745   * @retval None
01746   */
01747 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01748 {
01749   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01750
01751   HAL_QSPI_TxHalfCpltCallback(hqspi);
01752 }
01753
01754 /**
01755   * @brief  DMA QSPI communication error callback.
01756   * @param  hdma: DMA handle
01757   * @retval None
01758   */
01759 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
01760 {
01761   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01762
01763   hqspi->RxXferCount = 0U;
01764   hqspi->TxXferCount = 0U;
01765   hqspi->State       = HAL_QSPI_STATE_ERROR;
01766   hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
01767
01768   HAL_QSPI_ErrorCallback(hqspi);
01769 }
01770
01771 /**
01772   * @brief  This function wait a flag state until time out.
01773   * @param  hqspi: QSPI handle
01774   * @param  Flag: Flag checked
01775   * @param  State: Value of the flag expected
01776   * @param  Timeout: Duration of the time out
01777   * @retval HAL status
01778   */
01779 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
01780                                                         FlagStatus State, uint32_t Timeout)
01781 {
01782   uint32_t tickstart = HAL_GetTick();
01783
01784   /* Wait until flag is in expected state */
01785   while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
01786   {
01787     /* Check for the Timeout */
01788     if (Timeout != HAL_MAX_DELAY)
01789     {
01790       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01791       {
01792         hqspi->State     = HAL_QSPI_STATE_ERROR;
01793         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
01794
01795         return HAL_TIMEOUT;
01796       }
01797     }
01798   }
01799   return HAL_OK;
01800 }
01801
01802 /**
01803   * @brief  This function configures the communication registers
01804   * @param  hqspi: QSPI handle
01805   * @param  cmd: structure that contains the command configuration information
01806   * @param  FunctionalMode: functional mode to configured
01807   *           This parameter can be one of the following values:
01808   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
01809   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
01810   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
01811   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
01812   * @retval None
01813   */
01814 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
01815 {
01816   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
01817
01818   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
01819   {
01820     /* Configure QSPI: DLR register with the number of data to read or write */
01821     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
01822   }
01823
01824   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01825   {
01826     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01827     {
01828       /* Configure QSPI: ABR register with alternate bytes value */
01829       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
01830
01831       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01832       {
01833         /*---- Command with instruction, address and alternate bytes ----*/
01834         /* Configure QSPI: CCR register with all communications parameters */
01835         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01836                                          cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
01837                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
01838                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
01839
01840         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01841         {
01842           /* Configure QSPI: AR register with address value */
01843           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01844         }
01845       }
01846       else
01847       {
01848         /*---- Command with instruction and alternate bytes ----*/
01849         /* Configure QSPI: CCR register with all communications parameters */
01850         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01851                                          cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
01852                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
01853                                          cmd->Instruction | FunctionalMode));
01854       }
01855     }
01856     else
01857     {
01858       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01859       {
01860         /*---- Command with instruction and address ----*/
01861         /* Configure QSPI: CCR register with all communications parameters */
01862         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01863                                          cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
01864                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
01865                                          cmd->Instruction | FunctionalMode));
01866
01867         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01868         {
01869           /* Configure QSPI: AR register with address value */
01870           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01871         }
01872       }
01873       else
01874       {
01875         /*---- Command with only instruction ----*/
01876         /* Configure QSPI: CCR register with all communications parameters */
01877         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01878                                          cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
01879                                          cmd->AddressMode | cmd->InstructionMode | cmd->Instruction  |
01880                                          FunctionalMode));
01881       }
01882     }
01883   }
01884   else
01885   {
01886     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01887     {
01888       /* Configure QSPI: ABR register with alternate bytes value */
01889       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
01890
01891       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01892       {
01893         /*---- Command with address and alternate bytes ----*/
01894         /* Configure QSPI: CCR register with all communications parameters */
01895         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01896                                          cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
01897                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
01898                                          cmd->InstructionMode | FunctionalMode));
01899
01900         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01901         {
01902           /* Configure QSPI: AR register with address value */
01903           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01904         }
01905       }
01906       else
01907       {
01908         /*---- Command with only alternate bytes ----*/
01909         /* Configure QSPI: CCR register with all communications parameters */
01910         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01911                                          cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
01912                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
01913                                          FunctionalMode));
01914       }
01915     }
01916     else
01917     {
01918       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01919       {
01920         /*---- Command with only address ----*/
01921         /* Configure QSPI: CCR register with all communications parameters */
01922         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01923                                          cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
01924                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
01925                                          FunctionalMode));
01926
01927         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
01928         {
01929           /* Configure QSPI: AR register with address value */
01930           WRITE_REG(hqspi->Instance->AR, cmd->Address);
01931         }
01932       }
01933       else
01934       {
01935         /*---- Command with only data phase ----*/
01936         if (cmd->DataMode != QSPI_DATA_NONE)
01937         {
01938           /* Configure QSPI: CCR register with all communications parameters */
01939           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
01940                                            cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
01941                                            cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
01942         }
01943       }
01944     }
01945   }
01946 }
01947
01948 /**
01949   * @}
01950   */
01951
01952 /**
01953   * @}
01954   */
01955 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
01956
01957 #endif /* HAL_QSPI_MODULE_ENABLED */
01958 /**
01959   * @}
01960   */
01961
01962 /**
01963   * @}
01964   */
01965
01966 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_qspi.h Source File

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stm32f4xx_hal_qspi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of QSPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_QSPI_H
00040 #define __STM32F4xx_HAL_QSPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f4xx_hal_def.h"
00049
00050 /** @addtogroup STM32F4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup QSPI
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  QSPI Init structure definition
00065   */
00066
00067 typedef struct
00068 {
00069   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00070                                   This parameter can be a number between 0 and 255 */
00071
00072   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00073                                   This parameter can be a value between 1 and 32 */
00074
00075   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
00076                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00077                                   This parameter can be a value of @ref QSPI_SampleShifting */
00078
00079   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
00080                                   required to address the flash memory. The flash capacity can be up to 4GB
00081                                   (addressed using 32 bits) in indirect mode, but the addressable space in
00082                                   memory-mapped mode is limited to 256MB
00083                                   This parameter can be a number between 0 and 31 */
00084
00085   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
00086                                   of clock cycles which the chip select must remain high between commands.
00087                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */
00088
00089   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00090                                   This parameter can be a value of @ref QSPI_ClockMode */
00091
00092   uint32_t FlashID;            /* Specifies the Flash which will be used,
00093                                   This parameter can be a value of @ref QSPI_Flash_Select */
00094
00095   uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
00096                                   This parameter can be a value of @ref QSPI_DualFlash_Mode */
00097 }QSPI_InitTypeDef;
00098
00099 /**
00100   * @brief HAL QSPI State structures definition
00101   */
00102 typedef enum
00103 {
00104   HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
00105   HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
00106   HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
00107   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
00108   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
00109   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
00110   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
00111   HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
00112 }HAL_QSPI_StateTypeDef;
00113
00114 /**
00115   * @brief  QSPI Handle Structure definition
00116   */
00117 typedef struct
00118 {
00119   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00120   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00121   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00122   __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */
00123   __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00124   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00125   __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */
00126   __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00127   DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
00128   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00129   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00130   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00131   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
00132 }QSPI_HandleTypeDef;
00133
00134 /**
00135   * @brief  QSPI Command structure definition
00136   */
00137 typedef struct
00138 {
00139   uint32_t Instruction;        /* Specifies the Instruction to be sent
00140                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00141   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00142                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
00143   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00144                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
00145   uint32_t AddressSize;        /* Specifies the Address Size
00146                                   This parameter can be a value of @ref QSPI_AddressSize */
00147   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00148                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00149   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00150                                   This parameter can be a number between 0 and 31 */
00151   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00152                                   This parameter can be a value of @ref QSPI_InstructionMode */
00153   uint32_t AddressMode;        /* Specifies the Address Mode
00154                                   This parameter can be a value of @ref QSPI_AddressMode */
00155   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00156                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00157   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00158                                   This parameter can be a value of @ref QSPI_DataMode */
00159   uint32_t NbData;             /* Specifies the number of data to transfer.
00160                                   This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
00161                                   until end of memory)*/
00162   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00163                                   This parameter can be a value of @ref QSPI_DdrMode */
00164   uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of
00165                                   system clock in DDR mode.
00166                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
00167   uint32_t SIOOMode;          /* Specifies the send instruction only once mode
00168                                   This parameter can be a value of @ref QSPI_SIOOMode */
00169 }QSPI_CommandTypeDef;
00170
00171 /**
00172   * @brief  QSPI Auto Polling mode configuration structure definition
00173   */
00174 typedef struct
00175 {
00176   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00177                                   This parameter can be any value between 0 and 0xFFFFFFFFU */
00178   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00179                                   This parameter can be any value between 0 and 0xFFFFFFFFU */
00180   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00181                                   This parameter can be any value between 0 and 0xFFFFU */
00182   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00183                                   This parameter can be any value between 1 and 4 */
00184   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00185                                   This parameter can be a value of @ref QSPI_MatchMode */
00186   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00187                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00188 }QSPI_AutoPollingTypeDef;
00189
00190 /**
00191   * @brief  QSPI Memory Mapped mode configuration structure definition
00192   */
00193 typedef struct
00194 {
00195   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00196                                   This parameter can be any value between 0 and 0xFFFFU */
00197   uint32_t TimeOutActivation;  /* Specifies if the time out counter is enabled to release the chip select.
00198                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00199 }QSPI_MemoryMappedTypeDef;
00200 /**
00201   * @}
00202   */
00203
00204 /* Exported constants --------------------------------------------------------*/
00205 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00206   * @{
00207   */
00208 /** @defgroup QSPI_ErrorCode QSPI Error Code
00209   * @{
00210   */
00211 #define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error           */
00212 #define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error      */
00213 #define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002U) /*!< Transfer error     */
00214 #define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004U) /*!< DMA transfer error */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00220   * @{
00221   */
00222 #define QSPI_SAMPLE_SHIFTING_NONE           ((uint32_t)0x00000000U)        /*!<No clock cycle shift to sample data*/
00223 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE      ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
00229   * @{
00230   */
00231 #define QSPI_CS_HIGH_TIME_1_CYCLE           ((uint32_t)0x00000000U)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
00232 #define QSPI_CS_HIGH_TIME_2_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00233 #define QSPI_CS_HIGH_TIME_3_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00234 #define QSPI_CS_HIGH_TIME_4_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00235 #define QSPI_CS_HIGH_TIME_5_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00236 #define QSPI_CS_HIGH_TIME_6_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00237 #define QSPI_CS_HIGH_TIME_7_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00238 #define QSPI_CS_HIGH_TIME_8_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00244   * @{
00245   */
00246 #define QSPI_CLOCK_MODE_0                   ((uint32_t)0x00000000U)         /*!<Clk stays low while nCS is released*/
00247 #define QSPI_CLOCK_MODE_3                   ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup QSPI_Flash_Select QSPI Flash Select
00253   * @{
00254   */
00255 #define QSPI_FLASH_ID_1           ((uint32_t)0x00000000U)
00256 #define QSPI_FLASH_ID_2           ((uint32_t)QUADSPI_CR_FSEL)
00257 /**
00258   * @}
00259   */
00260
00261   /** @defgroup QSPI_DualFlash_Mode  QSPI Dual Flash Mode
00262   * @{
00263   */
00264 #define QSPI_DUALFLASH_ENABLE            ((uint32_t)QUADSPI_CR_DFM)
00265 #define QSPI_DUALFLASH_DISABLE           ((uint32_t)0x00000000U)
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup QSPI_AddressSize QSPI Address Size
00271   * @{
00272   */
00273 #define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000U)           /*!<8-bit address*/
00274 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00275 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00276 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00282   * @{
00283   */
00284 #define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000U)           /*!<8-bit alternate bytes*/
00285 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00286 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00287 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00293 * @{
00294 */
00295 #define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000U)          /*!<No instruction*/
00296 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00297 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00298 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup QSPI_AddressMode QSPI Address Mode
00304 * @{
00305 */
00306 #define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000U)           /*!<No address*/
00307 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00308 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00309 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup QSPI_AlternateBytesMode  QSPI Alternate Bytes Mode
00315 * @{
00316 */
00317 #define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000U)           /*!<No alternate bytes*/
00318 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00319 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00320 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup QSPI_DataMode QSPI Data Mode
00326   * @{
00327   */
00328 #define QSPI_DATA_NONE                 ((uint32_t)0x00000000U)           /*!<No data*/
00329 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00330 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00331 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup QSPI_DdrMode QSPI Ddr Mode
00337   * @{
00338   */
00339 #define QSPI_DDR_MODE_DISABLE              ((uint32_t)0x00000000U)       /*!<Double data rate mode disabled*/
00340 #define QSPI_DDR_MODE_ENABLE               ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
00346   * @{
00347   */
00348 #define QSPI_DDR_HHC_ANALOG_DELAY           ((uint32_t)0x00000000U)       /*!<Delay the data output using analog delay in DDR mode*/
00349 #define QSPI_DDR_HHC_HALF_CLK_DELAY         ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode
00355   * @{
00356   */
00357 #define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000U)       /*!<Send instruction on every transaction*/
00358 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup QSPI_MatchMode QSPI Match Mode
00364   * @{
00365   */
00366 #define QSPI_MATCH_MODE_AND                 ((uint32_t)0x00000000U)     /*!<AND match mode between unmasked bits*/
00367 #define QSPI_MATCH_MODE_OR                  ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00368 /**
00369   * @}
00370   */
00371
00372 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00373   * @{
00374   */
00375 #define QSPI_AUTOMATIC_STOP_DISABLE        ((uint32_t)0x00000000U)      /*!<AutoPolling stops only with abort or QSPI disabling*/
00376 #define QSPI_AUTOMATIC_STOP_ENABLE         ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
00382   * @{
00383   */
00384 #define QSPI_TIMEOUT_COUNTER_DISABLE       ((uint32_t)0x00000000U)      /*!<Timeout counter disabled, nCS remains active*/
00385 #define QSPI_TIMEOUT_COUNTER_ENABLE        ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00386 /**
00387   * @}
00388   */
00389
00390 /** @defgroup QSPI_Flags  QSPI Flags
00391   * @{
00392   */
00393 #define QSPI_FLAG_BUSY                      QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00394 #define QSPI_FLAG_TO                        QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00395 #define QSPI_FLAG_SM                        QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00396 #define QSPI_FLAG_FT                        QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00397 #define QSPI_FLAG_TC                        QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00398 #define QSPI_FLAG_TE                        QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup QSPI_Interrupts  QSPI Interrupts
00404   * @{
00405   */
00406 #define QSPI_IT_TO                          QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00407 #define QSPI_IT_SM                          QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00408 #define QSPI_IT_FT                          QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00409 #define QSPI_IT_TC                          QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00410 #define QSPI_IT_TE                          QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00416   * @{
00417   */
00418 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U)/* 5 s */
00419 /**
00420   * @}
00421   */
00422
00423 /**
00424   * @}
00425   */
00426
00427 /* Exported macros -----------------------------------------------------------*/
00428 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00429   * @{
00430   */
00431
00432 /** @brief Reset QSPI handle state
00433   * @param  __HANDLE__: QSPI handle.
00434   * @retval None
00435   */
00436 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00437
00438 /** @brief  Enable QSPI
00439   * @param  __HANDLE__: specifies the QSPI Handle.
00440   * @retval None
00441   */
00442 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00443
00444 /** @brief  Disable QSPI
00445   * @param  __HANDLE__: specifies the QSPI Handle.
00446   * @retval None
00447   */
00448 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00449
00450 /** @brief  Enables the specified QSPI interrupt.
00451   * @param  __HANDLE__: specifies the QSPI Handle.
00452   * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
00453   *          This parameter can be one of the following values:
00454   *            @arg QSPI_IT_TO: QSPI Time out interrupt
00455   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00456   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00457   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00458   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00459   * @retval None
00460   */
00461 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00462
00463
00464 /** @brief  Disables the specified QSPI interrupt.
00465   * @param  __HANDLE__: specifies the QSPI Handle.
00466   * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
00467   *          This parameter can be one of the following values:
00468   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00469   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00470   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00471   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00472   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00473   * @retval None
00474   */
00475 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00476
00477 /** @brief  Checks whether the specified QSPI interrupt source is enabled.
00478   * @param  __HANDLE__: specifies the QSPI Handle.
00479   * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
00480   *          This parameter can be one of the following values:
00481   *            @arg QSPI_IT_TO: QSPI Time out interrupt
00482   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00483   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00484   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00485   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00486   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00487   */
00488 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00489
00490 /**
00491   * @brief  Get the selected QSPI's flag status.
00492   * @param  __HANDLE__: specifies the QSPI Handle.
00493   * @param  __FLAG__: specifies the QSPI flag to check.
00494   *          This parameter can be one of the following values:
00495   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00496   *            @arg QSPI_FLAG_TO:   QSPI Time out flag
00497   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00498   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00499   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00500   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00501   * @retval None
00502   */
00503 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
00504
00505 /** @brief  Clears the specified QSPI's flag status.
00506   * @param  __HANDLE__: specifies the QSPI Handle.
00507   * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
00508   *          This parameter can be one of the following values:
00509   *            @arg QSPI_FLAG_TO: QSPI Time out flag
00510   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00511   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00512   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00513   * @retval None
00514   */
00515 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00516 /**
00517   * @}
00518   */
00519
00520 /* Exported functions --------------------------------------------------------*/
00521 /** @addtogroup QSPI_Exported_Functions
00522   * @{
00523   */
00524
00525 /** @addtogroup QSPI_Exported_Functions_Group1
00526   * @{
00527   */
00528 /* Initialization/de-initialization functions  ********************************/
00529 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00530 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00531 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00532 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00533 /**
00534   * @}
00535   */
00536
00537 /** @addtogroup QSPI_Exported_Functions_Group2
00538   * @{
00539   */
00540 /* IO operation functions *****************************************************/
00541 /* QSPI IRQ handler method */
00542 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00543
00544 /* QSPI indirect mode */
00545 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00546 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00547 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00548 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00549 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00550 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00551 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00552 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00553
00554 /* QSPI status flag polling mode */
00555 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00556 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00557
00558 /* QSPI memory-mapped mode */
00559 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00560 /**
00561   * @}
00562   */
00563
00564 /** @addtogroup QSPI_Exported_Functions_Group3
00565   * @{
00566   */
00567 /* Callback functions in non-blocking modes ***********************************/
00568 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00569 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00570
00571 /* QSPI indirect mode */
00572 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00573 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00574 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00575 void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00576 void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00577
00578 /* QSPI status flag polling mode */
00579 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00580
00581 /* QSPI memory-mapped mode */
00582 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00583 /**
00584   * @}
00585   */
00586
00587 /** @addtogroup QSPI_Exported_Functions_Group4
00588   * @{
00589   */
00590 /* Peripheral Control and State functions  ************************************/
00591 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
00592 uint32_t              HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
00593 HAL_StatusTypeDef     HAL_QSPI_Abort   (QSPI_HandleTypeDef *hqspi);
00594 void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00595 /**
00596   * @}
00597   */
00598
00599 /**
00600   * @}
00601   */
00602
00603 /* Private types -------------------------------------------------------------*/
00604 /* Private variables ---------------------------------------------------------*/
00605 /* Private constants ---------------------------------------------------------*/
00606 /** @defgroup QSPI_Private_Constants QSPI Private Constants
00607   * @{
00608   */
00609
00610 /**
00611   * @}
00612   */
00613
00614 /* Private macros ------------------------------------------------------------*/
00615 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00616   * @{
00617   */
00618 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
00619   * @{
00620   */
00621 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER)  ((PRESCALER) <= 0xFFU)
00622 /**
00623   * @}
00624   */
00625
00626 /** @defgroup QSPI_FifoThreshold  QSPI Fifo Threshold
00627   * @{
00628   */
00629 #define IS_QSPI_FIFO_THRESHOLD(THR)         (((THR) > 0U) && ((THR) <= 32U))
00630 /**
00631   * @}
00632   */
00633
00634 #define IS_QSPI_SSHIFT(SSHIFT)              (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00635                                              ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00636
00637 /** @defgroup QSPI_FlashSize QSPI Flash Size
00638   * @{
00639   */
00640 #define IS_QSPI_FLASH_SIZE(FSIZE)           (((FSIZE) <= 31U))
00641 /**
00642   * @}
00643   */
00644
00645 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)       (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00646                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00647                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00648                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00649                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00650                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00651                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00652                                              ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00653
00654 #define IS_QSPI_CLOCK_MODE(CLKMODE)         (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00655                                              ((CLKMODE) == QSPI_CLOCK_MODE_3))
00656
00657 #define IS_QSPI_FLASH_ID(FLA)    (((FLA) == QSPI_FLASH_ID_1) || \
00658                                   ((FLA) == QSPI_FLASH_ID_2))
00659
00660 #define IS_QSPI_DUAL_FLASH_MODE(MODE)    (((MODE) == QSPI_DUALFLASH_ENABLE) || \
00661                                           ((MODE) == QSPI_DUALFLASH_DISABLE))
00662
00663
00664 /** @defgroup QSPI_Instruction QSPI Instruction
00665   * @{
00666   */
00667 #define IS_QSPI_INSTRUCTION(INSTRUCTION)    ((INSTRUCTION) <= 0xFFU)
00668 /**
00669   * @}
00670   */
00671
00672 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)     (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00673                                              ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00674                                              ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00675                                              ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00676
00677 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)  (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00678                                              ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00679                                              ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00680                                              ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00681
00682
00683 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
00684   * @{
00685   */
00686 #define IS_QSPI_DUMMY_CYCLES(DCY)           ((DCY) <= 31U)
00687 /**
00688   * @}
00689   */
00690
00691 #define IS_QSPI_INSTRUCTION_MODE(MODE)      (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00692                                              ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00693                                              ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00694                                              ((MODE) == QSPI_INSTRUCTION_4_LINES))
00695
00696 #define IS_QSPI_ADDRESS_MODE(MODE)          (((MODE) == QSPI_ADDRESS_NONE)    || \
00697                                              ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00698                                              ((MODE) == QSPI_ADDRESS_2_LINES) || \
00699                                              ((MODE) == QSPI_ADDRESS_4_LINES))
00700
00701 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE)  (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00702                                              ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00703                                              ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00704                                              ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00705
00706 #define IS_QSPI_DATA_MODE(MODE)             (((MODE) == QSPI_DATA_NONE)    || \
00707                                              ((MODE) == QSPI_DATA_1_LINE)  || \
00708                                              ((MODE) == QSPI_DATA_2_LINES) || \
00709                                              ((MODE) == QSPI_DATA_4_LINES))
00710
00711 #define IS_QSPI_DDR_MODE(DDR_MODE)          (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00712                                              ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00713
00714 #define IS_QSPI_DDR_HHC(DDR_HHC)            (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
00715                                              ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
00716
00717 #define IS_QSPI_SIOO_MODE(SIOO_MODE)      (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00718                                              ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00719
00720 /** @defgroup QSPI_Interval QSPI Interval
00721   * @{
00722   */
00723 #define IS_QSPI_INTERVAL(INTERVAL)        ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
00724 /**
00725   * @}
00726   */
00727
00728 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
00729   * @{
00730   */
00731 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)   (((SIZE) >= 1U) && ((SIZE) <= 4U))
00732 /**
00733   * @}
00734   */
00735 #define IS_QSPI_MATCH_MODE(MODE)            (((MODE) == QSPI_MATCH_MODE_AND) || \
00736                                              ((MODE) == QSPI_MATCH_MODE_OR))
00737
00738 #define IS_QSPI_AUTOMATIC_STOP(APMS)        (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00739                                              ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
00740
00741 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)    (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00742                                              ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
00743
00744 /** @defgroup QSPI_TimeOutPeriod  QSPI TimeOut Period
00745   * @{
00746   */
00747 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)      ((PERIOD) <= 0xFFFFU)
00748 /**
00749   * @}
00750   */
00751
00752 #define IS_QSPI_GET_FLAG(FLAG)              (((FLAG) == QSPI_FLAG_BUSY) || \
00753                                              ((FLAG) == QSPI_FLAG_TO)   || \
00754                                              ((FLAG) == QSPI_FLAG_SM)   || \
00755                                              ((FLAG) == QSPI_FLAG_FT)   || \
00756                                              ((FLAG) == QSPI_FLAG_TC)   || \
00757                                              ((FLAG) == QSPI_FLAG_TE))
00758
00759 #define IS_QSPI_IT(IT)                      ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
00760 /**
00761   * @}
00762   */
00763
00764 /* Private functions ---------------------------------------------------------*/
00765 /** @defgroup QSPI_Private_Functions QSPI Private Functions
00766   * @{
00767   */
00768
00769 /**
00770   * @}
00771   */
00772
00773 /**
00774   * @}
00775   */
00776
00777 /**
00778   * @}
00779   */
00780 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00781
00782 #ifdef __cplusplus
00783 }
00784 #endif
00785
00786 #endif /* __STM32F4xx_HAL_QSPI_H */
00787
00788 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc.c Source File

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stm32f4xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### RCC specific features #####
00016   ==============================================================================
00017     [..]
00018       After reset the device is running from Internal High Speed oscillator
00019       (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
00020       and I-Cache are disabled, and all peripherals are off except internal
00021       SRAM, Flash and JTAG.
00022       (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
00023           all peripherals mapped on these busses are running at HSI speed.
00024       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00025       (+) All GPIOs are in input floating state, except the JTAG pins which
00026           are assigned to be used for debug purpose.
00027
00028     [..]
00029       Once the device started from reset, the user application has to:
00030       (+) Configure the clock source to be used to drive the System clock
00031           (if the application needs higher frequency/performance)
00032       (+) Configure the System clock frequency and Flash settings
00033       (+) Configure the AHB and APB busses prescalers
00034       (+) Enable the clock for the peripheral(s) to be used
00035       (+) Configure the clock source(s) for peripherals which clocks are not
00036           derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
00037
00038                       ##### RCC Limitations #####
00039   ==============================================================================
00040     [..]
00041       A delay between an RCC peripheral clock enable and the effective peripheral
00042       enabling should be taken into account in order to manage the peripheral read/write
00043       from/to registers.
00044       (+) This delay depends on the peripheral mapping.
00045       (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
00046           after the clock enable bit is set on the hardware register
00047       (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
00048           after the clock enable bit is set on the hardware register
00049
00050     [..]
00051       Implemented Workaround:
00052       (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
00053           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
00054
00055   @endverbatim
00056   ******************************************************************************
00057   * @attention
00058   *
00059   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00060   *
00061   * Redistribution and use in source and binary forms, with or without modification,
00062   * are permitted provided that the following conditions are met:
00063   *   1. Redistributions of source code must retain the above copyright notice,
00064   *      this list of conditions and the following disclaimer.
00065   *   2. Redistributions in binary form must reproduce the above copyright notice,
00066   *      this list of conditions and the following disclaimer in the documentation
00067   *      and/or other materials provided with the distribution.
00068   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00069   *      may be used to endorse or promote products derived from this software
00070   *      without specific prior written permission.
00071   *
00072   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00073   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00074   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00075   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00076   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00077   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00078   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00079   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00080   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00081   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00082   *
00083   ******************************************************************************
00084   */
00085
00086 /* Includes ------------------------------------------------------------------*/
00087 #include "stm32f4xx_hal.h"
00088
00089 /** @addtogroup STM32F4xx_HAL_Driver
00090   * @{
00091   */
00092
00093 /** @defgroup RCC RCC
00094   * @brief RCC HAL module driver
00095   * @{
00096   */
00097
00098 #ifdef HAL_RCC_MODULE_ENABLED
00099
00100 /* Private typedef -----------------------------------------------------------*/
00101 /* Private define ------------------------------------------------------------*/
00102 /** @addtogroup RCC_Private_Constants
00103   * @{
00104   */
00105 #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000U) /* 5 s    */
00106
00107 /* Private macro -------------------------------------------------------------*/
00108 #define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00109 #define MCO1_GPIO_PORT        GPIOA
00110 #define MCO1_PIN              GPIO_PIN_8
00111
00112 #define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
00113 #define MCO2_GPIO_PORT         GPIOC
00114 #define MCO2_PIN               GPIO_PIN_9
00115 /**
00116   * @}
00117   */
00118
00119 /* Private variables ---------------------------------------------------------*/
00120 /** @defgroup RCC_Private_Variables RCC Private Variables
00121   * @{
00122   */
00123 const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
00124 /**
00125   * @}
00126   */
00127
00128 /* Private function prototypes -----------------------------------------------*/
00129 /* Private functions ---------------------------------------------------------*/
00130
00131 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00132   *  @{
00133   */
00134
00135 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00136  *  @brief    Initialization and Configuration functions
00137  *
00138 @verbatim
00139  ===============================================================================
00140            ##### Initialization and de-initialization functions #####
00141  ===============================================================================
00142     [..]
00143       This section provides functions allowing to configure the internal/external oscillators
00144       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
00145        and APB2).
00146
00147     [..] Internal/external clock and PLL configuration
00148          (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
00149              the PLL as System clock source.
00150
00151          (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
00152              clock source.
00153
00154          (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
00155              through the PLL as System clock source. Can be used also as RTC clock source.
00156
00157          (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00158
00159          (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
00160            (++) The first output is used to generate the high speed system clock (up to 168 MHz)
00161            (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
00162                 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
00163
00164          (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
00165              and if a HSE clock failure occurs(HSE used directly or through PLL as System
00166              clock source), the System clocks automatically switched to HSI and an interrupt
00167              is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
00168              (Non-Maskable Interrupt) exception vector.
00169
00170          (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
00171              clock (through a configurable prescaler) on PA8 pin.
00172
00173          (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
00174              clock (through a configurable prescaler) on PC9 pin.
00175
00176     [..] System, AHB and APB busses clocks configuration
00177          (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00178              HSE and PLL.
00179              The AHB clock (HCLK) is derived from System clock through configurable
00180              prescaler and used to clock the CPU, memory and peripherals mapped
00181              on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00182              from AHB clock through configurable prescalers and used to clock
00183              the peripherals mapped on these busses. You can use
00184              "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00185
00186          (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
00187              frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
00188              Depending on the device voltage range, the maximum frequency should
00189              be adapted accordingly (refer to the product datasheets for more details).
00190
00191          (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
00192              the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
00193              Depending on the device voltage range, the maximum frequency should
00194              be adapted accordingly (refer to the product datasheets for more details).
00195
00196          (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
00197              PCLK2 84 MHz and PCLK1 42 MHz.
00198              Depending on the device voltage range, the maximum frequency should
00199              be adapted accordingly (refer to the product datasheets for more details).
00200
00201          (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
00202              PCLK2 100 MHz and PCLK1 50 MHz.
00203              Depending on the device voltage range, the maximum frequency should
00204              be adapted accordingly (refer to the product datasheets for more details).
00205
00206 @endverbatim
00207   * @{
00208   */
00209
00210 /**
00211   * @brief  Resets the RCC clock configuration to the default reset state.
00212   * @note   The default reset state of the clock configuration is given below:
00213   *            - HSI ON and used as system clock source
00214   *            - HSE and PLL OFF
00215   *            - AHB, APB1 and APB2 prescaler set to 1.
00216   *            - CSS, MCO1 and MCO2 OFF
00217   *            - All interrupts disabled
00218   * @note   This function doesn't modify the configuration of the
00219   *            - Peripheral clocks
00220   *            - LSI, LSE and RTC clocks
00221   * @retval None
00222   */
00223 __weak void HAL_RCC_DeInit(void)
00224 {}
00225
00226 /**
00227   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
00228   *         RCC_OscInitTypeDef.
00229   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
00230   *         contains the configuration information for the RCC Oscillators.
00231   * @note   The PLL is not disabled when used as system clock.
00232   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00233   *         supported by this API. User should request a transition to LSE Off
00234   *         first and then LSE On or LSE Bypass.
00235   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00236   *         supported by this API. User should request a transition to HSE Off
00237   *         first and then HSE On or HSE Bypass.
00238
00239   * @retval HAL status
00240   */
00241 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00242 {
00243  uint32_t tickstart = 0U;
00244
00245   /* Check the parameters */
00246   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00247   /*------------------------------- HSE Configuration ------------------------*/
00248   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00249   {
00250     /* Check the parameters */
00251     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00252     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
00253     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
00254       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
00255     {
00256       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00257       {
00258         return HAL_ERROR;
00259       }
00260     }
00261     else
00262     {
00263       /* Set the new HSE configuration ---------------------------------------*/
00264       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00265
00266       /* Check the HSE State */
00267       if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
00268       {
00269         /* Get Start Tick*/
00270         tickstart = HAL_GetTick();
00271
00272         /* Wait till HSE is ready */
00273         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00274         {
00275           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00276           {
00277             return HAL_TIMEOUT;
00278           }
00279         }
00280       }
00281       else
00282       {
00283         /* Get Start Tick*/
00284         tickstart = HAL_GetTick();
00285
00286         /* Wait till HSE is bypassed or disabled */
00287         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
00288         {
00289           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00290           {
00291             return HAL_TIMEOUT;
00292           }
00293         }
00294       }
00295     }
00296   }
00297   /*----------------------------- HSI Configuration --------------------------*/
00298   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00299   {
00300     /* Check the parameters */
00301     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00302     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00303
00304     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00305     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
00306       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
00307     {
00308       /* When HSI is used as system clock it will not disabled */
00309       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
00310       {
00311         return HAL_ERROR;
00312       }
00313       /* Otherwise, just the calibration is allowed */
00314       else
00315       {
00316         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00317         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00318       }
00319     }
00320     else
00321     {
00322       /* Check the HSI State */
00323       if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
00324       {
00325         /* Enable the Internal High Speed oscillator (HSI). */
00326         __HAL_RCC_HSI_ENABLE();
00327
00328         /* Get Start Tick*/
00329         tickstart = HAL_GetTick();
00330
00331         /* Wait till HSI is ready */
00332         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00333         {
00334           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00335           {
00336             return HAL_TIMEOUT;
00337           }
00338         }
00339
00340         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00341         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00342       }
00343       else
00344       {
00345         /* Disable the Internal High Speed oscillator (HSI). */
00346         __HAL_RCC_HSI_DISABLE();
00347
00348         /* Get Start Tick*/
00349         tickstart = HAL_GetTick();
00350
00351         /* Wait till HSI is ready */
00352         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
00353         {
00354           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00355           {
00356             return HAL_TIMEOUT;
00357           }
00358         }
00359       }
00360     }
00361   }
00362   /*------------------------------ LSI Configuration -------------------------*/
00363   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00364   {
00365     /* Check the parameters */
00366     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00367
00368     /* Check the LSI State */
00369     if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
00370     {
00371       /* Enable the Internal Low Speed oscillator (LSI). */
00372       __HAL_RCC_LSI_ENABLE();
00373
00374       /* Get Start Tick*/
00375       tickstart = HAL_GetTick();
00376
00377       /* Wait till LSI is ready */
00378       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
00379       {
00380         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00381         {
00382           return HAL_TIMEOUT;
00383         }
00384       }
00385     }
00386     else
00387     {
00388       /* Disable the Internal Low Speed oscillator (LSI). */
00389       __HAL_RCC_LSI_DISABLE();
00390
00391       /* Get Start Tick*/
00392       tickstart = HAL_GetTick();
00393
00394       /* Wait till LSI is ready */
00395       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
00396       {
00397         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00398         {
00399           return HAL_TIMEOUT;
00400         }
00401       }
00402     }
00403   }
00404   /*------------------------------ LSE Configuration -------------------------*/
00405   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00406   {
00407     /* Check the parameters */
00408     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00409
00410     /* Enable Power Clock*/
00411     __HAL_RCC_PWR_CLK_ENABLE();
00412
00413     /* Enable write access to Backup domain */
00414     PWR->CR |= PWR_CR_DBP;
00415
00416     /* Wait for Backup domain Write protection enable */
00417     tickstart = HAL_GetTick();
00418
00419     while((PWR->CR & PWR_CR_DBP) == RESET)
00420     {
00421       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
00422       {
00423         return HAL_TIMEOUT;
00424       }
00425     }
00426
00427     /* Set the new LSE configuration -----------------------------------------*/
00428     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00429     /* Check the LSE State */
00430     if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
00431     {
00432       /* Get Start Tick*/
00433       tickstart = HAL_GetTick();
00434
00435       /* Wait till LSE is ready */
00436       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00437       {
00438         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00439         {
00440           return HAL_TIMEOUT;
00441         }
00442       }
00443     }
00444     else
00445     {
00446       /* Get Start Tick*/
00447       tickstart = HAL_GetTick();
00448
00449       /* Wait till LSE is ready */
00450       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
00451       {
00452         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00453         {
00454           return HAL_TIMEOUT;
00455         }
00456       }
00457     }
00458   }
00459   /*-------------------------------- PLL Configuration -----------------------*/
00460   /* Check the parameters */
00461   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00462   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
00463   {
00464     /* Check if the PLL is used as system clock or not */
00465     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
00466     {
00467       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
00468       {
00469         /* Check the parameters */
00470         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00471         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00472         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00473         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00474         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00475
00476         /* Disable the main PLL. */
00477         __HAL_RCC_PLL_DISABLE();
00478
00479         /* Get Start Tick*/
00480         tickstart = HAL_GetTick();
00481
00482         /* Wait till PLL is ready */
00483         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00484         {
00485           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00486           {
00487             return HAL_TIMEOUT;
00488           }
00489         }
00490
00491         /* Configure the main PLL clock source, multiplication and division factors. */
00492         WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
00493                                  RCC_OscInitStruct->PLL.PLLM                                                 | \
00494                                  (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN))             | \
00495                                  (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
00496                                  (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
00497         /* Enable the main PLL. */
00498         __HAL_RCC_PLL_ENABLE();
00499
00500         /* Get Start Tick*/
00501         tickstart = HAL_GetTick();
00502
00503         /* Wait till PLL is ready */
00504         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00505         {
00506           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00507           {
00508             return HAL_TIMEOUT;
00509           }
00510         }
00511       }
00512       else
00513       {
00514         /* Disable the main PLL. */
00515         __HAL_RCC_PLL_DISABLE();
00516
00517         /* Get Start Tick*/
00518         tickstart = HAL_GetTick();
00519
00520         /* Wait till PLL is ready */
00521         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00522         {
00523           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00524           {
00525             return HAL_TIMEOUT;
00526           }
00527         }
00528       }
00529     }
00530     else
00531     {
00532       return HAL_ERROR;
00533     }
00534   }
00535   return HAL_OK;
00536 }
00537
00538 /**
00539   * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
00540   *         parameters in the RCC_ClkInitStruct.
00541   * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
00542   *         contains the configuration information for the RCC peripheral.
00543   * @param  FLatency: FLASH Latency, this parameter depend on device selected
00544   *
00545   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00546   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
00547   *
00548   * @note   The HSI is used (enabled by hardware) as system clock source after
00549   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
00550   *         of failure of the HSE used directly or indirectly as system clock
00551   *         (if the Clock Security System CSS is enabled).
00552   *
00553   * @note   A switch from one clock source to another occurs only if the target
00554   *         clock source is ready (clock stable after startup delay or PLL locked).
00555   *         If a clock source which is not yet ready is selected, the switch will
00556   *         occur when the clock source will be ready.
00557   *
00558   * @note   Depending on the device voltage range, the software has to set correctly
00559   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
00560   *         (for more details refer to section above "Initialization/de-initialization functions")
00561   * @retval None
00562   */
00563 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00564 {
00565   uint32_t tickstart = 0U;
00566
00567   /* Check the parameters */
00568   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00569   assert_param(IS_FLASH_LATENCY(FLatency));
00570
00571   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00572     must be correctly programmed according to the frequency of the CPU clock
00573     (HCLK) and the supply voltage of the device. */
00574
00575   /* Increasing the number of wait states because of higher CPU frequency */
00576   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
00577   {
00578     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00579     __HAL_FLASH_SET_LATENCY(FLatency);
00580
00581     /* Check that the new number of wait states is taken into account to access the Flash
00582     memory by reading the FLASH_ACR register */
00583     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00584     {
00585       return HAL_ERROR;
00586     }
00587   }
00588
00589   /*-------------------------- HCLK Configuration --------------------------*/
00590   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00591   {
00592     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00593     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00594   }
00595
00596   /*------------------------- SYSCLK Configuration ---------------------------*/
00597   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00598   {
00599     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00600
00601     /* HSE is selected as System Clock Source */
00602     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00603     {
00604       /* Check the HSE ready flag */
00605       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00606       {
00607         return HAL_ERROR;
00608       }
00609     }
00610     /* PLL is selected as System Clock Source */
00611     else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
00612             (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
00613     {
00614       /* Check the PLL ready flag */
00615       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00616       {
00617         return HAL_ERROR;
00618       }
00619     }
00620     /* HSI is selected as System Clock Source */
00621     else
00622     {
00623       /* Check the HSI ready flag */
00624       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00625       {
00626         return HAL_ERROR;
00627       }
00628     }
00629
00630     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
00631     /* Get Start Tick*/
00632     tickstart = HAL_GetTick();
00633
00634     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00635     {
00636       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
00637       {
00638         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00639         {
00640           return HAL_TIMEOUT;
00641         }
00642       }
00643     }
00644     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00645     {
00646       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00647       {
00648         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00649         {
00650           return HAL_TIMEOUT;
00651         }
00652       }
00653     }
00654     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
00655     {
00656       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
00657       {
00658         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00659         {
00660           return HAL_TIMEOUT;
00661         }
00662       }
00663     }
00664     else
00665     {
00666       while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
00667       {
00668         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00669         {
00670           return HAL_TIMEOUT;
00671         }
00672       }
00673     }
00674   }
00675
00676   /* Decreasing the number of wait states because of lower CPU frequency */
00677   if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
00678   {
00679      /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00680     __HAL_FLASH_SET_LATENCY(FLatency);
00681
00682     /* Check that the new number of wait states is taken into account to access the Flash
00683     memory by reading the FLASH_ACR register */
00684     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00685     {
00686       return HAL_ERROR;
00687     }
00688  }
00689
00690   /*-------------------------- PCLK1 Configuration ---------------------------*/
00691   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00692   {
00693     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00694     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
00695   }
00696
00697   /*-------------------------- PCLK2 Configuration ---------------------------*/
00698   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00699   {
00700     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
00701     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
00702   }
00703
00704   /* Configure the source of time base considering new system clocks settings*/
00705   HAL_InitTick (TICK_INT_PRIORITY);
00706
00707   return HAL_OK;
00708 }
00709
00710 /**
00711   * @}
00712   */
00713
00714 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
00715  *  @brief   RCC clocks control functions
00716  *
00717 @verbatim
00718  ===============================================================================
00719                       ##### Peripheral Control functions #####
00720  ===============================================================================
00721     [..]
00722     This subsection provides a set of functions allowing to control the RCC Clocks
00723     frequencies.
00724
00725 @endverbatim
00726   * @{
00727   */
00728
00729 /**
00730   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
00731   * @note   PA8/PC9 should be configured in alternate function mode.
00732   * @param  RCC_MCOx: specifies the output direction for the clock source.
00733   *          This parameter can be one of the following values:
00734   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
00735   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
00736   * @param  RCC_MCOSource: specifies the clock source to output.
00737   *          This parameter can be one of the following values:
00738   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
00739   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
00740   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
00741   *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
00742   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
00743   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
00744   *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
00745   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
00746   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
00747   * @param  RCC_MCODiv: specifies the MCOx prescaler.
00748   *          This parameter can be one of the following values:
00749   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
00750   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
00751   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
00752   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
00753   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
00754   * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
00755   *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
00756   * @retval None
00757   */
00758 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
00759 {
00760   GPIO_InitTypeDef GPIO_InitStruct;
00761   /* Check the parameters */
00762   assert_param(IS_RCC_MCO(RCC_MCOx));
00763   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
00764   /* RCC_MCO1 */
00765   if(RCC_MCOx == RCC_MCO1)
00766   {
00767     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
00768
00769     /* MCO1 Clock Enable */
00770     __MCO1_CLK_ENABLE();
00771
00772     /* Configure the MCO1 pin in alternate function mode */
00773     GPIO_InitStruct.Pin = MCO1_PIN;
00774     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00775     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
00776     GPIO_InitStruct.Pull = GPIO_NOPULL;
00777     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00778     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
00779
00780     /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
00781     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
00782
00783    /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
00784 #if defined(RCC_CFGR_MCO1EN)
00785     __HAL_RCC_MCO1_ENABLE();
00786 #endif /* RCC_CFGR_MCO1EN */
00787   }
00788 #if defined(RCC_CFGR_MCO2)
00789   else
00790   {
00791     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
00792
00793     /* MCO2 Clock Enable */
00794     __MCO2_CLK_ENABLE();
00795
00796     /* Configure the MCO2 pin in alternate function mode */
00797     GPIO_InitStruct.Pin = MCO2_PIN;
00798     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00799     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
00800     GPIO_InitStruct.Pull = GPIO_NOPULL;
00801     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00802     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
00803
00804     /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
00805     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
00806
00807    /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
00808 #if defined(RCC_CFGR_MCO2EN)
00809     __HAL_RCC_MCO2_ENABLE();
00810 #endif /* RCC_CFGR_MCO2EN */
00811   }
00812 #endif /* RCC_CFGR_MCO2 */
00813 }
00814
00815 /**
00816   * @brief  Enables the Clock Security System.
00817   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
00818   *         is automatically disabled and an interrupt is generated to inform the
00819   *         software about the failure (Clock Security System Interrupt, CSSI),
00820   *         allowing the MCU to perform rescue operations. The CSSI is linked to
00821   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
00822   * @retval None
00823   */
00824 void HAL_RCC_EnableCSS(void)
00825 {
00826   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
00827 }
00828
00829 /**
00830   * @brief  Disables the Clock Security System.
00831   * @retval None
00832   */
00833 void HAL_RCC_DisableCSS(void)
00834 {
00835   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
00836 }
00837
00838 /**
00839   * @brief  Returns the SYSCLK frequency
00840   *
00841   * @note   The system frequency computed by this function is not the real
00842   *         frequency in the chip. It is calculated based on the predefined
00843   *         constant and the selected clock source:
00844   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
00845   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
00846   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
00847   *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
00848   * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
00849   *               16 MHz) but the real value may vary depending on the variations
00850   *               in voltage and temperature.
00851   * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
00852   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
00853   *                frequency of the crystal used. Otherwise, this function may
00854   *                have wrong result.
00855   *
00856   * @note   The result of this function could be not correct when using fractional
00857   *         value for HSE crystal.
00858   *
00859   * @note   This function can be used by the user application to compute the
00860   *         baudrate for the communication peripherals or configure other parameters.
00861   *
00862   * @note   Each time SYSCLK changes, this function must be called to update the
00863   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
00864   *
00865   *
00866   * @retval SYSCLK frequency
00867   */
00868 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
00869 {
00870   uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
00871   uint32_t sysclockfreq = 0U;
00872
00873   /* Get SYSCLK source -------------------------------------------------------*/
00874   switch (RCC->CFGR & RCC_CFGR_SWS)
00875   {
00876     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
00877     {
00878       sysclockfreq = HSI_VALUE;
00879        break;
00880     }
00881     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
00882     {
00883       sysclockfreq = HSE_VALUE;
00884       break;
00885     }
00886     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
00887     {
00888       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
00889       SYSCLK = PLL_VCO / PLLP */
00890       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
00891       if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
00892       {
00893         /* HSE used as PLL clock source */
00894         pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
00895       }
00896       else
00897       {
00898         /* HSI used as PLL clock source */
00899         pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
00900       }
00901       pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
00902
00903       sysclockfreq = pllvco/pllp;
00904       break;
00905     }
00906     default:
00907     {
00908       sysclockfreq = HSI_VALUE;
00909       break;
00910     }
00911   }
00912   return sysclockfreq;
00913 }
00914
00915 /**
00916   * @brief  Returns the HCLK frequency
00917   * @note   Each time HCLK changes, this function must be called to update the
00918   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
00919   *
00920   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00921   *         and updated within this function
00922   * @retval HCLK frequency
00923   */
00924 uint32_t HAL_RCC_GetHCLKFreq(void)
00925 {
00926   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
00927   return SystemCoreClock;
00928 }
00929
00930 /**
00931   * @brief  Returns the PCLK1 frequency
00932   * @note   Each time PCLK1 changes, this function must be called to update the
00933   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
00934   * @retval PCLK1 frequency
00935   */
00936 uint32_t HAL_RCC_GetPCLK1Freq(void)
00937 {
00938   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
00939   return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
00940 }
00941
00942 /**
00943   * @brief  Returns the PCLK2 frequency
00944   * @note   Each time PCLK2 changes, this function must be called to update the
00945   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
00946   * @retval PCLK2 frequency
00947   */
00948 uint32_t HAL_RCC_GetPCLK2Freq(void)
00949 {
00950   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
00951   return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
00952 }
00953
00954 /**
00955   * @brief  Configures the RCC_OscInitStruct according to the internal
00956   * RCC configuration registers.
00957   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
00958   * will be configured.
00959   * @retval None
00960   */
00961 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00962 {
00963   /* Set all possible values for the Oscillator type parameter ---------------*/
00964   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
00965
00966   /* Get the HSE configuration -----------------------------------------------*/
00967   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
00968   {
00969     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
00970   }
00971   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
00972   {
00973     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
00974   }
00975   else
00976   {
00977     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
00978   }
00979
00980   /* Get the HSI configuration -----------------------------------------------*/
00981   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
00982   {
00983     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
00984   }
00985   else
00986   {
00987     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
00988   }
00989
00990   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
00991
00992   /* Get the LSE configuration -----------------------------------------------*/
00993   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
00994   {
00995     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
00996   }
00997   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
00998   {
00999     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01000   }
01001   else
01002   {
01003     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01004   }
01005
01006   /* Get the LSI configuration -----------------------------------------------*/
01007   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
01008   {
01009     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01010   }
01011   else
01012   {
01013     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01014   }
01015
01016   /* Get the PLL configuration -----------------------------------------------*/
01017   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
01018   {
01019     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01020   }
01021   else
01022   {
01023     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01024   }
01025   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
01026   RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
01027   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
01028   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
01029   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
01030 }
01031
01032 /**
01033   * @brief  Configures the RCC_ClkInitStruct according to the internal
01034   * RCC configuration registers.
01035   * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
01036   * will be configured.
01037   * @param  pFLatency: Pointer on the Flash Latency.
01038   * @retval None
01039   */
01040 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01041 {
01042   /* Set all possible values for the Clock type parameter --------------------*/
01043   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
01044
01045   /* Get the SYSCLK configuration --------------------------------------------*/
01046   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01047
01048   /* Get the HCLK configuration ----------------------------------------------*/
01049   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
01050
01051   /* Get the APB1 configuration ----------------------------------------------*/
01052   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
01053
01054   /* Get the APB2 configuration ----------------------------------------------*/
01055   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
01056
01057   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01058   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01059 }
01060
01061 /**
01062   * @brief This function handles the RCC CSS interrupt request.
01063   * @note This API should be called under the NMI_Handler().
01064   * @retval None
01065   */
01066 void HAL_RCC_NMI_IRQHandler(void)
01067 {
01068   /* Check RCC CSSF flag  */
01069   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01070   {
01071     /* RCC Clock Security System interrupt user callback */
01072     HAL_RCC_CSSCallback();
01073
01074     /* Clear RCC CSS pending bit */
01075     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01076   }
01077 }
01078
01079 /**
01080   * @brief  RCC Clock Security System interrupt callback
01081   * @retval None
01082   */
01083 __weak void HAL_RCC_CSSCallback(void)
01084 {
01085   /* NOTE : This function Should not be modified, when the callback is needed,
01086             the HAL_RCC_CSSCallback could be implemented in the user file
01087    */
01088 }
01089
01090 /**
01091   * @}
01092   */
01093
01094 /**
01095   * @}
01096   */
01097
01098 #endif /* HAL_RCC_MODULE_ENABLED */
01099 /**
01100   * @}
01101   */
01102
01103 /**
01104   * @}
01105   */
01106
01107 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc.h Source File

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stm32f4xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of RCC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_RCC_H
00040 #define __STM32F4xx_HAL_RCC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /* Include RCC HAL Extended module */
00050 /* (include on top of file since RCC structures are defined in extended file) */
00051 #include "stm32f4xx_hal_rcc_ex.h"
00052
00053 /** @addtogroup STM32F4xx_HAL_Driver
00054   * @{
00055   */
00056
00057 /** @addtogroup RCC
00058   * @{
00059   */
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 /** @defgroup RCC_Exported_Types RCC Exported Types
00063   * @{
00064   */
00065
00066 /**
00067   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
00068   */
00069 typedef struct
00070 {
00071   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00072                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
00073
00074   uint32_t HSEState;             /*!< The new state of the HSE.
00075                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00076
00077   uint32_t LSEState;             /*!< The new state of the LSE.
00078                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00079
00080   uint32_t HSIState;             /*!< The new state of the HSI.
00081                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00082
00083   uint32_t HSICalibrationValue;  /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
00084                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00085
00086   uint32_t LSIState;             /*!< The new state of the LSI.
00087                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00088
00089   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
00090 }RCC_OscInitTypeDef;
00091
00092 /**
00093   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00094   */
00095 typedef struct
00096 {
00097   uint32_t ClockType;             /*!< The clock to be configured.
00098                                        This parameter can be a value of @ref RCC_System_Clock_Type      */
00099
00100   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
00101                                        This parameter can be a value of @ref RCC_System_Clock_Source    */
00102
00103   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00104                                        This parameter can be a value of @ref RCC_AHB_Clock_Source       */
00105
00106   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00107                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00108
00109   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00110                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00111
00112 }RCC_ClkInitTypeDef;
00113
00114 /**
00115   * @}
00116   */
00117
00118 /* Exported constants --------------------------------------------------------*/
00119 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00120   * @{
00121   */
00122
00123 /** @defgroup RCC_Oscillator_Type Oscillator Type
00124   * @{
00125   */
00126 #define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000U)
00127 #define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001U)
00128 #define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002U)
00129 #define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004U)
00130 #define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008U)
00131 /**
00132   * @}
00133   */
00134
00135 /** @defgroup RCC_HSE_Config HSE Config
00136   * @{
00137   */
00138 #define RCC_HSE_OFF                      ((uint8_t)0x00U)
00139 #define RCC_HSE_ON                       ((uint8_t)0x01U)
00140 #define RCC_HSE_BYPASS                   ((uint8_t)0x05U)
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup RCC_LSE_Config LSE Config
00146   * @{
00147   */
00148 #define RCC_LSE_OFF                      ((uint8_t)0x00U)
00149 #define RCC_LSE_ON                       ((uint8_t)0x01U)
00150 #define RCC_LSE_BYPASS                   ((uint8_t)0x05U)
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup RCC_HSI_Config HSI Config
00156   * @{
00157   */
00158 #define RCC_HSI_OFF                      ((uint8_t)0x00U)
00159 #define RCC_HSI_ON                       ((uint8_t)0x01U)
00160
00161 #define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10U)         /* Default HSI calibration trimming value */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup RCC_LSI_Config LSI Config
00167   * @{
00168   */
00169 #define RCC_LSI_OFF                      ((uint8_t)0x00U)
00170 #define RCC_LSI_ON                       ((uint8_t)0x01U)
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup RCC_PLL_Config PLL Config
00176   * @{
00177   */
00178 #define RCC_PLL_NONE                      ((uint8_t)0x00U)
00179 #define RCC_PLL_OFF                       ((uint8_t)0x01U)
00180 #define RCC_PLL_ON                        ((uint8_t)0x02U)
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
00186   * @{
00187   */
00188 #define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U)
00189 #define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U)
00190 #define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U)
00191 #define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U)
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00197   * @{
00198   */
00199 #define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
00200 #define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup RCC_System_Clock_Type System Clock Type
00206   * @{
00207   */
00208 #define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001U)
00209 #define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002U)
00210 #define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004U)
00211 #define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008U)
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup RCC_System_Clock_Source System Clock Source
00217   * @{
00218   */
00219 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
00220 #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
00221 #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
00222 #define RCC_SYSCLKSOURCE_PLLRCLK         ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00228   * @{
00229   */
00230 #define RCC_SYSCLKSOURCE_STATUS_HSI     RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00231 #define RCC_SYSCLKSOURCE_STATUS_HSE     RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00232 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK  RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00233 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))   /*!< PLLR used as system clock */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
00239   * @{
00240   */
00241 #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
00242 #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
00243 #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
00244 #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
00245 #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
00246 #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
00247 #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
00248 #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
00249 #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
00255   * @{
00256   */
00257 #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
00258 #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
00259 #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
00260 #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
00261 #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
00267   * @{
00268   */
00269 #define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100U)
00270 #define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200U)
00271 #define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300U)
00272 #define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300U)
00273 #define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300U)
00274 #define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300U)
00275 #define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300U)
00276 #define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300U)
00277 #define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300U)
00278 #define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300U)
00279 #define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300U)
00280 #define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300U)
00281 #define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300U)
00282 #define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300U)
00283 #define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300U)
00284 #define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300U)
00285 #define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300U)
00286 #define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300U)
00287 #define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300U)
00288 #define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300U)
00289 #define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300U)
00290 #define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300U)
00291 #define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300U)
00292 #define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300U)
00293 #define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300U)
00294 #define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300U)
00295 #define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300U)
00296 #define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300U)
00297 #define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300U)
00298 #define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300U)
00299 #define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300U)
00300 #define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300U)
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup RCC_MCO_Index MCO Index
00306   * @{
00307   */
00308 #define RCC_MCO1                         ((uint32_t)0x00000000U)
00309 #define RCC_MCO2                         ((uint32_t)0x00000001U)
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
00315   * @{
00316   */
00317 #define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000U)
00318 #define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
00319 #define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
00320 #define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
00326   * @{
00327   */
00328 #define RCC_MCODIV_1                    ((uint32_t)0x00000000U)
00329 #define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
00330 #define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
00331 #define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
00332 #define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup RCC_Interrupt Interrupts
00338   * @{
00339   */
00340 #define RCC_IT_LSIRDY                    ((uint8_t)0x01U)
00341 #define RCC_IT_LSERDY                    ((uint8_t)0x02U)
00342 #define RCC_IT_HSIRDY                    ((uint8_t)0x04U)
00343 #define RCC_IT_HSERDY                    ((uint8_t)0x08U)
00344 #define RCC_IT_PLLRDY                    ((uint8_t)0x10U)
00345 #define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20U)
00346 #define RCC_IT_CSS                       ((uint8_t)0x80U)
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup RCC_Flag Flags
00352   *        Elements values convention: 0XXYYYYYb
00353   *           - YYYYY  : Flag position in the register
00354   *           - 0XX  : Register index
00355   *                 - 01: CR register
00356   *                 - 10: BDCR register
00357   *                 - 11: CSR register
00358   * @{
00359   */
00360 /* Flags in the CR register */
00361 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21U)
00362 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31U)
00363 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39U)
00364 #define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3BU)
00365
00366 /* Flags in the BDCR register */
00367 #define RCC_FLAG_LSERDY                  ((uint8_t)0x41U)
00368
00369 /* Flags in the CSR register */
00370 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61U)
00371 #define RCC_FLAG_BORRST                  ((uint8_t)0x79U)
00372 #define RCC_FLAG_PINRST                  ((uint8_t)0x7AU)
00373 #define RCC_FLAG_PORRST                  ((uint8_t)0x7BU)
00374 #define RCC_FLAG_SFTRST                  ((uint8_t)0x7CU)
00375 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7DU)
00376 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7EU)
00377 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7FU)
00378 /**
00379   * @}
00380   */
00381
00382 /**
00383   * @}
00384   */
00385
00386 /* Exported macro ------------------------------------------------------------*/
00387 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00388   * @{
00389   */
00390
00391 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
00392   * @brief  Enable or disable the AHB1 peripheral clock.
00393   * @note   After reset, the peripheral clock (used for registers read/write access)
00394   *         is disabled and the application software has to enable this clock before
00395   *         using it.
00396   * @{
00397   */
00398 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
00399                                         __IO uint32_t tmpreg = 0x00U; \
00400                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
00401                                         /* Delay after an RCC peripheral clock enabling */ \
00402                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
00403                                         UNUSED(tmpreg); \
00404                                           } while(0)
00405 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
00406                                         __IO uint32_t tmpreg = 0x00U; \
00407                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
00408                                         /* Delay after an RCC peripheral clock enabling */ \
00409                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
00410                                         UNUSED(tmpreg); \
00411                                           } while(0)
00412 #define __HAL_RCC_GPIOC_CLK_ENABLE()  do { \
00413                                         __IO uint32_t tmpreg = 0x00U; \
00414                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
00415                                         /* Delay after an RCC peripheral clock enabling */ \
00416                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
00417                                         UNUSED(tmpreg); \
00418                                           } while(0)
00419 #define __HAL_RCC_GPIOH_CLK_ENABLE()  do { \
00420                                         __IO uint32_t tmpreg = 0x00U; \
00421                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
00422                                         /* Delay after an RCC peripheral clock enabling */ \
00423                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
00424                                         UNUSED(tmpreg); \
00425                                          } while(0)
00426 #define __HAL_RCC_DMA1_CLK_ENABLE()  do { \
00427                                         __IO uint32_t tmpreg = 0x00U; \
00428                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00429                                         /* Delay after an RCC peripheral clock enabling */ \
00430                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
00431                                         UNUSED(tmpreg); \
00432                                          } while(0)
00433 #define __HAL_RCC_DMA2_CLK_ENABLE()     do { \
00434                                         __IO uint32_t tmpreg = 0x00U; \
00435                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00436                                         /* Delay after an RCC peripheral clock enabling */ \
00437                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
00438                                         UNUSED(tmpreg); \
00439                                           } while(0)
00440
00441 #define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
00442 #define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
00443 #define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
00444 #define __HAL_RCC_GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
00445 #define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
00446 #define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
00452   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
00453   * @note   After reset, the peripheral clock (used for registers read/write access)
00454   *         is disabled and the application software has to enable this clock before
00455   *         using it.
00456   * @{
00457   */
00458 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
00459 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
00460 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
00461 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
00462 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
00463 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
00464
00465 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
00466 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
00467 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
00468 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
00469 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
00470 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
00471 /**
00472   * @}
00473   */
00474
00475 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
00476   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
00477   * @note   After reset, the peripheral clock (used for registers read/write access)
00478   *         is disabled and the application software has to enable this clock before
00479   *         using it.
00480   * @{
00481   */
00482 #define __HAL_RCC_TIM5_CLK_ENABLE()     do { \
00483                                         __IO uint32_t tmpreg = 0x00U; \
00484                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00485                                         /* Delay after an RCC peripheral clock enabling */ \
00486                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00487                                         UNUSED(tmpreg); \
00488                                           } while(0)
00489 #define __HAL_RCC_WWDG_CLK_ENABLE()     do { \
00490                                         __IO uint32_t tmpreg = 0x00U; \
00491                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00492                                         /* Delay after an RCC peripheral clock enabling */ \
00493                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00494                                         UNUSED(tmpreg); \
00495                                           } while(0)
00496 #define __HAL_RCC_SPI2_CLK_ENABLE()     do { \
00497                                         __IO uint32_t tmpreg = 0x00U; \
00498                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
00499                                         /* Delay after an RCC peripheral clock enabling */ \
00500                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
00501                                         UNUSED(tmpreg); \
00502                                           } while(0)
00503 #define __HAL_RCC_USART2_CLK_ENABLE()     do { \
00504                                         __IO uint32_t tmpreg = 0x00U; \
00505                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00506                                         /* Delay after an RCC peripheral clock enabling */ \
00507                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00508                                         UNUSED(tmpreg); \
00509                                           } while(0)
00510 #define __HAL_RCC_I2C1_CLK_ENABLE()     do { \
00511                                         __IO uint32_t tmpreg = 0x00U; \
00512                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00513                                         /* Delay after an RCC peripheral clock enabling */ \
00514                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00515                                         UNUSED(tmpreg); \
00516                                           } while(0)
00517 #define __HAL_RCC_I2C2_CLK_ENABLE()     do { \
00518                                         __IO uint32_t tmpreg = 0x00U; \
00519                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
00520                                         /* Delay after an RCC peripheral clock enabling */ \
00521                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
00522                                         UNUSED(tmpreg); \
00523                                           } while(0)
00524 #define __HAL_RCC_PWR_CLK_ENABLE()     do { \
00525                                         __IO uint32_t tmpreg = 0x00U; \
00526                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00527                                         /* Delay after an RCC peripheral clock enabling */ \
00528                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00529                                         UNUSED(tmpreg); \
00530                                           } while(0)
00531
00532 #define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
00533 #define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
00534 #define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
00535 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
00536 #define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
00537 #define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
00538 #define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
00539 /**
00540   * @}
00541   */
00542
00543 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
00544   * @brief  Get the enable or disable status of the APB1 peripheral clock.
00545   * @note   After reset, the peripheral clock (used for registers read/write access)
00546   *         is disabled and the application software has to enable this clock before
00547   *         using it.
00548   * @{
00549   */
00550 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
00551 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
00552 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
00553 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
00554 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
00555 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
00556 #define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
00557
00558 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
00559 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
00560 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
00561 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
00562 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
00563 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
00564 #define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
00565 /**
00566   * @}
00567   */
00568
00569 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
00570   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
00571   * @note   After reset, the peripheral clock (used for registers read/write access)
00572   *         is disabled and the application software has to enable this clock before
00573   *         using it.
00574   * @{
00575   */
00576 #define __HAL_RCC_TIM1_CLK_ENABLE()     do { \
00577                                         __IO uint32_t tmpreg = 0x00U; \
00578                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
00579                                         /* Delay after an RCC peripheral clock enabling */ \
00580                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
00581                                         UNUSED(tmpreg); \
00582                                           } while(0)
00583 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
00584                                         __IO uint32_t tmpreg = 0x00U; \
00585                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
00586                                         /* Delay after an RCC peripheral clock enabling */ \
00587                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
00588                                         UNUSED(tmpreg); \
00589                                           } while(0)
00590 #define __HAL_RCC_USART6_CLK_ENABLE()   do { \
00591                                         __IO uint32_t tmpreg = 0x00U; \
00592                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
00593                                         /* Delay after an RCC peripheral clock enabling */ \
00594                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
00595                                         UNUSED(tmpreg); \
00596                                           } while(0)
00597 #define __HAL_RCC_ADC1_CLK_ENABLE()     do { \
00598                                         __IO uint32_t tmpreg = 0x00U; \
00599                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
00600                                         /* Delay after an RCC peripheral clock enabling */ \
00601                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
00602                                         UNUSED(tmpreg); \
00603                                           } while(0)
00604 #define __HAL_RCC_SPI1_CLK_ENABLE()     do { \
00605                                         __IO uint32_t tmpreg = 0x00U; \
00606                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
00607                                         /* Delay after an RCC peripheral clock enabling */ \
00608                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
00609                                         UNUSED(tmpreg); \
00610                                           } while(0)
00611 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
00612                                         __IO uint32_t tmpreg = 0x00U; \
00613                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
00614                                         /* Delay after an RCC peripheral clock enabling */ \
00615                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
00616                                         UNUSED(tmpreg); \
00617                                           } while(0)
00618 #define __HAL_RCC_TIM9_CLK_ENABLE()     do { \
00619                                         __IO uint32_t tmpreg = 0x00U; \
00620                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
00621                                         /* Delay after an RCC peripheral clock enabling */ \
00622                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
00623                                         UNUSED(tmpreg); \
00624                                           } while(0)
00625 #define __HAL_RCC_TIM11_CLK_ENABLE()    do { \
00626                                         __IO uint32_t tmpreg = 0x00U; \
00627                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
00628                                         /* Delay after an RCC peripheral clock enabling */ \
00629                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
00630                                         UNUSED(tmpreg); \
00631                                           } while(0)
00632
00633 #define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
00634 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
00635 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
00636 #define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
00637 #define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
00638 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
00639 #define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
00640 #define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
00641 /**
00642   * @}
00643   */
00644
00645 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
00646   * @brief  Get the enable or disable status of the APB2 peripheral clock.
00647   * @note   After reset, the peripheral clock (used for registers read/write access)
00648   *         is disabled and the application software has to enable this clock before
00649   *         using it.
00650   * @{
00651   */
00652 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
00653 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
00654 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
00655 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
00656 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
00657 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
00658 #define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
00659 #define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
00660
00661 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
00662 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
00663 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
00664 #define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
00665 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
00666 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
00667 #define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
00668 #define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
00674   * @brief  Force or release AHB1 peripheral reset.
00675   * @{
00676   */
00677 #define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
00678 #define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
00679 #define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
00680 #define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
00681 #define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
00682 #define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
00683 #define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
00684
00685 #define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
00686 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
00687 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
00688 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
00689 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
00690 #define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
00691 #define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
00697   * @brief  Force or release APB1 peripheral reset.
00698   * @{
00699   */
00700 #define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
00701 #define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
00702 #define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
00703 #define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
00704 #define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
00705 #define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
00706 #define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
00707 #define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
00708
00709 #define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)
00710 #define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
00711 #define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
00712 #define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
00713 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
00714 #define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
00715 #define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
00716 #define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
00722   * @brief  Force or release APB2 peripheral reset.
00723   * @{
00724   */
00725 #define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
00726 #define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
00727 #define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
00728 #define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
00729 #define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
00730 #define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
00731 #define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
00732 #define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
00733 #define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
00734
00735 #define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
00736 #define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
00737 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
00738 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
00739 #define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
00740 #define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
00741 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
00742 #define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
00743 #define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
00744 /**
00745   * @}
00746   */
00747
00748 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
00749   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
00750   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00751   *         power consumption.
00752   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
00753   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00754   * @{
00755   */
00756 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
00757 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
00758 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
00759 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
00760 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
00761 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
00762
00763 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
00764 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
00765 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
00766 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
00767 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
00768 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
00769 /**
00770   * @}
00771   */
00772
00773 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
00774   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
00775   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00776   *         power consumption.
00777   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
00778   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00779   * @{
00780   */
00781 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
00782 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
00783 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
00784 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
00785 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
00786 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
00787 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
00788
00789 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
00790 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
00791 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
00792 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
00793 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
00794 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
00795 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
00796 /**
00797   * @}
00798   */
00799
00800 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
00801   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
00802   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
00803   *         power consumption.
00804   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
00805   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
00806   * @{
00807   */
00808 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
00809 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
00810 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
00811 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
00812 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
00813 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
00814 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
00815 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
00816
00817 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
00818 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
00819 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
00820 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
00821 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
00822 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
00823 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
00824 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
00825 /**
00826   * @}
00827   */
00828
00829 /** @defgroup RCC_HSI_Configuration HSI Configuration
00830   * @{
00831   */
00832
00833 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
00834   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
00835   *         It is used (enabled by hardware) as system clock source after startup
00836   *         from Reset, wake-up from STOP and STANDBY mode, or in case of failure
00837   *         of the HSE used directly or indirectly as system clock (if the Clock
00838   *         Security System CSS is enabled).
00839   * @note   HSI can not be stopped if it is used as system clock source. In this case,
00840   *         you have to select another source of the system clock then stop the HSI.
00841   * @note   After enabling the HSI, the application software should wait on HSIRDY
00842   *         flag to be set indicating that HSI clock is stable and can be used as
00843   *         system clock source.
00844   *         This parameter can be: ENABLE or DISABLE.
00845   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
00846   *         clock cycles.
00847   */
00848 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
00849 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
00850
00851 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
00852   * @note   The calibration is used to compensate for the variations in voltage
00853   *         and temperature that influence the frequency of the internal HSI RC.
00854   * @param  __HSICalibrationValue__: specifies the calibration trimming value.
00855   *         (default is RCC_HSICALIBRATION_DEFAULT).
00856   *         This parameter must be a number between 0 and 0x1F.
00857   */
00858 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
00859         RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
00860 /**
00861   * @}
00862   */
00863
00864 /** @defgroup RCC_LSI_Configuration LSI Configuration
00865   * @{
00866   */
00867
00868 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
00869   * @note   After enabling the LSI, the application software should wait on
00870   *         LSIRDY flag to be set indicating that LSI clock is stable and can
00871   *         be used to clock the IWDG and/or the RTC.
00872   * @note   LSI can not be disabled if the IWDG is running.
00873   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
00874   *         clock cycles.
00875   */
00876 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
00877 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
00878 /**
00879   * @}
00880   */
00881
00882 /** @defgroup RCC_HSE_Configuration HSE Configuration
00883   * @{
00884   */
00885
00886 /**
00887   * @brief  Macro to configure the External High Speed oscillator (HSE).
00888   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
00889   *         User should request a transition to HSE Off first and then HSE On or HSE Bypass.
00890   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
00891   *         software should wait on HSERDY flag to be set indicating that HSE clock
00892   *         is stable and can be used to clock the PLL and/or system clock.
00893   * @note   HSE state can not be changed if it is used directly or through the
00894   *         PLL as system clock. In this case, you have to select another source
00895   *         of the system clock then change the HSE state (ex. disable it).
00896   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
00897   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
00898   *         was previously enabled you have to enable it again after calling this
00899   *         function.
00900   * @param  __STATE__: specifies the new state of the HSE.
00901   *         This parameter can be one of the following values:
00902   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
00903   *                              6 HSE oscillator clock cycles.
00904   *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
00905   *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
00906   */
00907 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
00908 /**
00909   * @}
00910   */
00911
00912 /** @defgroup RCC_LSE_Configuration LSE Configuration
00913   * @{
00914   */
00915
00916 /**
00917   * @brief  Macro to configure the External Low Speed oscillator (LSE).
00918   * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
00919   *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
00920   * @note   As the LSE is in the Backup domain and write access is denied to
00921   *         this domain after reset, you have to enable write access using
00922   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
00923   *         (to be done once after reset).
00924   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
00925   *         software should wait on LSERDY flag to be set indicating that LSE clock
00926   *         is stable and can be used to clock the RTC.
00927   * @param  __STATE__: specifies the new state of the LSE.
00928   *         This parameter can be one of the following values:
00929   *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
00930   *                              6 LSE oscillator clock cycles.
00931   *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
00932   *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
00933   */
00934 #define __HAL_RCC_LSE_CONFIG(__STATE__)  (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
00935
00936 /**
00937   * @}
00938   */
00939
00940 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
00941   * @{
00942   */
00943
00944 /** @brief  Macros to enable or disable the RTC clock.
00945   * @note   These macros must be used only after the RTC clock source was selected.
00946   */
00947 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
00948 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
00949
00950 /** @brief  Macros to configure the RTC clock (RTCCLK).
00951   * @note   As the RTC clock configuration bits are in the Backup domain and write
00952   *         access is denied to this domain after reset, you have to enable write
00953   *         access using the Power Backup Access macro before to configure
00954   *         the RTC clock source (to be done once after reset).
00955   * @note   Once the RTC clock is configured it can't be changed unless the
00956   *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
00957   *         a Power On Reset (POR).
00958   * @param  __RTCCLKSource__: specifies the RTC clock source.
00959   *         This parameter can be one of the following values:
00960   *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
00961   *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
00962   *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
00963   *                                            as RTC clock, where x:[2,31]
00964   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
00965   *         work in STOP and STANDBY modes, and can be used as wake-up source.
00966   *         However, when the HSE clock is used as RTC clock source, the RTC
00967   *         cannot be used in STOP and STANDBY modes.
00968   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
00969   *         RTC clock source).
00970   */
00971 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
00972                                                  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
00973
00974 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
00975                                                     RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
00976                                                    } while (0)
00977
00978 /** @brief  Macros to force or release the Backup domain reset.
00979   * @note   This function resets the RTC peripheral (including the backup registers)
00980   *         and the RTC clock source selection in RCC_CSR register.
00981   * @note   The BKPSRAM is not affected by this reset.
00982   */
00983 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
00984 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
00985 /**
00986   * @}
00987   */
00988
00989 /** @defgroup RCC_PLL_Configuration PLL Configuration
00990   * @{
00991   */
00992
00993 /** @brief  Macros to enable or disable the main PLL.
00994   * @note   After enabling the main PLL, the application software should wait on
00995   *         PLLRDY flag to be set indicating that PLL clock is stable and can
00996   *         be used as system clock source.
00997   * @note   The main PLL can not be disabled if it is used as system clock source
00998   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
00999   */
01000 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
01001 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
01002
01003 /** @brief  Macro to configure the PLL clock source.
01004   * @note   This function must be used only when the main PLL is disabled.
01005   * @param  __PLLSOURCE__: specifies the PLL entry clock source.
01006   *         This parameter can be one of the following values:
01007   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
01008   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
01009   *
01010   */
01011 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
01012
01013 /** @brief  Macro to configure the PLL multiplication factor.
01014   * @note   This function must be used only when the main PLL is disabled.
01015   * @param  __PLLM__: specifies the division factor for PLL VCO input clock
01016   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
01017   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
01018   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
01019   *         of 2 MHz to limit PLL jitter.
01020   *
01021   */
01022 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
01023 /**
01024   * @}
01025   */
01026
01027 /** @defgroup RCC_Get_Clock_source Get Clock source
01028   * @{
01029   */
01030 /**
01031   * @brief Macro to configure the system clock source.
01032   * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
01033   * This parameter can be one of the following values:
01034   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
01035   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
01036   *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
01037   *              - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
01038   */
01039 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
01040
01041 /** @brief  Macro to get the clock source used as system clock.
01042   * @retval The clock source used as system clock. The returned value can be one
01043   *         of the following:
01044   *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
01045   *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
01046   *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
01047   *              - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
01048   */
01049 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
01050
01051 /** @brief  Macro to get the oscillator used as PLL clock source.
01052   * @retval The oscillator used as PLL clock source. The returned value can be one
01053   *         of the following:
01054   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
01055   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
01056   */
01057 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
01058 /**
01059   * @}
01060   */
01061
01062 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
01063   * @{
01064   */
01065
01066 /** @brief  Macro to configure the MCO1 clock.
01067   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
01068   *          This parameter can be one of the following values:
01069   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
01070   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
01071   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
01072   *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
01073   * @param  __MCODIV__ specifies the MCO clock prescaler.
01074   *          This parameter can be one of the following values:
01075   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
01076   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
01077   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
01078   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
01079   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
01080   */
01081 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
01082                  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
01083
01084 /** @brief  Macro to configure the MCO2 clock.
01085   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
01086   *          This parameter can be one of the following values:
01087   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
01088   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
01089   *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
01090   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
01091   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
01092   * @param  __MCODIV__ specifies the MCO clock prescaler.
01093   *          This parameter can be one of the following values:
01094   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
01095   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
01096   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
01097   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
01098   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
01099   * @note  For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
01100   *        at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
01101   */
01102 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
01103     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
01104 /**
01105   * @}
01106   */
01107
01108 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
01109   * @brief macros to manage the specified RCC Flags and interrupts.
01110   * @{
01111   */
01112
01113 /** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
01114   *         the selected interrupts).
01115   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
01116   *         This parameter can be any combination of the following values:
01117   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01118   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01119   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01120   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01121   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01122   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01123   */
01124 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
01125
01126 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
01127   *        the selected interrupts).
01128   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
01129   *         This parameter can be any combination of the following values:
01130   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01131   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01132   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01133   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01134   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01135   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01136   */
01137 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
01138
01139 /** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
01140   *         bits to clear the selected interrupt pending bits.
01141   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
01142   *         This parameter can be any combination of the following values:
01143   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01144   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01145   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01146   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01147   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01148   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01149   *            @arg RCC_IT_CSS: Clock Security System interrupt
01150   */
01151 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
01152
01153 /** @brief  Check the RCC's interrupt has occurred or not.
01154   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
01155   *         This parameter can be one of the following values:
01156   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
01157   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
01158   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
01159   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
01160   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
01161   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
01162   *            @arg RCC_IT_CSS: Clock Security System interrupt
01163   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
01164   */
01165 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
01166
01167 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
01168   *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
01169   */
01170 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
01171
01172 /** @brief  Check RCC flag is set or not.
01173   * @param  __FLAG__: specifies the flag to check.
01174   *         This parameter can be one of the following values:
01175   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
01176   *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
01177   *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
01178   *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
01179   *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
01180   *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
01181   *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
01182   *            @arg RCC_FLAG_PINRST: Pin reset.
01183   *            @arg RCC_FLAG_PORRST: POR/PDR reset.
01184   *            @arg RCC_FLAG_SFTRST: Software reset.
01185   *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
01186   *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
01187   *            @arg RCC_FLAG_LPWRRST: Low Power reset.
01188   * @retval The new state of __FLAG__ (TRUE or FALSE).
01189   */
01190 #define RCC_FLAG_MASK  ((uint8_t)0x1FU)
01191 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
01192
01193 /**
01194   * @}
01195   */
01196
01197 /**
01198   * @}
01199   */
01200
01201 /* Exported functions --------------------------------------------------------*/
01202  /** @addtogroup RCC_Exported_Functions
01203   * @{
01204   */
01205
01206 /** @addtogroup RCC_Exported_Functions_Group1
01207   * @{
01208   */
01209 /* Initialization and de-initialization functions  ******************************/
01210 void HAL_RCC_DeInit(void);
01211 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
01212 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
01213 /**
01214   * @}
01215   */
01216
01217 /** @addtogroup RCC_Exported_Functions_Group2
01218   * @{
01219   */
01220 /* Peripheral Control functions  ************************************************/
01221 void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
01222 void     HAL_RCC_EnableCSS(void);
01223 void     HAL_RCC_DisableCSS(void);
01224 uint32_t HAL_RCC_GetSysClockFreq(void);
01225 uint32_t HAL_RCC_GetHCLKFreq(void);
01226 uint32_t HAL_RCC_GetPCLK1Freq(void);
01227 uint32_t HAL_RCC_GetPCLK2Freq(void);
01228 void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
01229 void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
01230
01231 /* CSS NMI IRQ handler */
01232 void HAL_RCC_NMI_IRQHandler(void);
01233
01234 /* User Callbacks in non blocking mode (IT mode) */
01235 void HAL_RCC_CSSCallback(void);
01236
01237 /**
01238   * @}
01239   */
01240
01241 /**
01242   * @}
01243   */
01244
01245 /* Private types -------------------------------------------------------------*/
01246 /* Private variables ---------------------------------------------------------*/
01247 /* Private constants ---------------------------------------------------------*/
01248 /** @defgroup RCC_Private_Constants RCC Private Constants
01249   * @{
01250   */
01251
01252 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
01253   * @brief RCC registers bit address in the alias region
01254   * @{
01255   */
01256 #define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
01257 /* --- CR Register ---*/
01258 /* Alias word address of HSION bit */
01259 #define RCC_CR_OFFSET              (RCC_OFFSET + 0x00U)
01260 #define RCC_HSION_BIT_NUMBER       0x00U
01261 #define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
01262 /* Alias word address of CSSON bit */
01263 #define RCC_CSSON_BIT_NUMBER       0x13U
01264 #define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
01265 /* Alias word address of PLLON bit */
01266 #define RCC_PLLON_BIT_NUMBER       0x18U
01267 #define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
01268
01269 /* --- BDCR Register ---*/
01270 /* Alias word address of RTCEN bit */
01271 #define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70U)
01272 #define RCC_RTCEN_BIT_NUMBER       0x0FU
01273 #define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
01274 /* Alias word address of BDRST bit */
01275 #define RCC_BDRST_BIT_NUMBER       0x10U
01276 #define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
01277
01278 /* --- CSR Register ---*/
01279 /* Alias word address of LSION bit */
01280 #define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74U)
01281 #define RCC_LSION_BIT_NUMBER        0x00U
01282 #define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
01283
01284 /* CR register byte 3 (Bits[23:16]) base address */
01285 #define RCC_CR_BYTE2_ADDRESS       ((uint32_t)0x40023802U)
01286
01287 /* CIR register byte 2 (Bits[15:8]) base address */
01288 #define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
01289
01290 /* CIR register byte 3 (Bits[23:16]) base address */
01291 #define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
01292
01293 /* BDCR register base address */
01294 #define RCC_BDCR_BYTE0_ADDRESS     (PERIPH_BASE + RCC_BDCR_OFFSET)
01295
01296 #define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)2U)
01297 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
01298
01299 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
01300 #define HSI_TIMEOUT_VALUE          ((uint32_t)2U)  /* 2 ms */
01301 #define LSI_TIMEOUT_VALUE          ((uint32_t)2U)  /* 2 ms */
01302
01303 /**
01304   * @}
01305   */
01306
01307 /**
01308   * @}
01309   */
01310
01311 /* Private macros ------------------------------------------------------------*/
01312 /** @defgroup RCC_Private_Macros RCC Private Macros
01313   * @{
01314   */
01315
01316 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
01317   * @{
01318   */
01319 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
01320
01321 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
01322                          ((HSE) == RCC_HSE_BYPASS))
01323
01324 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
01325                          ((LSE) == RCC_LSE_BYPASS))
01326
01327 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
01328
01329 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
01330
01331 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
01332
01333 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
01334                                   ((SOURCE) == RCC_PLLSOURCE_HSE))
01335
01336 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
01337                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
01338                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
01339                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
01340
01341 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
01342
01343 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
01344
01345 #define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
01346
01347 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
01348                            ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
01349                            ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
01350                            ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
01351                            ((HCLK) == RCC_SYSCLK_DIV512))
01352
01353 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
01354
01355 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
01356                            ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
01357                            ((PCLK) == RCC_HCLK_DIV16))
01358
01359 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
01360
01361 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
01362                                    ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
01363
01364 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
01365                              ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
01366                              ((DIV) == RCC_MCODIV_5))
01367 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
01368
01369 /**
01370   * @}
01371   */
01372
01373 /**
01374   * @}
01375   */
01376
01377 /**
01378   * @}
01379   */
01380
01381 /**
01382   * @}
01383   */
01384
01385 #ifdef __cplusplus
01386 }
01387 #endif
01388
01389 #endif /* __STM32F4xx_HAL_RCC_H */
01390
01391 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc_ex.c Source File

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stm32f4xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Extension RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities RCC extension peripheral:
00010   *           + Extended Peripheral Control functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f4xx_hal.h"
00044
00045 /** @addtogroup STM32F4xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup RCCEx RCCEx
00050   * @brief RCCEx HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_RCC_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @addtogroup RCCEx_Private_Constants
00059   * @{
00060   */
00061 /**
00062   * @}
00063   */
00064 /* Private macro -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private function prototypes -----------------------------------------------*/
00067 /* Private functions ---------------------------------------------------------*/
00068 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00069   *  @{
00070   */
00071
00072 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00073  *  @brief  Extended Peripheral Control functions
00074  *
00075 @verbatim
00076  ===============================================================================
00077                 ##### Extended Peripheral Control functions  #####
00078  ===============================================================================
00079     [..]
00080     This subsection provides a set of functions allowing to control the RCC Clocks
00081     frequencies.
00082     [..]
00083     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00084         select the RTC clock source; in this case the Backup domain will be reset in
00085         order to modify the RTC Clock source, as consequence RTC registers (including
00086         the backup registers) and RCC_BDCR register are set to their reset values.
00087
00088 @endverbatim
00089   * @{
00090   */
00091 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00092     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00093     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00094     defined(STM32F469xx) || defined(STM32F479xx)
00095 /**
00096   * @brief  Resets the RCC clock configuration to the default reset state.
00097   * @note   The default reset state of the clock configuration is given below:
00098   *            - HSI ON and used as system clock source
00099   *            - HSE, PLL and PLLI2S OFF
00100   *            - AHB, APB1 and APB2 prescaler set to 1.
00101   *            - CSS, MCO1 and MCO2 OFF
00102   *            - All interrupts disabled
00103   * @note   This function doesn't modify the configuration of the
00104   *            - Peripheral clocks
00105   *            - LSI, LSE and RTC clocks
00106   * @retval None
00107   */
00108 void HAL_RCC_DeInit(void)
00109 {
00110   /* Set HSION bit */
00111   SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
00112
00113   /* Reset CFGR register */
00114   CLEAR_REG(RCC->CFGR);
00115
00116   /* Reset HSEON, CSSON, PLLON, PLLI2S */
00117   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
00118
00119   /* Reset PLLCFGR register */
00120   CLEAR_REG(RCC->PLLCFGR);
00121   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
00122
00123   /* Reset PLLI2SCFGR register */
00124   CLEAR_REG(RCC->PLLI2SCFGR);
00125   SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
00126
00127   /* Reset HSEBYP bit */
00128   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00129
00130   /* Disable all interrupts */
00131   CLEAR_REG(RCC->CIR);
00132 }
00133 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00134           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00135
00136 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00137 /**
00138   * @brief  Resets the RCC clock configuration to the default reset state.
00139   * @note   The default reset state of the clock configuration is given below:
00140   *            - HSI ON and used as system clock source
00141   *            - HSE and PLL OFF
00142   *            - AHB, APB1 and APB2 prescaler set to 1.
00143   *            - CSS, MCO1 and MCO2 OFF
00144   *            - All interrupts disabled
00145   * @note   This function doesn't modify the configuration of the
00146   *            - Peripheral clocks
00147   *            - LSI, LSE and RTC clocks
00148   * @retval None
00149   */
00150 void HAL_RCC_DeInit(void)
00151 {
00152   /* Set HSION bit */
00153   SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
00154
00155   /* Reset CFGR register */
00156   CLEAR_REG(RCC->CFGR);
00157
00158   /* Reset HSEON, CSSON, PLLON */
00159   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
00160
00161   /* Reset PLLCFGR register */
00162   CLEAR_REG(RCC->PLLCFGR);
00163   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
00164
00165   /* Reset HSEBYP bit */
00166   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00167
00168   /* Disable all interrupts */
00169   CLEAR_REG(RCC->CIR);
00170 }
00171 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00172
00173 #if defined(STM32F446xx)
00174 /**
00175   * @brief  Initializes the RCC extended peripherals clocks according to the specified
00176   *         parameters in the RCC_PeriphCLKInitTypeDef.
00177   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
00178   *         contains the configuration information for the Extended Peripherals
00179   *         clocks(I2S, SAI, LTDC RTC and TIM).
00180   *
00181   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00182   *         the RTC clock source; in this case the Backup domain will be reset in
00183   *         order to modify the RTC Clock source, as consequence RTC registers (including
00184   *         the backup registers) and RCC_BDCR register are set to their reset values.
00185   *
00186   * @retval HAL status
00187   */
00188 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00189 {
00190   uint32_t tickstart = 0U;
00191   uint32_t tmpreg1 = 0U;
00192   uint32_t plli2sp = 0U;
00193   uint32_t plli2sq = 0U;
00194   uint32_t plli2sr = 0U;
00195   uint32_t pllsaip = 0U;
00196   uint32_t pllsaiq = 0U;
00197   uint32_t plli2sused = 0U;
00198   uint32_t pllsaiused = 0U;
00199
00200   /* Check the peripheral clock selection parameters */
00201   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00202
00203   /*------------------------ I2S APB1 configuration --------------------------*/
00204   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
00205   {
00206     /* Check the parameters */
00207     assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
00208
00209     /* Configure I2S Clock source */
00210     __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
00211     /* Enable the PLLI2S when it's used as clock source for I2S */
00212     if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
00213     {
00214       plli2sused = 1U;
00215     }
00216   }
00217   /*--------------------------------------------------------------------------*/
00218
00219   /*---------------------------- I2S APB2 configuration ----------------------*/
00220   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
00221   {
00222     /* Check the parameters */
00223     assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
00224
00225     /* Configure I2S Clock source */
00226     __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
00227     /* Enable the PLLI2S when it's used as clock source for I2S */
00228     if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
00229     {
00230       plli2sused = 1U;
00231     }
00232   }
00233   /*--------------------------------------------------------------------------*/
00234
00235   /*--------------------------- SAI1 configuration ---------------------------*/
00236   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
00237   {
00238     /* Check the parameters */
00239     assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
00240
00241     /* Configure SAI1 Clock source */
00242     __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
00243     /* Enable the PLLI2S when it's used as clock source for SAI */
00244     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
00245     {
00246       plli2sused = 1U;
00247     }
00248     /* Enable the PLLSAI when it's used as clock source for SAI */
00249     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
00250     {
00251       pllsaiused = 1U;
00252     }
00253   }
00254   /*--------------------------------------------------------------------------*/
00255
00256   /*-------------------------- SAI2 configuration ----------------------------*/
00257   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
00258   {
00259     /* Check the parameters */
00260     assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
00261
00262     /* Configure SAI2 Clock source */
00263     __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
00264
00265     /* Enable the PLLI2S when it's used as clock source for SAI */
00266     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
00267     {
00268       plli2sused = 1U;
00269     }
00270     /* Enable the PLLSAI when it's used as clock source for SAI */
00271     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
00272     {
00273       pllsaiused = 1U;
00274     }
00275   }
00276   /*--------------------------------------------------------------------------*/
00277
00278   /*----------------------------- RTC configuration --------------------------*/
00279   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
00280   {
00281     /* Enable Power Clock*/
00282     __HAL_RCC_PWR_CLK_ENABLE();
00283
00284     /* Enable write access to Backup domain */
00285     PWR->CR |= PWR_CR_DBP;
00286
00287     /* Get tick */
00288     tickstart = HAL_GetTick();
00289
00290     while((PWR->CR & PWR_CR_DBP) == RESET)
00291     {
00292       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
00293       {
00294         return HAL_TIMEOUT;
00295       }
00296     }
00297     /* Reset the Backup domain only if the RTC Clock source selection is modified */
00298     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
00299     {
00300       /* Store the content of BDCR register before the reset of Backup Domain */
00301       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
00302       /* RTC Clock selection can be changed only if the Backup Domain is reset */
00303       __HAL_RCC_BACKUPRESET_FORCE();
00304       __HAL_RCC_BACKUPRESET_RELEASE();
00305       /* Restore the Content of BDCR register */
00306       RCC->BDCR = tmpreg1;
00307
00308       /* Wait for LSERDY if LSE was enabled */
00309       if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
00310       {
00311         /* Get tick */
00312         tickstart = HAL_GetTick();
00313
00314         /* Wait till LSE is ready */
00315         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00316         {
00317           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00318           {
00319             return HAL_TIMEOUT;
00320           }
00321         }
00322       }
00323       __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00324     }
00325   }
00326   /*--------------------------------------------------------------------------*/
00327
00328   /*---------------------------- TIM configuration ---------------------------*/
00329   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
00330   {
00331     /* Configure Timer Prescaler */
00332     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
00333   }
00334   /*--------------------------------------------------------------------------*/
00335
00336   /*---------------------------- FMPI2C1 Configuration -----------------------*/
00337   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
00338   {
00339     /* Check the parameters */
00340     assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
00341
00342     /* Configure the FMPI2C1 clock source */
00343     __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
00344   }
00345   /*--------------------------------------------------------------------------*/
00346
00347   /*------------------------------ CEC Configuration -------------------------*/
00348   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
00349   {
00350     /* Check the parameters */
00351     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
00352
00353     /* Configure the CEC clock source */
00354     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
00355   }
00356   /*--------------------------------------------------------------------------*/
00357
00358   /*------------------------------ CK48 Configuration ------------------------*/
00359   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
00360   {
00361     /* Check the parameters */
00362     assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
00363
00364     /* Configure the CK48 clock source */
00365     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
00366
00367     /* Enable the PLLSAI when it's used as clock source for CK48 */
00368     if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
00369     {
00370       pllsaiused = 1U;
00371     }
00372   }
00373   /*--------------------------------------------------------------------------*/
00374
00375   /*----------------------------- SDIO Configuration -------------------------*/
00376   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
00377   {
00378     /* Check the parameters */
00379     assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
00380
00381     /* Configure the SDIO clock source */
00382     __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
00383   }
00384   /*--------------------------------------------------------------------------*/
00385
00386   /*------------------------------ SPDIFRX Configuration ---------------------*/
00387   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
00388   {
00389     /* Check the parameters */
00390     assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
00391
00392     /* Configure the SPDIFRX clock source */
00393     __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
00394     /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
00395     if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
00396     {
00397       plli2sused = 1U;
00398     }
00399   }
00400   /*--------------------------------------------------------------------------*/
00401
00402   /*---------------------------- PLLI2S Configuration ------------------------*/
00403   /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
00404      I2S on APB2 or SPDIFRX */
00405   if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
00406   {
00407     /* Disable the PLLI2S */
00408     __HAL_RCC_PLLI2S_DISABLE();
00409     /* Get tick */
00410     tickstart = HAL_GetTick();
00411     /* Wait till PLLI2S is disabled */
00412     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
00413     {
00414       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00415       {
00416         /* return in case of Timeout detected */
00417         return HAL_TIMEOUT;
00418       }
00419     }
00420
00421     /* check for common PLLI2S Parameters */
00422     assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
00423     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
00424
00425     /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
00426     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
00427        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
00428     {
00429       /* check for Parameters */
00430       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
00431
00432       /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
00433       plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
00434       plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
00435       /* Configure the PLLI2S division factors */
00436       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
00437       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
00438       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
00439     }
00440
00441     /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
00442     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
00443        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
00444     {
00445       /* Check for PLLI2S Parameters */
00446       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
00447       /* Check for PLLI2S/DIVQ parameters */
00448       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
00449
00450       /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
00451       plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
00452       plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
00453       /* Configure the PLLI2S division factors */
00454       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
00455       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
00456       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
00457       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
00458
00459       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
00460       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
00461     }
00462
00463     /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
00464     if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
00465     {
00466       /* check for Parameters */
00467       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
00468       /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
00469       plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
00470       plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
00471       /* Configure the PLLI2S division factors */
00472       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
00473       /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
00474       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
00475     }
00476
00477      /*----------------- In Case of PLLI2S is just selected  -----------------*/
00478     if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
00479     {
00480       /* Check for Parameters */
00481       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
00482       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
00483       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
00484
00485       /* Configure the PLLI2S division factors */
00486       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
00487       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
00488     }
00489
00490     /* Enable the PLLI2S */
00491     __HAL_RCC_PLLI2S_ENABLE();
00492     /* Get tick */
00493     tickstart = HAL_GetTick();
00494     /* Wait till PLLI2S is ready */
00495     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
00496     {
00497       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00498       {
00499         /* return in case of Timeout detected */
00500         return HAL_TIMEOUT;
00501       }
00502     }
00503   }
00504   /*--------------------------------------------------------------------------*/
00505
00506   /*----------------------------- PLLSAI Configuration -----------------------*/
00507   /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
00508   if(pllsaiused == 1U)
00509   {
00510     /* Disable PLLSAI Clock */
00511     __HAL_RCC_PLLSAI_DISABLE();
00512     /* Get tick */
00513     tickstart = HAL_GetTick();
00514     /* Wait till PLLSAI is disabled */
00515     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
00516     {
00517       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
00518       {
00519         /* return in case of Timeout detected */
00520         return HAL_TIMEOUT;
00521       }
00522     }
00523
00524     /* Check the PLLSAI division factors */
00525     assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
00526     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
00527
00528     /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
00529     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
00530        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
00531     {
00532       /* check for PLLSAIQ Parameter */
00533       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
00534       /* check for PLLSAI/DIVQ Parameter */
00535       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
00536
00537       /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
00538       pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
00539       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00540       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00541       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
00542       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
00543
00544       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
00545       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
00546     }
00547
00548     /*------ In Case of PLLSAI is selected as source clock for CK48 ----------*/
00549     /* In Case of PLLI2S is selected as source clock for CK48 */
00550     if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
00551     {
00552       /* check for Parameters */
00553       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
00554       /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
00555       pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
00556       /* Configure the PLLSAI division factors */
00557       /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
00558       /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
00559       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
00560     }
00561
00562     /* Enable PLLSAI Clock */
00563     __HAL_RCC_PLLSAI_ENABLE();
00564     /* Get tick */
00565     tickstart = HAL_GetTick();
00566     /* Wait till PLLSAI is ready */
00567     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
00568     {
00569       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
00570       {
00571         /* return in case of Timeout detected */
00572         return HAL_TIMEOUT;
00573       }
00574     }
00575   }
00576   return HAL_OK;
00577 }
00578
00579 /**
00580   * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
00581   *         RCC configuration registers.
00582   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
00583   *         will be configured.
00584   * @retval None
00585   */
00586 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00587 {
00588   uint32_t tempreg;
00589
00590   /* Set all possible values for the extended clock type parameter------------*/
00591   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
00592                                         RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
00593                                         RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
00594                                         RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_FMPI2C1  |\
00595                                         RCC_PERIPHCLK_CK48     | RCC_PERIPHCLK_SDIO     |\
00596                                         RCC_PERIPHCLK_SPDIFRX;
00597
00598   /* Get the PLLI2S Clock configuration --------------------------------------*/
00599   PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
00600   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
00601   PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
00602   PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
00603   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
00604   /* Get the PLLSAI Clock configuration --------------------------------------*/
00605   PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
00606   PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
00607   PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
00608   PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
00609   /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
00610   PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
00611   PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
00612
00613   /* Get the SAI1 clock configuration ----------------------------------------*/
00614   PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
00615
00616   /* Get the SAI2 clock configuration ----------------------------------------*/
00617   PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
00618
00619   /* Get the I2S APB1 clock configuration ------------------------------------*/
00620   PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
00621
00622   /* Get the I2S APB2 clock configuration ------------------------------------*/
00623   PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
00624
00625   /* Get the RTC Clock configuration -----------------------------------------*/
00626   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
00627   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
00628
00629   /* Get the CEC clock configuration -----------------------------------------*/
00630   PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
00631
00632   /* Get the FMPI2C1 clock configuration -------------------------------------*/
00633   PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
00634
00635   /* Get the CK48 clock configuration ----------------------------------------*/
00636   PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
00637
00638   /* Get the SDIO clock configuration ----------------------------------------*/
00639   PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
00640
00641   /* Get the SPDIFRX clock configuration -------------------------------------*/
00642   PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
00643
00644   /* Get the TIM Prescaler configuration -------------------------------------*/
00645   if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
00646   {
00647     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
00648   }
00649   else
00650   {
00651     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
00652   }
00653 }
00654
00655 /**
00656   * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
00657   * @note   Return 0 if peripheral clock identifier not managed by this API
00658   * @param  PeriphClk: Peripheral clock identifier
00659   *         This parameter can be one of the following values:
00660   *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
00661   *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
00662   * @retval Frequency in KHz
00663   */
00664 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00665 {
00666   uint32_t tmpreg1 = 0U;
00667   /* This variable used to store the SAI clock frequency (value in Hz) */
00668   uint32_t frequency = 0U;
00669   /* This variable used to store the VCO Input (value in Hz) */
00670   uint32_t vcoinput = 0U;
00671   /* This variable used to store the SAI clock source */
00672   uint32_t saiclocksource = 0U;
00673   if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
00674   {
00675     saiclocksource = RCC->DCKCFGR;
00676     saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
00677     switch (saiclocksource)
00678     {
00679     case 0U: /* PLLSAI is the clock source for SAI*/
00680       {
00681         /* Configure the PLLSAI division factor */
00682         /* PLLSAI_VCO Input  = PLL_SOURCE/PLLSAIM */
00683         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00684         {
00685           /* In Case the PLL Source is HSI (Internal Clock) */
00686           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
00687         }
00688         else
00689         {
00690           /* In Case the PLL Source is HSE (External Clock) */
00691           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
00692         }
00693         /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00694         /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
00695         tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
00696         frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
00697
00698         /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
00699         tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
00700         frequency = frequency/(tmpreg1);
00701         break;
00702       }
00703     case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
00704     case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
00705       {
00706         /* Configure the PLLI2S division factor */
00707         /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
00708         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00709         {
00710           /* In Case the PLL Source is HSI (Internal Clock) */
00711           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
00712         }
00713         else
00714         {
00715           /* In Case the PLL Source is HSE (External Clock) */
00716           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
00717         }
00718
00719         /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
00720         /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
00721         tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
00722         frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
00723
00724         /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
00725         tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
00726         frequency = frequency/(tmpreg1);
00727         break;
00728       }
00729     case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
00730     case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
00731       {
00732         /* Configure the PLLI2S division factor */
00733         /* PLL_VCO Input  = PLL_SOURCE/PLLM */
00734         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00735         {
00736           /* In Case the PLL Source is HSI (Internal Clock) */
00737           vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
00738         }
00739         else
00740         {
00741           /* In Case the PLL Source is HSE (External Clock) */
00742           vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
00743         }
00744
00745         /* PLL_VCO Output = PLL_VCO Input * PLLN */
00746         /* SAI_CLK_x = PLL_VCO Output/PLLR */
00747         tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
00748         frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
00749         break;
00750       }
00751     case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
00752       {
00753         frequency = EXTERNAL_CLOCK_VALUE;
00754         break;
00755       }
00756     case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
00757       {
00758         if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00759         {
00760           /* In Case the PLL Source is HSI (Internal Clock) */
00761           frequency = (uint32_t)(HSI_VALUE);
00762         }
00763         else
00764         {
00765           /* In Case the PLL Source is HSE (External Clock) */
00766           frequency = (uint32_t)(HSE_VALUE);
00767         }
00768         break;
00769       }
00770     default :
00771       {
00772         break;
00773       }
00774     }
00775   }
00776   return frequency;
00777 }
00778
00779 #endif /* STM32F446xx */
00780
00781 #if defined(STM32F469xx) || defined(STM32F479xx)
00782 /**
00783   * @brief  Initializes the RCC extended peripherals clocks according to the specified
00784   *         parameters in the RCC_PeriphCLKInitTypeDef.
00785   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
00786   *         contains the configuration information for the Extended Peripherals
00787   *         clocks(I2S, SAI, LTDC, RTC and TIM).
00788   *
00789   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00790   *         the RTC clock source; in this case the Backup domain will be reset in
00791   *         order to modify the RTC Clock source, as consequence RTC registers (including
00792   *         the backup registers) and RCC_BDCR register are set to their reset values.
00793   *
00794   * @retval HAL status
00795   */
00796 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00797 {
00798   uint32_t tickstart = 0U;
00799   uint32_t tmpreg1 = 0U;
00800   uint32_t pllsaip = 0U;
00801   uint32_t pllsaiq = 0U;
00802   uint32_t pllsair = 0U;
00803
00804   /* Check the parameters */
00805   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00806
00807   /*--------------------------- CLK48 Configuration --------------------------*/
00808   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
00809   {
00810     /* Check the parameters */
00811     assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
00812
00813     /* Configure the CLK48 clock source */
00814     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
00815   }
00816   /*--------------------------------------------------------------------------*/
00817
00818   /*------------------------------ SDIO Configuration ------------------------*/
00819   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
00820   {
00821     /* Check the parameters */
00822     assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
00823
00824     /* Configure the SDIO clock source */
00825     __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
00826   }
00827   /*--------------------------------------------------------------------------*/
00828
00829   /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
00830   /*------------------- Common configuration SAI/I2S -------------------------*/
00831   /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
00832      factor is common parameters for both peripherals */
00833   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
00834      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
00835      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
00836   {
00837     /* check for Parameters */
00838     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
00839
00840     /* Disable the PLLI2S */
00841     __HAL_RCC_PLLI2S_DISABLE();
00842     /* Get tick */
00843     tickstart = HAL_GetTick();
00844     /* Wait till PLLI2S is disabled */
00845     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
00846     {
00847       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00848       {
00849         /* return in case of Timeout detected */
00850         return HAL_TIMEOUT;
00851       }
00852     }
00853
00854     /*---------------------- I2S configuration -------------------------------*/
00855     /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
00856       only for I2S configuration */
00857     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
00858     {
00859       /* check for Parameters */
00860       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
00861       /* Configure the PLLI2S division factors */
00862       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
00863       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
00864       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
00865     }
00866
00867     /*---------------------------- SAI configuration -------------------------*/
00868     /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
00869        be added only for SAI configuration */
00870     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
00871     {
00872       /* Check the PLLI2S division factors */
00873       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
00874       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
00875
00876       /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
00877       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
00878       /* Configure the PLLI2S division factors */
00879       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
00880       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
00881       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
00882       __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
00883       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
00884       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
00885     }
00886
00887     /*----------------- In Case of PLLI2S is just selected  -----------------*/
00888     if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
00889     {
00890       /* Check for Parameters */
00891       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
00892       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
00893
00894       /* Configure the PLLI2S multiplication and division factors */
00895       __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
00896     }
00897
00898     /* Enable the PLLI2S */
00899     __HAL_RCC_PLLI2S_ENABLE();
00900     /* Get tick */
00901     tickstart = HAL_GetTick();
00902     /* Wait till PLLI2S is ready */
00903     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
00904     {
00905       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00906       {
00907         /* return in case of Timeout detected */
00908         return HAL_TIMEOUT;
00909       }
00910     }
00911   }
00912   /*--------------------------------------------------------------------------*/
00913
00914   /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
00915   /*----------------------- Common configuration SAI/LTDC --------------------*/
00916   /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
00917      factor is common parameters for these peripherals */
00918   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
00919      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)             ||
00920      ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)            &&
00921       (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)))
00922   {
00923     /* Check the PLLSAI division factors */
00924     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
00925
00926     /* Disable PLLSAI Clock */
00927     __HAL_RCC_PLLSAI_DISABLE();
00928     /* Get tick */
00929     tickstart = HAL_GetTick();
00930     /* Wait till PLLSAI is disabled */
00931     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
00932     {
00933       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
00934       {
00935         /* return in case of Timeout detected */
00936         return HAL_TIMEOUT;
00937       }
00938     }
00939
00940     /*---------------------------- SAI configuration -------------------------*/
00941     /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
00942        be added only for SAI configuration */
00943     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
00944     {
00945       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
00946       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
00947
00948       /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
00949       pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
00950       /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
00951       pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
00952       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00953       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00954       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
00955       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
00956       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
00957       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
00958     }
00959
00960     /*---------------------------- LTDC configuration ------------------------*/
00961     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
00962     {
00963       assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
00964       assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
00965
00966       /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
00967       pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
00968       /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
00969       pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
00970       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00971       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00972       /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
00973       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
00974       /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
00975       __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
00976     }
00977
00978     /*---------------------------- CLK48 configuration ------------------------*/
00979     /* Configure the PLLSAI when it is used as clock source for CLK48 */
00980     if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == (RCC_PERIPHCLK_CK48)) &&
00981        (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
00982     {
00983       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
00984
00985       /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
00986       pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
00987       /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
00988       pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
00989       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00990       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00991       /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
00992       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
00993     }
00994
00995     /* Enable PLLSAI Clock */
00996     __HAL_RCC_PLLSAI_ENABLE();
00997     /* Get tick */
00998     tickstart = HAL_GetTick();
00999     /* Wait till PLLSAI is ready */
01000     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
01001     {
01002       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
01003       {
01004         /* return in case of Timeout detected */
01005         return HAL_TIMEOUT;
01006       }
01007     }
01008   }
01009
01010   /*--------------------------------------------------------------------------*/
01011
01012   /*---------------------------- RTC configuration ---------------------------*/
01013   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
01014   {
01015     /* Enable Power Clock*/
01016     __HAL_RCC_PWR_CLK_ENABLE();
01017
01018     /* Enable write access to Backup domain */
01019     PWR->CR |= PWR_CR_DBP;
01020
01021     /* Get tick */
01022     tickstart = HAL_GetTick();
01023
01024     while((PWR->CR & PWR_CR_DBP) == RESET)
01025     {
01026       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
01027       {
01028         return HAL_TIMEOUT;
01029       }
01030     }
01031     /* Reset the Backup domain only if the RTC Clock source selection is modified */
01032     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
01033     {
01034       /* Store the content of BDCR register before the reset of Backup Domain */
01035       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
01036       /* RTC Clock selection can be changed only if the Backup Domain is reset */
01037       __HAL_RCC_BACKUPRESET_FORCE();
01038       __HAL_RCC_BACKUPRESET_RELEASE();
01039       /* Restore the Content of BDCR register */
01040       RCC->BDCR = tmpreg1;
01041
01042       /* Wait for LSERDY if LSE was enabled */
01043       if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
01044       {
01045         /* Get tick */
01046         tickstart = HAL_GetTick();
01047
01048         /* Wait till LSE is ready */
01049         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
01050         {
01051           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
01052           {
01053             return HAL_TIMEOUT;
01054           }
01055         }
01056       }
01057       __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
01058     }
01059   }
01060   /*--------------------------------------------------------------------------*/
01061
01062   /*---------------------------- TIM configuration ---------------------------*/
01063   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
01064   {
01065     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
01066   }
01067   return HAL_OK;
01068 }
01069
01070 /**
01071   * @brief  Configures the RCC_PeriphCLKInitTypeDef according to the internal
01072   * RCC configuration registers.
01073   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01074   *         will be configured.
01075   * @retval None
01076   */
01077 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01078 {
01079   uint32_t tempreg;
01080
01081   /* Set all possible values for the extended clock type parameter------------*/
01082   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S        | RCC_PERIPHCLK_SAI_PLLSAI |\
01083                                         RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC       |\
01084                                         RCC_PERIPHCLK_TIM        | RCC_PERIPHCLK_RTC        |\
01085                                         RCC_PERIPHCLK_CK48       | RCC_PERIPHCLK_SDIO;
01086
01087   /* Get the PLLI2S Clock configuration --------------------------------------*/
01088   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
01089   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
01090   PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
01091   /* Get the PLLSAI Clock configuration --------------------------------------*/
01092   PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
01093   PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
01094   PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
01095   /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
01096   PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
01097   PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
01098   PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
01099   /* Get the RTC Clock configuration -----------------------------------------*/
01100   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
01101   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
01102
01103     /* Get the CK48 clock configuration --------------------------------------*/
01104   PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
01105
01106   /* Get the SDIO clock configuration ----------------------------------------*/
01107   PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
01108
01109   if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
01110   {
01111     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
01112   }
01113   else
01114   {
01115     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
01116   }
01117 }
01118 #endif /* STM32F469xx || STM32F479xx */
01119
01120 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
01121 /**
01122   * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
01123   *         RCC_PeriphCLKInitTypeDef.
01124   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01125   *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
01126   *
01127   * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
01128   *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
01129   *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
01130   *
01131   * @retval HAL status
01132   */
01133 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01134 {
01135   uint32_t tickstart = 0U;
01136   uint32_t tmpreg1 = 0U;
01137
01138   /* Check the parameters */
01139   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
01140
01141   /*---------------------------- RTC configuration ---------------------------*/
01142   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
01143   {
01144     /* Enable Power Clock*/
01145     __HAL_RCC_PWR_CLK_ENABLE();
01146
01147     /* Enable write access to Backup domain */
01148     PWR->CR |= PWR_CR_DBP;
01149
01150     /* Get tick */
01151     tickstart = HAL_GetTick();
01152
01153     while((PWR->CR & PWR_CR_DBP) == RESET)
01154     {
01155       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
01156       {
01157         return HAL_TIMEOUT;
01158       }
01159     }
01160     /* Reset the Backup domain only if the RTC Clock source selection is modified */
01161     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
01162     {
01163       /* Store the content of BDCR register before the reset of Backup Domain */
01164       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
01165       /* RTC Clock selection can be changed only if the Backup Domain is reset */
01166       __HAL_RCC_BACKUPRESET_FORCE();
01167       __HAL_RCC_BACKUPRESET_RELEASE();
01168       /* Restore the Content of BDCR register */
01169       RCC->BDCR = tmpreg1;
01170
01171       /* Wait for LSERDY if LSE was enabled */
01172       if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
01173       {
01174         /* Get tick */
01175         tickstart = HAL_GetTick();
01176
01177         /* Wait till LSE is ready */
01178         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
01179         {
01180           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
01181           {
01182             return HAL_TIMEOUT;
01183           }
01184         }
01185       }
01186       __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
01187     }
01188   }
01189   /*--------------------------------------------------------------------------*/
01190
01191   /*---------------------------- TIM configuration ---------------------------*/
01192   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
01193   {
01194     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
01195   }
01196   /*--------------------------------------------------------------------------*/
01197
01198   /*---------------------------- FMPI2C1 Configuration -----------------------*/
01199   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
01200   {
01201     /* Check the parameters */
01202     assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
01203
01204     /* Configure the FMPI2C1 clock source */
01205     __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
01206   }
01207   /*--------------------------------------------------------------------------*/
01208
01209   /*---------------------------- LPTIM1 Configuration ------------------------*/
01210   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
01211   {
01212     /* Check the parameters */
01213     assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
01214
01215     /* Configure the LPTIM1 clock source */
01216     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
01217   }
01218
01219   /*---------------------------- I2S Configuration ------------------------*/
01220   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
01221   {
01222     /* Check the parameters */
01223     assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
01224
01225     /* Configure the I2S clock source */
01226     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
01227   }
01228
01229   return HAL_OK;
01230 }
01231
01232 /**
01233   * @brief  Configures the RCC_OscInitStruct according to the internal
01234   * RCC configuration registers.
01235   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01236   * will be configured.
01237   * @retval None
01238   */
01239 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01240 {
01241   uint32_t tempreg;
01242
01243   /* Set all possible values for the extended clock type parameter------------*/
01244   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
01245
01246   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
01247   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
01248
01249   if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
01250   {
01251     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
01252   }
01253   else
01254   {
01255     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
01256   }
01257   /* Get the FMPI2C1 clock configuration -------------------------------------*/
01258   PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
01259
01260   /* Get the I2S clock configuration -----------------------------------------*/
01261   PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
01262
01263
01264 }
01265 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
01266
01267 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
01268 /**
01269   * @brief  Initializes the RCC extended peripherals clocks according to the specified
01270   *         parameters in the RCC_PeriphCLKInitTypeDef.
01271   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01272   *         contains the configuration information for the Extended Peripherals
01273   *         clocks(I2S, SAI, LTDC RTC and TIM).
01274   *
01275   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
01276   *         the RTC clock source; in this case the Backup domain will be reset in
01277   *         order to modify the RTC Clock source, as consequence RTC registers (including
01278   *         the backup registers) and RCC_BDCR register are set to their reset values.
01279   *
01280   * @retval HAL status
01281   */
01282 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01283 {
01284   uint32_t tickstart = 0U;
01285   uint32_t tmpreg1 = 0U;
01286
01287   /* Check the parameters */
01288   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
01289
01290   /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
01291   /*----------------------- Common configuration SAI/I2S ----------------------*/
01292   /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
01293      factor is common parameters for both peripherals */
01294   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
01295      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
01296   {
01297     /* check for Parameters */
01298     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
01299
01300     /* Disable the PLLI2S */
01301     __HAL_RCC_PLLI2S_DISABLE();
01302     /* Get tick */
01303     tickstart = HAL_GetTick();
01304     /* Wait till PLLI2S is disabled */
01305     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
01306     {
01307       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
01308       {
01309         /* return in case of Timeout detected */
01310         return HAL_TIMEOUT;
01311       }
01312     }
01313
01314     /*---------------------------- I2S configuration -------------------------------*/
01315     /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
01316       only for I2S configuration */
01317     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
01318     {
01319       /* check for Parameters */
01320       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
01321       /* Configure the PLLI2S division factors */
01322       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
01323       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
01324       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
01325     }
01326
01327     /*---------------------------- SAI configuration -------------------------------*/
01328     /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
01329        be added only for SAI configuration */
01330     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
01331     {
01332       /* Check the PLLI2S division factors */
01333       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
01334       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
01335
01336       /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
01337       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
01338       /* Configure the PLLI2S division factors */
01339       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
01340       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
01341       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
01342       __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
01343       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
01344       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
01345     }
01346
01347     /* Enable the PLLI2S */
01348     __HAL_RCC_PLLI2S_ENABLE();
01349     /* Get tick */
01350     tickstart = HAL_GetTick();
01351     /* Wait till PLLI2S is ready */
01352     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
01353     {
01354       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
01355       {
01356         /* return in case of Timeout detected */
01357         return HAL_TIMEOUT;
01358       }
01359     }
01360   }
01361   /*--------------------------------------------------------------------------*/
01362
01363   /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
01364   /*----------------------- Common configuration SAI/LTDC --------------------*/
01365   /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
01366      factor is common parameters for both peripherals */
01367   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
01368      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
01369   {
01370     /* Check the PLLSAI division factors */
01371     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
01372
01373     /* Disable PLLSAI Clock */
01374     __HAL_RCC_PLLSAI_DISABLE();
01375     /* Get tick */
01376     tickstart = HAL_GetTick();
01377     /* Wait till PLLSAI is disabled */
01378     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
01379     {
01380       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
01381       {
01382         /* return in case of Timeout detected */
01383         return HAL_TIMEOUT;
01384       }
01385     }
01386
01387     /*---------------------------- SAI configuration -------------------------*/
01388     /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
01389        be added only for SAI configuration */
01390     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
01391     {
01392       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
01393       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
01394
01395       /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
01396       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
01397       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
01398       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
01399       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
01400       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
01401       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
01402       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
01403     }
01404
01405     /*---------------------------- LTDC configuration ------------------------*/
01406     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
01407     {
01408       assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
01409       assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
01410
01411       /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
01412       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
01413       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
01414       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
01415       /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
01416       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
01417       /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
01418       __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
01419     }
01420     /* Enable PLLSAI Clock */
01421     __HAL_RCC_PLLSAI_ENABLE();
01422     /* Get tick */
01423     tickstart = HAL_GetTick();
01424     /* Wait till PLLSAI is ready */
01425     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
01426     {
01427       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
01428       {
01429         /* return in case of Timeout detected */
01430         return HAL_TIMEOUT;
01431       }
01432     }
01433   }
01434   /*--------------------------------------------------------------------------*/
01435
01436   /*---------------------------- RTC configuration ---------------------------*/
01437   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
01438   {
01439     /* Enable Power Clock*/
01440     __HAL_RCC_PWR_CLK_ENABLE();
01441
01442     /* Enable write access to Backup domain */
01443     PWR->CR |= PWR_CR_DBP;
01444
01445     /* Get tick */
01446     tickstart = HAL_GetTick();
01447
01448     while((PWR->CR & PWR_CR_DBP) == RESET)
01449     {
01450       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
01451       {
01452         return HAL_TIMEOUT;
01453       }
01454     }
01455
01456     /* Reset the Backup domain only if the RTC Clock source selection is modified */
01457     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
01458     {
01459
01460       /* Store the content of BDCR register before the reset of Backup Domain */
01461       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
01462       /* RTC Clock selection can be changed only if the Backup Domain is reset */
01463       __HAL_RCC_BACKUPRESET_FORCE();
01464       __HAL_RCC_BACKUPRESET_RELEASE();
01465       /* Restore the Content of BDCR register */
01466       RCC->BDCR = tmpreg1;
01467
01468       /* Wait for LSERDY if LSE was enabled */
01469       if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
01470       {
01471         /* Get tick */
01472         tickstart = HAL_GetTick();
01473
01474         /* Wait till LSE is ready */
01475         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
01476         {
01477           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
01478           {
01479             return HAL_TIMEOUT;
01480           }
01481         }
01482       }
01483       __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
01484     }
01485   }
01486   /*--------------------------------------------------------------------------*/
01487
01488   /*---------------------------- TIM configuration ---------------------------*/
01489   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
01490   {
01491     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
01492   }
01493   return HAL_OK;
01494 }
01495
01496 /**
01497   * @brief  Configures the PeriphClkInit according to the internal
01498   * RCC configuration registers.
01499   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01500   *         will be configured.
01501   * @retval None
01502   */
01503 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01504 {
01505   uint32_t tempreg;
01506
01507   /* Set all possible values for the extended clock type parameter------------*/
01508   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
01509
01510   /* Get the PLLI2S Clock configuration -----------------------------------------------*/
01511   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
01512   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
01513   PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
01514   /* Get the PLLSAI Clock configuration -----------------------------------------------*/
01515   PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
01516   PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
01517   PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
01518   /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
01519   PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
01520   PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
01521   PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
01522   /* Get the RTC Clock configuration -----------------------------------------------*/
01523   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
01524   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
01525
01526   if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
01527   {
01528     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
01529   }
01530   else
01531   {
01532     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
01533   }
01534 }
01535
01536 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
01537
01538 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
01539     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
01540 /**
01541   * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
01542   *         RCC_PeriphCLKInitTypeDef.
01543   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01544   *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
01545   *
01546   * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
01547   *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
01548   *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
01549   *
01550   * @retval HAL status
01551   */
01552 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01553 {
01554   uint32_t tickstart = 0U;
01555   uint32_t tmpreg1 = 0U;
01556
01557   /* Check the parameters */
01558   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
01559
01560   /*---------------------------- I2S configuration ---------------------------*/
01561   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
01562   {
01563     /* check for Parameters */
01564     assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
01565     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
01566 #if defined(STM32F411xE)
01567     assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
01568 #endif /* STM32F411xE */
01569     /* Disable the PLLI2S */
01570     __HAL_RCC_PLLI2S_DISABLE();
01571     /* Get tick */
01572     tickstart = HAL_GetTick();
01573     /* Wait till PLLI2S is disabled */
01574     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
01575     {
01576       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
01577       {
01578         /* return in case of Timeout detected */
01579         return HAL_TIMEOUT;
01580       }
01581     }
01582
01583 #if defined(STM32F411xE)
01584     /* Configure the PLLI2S division factors */
01585     /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
01586     /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
01587     __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
01588 #else
01589     /* Configure the PLLI2S division factors */
01590     /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
01591     /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
01592     __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
01593 #endif /* STM32F411xE */
01594
01595     /* Enable the PLLI2S */
01596     __HAL_RCC_PLLI2S_ENABLE();
01597     /* Get tick */
01598     tickstart = HAL_GetTick();
01599     /* Wait till PLLI2S is ready */
01600     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
01601     {
01602       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
01603       {
01604         /* return in case of Timeout detected */
01605         return HAL_TIMEOUT;
01606       }
01607     }
01608   }
01609
01610   /*---------------------------- RTC configuration ---------------------------*/
01611   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
01612   {
01613     /* Enable Power Clock*/
01614     __HAL_RCC_PWR_CLK_ENABLE();
01615
01616     /* Enable write access to Backup domain */
01617     PWR->CR |= PWR_CR_DBP;
01618
01619     /* Get tick */
01620     tickstart = HAL_GetTick();
01621
01622     while((PWR->CR & PWR_CR_DBP) == RESET)
01623     {
01624       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
01625       {
01626         return HAL_TIMEOUT;
01627       }
01628     }
01629     /* Reset the Backup domain only if the RTC Clock source selection is modified */
01630     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
01631     {
01632       /* Store the content of BDCR register before the reset of Backup Domain */
01633       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
01634       /* RTC Clock selection can be changed only if the Backup Domain is reset */
01635       __HAL_RCC_BACKUPRESET_FORCE();
01636       __HAL_RCC_BACKUPRESET_RELEASE();
01637       /* Restore the Content of BDCR register */
01638       RCC->BDCR = tmpreg1;
01639
01640       /* Wait for LSERDY if LSE was enabled */
01641       if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
01642       {
01643         /* Get tick */
01644         tickstart = HAL_GetTick();
01645
01646         /* Wait till LSE is ready */
01647         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
01648         {
01649           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
01650           {
01651             return HAL_TIMEOUT;
01652           }
01653         }
01654       }
01655       __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
01656     }
01657   }
01658
01659   return HAL_OK;
01660 }
01661
01662 /**
01663   * @brief  Configures the RCC_OscInitStruct according to the internal
01664   * RCC configuration registers.
01665   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
01666   * will be configured.
01667   * @retval None
01668   */
01669 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
01670 {
01671   uint32_t tempreg;
01672
01673   /* Set all possible values for the extended clock type parameter------------*/
01674   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
01675
01676   /* Get the PLLI2S Clock configuration --------------------------------------*/
01677   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
01678   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
01679 #if defined(STM32F411xE)
01680   PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
01681 #endif /* STM32F411xE */
01682   /* Get the RTC Clock configuration -----------------------------------------*/
01683   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
01684   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
01685
01686 }
01687 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE  || STM32F411xE */
01688
01689 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
01690 /**
01691   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
01692   *         RCC_OscInitTypeDef.
01693   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
01694   *         contains the configuration information for the RCC Oscillators.
01695   * @note   The PLL is not disabled when used as system clock.
01696   * @note   This function add the PLL/PLLR factor management during PLL configuration this feature
01697   *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices
01698   * @retval HAL status
01699   */
01700 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01701 {
01702   uint32_t tickstart = 0U;
01703
01704   /* Check the parameters */
01705   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
01706   /*------------------------------- HSE Configuration ------------------------*/
01707   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
01708   {
01709     /* Check the parameters */
01710     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
01711     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
01712 #if defined(STM32F446xx)
01713     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
01714       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
01715       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
01716 #else
01717     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
01718       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
01719 #endif /* STM32F446xx */
01720     {
01721       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
01722       {
01723         return HAL_ERROR;
01724       }
01725     }
01726     else
01727     {
01728       /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
01729       __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
01730
01731       /* Get Start Tick*/
01732       tickstart = HAL_GetTick();
01733
01734       /* Wait till HSE is disabled */
01735       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
01736       {
01737         if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
01738         {
01739           return HAL_TIMEOUT;
01740         }
01741       }
01742
01743       /* Set the new HSE configuration ---------------------------------------*/
01744       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
01745
01746       /* Check the HSE State */
01747       if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
01748       {
01749         /* Get Start Tick*/
01750         tickstart = HAL_GetTick();
01751
01752         /* Wait till HSE is ready */
01753         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
01754         {
01755           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
01756           {
01757             return HAL_TIMEOUT;
01758           }
01759         }
01760       }
01761       else
01762       {
01763         /* Get Start Tick*/
01764         tickstart = HAL_GetTick();
01765
01766         /* Wait till HSE is bypassed or disabled */
01767         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
01768         {
01769           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
01770           {
01771             return HAL_TIMEOUT;
01772           }
01773         }
01774       }
01775     }
01776   }
01777   /*----------------------------- HSI Configuration --------------------------*/
01778   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
01779   {
01780     /* Check the parameters */
01781     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
01782     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
01783
01784     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
01785 #if defined(STM32F446xx)
01786     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
01787       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
01788       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
01789 #else
01790     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
01791       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
01792 #endif /* STM32F446xx */
01793     {
01794       /* When HSI is used as system clock it will not disabled */
01795       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
01796       {
01797         return HAL_ERROR;
01798       }
01799       /* Otherwise, just the calibration is allowed */
01800       else
01801       {
01802         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
01803         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
01804       }
01805     }
01806     else
01807     {
01808       /* Check the HSI State */
01809       if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
01810       {
01811         /* Enable the Internal High Speed oscillator (HSI). */
01812         __HAL_RCC_HSI_ENABLE();
01813
01814         /* Get Start Tick*/
01815         tickstart = HAL_GetTick();
01816
01817         /* Wait till HSI is ready */
01818         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
01819         {
01820           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
01821           {
01822             return HAL_TIMEOUT;
01823           }
01824         }
01825
01826         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
01827         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
01828       }
01829       else
01830       {
01831         /* Disable the Internal High Speed oscillator (HSI). */
01832         __HAL_RCC_HSI_DISABLE();
01833
01834         /* Get Start Tick*/
01835         tickstart = HAL_GetTick();
01836
01837         /* Wait till HSI is ready */
01838         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
01839         {
01840           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
01841           {
01842             return HAL_TIMEOUT;
01843           }
01844         }
01845       }
01846     }
01847   }
01848   /*------------------------------ LSI Configuration -------------------------*/
01849   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
01850   {
01851     /* Check the parameters */
01852     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
01853
01854     /* Check the LSI State */
01855     if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
01856     {
01857       /* Enable the Internal Low Speed oscillator (LSI). */
01858       __HAL_RCC_LSI_ENABLE();
01859
01860       /* Get Start Tick*/
01861       tickstart = HAL_GetTick();
01862
01863       /* Wait till LSI is ready */
01864       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
01865       {
01866         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
01867         {
01868           return HAL_TIMEOUT;
01869         }
01870       }
01871     }
01872     else
01873     {
01874       /* Disable the Internal Low Speed oscillator (LSI). */
01875       __HAL_RCC_LSI_DISABLE();
01876
01877       /* Get Start Tick*/
01878       tickstart = HAL_GetTick();
01879
01880       /* Wait till LSI is ready */
01881       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
01882       {
01883         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
01884         {
01885           return HAL_TIMEOUT;
01886         }
01887       }
01888     }
01889   }
01890   /*------------------------------ LSE Configuration -------------------------*/
01891   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
01892   {
01893     /* Check the parameters */
01894     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
01895
01896     /* Enable Power Clock*/
01897     __HAL_RCC_PWR_CLK_ENABLE();
01898
01899     /* Enable write access to Backup domain */
01900     PWR->CR |= PWR_CR_DBP;
01901
01902     /* Wait for Backup domain Write protection disable */
01903     tickstart = HAL_GetTick();
01904
01905     while((PWR->CR & PWR_CR_DBP) == RESET)
01906     {
01907       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
01908       {
01909         return HAL_TIMEOUT;
01910       }
01911     }
01912
01913     /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
01914     __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
01915
01916     /* Get Start Tick*/
01917     tickstart = HAL_GetTick();
01918
01919     /* Wait till LSE is ready */
01920     while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
01921     {
01922       if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
01923       {
01924         return HAL_TIMEOUT;
01925       }
01926     }
01927
01928     /* Set the new LSE configuration -----------------------------------------*/
01929     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
01930     /* Check the LSE State */
01931     if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
01932     {
01933       /* Get Start Tick*/
01934       tickstart = HAL_GetTick();
01935
01936       /* Wait till LSE is ready */
01937       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
01938       {
01939         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
01940         {
01941           return HAL_TIMEOUT;
01942         }
01943       }
01944     }
01945     else
01946     {
01947       /* Get Start Tick*/
01948       tickstart = HAL_GetTick();
01949
01950       /* Wait till LSE is ready */
01951       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
01952       {
01953         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
01954         {
01955           return HAL_TIMEOUT;
01956         }
01957       }
01958     }
01959   }
01960   /*-------------------------------- PLL Configuration -----------------------*/
01961   /* Check the parameters */
01962   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
01963   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
01964   {
01965     /* Check if the PLL is used as system clock or not */
01966     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
01967     {
01968       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
01969       {
01970         /* Check the parameters */
01971         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
01972         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
01973         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
01974         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
01975         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
01976         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
01977
01978         /* Disable the main PLL. */
01979         __HAL_RCC_PLL_DISABLE();
01980
01981         /* Get Start Tick*/
01982         tickstart = HAL_GetTick();
01983
01984         /* Wait till PLL is ready */
01985         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
01986         {
01987           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
01988           {
01989             return HAL_TIMEOUT;
01990           }
01991         }
01992
01993         /* Configure the main PLL clock source, multiplication and division factors. */
01994         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
01995                              RCC_OscInitStruct->PLL.PLLM,
01996                              RCC_OscInitStruct->PLL.PLLN,
01997                              RCC_OscInitStruct->PLL.PLLP,
01998                              RCC_OscInitStruct->PLL.PLLQ,
01999                              RCC_OscInitStruct->PLL.PLLR);
02000
02001         /* Enable the main PLL. */
02002         __HAL_RCC_PLL_ENABLE();
02003
02004         /* Get Start Tick*/
02005         tickstart = HAL_GetTick();
02006
02007         /* Wait till PLL is ready */
02008         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
02009         {
02010           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
02011           {
02012             return HAL_TIMEOUT;
02013           }
02014         }
02015       }
02016       else
02017       {
02018         /* Disable the main PLL. */
02019         __HAL_RCC_PLL_DISABLE();
02020
02021         /* Get Start Tick*/
02022         tickstart = HAL_GetTick();
02023
02024         /* Wait till PLL is ready */
02025         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
02026         {
02027           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
02028           {
02029             return HAL_TIMEOUT;
02030           }
02031         }
02032       }
02033     }
02034     else
02035     {
02036       return HAL_ERROR;
02037     }
02038   }
02039   return HAL_OK;
02040 }
02041
02042 /**
02043   * @brief  Configures the RCC_OscInitStruct according to the internal
02044   * RCC configuration registers.
02045   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
02046   *
02047   * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
02048   * @note   This function add the PLL/PLLR factor management
02049   * @retval None
02050   */
02051 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
02052 {
02053   /* Set all possible values for the Oscillator type parameter ---------------*/
02054   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
02055
02056   /* Get the HSE configuration -----------------------------------------------*/
02057   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
02058   {
02059     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
02060   }
02061   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
02062   {
02063     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
02064   }
02065   else
02066   {
02067     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
02068   }
02069
02070   /* Get the HSI configuration -----------------------------------------------*/
02071   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
02072   {
02073     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
02074   }
02075   else
02076   {
02077     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
02078   }
02079
02080   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
02081
02082   /* Get the LSE configuration -----------------------------------------------*/
02083   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
02084   {
02085     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
02086   }
02087   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
02088   {
02089     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
02090   }
02091   else
02092   {
02093     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
02094   }
02095
02096   /* Get the LSI configuration -----------------------------------------------*/
02097   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
02098   {
02099     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
02100   }
02101   else
02102   {
02103     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
02104   }
02105
02106   /* Get the PLL configuration -----------------------------------------------*/
02107   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
02108   {
02109     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
02110   }
02111   else
02112   {
02113     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
02114   }
02115   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
02116   RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
02117   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
02118   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
02119   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
02120   RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
02121 }
02122 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
02123
02124 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
02125 /**
02126   * @brief  Select LSE mode
02127   *
02128   * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
02129   *
02130   * @param  Mode: specifies the LSE mode.
02131   *          This parameter can be one of the following values:
02132   *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode selection
02133   *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
02134   * @retval None
02135   */
02136 void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
02137 {
02138   /* Check the parameters */
02139   assert_param(IS_RCC_LSE_MODE(Mode));
02140   if(Mode == RCC_LSE_HIGHDRIVE_MODE)
02141   {
02142     SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
02143   }
02144   else
02145   {
02146     CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
02147   }
02148 }
02149
02150 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
02151
02152 #if defined(STM32F446xx)
02153 /**
02154   * @brief  Returns the SYSCLK frequency
02155   *
02156   * @note   This function implementation is valid only for STM32F446xx devices.
02157   * @note   This function add the PLL/PLLR System clock source
02158   *
02159   * @note   The system frequency computed by this function is not the real
02160   *         frequency in the chip. It is calculated based on the predefined
02161   *         constant and the selected clock source:
02162   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
02163   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
02164   * @note     If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
02165   *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
02166   * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
02167   *               16 MHz) but the real value may vary depending on the variations
02168   *               in voltage and temperature.
02169   * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
02170   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
02171   *                frequency of the crystal used. Otherwise, this function may
02172   *                have wrong result.
02173   *
02174   * @note   The result of this function could be not correct when using fractional
02175   *         value for HSE crystal.
02176   *
02177   * @note   This function can be used by the user application to compute the
02178   *         baudrate for the communication peripherals or configure other parameters.
02179   *
02180   * @note   Each time SYSCLK changes, this function must be called to update the
02181   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
02182   *
02183   *
02184   * @retval SYSCLK frequency
02185   */
02186 uint32_t HAL_RCC_GetSysClockFreq(void)
02187 {
02188   uint32_t pllm = 0U;
02189   uint32_t pllvco = 0U;
02190   uint32_t pllp = 0U;
02191   uint32_t pllr = 0U;
02192   uint32_t sysclockfreq = 0U;
02193
02194   /* Get SYSCLK source -------------------------------------------------------*/
02195   switch (RCC->CFGR & RCC_CFGR_SWS)
02196   {
02197     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
02198     {
02199       sysclockfreq = HSI_VALUE;
02200        break;
02201     }
02202     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
02203     {
02204       sysclockfreq = HSE_VALUE;
02205       break;
02206     }
02207     case RCC_CFGR_SWS_PLL:  /* PLL/PLLP used as system clock  source */
02208     {
02209       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
02210       SYSCLK = PLL_VCO / PLLP */
02211       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
02212       if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
02213       {
02214         /* HSE used as PLL clock source */
02215         pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
02216       }
02217       else
02218       {
02219         /* HSI used as PLL clock source */
02220         pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
02221       }
02222       pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
02223
02224       sysclockfreq = pllvco/pllp;
02225       break;
02226     }
02227     case RCC_CFGR_SWS_PLLR:  /* PLL/PLLR used as system clock  source */
02228     {
02229       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
02230       SYSCLK = PLL_VCO / PLLR */
02231       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
02232       if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
02233       {
02234         /* HSE used as PLL clock source */
02235         pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
02236       }
02237       else
02238       {
02239         /* HSI used as PLL clock source */
02240         pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
02241       }
02242       pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
02243
02244       sysclockfreq = pllvco/pllr;
02245       break;
02246     }
02247     default:
02248     {
02249       sysclockfreq = HSI_VALUE;
02250       break;
02251     }
02252   }
02253   return sysclockfreq;
02254 }
02255 #endif /* STM32F446xx */
02256
02257 /**
02258   * @}
02259   */
02260
02261 /**
02262   * @}
02263   */
02264
02265 #endif /* HAL_RCC_MODULE_ENABLED */
02266 /**
02267   * @}
02268   */
02269
02270 /**
02271   * @}
02272   */
02273
02274 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rcc_ex.h Source File

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stm32f4xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of RCC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_RCC_EX_H
00040 #define __STM32F4xx_HAL_RCC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  RCC PLL configuration structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t PLLState;   /*!< The new state of the PLL.
00068                             This parameter can be a value of @ref RCC_PLL_Config                      */
00069
00070   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00071                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00072
00073   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00074                             This parameter must be a number between Min_Data = 0 and Max_Data = 63    */
00075
00076   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00077                             This parameter must be a number between Min_Data = 50 and Max_Data = 432
00078                             except for STM32F411xE devices where the Min_Data = 192 */
00079
00080   uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
00081                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
00082
00083   uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
00084                             This parameter must be a number between Min_Data = 4 and Max_Data = 15    */
00085 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
00086     defined(STM32F479xx)
00087   uint32_t PLLR;       /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
00088                             This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx and STM32F479xx devices.
00089                             This parameter must be a number between Min_Data = 2 and Max_Data = 7     */
00090 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
00091 }RCC_PLLInitTypeDef;
00092
00093 #if defined(STM32F446xx)
00094 /**
00095   * @brief  PLLI2S Clock structure definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
00100                             This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
00101
00102   uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
00103                             This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
00104
00105   uint32_t PLLI2SP;    /*!< Specifies division factor for SPDIFRX Clock.
00106                             This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider           */
00107
00108   uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
00109                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
00110                             This parameter will be used only when PLLI2S is selected as Clock Source SAI */
00111
00112   uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
00113                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
00114                             This parameter will be used only when PLLI2S is selected as Clock Source I2S */
00115 }RCC_PLLI2SInitTypeDef;
00116
00117 /**
00118   * @brief  PLLSAI Clock structure definition
00119   */
00120 typedef struct
00121 {
00122   uint32_t PLLSAIM;    /*!< Spcifies division factor for PLL VCO input clock.
00123                             This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
00124
00125   uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
00126                             This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
00127
00128   uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
00129                             This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider           */
00130
00131   uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI clock.
00132                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
00133                             This parameter will be used only when PLLSAI is selected as Clock Source SAI */
00134 }RCC_PLLSAIInitTypeDef;
00135
00136 /**
00137   * @brief  RCC extended clocks structure definition
00138   */
00139 typedef struct
00140 {
00141   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00142                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00143
00144   RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
00145                                       This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00146
00147   RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters.
00148                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
00149
00150   uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
00151                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
00152                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI */
00153
00154   uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
00155                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
00156                                       This parameter will be used only when PLLSAI is selected as Clock Source SAI */
00157
00158   uint32_t Sai1ClockSelection;    /*!< Specifies SAI1 Clock Source Selection.
00159                                       This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
00160
00161   uint32_t Sai2ClockSelection;    /*!< Specifies SAI2 Clock Source Selection.
00162                                       This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
00163
00164   uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection.
00165                                       This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
00166
00167   uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection.
00168                                       This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
00169
00170   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection.
00171                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00172
00173   uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection.
00174                                       This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
00175
00176   uint32_t CecClockSelection;      /*!< Specifies CEC Clock Source Selection.
00177                                       This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
00178
00179   uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection.
00180                                       This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
00181
00182   uint32_t SpdifClockSelection;    /*!< Specifies SPDIFRX Clock Source Selection.
00183                                       This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
00184
00185   uint32_t Clk48ClockSelection;     /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
00186                                       This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
00187
00188   uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection.
00189                                       This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
00190 }RCC_PeriphCLKInitTypeDef;
00191 #endif /* STM32F446xx */
00192
00193 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00194 /**
00195   * @brief  RCC extended clocks structure definition
00196   */
00197 typedef struct
00198 {
00199   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00200                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00201
00202   uint32_t I2SClockSelection;      /*!< Specifies RTC Clock Source Selection.
00203                                       This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
00204
00205   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection.
00206                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00207
00208   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection.
00209                                       This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
00210
00211   uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection.
00212                                       This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
00213   uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection.
00214                                       This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
00215 }RCC_PeriphCLKInitTypeDef;
00216 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00217
00218 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00219
00220 /**
00221   * @brief  PLLI2S Clock structure definition
00222   */
00223 typedef struct
00224 {
00225   uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
00226                             This parameter must be a number between Min_Data = 50 and Max_Data = 432.
00227                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00228
00229   uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
00230                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
00231                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00232
00233   uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
00234                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
00235                             This parameter will be used only when PLLI2S is selected as Clock Source SAI */
00236 }RCC_PLLI2SInitTypeDef;
00237
00238 /**
00239   * @brief  PLLSAI Clock structure definition
00240   */
00241 typedef struct
00242 {
00243   uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
00244                             This parameter must be a number between Min_Data = 50 and Max_Data = 432.
00245                             This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
00246 #if defined(STM32F469xx) || defined(STM32F479xx)
00247   uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS and SDIO clocks.
00248                             This parameter is only available in STM32F469xx/STM32F479xx devices.
00249                             This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider  */
00250 #endif /* STM32F469xx || STM32F479xx */
00251
00252   uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
00253                             This parameter must be a number between Min_Data = 2 and Max_Data = 15.
00254                             This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
00255
00256   uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
00257                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
00258                             This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
00259
00260 }RCC_PLLSAIInitTypeDef;
00261
00262 /**
00263   * @brief  RCC extended clocks structure definition
00264   */
00265 typedef struct
00266 {
00267   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00268                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00269
00270   RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
00271                                       This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00272
00273   RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters.
00274                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
00275
00276   uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
00277                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
00278                                       This parameter will be used only when PLLI2S is selected as Clock Source SAI */
00279
00280   uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
00281                                       This parameter must be a number between Min_Data = 1 and Max_Data = 32
00282                                       This parameter will be used only when PLLSAI is selected as Clock Source SAI */
00283
00284   uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
00285                                       This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
00286
00287   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
00288                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
00289
00290   uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection.
00291                                       This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
00292 #if defined(STM32F469xx) || defined(STM32F479xx)
00293   uint32_t Clk48ClockSelection;  /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
00294                                       This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
00295
00296   uint32_t SdioClockSelection;   /*!< Specifies SDIO Clock Source Selection.
00297                                       This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
00298 #endif /* STM32F469xx || STM32F479xx */
00299 }RCC_PeriphCLKInitTypeDef;
00300
00301 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00302
00303 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00304     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
00305 /**
00306   * @brief  PLLI2S Clock structure definition
00307   */
00308 typedef struct
00309 {
00310 #if defined(STM32F411xE)
00311   uint32_t PLLI2SM;    /*!< PLLM: Division factor for PLLI2S VCO input clock.
00312                             This parameter must be a number between Min_Data = 2 and Max_Data = 62  */
00313 #endif /* STM32F411xE */
00314
00315   uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
00316                             This parameter must be a number between Min_Data = 50 and Max_Data = 432
00317                             Except for STM32F411xE devices where the Min_Data = 192.
00318                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00319
00320   uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
00321                             This parameter must be a number between Min_Data = 2 and Max_Data = 7.
00322                             This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00323
00324 }RCC_PLLI2SInitTypeDef;
00325
00326 /**
00327   * @brief  RCC extended clocks structure definition
00328   */
00329 typedef struct
00330 {
00331   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
00332                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00333
00334   RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
00335                                       This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
00336
00337   uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
00338                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
00339
00340 }RCC_PeriphCLKInitTypeDef;
00341 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
00342 /**
00343   * @}
00344   */
00345
00346 /* Exported constants --------------------------------------------------------*/
00347 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00348   * @{
00349   */
00350
00351 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
00352   * @{
00353   */
00354 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/
00355 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00356 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
00357 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000002U)
00358 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000004U)
00359 #define RCC_PERIPHCLK_FMPI2C1         ((uint32_t)0x00000008U)
00360 #define RCC_PERIPHCLK_LPTIM1          ((uint32_t)0x00000010U)
00361 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00362 /*----------------------------------------------------------------------------*/
00363
00364 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/
00365 #if defined(STM32F446xx)
00366 #define RCC_PERIPHCLK_I2S_APB1        ((uint32_t)0x00000001U)
00367 #define RCC_PERIPHCLK_I2S_APB2        ((uint32_t)0x00000002U)
00368 #define RCC_PERIPHCLK_SAI1            ((uint32_t)0x00000004U)
00369 #define RCC_PERIPHCLK_SAI2            ((uint32_t)0x00000008U)
00370 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
00371 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
00372 #define RCC_PERIPHCLK_CEC             ((uint32_t)0x00000040U)
00373 #define RCC_PERIPHCLK_FMPI2C1         ((uint32_t)0x00000080U)
00374 #define RCC_PERIPHCLK_CK48            ((uint32_t)0x00000100U)
00375 #define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000200U)
00376 #define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x00000400U)
00377 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000800U)
00378 #endif /* STM32F446xx */
00379 /*-----------------------------------------------------------------------------*/
00380
00381 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
00382 #if defined(STM32F469xx) || defined(STM32F479xx)
00383 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
00384 #define RCC_PERIPHCLK_SAI_PLLI2S      ((uint32_t)0x00000002U)
00385 #define RCC_PERIPHCLK_SAI_PLLSAI      ((uint32_t)0x00000004U)
00386 #define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)
00387 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
00388 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
00389 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000040U)
00390 #define RCC_PERIPHCLK_CK48            ((uint32_t)0x00000080U)
00391 #define RCC_PERIPHCLK_SDIO            ((uint32_t)0x00000100U)
00392 #endif /* STM32F469xx || STM32F479xx */
00393 /*----------------------------------------------------------------------------*/
00394
00395 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
00396 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
00397 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
00398 #define RCC_PERIPHCLK_SAI_PLLI2S      ((uint32_t)0x00000002U)
00399 #define RCC_PERIPHCLK_SAI_PLLSAI      ((uint32_t)0x00000004U)
00400 #define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)
00401 #define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)
00402 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)
00403 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000040U)
00404 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
00405 /*----------------------------------------------------------------------------*/
00406
00407 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
00408 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
00409     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
00410 #define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)
00411 #define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000002U)
00412 #define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x00000004U)
00413 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
00414 /*----------------------------------------------------------------------------*/
00415 /**
00416   * @}
00417   */
00418 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00419     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00420     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00421     defined(STM32F469xx) || defined(STM32F479xx)
00422 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
00423   * @{
00424   */
00425 #define RCC_I2SCLKSOURCE_PLLI2S         ((uint32_t)0x00000000U)
00426 #define RCC_I2SCLKSOURCE_EXT            ((uint32_t)0x00000001U)
00427 /**
00428   * @}
00429   */
00430 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00431           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx */
00432
00433 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
00434   * @{
00435   */
00436 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
00437     defined(STM32F469xx) || defined(STM32F479xx)
00438 #define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000U)
00439 #define RCC_PLLSAIDIVR_4                ((uint32_t)0x00010000U)
00440 #define RCC_PLLSAIDIVR_8                ((uint32_t)0x00020000U)
00441 #define RCC_PLLSAIDIVR_16               ((uint32_t)0x00030000U)
00442 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00443 /**
00444   * @}
00445   */
00446
00447 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
00448   * @{
00449   */
00450 #if defined(STM32F446xx)
00451 #define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000002U)
00452 #define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000004U)
00453 #define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000006U)
00454 #define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000008U)
00455 #endif /* STM32F446xx */
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
00461   * @{
00462   */
00463 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00464 #define RCC_PLLSAIP_DIV2                  ((uint32_t)0x00000002U)
00465 #define RCC_PLLSAIP_DIV4                  ((uint32_t)0x00000004U)
00466 #define RCC_PLLSAIP_DIV6                  ((uint32_t)0x00000006U)
00467 #define RCC_PLLSAIP_DIV8                  ((uint32_t)0x00000008U)
00468 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
00469 /**
00470   * @}
00471   */
00472
00473 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00474 /** @defgroup RCCEx_SAI_BlockA_Clock_Source  RCC SAI BlockA Clock Source
00475   * @{
00476   */
00477 #define RCC_SAIACLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
00478 #define RCC_SAIACLKSOURCE_PLLI2S             ((uint32_t)0x00100000U)
00479 #define RCC_SAIACLKSOURCE_EXT                ((uint32_t)0x00200000U)
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup RCCEx_SAI_BlockB_Clock_Source  RCC SAI BlockB Clock Source
00485   * @{
00486   */
00487 #define RCC_SAIBCLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
00488 #define RCC_SAIBCLKSOURCE_PLLI2S             ((uint32_t)0x00400000U)
00489 #define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)0x00800000U)
00490 /**
00491   * @}
00492   */
00493 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00494
00495 #if defined(STM32F469xx) || defined(STM32F479xx)
00496 /** @defgroup RCCEx_CK48_Clock_Source  RCC CK48 Clock Source
00497   * @{
00498   */
00499 #define RCC_CK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
00500 #define RCC_CK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
00506   * @{
00507   */
00508 #define RCC_SDIOCLKSOURCE_CK48              ((uint32_t)0x00000000U)
00509 #define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR_SDIOSEL)
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source
00515   * @{
00516   */
00517 #define RCC_DSICLKSOURCE_DSIPHY             ((uint32_t)0x00000000U)
00518 #define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_DSISEL)
00519 /**
00520   * @}
00521   */
00522 #endif /* STM32F469xx || STM32F479xx */
00523
00524 #if defined(STM32F446xx)
00525 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
00526   * @{
00527   */
00528 #define RCC_SAI1CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
00529 #define RCC_SAI1CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
00530 #define RCC_SAI1CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
00531 #define RCC_SAI1CLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1SRC)
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup RCCEx_SAI2_Clock_Source  RCC SAI2 Clock Source
00537   * @{
00538   */
00539 #define RCC_SAI2CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
00540 #define RCC_SAI2CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
00541 #define RCC_SAI2CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
00542 #define RCC_SAI2CLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI2SRC)
00543 /**
00544   * @}
00545   */
00546
00547 /** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
00548   * @{
00549   */
00550 #define RCC_I2SAPB1CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
00551 #define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
00552 #define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
00553 #define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
00559   * @{
00560   */
00561 #define RCC_I2SAPB2CLKSOURCE_PLLI2S          ((uint32_t)0x00000000U)
00562 #define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
00563 #define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
00564 #define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)
00565 /**
00566   * @}
00567   */
00568
00569 /** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
00570   * @{
00571   */
00572 #define RCC_FMPI2C1CLKSOURCE_APB                ((uint32_t)0x00000000U)
00573 #define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
00574 #define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
00575 /**
00576   * @}
00577   */
00578
00579 /** @defgroup RCCEx_CEC_Clock_Source  RCC CEC Clock Source
00580   * @{
00581   */
00582 #define RCC_CECCLKSOURCE_HSI                ((uint32_t)0x00000000U)
00583 #define RCC_CECCLKSOURCE_LSE                ((uint32_t)RCC_DCKCFGR2_CECSEL)
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup RCCEx_CK48_Clock_Source  RCC CK48 Clock Source
00589   * @{
00590   */
00591 #define RCC_CK48CLKSOURCE_PLLQ              ((uint32_t)0x00000000U)
00592 #define RCC_CK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
00593 /**
00594   * @}
00595   */
00596
00597 /** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
00598   * @{
00599   */
00600 #define RCC_SDIOCLKSOURCE_CK48              ((uint32_t)0x00000000U)
00601 #define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup RCCEx_SPDIFRX_Clock_Source   RCC SPDIFRX Clock Source
00607   * @{
00608   */
00609 #define RCC_SPDIFRXCLKSOURCE_PLLR             ((uint32_t)0x00000000U)
00610 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP          ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
00611 /**
00612   * @}
00613   */
00614
00615 #endif /* STM32F446xx */
00616
00617 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00618
00619 /** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source
00620   * @{
00621   */
00622 #define RCC_I2SAPBCLKSOURCE_PLLR            ((uint32_t)0x00000000U)
00623 #define RCC_I2SAPBCLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
00624 #define RCC_I2SAPBCLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
00625 /**
00626   * @}
00627   */
00628
00629 /** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
00630   * @{
00631   */
00632 #define RCC_FMPI2C1CLKSOURCE_APB                ((uint32_t)0x00000000U)
00633 #define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
00634 #define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
00640   * @{
00641   */
00642 #define RCC_LPTIM1CLKSOURCE_PCLK            ((uint32_t)0x00000000U)
00643 #define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
00644 #define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
00645 #define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
00651   * @{
00652   */
00653 #define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00U)
00654 #define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01U)
00655 /**
00656   * @}
00657   */
00658 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00659
00660 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00661     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
00662     defined(STM32F469xx) || defined(STM32F479xx)
00663 /** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
00664   * @{
00665   */
00666 #define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00U)
00667 #define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01U)
00668 /**
00669   * @}
00670   */
00671 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
00672           STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00673
00674 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
00675     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00676 /** @defgroup RCCEx_LSE_Dual_Mode_Selection  RCC LSE Dual Mode Selection
00677   * @{
00678   */
00679 #define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00U)
00680 #define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01U)
00681 /**
00682   * @}
00683   */
00684 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00685
00686 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00687     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00688     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00689     defined(STM32F469xx) || defined(STM32F479xx)
00690 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
00691   * @{
00692   */
00693 #define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)
00694 #define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
00695 #define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
00696 #define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
00697 /**
00698   * @}
00699   */
00700 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00701           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00702
00703 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00704 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
00705   * @{
00706   */
00707 #define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)
00708 #define RCC_MCO2SOURCE_I2SCLK            RCC_CFGR_MCO2_0
00709 #define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
00710 #define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
00711 /**
00712   * @}
00713   */
00714 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00715
00716 /**
00717   * @}
00718   */
00719
00720 /* Exported macro ------------------------------------------------------------*/
00721 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00722   * @{
00723   */
00724 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
00725 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00726 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
00727   * @brief  Enables or disables the AHB1 peripheral clock.
00728   * @note   After reset, the peripheral clock (used for registers read/write access)
00729   *         is disabled and the application software has to enable this clock before
00730   *         using it.
00731   * @{
00732   */
00733 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
00734                                         __IO uint32_t tmpreg = 0x00U; \
00735                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
00736                                         /* Delay after an RCC peripheral clock enabling */ \
00737                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
00738                                         UNUSED(tmpreg); \
00739                                         } while(0)
00740 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
00741                                         __IO uint32_t tmpreg = 0x00U; \
00742                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
00743                                         /* Delay after an RCC peripheral clock enabling */ \
00744                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
00745                                         UNUSED(tmpreg); \
00746                                         } while(0)
00747 #define __HAL_RCC_CRC_CLK_ENABLE()     do { \
00748                                         __IO uint32_t tmpreg = 0x00U; \
00749                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
00750                                         /* Delay after an RCC peripheral clock enabling */ \
00751                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
00752                                         UNUSED(tmpreg); \
00753                                         } while(0)
00754 #define __HAL_RCC_GPIOD_CLK_ENABLE()    do { \
00755                                         __IO uint32_t tmpreg = 0x00U; \
00756                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
00757                                         /* Delay after an RCC peripheral clock enabling */ \
00758                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
00759                                         UNUSED(tmpreg); \
00760                                         } while(0)
00761 #define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
00762                                         __IO uint32_t tmpreg = 0x00U; \
00763                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
00764                                         /* Delay after an RCC peripheral clock enabling */ \
00765                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
00766                                         UNUSED(tmpreg); \
00767                                         } while(0)
00768 #define __HAL_RCC_GPIOI_CLK_ENABLE()    do { \
00769                                         __IO uint32_t tmpreg = 0x00U; \
00770                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
00771                                         /* Delay after an RCC peripheral clock enabling */ \
00772                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
00773                                         UNUSED(tmpreg); \
00774                                         } while(0)
00775 #define __HAL_RCC_GPIOF_CLK_ENABLE()    do { \
00776                                         __IO uint32_t tmpreg = 0x00U; \
00777                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
00778                                         /* Delay after an RCC peripheral clock enabling */ \
00779                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
00780                                         UNUSED(tmpreg); \
00781                                         } while(0)
00782 #define __HAL_RCC_GPIOG_CLK_ENABLE()    do { \
00783                                         __IO uint32_t tmpreg = 0x00U; \
00784                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
00785                                         /* Delay after an RCC peripheral clock enabling */ \
00786                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
00787                                         UNUSED(tmpreg); \
00788                                         } while(0)
00789 #define __HAL_RCC_GPIOJ_CLK_ENABLE()    do { \
00790                                         __IO uint32_t tmpreg = 0x00U; \
00791                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
00792                                         /* Delay after an RCC peripheral clock enabling */ \
00793                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
00794                                         UNUSED(tmpreg); \
00795                                         } while(0)
00796 #define __HAL_RCC_GPIOK_CLK_ENABLE()    do { \
00797                                         __IO uint32_t tmpreg = 0x00U; \
00798                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
00799                                         /* Delay after an RCC peripheral clock enabling */ \
00800                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
00801                                         UNUSED(tmpreg); \
00802                                         } while(0)
00803 #define __HAL_RCC_DMA2D_CLK_ENABLE()    do { \
00804                                         __IO uint32_t tmpreg = 0x00U; \
00805                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
00806                                         /* Delay after an RCC peripheral clock enabling */ \
00807                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
00808                                         UNUSED(tmpreg); \
00809                                         } while(0)
00810 #define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
00811                                         __IO uint32_t tmpreg = 0x00U; \
00812                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
00813                                         /* Delay after an RCC peripheral clock enabling */ \
00814                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
00815                                         UNUSED(tmpreg); \
00816                                         } while(0)
00817 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
00818                                         __IO uint32_t tmpreg = 0x00U; \
00819                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
00820                                         /* Delay after an RCC peripheral clock enabling */ \
00821                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
00822                                         UNUSED(tmpreg); \
00823                                         } while(0)
00824 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
00825                                         __IO uint32_t tmpreg = 0x00U; \
00826                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
00827                                         /* Delay after an RCC peripheral clock enabling */ \
00828                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
00829                                          UNUSED(tmpreg); \
00830                                          } while(0)
00831 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
00832                                          __IO uint32_t tmpreg = 0x00U; \
00833                                          SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
00834                                          /* Delay after an RCC peripheral clock enabling */ \
00835                                          tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
00836                                          UNUSED(tmpreg); \
00837                                          } while(0)
00838 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
00839                                         __IO uint32_t tmpreg = 0x00U; \
00840                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
00841                                         /* Delay after an RCC peripheral clock enabling */ \
00842                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
00843                                         UNUSED(tmpreg); \
00844                                         } while(0)
00845 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
00846                                         __IO uint32_t tmpreg = 0x00U; \
00847                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
00848                                         /* Delay after an RCC peripheral clock enabling */ \
00849                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
00850                                         UNUSED(tmpreg); \
00851                                         } while(0)
00852 #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
00853 #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
00854 #define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
00855 #define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
00856 #define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
00857 #define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
00858 #define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
00859 #define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
00860 #define __HAL_RCC_ETHMAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
00861 #define __HAL_RCC_ETHMACTX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
00862 #define __HAL_RCC_ETHMACRX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
00863 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
00864 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
00865 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
00866 #define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
00867 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
00868 #define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
00869
00870 /**
00871   * @brief  Enable ETHERNET clock.
00872   */
00873 #define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \
00874                                         __HAL_RCC_ETHMAC_CLK_ENABLE();      \
00875                                         __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
00876                                         __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
00877                                       } while(0)
00878 /**
00879   * @brief  Disable ETHERNET clock.
00880   */
00881 #define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \
00882                                           __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
00883                                           __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
00884                                           __HAL_RCC_ETHMAC_CLK_DISABLE();      \
00885                                         } while(0)
00886 /**
00887   * @}
00888   */
00889
00890 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
00891   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
00892   * @note   After reset, the peripheral clock (used for registers read/write access)
00893   *         is disabled and the application software has to enable this clock before
00894   *         using it.
00895   * @{
00896   */
00897 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
00898 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
00899 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
00900 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
00901 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
00902 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
00903 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
00904 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
00905 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
00906 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
00907 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
00908 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
00909 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
00910 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
00911 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
00912 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
00913 #define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
00914 #define __HAL_RCC_ETH_IS_CLK_ENABLED()             (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
00915                                                     __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
00916                                                     __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
00917
00918 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
00919 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
00920 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
00921 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
00922 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
00923 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
00924 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
00925 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
00926 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
00927 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
00928 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
00929 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
00930 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
00931 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
00932 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
00933 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
00934 #define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
00935 #define __HAL_RCC_ETH_IS_CLK_DISABLED()             (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
00936                                                      __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
00937                                                      __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
00938 /**
00939   * @}
00940   */
00941
00942 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
00943   * @brief  Enable or disable the AHB2 peripheral clock.
00944   * @note   After reset, the peripheral clock (used for registers read/write access)
00945   *         is disabled and the application software has to enable this clock before
00946   *         using it.
00947   * @{
00948   */
00949  #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
00950                                       __IO uint32_t tmpreg = 0x00U; \
00951                                       SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
00952                                       /* Delay after an RCC peripheral clock enabling */ \
00953                                       tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
00954                                       UNUSED(tmpreg); \
00955                                       } while(0)
00956 #define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
00957
00958 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
00959 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
00960                                       __IO uint32_t tmpreg = 0x00U; \
00961                                       SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
00962                                       /* Delay after an RCC peripheral clock enabling */ \
00963                                       tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
00964                                       UNUSED(tmpreg); \
00965                                       } while(0)
00966 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
00967                                       __IO uint32_t tmpreg = 0x00U; \
00968                                       SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
00969                                       /* Delay after an RCC peripheral clock enabling */ \
00970                                       tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
00971                                       UNUSED(tmpreg); \
00972                                       } while(0)
00973
00974 #define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
00975 #define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
00976 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
00977
00978 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
00979                                                __HAL_RCC_SYSCFG_CLK_ENABLE();\
00980                                               }while(0)
00981
00982 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
00983
00984 #define __HAL_RCC_RNG_CLK_ENABLE()    do { \
00985                                         __IO uint32_t tmpreg = 0x00U; \
00986                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
00987                                         /* Delay after an RCC peripheral clock enabling */ \
00988                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
00989                                         UNUSED(tmpreg); \
00990                                       } while(0)
00991 #define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
00992 /**
00993   * @}
00994   */
00995
00996 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
00997   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
00998   * @note   After reset, the peripheral clock (used for registers read/write access)
00999   *         is disabled and the application software has to enable this clock before
01000   *         using it.
01001   * @{
01002   */
01003 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
01004 #define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
01005
01006 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
01007 #define __HAL_RCC_CRYP_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
01008 #define __HAL_RCC_CRYP_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
01009
01010 #define __HAL_RCC_HASH_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
01011 #define __HAL_RCC_HASH_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
01012 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
01013
01014 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
01015 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
01016
01017 #define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
01018 #define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
01019 /**
01020   * @}
01021   */
01022
01023 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
01024   * @brief  Enables or disables the AHB3 peripheral clock.
01025   * @note   After reset, the peripheral clock (used for registers read/write access)
01026   *         is disabled and the application software has to enable this clock before
01027   *         using it.
01028   * @{
01029   */
01030 #define __HAL_RCC_FMC_CLK_ENABLE()    do { \
01031                                       __IO uint32_t tmpreg = 0x00U; \
01032                                       SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
01033                                       /* Delay after an RCC peripheral clock enabling */ \
01034                                       tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
01035                                       UNUSED(tmpreg); \
01036                                       } while(0)
01037 #define __HAL_RCC_FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
01038 #if defined(STM32F469xx) || defined(STM32F479xx)
01039 #define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
01040                                       __IO uint32_t tmpreg = 0x00U; \
01041                                       SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
01042                                       /* Delay after an RCC peripheral clock enabling */ \
01043                                       tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
01044                                       UNUSED(tmpreg); \
01045                                       } while(0)
01046 #define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
01047 #endif /* STM32F469xx || STM32F479xx */
01048 /**
01049   * @}
01050   */
01051
01052
01053 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
01054   * @brief  Get the enable or disable status of the AHB3 peripheral clock.
01055   * @note   After reset, the peripheral clock (used for registers read/write access)
01056   *         is disabled and the application software has to enable this clock before
01057   *         using it.
01058   * @{
01059   */
01060 #define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
01061 #define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
01062 #if defined(STM32F469xx) || defined(STM32F479xx)
01063 #define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
01064 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
01065 #endif /* STM32F469xx || STM32F479xx */
01066 /**
01067   * @}
01068   */
01069
01070 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
01071   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
01072   * @note   After reset, the peripheral clock (used for registers read/write access)
01073   *         is disabled and the application software has to enable this clock before
01074   *         using it.
01075   * @{
01076   */
01077 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
01078                                       __IO uint32_t tmpreg = 0x00U; \
01079                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
01080                                       /* Delay after an RCC peripheral clock enabling */ \
01081                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
01082                                       UNUSED(tmpreg); \
01083                                       } while(0)
01084 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
01085                                       __IO uint32_t tmpreg = 0x00U; \
01086                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
01087                                       /* Delay after an RCC peripheral clock enabling */ \
01088                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
01089                                       UNUSED(tmpreg); \
01090                                       } while(0)
01091 #define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
01092                                       __IO uint32_t tmpreg = 0x00U; \
01093                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
01094                                       /* Delay after an RCC peripheral clock enabling */ \
01095                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
01096                                       UNUSED(tmpreg); \
01097                                       } while(0)
01098 #define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
01099                                       __IO uint32_t tmpreg = 0x00U; \
01100                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
01101                                       /* Delay after an RCC peripheral clock enabling */ \
01102                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
01103                                       UNUSED(tmpreg); \
01104                                       } while(0)
01105 #define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
01106                                       __IO uint32_t tmpreg = 0x00U; \
01107                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
01108                                       /* Delay after an RCC peripheral clock enabling */ \
01109                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
01110                                       UNUSED(tmpreg); \
01111                                       } while(0)
01112 #define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
01113                                       __IO uint32_t tmpreg = 0x00U; \
01114                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
01115                                       /* Delay after an RCC peripheral clock enabling */ \
01116                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
01117                                       UNUSED(tmpreg); \
01118                                       } while(0)
01119 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
01120                                       __IO uint32_t tmpreg = 0x00U; \
01121                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
01122                                       /* Delay after an RCC peripheral clock enabling */ \
01123                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
01124                                       UNUSED(tmpreg); \
01125                                       } while(0)
01126 #define __HAL_RCC_UART4_CLK_ENABLE()  do { \
01127                                       __IO uint32_t tmpreg = 0x00U; \
01128                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
01129                                       /* Delay after an RCC peripheral clock enabling */ \
01130                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
01131                                       UNUSED(tmpreg); \
01132                                       } while(0)
01133 #define __HAL_RCC_UART5_CLK_ENABLE()  do { \
01134                                       __IO uint32_t tmpreg = 0x00U; \
01135                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
01136                                       /* Delay after an RCC peripheral clock enabling */ \
01137                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
01138                                       UNUSED(tmpreg); \
01139                                       } while(0)
01140 #define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
01141                                       __IO uint32_t tmpreg = 0x00U; \
01142                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
01143                                       /* Delay after an RCC peripheral clock enabling */ \
01144                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
01145                                       UNUSED(tmpreg); \
01146                                       } while(0)
01147 #define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
01148                                       __IO uint32_t tmpreg = 0x00U; \
01149                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
01150                                       /* Delay after an RCC peripheral clock enabling */ \
01151                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
01152                                       UNUSED(tmpreg); \
01153                                       } while(0)
01154 #define __HAL_RCC_DAC_CLK_ENABLE()    do { \
01155                                       __IO uint32_t tmpreg = 0x00U; \
01156                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
01157                                       /* Delay after an RCC peripheral clock enabling */ \
01158                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
01159                                       UNUSED(tmpreg); \
01160                                       } while(0)
01161 #define __HAL_RCC_UART7_CLK_ENABLE()  do { \
01162                                       __IO uint32_t tmpreg = 0x00U; \
01163                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
01164                                       /* Delay after an RCC peripheral clock enabling */ \
01165                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
01166                                       UNUSED(tmpreg); \
01167                                       } while(0)
01168 #define __HAL_RCC_UART8_CLK_ENABLE()  do { \
01169                                       __IO uint32_t tmpreg = 0x00U; \
01170                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
01171                                       /* Delay after an RCC peripheral clock enabling */ \
01172                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
01173                                       UNUSED(tmpreg); \
01174                                       } while(0)
01175 #define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
01176                                         __IO uint32_t tmpreg = 0x00U; \
01177                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
01178                                         /* Delay after an RCC peripheral clock enabling */ \
01179                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
01180                                         UNUSED(tmpreg); \
01181                                       } while(0)
01182 #define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
01183                                         __IO uint32_t tmpreg = 0x00U; \
01184                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
01185                                         /* Delay after an RCC peripheral clock enabling */ \
01186                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
01187                                         UNUSED(tmpreg); \
01188                                       } while(0)
01189 #define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
01190                                         __IO uint32_t tmpreg = 0x00U; \
01191                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
01192                                         /* Delay after an RCC peripheral clock enabling */ \
01193                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
01194                                         UNUSED(tmpreg); \
01195                                       } while(0)
01196 #define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
01197                                         __IO uint32_t tmpreg = 0x00U; \
01198                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
01199                                         /* Delay after an RCC peripheral clock enabling */ \
01200                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
01201                                         UNUSED(tmpreg); \
01202                                       } while(0)
01203 #define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
01204                                         __IO uint32_t tmpreg = 0x00U; \
01205                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
01206                                         /* Delay after an RCC peripheral clock enabling */ \
01207                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
01208                                         UNUSED(tmpreg); \
01209                                       } while(0)
01210 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
01211 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
01212 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
01213 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
01214 #define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
01215 #define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
01216 #define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
01217 #define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
01218 #define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
01219 #define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
01220 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
01221 #define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
01222 #define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
01223 #define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
01224 #define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
01225 #define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
01226 #define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
01227 #define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
01228 /**
01229   * @}
01230   */
01231
01232 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
01233   * @brief  Get the enable or disable status of the APB1 peripheral clock.
01234   * @note   After reset, the peripheral clock (used for registers read/write access)
01235   *         is disabled and the application software has to enable this clock before
01236   *         using it.
01237   * @{
01238   */
01239 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
01240 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
01241 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
01242 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
01243 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
01244 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
01245 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
01246 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
01247 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
01248 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
01249 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
01250 #define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
01251 #define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
01252 #define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
01253 #define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
01254 #define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
01255 #define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
01256 #define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
01257
01258 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
01259 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
01260 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
01261 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
01262 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
01263 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
01264 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
01265 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
01266 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
01267 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
01268 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
01269 #define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
01270 #define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
01271 #define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
01272 #define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
01273 #define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
01274 #define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
01275 #define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
01276 /**
01277   * @}
01278   */
01279
01280 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
01281   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
01282   * @note   After reset, the peripheral clock (used for registers read/write access)
01283   *         is disabled and the application software has to enable this clock before
01284   *         using it.
01285   * @{
01286   */
01287 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
01288                                       __IO uint32_t tmpreg = 0x00U; \
01289                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01290                                       /* Delay after an RCC peripheral clock enabling */ \
01291                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01292                                       UNUSED(tmpreg); \
01293                                       } while(0)
01294 #define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
01295                                       __IO uint32_t tmpreg = 0x00U; \
01296                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
01297                                       /* Delay after an RCC peripheral clock enabling */ \
01298                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
01299                                       UNUSED(tmpreg); \
01300                                       } while(0)
01301 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
01302                                       __IO uint32_t tmpreg = 0x00U; \
01303                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
01304                                       /* Delay after an RCC peripheral clock enabling */ \
01305                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
01306                                       UNUSED(tmpreg); \
01307                                       } while(0)
01308 #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
01309                                       __IO uint32_t tmpreg = 0x00U; \
01310                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
01311                                       /* Delay after an RCC peripheral clock enabling */ \
01312                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
01313                                       UNUSED(tmpreg); \
01314                                       } while(0)
01315 #define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
01316                                       __IO uint32_t tmpreg = 0x00U; \
01317                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
01318                                       /* Delay after an RCC peripheral clock enabling */ \
01319                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
01320                                       UNUSED(tmpreg); \
01321                                       } while(0)
01322 #define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
01323                                       __IO uint32_t tmpreg = 0x00U; \
01324                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
01325                                       /* Delay after an RCC peripheral clock enabling */ \
01326                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
01327                                       UNUSED(tmpreg); \
01328                                       } while(0)
01329 #define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
01330                                         __IO uint32_t tmpreg = 0x00U; \
01331                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
01332                                         /* Delay after an RCC peripheral clock enabling */ \
01333                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
01334                                         UNUSED(tmpreg); \
01335                                       } while(0)
01336 #define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
01337                                         __IO uint32_t tmpreg = 0x00U; \
01338                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
01339                                         /* Delay after an RCC peripheral clock enabling */ \
01340                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
01341                                         UNUSED(tmpreg); \
01342                                       } while(0)
01343 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
01344                                         __IO uint32_t tmpreg = 0x00U; \
01345                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
01346                                         /* Delay after an RCC peripheral clock enabling */ \
01347                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
01348                                         UNUSED(tmpreg); \
01349                                       } while(0)
01350 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
01351 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
01352 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
01353 #define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
01354 #define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
01355 #define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
01356 #define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
01357 #define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
01358 #define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
01359
01360 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
01361 #define __HAL_RCC_LTDC_CLK_ENABLE()  do { \
01362                                       __IO uint32_t tmpreg = 0x00U; \
01363                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
01364                                       /* Delay after an RCC peripheral clock enabling */ \
01365                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
01366                                       UNUSED(tmpreg); \
01367                                       } while(0)
01368
01369 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
01370 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
01371
01372 #if defined(STM32F469xx) || defined(STM32F479xx)
01373 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
01374                                       __IO uint32_t tmpreg = 0x00U; \
01375                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
01376                                       /* Delay after an RCC peripheral clock enabling */ \
01377                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
01378                                       UNUSED(tmpreg); \
01379                                       } while(0)
01380
01381 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
01382 #endif /* STM32F469xx || STM32F479xx */
01383 /**
01384   * @}
01385   */
01386
01387 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
01388   * @brief  Get the enable or disable status of the APB2 peripheral clock.
01389   * @note   After reset, the peripheral clock (used for registers read/write access)
01390   *         is disabled and the application software has to enable this clock before
01391   *         using it.
01392   * @{
01393   */
01394 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
01395 #define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
01396 #define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
01397 #define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
01398 #define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
01399 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
01400 #define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
01401 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
01402 #define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
01403
01404 #define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
01405 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
01406 #define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
01407 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
01408 #define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
01409 #define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
01410 #define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
01411 #define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
01412 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
01413
01414 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
01415 #define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
01416 #define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
01417 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
01418
01419 #if defined(STM32F469xx) || defined(STM32F479xx)
01420 #define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
01421 #define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
01422 #endif /* STM32F469xx || STM32F479xx */
01423 /**
01424   * @}
01425   */
01426
01427 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
01428   * @brief  Force or release AHB1 peripheral reset.
01429   * @{
01430   */
01431 #define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
01432 #define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
01433 #define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
01434 #define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
01435 #define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
01436 #define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
01437 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
01438 #define __HAL_RCC_GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
01439 #define __HAL_RCC_GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
01440 #define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
01441 #define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
01442
01443 #define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
01444 #define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
01445 #define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
01446 #define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
01447 #define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
01448 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
01449 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
01450 #define __HAL_RCC_GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
01451 #define __HAL_RCC_GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
01452 #define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
01453 #define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
01454 /**
01455   * @}
01456   */
01457
01458 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
01459   * @brief  Force or release AHB2 peripheral reset.
01460   * @{
01461   */
01462 #define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
01463 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
01464 #define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
01465 #define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
01466
01467 #define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
01468 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
01469 #define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
01470 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
01471
01472 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
01473 #define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
01474 #define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
01475
01476 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
01477 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
01478 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
01479 /**
01480   * @}
01481   */
01482
01483 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
01484   * @brief  Force or release AHB3 peripheral reset.
01485   * @{
01486   */
01487 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
01488 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
01489 #define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
01490 #define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
01491
01492 #if defined(STM32F469xx) || defined(STM32F479xx)
01493 #define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
01494 #define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
01495 #endif /* STM32F469xx || STM32F479xx */
01496 /**
01497   * @}
01498   */
01499
01500 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
01501   * @brief  Force or release APB1 peripheral reset.
01502   * @{
01503   */
01504 #define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
01505 #define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
01506 #define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
01507 #define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
01508 #define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
01509 #define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
01510 #define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
01511 #define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
01512 #define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
01513 #define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
01514 #define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
01515 #define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
01516 #define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
01517 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
01518 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
01519 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
01520 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
01521 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
01522
01523 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
01524 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
01525 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
01526 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
01527 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
01528 #define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
01529 #define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
01530 #define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
01531 #define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
01532 #define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
01533 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
01534 #define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
01535 #define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
01536 #define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
01537 #define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
01538 #define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
01539 #define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
01540 #define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
01541 /**
01542   * @}
01543   */
01544
01545 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
01546   * @brief  Force or release APB2 peripheral reset.
01547   * @{
01548   */
01549 #define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
01550 #define __HAL_RCC_SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
01551 #define __HAL_RCC_SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
01552 #define __HAL_RCC_SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
01553 #define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
01554 #define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
01555 #define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
01556
01557 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
01558 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
01559 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
01560 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
01561 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
01562 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
01563 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
01564
01565 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
01566 #define __HAL_RCC_LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
01567 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
01568 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
01569
01570 #if defined(STM32F469xx) || defined(STM32F479xx)
01571 #define __HAL_RCC_DSI_FORCE_RESET()   (RCC->APB2RSTR |=  (RCC_APB2RSTR_DSIRST))
01572 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
01573 #endif /* STM32F469xx || STM32F479xx */
01574 /**
01575   * @}
01576   */
01577
01578 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
01579   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
01580   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01581   *         power consumption.
01582   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01583   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01584   * @{
01585   */
01586 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
01587 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
01588 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
01589 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
01590 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
01591 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
01592 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
01593 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
01594 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
01595 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
01596 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
01597 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
01598 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
01599 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
01600 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
01601 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
01602 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
01603 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
01604 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
01605 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
01606
01607 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
01608 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
01609 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
01610 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
01611 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
01612 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
01613 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
01614 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
01615 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
01616 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
01617 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
01618 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
01619 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
01620 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
01621 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
01622 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
01623 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
01624 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
01625 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
01626 /**
01627   * @}
01628   */
01629
01630 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
01631   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
01632   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01633   *         power consumption.
01634   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
01635   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01636   * @{
01637   */
01638 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
01639 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
01640
01641 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
01642 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
01643
01644 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
01645 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
01646
01647 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
01648 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
01649 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
01650
01651 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
01652 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
01653 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
01654 /**
01655   * @}
01656   */
01657
01658 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
01659   * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
01660   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01661   *         power consumption.
01662   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01663   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01664   * @{
01665   */
01666 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
01667 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
01668
01669 #if defined(STM32F469xx) || defined(STM32F479xx)
01670 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
01671 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
01672 #endif /* STM32F469xx || STM32F479xx */
01673 /**
01674   * @}
01675   */
01676
01677 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
01678   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
01679   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01680   *         power consumption.
01681   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01682   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01683   * @{
01684   */
01685 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
01686 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
01687 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
01688 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
01689 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
01690 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
01691 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
01692 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
01693 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
01694 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
01695 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
01696 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
01697 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
01698 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
01699 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
01700 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
01701 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
01702 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
01703
01704 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
01705 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
01706 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
01707 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
01708 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
01709 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
01710 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
01711 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
01712 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
01713 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
01714 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
01715 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
01716 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
01717 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
01718 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
01719 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
01720 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
01721 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
01722 /**
01723   * @}
01724   */
01725
01726 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
01727   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
01728   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01729   *         power consumption.
01730   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01731   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01732   * @{
01733   */
01734 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
01735 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
01736 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
01737 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
01738 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
01739 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
01740 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
01741 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
01742 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
01743
01744 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
01745 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
01746 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
01747 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
01748 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
01749 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
01750 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
01751 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
01752 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
01753
01754 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
01755 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
01756
01757 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
01758 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
01759
01760 #if defined(STM32F469xx) || defined(STM32F479xx)
01761 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |=  (RCC_APB2LPENR_DSILPEN))
01762 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
01763 #endif /* STM32F469xx || STM32F479xx */
01764 /**
01765   * @}
01766   */
01767 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
01768 /*----------------------------------------------------------------------------*/
01769
01770 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
01771 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
01772 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
01773   * @brief  Enables or disables the AHB1 peripheral clock.
01774   * @note   After reset, the peripheral clock (used for registers read/write access)
01775   *         is disabled and the application software has to enable this clock before
01776   *         using it.
01777   * @{
01778   */
01779 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
01780                                         __IO uint32_t tmpreg = 0x00U; \
01781                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
01782                                         /* Delay after an RCC peripheral clock enabling */ \
01783                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
01784                                         UNUSED(tmpreg); \
01785                                         } while(0)
01786 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
01787                                         __IO uint32_t tmpreg = 0x00U; \
01788                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
01789                                         /* Delay after an RCC peripheral clock enabling */ \
01790                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
01791                                         UNUSED(tmpreg); \
01792                                         } while(0)
01793 #define __HAL_RCC_CRC_CLK_ENABLE()     do { \
01794                                         __IO uint32_t tmpreg = 0x00U; \
01795                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
01796                                         /* Delay after an RCC peripheral clock enabling */ \
01797                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
01798                                         UNUSED(tmpreg); \
01799                                         } while(0)
01800 #define __HAL_RCC_GPIOD_CLK_ENABLE()    do { \
01801                                         __IO uint32_t tmpreg = 0x00U; \
01802                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
01803                                         /* Delay after an RCC peripheral clock enabling */ \
01804                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
01805                                         UNUSED(tmpreg); \
01806                                         } while(0)
01807 #define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
01808                                         __IO uint32_t tmpreg = 0x00U; \
01809                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
01810                                         /* Delay after an RCC peripheral clock enabling */ \
01811                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
01812                                         UNUSED(tmpreg); \
01813                                         } while(0)
01814 #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
01815                                        __IO uint32_t tmpreg = 0x00U; \
01816                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
01817                                        /* Delay after an RCC peripheral clock enabling */ \
01818                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
01819                                        UNUSED(tmpreg); \
01820                                        } while(0)
01821 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
01822                                        __IO uint32_t tmpreg = 0x00U; \
01823                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
01824                                        /* Delay after an RCC peripheral clock enabling */ \
01825                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
01826                                        UNUSED(tmpreg); \
01827                                        } while(0)
01828 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
01829                                        __IO uint32_t tmpreg = 0x00U; \
01830                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
01831                                        /* Delay after an RCC peripheral clock enabling */ \
01832                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
01833                                        UNUSED(tmpreg); \
01834                                        } while(0)
01835 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
01836                                        __IO uint32_t tmpreg = 0x00U; \
01837                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
01838                                        /* Delay after an RCC peripheral clock enabling */ \
01839                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
01840                                        UNUSED(tmpreg); \
01841                                        } while(0)
01842 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
01843                                        __IO uint32_t tmpreg = 0x00U; \
01844                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
01845                                        /* Delay after an RCC peripheral clock enabling */ \
01846                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
01847                                        UNUSED(tmpreg); \
01848                                        } while(0)
01849 #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
01850 #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
01851 #define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
01852 #define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
01853 #define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
01854 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
01855 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
01856 #define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
01857 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
01858 #define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
01859 #if defined(STM32F407xx)|| defined(STM32F417xx)
01860 /**
01861   * @brief  Enable ETHERNET clock.
01862   */
01863 #define __HAL_RCC_ETHMAC_CLK_ENABLE()  do { \
01864                                        __IO uint32_t tmpreg = 0x00U; \
01865                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
01866                                        /* Delay after an RCC peripheral clock enabling */ \
01867                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
01868                                        UNUSED(tmpreg); \
01869                                        } while(0)
01870 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
01871                                         __IO uint32_t tmpreg = 0x00U; \
01872                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
01873                                         /* Delay after an RCC peripheral clock enabling */ \
01874                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
01875                                         UNUSED(tmpreg); \
01876                                         } while(0)
01877 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
01878                                         __IO uint32_t tmpreg = 0x00U; \
01879                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
01880                                         /* Delay after an RCC peripheral clock enabling */ \
01881                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
01882                                         UNUSED(tmpreg); \
01883                                         } while(0)
01884 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
01885                                         __IO uint32_t tmpreg = 0x00U; \
01886                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
01887                                         /* Delay after an RCC peripheral clock enabling */ \
01888                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
01889                                         UNUSED(tmpreg); \
01890                                         } while(0)
01891 #define __HAL_RCC_ETH_CLK_ENABLE()      do {                            \
01892                                         __HAL_RCC_ETHMAC_CLK_ENABLE();      \
01893                                         __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
01894                                         __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
01895                                         } while(0)
01896
01897 /**
01898   * @brief  Disable ETHERNET clock.
01899   */
01900 #define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
01901 #define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
01902 #define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
01903 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
01904 #define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
01905                                       __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
01906                                       __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
01907                                       __HAL_RCC_ETHMAC_CLK_DISABLE();      \
01908                                      } while(0)
01909 #endif /* STM32F407xx || STM32F417xx */
01910 /**
01911   * @}
01912   */
01913
01914 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
01915   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
01916   * @note   After reset, the peripheral clock (used for registers read/write access)
01917   *         is disabled and the application software has to enable this clock before
01918   *         using it.
01919   * @{
01920   */
01921 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
01922 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
01923 #define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
01924 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
01925 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
01926 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
01927 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
01928 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
01929 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
01930 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
01931
01932 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
01933 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
01934 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
01935 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
01936 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
01937 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
01938 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
01939 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
01940 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
01941 #define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
01942 #if defined(STM32F407xx)|| defined(STM32F417xx)
01943 /**
01944   * @brief  Enable ETHERNET clock.
01945   */
01946 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
01947 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
01948 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
01949 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
01950 #define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
01951                                                __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
01952                                                                                                                  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
01953 /**
01954   * @brief  Disable ETHERNET clock.
01955   */
01956 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
01957 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
01958 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
01959 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
01960 #define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
01961                                                 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
01962                                                                                                                   __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
01963 #endif /* STM32F407xx || STM32F417xx */
01964 /**
01965   * @}
01966   */
01967
01968 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
01969   * @brief  Enable or disable the AHB2 peripheral clock.
01970   * @note   After reset, the peripheral clock (used for registers read/write access)
01971   *         is disabled and the application software has to enable this clock before
01972   *         using it.
01973   * @{
01974   */
01975 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
01976                                                __HAL_RCC_SYSCFG_CLK_ENABLE();\
01977                                               }while(0)
01978
01979 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
01980
01981 #define __HAL_RCC_RNG_CLK_ENABLE()    do { \
01982                                         __IO uint32_t tmpreg = 0x00U; \
01983                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
01984                                         /* Delay after an RCC peripheral clock enabling */ \
01985                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
01986                                         UNUSED(tmpreg); \
01987                                       } while(0)
01988 #define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
01989
01990 #if defined(STM32F407xx)|| defined(STM32F417xx)
01991 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
01992                                       __IO uint32_t tmpreg = 0x00U; \
01993                                       SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
01994                                       /* Delay after an RCC peripheral clock enabling */ \
01995                                       tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
01996                                       UNUSED(tmpreg); \
01997                                       } while(0)
01998 #define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
01999 #endif /* STM32F407xx || STM32F417xx */
02000
02001 #if defined(STM32F415xx) || defined(STM32F417xx)
02002 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
02003                                       __IO uint32_t tmpreg = 0x00U; \
02004                                       SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
02005                                       /* Delay after an RCC peripheral clock enabling */ \
02006                                       tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
02007                                       UNUSED(tmpreg); \
02008                                       } while(0)
02009 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
02010                                       __IO uint32_t tmpreg = 0x00U; \
02011                                       SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
02012                                       /* Delay after an RCC peripheral clock enabling */ \
02013                                       tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
02014                                       UNUSED(tmpreg); \
02015                                       } while(0)
02016 #define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
02017 #define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
02018 #endif /* STM32F415xx || STM32F417xx */
02019 /**
02020   * @}
02021   */
02022
02023
02024 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
02025   * @brief  Get the enable or disable status of the AHB2 peripheral clock.
02026   * @note   After reset, the peripheral clock (used for registers read/write access)
02027   *         is disabled and the application software has to enable this clock before
02028   *         using it.
02029   * @{
02030   */
02031 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
02032 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
02033
02034 #define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
02035 #define __HAL_RCC_RNG_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
02036
02037 #if defined(STM32F407xx)|| defined(STM32F417xx)
02038 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
02039 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
02040 #endif /* STM32F407xx || STM32F417xx */
02041
02042 #if defined(STM32F415xx) || defined(STM32F417xx)
02043 #define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
02044 #define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
02045
02046 #define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
02047 #define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
02048 #endif /* STM32F415xx || STM32F417xx */
02049 /**
02050   * @}
02051   */
02052
02053 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
02054   * @brief  Enables or disables the AHB3 peripheral clock.
02055   * @note   After reset, the peripheral clock (used for registers read/write access)
02056   *         is disabled and the application software has to enable this clock before
02057   *         using it.
02058   * @{
02059   */
02060 #define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
02061                                       __IO uint32_t tmpreg = 0x00U; \
02062                                       SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
02063                                       /* Delay after an RCC peripheral clock enabling */ \
02064                                       tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
02065                                       UNUSED(tmpreg); \
02066                                       } while(0)
02067 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
02068 /**
02069   * @}
02070   */
02071
02072 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
02073   * @brief  Get the enable or disable status of the AHB3 peripheral clock.
02074   * @note   After reset, the peripheral clock (used for registers read/write access)
02075   *         is disabled and the application software has to enable this clock before
02076   *         using it.
02077   * @{
02078   */
02079 #define __HAL_RCC_FSMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
02080 #define __HAL_RCC_FSMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
02081 /**
02082   * @}
02083   */
02084
02085 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
02086   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
02087   * @note   After reset, the peripheral clock (used for registers read/write access)
02088   *         is disabled and the application software has to enable this clock before
02089   *         using it.
02090   * @{
02091   */
02092 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
02093                                       __IO uint32_t tmpreg = 0x00U; \
02094                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
02095                                       /* Delay after an RCC peripheral clock enabling */ \
02096                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
02097                                       UNUSED(tmpreg); \
02098                                       } while(0)
02099 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
02100                                       __IO uint32_t tmpreg = 0x00U; \
02101                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
02102                                       /* Delay after an RCC peripheral clock enabling */ \
02103                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
02104                                       UNUSED(tmpreg); \
02105                                       } while(0)
02106 #define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
02107                                       __IO uint32_t tmpreg = 0x00U; \
02108                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
02109                                       /* Delay after an RCC peripheral clock enabling */ \
02110                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
02111                                       UNUSED(tmpreg); \
02112                                       } while(0)
02113 #define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
02114                                       __IO uint32_t tmpreg = 0x00U; \
02115                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
02116                                       /* Delay after an RCC peripheral clock enabling */ \
02117                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
02118                                       UNUSED(tmpreg); \
02119                                       } while(0)
02120 #define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
02121                                       __IO uint32_t tmpreg = 0x00U; \
02122                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
02123                                       /* Delay after an RCC peripheral clock enabling */ \
02124                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
02125                                       UNUSED(tmpreg); \
02126                                       } while(0)
02127 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
02128                                       __IO uint32_t tmpreg = 0x00U; \
02129                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
02130                                       /* Delay after an RCC peripheral clock enabling */ \
02131                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
02132                                       UNUSED(tmpreg); \
02133                                       } while(0)
02134 #define __HAL_RCC_UART4_CLK_ENABLE()  do { \
02135                                       __IO uint32_t tmpreg = 0x00U; \
02136                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
02137                                       /* Delay after an RCC peripheral clock enabling */ \
02138                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
02139                                       UNUSED(tmpreg); \
02140                                       } while(0)
02141 #define __HAL_RCC_UART5_CLK_ENABLE()  do { \
02142                                       __IO uint32_t tmpreg = 0x00U; \
02143                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
02144                                       /* Delay after an RCC peripheral clock enabling */ \
02145                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
02146                                       UNUSED(tmpreg); \
02147                                       } while(0)
02148 #define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
02149                                       __IO uint32_t tmpreg = 0x00U; \
02150                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
02151                                       /* Delay after an RCC peripheral clock enabling */ \
02152                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
02153                                       UNUSED(tmpreg); \
02154                                       } while(0)
02155 #define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
02156                                       __IO uint32_t tmpreg = 0x00U; \
02157                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
02158                                       /* Delay after an RCC peripheral clock enabling */ \
02159                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
02160                                       UNUSED(tmpreg); \
02161                                       } while(0)
02162 #define __HAL_RCC_DAC_CLK_ENABLE()    do { \
02163                                       __IO uint32_t tmpreg = 0x00U; \
02164                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
02165                                       /* Delay after an RCC peripheral clock enabling */ \
02166                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
02167                                       UNUSED(tmpreg); \
02168                                       } while(0)
02169 #define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
02170                                         __IO uint32_t tmpreg = 0x00U; \
02171                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
02172                                         /* Delay after an RCC peripheral clock enabling */ \
02173                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
02174                                         UNUSED(tmpreg); \
02175                                       } while(0)
02176 #define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
02177                                         __IO uint32_t tmpreg = 0x00U; \
02178                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02179                                         /* Delay after an RCC peripheral clock enabling */ \
02180                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02181                                         UNUSED(tmpreg); \
02182                                       } while(0)
02183 #define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
02184                                         __IO uint32_t tmpreg = 0x00U; \
02185                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02186                                         /* Delay after an RCC peripheral clock enabling */ \
02187                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02188                                         UNUSED(tmpreg); \
02189                                       } while(0)
02190 #define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
02191                                         __IO uint32_t tmpreg = 0x00U; \
02192                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02193                                         /* Delay after an RCC peripheral clock enabling */ \
02194                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02195                                         UNUSED(tmpreg); \
02196                                       } while(0)
02197 #define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
02198                                         __IO uint32_t tmpreg = 0x00U; \
02199                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02200                                         /* Delay after an RCC peripheral clock enabling */ \
02201                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02202                                         UNUSED(tmpreg); \
02203                                       } while(0)
02204 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
02205 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
02206 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
02207 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
02208 #define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
02209 #define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
02210 #define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
02211 #define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
02212 #define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
02213 #define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
02214 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
02215 #define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
02216 #define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
02217 #define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
02218 #define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
02219 #define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
02220 /**
02221   * @}
02222   */
02223
02224 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
02225   * @brief  Get the enable or disable status of the APB1 peripheral clock.
02226   * @note   After reset, the peripheral clock (used for registers read/write access)
02227   *         is disabled and the application software has to enable this clock before
02228   *         using it.
02229   * @{
02230   */
02231 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
02232 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
02233 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
02234 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
02235 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
02236 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
02237 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
02238 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
02239 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
02240 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
02241 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
02242 #define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
02243 #define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
02244 #define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
02245 #define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
02246 #define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
02247
02248 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
02249 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
02250 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
02251 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
02252 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
02253 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
02254 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
02255 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
02256 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
02257 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
02258 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
02259 #define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
02260 #define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
02261 #define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
02262 #define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
02263 #define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
02264   /**
02265   * @}
02266   */
02267
02268 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
02269   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
02270   * @note   After reset, the peripheral clock (used for registers read/write access)
02271   *         is disabled and the application software has to enable this clock before
02272   *         using it.
02273   * @{
02274   */
02275 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
02276                                       __IO uint32_t tmpreg = 0x00U; \
02277                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
02278                                       /* Delay after an RCC peripheral clock enabling */ \
02279                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
02280                                       UNUSED(tmpreg); \
02281                                       } while(0)
02282 #define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
02283                                       __IO uint32_t tmpreg = 0x00U; \
02284                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
02285                                       /* Delay after an RCC peripheral clock enabling */ \
02286                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
02287                                       UNUSED(tmpreg); \
02288                                       } while(0)
02289 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
02290                                       __IO uint32_t tmpreg = 0x00U; \
02291                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
02292                                       /* Delay after an RCC peripheral clock enabling */ \
02293                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
02294                                       UNUSED(tmpreg); \
02295                                       } while(0)
02296 #define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
02297                                         __IO uint32_t tmpreg = 0x00U; \
02298                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
02299                                         /* Delay after an RCC peripheral clock enabling */ \
02300                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
02301                                         UNUSED(tmpreg); \
02302                                       } while(0)
02303 #define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
02304                                         __IO uint32_t tmpreg = 0x00U; \
02305                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02306                                         /* Delay after an RCC peripheral clock enabling */ \
02307                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02308                                         UNUSED(tmpreg); \
02309                                       } while(0)
02310 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
02311                                         __IO uint32_t tmpreg = 0x00U; \
02312                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
02313                                         /* Delay after an RCC peripheral clock enabling */ \
02314                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
02315                                         UNUSED(tmpreg); \
02316                                       } while(0)
02317
02318 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
02319 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
02320 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
02321 #define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
02322 #define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
02323 #define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
02324 /**
02325   * @}
02326   */
02327
02328 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
02329   * @brief  Get the enable or disable status of the APB2 peripheral clock.
02330   * @note   After reset, the peripheral clock (used for registers read/write access)
02331   *         is disabled and the application software has to enable this clock before
02332   *         using it.
02333   * @{
02334   */
02335 #define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
02336 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
02337 #define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
02338 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
02339 #define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
02340 #define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
02341
02342 #define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
02343 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
02344 #define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
02345 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
02346 #define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
02347 #define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
02348 /**
02349   * @}
02350   */
02351
02352 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
02353   * @brief  Force or release AHB1 peripheral reset.
02354   * @{
02355   */
02356 #define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
02357 #define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
02358 #define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
02359 #define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
02360 #define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
02361 #define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
02362 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
02363 #define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
02364
02365 #define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
02366 #define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
02367 #define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
02368 #define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
02369 #define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
02370 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
02371 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
02372 #define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
02373 /**
02374   * @}
02375   */
02376
02377 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
02378   * @brief  Force or release AHB2 peripheral reset.
02379   * @{
02380   */
02381 #define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFFU)
02382 #define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00U)
02383
02384 #if defined(STM32F407xx)|| defined(STM32F417xx)
02385 #define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
02386 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
02387 #endif /* STM32F407xx || STM32F417xx */
02388
02389 #if defined(STM32F415xx) || defined(STM32F417xx)
02390 #define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
02391 #define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
02392
02393 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
02394 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
02395 #endif /* STM32F415xx || STM32F417xx */
02396
02397 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
02398 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
02399
02400 #define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
02401 #define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
02402 /**
02403   * @}
02404   */
02405
02406 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
02407   * @brief  Force or release AHB3 peripheral reset.
02408   * @{
02409   */
02410 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
02411 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
02412
02413 #define __HAL_RCC_FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
02414 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
02415 /**
02416   * @}
02417   */
02418
02419 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
02420   * @brief  Force or release APB1 peripheral reset.
02421   * @{
02422   */
02423 #define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
02424 #define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
02425 #define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
02426 #define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
02427 #define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
02428 #define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
02429 #define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
02430 #define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
02431 #define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
02432 #define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
02433 #define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
02434 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
02435 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
02436 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
02437 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
02438 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
02439
02440 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
02441 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
02442 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
02443 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
02444 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
02445 #define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
02446 #define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
02447 #define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
02448 #define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
02449 #define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
02450 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
02451 #define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
02452 #define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
02453 #define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
02454 #define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
02455 #define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
02456 /**
02457   * @}
02458   */
02459
02460 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
02461   * @brief  Force or release APB2 peripheral reset.
02462   * @{
02463   */
02464 #define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
02465 #define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
02466 #define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
02467 #define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
02468
02469 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
02470 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
02471 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
02472 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
02473 /**
02474   * @}
02475   */
02476
02477 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
02478   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
02479   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02480   *         power consumption.
02481   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02482   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02483   * @{
02484   */
02485 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
02486 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
02487 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
02488 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
02489 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
02490 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
02491 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
02492 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
02493 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
02494 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
02495 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
02496 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
02497 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
02498 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
02499 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
02500 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
02501
02502 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
02503 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
02504 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
02505 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
02506 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
02507 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
02508 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
02509 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
02510 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
02511 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
02512 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
02513 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
02514 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
02515 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
02516 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
02517 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
02518 /**
02519   * @}
02520   */
02521
02522 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
02523   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
02524   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02525   *         power consumption.
02526   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
02527   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02528   * @{
02529   */
02530 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
02531 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
02532
02533 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
02534 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
02535
02536 #if defined(STM32F407xx)|| defined(STM32F417xx)
02537 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
02538 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
02539 #endif /* STM32F407xx || STM32F417xx */
02540
02541 #if defined(STM32F415xx) || defined(STM32F417xx)
02542 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
02543 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
02544
02545 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
02546 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
02547 #endif /* STM32F415xx || STM32F417xx */
02548 /**
02549   * @}
02550   */
02551
02552 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
02553   * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
02554   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02555   *         power consumption.
02556   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02557   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02558   * @{
02559   */
02560 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
02561 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
02562 /**
02563   * @}
02564   */
02565
02566 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
02567   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
02568   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02569   *         power consumption.
02570   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02571   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02572   * @{
02573   */
02574 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
02575 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
02576 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
02577 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
02578 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
02579 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
02580 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
02581 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
02582 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
02583 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
02584 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
02585 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
02586 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
02587 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
02588 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
02589 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
02590
02591 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
02592 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
02593 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
02594 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
02595 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
02596 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
02597 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
02598 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
02599 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
02600 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
02601 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
02602 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
02603 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
02604 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
02605 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
02606 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
02607 /**
02608   * @}
02609   */
02610
02611 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
02612   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
02613   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02614   *         power consumption.
02615   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02616   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02617   * @{
02618   */
02619 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
02620 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
02621 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
02622 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
02623 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
02624 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
02625
02626 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
02627 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
02628 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
02629 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
02630 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
02631 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
02632 /**
02633   * @}
02634   */
02635 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
02636 /*----------------------------------------------------------------------------*/
02637
02638 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/
02639 #if defined(STM32F401xC) || defined(STM32F401xE)
02640 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
02641   * @brief  Enable or disable the AHB1 peripheral clock.
02642   * @note   After reset, the peripheral clock (used for registers read/write access)
02643   *         is disabled and the application software has to enable this clock before
02644   *         using it.
02645   * @{
02646   */
02647 #define __HAL_RCC_GPIOD_CLK_ENABLE()    do { \
02648                                         __IO uint32_t tmpreg = 0x00U; \
02649                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
02650                                         /* Delay after an RCC peripheral clock enabling */ \
02651                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
02652                                         UNUSED(tmpreg); \
02653                                       } while(0)
02654 #define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
02655                                         __IO uint32_t tmpreg = 0x00U; \
02656                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
02657                                         /* Delay after an RCC peripheral clock enabling */ \
02658                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
02659                                         UNUSED(tmpreg); \
02660                                       } while(0)
02661 #define __HAL_RCC_CRC_CLK_ENABLE()      do { \
02662                                         __IO uint32_t tmpreg = 0x00U; \
02663                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
02664                                         /* Delay after an RCC peripheral clock enabling */ \
02665                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
02666                                         UNUSED(tmpreg); \
02667                                       } while(0)
02668 #define __HAL_RCC_BKPSRAM_CLK_ENABLE()  do { \
02669                                         __IO uint32_t tmpreg = 0x00U; \
02670                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
02671                                         /* Delay after an RCC peripheral clock enabling */ \
02672                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
02673                                         UNUSED(tmpreg); \
02674                                       } while(0)
02675 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE()  do { \
02676                                         __IO uint32_t tmpreg = 0x00U; \
02677                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
02678                                         /* Delay after an RCC peripheral clock enabling */ \
02679                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
02680                                         UNUSED(tmpreg); \
02681                                       } while(0)
02682
02683 #define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
02684 #define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
02685 #define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
02686 #define __HAL_RCC_BKPSRAM_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
02687 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
02688 /**
02689   * @}
02690   */
02691
02692 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
02693   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
02694   * @note   After reset, the peripheral clock (used for registers read/write access)
02695   *         is disabled and the application software has to enable this clock before
02696   *         using it.
02697   * @{
02698   */
02699 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
02700 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
02701 #define __HAL_RCC_CRC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
02702 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
02703 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
02704
02705 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
02706 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
02707 #define __HAL_RCC_CRC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
02708 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
02709 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
02710 /**
02711   * @}
02712   */
02713
02714 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
02715   * @brief  Enable or disable the AHB2 peripheral clock.
02716   * @note   After reset, the peripheral clock (used for registers read/write access)
02717   *         is disabled and the application software has to enable this clock before
02718   *         using it.
02719   * @{
02720   */
02721 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
02722                                                __HAL_RCC_SYSCFG_CLK_ENABLE();\
02723                                               }while(0)
02724
02725 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
02726 /**
02727   * @}
02728   */
02729
02730 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
02731   * @brief  Get the enable or disable status of the AHB2 peripheral clock.
02732   * @note   After reset, the peripheral clock (used for registers read/write access)
02733   *         is disabled and the application software has to enable this clock before
02734   *         using it.
02735   * @{
02736   */
02737 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
02738 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
02739 /**
02740   * @}
02741   */
02742
02743 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
02744   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
02745   * @note   After reset, the peripheral clock (used for registers read/write access)
02746   *         is disabled and the application software has to enable this clock before
02747   *         using it.
02748   * @{
02749   */
02750 #define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
02751                                         __IO uint32_t tmpreg = 0x00U; \
02752                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
02753                                         /* Delay after an RCC peripheral clock enabling */ \
02754                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
02755                                         UNUSED(tmpreg); \
02756                                       } while(0)
02757 #define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
02758                                         __IO uint32_t tmpreg = 0x00U; \
02759                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02760                                         /* Delay after an RCC peripheral clock enabling */ \
02761                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
02762                                         UNUSED(tmpreg); \
02763                                       } while(0)
02764 #define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
02765                                         __IO uint32_t tmpreg = 0x00U; \
02766                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02767                                         /* Delay after an RCC peripheral clock enabling */ \
02768                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
02769                                         UNUSED(tmpreg); \
02770                                       } while(0)
02771 #define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
02772                                         __IO uint32_t tmpreg = 0x00U; \
02773                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02774                                         /* Delay after an RCC peripheral clock enabling */ \
02775                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
02776                                         UNUSED(tmpreg); \
02777                                       } while(0)
02778 #define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
02779                                         __IO uint32_t tmpreg = 0x00U; \
02780                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02781                                         /* Delay after an RCC peripheral clock enabling */ \
02782                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
02783                                         UNUSED(tmpreg); \
02784                                       } while(0)
02785 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
02786 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
02787 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
02788 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
02789 #define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
02790 /**
02791   * @}
02792   */
02793
02794 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
02795   * @brief  Get the enable or disable status of the APB1 peripheral clock.
02796   * @note   After reset, the peripheral clock (used for registers read/write access)
02797   *         is disabled and the application software has to enable this clock before
02798   *         using it.
02799   * @{
02800   */
02801 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
02802 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
02803 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
02804 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
02805 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
02806
02807 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
02808 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
02809 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
02810 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
02811 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
02812 /**
02813   * @}
02814   */
02815
02816 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
02817   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
02818   * @note   After reset, the peripheral clock (used for registers read/write access)
02819   *         is disabled and the application software has to enable this clock before
02820   *         using it.
02821   * @{
02822   */
02823 #define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
02824                                         __IO uint32_t tmpreg = 0x00U; \
02825                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
02826                                         /* Delay after an RCC peripheral clock enabling */ \
02827                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
02828                                         UNUSED(tmpreg); \
02829                                       } while(0)
02830 #define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
02831                                         __IO uint32_t tmpreg = 0x00U; \
02832                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02833                                         /* Delay after an RCC peripheral clock enabling */ \
02834                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
02835                                         UNUSED(tmpreg); \
02836                                       } while(0)
02837 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
02838                                         __IO uint32_t tmpreg = 0x00U; \
02839                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
02840                                         /* Delay after an RCC peripheral clock enabling */ \
02841                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
02842                                         UNUSED(tmpreg); \
02843                                       } while(0)
02844
02845 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
02846 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
02847 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
02848 /**
02849   * @}
02850   */
02851
02852 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
02853   * @brief  Get the enable or disable status of the APB2 peripheral clock.
02854   * @note   After reset, the peripheral clock (used for registers read/write access)
02855   *         is disabled and the application software has to enable this clock before
02856   *         using it.
02857   * @{
02858   */
02859 #define __HAL_RCC_SDIO_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
02860 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
02861 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
02862 /**
02863   * @}
02864   */
02865 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
02866   * @brief  Force or release AHB1 peripheral reset.
02867   * @{
02868   */
02869 #define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
02870 #define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
02871 #define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
02872 #define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
02873
02874 #define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
02875 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
02876 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
02877 #define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
02878 /**
02879   * @}
02880   */
02881
02882 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
02883   * @brief  Force or release AHB2 peripheral reset.
02884   * @{
02885   */
02886 #define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
02887 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
02888
02889 #define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
02890 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
02891 /**
02892   * @}
02893   */
02894
02895 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
02896   * @brief  Force or release APB1 peripheral reset.
02897   * @{
02898   */
02899 #define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
02900 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
02901 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
02902 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
02903 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
02904 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
02905
02906 #define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)
02907 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
02908 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
02909 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
02910 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
02911 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
02912 /**
02913   * @}
02914   */
02915
02916 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
02917   * @brief  Force or release APB2 peripheral reset.
02918   * @{
02919   */
02920 #define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
02921 #define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
02922 #define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
02923 #define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
02924
02925 #define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
02926 #define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
02927 #define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
02928 #define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
02929 /**
02930   * @}
02931   */
02932
02933 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
02934   * @brief  Force or release AHB3 peripheral reset.
02935   * @{
02936   */
02937 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
02938 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
02939 /**
02940   * @}
02941   */
02942
02943 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
02944   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
02945   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02946   *         power consumption.
02947   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
02948   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02949   * @{
02950   */
02951 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
02952 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
02953 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
02954 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
02955 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
02956 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
02957
02958 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
02959 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
02960 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
02961 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
02962 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
02963 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
02964 /**
02965   * @}
02966   */
02967
02968 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
02969   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
02970   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02971   *         power consumption.
02972   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
02973   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02974   * @{
02975   */
02976 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
02977
02978 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
02979 /**
02980   * @}
02981   */
02982
02983 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
02984   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
02985   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02986   *         power consumption.
02987   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
02988   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02989   * @{
02990   */
02991 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
02992 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
02993 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
02994 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
02995 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
02996
02997 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
02998 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
02999 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
03000 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
03001 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
03002 /**
03003   * @}
03004   */
03005
03006 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
03007   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
03008   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
03009   *         power consumption.
03010   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
03011   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
03012   * @{
03013   */
03014 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
03015 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
03016 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
03017
03018 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
03019 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
03020 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
03021 /**
03022   * @}
03023   */
03024 #endif /* STM32F401xC || STM32F401xE*/
03025 /*----------------------------------------------------------------------------*/
03026
03027 /*-------------------------------- STM32F410xx -------------------------------*/
03028 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
03029 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
03030   * @brief  Enables or disables the AHB1 peripheral clock.
03031   * @note   After reset, the peripheral clock (used for registers read/write access)
03032   *         is disabled and the application software has to enable this clock before
03033   *         using it.
03034   * @{
03035   */
03036 #define __HAL_RCC_CRC_CLK_ENABLE()     do { \
03037                                         __IO uint32_t tmpreg = 0x00U; \
03038                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
03039                                         /* Delay after an RCC peripheral clock enabling */ \
03040                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
03041                                         UNUSED(tmpreg); \
03042                                         } while(0)
03043 #define __HAL_RCC_RNG_CLK_ENABLE()     do { \
03044                                         __IO uint32_t tmpreg = 0x00U; \
03045                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
03046                                         /* Delay after an RCC peripheral clock enabling */ \
03047                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
03048                                         UNUSED(tmpreg); \
03049                                         } while(0)
03050 #define __HAL_RCC_CRC_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
03051 #define __HAL_RCC_RNG_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
03052 /**
03053   * @}
03054   */
03055
03056 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
03057   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
03058   * @note   After reset, the peripheral clock (used for registers read/write access)
03059   *         is disabled and the application software has to enable this clock before
03060   *         using it.
03061   * @{
03062   */
03063 #define __HAL_RCC_CRC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
03064 #define __HAL_RCC_RNG_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
03065 /**
03066   * @}
03067   */
03068
03069 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
03070   * @brief  Enable or disable the High Speed APB (APB1) peripheral clock.
03071   * @{
03072   */
03073 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
03074                                       __IO uint32_t tmpreg = 0x00U; \
03075                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
03076                                       /* Delay after an RCC peripheral clock enabling */ \
03077                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
03078                                       UNUSED(tmpreg); \
03079                                       } while(0)
03080 #define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
03081                                       __IO uint32_t tmpreg = 0x00U; \
03082                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
03083                                       /* Delay after an RCC peripheral clock enabling */ \
03084                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
03085                                       UNUSED(tmpreg); \
03086                                       } while(0)
03087 #define __HAL_RCC_RTCAPB_CLK_ENABLE()   do { \
03088                                       __IO uint32_t tmpreg = 0x00U; \
03089                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
03090                                       /* Delay after an RCC peripheral clock enabling */ \
03091                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
03092                                       UNUSED(tmpreg); \
03093                                       } while(0)
03094 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
03095                                       __IO uint32_t tmpreg = 0x00U; \
03096                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
03097                                       /* Delay after an RCC peripheral clock enabling */ \
03098                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
03099                                       UNUSED(tmpreg); \
03100                                       } while(0)
03101 #define __HAL_RCC_DAC_CLK_ENABLE()   do { \
03102                                       __IO uint32_t tmpreg = 0x00U; \
03103                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
03104                                       /* Delay after an RCC peripheral clock enabling */ \
03105                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
03106                                       UNUSED(tmpreg); \
03107                                       } while(0)
03108
03109 #define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
03110 #define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
03111 #define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
03112 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
03113 #define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
03114 /**
03115   * @}
03116   */
03117
03118 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
03119   * @brief  Get the enable or disable status of the APB1 peripheral clock.
03120   * @note   After reset, the peripheral clock (used for registers read/write access)
03121   *         is disabled and the application software has to enable this clock before
03122   *         using it.
03123   * @{
03124   */
03125 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
03126 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
03127 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
03128 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
03129 #define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
03130
03131 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
03132 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
03133 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
03134 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
03135 #define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
03136 /**
03137   * @}
03138   */
03139
03140 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
03141   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
03142   * @{
03143   */
03144 #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
03145                                       __IO uint32_t tmpreg = 0x00U; \
03146                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
03147                                       /* Delay after an RCC peripheral clock enabling */ \
03148                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
03149                                       UNUSED(tmpreg); \
03150                                       } while(0)
03151 #define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
03152                                       __IO uint32_t tmpreg = 0x00U; \
03153                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
03154                                       /* Delay after an RCC peripheral clock enabling */ \
03155                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
03156                                       UNUSED(tmpreg); \
03157                                       } while(0)
03158 #define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
03159 #define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
03160 /**
03161   * @}
03162   */
03163
03164 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
03165   * @brief  Get the enable or disable status of the APB2 peripheral clock.
03166   * @note   After reset, the peripheral clock (used for registers read/write access)
03167   *         is disabled and the application software has to enable this clock before
03168   *         using it.
03169   * @{
03170   */
03171 #define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
03172 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
03173
03174 #define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
03175 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
03176 /**
03177   * @}
03178   */
03179
03180 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
03181   * @brief  Force or release AHB1 peripheral reset.
03182   * @{
03183   */
03184 #define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
03185 #define __HAL_RCC_RNG_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
03186 #define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
03187 #define __HAL_RCC_RNG_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
03188 /**
03189   * @}
03190   */
03191
03192 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
03193   * @brief  Force or release AHB2 peripheral reset.
03194   * @{
03195   */
03196 #define __HAL_RCC_AHB2_FORCE_RESET()
03197 #define __HAL_RCC_AHB2_RELEASE_RESET()
03198 /**
03199   * @}
03200   */
03201
03202 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
03203   * @brief  Force or release AHB3 peripheral reset.
03204   * @{
03205   */
03206 #define __HAL_RCC_AHB3_FORCE_RESET()
03207 #define __HAL_RCC_AHB3_RELEASE_RESET()
03208 /**
03209   * @}
03210   */
03211
03212 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
03213   * @brief  Force or release APB1 peripheral reset.
03214   * @{
03215   */
03216 #define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
03217 #define __HAL_RCC_LPTIM1_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
03218 #define __HAL_RCC_FMPI2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
03219 #define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
03220
03221 #define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
03222 #define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
03223 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
03224 #define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
03225 /**
03226   * @}
03227   */
03228
03229 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
03230   * @brief  Force or release APB2 peripheral reset.
03231   * @{
03232   */
03233 #define __HAL_RCC_SPI5_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
03234 #define __HAL_RCC_SPI5_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
03235 /**
03236   * @}
03237   */
03238
03239 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
03240   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
03241   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
03242   *         power consumption.
03243   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
03244   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
03245   * @{
03246   */
03247 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
03248 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
03249 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
03250 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
03251
03252 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
03253 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
03254 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
03255 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
03256 /**
03257   * @}
03258   */
03259
03260 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
03261   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
03262   * @{
03263   */
03264 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
03265 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
03266 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
03267 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
03268 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
03269
03270 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
03271 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
03272 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
03273 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
03274 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
03275 /**
03276   * @}
03277   */
03278
03279 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
03280   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
03281   * @{
03282   */
03283 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
03284 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
03285 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
03286 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
03287 /**
03288   * @}
03289   */
03290
03291 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
03292 /*----------------------------------------------------------------------------*/
03293
03294 /*-------------------------------- STM32F411xx -------------------------------*/
03295 #if defined(STM32F411xE)
03296 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
03297   * @brief  Enables or disables the AHB1 peripheral clock.
03298   * @note   After reset, the peripheral clock (used for registers read/write access)
03299   *         is disabled and the application software has to enable this clock before
03300   *         using it.
03301   * @{
03302   */
03303 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
03304                                         __IO uint32_t tmpreg = 0x00U; \
03305                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
03306                                         /* Delay after an RCC peripheral clock enabling */ \
03307                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
03308                                         UNUSED(tmpreg); \
03309                                         } while(0)
03310 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
03311                                         __IO uint32_t tmpreg = 0x00U; \
03312                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
03313                                         /* Delay after an RCC peripheral clock enabling */ \
03314                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
03315                                         UNUSED(tmpreg); \
03316                                         } while(0)
03317 #define __HAL_RCC_GPIOD_CLK_ENABLE()    do { \
03318                                         __IO uint32_t tmpreg = 0x00U; \
03319                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
03320                                         /* Delay after an RCC peripheral clock enabling */ \
03321                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
03322                                         UNUSED(tmpreg); \
03323                                         } while(0)
03324 #define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
03325                                         __IO uint32_t tmpreg = 0x00U; \
03326                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
03327                                         /* Delay after an RCC peripheral clock enabling */ \
03328                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
03329                                         UNUSED(tmpreg); \
03330                                         } while(0)
03331 #define __HAL_RCC_CRC_CLK_ENABLE()     do { \
03332                                         __IO uint32_t tmpreg = 0x00U; \
03333                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
03334                                         /* Delay after an RCC peripheral clock enabling */ \
03335                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
03336                                         UNUSED(tmpreg); \
03337                                         } while(0)
03338 #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
03339 #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
03340 #define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
03341 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
03342 #define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
03343 /**
03344   * @}
03345   */
03346
03347 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
03348   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
03349   * @note   After reset, the peripheral clock (used for registers read/write access)
03350   *         is disabled and the application software has to enable this clock before
03351   *         using it.
03352   * @{
03353   */
03354 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
03355 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
03356 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
03357 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
03358 #define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
03359
03360 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
03361 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
03362 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
03363 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
03364 #define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
03365 /**
03366   * @}
03367   */
03368
03369 /** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
03370   * @brief  Enable or disable the AHB2 peripheral clock.
03371   * @note   After reset, the peripheral clock (used for registers read/write access)
03372   *         is disabled and the application software has to enable this clock before
03373   *         using it.
03374   * @{
03375   */
03376 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
03377                                                __HAL_RCC_SYSCFG_CLK_ENABLE();\
03378                                               }while(0)
03379
03380 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
03381 /**
03382   * @}
03383   */
03384
03385 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
03386   * @brief  Get the enable or disable status of the AHB2 peripheral clock.
03387   * @note   After reset, the peripheral clock (used for registers read/write access)
03388   *         is disabled and the application software has to enable this clock before
03389   *         using it.
03390   * @{
03391   */
03392 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
03393 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
03394 /**
03395   * @}
03396   */
03397
03398 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
03399   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
03400   * @note   After reset, the peripheral clock (used for registers read/write access)
03401   *         is disabled and the application software has to enable this clock before
03402   *         using it.
03403   * @{
03404   */
03405 #define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
03406                                         __IO uint32_t tmpreg = 0x00U; \
03407                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
03408                                         /* Delay after an RCC peripheral clock enabling */ \
03409                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
03410                                         UNUSED(tmpreg); \
03411                                         } while(0)
03412 #define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
03413                                         __IO uint32_t tmpreg = 0x00U; \
03414                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
03415                                         /* Delay after an RCC peripheral clock enabling */ \
03416                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
03417                                         UNUSED(tmpreg); \
03418                                         } while(0)
03419 #define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
03420                                         __IO uint32_t tmpreg = 0x00U; \
03421                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
03422                                         /* Delay after an RCC peripheral clock enabling */ \
03423                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
03424                                         UNUSED(tmpreg); \
03425                                         } while(0)
03426 #define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
03427                                         __IO uint32_t tmpreg = 0x00U; \
03428                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
03429                                         /* Delay after an RCC peripheral clock enabling */ \
03430                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
03431                                         UNUSED(tmpreg); \
03432                                         } while(0)
03433 #define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
03434                                         __IO uint32_t tmpreg = 0x00U; \
03435                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
03436                                         /* Delay after an RCC peripheral clock enabling */ \
03437                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
03438                                         UNUSED(tmpreg); \
03439                                         } while(0)
03440 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
03441 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
03442 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
03443 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
03444 #define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
03445 /**
03446   * @}
03447   */
03448
03449 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
03450   * @brief  Get the enable or disable status of the APB1 peripheral clock.
03451   * @note   After reset, the peripheral clock (used for registers read/write access)
03452   *         is disabled and the application software has to enable this clock before
03453   *         using it.
03454   * @{
03455   */
03456 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
03457 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
03458 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
03459 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
03460 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
03461
03462 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
03463 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
03464 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
03465 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
03466 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
03467 /**
03468   * @}
03469   */
03470
03471 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
03472   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
03473   * @{
03474   */
03475 #define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
03476                                       __IO uint32_t tmpreg = 0x00U; \
03477                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
03478                                       /* Delay after an RCC peripheral clock enabling */ \
03479                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
03480                                       UNUSED(tmpreg); \
03481                                       } while(0)
03482 #define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
03483                                         __IO uint32_t tmpreg = 0x00U; \
03484                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
03485                                         /* Delay after an RCC peripheral clock enabling */ \
03486                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
03487                                         UNUSED(tmpreg); \
03488                                         } while(0)
03489 #define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
03490                                         __IO uint32_t tmpreg = 0x00U; \
03491                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
03492                                         /* Delay after an RCC peripheral clock enabling */ \
03493                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
03494                                         UNUSED(tmpreg); \
03495                                         } while(0)
03496 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
03497                                         __IO uint32_t tmpreg = 0x00U; \
03498                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
03499                                         /* Delay after an RCC peripheral clock enabling */ \
03500                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
03501                                         UNUSED(tmpreg); \
03502                                         } while(0)
03503 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
03504 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
03505 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
03506 #define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
03507 /**
03508   * @}
03509   */
03510
03511 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
03512   * @brief  Get the enable or disable status of the APB2 peripheral clock.
03513   * @note   After reset, the peripheral clock (used for registers read/write access)
03514   *         is disabled and the application software has to enable this clock before
03515   *         using it.
03516   * @{
03517   */
03518 #define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
03519 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
03520 #define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
03521 #define __HAL_RCC_SPI5_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
03522
03523 #define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
03524 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
03525 #define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
03526 #define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
03527 /**
03528   * @}
03529   */
03530
03531 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
03532   * @brief  Force or release AHB1 peripheral reset.
03533   * @{
03534   */
03535 #define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
03536 #define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
03537 #define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
03538
03539 #define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
03540 #define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
03541 #define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
03542 /**
03543   * @}
03544   */
03545
03546 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
03547   * @brief  Force or release AHB2 peripheral reset.
03548   * @{
03549   */
03550 #define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
03551 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
03552
03553 #define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
03554 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
03555 /**
03556   * @}
03557   */
03558
03559 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
03560   * @brief  Force or release AHB3 peripheral reset.
03561   * @{
03562   */
03563 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
03564 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
03565 /**
03566   * @}
03567   */
03568
03569 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
03570   * @brief  Force or release APB1 peripheral reset.
03571   * @{
03572   */
03573 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
03574 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
03575 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
03576 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
03577 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
03578
03579 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
03580 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
03581 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
03582 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
03583 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
03584 /**
03585   * @}
03586   */
03587
03588 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
03589   * @brief  Force or release APB2 peripheral reset.
03590   * @{
03591   */
03592 #define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
03593 #define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
03594 #define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
03595 #define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
03596
03597 #define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
03598 #define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
03599 #define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
03600 #define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
03601 /**
03602   * @}
03603   */
03604
03605 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
03606   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
03607   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
03608   *         power consumption.
03609   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
03610   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
03611   * @{
03612   */
03613 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
03614 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
03615 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
03616 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
03617 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
03618
03619 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
03620 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
03621 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
03622 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
03623 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
03624 /**
03625   * @}
03626   */
03627
03628 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
03629   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
03630   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
03631   *         power consumption.
03632   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
03633   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
03634   * @{
03635   */
03636 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
03637 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
03638 /**
03639   * @}
03640   */
03641
03642 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
03643   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
03644   * @{
03645   */
03646 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
03647 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
03648 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
03649 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
03650 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
03651
03652 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
03653 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
03654 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
03655 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
03656 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
03657 /**
03658   * @}
03659   */
03660
03661 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
03662   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
03663   * @{
03664   */
03665 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
03666 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
03667 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
03668 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
03669
03670 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
03671 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
03672 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
03673 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
03674 /**
03675   * @}
03676   */
03677 #endif /* STM32F411xE */
03678 /*----------------------------------------------------------------------------*/
03679
03680 /*---------------------------------- STM32F446xx -----------------------------*/
03681 #if defined(STM32F446xx)
03682 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
03683   * @brief  Enables or disables the AHB1 peripheral clock.
03684   * @note   After reset, the peripheral clock (used for registers read/write access)
03685   *         is disabled and the application software has to enable this clock before
03686   *         using it.
03687   * @{
03688   */
03689 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
03690                                         __IO uint32_t tmpreg = 0x00U; \
03691                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
03692                                         /* Delay after an RCC peripheral clock enabling */ \
03693                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
03694                                         UNUSED(tmpreg); \
03695                                         } while(0)
03696 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
03697                                         __IO uint32_t tmpreg = 0x00U; \
03698                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
03699                                         /* Delay after an RCC peripheral clock enabling */ \
03700                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
03701                                         UNUSED(tmpreg); \
03702                                         } while(0)
03703 #define __HAL_RCC_CRC_CLK_ENABLE()     do { \
03704                                         __IO uint32_t tmpreg = 0x00U; \
03705                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
03706                                         /* Delay after an RCC peripheral clock enabling */ \
03707                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
03708                                         UNUSED(tmpreg); \
03709                                         } while(0)
03710 #define __HAL_RCC_GPIOD_CLK_ENABLE()    do { \
03711                                         __IO uint32_t tmpreg = 0x00U; \
03712                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
03713                                         /* Delay after an RCC peripheral clock enabling */ \
03714                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
03715                                         UNUSED(tmpreg); \
03716                                         } while(0)
03717 #define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
03718                                         __IO uint32_t tmpreg = 0x00U; \
03719                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
03720                                         /* Delay after an RCC peripheral clock enabling */ \
03721                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
03722                                         UNUSED(tmpreg); \
03723                                         } while(0)
03724 #define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
03725                                       __IO uint32_t tmpreg = 0x00U; \
03726                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
03727                                       /* Delay after an RCC peripheral clock enabling */ \
03728                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
03729                                       UNUSED(tmpreg); \
03730                                       } while(0)
03731 #define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
03732                                       __IO uint32_t tmpreg = 0x00U; \
03733                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
03734                                       /* Delay after an RCC peripheral clock enabling */ \
03735                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
03736                                       UNUSED(tmpreg); \
03737                                       } while(0)
03738 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
03739                                       __IO uint32_t tmpreg = 0x00U; \
03740                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
03741                                       /* Delay after an RCC peripheral clock enabling */ \
03742                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
03743                                       UNUSED(tmpreg); \
03744                                       } while(0)
03745 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
03746                                       __IO uint32_t tmpreg = 0x00U; \
03747                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
03748                                       /* Delay after an RCC peripheral clock enabling */ \
03749                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
03750                                       UNUSED(tmpreg); \
03751                                       } while(0)
03752 #define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
03753 #define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
03754 #define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
03755 #define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
03756 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
03757 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
03758 #define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
03759 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
03760 #define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
03761 /**
03762   * @}
03763   */
03764
03765 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
03766   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
03767   * @note   After reset, the peripheral clock (used for registers read/write access)
03768   *         is disabled and the application software has to enable this clock before
03769   *         using it.
03770   * @{
03771   */
03772 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
03773 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
03774 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
03775 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
03776 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
03777 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
03778 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
03779 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
03780 #define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
03781
03782 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
03783 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
03784 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
03785 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
03786 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
03787 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
03788 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
03789 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
03790 #define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
03791 /**
03792   * @}
03793   */
03794
03795 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
03796   * @brief  Enable or disable the AHB2 peripheral clock.
03797   * @note   After reset, the peripheral clock (used for registers read/write access)
03798   *         is disabled and the application software has to enable this clock before
03799   *         using it.
03800   * @{
03801   */
03802 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
03803                                       __IO uint32_t tmpreg = 0x00U; \
03804                                       SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
03805                                       /* Delay after an RCC peripheral clock enabling */ \
03806                                       tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
03807                                       UNUSED(tmpreg); \
03808                                       } while(0)
03809 #define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
03810 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
03811                                                __HAL_RCC_SYSCFG_CLK_ENABLE();\
03812                                               }while(0)
03813
03814 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
03815
03816 #define __HAL_RCC_RNG_CLK_ENABLE()    do { \
03817                                         __IO uint32_t tmpreg = 0x00U; \
03818                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
03819                                         /* Delay after an RCC peripheral clock enabling */ \
03820                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
03821                                         UNUSED(tmpreg); \
03822                                       } while(0)
03823 #define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
03824 /**
03825   * @}
03826   */
03827
03828 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
03829   * @brief  Get the enable or disable status of the AHB2 peripheral clock.
03830   * @note   After reset, the peripheral clock (used for registers read/write access)
03831   *         is disabled and the application software has to enable this clock before
03832   *         using it.
03833   * @{
03834   */
03835 #define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
03836 #define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
03837
03838 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
03839 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
03840
03841 #define __HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
03842 #define __HAL_RCC_RNG_IS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
03843 /**
03844   * @}
03845   */
03846
03847 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
03848   * @brief  Enables or disables the AHB3 peripheral clock.
03849   * @note   After reset, the peripheral clock (used for registers read/write access)
03850   *         is disabled and the application software has to enable this clock before
03851   *         using it.
03852   * @{
03853   */
03854 #define __HAL_RCC_FMC_CLK_ENABLE()    do { \
03855                                       __IO uint32_t tmpreg = 0x00U; \
03856                                       SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
03857                                       /* Delay after an RCC peripheral clock enabling */ \
03858                                       tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
03859                                       UNUSED(tmpreg); \
03860                                       } while(0)
03861 #define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
03862                                       __IO uint32_t tmpreg = 0x00U; \
03863                                       SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
03864                                       /* Delay after an RCC peripheral clock enabling */ \
03865                                       tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
03866                                       UNUSED(tmpreg); \
03867                                       } while(0)
03868
03869 #define __HAL_RCC_FMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
03870 #define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
03871 /**
03872   * @}
03873   */
03874
03875 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
03876   * @brief  Get the enable or disable status of the AHB3 peripheral clock.
03877   * @note   After reset, the peripheral clock (used for registers read/write access)
03878   *         is disabled and the application software has to enable this clock before
03879   *         using it.
03880   * @{
03881   */
03882 #define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
03883 #define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
03884
03885 #define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
03886 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
03887 /**
03888   * @}
03889   */
03890
03891 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
03892   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
03893   * @note   After reset, the peripheral clock (used for registers read/write access)
03894   *         is disabled and the application software has to enable this clock before
03895   *         using it.
03896   * @{
03897   */
03898 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
03899                                       __IO uint32_t tmpreg = 0x00U; \
03900                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
03901                                       /* Delay after an RCC peripheral clock enabling */ \
03902                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
03903                                       UNUSED(tmpreg); \
03904                                       } while(0)
03905 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
03906                                       __IO uint32_t tmpreg = 0x00U; \
03907                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
03908                                       /* Delay after an RCC peripheral clock enabling */ \
03909                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
03910                                       UNUSED(tmpreg); \
03911                                       } while(0)
03912 #define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
03913                                       __IO uint32_t tmpreg = 0x00U; \
03914                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
03915                                       /* Delay after an RCC peripheral clock enabling */ \
03916                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
03917                                       UNUSED(tmpreg); \
03918                                       } while(0)
03919 #define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
03920                                       __IO uint32_t tmpreg = 0x00U; \
03921                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
03922                                       /* Delay after an RCC peripheral clock enabling */ \
03923                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
03924                                       UNUSED(tmpreg); \
03925                                       } while(0)
03926 #define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
03927                                       __IO uint32_t tmpreg = 0x00U; \
03928                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
03929                                       /* Delay after an RCC peripheral clock enabling */ \
03930                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
03931                                       UNUSED(tmpreg); \
03932                                       } while(0)
03933 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
03934                                       __IO uint32_t tmpreg = 0x00U; \
03935                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
03936                                       /* Delay after an RCC peripheral clock enabling */ \
03937                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
03938                                       UNUSED(tmpreg); \
03939                                       } while(0)
03940 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
03941                                       __IO uint32_t tmpreg = 0x00U; \
03942                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
03943                                       /* Delay after an RCC peripheral clock enabling */ \
03944                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
03945                                       UNUSED(tmpreg); \
03946                                       } while(0)
03947 #define __HAL_RCC_UART4_CLK_ENABLE()  do { \
03948                                       __IO uint32_t tmpreg = 0x00U; \
03949                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
03950                                       /* Delay after an RCC peripheral clock enabling */ \
03951                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
03952                                       UNUSED(tmpreg); \
03953                                       } while(0)
03954 #define __HAL_RCC_UART5_CLK_ENABLE()  do { \
03955                                       __IO uint32_t tmpreg = 0x00U; \
03956                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
03957                                       /* Delay after an RCC peripheral clock enabling */ \
03958                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
03959                                       UNUSED(tmpreg); \
03960                                       } while(0)
03961 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
03962                                       __IO uint32_t tmpreg = 0x00U; \
03963                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
03964                                       /* Delay after an RCC peripheral clock enabling */ \
03965                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
03966                                       UNUSED(tmpreg); \
03967                                       } while(0)
03968 #define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
03969                                       __IO uint32_t tmpreg = 0x00U; \
03970                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
03971                                       /* Delay after an RCC peripheral clock enabling */ \
03972                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
03973                                       UNUSED(tmpreg); \
03974                                       } while(0)
03975 #define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
03976                                       __IO uint32_t tmpreg = 0x00U; \
03977                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
03978                                       /* Delay after an RCC peripheral clock enabling */ \
03979                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
03980                                       UNUSED(tmpreg); \
03981                                       } while(0)
03982 #define __HAL_RCC_CEC_CLK_ENABLE()    do { \
03983                                       __IO uint32_t tmpreg = 0x00U; \
03984                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
03985                                       /* Delay after an RCC peripheral clock enabling */ \
03986                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
03987                                       UNUSED(tmpreg); \
03988                                       } while(0)
03989 #define __HAL_RCC_DAC_CLK_ENABLE()    do { \
03990                                       __IO uint32_t tmpreg = 0x00U; \
03991                                       SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
03992                                       /* Delay after an RCC peripheral clock enabling */ \
03993                                       tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
03994                                       UNUSED(tmpreg); \
03995                                       } while(0)
03996 #define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
03997                                         __IO uint32_t tmpreg = 0x00U; \
03998                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
03999                                         /* Delay after an RCC peripheral clock enabling */ \
04000                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
04001                                         UNUSED(tmpreg); \
04002                                         } while(0)
04003 #define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
04004                                         __IO uint32_t tmpreg = 0x00U; \
04005                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
04006                                         /* Delay after an RCC peripheral clock enabling */ \
04007                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
04008                                         UNUSED(tmpreg); \
04009                                         } while(0)
04010 #define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
04011                                         __IO uint32_t tmpreg = 0x00U; \
04012                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
04013                                         /* Delay after an RCC peripheral clock enabling */ \
04014                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
04015                                         UNUSED(tmpreg); \
04016                                         } while(0)
04017 #define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
04018                                         __IO uint32_t tmpreg = 0x00U; \
04019                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
04020                                         /* Delay after an RCC peripheral clock enabling */ \
04021                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
04022                                         UNUSED(tmpreg); \
04023                                         } while(0)
04024 #define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
04025                                         __IO uint32_t tmpreg = 0x00U; \
04026                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
04027                                         /* Delay after an RCC peripheral clock enabling */ \
04028                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
04029                                         UNUSED(tmpreg); \
04030                                         } while(0)
04031 #define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
04032 #define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
04033 #define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
04034 #define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
04035 #define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
04036 #define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
04037 #define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
04038 #define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
04039 #define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
04040 #define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
04041 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
04042 #define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
04043 #define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
04044 #define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
04045 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
04046 #define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
04047 #define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
04048 #define __HAL_RCC_CEC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
04049 #define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
04050 /**
04051   * @}
04052   */
04053
04054 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
04055   * @brief  Get the enable or disable status of the APB1 peripheral clock.
04056   * @note   After reset, the peripheral clock (used for registers read/write access)
04057   *         is disabled and the application software has to enable this clock before
04058   *         using it.
04059   * @{
04060   */
04061 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
04062 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
04063 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
04064 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
04065 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
04066 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
04067 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
04068 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
04069 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
04070 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
04071 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
04072 #define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
04073 #define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
04074 #define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
04075 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
04076 #define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
04077 #define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
04078 #define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
04079 #define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
04080
04081 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
04082 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
04083 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
04084 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
04085 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
04086 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
04087 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
04088 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
04089 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
04090 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
04091 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
04092 #define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
04093 #define __HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
04094 #define __HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
04095 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
04096 #define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
04097 #define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
04098 #define __HAL_RCC_CEC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
04099 #define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
04100 /**
04101   * @}
04102   */
04103
04104 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
04105   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
04106   * @note   After reset, the peripheral clock (used for registers read/write access)
04107   *         is disabled and the application software has to enable this clock before
04108   *         using it.
04109   * @{
04110   */
04111 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
04112                                       __IO uint32_t tmpreg = 0x00U; \
04113                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
04114                                       /* Delay after an RCC peripheral clock enabling */ \
04115                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
04116                                       UNUSED(tmpreg); \
04117                                       } while(0)
04118 #define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
04119                                       __IO uint32_t tmpreg = 0x00U; \
04120                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
04121                                       /* Delay after an RCC peripheral clock enabling */ \
04122                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
04123                                       UNUSED(tmpreg); \
04124                                       } while(0)
04125 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
04126                                       __IO uint32_t tmpreg = 0x00U; \
04127                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
04128                                       /* Delay after an RCC peripheral clock enabling */ \
04129                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
04130                                       UNUSED(tmpreg); \
04131                                       } while(0)
04132 #define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
04133                                       __IO uint32_t tmpreg = 0x00U; \
04134                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
04135                                       /* Delay after an RCC peripheral clock enabling */ \
04136                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
04137                                       UNUSED(tmpreg); \
04138                                       } while(0)
04139 #define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
04140                                       __IO uint32_t tmpreg = 0x00U; \
04141                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
04142                                       /* Delay after an RCC peripheral clock enabling */ \
04143                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
04144                                       UNUSED(tmpreg); \
04145                                       } while(0)
04146 #define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
04147                                         __IO uint32_t tmpreg = 0x00U; \
04148                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
04149                                         /* Delay after an RCC peripheral clock enabling */ \
04150                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
04151                                         UNUSED(tmpreg); \
04152                                         } while(0)
04153 #define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
04154                                         __IO uint32_t tmpreg = 0x00U; \
04155                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
04156                                         /* Delay after an RCC peripheral clock enabling */ \
04157                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
04158                                         UNUSED(tmpreg); \
04159                                         } while(0)
04160 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
04161                                         __IO uint32_t tmpreg = 0x00U; \
04162                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
04163                                         /* Delay after an RCC peripheral clock enabling */ \
04164                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
04165                                         UNUSED(tmpreg); \
04166                                         } while(0)
04167 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
04168 #define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
04169 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
04170 #define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
04171 #define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
04172 #define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
04173 #define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
04174 #define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
04175 /**
04176   * @}
04177   */
04178
04179 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
04180   * @brief  Get the enable or disable status of the APB2 peripheral clock.
04181   * @note   After reset, the peripheral clock (used for registers read/write access)
04182   *         is disabled and the application software has to enable this clock before
04183   *         using it.
04184   * @{
04185   */
04186 #define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
04187 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
04188 #define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
04189 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
04190 #define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
04191 #define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
04192 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
04193 #define __HAL_RCC_SAI2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
04194
04195 #define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
04196 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
04197 #define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
04198 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
04199 #define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
04200 #define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
04201 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
04202 #define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
04203 /**
04204   * @}
04205   */
04206
04207 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
04208   * @brief  Force or release AHB1 peripheral reset.
04209   * @{
04210   */
04211 #define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
04212 #define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
04213 #define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
04214 #define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
04215 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
04216 #define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
04217
04218 #define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
04219 #define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
04220 #define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
04221 #define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
04222 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
04223 #define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
04224 /**
04225   * @}
04226   */
04227
04228 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
04229   * @brief  Force or release AHB2 peripheral reset.
04230   * @{
04231   */
04232 #define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
04233 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
04234 #define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
04235 #define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
04236
04237 #define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
04238 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
04239 #define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
04240 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
04241 /**
04242   * @}
04243   */
04244
04245 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
04246   * @brief  Force or release AHB3 peripheral reset.
04247   * @{
04248   */
04249 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
04250 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
04251
04252 #define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
04253 #define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
04254
04255 #define __HAL_RCC_FMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
04256 #define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
04257 /**
04258   * @}
04259   */
04260
04261 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
04262   * @brief  Force or release APB1 peripheral reset.
04263   * @{
04264   */
04265 #define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
04266 #define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
04267 #define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
04268 #define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
04269 #define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
04270 #define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
04271 #define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
04272 #define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
04273 #define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
04274 #define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
04275 #define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
04276 #define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
04277 #define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
04278 #define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
04279 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
04280 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
04281 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
04282 #define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
04283 #define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
04284
04285 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
04286 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
04287 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
04288 #define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
04289 #define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
04290 #define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
04291 #define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
04292 #define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
04293 #define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
04294 #define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
04295 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
04296 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
04297 #define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
04298 #define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
04299 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
04300 #define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
04301 #define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
04302 #define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
04303 #define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
04304 /**
04305   * @}
04306   */
04307
04308 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
04309   * @brief  Force or release APB2 peripheral reset.
04310   * @{
04311   */
04312 #define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
04313 #define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
04314 #define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
04315 #define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
04316 #define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
04317 #define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
04318
04319 #define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
04320 #define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
04321 #define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
04322 #define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
04323 #define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
04324 #define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
04325 /**
04326   * @}
04327   */
04328
04329 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
04330   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
04331   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
04332   *         power consumption.
04333   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
04334   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
04335   * @{
04336   */
04337 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
04338 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
04339 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
04340 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
04341 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
04342 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
04343 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
04344 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
04345 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
04346 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
04347 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
04348
04349 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
04350 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
04351 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
04352 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
04353 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
04354 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
04355 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
04356 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
04357 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
04358 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
04359 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
04360 /**
04361   * @}
04362   */
04363
04364 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
04365   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
04366   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
04367   *         power consumption.
04368   * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
04369   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
04370   * @{
04371   */
04372 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
04373 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
04374
04375 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
04376 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
04377
04378 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
04379 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
04380 /**
04381   * @}
04382   */
04383
04384 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
04385   * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
04386   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
04387   *         power consumption.
04388   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
04389   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
04390   * @{
04391   */
04392 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
04393 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
04394
04395 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
04396 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
04397 /**
04398   * @}
04399   */
04400
04401 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
04402   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
04403   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
04404   *         power consumption.
04405   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
04406   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
04407   * @{
04408   */
04409 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
04410 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
04411 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
04412 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
04413 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
04414 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
04415 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
04416 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
04417 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
04418 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
04419 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
04420 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
04421 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
04422 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
04423 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
04424 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
04425 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
04426 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
04427 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
04428
04429 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
04430 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
04431 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
04432 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
04433 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
04434 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
04435 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
04436 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
04437 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
04438 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
04439 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
04440 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
04441 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
04442 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
04443 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
04444 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
04445 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
04446 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
04447 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
04448 /**
04449   * @}
04450   */
04451
04452 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
04453   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
04454   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
04455   *         power consumption.
04456   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
04457   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
04458   * @{
04459   */
04460 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
04461 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
04462 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
04463 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
04464 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
04465 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
04466 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
04467 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
04468
04469 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
04470 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
04471 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
04472 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
04473 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
04474 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
04475 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
04476 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
04477 /**
04478   * @}
04479   */
04480
04481 #endif /* STM32F446xx */
04482 /*----------------------------------------------------------------------------*/
04483 /*------------------------------- PLL Configuration --------------------------*/
04484 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
04485     defined(STM32F469xx) || defined(STM32F479xx)
04486 /** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
04487   * @note   This function must be used only when the main PLL is disabled.
04488   * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
04489   *         This parameter can be one of the following values:
04490   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
04491   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
04492   * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
04493   * @param  __PLLM__: specifies the division factor for PLL VCO input clock
04494   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
04495   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
04496   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
04497   *         of 2 MHz to limit PLL jitter.
04498   * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
04499   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
04500   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
04501   *         output frequency is between 100 and 432 MHz.
04502   *
04503   * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
04504   *         This parameter must be a number in the range {2, 4, 6, or 8}.
04505   *
04506   * @param  __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
04507   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
04508   * @note   If the USB OTG FS is used in your application, you have to set the
04509   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
04510   *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
04511   *         correctly.
04512   *
04513   * @param  __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
04514   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04515   * @note   This parameter is only available in STM32F446xx/STM32F469xx and STM32F479xx devices.
04516   *
04517   */
04518 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
04519                             (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
04520                             ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                      | \
04521                             ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))          | \
04522                             ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))                      | \
04523                             ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
04524 #else
04525 /** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
04526   * @note   This function must be used only when the main PLL is disabled.
04527   * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
04528   *         This parameter can be one of the following values:
04529   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
04530   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
04531   * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
04532   * @param  __PLLM__: specifies the division factor for PLL VCO input clock
04533   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
04534   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
04535   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
04536   *         of 2 MHz to limit PLL jitter.
04537   * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
04538   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432
04539   *         Except for STM32F411xE devices where Min_Data = 192.
04540   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
04541   *         output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
04542   *         where frequency is between 192 and 432 MHz.
04543   * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
04544   *         This parameter must be a number in the range {2, 4, 6, or 8}.
04545   *
04546   * @param  __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
04547   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
04548   * @note   If the USB OTG FS is used in your application, you have to set the
04549   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
04550   *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
04551   *         correctly.
04552   *
04553   */
04554 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
04555                             (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
04556                             ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                | \
04557                             ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))    | \
04558                             ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
04559  #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
04560 /*----------------------------------------------------------------------------*/
04561
04562 /*----------------------------PLLI2S Configuration ---------------------------*/
04563 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
04564     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
04565     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
04566     defined(STM32F469xx) || defined(STM32F479xx)
04567
04568 /** @brief Macros to enable or disable the PLLI2S.
04569   * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
04570   */
04571 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
04572 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
04573
04574 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
04575           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
04576 #if defined(STM32F446xx)
04577 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
04578   * @note   This macro must be used only when the PLLI2S is disabled.
04579   * @note   PLLI2S clock source is common with the main PLL (configured in
04580   *         HAL_RCC_ClockConfig() API).
04581   * @param  __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
04582   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
04583   * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
04584   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
04585   *         of 1 MHz to limit PLLI2S jitter.
04586   *
04587   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
04588   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
04589   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
04590   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
04591   *
04592   * @param  __PLLI2SP__: specifies division factor for SPDIFRX Clock.
04593   *         This parameter must be a number in the range {2, 4, 6, or 8}.
04594   * @note   the PLLI2SP parameter is only available with STM32F446xx Devices
04595   *
04596   * @param  __PLLI2SR__: specifies the division factor for I2S clock
04597   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04598   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
04599   *         on the I2S clock frequency.
04600   *
04601   * @param  __PLLI2SQ__: specifies the division factor for SAI clock
04602   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
04603   */
04604 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)    \
04605                                (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
04606                                ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))             |\
04607                                ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
04608                                ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))             |\
04609                                ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
04610 #else
04611 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
04612   * @note   This macro must be used only when the PLLI2S is disabled.
04613   * @note   PLLI2S clock source is common with the main PLL (configured in
04614   *         HAL_RCC_ClockConfig() API).
04615   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
04616   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
04617   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
04618   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
04619   *
04620   * @param  __PLLI2SR__: specifies the division factor for I2S clock
04621   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04622   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
04623   *         on the I2S clock frequency.
04624   *
04625   */
04626 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)                                                    \
04627                                (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))  |\
04628                                ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
04629 #endif /* STM32F446xx */
04630
04631 #if defined(STM32F411xE)
04632 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
04633   * @note   This macro must be used only when the PLLI2S is disabled.
04634   * @note   This macro must be used only when the PLLI2S is disabled.
04635   * @note   PLLI2S clock source is common with the main PLL (configured in
04636   *         HAL_RCC_ClockConfig() API).
04637   * @param  __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
04638   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
04639   * @note   The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
04640   * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
04641   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
04642   *         of 2 MHz to limit PLLI2S jitter.
04643   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
04644   *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
04645   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
04646   *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
04647   * @param  __PLLI2SR__: specifies the division factor for I2S clock
04648   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04649   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
04650   *         on the I2S clock frequency.
04651   */
04652 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                                       |\
04653                                                                                                   ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN))             |\
04654                                                                                                   ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
04655 #endif /* STM32F411xE */
04656
04657 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
04658 /** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
04659   * @note   This macro must be used only when the PLLI2S is disabled.
04660   * @note   PLLI2S clock source is common with the main PLL (configured in
04661   *         HAL_RCC_ClockConfig() API)
04662   * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
04663   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
04664   * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
04665   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
04666   * @param  __PLLI2SQ__: specifies the division factor for SAI1 clock.
04667   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
04668   * @note   the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
04669   *         Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
04670   * @param  __PLLI2SR__: specifies the division factor for I2S clock
04671   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04672   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
04673   *         on the I2S clock frequency.
04674   */
04675 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6)  |\
04676                                                                                                  ((__PLLI2SQ__) << 24) |\
04677                                                                                                  ((__PLLI2SR__) << 28))
04678 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
04679 /*----------------------------------------------------------------------------*/
04680
04681 /*------------------------------ PLLSAI Configuration ------------------------*/
04682 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
04683 /** @brief Macros to Enable or Disable the PLLISAI.
04684   * @note  The PLLSAI is only available with STM32F429x/439x Devices.
04685   * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
04686   */
04687 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
04688 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
04689
04690 #if defined(STM32F446xx)
04691 /** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
04692   *
04693   * @param  __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
04694   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
04695   * @note   You have to set the PLLSAIM parameter correctly to ensure that the VCO input
04696   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
04697   *         of 1 MHz to limit PLLI2S jitter.
04698   * @note   The PLLSAIM parameter is only used with STM32F446xx Devices
04699   *
04700   * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
04701   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
04702   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
04703   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
04704   *
04705   * @param  __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
04706   *         This parameter must be a number in the range {2, 4, 6, or 8}.
04707   * @note   the PLLSAIP parameter is only available with STM32F446xx Devices
04708   *
04709   * @param  __PLLSAIQ__: specifies the division factor for SAI clock
04710   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
04711   *
04712   * @param  __PLLSAIR__: specifies the division factor for LTDC clock
04713   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04714   * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
04715   */
04716 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)     \
04717                                (RCC->PLLSAICFGR = ((__PLLSAIM__)                                   | \
04718                                ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN))             | \
04719                                ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \
04720                                ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
04721 #endif /* STM32F446xx */
04722
04723 #if defined(STM32F469xx) || defined(STM32F479xx)
04724 /** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
04725   *
04726   * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
04727   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
04728   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
04729   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
04730   *
04731   * @param  __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
04732   *         This parameter must be a number in the range {2, 4, 6, or 8}.
04733   *
04734   * @param  __PLLSAIQ__: specifies the division factor for SAI clock
04735   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
04736   *
04737   * @param  __PLLSAIR__: specifies the division factor for LTDC clock
04738   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04739   */
04740 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
04741                                (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN))             |\
04742                                                    ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
04743                                                    ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))             |\
04744                                                    ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
04745 #endif /* STM32F469xx || STM32F479xx */
04746
04747 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
04748 /** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
04749   *
04750   * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
04751   *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
04752   * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO
04753   *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
04754   *
04755   * @param  __PLLSAIQ__: specifies the division factor for SAI clock
04756   *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
04757   *
04758   * @param  __PLLSAIR__: specifies the division factor for LTDC clock
04759   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
04760   * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
04761   */
04762 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__)                                        \
04763                                (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN))  | \
04764                                ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))                      | \
04765                                ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
04766 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
04767
04768 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
04769 /*----------------------------------------------------------------------------*/
04770
04771 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
04772 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)  || defined(STM32F446xx) ||\
04773     defined(STM32F469xx) || defined(STM32F479xx)
04774 /** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
04775   * @note   This function must be called before enabling the PLLI2S.
04776   * @param  __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
04777   *          This parameter must be a number between 1 and 32.
04778   *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
04779   */
04780 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
04781
04782 /** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
04783   * @note   This function must be called before enabling the PLLSAI.
04784   * @param  __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
04785   *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
04786   *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
04787   */
04788 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
04789 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
04790
04791 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
04792 /** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
04793   *
04794   * @note   The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
04795   * @note   This function must be called before enabling the PLLSAI.
04796   * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
04797   *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
04798   *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
04799   */
04800 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
04801 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
04802 /*----------------------------------------------------------------------------*/
04803
04804 /*------------------------- Peripheral Clock selection -----------------------*/
04805 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
04806     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
04807     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
04808     defined(STM32F479xx)
04809 /** @brief  Macro to configure the I2S clock source (I2SCLK).
04810   * @note   This function must be called before enabling the I2S APB clock.
04811   * @param  __SOURCE__: specifies the I2S clock source.
04812   *         This parameter can be one of the following values:
04813   *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
04814   *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
04815   *                                       used as I2S clock source.
04816   */
04817 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
04818 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
04819
04820 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
04821
04822 /** @brief  Macro to configure SAI1BlockA clock source selection.
04823   * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
04824   * @note   This function must be called before enabling PLLSAI, PLLI2S and
04825   *         the SAI clock.
04826   * @param  __SOURCE__: specifies the SAI Block A clock source.
04827   *         This parameter can be one of the following values:
04828   *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
04829   *                                           as SAI1 Block A clock.
04830   *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
04831   *                                           as SAI1 Block A clock.
04832   *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
04833   *                                        used as SAI1 Block A clock.
04834   */
04835 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
04836
04837 /** @brief  Macro to configure SAI1BlockB clock source selection.
04838   * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
04839   * @note   This function must be called before enabling PLLSAI, PLLI2S and
04840   *         the SAI clock.
04841   * @param  __SOURCE__: specifies the SAI Block B clock source.
04842   *         This parameter can be one of the following values:
04843   *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
04844   *                                           as SAI1 Block B clock.
04845   *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
04846   *                                           as SAI1 Block B clock.
04847   *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
04848   *                                        used as SAI1 Block B clock.
04849   */
04850 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
04851 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
04852
04853 #if defined(STM32F446xx)
04854 /** @brief  Macro to configure SAI1 clock source selection.
04855   * @note   This configuration is only available with STM32F446xx Devices.
04856   * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and
04857   *         the SAI clock.
04858   * @param  __SOURCE__: specifies the SAI1 clock source.
04859   *         This parameter can be one of the following values:
04860   *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
04861   *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
04862   *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
04863   *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
04864   */
04865 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
04866
04867 /** @brief  Macro to Get SAI1 clock source selection.
04868   * @note   This configuration is only available with STM32F446xx Devices.
04869   * @retval The clock source can be one of the following values:
04870   *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
04871   *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
04872   *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
04873   *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
04874   */
04875 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
04876
04877 /** @brief  Macro to configure SAI2 clock source selection.
04878   * @note   This configuration is only available with STM32F446xx Devices.
04879   * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and
04880   *         the SAI clock.
04881   * @param  __SOURCE__: specifies the SAI2 clock source.
04882   *         This parameter can be one of the following values:
04883   *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
04884   *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
04885   *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
04886   *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
04887   */
04888 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
04889
04890 /** @brief  Macro to Get SAI2 clock source selection.
04891   * @note   This configuration is only available with STM32F446xx Devices.
04892   * @retval The clock source can be one of the following values:
04893   *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
04894   *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
04895   *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
04896   *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
04897   */
04898 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
04899
04900 /** @brief  Macro to configure I2S APB1 clock source selection.
04901   * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
04902   * @param  __SOURCE__: specifies the I2S APB1 clock source.
04903   *         This parameter can be one of the following values:
04904   *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
04905   *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
04906   *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
04907   *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
04908   */
04909 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
04910
04911 /** @brief  Macro to Get I2S APB1 clock source selection.
04912   * @retval The clock source can be one of the following values:
04913   *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
04914   *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
04915   *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
04916   *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
04917   */
04918 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
04919
04920 /** @brief  Macro to configure I2S APB2 clock source selection.
04921   * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
04922   * @param  __SOURCE__: specifies the SAI Block A clock source.
04923   *         This parameter can be one of the following values:
04924   *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
04925   *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
04926   *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
04927   *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
04928   */
04929 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
04930
04931 /** @brief  Macro to Get I2S APB2 clock source selection.
04932   * @retval The clock source can be one of the following values:
04933   *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
04934   *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
04935   *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
04936   *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
04937   */
04938 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
04939
04940 /** @brief  Macro to configure the CEC clock.
04941   * @param  __SOURCE__: specifies the CEC clock source.
04942   *         This parameter can be one of the following values:
04943   *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
04944   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
04945   */
04946 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
04947
04948 /** @brief  Macro to Get the CEC clock.
04949   * @retval The clock source can be one of the following values:
04950   *            @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
04951   *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
04952   */
04953 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
04954
04955 /** @brief  Macro to configure the FMPI2C1 clock.
04956   * @param  __SOURCE__: specifies the FMPI2C1 clock source.
04957   *         This parameter can be one of the following values:
04958   *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
04959   *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
04960   *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
04961   */
04962 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
04963
04964 /** @brief  Macro to Get the FMPI2C1 clock.
04965   * @retval The clock source can be one of the following values:
04966   *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
04967   *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
04968   *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
04969   */
04970 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
04971
04972 /** @brief  Macro to configure the CLK48 clock.
04973   * @param  __SOURCE__: specifies the CK48 clock source.
04974   *         This parameter can be one of the following values:
04975   *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
04976   *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
04977   */
04978 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
04979
04980 /** @brief  Macro to Get the CLK48 clock.
04981   * @retval The clock source can be one of the following values:
04982   *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
04983   *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
04984   */
04985 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
04986
04987 /** @brief  Macro to configure the SDIO clock.
04988   * @param  __SOURCE__: specifies the SDIO clock source.
04989   *         This parameter can be one of the following values:
04990   *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
04991   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
04992   */
04993 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
04994
04995 /** @brief  Macro to Get the SDIO clock.
04996   * @retval The clock source can be one of the following values:
04997   *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
04998   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
04999   */
05000 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
05001
05002 /** @brief  Macro to configure the SPDIFRX clock.
05003   * @param  __SOURCE__: specifies the SPDIFRX clock source.
05004   *         This parameter can be one of the following values:
05005   *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
05006   *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
05007   */
05008 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
05009
05010 /** @brief  Macro to Get the SPDIFRX clock.
05011   * @retval The clock source can be one of the following values:
05012   *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
05013   *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
05014   */
05015 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
05016 #endif /* STM32F446xx */
05017
05018 #if defined(STM32F469xx) || defined(STM32F479xx)
05019
05020 /** @brief  Macro to configure the CLK48 clock.
05021   * @param  __SOURCE__: specifies the CK48 clock source.
05022   *         This parameter can be one of the following values:
05023   *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
05024   *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
05025   */
05026 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
05027
05028 /** @brief  Macro to Get the CLK48 clock.
05029   * @retval The clock source can be one of the following values:
05030   *            @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
05031   *            @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
05032   */
05033 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
05034
05035 /** @brief  Macro to configure the SDIO clock.
05036   * @param  __SOURCE__: specifies the SDIO clock source.
05037   *         This parameter can be one of the following values:
05038   *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
05039   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
05040   */
05041 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
05042
05043 /** @brief  Macro to Get the SDIO clock.
05044   * @retval The clock source can be one of the following values:
05045   *            @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
05046   *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
05047   */
05048 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
05049
05050 /** @brief  Macro to configure the DSI clock.
05051   * @param  __SOURCE__: specifies the DSI clock source.
05052   *         This parameter can be one of the following values:
05053   *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
05054   *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
05055   */
05056 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
05057
05058 /** @brief  Macro to Get the DSI clock.
05059   * @retval The clock source can be one of the following values:
05060   *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
05061   *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
05062   */
05063 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
05064
05065 #endif /* STM32F469xx || STM32F479xx */
05066
05067 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
05068 /** @brief  Macro to configure I2S clock source selection.
05069   * @param  __SOURCE__: specifies the I2S clock source.
05070   *         This parameter can be one of the following values:
05071   *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
05072   *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
05073   *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
05074   */
05075 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
05076
05077 /** @brief  Macro to Get I2S clock source selection.
05078   * @retval The clock source can be one of the following values:
05079   *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
05080   *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
05081   *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
05082   */
05083 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
05084
05085 /** @brief  Macro to configure the FMPI2C1 clock.
05086   * @param  __SOURCE__: specifies the FMPI2C1 clock source.
05087   *         This parameter can be one of the following values:
05088   *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
05089   *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
05090   *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
05091   */
05092 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
05093
05094 /** @brief  Macro to Get the FMPI2C1 clock.
05095   * @retval The clock source can be one of the following values:
05096   *            @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
05097   *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
05098   *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
05099   */
05100 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
05101
05102 /** @brief  Macro to configure the LPTIM1 clock.
05103   * @param  __SOURCE__: specifies the LPTIM1 clock source.
05104   *         This parameter can be one of the following values:
05105   *            @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
05106   *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
05107   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
05108   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
05109   */
05110 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
05111
05112 /** @brief  Macro to Get the LPTIM1 clock.
05113   * @retval The clock source can be one of the following values:
05114   *            @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
05115   *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
05116   *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
05117   *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
05118   */
05119 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
05120 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
05121
05122 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
05123     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
05124     defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
05125     defined(STM32F479xx)
05126 /** @brief  Macro to configure the Timers clocks prescalers
05127   * @note   This feature is only available with STM32F429x/439x Devices.
05128   * @param  __PRESC__ : specifies the Timers clocks prescalers selection
05129   *         This parameter can be one of the following values:
05130   *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
05131   *                 equal to HPRE if PPREx is corresponding to division by 1 or 2,
05132   *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
05133   *                 division by 4 or more.
05134   *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
05135   *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
05136   *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
05137   *                 to division by 8 or more.
05138   */
05139 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
05140
05141 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
05142           STM32F446xx || STM32F469xx || STM32F479xx */
05143
05144 /*----------------------------------------------------------------------------*/
05145
05146 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
05147 /** @brief Enable PLLSAI_RDY interrupt.
05148   */
05149 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
05150
05151 /** @brief Disable PLLSAI_RDY interrupt.
05152   */
05153 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
05154
05155 /** @brief Clear the PLLSAI RDY interrupt pending bits.
05156   */
05157 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
05158
05159 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
05160   * @retval The new state (TRUE or FALSE).
05161   */
05162 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
05163
05164 /** @brief  Check PLLSAI RDY flag is set or not.
05165   * @retval The new state (TRUE or FALSE).
05166   */
05167 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
05168
05169 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
05170
05171 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
05172 /** @brief  Macros to enable or disable the RCC MCO1 feature.
05173   */
05174 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
05175 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
05176
05177 /** @brief  Macros to enable or disable the RCC MCO2 feature.
05178   */
05179 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
05180 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
05181
05182 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
05183
05184 /**
05185   * @}
05186   */
05187
05188 /* Exported functions --------------------------------------------------------*/
05189 /** @addtogroup RCCEx_Exported_Functions
05190   *  @{
05191   */
05192
05193 /** @addtogroup RCCEx_Exported_Functions_Group1
05194   *  @{
05195   */
05196 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
05197 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
05198
05199 #if defined(STM32F446xx)
05200 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
05201 #endif /* STM32F446xx */
05202
05203 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
05204     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
05205 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
05206 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
05207 /**
05208   * @}
05209   */
05210
05211 /**
05212   * @}
05213   */
05214 /* Private types -------------------------------------------------------------*/
05215 /* Private variables ---------------------------------------------------------*/
05216 /* Private constants ---------------------------------------------------------*/
05217 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
05218   * @{
05219   */
05220
05221 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
05222   * @brief RCC registers bit address in the alias region
05223   * @{
05224   */
05225 /* --- CR Register ---*/
05226 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
05227     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
05228 /* Alias word address of PLLSAION bit */
05229 #define RCC_PLLSAION_BIT_NUMBER        0x1C
05230 #define RCC_CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
05231
05232 #define PLLSAI_TIMEOUT_VALUE       ((uint32_t)2)  /* Timeout value fixed to 2 ms  */
05233 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
05234
05235 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
05236     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
05237     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
05238     defined(STM32F469xx) || defined(STM32F479xx)
05239 /* Alias word address of PLLI2SON bit */
05240 #define RCC_PLLI2SON_BIT_NUMBER    0x1A
05241 #define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
05242 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
05243           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx */
05244
05245 /* --- DCKCFGR Register ---*/
05246 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
05247     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
05248     defined(STM32F469xx) || defined(STM32F479xx)
05249 /* Alias word address of TIMPRE bit */
05250 #define RCC_DCKCFGR_OFFSET            (RCC_OFFSET + 0x8C)
05251 #define RCC_TIMPRE_BIT_NUMBER          0x18
05252 #define RCC_DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
05253 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */
05254
05255 /* --- CFGR Register ---*/
05256 #define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)
05257 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
05258     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
05259     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
05260     defined(STM32F469xx) || defined(STM32F479xx)
05261 /* Alias word address of I2SSRC bit */
05262 #define RCC_I2SSRC_BIT_NUMBER      0x17
05263 #define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
05264
05265 #define PLLI2S_TIMEOUT_VALUE       ((uint32_t)2)  /* Timeout value fixed to 2 ms  */
05266 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
05267           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
05268
05269 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
05270 /* Alias word address of MCO1EN bit */
05271 #define RCC_MCO1EN_BIT_NUMBER      0x8
05272 #define RCC_CFGR_MCO1EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
05273
05274 /* Alias word address of MCO2EN bit */
05275 #define RCC_MCO2EN_BIT_NUMBER      0x9
05276 #define RCC_CFGR_MCO2EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
05277 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
05278
05279 #define PLL_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */
05280 /**
05281   * @}
05282   */
05283
05284 /**
05285   * @}
05286   */
05287
05288 /* Private macros ------------------------------------------------------------*/
05289 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
05290   * @{
05291   */
05292 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
05293   * @{
05294   */
05295 #if defined(STM32F411xE)
05296 #define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
05297 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
05298 #else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
05299          STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
05300          STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx */
05301 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
05302 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
05303 #endif  /* STM32F411xE */
05304
05305 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
05306 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
05307 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
05308
05309 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
05310     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
05311 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
05312 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
05313
05314 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
05315 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
05316 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
05317
05318 #if defined(STM32F446xx)
05319 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
05320 #endif /* STM32F446xx */
05321
05322 #if defined(STM32F469xx) || defined(STM32F479xx)
05323 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
05324 #endif /* STM32F469xx || STM32F479xx */
05325
05326 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
05327
05328 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
05329     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
05330 #define IS_RCC_PLLI2SQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
05331
05332 #define IS_RCC_PLLSAIN_VALUE(VALUE)     ((50U <= (VALUE)) && ((VALUE) <= 432U))
05333
05334 #define IS_RCC_PLLSAIQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
05335
05336 #define IS_RCC_PLLSAIR_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 7U))
05337
05338 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
05339
05340 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
05341
05342 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2)  ||\
05343                                          ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
05344                                          ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
05345                                          ((VALUE) == RCC_PLLSAIDIVR_16))
05346 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
05347
05348 #if defined(STM32F411xE) || defined(STM32F446xx)
05349 #define IS_RCC_PLLI2SM_VALUE(VALUE)     ((VALUE) <= 63U)
05350
05351 #define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
05352                                          ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
05353 #endif /* STM32F411xE || STM32F446xx */
05354
05355 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
05356 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
05357
05358 #define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
05359                                          ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
05360
05361 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB)    ||\
05362                                            ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
05363                                            ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
05364
05365 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) ||\
05366                                           ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
05367                                           ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
05368                                           ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
05369
05370 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE)      (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR)    ||\
05371                                              ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT)    ||\
05372                                              ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
05373 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
05374
05375 #if defined(STM32F446xx)
05376 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
05377
05378 #define IS_RCC_PLLI2SP_VALUE(VALUE)       (((VALUE) == RCC_PLLI2SP_DIV2) ||\
05379                                            ((VALUE) == RCC_PLLI2SP_DIV4) ||\
05380                                            ((VALUE) == RCC_PLLI2SP_DIV6) ||\
05381                                            ((VALUE) == RCC_PLLI2SP_DIV8))
05382
05383 #define IS_RCC_PLLSAIM_VALUE(VALUE)       ((VALUE) <= 63U)
05384
05385 #define IS_RCC_PLLSAIP_VALUE(VALUE)       (((VALUE) == RCC_PLLSAIP_DIV2) ||\
05386                                            ((VALUE) == RCC_PLLSAIP_DIV4) ||\
05387                                            ((VALUE) == RCC_PLLSAIP_DIV6) ||\
05388                                            ((VALUE) == RCC_PLLSAIP_DIV8))
05389
05390 #define IS_RCC_SAI1CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
05391                                            ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
05392                                            ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR)   ||\
05393                                            ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
05394
05395 #define IS_RCC_SAI2CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
05396                                            ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
05397                                            ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR)   ||\
05398                                            ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
05399
05400 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
05401                                            ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
05402                                            ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
05403                                            ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
05404
05405  #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
05406                                            ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
05407                                            ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
05408                                            ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
05409
05410 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB)    ||\
05411                                            ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
05412                                            ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
05413
05414 #define IS_RCC_CECCLKSOURCE(SOURCE)       (((SOURCE) == RCC_CECCLKSOURCE_HSI)   ||\
05415                                            ((SOURCE) == RCC_CECCLKSOURCE_LSE))
05416
05417 #define IS_RCC_CK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
05418                                            ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
05419
05420 #define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
05421                                            ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
05422
05423 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)   (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
05424                                            ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
05425 #endif /* STM32F446xx */
05426
05427 #if defined(STM32F469xx) || defined(STM32F479xx)
05428 #define IS_RCC_PLLR_VALUE(VALUE)            ((2U <= (VALUE)) && ((VALUE) <= 7U))
05429
05430 #define IS_RCC_PLLSAIP_VALUE(VALUE)         (((VALUE) == RCC_PLLSAIP_DIV2) ||\
05431                                              ((VALUE) == RCC_PLLSAIP_DIV4) ||\
05432                                              ((VALUE) == RCC_PLLSAIP_DIV6) ||\
05433                                              ((VALUE) == RCC_PLLSAIP_DIV8))
05434
05435 #define IS_RCC_CK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
05436                                              ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
05437
05438 #define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
05439                                              ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
05440
05441 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
05442                                              ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
05443
05444 #define IS_RCC_LSE_MODE(MODE)               (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
05445                                              ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
05446 #endif /* STM32F469xx || STM32F479xx */
05447
05448 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
05449     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
05450     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
05451     defined(STM32F469xx) || defined(STM32F479xx)
05452 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
05453                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
05454
05455 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
05456           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
05457
05458 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
05459 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
05460                                    ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
05461 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
05462 /**
05463   * @}
05464   */
05465
05466 /**
05467   * @}
05468   */
05469
05470 /**
05471   * @}
05472   */
05473
05474 /**
05475   * @}
05476   */
05477 #ifdef __cplusplus
05478 }
05479 #endif
05480
05481 #endif /* __STM32F4xx_HAL_RCC_EX_H */
05482
05483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rng.c Source File

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stm32f4xx_hal_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   RNG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Random Number Generator (RNG) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019       The RNG HAL driver can be used as follows:
00020
00021       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00022           in HAL_RNG_MspInit().
00023       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00024       (#) Wait until the 32 bit Random Number Generator contains a valid
00025           random data using (polling/interrupt) mode.
00026       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00033   *
00034   * Redistribution and use in source and binary forms, with or without modification,
00035   * are permitted provided that the following conditions are met:
00036   *   1. Redistributions of source code must retain the above copyright notice,
00037   *      this list of conditions and the following disclaimer.
00038   *   2. Redistributions in binary form must reproduce the above copyright notice,
00039   *      this list of conditions and the following disclaimer in the documentation
00040   *      and/or other materials provided with the distribution.
00041   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00042   *      may be used to endorse or promote products derived from this software
00043   *      without specific prior written permission.
00044   *
00045   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00046   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00047   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00048   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00049   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00050   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00051   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00052   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00053   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00054   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00055   *
00056   ******************************************************************************
00057   */
00058
00059 /* Includes ------------------------------------------------------------------*/
00060 #include "stm32f4xx_hal.h"
00061
00062 /** @addtogroup STM32F4xx_HAL_Driver
00063   * @{
00064   */
00065
00066 /** @addtogroup RNG
00067   * @{
00068   */
00069
00070 #ifdef HAL_RNG_MODULE_ENABLED
00071
00072 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00073     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00074     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
00075     defined(STM32F479xx)
00076
00077
00078 /* Private types -------------------------------------------------------------*/
00079 /* Private defines -----------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private constants ---------------------------------------------------------*/
00082 /** @addtogroup RNG_Private_Constants
00083   * @{
00084   */
00085 #define RNG_TIMEOUT_VALUE     2U
00086 /**
00087   * @}
00088   */
00089 /* Private macros ------------------------------------------------------------*/
00090 /* Private functions prototypes ----------------------------------------------*/
00091 /* Private functions ---------------------------------------------------------*/
00092 /* Exported functions --------------------------------------------------------*/
00093
00094 /** @addtogroup RNG_Exported_Functions
00095   * @{
00096   */
00097
00098 /** @addtogroup RNG_Exported_Functions_Group1
00099  *  @brief   Initialization and de-initialization functions
00100  *
00101 @verbatim
00102  ===============================================================================
00103           ##### Initialization and de-initialization functions #####
00104  ===============================================================================
00105     [..]  This section provides functions allowing to:
00106       (+) Initialize the RNG according to the specified parameters
00107           in the RNG_InitTypeDef and create the associated handle
00108       (+) DeInitialize the RNG peripheral
00109       (+) Initialize the RNG MSP
00110       (+) DeInitialize RNG MSP
00111
00112 @endverbatim
00113   * @{
00114   */
00115
00116 /**
00117   * @brief  Initializes the RNG peripheral and creates the associated handle.
00118   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00119   *                the configuration information for RNG.
00120   * @retval HAL status
00121   */
00122 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00123 {
00124   /* Check the RNG handle allocation */
00125   if(hrng == NULL)
00126   {
00127     return HAL_ERROR;
00128   }
00129
00130   __HAL_LOCK(hrng);
00131
00132   if(hrng->State == HAL_RNG_STATE_RESET)
00133   {
00134     /* Allocate lock resource and initialize it */
00135     hrng->Lock = HAL_UNLOCKED;
00136     /* Init the low level hardware */
00137     HAL_RNG_MspInit(hrng);
00138   }
00139
00140   /* Change RNG peripheral state */
00141   hrng->State = HAL_RNG_STATE_BUSY;
00142
00143   /* Enable the RNG Peripheral */
00144   __HAL_RNG_ENABLE(hrng);
00145
00146   /* Initialize the RNG state */
00147   hrng->State = HAL_RNG_STATE_READY;
00148
00149   __HAL_UNLOCK(hrng);
00150
00151   /* Return function status */
00152   return HAL_OK;
00153 }
00154
00155 /**
00156   * @brief  DeInitializes the RNG peripheral.
00157   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00158   *                the configuration information for RNG.
00159   * @retval HAL status
00160   */
00161 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00162 {
00163   /* Check the RNG handle allocation */
00164   if(hrng == NULL)
00165   {
00166     return HAL_ERROR;
00167   }
00168   /* Disable the RNG Peripheral */
00169   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
00170
00171   /* Clear RNG interrupt status flags */
00172   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00173
00174   /* DeInit the low level hardware */
00175   HAL_RNG_MspDeInit(hrng);
00176
00177   /* Update the RNG state */
00178   hrng->State = HAL_RNG_STATE_RESET;
00179
00180   /* Release Lock */
00181   __HAL_UNLOCK(hrng);
00182
00183   /* Return the function status */
00184   return HAL_OK;
00185 }
00186
00187 /**
00188   * @brief  Initializes the RNG MSP.
00189   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00190   *                the configuration information for RNG.
00191   * @retval None
00192   */
00193 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00194 {
00195   /* Prevent unused argument(s) compilation warning */
00196   UNUSED(hrng);
00197   /* NOTE : This function should not be modified. When the callback is needed,
00198             function HAL_RNG_MspInit must be implemented in the user file.
00199    */
00200 }
00201
00202 /**
00203   * @brief  DeInitializes the RNG MSP.
00204   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00205   *                the configuration information for RNG.
00206   * @retval None
00207   */
00208 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00209 {
00210   /* Prevent unused argument(s) compilation warning */
00211   UNUSED(hrng);
00212   /* NOTE : This function should not be modified. When the callback is needed,
00213             function HAL_RNG_MspDeInit must be implemented in the user file.
00214    */
00215 }
00216
00217 /**
00218   * @}
00219   */
00220
00221 /** @addtogroup RNG_Exported_Functions_Group2
00222  *  @brief   Peripheral Control functions
00223  *
00224 @verbatim
00225  ===============================================================================
00226                       ##### Peripheral Control functions #####
00227  ===============================================================================
00228     [..]  This section provides functions allowing to:
00229       (+) Get the 32 bit Random number
00230       (+) Get the 32 bit Random number with interrupt enabled
00231       (+) Handle RNG interrupt request
00232
00233 @endverbatim
00234   * @{
00235   */
00236
00237 /**
00238   * @brief  Generates a 32-bit random number.
00239   * @note   Each time the random number data is read the RNG_FLAG_DRDY flag
00240   *         is automatically cleared.
00241   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00242   *                the configuration information for RNG.
00243   * @param  random32bit: pointer to generated random number variable if successful.
00244   * @retval HAL status
00245   */
00246
00247 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00248 {
00249   uint32_t tickstart = 0U;
00250   HAL_StatusTypeDef status = HAL_OK;
00251
00252   /* Process Locked */
00253   __HAL_LOCK(hrng);
00254
00255   /* Check RNG peripheral state */
00256   if(hrng->State == HAL_RNG_STATE_READY)
00257   {
00258     /* Change RNG peripheral state */
00259     hrng->State = HAL_RNG_STATE_BUSY;
00260
00261     /* Get tick */
00262     tickstart = HAL_GetTick();
00263
00264     /* Check if data register contains valid random data */
00265     while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00266     {
00267       if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
00268       {
00269         hrng->State = HAL_RNG_STATE_ERROR;
00270
00271         /* Process Unlocked */
00272         __HAL_UNLOCK(hrng);
00273
00274         return HAL_TIMEOUT;
00275       }
00276     }
00277
00278     /* Get a 32bit Random number */
00279     hrng->RandomNumber = hrng->Instance->DR;
00280     *random32bit = hrng->RandomNumber;
00281
00282     hrng->State = HAL_RNG_STATE_READY;
00283   }
00284   else
00285   {
00286     status = HAL_ERROR;
00287   }
00288
00289   /* Process Unlocked */
00290   __HAL_UNLOCK(hrng);
00291
00292   return status;
00293 }
00294
00295 /**
00296   * @brief  Generates a 32-bit random number in interrupt mode.
00297   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00298   *                the configuration information for RNG.
00299   * @retval HAL status
00300   */
00301 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00302 {
00303   HAL_StatusTypeDef status = HAL_OK;
00304
00305   /* Process Locked */
00306   __HAL_LOCK(hrng);
00307
00308   /* Check RNG peripheral state */
00309   if(hrng->State == HAL_RNG_STATE_READY)
00310   {
00311     /* Change RNG peripheral state */
00312     hrng->State = HAL_RNG_STATE_BUSY;
00313
00314     /* Process Unlocked */
00315     __HAL_UNLOCK(hrng);
00316
00317     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00318     __HAL_RNG_ENABLE_IT(hrng);
00319   }
00320   else
00321   {
00322     /* Process Unlocked */
00323     __HAL_UNLOCK(hrng);
00324
00325     status = HAL_ERROR;
00326   }
00327
00328   return status;
00329 }
00330
00331 /**
00332   * @brief  Handles RNG interrupt request.
00333   * @note   In the case of a clock error, the RNG is no more able to generate
00334   *         random numbers because the PLL48CLK clock is not correct. User has
00335   *         to check that the clock controller is correctly configured to provide
00336   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00337   *         The clock error has no impact on the previously generated
00338   *         random numbers, and the RNG_DR register contents can be used.
00339   * @note   In the case of a seed error, the generation of random numbers is
00340   *         interrupted as long as the SECS bit is '1'. If a number is
00341   *         available in the RNG_DR register, it must not be used because it may
00342   *         not have enough entropy. In this case, it is recommended to clear the
00343   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00344   *         the RNG peripheral to reinitialize and restart the RNG.
00345   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00346   *         or CEIS are set.
00347   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00348   *                the configuration information for RNG.
00349   * @retval None
00350
00351   */
00352 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00353 {
00354   /* RNG clock error interrupt occurred */
00355   if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
00356   {
00357     /* Change RNG peripheral state */
00358     hrng->State = HAL_RNG_STATE_ERROR;
00359
00360     HAL_RNG_ErrorCallback(hrng);
00361
00362     /* Clear the clock error flag */
00363     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
00364
00365   }
00366
00367   /* Check RNG data ready interrupt occurred */
00368   if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
00369   {
00370     /* Generate random number once, so disable the IT */
00371     __HAL_RNG_DISABLE_IT(hrng);
00372
00373     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00374     hrng->RandomNumber = hrng->Instance->DR;
00375
00376     if(hrng->State != HAL_RNG_STATE_ERROR)
00377     {
00378       /* Change RNG peripheral state */
00379       hrng->State = HAL_RNG_STATE_READY;
00380
00381       /* Data Ready callback */
00382       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00383     }
00384   }
00385 }
00386
00387 /**
00388   * @brief  Returns generated random number in polling mode (Obsolete)
00389   *         Use HAL_RNG_GenerateRandomNumber() API instead.
00390   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00391   *                the configuration information for RNG.
00392   * @retval Random value
00393   */
00394 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
00395 {
00396   if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
00397   {
00398     return hrng->RandomNumber;
00399   }
00400   else
00401   {
00402     return 0U;
00403   }
00404 }
00405
00406 /**
00407   * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),
00408   *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.
00409   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00410   *                the configuration information for RNG.
00411   * @retval 32-bit random number
00412   */
00413 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
00414 {
00415   uint32_t random32bit = 0U;
00416
00417   /* Process locked */
00418   __HAL_LOCK(hrng);
00419
00420   /* Change RNG peripheral state */
00421   hrng->State = HAL_RNG_STATE_BUSY;
00422
00423   /* Get a 32bit Random number */
00424   random32bit = hrng->Instance->DR;
00425
00426   /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00427   __HAL_RNG_ENABLE_IT(hrng);
00428
00429   /* Return the 32 bit random number */
00430   return random32bit;
00431 }
00432
00433 /**
00434   * @brief  Read latest generated random number.
00435   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00436   *                the configuration information for RNG.
00437   * @retval random value
00438   */
00439 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
00440 {
00441   return(hrng->RandomNumber);
00442 }
00443
00444 /**
00445   * @brief  Data Ready callback in non-blocking mode.
00446   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00447   *                the configuration information for RNG.
00448   * @param  random32bit: generated random number.
00449   * @retval None
00450   */
00451 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(hrng);
00455   UNUSED(random32bit);
00456   /* NOTE : This function should not be modified. When the callback is needed,
00457             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00458    */
00459 }
00460
00461 /**
00462   * @brief  RNG error callbacks.
00463   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00464   *                the configuration information for RNG.
00465   * @retval None
00466   */
00467 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00468 {
00469   /* Prevent unused argument(s) compilation warning */
00470   UNUSED(hrng);
00471   /* NOTE : This function should not be modified. When the callback is needed,
00472             function HAL_RNG_ErrorCallback must be implemented in the user file.
00473    */
00474 }
00475 /**
00476   * @}
00477   */
00478
00479
00480 /** @addtogroup RNG_Exported_Functions_Group3
00481  *  @brief   Peripheral State functions
00482  *
00483 @verbatim
00484  ===============================================================================
00485                       ##### Peripheral State functions #####
00486  ===============================================================================
00487     [..]
00488     This subsection permits to get in run-time the status of the peripheral
00489     and the data flow.
00490
00491 @endverbatim
00492   * @{
00493   */
00494
00495 /**
00496   * @brief  Returns the RNG state.
00497   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00498   *                the configuration information for RNG.
00499   * @retval HAL state
00500   */
00501 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
00502 {
00503   return hrng->State;
00504 }
00505
00506 /**
00507   * @}
00508   */
00509
00510 /**
00511   * @}
00512   */
00513
00514 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00515           STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */
00516
00517 #endif /* HAL_RNG_MODULE_ENABLED */
00518
00519 /**
00520   * @}
00521   */
00522
00523 /**
00524   * @}
00525   */
00526
00527 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rng.h Source File

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stm32f4xx_hal_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of RNG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_RNG_H
00040 #define __STM32F4xx_HAL_RNG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00047     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00048     defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
00049     defined(STM32F479xx)
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32f4xx_hal_def.h"
00053
00054 /** @addtogroup STM32F4xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @defgroup RNG RNG
00059   * @brief RNG HAL module driver
00060   * @{
00061   */
00062
00063 /* Exported types ------------------------------------------------------------*/
00064
00065 /** @defgroup RNG_Exported_Types RNG Exported Types
00066   * @{
00067   */
00068
00069 /** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
00070   * @{
00071   */
00072 typedef enum
00073 {
00074   HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
00075   HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
00076   HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
00077   HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
00078   HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
00079
00080 }HAL_RNG_StateTypeDef;
00081
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
00087   * @{
00088   */
00089 typedef struct
00090 {
00091   RNG_TypeDef                 *Instance;    /*!< Register base address   */
00092
00093   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
00094
00095   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
00096
00097   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
00098
00099 }RNG_HandleTypeDef;
00100
00101 /**
00102   * @}
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 /* Exported constants --------------------------------------------------------*/
00110
00111 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00112   * @{
00113   */
00114
00115 /** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
00116   * @{
00117   */
00118 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00119 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00120 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
00126   * @{
00127   */
00128 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00129 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00130 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00131
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140 /* Exported macros -----------------------------------------------------------*/
00141
00142 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00143   * @{
00144   */
00145
00146 /** @brief Reset RNG handle state
00147   * @param  __HANDLE__: RNG Handle
00148   * @retval None
00149   */
00150 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00151
00152 /**
00153   * @brief  Enables the RNG peripheral.
00154   * @param  __HANDLE__: RNG Handle
00155   * @retval None
00156   */
00157 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00158
00159 /**
00160   * @brief  Disables the RNG peripheral.
00161   * @param  __HANDLE__: RNG Handle
00162   * @retval None
00163   */
00164 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00165
00166 /**
00167   * @brief  Check the selected RNG flag status.
00168   * @param  __HANDLE__: RNG Handle
00169   * @param  __FLAG__: RNG flag
00170   *          This parameter can be one of the following values:
00171   *            @arg RNG_FLAG_DRDY: Data ready
00172   *            @arg RNG_FLAG_CECS: Clock error current status
00173   *            @arg RNG_FLAG_SECS: Seed error current status
00174   * @retval The new state of __FLAG__ (SET or RESET).
00175   */
00176 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00177
00178 /**
00179   * @brief  Clears the selected RNG flag status.
00180   * @param  __HANDLE__: RNG handle
00181   * @param  __FLAG__: RNG flag to clear
00182   * @note   WARNING: This is a dummy macro for HAL code alignment,
00183   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00184   * @retval None
00185   */
00186 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00187
00188
00189
00190 /**
00191   * @brief  Enables the RNG interrupts.
00192   * @param  __HANDLE__: RNG Handle
00193   * @retval None
00194   */
00195 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00196
00197 /**
00198   * @brief  Disables the RNG interrupts.
00199   * @param  __HANDLE__: RNG Handle
00200   * @retval None
00201   */
00202 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00203
00204 /**
00205   * @brief  Checks whether the specified RNG interrupt has occurred or not.
00206   * @param  __HANDLE__: RNG Handle
00207   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
00208   *         This parameter can be one of the following values:
00209   *            @arg RNG_IT_DRDY: Data ready interrupt
00210   *            @arg RNG_IT_CEI: Clock error interrupt
00211   *            @arg RNG_IT_SEI: Seed error interrupt
00212   * @retval The new state of __INTERRUPT__ (SET or RESET).
00213   */
00214 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00215
00216 /**
00217   * @brief  Clear the RNG interrupt status flags.
00218   * @param  __HANDLE__: RNG Handle
00219   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
00220   *          This parameter can be one of the following values:
00221   *            @arg RNG_IT_CEI: Clock error interrupt
00222   *            @arg RNG_IT_SEI: Seed error interrupt
00223   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00224   * @retval None
00225   */
00226 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00227
00228 /**
00229   * @}
00230   */
00231
00232 /* Exported functions --------------------------------------------------------*/
00233 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00234   * @{
00235   */
00236
00237 /** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
00238   * @{
00239   */
00240 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00241 HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
00242 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00243 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00244
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00250   * @{
00251   */
00252 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
00253 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
00254
00255 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00256 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00257 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
00258
00259 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00260 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00261 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
00262
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00268   * @{
00269   */
00270 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
00271
00272 /**
00273   * @}
00274   */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /* Private types -------------------------------------------------------------*/
00281 /** @defgroup RNG_Private_Types RNG Private Types
00282   * @{
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /* Private defines -----------------------------------------------------------*/
00290 /** @defgroup RNG_Private_Defines RNG Private Defines
00291   * @{
00292   */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /* Private variables ---------------------------------------------------------*/
00299 /** @defgroup RNG_Private_Variables RNG Private Variables
00300   * @{
00301   */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /* Private constants ---------------------------------------------------------*/
00308 /** @defgroup RNG_Private_Constants RNG Private Constants
00309   * @{
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /* Private macros ------------------------------------------------------------*/
00317 /** @defgroup RNG_Private_Macros RNG Private Macros
00318   * @{
00319   */
00320 #define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
00321                        ((IT) == RNG_IT_SEI))
00322
00323 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
00324                            ((FLAG) == RNG_FLAG_CECS) || \
00325                            ((FLAG) == RNG_FLAG_SECS))
00326
00327 /**
00328   * @}
00329   */
00330
00331 /* Private functions prototypes ----------------------------------------------*/
00332 /** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
00333   * @{
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 /* Private functions ---------------------------------------------------------*/
00341 /** @defgroup RNG_Private_Functions RNG Private Functions
00342   * @{
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /**
00350   * @}
00351   */
00352
00353 /**
00354   * @}
00355   */
00356
00357 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00358           STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */
00359
00360 #ifdef __cplusplus
00361 }
00362 #endif
00363
00364
00365 #endif /* __STM32F4xx_HAL_RNG_H */
00366
00367 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc.c Source File

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stm32f4xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + RTC Time and Date functions
00012   *           + RTC Alarm functions
00013   *           + Peripheral Control functions
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018               ##### Backup Domain Operating Condition #####
00019   ==============================================================================
00020   [..] The real-time clock (RTC), the RTC backup registers, and the backup
00021        SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
00022        VDD supply is powered off.
00023        To retain the content of the RTC backup registers, backup SRAM, and supply
00024        the RTC when VDD is turned off, VBAT pin can be connected to an optional
00025        standby voltage supplied by a battery or by another source.
00026
00027   [..] To allow the RTC operating even when the main digital supply (VDD) is turned
00028        off, the VBAT pin powers the following blocks:
00029     (#) The RTC
00030     (#) The LSE oscillator
00031     (#) The backup SRAM when the low power backup regulator is enabled
00032     (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
00033
00034   [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
00035        the following pins are available:
00036     (#) PC14 and PC15 can be used as either GPIO or LSE pins
00037     (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
00038     (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
00039
00040   [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
00041        because VDD is not present), the following pins are available:
00042     (#) PC14 and PC15 can be used as LSE pins only
00043     (#) PC13 can be used as the RTC_AF1 pin
00044     (#) PI8 can be used as the RTC_AF2 pin
00045
00046                    ##### Backup Domain Reset #####
00047   ==================================================================
00048   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00049        to their reset values. The BKPSRAM is not affected by this reset. The only
00050        way to reset the BKPSRAM is through the Flash interface by requesting
00051        a protection level change from 1 to 0.
00052   [..] A backup domain reset is generated when one of the following events occurs:
00053     (#) Software reset, triggered by setting the BDRST bit in the
00054         RCC Backup domain control register (RCC_BDCR).
00055     (#) VDD or VBAT power on, if both supplies have previously been powered off.
00056
00057                    ##### Backup Domain Access #####
00058   ==================================================================
00059   [..] After reset, the backup domain (RTC registers, RTC backup data
00060        registers and backup SRAM) is protected against possible unwanted write
00061        accesses.
00062   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00063     (+) Enable the Power Controller (PWR) APB1 interface clock using the
00064         __HAL_RCC_PWR_CLK_ENABLE() function.
00065     (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00066     (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
00067     (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
00068
00069
00070                   ##### How to use this driver #####
00071   ==================================================================
00072   [..]
00073     (+) Enable the RTC domain access (see description in the section above).
00074     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00075         format using the HAL_RTC_Init() function.
00076
00077   *** Time and Date configuration ***
00078   ===================================
00079   [..]
00080     (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00081         and HAL_RTC_SetDate() functions.
00082     (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00083
00084   *** Alarm configuration ***
00085   ===========================
00086   [..]
00087     (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00088         You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
00089     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00090
00091                   ##### RTC and low power modes #####
00092   ==================================================================
00093   [..] The MCU can be woken up from a low power mode by an RTC alternate
00094        function.
00095   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00096        RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
00097        These RTC alternate functions can wake up the system from the Stop and
00098        Standby low power modes.
00099   [..] The system can also wake up from low power modes without depending
00100        on an external interrupt (Auto-wake-up mode), by using the RTC alarm
00101        or the RTC wake-up events.
00102   [..] The RTC provides a programmable time base for waking up from the
00103        Stop or Standby mode at regular intervals.
00104        Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
00105        is LSE or LSI.
00106
00107    @endverbatim
00108   ******************************************************************************
00109   * @attention
00110   *
00111   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00112   *
00113   * Redistribution and use in source and binary forms, with or without modification,
00114   * are permitted provided that the following conditions are met:
00115   *   1. Redistributions of source code must retain the above copyright notice,
00116   *      this list of conditions and the following disclaimer.
00117   *   2. Redistributions in binary form must reproduce the above copyright notice,
00118   *      this list of conditions and the following disclaimer in the documentation
00119   *      and/or other materials provided with the distribution.
00120   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00121   *      may be used to endorse or promote products derived from this software
00122   *      without specific prior written permission.
00123   *
00124   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00125   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00126   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00127   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00128   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00129   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00130   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00131   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00132   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00133   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00134   *
00135   ******************************************************************************
00136   */
00137
00138 /* Includes ------------------------------------------------------------------*/
00139 #include "stm32f4xx_hal.h"
00140
00141 /** @addtogroup STM32F4xx_HAL_Driver
00142   * @{
00143   */
00144
00145 /** @defgroup RTC RTC
00146   * @brief RTC HAL module driver
00147   * @{
00148   */
00149
00150 #ifdef HAL_RTC_MODULE_ENABLED
00151
00152 /* Private typedef -----------------------------------------------------------*/
00153 /* Private define ------------------------------------------------------------*/
00154 /* Private macro -------------------------------------------------------------*/
00155 /* Private variables ---------------------------------------------------------*/
00156 /* Private function prototypes -----------------------------------------------*/
00157 /* Private functions ---------------------------------------------------------*/
00158
00159 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00160   * @{
00161   */
00162
00163 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00164  *  @brief    Initialization and Configuration functions
00165  *
00166 @verbatim
00167  ===============================================================================
00168               ##### Initialization and de-initialization functions #####
00169  ===============================================================================
00170    [..] This section provides functions allowing to initialize and configure the
00171          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00172          RTC registers Write protection, enter and exit the RTC initialization mode,
00173          RTC registers synchronization check and reference clock detection enable.
00174          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00175              It is split into 2 programmable prescalers to minimize power consumption.
00176              (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
00177              (++) When both prescalers are used, it is recommended to configure the
00178                  asynchronous prescaler to a high value to minimize power consumption.
00179          (#) All RTC registers are Write protected. Writing to the RTC registers
00180              is enabled by writing a key into the Write Protection register, RTC_WPR.
00181          (#) To configure the RTC Calendar, user application should enter
00182              initialization mode. In this mode, the calendar counter is stopped
00183              and its value can be updated. When the initialization sequence is
00184              complete, the calendar restarts counting after 4 RTCCLK cycles.
00185          (#) To read the calendar through the shadow registers after Calendar
00186              initialization, calendar update or after wake-up from low power modes
00187              the software must first clear the RSF flag. The software must then
00188              wait until it is set again before reading the calendar, which means
00189              that the calendar registers have been correctly copied into the
00190              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00191              implements the above software sequence (RSF clear and RSF check).
00192
00193 @endverbatim
00194   * @{
00195   */
00196
00197 /**
00198   * @brief  Initializes the RTC peripheral
00199   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00200   *                the configuration information for RTC.
00201   * @retval HAL status
00202   */
00203 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00204 {
00205   /* Check the RTC peripheral state */
00206   if(hrtc == NULL)
00207   {
00208      return HAL_ERROR;
00209   }
00210
00211   /* Check the parameters */
00212   assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00213   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00214   assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00215   assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
00216   assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00217   assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00218
00219   if(hrtc->State == HAL_RTC_STATE_RESET)
00220   {
00221     /* Allocate lock resource and initialize it */
00222     hrtc->Lock = HAL_UNLOCKED;
00223     /* Initialize RTC MSP */
00224     HAL_RTC_MspInit(hrtc);
00225   }
00226
00227   /* Set RTC state */
00228   hrtc->State = HAL_RTC_STATE_BUSY;
00229
00230   /* Disable the write protection for RTC registers */
00231   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00232
00233   /* Set Initialization mode */
00234   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00235   {
00236     /* Enable the write protection for RTC registers */
00237     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00238
00239     /* Set RTC state */
00240     hrtc->State = HAL_RTC_STATE_ERROR;
00241
00242     return HAL_ERROR;
00243   }
00244   else
00245   {
00246     /* Clear RTC_CR FMT, OSEL and POL Bits */
00247     hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
00248     /* Set RTC_CR register */
00249     hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00250
00251     /* Configure the RTC PRER */
00252     hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
00253     hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
00254
00255     /* Exit Initialization mode */
00256     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
00257
00258     hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
00259     hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
00260
00261     /* Enable the write protection for RTC registers */
00262     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00263
00264     /* Set RTC state */
00265     hrtc->State = HAL_RTC_STATE_READY;
00266
00267     return HAL_OK;
00268   }
00269 }
00270
00271 /**
00272   * @brief  DeInitializes the RTC peripheral
00273   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00274   *                the configuration information for RTC.
00275   * @note   This function doesn't reset the RTC Backup Data registers.
00276   * @retval HAL status
00277   */
00278 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00279 {
00280   uint32_t tickstart = 0U;
00281
00282   /* Set RTC state */
00283   hrtc->State = HAL_RTC_STATE_BUSY;
00284
00285   /* Disable the write protection for RTC registers */
00286   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00287
00288   /* Set Initialization mode */
00289   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00290   {
00291     /* Enable the write protection for RTC registers */
00292     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00293
00294     /* Set RTC state */
00295     hrtc->State = HAL_RTC_STATE_ERROR;
00296
00297     return HAL_ERROR;
00298   }
00299   else
00300   {
00301     /* Reset TR, DR and CR registers */
00302     hrtc->Instance->TR = (uint32_t)0x00000000U;
00303     hrtc->Instance->DR = (uint32_t)0x00002101U;
00304     /* Reset All CR bits except CR[2:0] */
00305     hrtc->Instance->CR &= (uint32_t)0x00000007U;
00306
00307     /* Get tick */
00308     tickstart = HAL_GetTick();
00309
00310     /* Wait till WUTWF flag is set and if Time out is reached exit */
00311     while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
00312     {
00313       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00314       {
00315         /* Enable the write protection for RTC registers */
00316         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00317
00318         /* Set RTC state */
00319         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00320
00321         return HAL_TIMEOUT;
00322       }
00323     }
00324
00325     /* Reset all RTC CR register bits */
00326     hrtc->Instance->CR &= (uint32_t)0x00000000U;
00327     hrtc->Instance->WUTR = (uint32_t)0x0000FFFFU;
00328     hrtc->Instance->PRER = (uint32_t)0x007F00FFU;
00329     hrtc->Instance->CALIBR = (uint32_t)0x00000000U;
00330     hrtc->Instance->ALRMAR = (uint32_t)0x00000000U;
00331     hrtc->Instance->ALRMBR = (uint32_t)0x00000000U;
00332     hrtc->Instance->SHIFTR = (uint32_t)0x00000000U;
00333     hrtc->Instance->CALR = (uint32_t)0x00000000U;
00334     hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U;
00335     hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U;
00336
00337     /* Reset ISR register and exit initialization mode */
00338     hrtc->Instance->ISR = (uint32_t)0x00000000U;
00339
00340     /* Reset Tamper and alternate functions configuration register */
00341     hrtc->Instance->TAFCR = 0x00000000U;
00342
00343     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00344     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00345     {
00346       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00347       {
00348         /* Enable the write protection for RTC registers */
00349         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00350
00351         hrtc->State = HAL_RTC_STATE_ERROR;
00352
00353         return HAL_ERROR;
00354       }
00355     }
00356   }
00357
00358   /* Enable the write protection for RTC registers */
00359   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00360
00361   /* De-Initialize RTC MSP */
00362   HAL_RTC_MspDeInit(hrtc);
00363
00364   hrtc->State = HAL_RTC_STATE_RESET;
00365
00366   /* Release Lock */
00367   __HAL_UNLOCK(hrtc);
00368
00369   return HAL_OK;
00370 }
00371
00372 /**
00373   * @brief  Initializes the RTC MSP.
00374   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00375   *                the configuration information for RTC.
00376   * @retval None
00377   */
00378 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00379 {
00380   /* Prevent unused argument(s) compilation warning */
00381   UNUSED(hrtc);
00382   /* NOTE : This function Should not be modified, when the callback is needed,
00383             the HAL_RTC_MspInit could be implemented in the user file
00384    */
00385 }
00386
00387 /**
00388   * @brief  DeInitializes the RTC MSP.
00389   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00390   *                the configuration information for RTC.
00391   * @retval None
00392   */
00393 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00394 {
00395   /* Prevent unused argument(s) compilation warning */
00396   UNUSED(hrtc);
00397   /* NOTE : This function Should not be modified, when the callback is needed,
00398             the HAL_RTC_MspDeInit could be implemented in the user file
00399    */
00400 }
00401
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
00407  *  @brief   RTC Time and Date functions
00408  *
00409 @verbatim
00410  ===============================================================================
00411                  ##### RTC Time and Date functions #####
00412  ===============================================================================
00413
00414  [..] This section provides functions allowing to configure Time and Date features
00415
00416 @endverbatim
00417   * @{
00418   */
00419
00420 /**
00421   * @brief  Sets RTC current time.
00422   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00423   *                the configuration information for RTC.
00424   * @param  sTime: Pointer to Time structure
00425   * @param  Format: Specifies the format of the entered parameters.
00426   *          This parameter can be one of the following values:
00427   *            @arg RTC_FORMAT_BIN: Binary data format
00428   *            @arg RTC_FORMAT_BCD: BCD data format
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00432 {
00433   uint32_t tmpreg = 0U;
00434
00435  /* Check the parameters */
00436   assert_param(IS_RTC_FORMAT(Format));
00437   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00438   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00439
00440   /* Process Locked */
00441   __HAL_LOCK(hrtc);
00442
00443   hrtc->State = HAL_RTC_STATE_BUSY;
00444
00445   if(Format == RTC_FORMAT_BIN)
00446   {
00447     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00448     {
00449       assert_param(IS_RTC_HOUR12(sTime->Hours));
00450       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00451     }
00452     else
00453     {
00454       sTime->TimeFormat = 0x00U;
00455       assert_param(IS_RTC_HOUR24(sTime->Hours));
00456     }
00457     assert_param(IS_RTC_MINUTES(sTime->Minutes));
00458     assert_param(IS_RTC_SECONDS(sTime->Seconds));
00459
00460     tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
00461                         ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
00462                         ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
00463                         (((uint32_t)sTime->TimeFormat) << 16U));
00464   }
00465   else
00466   {
00467     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00468     {
00469       tmpreg = RTC_Bcd2ToByte(sTime->Hours);
00470       assert_param(IS_RTC_HOUR12(tmpreg));
00471       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00472     }
00473     else
00474     {
00475       sTime->TimeFormat = 0x00U;
00476       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00477     }
00478     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00479     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00480     tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
00481               ((uint32_t)(sTime->Minutes) << 8U) | \
00482               ((uint32_t)sTime->Seconds) | \
00483               ((uint32_t)(sTime->TimeFormat) << 16U));
00484   }
00485
00486   /* Disable the write protection for RTC registers */
00487   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00488
00489   /* Set Initialization mode */
00490   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00491   {
00492     /* Enable the write protection for RTC registers */
00493     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00494
00495     /* Set RTC state */
00496     hrtc->State = HAL_RTC_STATE_ERROR;
00497
00498     /* Process Unlocked */
00499     __HAL_UNLOCK(hrtc);
00500
00501     return HAL_ERROR;
00502   }
00503   else
00504   {
00505     /* Set the RTC_TR register */
00506     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00507
00508     /* Clear the bits to be configured */
00509     hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
00510
00511     /* Configure the RTC_CR register */
00512     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00513
00514     /* Exit Initialization mode */
00515     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
00516
00517     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00518     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00519     {
00520       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00521       {
00522         /* Enable the write protection for RTC registers */
00523         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00524
00525         hrtc->State = HAL_RTC_STATE_ERROR;
00526
00527         /* Process Unlocked */
00528         __HAL_UNLOCK(hrtc);
00529
00530         return HAL_ERROR;
00531       }
00532     }
00533
00534     /* Enable the write protection for RTC registers */
00535     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00536
00537    hrtc->State = HAL_RTC_STATE_READY;
00538
00539    __HAL_UNLOCK(hrtc);
00540
00541    return HAL_OK;
00542   }
00543 }
00544
00545 /**
00546   * @brief  Gets RTC current time.
00547   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00548   *                the configuration information for RTC.
00549   * @param  sTime: Pointer to Time structure
00550   * @param  Format: Specifies the format of the entered parameters.
00551   *          This parameter can be one of the following values:
00552   *            @arg RTC_FORMAT_BIN: Binary data format
00553   *            @arg RTC_FORMAT_BCD: BCD data format
00554   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00555   *        value in second fraction ratio with time unit following generic formula:
00556   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00557   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00558   * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00559   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00560   *        Reading RTC current time locks the values in calendar shadow registers until current date is read.
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00564 {
00565   uint32_t tmpreg = 0U;
00566
00567   /* Check the parameters */
00568   assert_param(IS_RTC_FORMAT(Format));
00569
00570   /* Get subseconds structure field from the corresponding register */
00571   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
00572
00573   /* Get SecondFraction structure field from the corresponding register field*/
00574   sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
00575
00576   /* Get the TR register */
00577   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
00578
00579   /* Fill the structure fields with the read parameters */
00580   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
00581   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
00582   sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
00583   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
00584
00585   /* Check the input parameters format */
00586   if(Format == RTC_FORMAT_BIN)
00587   {
00588     /* Convert the time structure parameters to Binary format */
00589     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
00590     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
00591     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
00592   }
00593
00594   return HAL_OK;
00595 }
00596
00597 /**
00598   * @brief  Sets RTC current date.
00599   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00600   *                the configuration information for RTC.
00601   * @param  sDate: Pointer to date structure
00602   * @param  Format: specifies the format of the entered parameters.
00603   *          This parameter can be one of the following values:
00604   *            @arg RTC_FORMAT_BIN: Binary data format
00605   *            @arg RTC_FORMAT_BCD: BCD data format
00606   * @retval HAL status
00607   */
00608 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00609 {
00610   uint32_t datetmpreg = 0U;
00611
00612  /* Check the parameters */
00613   assert_param(IS_RTC_FORMAT(Format));
00614
00615  /* Process Locked */
00616  __HAL_LOCK(hrtc);
00617
00618   hrtc->State = HAL_RTC_STATE_BUSY;
00619
00620   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
00621   {
00622     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
00623   }
00624
00625   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
00626
00627   if(Format == RTC_FORMAT_BIN)
00628   {
00629     assert_param(IS_RTC_YEAR(sDate->Year));
00630     assert_param(IS_RTC_MONTH(sDate->Month));
00631     assert_param(IS_RTC_DATE(sDate->Date));
00632
00633    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
00634                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
00635                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
00636                  ((uint32_t)sDate->WeekDay << 13U));
00637   }
00638   else
00639   {
00640     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00641     datetmpreg = RTC_Bcd2ToByte(sDate->Month);
00642     assert_param(IS_RTC_MONTH(datetmpreg));
00643     datetmpreg = RTC_Bcd2ToByte(sDate->Date);
00644     assert_param(IS_RTC_DATE(datetmpreg));
00645
00646     datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
00647                   (((uint32_t)sDate->Month) << 8U) | \
00648                   ((uint32_t)sDate->Date) | \
00649                   (((uint32_t)sDate->WeekDay) << 13U));
00650   }
00651
00652   /* Disable the write protection for RTC registers */
00653   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00654
00655   /* Set Initialization mode */
00656   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00657   {
00658     /* Enable the write protection for RTC registers */
00659     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00660
00661     /* Set RTC state*/
00662     hrtc->State = HAL_RTC_STATE_ERROR;
00663
00664     /* Process Unlocked */
00665     __HAL_UNLOCK(hrtc);
00666
00667     return HAL_ERROR;
00668   }
00669   else
00670   {
00671     /* Set the RTC_DR register */
00672     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
00673
00674     /* Exit Initialization mode */
00675     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
00676
00677     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00678     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00679     {
00680       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00681       {
00682         /* Enable the write protection for RTC registers */
00683         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00684
00685         hrtc->State = HAL_RTC_STATE_ERROR;
00686
00687         /* Process Unlocked */
00688         __HAL_UNLOCK(hrtc);
00689
00690         return HAL_ERROR;
00691       }
00692     }
00693
00694     /* Enable the write protection for RTC registers */
00695     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00696
00697     hrtc->State = HAL_RTC_STATE_READY ;
00698
00699     /* Process Unlocked */
00700     __HAL_UNLOCK(hrtc);
00701
00702     return HAL_OK;
00703   }
00704 }
00705
00706 /**
00707   * @brief  Gets RTC current date.
00708   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00709   *                the configuration information for RTC.
00710   * @param  sDate: Pointer to Date structure
00711   * @param  Format: Specifies the format of the entered parameters.
00712   *          This parameter can be one of the following values:
00713   *            @arg RTC_FORMAT_BIN:  Binary data format
00714   *            @arg RTC_FORMAT_BCD:  BCD data format
00715   * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00716   * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00717   * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
00718   * @retval HAL status
00719   */
00720 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00721 {
00722   uint32_t datetmpreg = 0U;
00723
00724   /* Check the parameters */
00725   assert_param(IS_RTC_FORMAT(Format));
00726
00727   /* Get the DR register */
00728   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
00729
00730   /* Fill the structure fields with the read parameters */
00731   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
00732   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
00733   sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
00734   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
00735
00736   /* Check the input parameters format */
00737   if(Format == RTC_FORMAT_BIN)
00738   {
00739     /* Convert the date structure parameters to Binary format */
00740     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
00741     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
00742     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
00743   }
00744   return HAL_OK;
00745 }
00746
00747 /**
00748   * @}
00749   */
00750
00751 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
00752  *  @brief   RTC Alarm functions
00753  *
00754 @verbatim
00755  ===============================================================================
00756                  ##### RTC Alarm functions #####
00757  ===============================================================================
00758
00759  [..] This section provides functions allowing to configure Alarm feature
00760
00761 @endverbatim
00762   * @{
00763   */
00764 /**
00765   * @brief  Sets the specified RTC Alarm.
00766   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00767   *                the configuration information for RTC.
00768   * @param  sAlarm: Pointer to Alarm structure
00769   * @param  Format: Specifies the format of the entered parameters.
00770   *          This parameter can be one of the following values:
00771   *             @arg RTC_FORMAT_BIN: Binary data format
00772   *             @arg RTC_FORMAT_BCD: BCD data format
00773   * @retval HAL status
00774   */
00775 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00776 {
00777   uint32_t tickstart = 0U;
00778   uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
00779
00780   /* Check the parameters */
00781   assert_param(IS_RTC_FORMAT(Format));
00782   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00783   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00784   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00785   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00786   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00787
00788   /* Process Locked */
00789   __HAL_LOCK(hrtc);
00790
00791   hrtc->State = HAL_RTC_STATE_BUSY;
00792
00793   if(Format == RTC_FORMAT_BIN)
00794   {
00795     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00796     {
00797       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00798       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00799     }
00800     else
00801     {
00802       sAlarm->AlarmTime.TimeFormat = 0x00U;
00803       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00804     }
00805     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00806     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00807
00808     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00809     {
00810       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00811     }
00812     else
00813     {
00814       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
00815     }
00816
00817     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
00818               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
00819               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
00820               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
00821               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
00822               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00823               ((uint32_t)sAlarm->AlarmMask));
00824   }
00825   else
00826   {
00827     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00828     {
00829       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
00830       assert_param(IS_RTC_HOUR12(tmpreg));
00831       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00832     }
00833     else
00834     {
00835       sAlarm->AlarmTime.TimeFormat = 0x00U;
00836       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
00837     }
00838
00839     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
00840     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
00841
00842     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00843     {
00844       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00845       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
00846     }
00847     else
00848     {
00849       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00850       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
00851     }
00852
00853     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
00854               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
00855               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
00856               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
00857               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
00858               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00859               ((uint32_t)sAlarm->AlarmMask));
00860   }
00861
00862   /* Configure the Alarm A or Alarm B Sub Second registers */
00863   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
00864
00865   /* Disable the write protection for RTC registers */
00866   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00867
00868   /* Configure the Alarm register */
00869   if(sAlarm->Alarm == RTC_ALARM_A)
00870   {
00871     /* Disable the Alarm A interrupt */
00872     __HAL_RTC_ALARMA_DISABLE(hrtc);
00873
00874     /* In case of interrupt mode is used, the interrupt source must disabled */
00875     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
00876
00877     /* Get tick */
00878     tickstart = HAL_GetTick();
00879
00880     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
00881     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
00882     {
00883       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00884       {
00885         /* Enable the write protection for RTC registers */
00886         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00887
00888         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00889
00890         /* Process Unlocked */
00891         __HAL_UNLOCK(hrtc);
00892
00893         return HAL_TIMEOUT;
00894       }
00895     }
00896
00897     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
00898     /* Configure the Alarm A Sub Second register */
00899     hrtc->Instance->ALRMASSR = subsecondtmpreg;
00900     /* Configure the Alarm state: Enable Alarm */
00901     __HAL_RTC_ALARMA_ENABLE(hrtc);
00902   }
00903   else
00904   {
00905     /* Disable the Alarm B interrupt */
00906     __HAL_RTC_ALARMB_DISABLE(hrtc);
00907
00908     /* In case of interrupt mode is used, the interrupt source must disabled */
00909     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
00910
00911     /* Get tick */
00912     tickstart = HAL_GetTick();
00913
00914     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
00915     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
00916     {
00917       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00918       {
00919         /* Enable the write protection for RTC registers */
00920         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00921
00922         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00923
00924         /* Process Unlocked */
00925         __HAL_UNLOCK(hrtc);
00926
00927         return HAL_TIMEOUT;
00928       }
00929     }
00930
00931     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
00932     /* Configure the Alarm B Sub Second register */
00933     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
00934     /* Configure the Alarm state: Enable Alarm */
00935     __HAL_RTC_ALARMB_ENABLE(hrtc);
00936   }
00937
00938   /* Enable the write protection for RTC registers */
00939   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00940
00941   /* Change RTC state */
00942   hrtc->State = HAL_RTC_STATE_READY;
00943
00944   /* Process Unlocked */
00945   __HAL_UNLOCK(hrtc);
00946
00947   return HAL_OK;
00948 }
00949
00950 /**
00951   * @brief  Sets the specified RTC Alarm with Interrupt
00952   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00953   *                the configuration information for RTC.
00954   * @param  sAlarm: Pointer to Alarm structure
00955   * @param  Format: Specifies the format of the entered parameters.
00956   *          This parameter can be one of the following values:
00957   *             @arg RTC_FORMAT_BIN: Binary data format
00958   *             @arg RTC_FORMAT_BCD: BCD data format
00959   * @retval HAL status
00960   */
00961 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00962 {
00963   uint32_t tickstart = 0U;
00964   uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
00965
00966   /* Check the parameters */
00967   assert_param(IS_RTC_FORMAT(Format));
00968   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00969   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00970   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00971   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00972   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00973
00974   /* Process Locked */
00975   __HAL_LOCK(hrtc);
00976
00977   hrtc->State = HAL_RTC_STATE_BUSY;
00978
00979   if(Format == RTC_FORMAT_BIN)
00980   {
00981     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00982     {
00983       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00984       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00985     }
00986     else
00987     {
00988       sAlarm->AlarmTime.TimeFormat = 0x00U;
00989       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00990     }
00991     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00992     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00993
00994     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00995     {
00996       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00997     }
00998     else
00999     {
01000       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01001     }
01002     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
01003               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
01004               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
01005               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01006               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
01007               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01008               ((uint32_t)sAlarm->AlarmMask));
01009   }
01010   else
01011   {
01012     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
01013     {
01014       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01015       assert_param(IS_RTC_HOUR12(tmpreg));
01016       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01017     }
01018     else
01019     {
01020       sAlarm->AlarmTime.TimeFormat = 0x00U;
01021       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01022     }
01023
01024     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01025     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01026
01027     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01028     {
01029       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01030       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
01031     }
01032     else
01033     {
01034       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01035       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
01036     }
01037     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
01038               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
01039               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
01040               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01041               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
01042               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01043               ((uint32_t)sAlarm->AlarmMask));
01044   }
01045   /* Configure the Alarm A or Alarm B Sub Second registers */
01046   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01047
01048   /* Disable the write protection for RTC registers */
01049   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01050
01051   /* Configure the Alarm register */
01052   if(sAlarm->Alarm == RTC_ALARM_A)
01053   {
01054     /* Disable the Alarm A interrupt */
01055     __HAL_RTC_ALARMA_DISABLE(hrtc);
01056
01057     /* Clear flag alarm A */
01058     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01059
01060     /* Get tick */
01061     tickstart = HAL_GetTick();
01062
01063     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01064     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01065     {
01066       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01067       {
01068         /* Enable the write protection for RTC registers */
01069         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01070
01071         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01072
01073         /* Process Unlocked */
01074         __HAL_UNLOCK(hrtc);
01075
01076         return HAL_TIMEOUT;
01077       }
01078     }
01079
01080     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01081     /* Configure the Alarm A Sub Second register */
01082     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01083     /* Configure the Alarm state: Enable Alarm */
01084     __HAL_RTC_ALARMA_ENABLE(hrtc);
01085     /* Configure the Alarm interrupt */
01086     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01087   }
01088   else
01089   {
01090     /* Disable the Alarm B interrupt */
01091     __HAL_RTC_ALARMB_DISABLE(hrtc);
01092
01093     /* Clear flag alarm B */
01094     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01095
01096     /* Get tick */
01097     tickstart = HAL_GetTick();
01098
01099     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01100     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01101     {
01102       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01103       {
01104         /* Enable the write protection for RTC registers */
01105         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01106
01107         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01108
01109         /* Process Unlocked */
01110         __HAL_UNLOCK(hrtc);
01111
01112         return HAL_TIMEOUT;
01113       }
01114     }
01115
01116     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01117     /* Configure the Alarm B Sub Second register */
01118     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01119     /* Configure the Alarm state: Enable Alarm */
01120     __HAL_RTC_ALARMB_ENABLE(hrtc);
01121     /* Configure the Alarm interrupt */
01122     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01123   }
01124
01125   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01126   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01127
01128   EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
01129
01130   /* Enable the write protection for RTC registers */
01131   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01132
01133   hrtc->State = HAL_RTC_STATE_READY;
01134
01135   /* Process Unlocked */
01136   __HAL_UNLOCK(hrtc);
01137
01138   return HAL_OK;
01139 }
01140
01141 /**
01142   * @brief  Deactivate the specified RTC Alarm
01143   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01144   *                the configuration information for RTC.
01145   * @param  Alarm: Specifies the Alarm.
01146   *          This parameter can be one of the following values:
01147   *            @arg RTC_ALARM_A:  AlarmA
01148   *            @arg RTC_ALARM_B:  AlarmB
01149   * @retval HAL status
01150   */
01151 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01152 {
01153   uint32_t tickstart = 0U;
01154
01155   /* Check the parameters */
01156   assert_param(IS_RTC_ALARM(Alarm));
01157
01158   /* Process Locked */
01159   __HAL_LOCK(hrtc);
01160
01161   hrtc->State = HAL_RTC_STATE_BUSY;
01162
01163   /* Disable the write protection for RTC registers */
01164   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01165
01166   if(Alarm == RTC_ALARM_A)
01167   {
01168     /* AlarmA */
01169     __HAL_RTC_ALARMA_DISABLE(hrtc);
01170
01171     /* In case of interrupt mode is used, the interrupt source must disabled */
01172     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01173
01174     /* Get tick */
01175     tickstart = HAL_GetTick();
01176
01177     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01178     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01179     {
01180       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01181       {
01182         /* Enable the write protection for RTC registers */
01183         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01184
01185         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01186
01187         /* Process Unlocked */
01188         __HAL_UNLOCK(hrtc);
01189
01190         return HAL_TIMEOUT;
01191       }
01192     }
01193   }
01194   else
01195   {
01196     /* AlarmB */
01197     __HAL_RTC_ALARMB_DISABLE(hrtc);
01198
01199     /* In case of interrupt mode is used, the interrupt source must disabled */
01200     __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
01201
01202     /* Get tick */
01203     tickstart = HAL_GetTick();
01204
01205     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01206     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01207     {
01208       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01209       {
01210         /* Enable the write protection for RTC registers */
01211         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01212
01213         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01214
01215         /* Process Unlocked */
01216         __HAL_UNLOCK(hrtc);
01217
01218         return HAL_TIMEOUT;
01219       }
01220     }
01221   }
01222   /* Enable the write protection for RTC registers */
01223   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01224
01225   hrtc->State = HAL_RTC_STATE_READY;
01226
01227   /* Process Unlocked */
01228   __HAL_UNLOCK(hrtc);
01229
01230   return HAL_OK;
01231 }
01232
01233 /**
01234   * @brief  Gets the RTC Alarm value and masks.
01235   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01236   *                the configuration information for RTC.
01237   * @param  sAlarm: Pointer to Date structure
01238   * @param  Alarm: Specifies the Alarm.
01239   *          This parameter can be one of the following values:
01240   *             @arg RTC_ALARM_A: AlarmA
01241   *             @arg RTC_ALARM_B: AlarmB
01242   * @param  Format: Specifies the format of the entered parameters.
01243   *          This parameter can be one of the following values:
01244   *             @arg RTC_FORMAT_BIN: Binary data format
01245   *             @arg RTC_FORMAT_BCD: BCD data format
01246   * @retval HAL status
01247   */
01248 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01249 {
01250   uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
01251
01252   /* Check the parameters */
01253   assert_param(IS_RTC_FORMAT(Format));
01254   assert_param(IS_RTC_ALARM(Alarm));
01255
01256   if(Alarm == RTC_ALARM_A)
01257   {
01258     /* AlarmA */
01259     sAlarm->Alarm = RTC_ALARM_A;
01260
01261     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01262     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
01263   }
01264   else
01265   {
01266     sAlarm->Alarm = RTC_ALARM_B;
01267
01268     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01269     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01270   }
01271
01272   /* Fill the structure with the read parameters */
01273   sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
01274   sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
01275   sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01276   sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
01277   sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01278   sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
01279   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01280   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01281
01282   if(Format == RTC_FORMAT_BIN)
01283   {
01284     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01285     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01286     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01287     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01288   }
01289
01290   return HAL_OK;
01291 }
01292
01293 /**
01294   * @brief  This function handles Alarm interrupt request.
01295   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01296   *                the configuration information for RTC.
01297   * @retval None
01298   */
01299 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01300 {
01301   if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
01302   {
01303     /* Get the status of the Interrupt */
01304     if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
01305     {
01306       /* AlarmA callback */
01307       HAL_RTC_AlarmAEventCallback(hrtc);
01308
01309       /* Clear the Alarm interrupt pending bit */
01310       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
01311     }
01312   }
01313
01314   if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
01315   {
01316     /* Get the status of the Interrupt */
01317     if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
01318     {
01319       /* AlarmB callback */
01320       HAL_RTCEx_AlarmBEventCallback(hrtc);
01321
01322       /* Clear the Alarm interrupt pending bit */
01323       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
01324     }
01325   }
01326
01327   /* Clear the EXTI's line Flag for RTC Alarm */
01328   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01329
01330   /* Change RTC state */
01331   hrtc->State = HAL_RTC_STATE_READY;
01332 }
01333
01334 /**
01335   * @brief  Alarm A callback.
01336   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01337   *                the configuration information for RTC.
01338   * @retval None
01339   */
01340 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01341 {
01342   /* Prevent unused argument(s) compilation warning */
01343   UNUSED(hrtc);
01344   /* NOTE : This function Should not be modified, when the callback is needed,
01345             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01346    */
01347 }
01348
01349 /**
01350   * @brief  This function handles AlarmA Polling request.
01351   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01352   *                the configuration information for RTC.
01353   * @param  Timeout: Timeout duration
01354   * @retval HAL status
01355   */
01356 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01357 {
01358   uint32_t tickstart = 0U;
01359
01360     /* Get tick */
01361     tickstart = HAL_GetTick();
01362
01363   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
01364   {
01365     if(Timeout != HAL_MAX_DELAY)
01366     {
01367       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01368       {
01369         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01370         return HAL_TIMEOUT;
01371       }
01372     }
01373   }
01374
01375   /* Clear the Alarm interrupt pending bit */
01376   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01377
01378   /* Change RTC state */
01379   hrtc->State = HAL_RTC_STATE_READY;
01380
01381   return HAL_OK;
01382 }
01383
01384 /**
01385   * @}
01386   */
01387
01388 /** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
01389  *  @brief   Peripheral Control functions
01390  *
01391 @verbatim
01392  ===============================================================================
01393                      ##### Peripheral Control functions #####
01394  ===============================================================================
01395     [..]
01396     This subsection provides functions allowing to
01397       (+) Wait for RTC Time and Date Synchronization
01398
01399 @endverbatim
01400   * @{
01401   */
01402
01403 /**
01404   * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01405   *         synchronized with RTC APB clock.
01406   * @note   The RTC Resynchronization mode is write protected, use the
01407   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01408   * @note   To read the calendar through the shadow registers after Calendar
01409   *         initialization, calendar update or after wake-up from low power modes
01410   *         the software must first clear the RSF flag.
01411   *         The software must then wait until it is set again before reading
01412   *         the calendar, which means that the calendar registers have been
01413   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01414   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01415   *                the configuration information for RTC.
01416   * @retval HAL status
01417   */
01418 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01419 {
01420   uint32_t tickstart = 0U;
01421
01422   /* Clear RSF flag */
01423   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
01424
01425     /* Get tick */
01426     tickstart = HAL_GetTick();
01427
01428   /* Wait the registers to be synchronised */
01429   while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
01430   {
01431     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01432     {
01433       return HAL_TIMEOUT;
01434     }
01435   }
01436
01437   return HAL_OK;
01438 }
01439
01440 /**
01441   * @}
01442   */
01443
01444 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
01445  *  @brief   Peripheral State functions
01446  *
01447 @verbatim
01448  ===============================================================================
01449                      ##### Peripheral State functions #####
01450  ===============================================================================
01451     [..]
01452     This subsection provides functions allowing to
01453       (+) Get RTC state
01454
01455 @endverbatim
01456   * @{
01457   */
01458 /**
01459   * @brief  Returns the RTC state.
01460   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01461   *                the configuration information for RTC.
01462   * @retval HAL state
01463   */
01464 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01465 {
01466   return hrtc->State;
01467 }
01468
01469 /**
01470   * @}
01471   */
01472
01473 /**
01474   * @brief  Enters the RTC Initialization mode.
01475   * @note   The RTC Initialization mode is write protected, use the
01476   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01477   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01478   *                the configuration information for RTC.
01479   * @retval HAL status
01480   */
01481 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01482 {
01483   uint32_t tickstart = 0U;
01484
01485   /* Check if the Initialization mode is set */
01486   if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01487   {
01488     /* Set the Initialization mode */
01489     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
01490
01491     /* Get tick */
01492     tickstart = HAL_GetTick();
01493
01494     /* Wait till RTC is in INIT state and if Time out is reached exit */
01495     while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01496     {
01497       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01498       {
01499         return HAL_TIMEOUT;
01500       }
01501     }
01502   }
01503
01504   return HAL_OK;
01505 }
01506
01507
01508 /**
01509   * @brief  Converts a 2 digit decimal to BCD format.
01510   * @param  Value: Byte to be converted
01511   * @retval Converted byte
01512   */
01513 uint8_t RTC_ByteToBcd2(uint8_t Value)
01514 {
01515   uint32_t bcdhigh = 0U;
01516
01517   while(Value >= 10U)
01518   {
01519     bcdhigh++;
01520     Value -= 10U;
01521   }
01522
01523   return  ((uint8_t)(bcdhigh << 4U) | Value);
01524 }
01525
01526 /**
01527   * @brief  Converts from 2 digit BCD to Binary.
01528   * @param  Value: BCD value to be converted
01529   * @retval Converted word
01530   */
01531 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01532 {
01533   uint32_t tmp = 0U;
01534   tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
01535   return (tmp + (Value & (uint8_t)0x0FU));
01536 }
01537
01538 /**
01539   * @}
01540   */
01541
01542 #endif /* HAL_RTC_MODULE_ENABLED */
01543 /**
01544   * @}
01545   */
01546
01547 /**
01548   * @}
01549   */
01550
01551 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc.h Source File

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stm32f4xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of RTC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_RTC_H
00040 #define __STM32F4xx_HAL_RTC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTC_Exported_Types RTC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  HAL State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
00068   HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
00069   HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
00070   HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
00071   HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
00072 }HAL_RTCStateTypeDef;
00073
00074 /**
00075   * @brief  RTC Configuration Structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
00080                                  This parameter can be a value of @ref RTC_Hour_Formats */
00081
00082   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00083                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00084
00085   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
00086                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */
00087
00088   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
00089                                  This parameter can be a value of @ref RTC_Output_selection_Definitions */
00090
00091   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
00092                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00093
00094   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
00095                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00096 }RTC_InitTypeDef;
00097
00098 /**
00099   * @brief  RTC Time structure definition
00100   */
00101 typedef struct
00102 {
00103   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00104                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00105                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */
00106
00107   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00108                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00109
00110   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00111                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00112
00113   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00114                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00115
00116   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00117                                  This parameter corresponds to a time unit range between [0-1] Second
00118                                  with [1 Sec / SecondFraction +1] granularity */
00119
00120   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00121                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00122                                  This parameter corresponds to a time unit range between [0-1] Second
00123                                  with [1 Sec / SecondFraction +1] granularity.
00124                                  This field will be used only by HAL_RTC_GetTime function */
00125
00126   uint32_t DayLightSaving;  /*!< Specifies DayLight Save Operation.
00127                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
00128
00129   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
00130                                  in CR register to store the operation.
00131                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
00132 }RTC_TimeTypeDef;
00133
00134 /**
00135   * @brief  RTC Date structure definition
00136   */
00137 typedef struct
00138 {
00139   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00140                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00141
00142   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00143                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00144
00145   uint8_t Date;     /*!< Specifies the RTC Date.
00146                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00147
00148   uint8_t Year;     /*!< Specifies the RTC Date Year.
00149                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00150
00151 }RTC_DateTypeDef;
00152
00153 /**
00154   * @brief  RTC Alarm structure definition
00155   */
00156 typedef struct
00157 {
00158   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00159
00160   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00161                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00162
00163   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00164                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00165
00166   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00167                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00168
00169   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00170                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00171                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00172
00173   uint32_t Alarm;                /*!< Specifies the alarm .
00174                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00175 }RTC_AlarmTypeDef;
00176
00177 /**
00178   * @brief  RTC Handle Structure definition
00179   */
00180 typedef struct
00181 {
00182   RTC_TypeDef                 *Instance;  /*!< Register base address    */
00183
00184   RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
00185
00186   HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
00187
00188   __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
00189
00190 }RTC_HandleTypeDef;
00191
00192 /**
00193   * @}
00194   */
00195
00196 /* Exported constants --------------------------------------------------------*/
00197 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00198   * @{
00199   */
00200
00201 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00202   * @{
00203   */
00204 #define RTC_HOURFORMAT_24              ((uint32_t)0x00000000U)
00205 #define RTC_HOURFORMAT_12              ((uint32_t)0x00000040U)
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
00211   * @{
00212   */
00213 #define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000U)
00214 #define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000U)
00215 #define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000U)
00216 #define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000U)
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00222   * @{
00223   */
00224 #define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000U)
00225 #define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000U)
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00231   * @{
00232   */
00233 #define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000U)
00234 #define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)0x00040000U)
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00240   * @{
00241   */
00242 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00U)
00243 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40U)
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
00249   * @{
00250   */
00251 #define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000U)
00252 #define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000U)
00253 #define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000U)
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
00259   * @{
00260   */
00261 #define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000U)
00262 #define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000U)
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00268   * @{
00269   */
00270 #define RTC_FORMAT_BIN                      ((uint32_t)0x00000000U)
00271 #define RTC_FORMAT_BCD                      ((uint32_t)0x00000001U)
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00277   * @{
00278   */
00279 /* Coded in BCD format */
00280 #define RTC_MONTH_JANUARY              ((uint8_t)0x01U)
00281 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02U)
00282 #define RTC_MONTH_MARCH                ((uint8_t)0x03U)
00283 #define RTC_MONTH_APRIL                ((uint8_t)0x04U)
00284 #define RTC_MONTH_MAY                  ((uint8_t)0x05U)
00285 #define RTC_MONTH_JUNE                 ((uint8_t)0x06U)
00286 #define RTC_MONTH_JULY                 ((uint8_t)0x07U)
00287 #define RTC_MONTH_AUGUST               ((uint8_t)0x08U)
00288 #define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09U)
00289 #define RTC_MONTH_OCTOBER              ((uint8_t)0x10U)
00290 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11U)
00291 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12U)
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00297   * @{
00298   */
00299 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01U)
00300 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02U)
00301 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03U)
00302 #define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04U)
00303 #define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05U)
00304 #define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06U)
00305 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07U)
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
00311   * @{
00312   */
00313 #define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000U)
00314 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000U)
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
00320   * @{
00321   */
00322 #define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000U)
00323 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
00324 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
00325 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
00326 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
00327 #define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080U)
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00333   * @{
00334   */
00335 #define RTC_ALARM_A                       RTC_CR_ALRAE
00336 #define RTC_ALARM_B                       RTC_CR_ALRBE
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00342   * @{
00343   */
00344 #define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000U)  /*!< All Alarm SS fields are masked.
00345                                                                         There is no comparison on sub seconds
00346                                                                         for Alarm */
00347 #define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000U)  /*!< SS[14:1] are don't care in Alarm
00348                                                                         comparison. Only SS[0] is compared.    */
00349 #define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000U)  /*!< SS[14:2] are don't care in Alarm
00350                                                                         comparison. Only SS[1:0] are compared  */
00351 #define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000U)  /*!< SS[14:3] are don't care in Alarm
00352                                                                         comparison. Only SS[2:0] are compared  */
00353 #define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000U)  /*!< SS[14:4] are don't care in Alarm
00354                                                                         comparison. Only SS[3:0] are compared  */
00355 #define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000U)  /*!< SS[14:5] are don't care in Alarm
00356                                                                         comparison. Only SS[4:0] are compared  */
00357 #define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000U)  /*!< SS[14:6] are don't care in Alarm
00358                                                                         comparison. Only SS[5:0] are compared  */
00359 #define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000U)  /*!< SS[14:7] are don't care in Alarm
00360                                                                         comparison. Only SS[6:0] are compared  */
00361 #define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000U)  /*!< SS[14:8] are don't care in Alarm
00362                                                                         comparison. Only SS[7:0] are compared  */
00363 #define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000U)  /*!< SS[14:9] are don't care in Alarm
00364                                                                         comparison. Only SS[8:0] are compared  */
00365 #define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000U)  /*!< SS[14:10] are don't care in Alarm
00366                                                                         comparison. Only SS[9:0] are compared  */
00367 #define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000U)  /*!< SS[14:11] are don't care in Alarm
00368                                                                         comparison. Only SS[10:0] are compared */
00369 #define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000U)  /*!< SS[14:12] are don't care in Alarm
00370                                                                         comparison.Only SS[11:0] are compared  */
00371 #define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000U)  /*!< SS[14:13] are don't care in Alarm
00372                                                                         comparison. Only SS[12:0] are compared */
00373 #define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000U)  /*!< SS[14] is don't care in Alarm
00374                                                                         comparison.Only SS[13:0] are compared  */
00375 #define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000U)  /*!< SS[14:0] are compared and must match
00376                                                                         to activate alarm. */
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00382   * @{
00383   */
00384 #define RTC_IT_TS                         ((uint32_t)0x00008000U)
00385 #define RTC_IT_WUT                        ((uint32_t)0x00004000U)
00386 #define RTC_IT_ALRB                       ((uint32_t)0x00002000U)
00387 #define RTC_IT_ALRA                       ((uint32_t)0x00001000U)
00388 #define RTC_IT_TAMP                       ((uint32_t)0x00000004U) /* Used only to Enable the Tamper Interrupt */
00389 #define RTC_IT_TAMP1                      ((uint32_t)0x00020000U)
00390 #define RTC_IT_TAMP2                      ((uint32_t)0x00040000U)
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00396   * @{
00397   */
00398 #define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000U)
00399 #define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000U)
00400 #define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000U)
00401 #define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000U)
00402 #define RTC_FLAG_TSF                      ((uint32_t)0x00000800U)
00403 #define RTC_FLAG_WUTF                     ((uint32_t)0x00000400U)
00404 #define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200U)
00405 #define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100U)
00406 #define RTC_FLAG_INITF                    ((uint32_t)0x00000040U)
00407 #define RTC_FLAG_RSF                      ((uint32_t)0x00000020U)
00408 #define RTC_FLAG_INITS                    ((uint32_t)0x00000010U)
00409 #define RTC_FLAG_SHPF                     ((uint32_t)0x00000008U)
00410 #define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004U)
00411 #define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002U)
00412 #define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001U)
00413 /**
00414   * @}
00415   */
00416
00417 /**
00418   * @}
00419   */
00420
00421 /* Exported macro ------------------------------------------------------------*/
00422 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00423   * @{
00424   */
00425
00426 /** @brief Reset RTC handle state
00427   * @param  __HANDLE__: specifies the RTC handle.
00428   * @retval None
00429   */
00430 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00431
00432 /**
00433   * @brief  Disable the write protection for RTC registers.
00434   * @param  __HANDLE__: specifies the RTC handle.
00435   * @retval None
00436   */
00437 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00438                         do{                                       \
00439                             (__HANDLE__)->Instance->WPR = 0xCAU;  \
00440                             (__HANDLE__)->Instance->WPR = 0x53U;  \
00441                           } while(0)
00442
00443 /**
00444   * @brief  Enable the write protection for RTC registers.
00445   * @param  __HANDLE__: specifies the RTC handle.
00446   * @retval None
00447   */
00448 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00449                         do{                                       \
00450                             (__HANDLE__)->Instance->WPR = 0xFFU;  \
00451                           } while(0)
00452
00453 /**
00454   * @brief  Enable the RTC ALARMA peripheral.
00455   * @param  __HANDLE__: specifies the RTC handle.
00456   * @retval None
00457   */
00458 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00459
00460 /**
00461   * @brief  Disable the RTC ALARMA peripheral.
00462   * @param  __HANDLE__: specifies the RTC handle.
00463   * @retval None
00464   */
00465 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00466
00467 /**
00468   * @brief  Enable the RTC ALARMB peripheral.
00469   * @param  __HANDLE__: specifies the RTC handle.
00470   * @retval None
00471   */
00472 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00473
00474 /**
00475   * @brief  Disable the RTC ALARMB peripheral.
00476   * @param  __HANDLE__: specifies the RTC handle.
00477   * @retval None
00478   */
00479 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00480
00481 /**
00482   * @brief  Enable the RTC Alarm interrupt.
00483   * @param  __HANDLE__: specifies the RTC handle.
00484   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00485   *          This parameter can be any combination of the following values:
00486   *             @arg RTC_IT_ALRA: Alarm A interrupt
00487   *             @arg RTC_IT_ALRB: Alarm B interrupt
00488   * @retval None
00489   */
00490 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00491
00492 /**
00493   * @brief  Disable the RTC Alarm interrupt.
00494   * @param  __HANDLE__: specifies the RTC handle.
00495   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00496   *         This parameter can be any combination of the following values:
00497   *            @arg RTC_IT_ALRA: Alarm A interrupt
00498   *            @arg RTC_IT_ALRB: Alarm B interrupt
00499   * @retval None
00500   */
00501 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00502
00503 /**
00504   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00505   * @param  __HANDLE__: specifies the RTC handle.
00506   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.
00507   *         This parameter can be:
00508   *            @arg RTC_IT_ALRA: Alarm A interrupt
00509   *            @arg RTC_IT_ALRB: Alarm B interrupt
00510   * @retval None
00511   */
00512 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
00513
00514 /**
00515   * @brief  Get the selected RTC Alarm's flag status.
00516   * @param  __HANDLE__: specifies the RTC handle.
00517   * @param  __FLAG__: specifies the RTC Alarm Flag to check.
00518   *         This parameter can be:
00519   *            @arg RTC_FLAG_ALRAF
00520   *            @arg RTC_FLAG_ALRBF
00521   *            @arg RTC_FLAG_ALRAWF
00522   *            @arg RTC_FLAG_ALRBWF
00523   * @retval None
00524   */
00525 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00526
00527 /**
00528   * @brief  Clear the RTC Alarm's pending flags.
00529   * @param  __HANDLE__: specifies the RTC handle.
00530   * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
00531   *          This parameter can be:
00532   *             @arg RTC_FLAG_ALRAF
00533   *             @arg RTC_FLAG_ALRBF
00534   * @retval None
00535   */
00536 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00537
00538
00539 /**
00540   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00541   * @param  __HANDLE__: specifies the RTC handle.
00542   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
00543   *         This parameter can be:
00544   *            @arg RTC_IT_ALRA: Alarm A interrupt
00545   *            @arg RTC_IT_ALRB: Alarm B interrupt
00546   * @retval None
00547   */
00548 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00549
00550 /**
00551   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00552   * @retval None
00553   */
00554 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
00555
00556 /**
00557   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00558   * @retval None
00559   */
00560 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00561
00562 /**
00563   * @brief  Enable event on the RTC Alarm associated Exti line.
00564   * @retval None.
00565   */
00566 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
00567
00568 /**
00569   * @brief  Disable event on the RTC Alarm associated Exti line.
00570   * @retval None.
00571   */
00572 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00573
00574 /**
00575   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00576   * @retval None.
00577   */
00578 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
00579
00580 /**
00581   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00582   * @retval None.
00583   */
00584 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00585
00586 /**
00587   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00588   * @retval None.
00589   */
00590 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
00591
00592 /**
00593   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00594   * @retval None.
00595   */
00596 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00597
00598 /**
00599   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00600   * @retval None.
00601   */
00602 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
00603                                                                __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
00604                                                              } while(0)
00605
00606 /**
00607   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00608   * @retval None.
00609   */
00610 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
00611                                                                 __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
00612                                                               } while(0)
00613
00614 /**
00615   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
00616   * @retval Line Status.
00617   */
00618 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
00619
00620 /**
00621   * @brief Clear the RTC Alarm associated Exti line flag.
00622   * @retval None.
00623   */
00624 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
00625
00626 /**
00627   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
00628   * @retval None.
00629   */
00630 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
00631 /**
00632   * @}
00633   */
00634
00635 /* Include RTC HAL Extension module */
00636 #include "stm32f4xx_hal_rtc_ex.h"
00637
00638 /* Exported functions --------------------------------------------------------*/
00639 /** @addtogroup RTC_Exported_Functions
00640   * @{
00641   */
00642
00643 /** @addtogroup RTC_Exported_Functions_Group1
00644   * @{
00645   */
00646 /* Initialization and de-initialization functions  ****************************/
00647 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00648 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00649 void       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00650 void       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00651 /**
00652   * @}
00653   */
00654
00655 /** @addtogroup RTC_Exported_Functions_Group2
00656   * @{
00657   */
00658 /* RTC Time and Date functions ************************************************/
00659 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00660 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00661 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00662 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00663 /**
00664   * @}
00665   */
00666
00667 /** @addtogroup RTC_Exported_Functions_Group3
00668   * @{
00669   */
00670 /* RTC Alarm functions ********************************************************/
00671 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00672 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00673 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00674 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00675 void                HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00676 HAL_StatusTypeDef   HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00677 void         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00678 /**
00679   * @}
00680   */
00681
00682 /** @addtogroup RTC_Exported_Functions_Group4
00683   * @{
00684   */
00685 /* Peripheral Control functions ***********************************************/
00686 HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00687 /**
00688   * @}
00689   */
00690
00691 /** @addtogroup RTC_Exported_Functions_Group5
00692   * @{
00693   */
00694 /* Peripheral State functions *************************************************/
00695 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00696 /**
00697   * @}
00698   */
00699
00700 /**
00701   * @}
00702   */
00703
00704 /* Private types -------------------------------------------------------------*/
00705 /* Private variables ---------------------------------------------------------*/
00706 /* Private constants ---------------------------------------------------------*/
00707 /** @defgroup RTC_Private_Constants RTC Private Constants
00708   * @{
00709   */
00710 /* Masks Definition */
00711 #define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7FU)
00712 #define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3FU)
00713 #define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)
00714 #define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
00715 #define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
00716                                             RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
00717                                             RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
00718                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
00719                                             RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
00720
00721 #define RTC_TIMEOUT_VALUE       1000
00722
00723 #define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
00724 /**
00725   * @}
00726   */
00727
00728 /* Private macros ------------------------------------------------------------*/
00729 /** @defgroup RTC_Private_Macros RTC Private Macros
00730   * @{
00731   */
00732
00733 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00734   * @{
00735   */
00736 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
00737                                         ((FORMAT) == RTC_HOURFORMAT_24))
00738 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
00739                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
00740                                ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
00741                                ((OUTPUT) == RTC_OUTPUT_WAKEUP))
00742 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
00743                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
00744 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00745                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
00746 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
00747 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23U)
00748 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7FU)
00749 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFFU)
00750 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59U)
00751 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59U)
00752
00753 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
00754 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
00755                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
00756                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
00757 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
00758                                            ((OPERATION) == RTC_STOREOPERATION_SET))
00759 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
00760 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99U)
00761 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
00762 #define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
00763 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00764                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00765                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00766                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00767                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00768                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00769                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00770 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0U) && ((DATE) <= (uint32_t)31U))
00771 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00772                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00773                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00774                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00775                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00776                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00777                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00778 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00779                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00780 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
00781 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
00782 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFFU)
00783
00784 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
00785                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
00786                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
00787                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
00788                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
00789                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
00790                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
00791                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
00792                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
00793                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
00794                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
00795                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
00796                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
00797                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
00798                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
00799                                               ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
00800 /**
00801   * @}
00802   */
00803
00804 /**
00805   * @}
00806   */
00807
00808 /* Private functions ---------------------------------------------------------*/
00809 /** @defgroup RTC_Private_Functions RTC Private Functions
00810   * @{
00811   */
00812 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00813 uint8_t            RTC_ByteToBcd2(uint8_t Value);
00814 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00815 /**
00816   * @}
00817   */
00818
00819 /**
00820   * @}
00821   */
00822
00823 /**
00824   * @}
00825   */
00826
00827 #ifdef __cplusplus
00828 }
00829 #endif
00830
00831 #endif /* __STM32F4xx_HAL_RTC_H */
00832
00833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc_ex.c Source File

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stm32f4xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
00010   *           + RTC Time Stamp functions
00011   *           + RTC Tamper functions
00012   *           + RTC Wake-up functions
00013   *           + Extension Control functions
00014   *           + Extension RTC features functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                   ##### How to use this driver #####
00019   ==============================================================================
00020   [..]
00021     (+) Enable the RTC domain access.
00022     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00023         format using the HAL_RTC_Init() function.
00024
00025   *** RTC Wake-up configuration ***
00026   ================================
00027   [..]
00028     (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
00029         function. You can also configure the RTC Wake-up timer in interrupt mode
00030         using the HAL_RTC_SetWakeUpTimer_IT() function.
00031     (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer()
00032         function.
00033
00034   *** TimeStamp configuration ***
00035   ===============================
00036   [..]
00037     (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
00038         HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
00039         interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
00040     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
00041         function.
00042     (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
00043         or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in
00044         RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
00045         or HAL_RTC_SetTimeStamp_IT() function.
00046
00047   *** Tamper configuration ***
00048   ============================
00049   [..]
00050     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00051         or Level according to the Tamper filter (if equal to 0 Edge else Level)
00052         value, sampling frequency, precharge or discharge and Pull-UP using the
00053         HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
00054         mode using HAL_RTC_SetTamper_IT() function.
00055     (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
00056         or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in
00057         RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
00058         or HAL_RTC_SetTamper_IT() function.
00059
00060   *** Backup Data Registers configuration ***
00061   ===========================================
00062   [..]
00063     (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
00064         function.
00065     (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
00066         function.
00067
00068    @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097   */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f4xx_hal.h"
00101
00102 /** @addtogroup STM32F4xx_HAL_Driver
00103   * @{
00104   */
00105
00106 /** @defgroup RTCEx RTCEx
00107   * @brief RTC HAL module driver
00108   * @{
00109   */
00110
00111 #ifdef HAL_RTC_MODULE_ENABLED
00112
00113 /* Private typedef -----------------------------------------------------------*/
00114 /* Private define ------------------------------------------------------------*/
00115 /* Private macro -------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /* Private function prototypes -----------------------------------------------*/
00118 /* Private functions ---------------------------------------------------------*/
00119
00120 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00121   * @{
00122   */
00123
00124 /** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
00125  *  @brief   RTC TimeStamp and Tamper functions
00126  *
00127 @verbatim
00128  ===============================================================================
00129                  ##### RTC TimeStamp and Tamper functions #####
00130  ===============================================================================
00131
00132  [..] This section provides functions allowing to configure TimeStamp feature
00133
00134 @endverbatim
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Sets TimeStamp.
00140   * @note   This API must be called before enabling the TimeStamp feature.
00141   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00142   *                the configuration information for RTC.
00143   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00144   *         activated.
00145   *          This parameter can be one of the following values:
00146   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00147   *                                        rising edge of the related pin.
00148   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00149   *                                         falling edge of the related pin.
00150   * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
00151   *          This parameter can be one of the following values:
00152   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00153   *             @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin.
00154   *             (PI8 for all STM32 devices except for STM32F446xx devices the PA0 is used)
00155   *             @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
00156   * @retval HAL status
00157   */
00158 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00159 {
00160   uint32_t tmpreg = 0U;
00161
00162   /* Check the parameters */
00163   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00164   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00165
00166   /* Process Locked */
00167   __HAL_LOCK(hrtc);
00168
00169   hrtc->State = HAL_RTC_STATE_BUSY;
00170
00171   /* Get the RTC_CR register and clear the bits to be configured */
00172   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00173
00174   tmpreg|= TimeStampEdge;
00175
00176   /* Disable the write protection for RTC registers */
00177   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00178
00179   hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
00180   hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin);
00181
00182   /* Configure the Time Stamp TSEDGE and Enable bits */
00183   hrtc->Instance->CR = (uint32_t)tmpreg;
00184
00185   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00186
00187   /* Enable the write protection for RTC registers */
00188   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00189
00190   /* Change RTC state */
00191   hrtc->State = HAL_RTC_STATE_READY;
00192
00193   /* Process Unlocked */
00194   __HAL_UNLOCK(hrtc);
00195
00196   return HAL_OK;
00197 }
00198
00199 /**
00200   * @brief  Sets TimeStamp with Interrupt.
00201   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00202   *                the configuration information for RTC.
00203   * @note   This API must be called before enabling the TimeStamp feature.
00204   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00205   *         activated.
00206   *          This parameter can be one of the following values:
00207   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00208   *                                        rising edge of the related pin.
00209   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00210   *                                         falling edge of the related pin.
00211   * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
00212   *          This parameter can be one of the following values:
00213   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00214   *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices)
00215   *             @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices
00216   * @retval HAL status
00217   */
00218 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00219 {
00220   uint32_t tmpreg = 0U;
00221
00222   /* Check the parameters */
00223   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00224   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00225
00226   /* Process Locked */
00227   __HAL_LOCK(hrtc);
00228
00229   hrtc->State = HAL_RTC_STATE_BUSY;
00230
00231   /* Get the RTC_CR register and clear the bits to be configured */
00232   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00233
00234   tmpreg |= TimeStampEdge;
00235
00236   /* Disable the write protection for RTC registers */
00237   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00238
00239   /* Configure the Time Stamp TSEDGE and Enable bits */
00240   hrtc->Instance->CR = (uint32_t)tmpreg;
00241
00242   hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
00243   hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin);
00244
00245   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00246
00247   /* Enable IT timestamp */
00248   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
00249
00250   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00251   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00252
00253   EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
00254
00255   /* Enable the write protection for RTC registers */
00256   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00257
00258   hrtc->State = HAL_RTC_STATE_READY;
00259
00260   /* Process Unlocked */
00261   __HAL_UNLOCK(hrtc);
00262
00263   return HAL_OK;
00264 }
00265
00266 /**
00267   * @brief  Deactivates TimeStamp.
00268   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00269   *                the configuration information for RTC.
00270   * @retval HAL status
00271   */
00272 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00273 {
00274   uint32_t tmpreg = 0U;
00275
00276   /* Process Locked */
00277   __HAL_LOCK(hrtc);
00278
00279   hrtc->State = HAL_RTC_STATE_BUSY;
00280
00281   /* Disable the write protection for RTC registers */
00282   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00283
00284   /* In case of interrupt mode is used, the interrupt source must disabled */
00285   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00286
00287   /* Get the RTC_CR register and clear the bits to be configured */
00288   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00289
00290   /* Configure the Time Stamp TSEDGE and Enable bits */
00291   hrtc->Instance->CR = (uint32_t)tmpreg;
00292
00293   /* Enable the write protection for RTC registers */
00294   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00295
00296   hrtc->State = HAL_RTC_STATE_READY;
00297
00298   /* Process Unlocked */
00299   __HAL_UNLOCK(hrtc);
00300
00301   return HAL_OK;
00302 }
00303
00304 /**
00305   * @brief  Gets the RTC TimeStamp value.
00306   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00307   *                the configuration information for RTC.
00308   * @param  sTimeStamp: Pointer to Time structure
00309   * @param  sTimeStampDate: Pointer to Date structure
00310   * @param  Format: specifies the format of the entered parameters.
00311   *          This parameter can be one of the following values:
00312   *             RTC_FORMAT_BIN: Binary data format
00313   *             RTC_FORMAT_BCD: BCD data format
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
00317 {
00318   uint32_t tmptime = 0U, tmpdate = 0U;
00319
00320   /* Check the parameters */
00321   assert_param(IS_RTC_FORMAT(Format));
00322
00323   /* Get the TimeStamp time and date registers values */
00324   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00325   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00326
00327   /* Fill the Time structure fields with the read parameters */
00328   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
00329   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
00330   sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
00331   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
00332   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00333
00334   /* Fill the Date structure fields with the read parameters */
00335   sTimeStampDate->Year = 0U;
00336   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
00337   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
00338   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
00339
00340   /* Check the input parameters format */
00341   if(Format == RTC_FORMAT_BIN)
00342   {
00343     /* Convert the TimeStamp structure parameters to Binary format */
00344     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00345     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00346     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00347
00348     /* Convert the DateTimeStamp structure parameters to Binary format */
00349     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00350     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00351     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00352   }
00353
00354   /* Clear the TIMESTAMP Flag */
00355   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00356
00357   return HAL_OK;
00358 }
00359
00360 /**
00361   * @brief  Sets Tamper
00362   * @note   By calling this API we disable the tamper interrupt for all tampers.
00363   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00364   *                the configuration information for RTC.
00365   * @param  sTamper: Pointer to Tamper Structure.
00366   * @retval HAL status
00367   */
00368 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00369 {
00370   uint32_t tmpreg = 0U;
00371
00372   /* Check the parameters */
00373   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00374   assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
00375   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00376   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00377   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00378   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00379   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00380   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00381
00382   /* Process Locked */
00383   __HAL_LOCK(hrtc);
00384
00385   hrtc->State = HAL_RTC_STATE_BUSY;
00386
00387   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00388   {
00389     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
00390   }
00391
00392   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger  |\
00393             (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
00394             (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00395
00396   hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
00397                                        (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
00398                                        (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL | (uint32_t)RTC_TAFCR_TAMPIE);
00399
00400   hrtc->Instance->TAFCR |= tmpreg;
00401
00402   hrtc->State = HAL_RTC_STATE_READY;
00403
00404   /* Process Unlocked */
00405   __HAL_UNLOCK(hrtc);
00406
00407   return HAL_OK;
00408 }
00409
00410 /**
00411   * @brief  Sets Tamper with interrupt.
00412   * @note   By calling this API we force the tamper interrupt for all tampers.
00413   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00414   *                the configuration information for RTC.
00415   * @param  sTamper: Pointer to RTC Tamper.
00416   * @retval HAL status
00417   */
00418 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00419 {
00420   uint32_t tmpreg = 0U;
00421
00422   /* Check the parameters */
00423   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00424   assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
00425   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00426   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00427   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00428   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00429   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00430   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00431
00432   /* Process Locked */
00433   __HAL_LOCK(hrtc);
00434
00435   hrtc->State = HAL_RTC_STATE_BUSY;
00436
00437   /* Configure the tamper trigger */
00438   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00439   {
00440     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
00441   }
00442
00443   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger  |\
00444             (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
00445             (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00446
00447   hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
00448                                        (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
00449                                        (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL);
00450
00451   hrtc->Instance->TAFCR |= tmpreg;
00452
00453   /* Configure the Tamper Interrupt in the RTC_TAFCR */
00454   hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
00455
00456   /* RTC Tamper Interrupt Configuration: EXTI configuration */
00457   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00458
00459   EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
00460
00461   hrtc->State = HAL_RTC_STATE_READY;
00462
00463   /* Process Unlocked */
00464   __HAL_UNLOCK(hrtc);
00465
00466   return HAL_OK;
00467 }
00468
00469 /**
00470   * @brief  Deactivates Tamper.
00471   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00472   *                the configuration information for RTC.
00473   * @param  Tamper: Selected tamper pin.
00474   *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
00478 {
00479   assert_param(IS_RTC_TAMPER(Tamper));
00480
00481   /* Process Locked */
00482   __HAL_LOCK(hrtc);
00483
00484   hrtc->State = HAL_RTC_STATE_BUSY;
00485
00486   /* Disable the selected Tamper pin */
00487   hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
00488
00489   hrtc->State = HAL_RTC_STATE_READY;
00490
00491   /* Process Unlocked */
00492   __HAL_UNLOCK(hrtc);
00493
00494   return HAL_OK;
00495 }
00496
00497 /**
00498   * @brief  This function handles TimeStamp interrupt request.
00499   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00500   *                the configuration information for RTC.
00501   * @retval None
00502   */
00503 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00504 {
00505   if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
00506   {
00507     /* Get the status of the Interrupt */
00508     if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
00509     {
00510       /* TIMESTAMP callback */
00511       HAL_RTCEx_TimeStampEventCallback(hrtc);
00512
00513       /* Clear the TIMESTAMP interrupt pending bit */
00514       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
00515     }
00516   }
00517
00518   /* Get the status of the Interrupt */
00519   if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
00520   {
00521     /* Get the TAMPER Interrupt enable bit and pending bit */
00522     if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET)
00523     {
00524       /* Tamper callback */
00525       HAL_RTCEx_Tamper1EventCallback(hrtc);
00526
00527       /* Clear the Tamper interrupt pending bit */
00528       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00529     }
00530   }
00531
00532   /* Get the status of the Interrupt */
00533   if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
00534   {
00535     /* Get the TAMPER Interrupt enable bit and pending bit */
00536     if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
00537     {
00538       /* Tamper callback */
00539       HAL_RTCEx_Tamper2EventCallback(hrtc);
00540
00541       /* Clear the Tamper interrupt pending bit */
00542       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00543     }
00544   }
00545   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
00546   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
00547
00548   /* Change RTC state */
00549   hrtc->State = HAL_RTC_STATE_READY;
00550 }
00551
00552 /**
00553   * @brief  TimeStamp callback.
00554   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00555   *                the configuration information for RTC.
00556   * @retval None
00557   */
00558 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00559 {
00560   /* Prevent unused argument(s) compilation warning */
00561   UNUSED(hrtc);
00562   /* NOTE : This function Should not be modified, when the callback is needed,
00563             the HAL_RTC_TimeStampEventCallback could be implemented in the user file
00564   */
00565 }
00566
00567 /**
00568   * @brief  Tamper 1 callback.
00569   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00570   *                the configuration information for RTC.
00571   * @retval None
00572   */
00573 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
00574 {
00575   /* Prevent unused argument(s) compilation warning */
00576   UNUSED(hrtc);
00577   /* NOTE : This function Should not be modified, when the callback is needed,
00578             the HAL_RTC_Tamper1EventCallback could be implemented in the user file
00579    */
00580 }
00581
00582 /**
00583   * @brief  Tamper 2 callback.
00584   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00585   *                the configuration information for RTC.
00586   * @retval None
00587   */
00588 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
00589 {
00590   /* Prevent unused argument(s) compilation warning */
00591   UNUSED(hrtc);
00592   /* NOTE : This function Should not be modified, when the callback is needed,
00593             the HAL_RTC_Tamper2EventCallback could be implemented in the user file
00594    */
00595 }
00596
00597 /**
00598   * @brief  This function handles TimeStamp polling request.
00599   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00600   *                the configuration information for RTC.
00601   * @param  Timeout: Timeout duration
00602   * @retval HAL status
00603   */
00604 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00605 {
00606   uint32_t tickstart = 0U;
00607
00608   /* Get tick */
00609   tickstart = HAL_GetTick();
00610
00611   while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
00612   {
00613     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
00614     {
00615       /* Clear the TIMESTAMP Overrun Flag */
00616       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00617
00618       /* Change TIMESTAMP state */
00619       hrtc->State = HAL_RTC_STATE_ERROR;
00620
00621       return HAL_ERROR;
00622     }
00623
00624     if(Timeout != HAL_MAX_DELAY)
00625     {
00626       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00627       {
00628         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00629         return HAL_TIMEOUT;
00630       }
00631     }
00632   }
00633
00634   /* Change RTC state */
00635   hrtc->State = HAL_RTC_STATE_READY;
00636
00637   return HAL_OK;
00638 }
00639
00640 /**
00641   * @brief  This function handles Tamper1 Polling.
00642   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00643   *                the configuration information for RTC.
00644   * @param  Timeout: Timeout duration
00645   * @retval HAL status
00646   */
00647 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00648 {
00649   uint32_t tickstart = 0U;
00650
00651   /* Get tick */
00652   tickstart = HAL_GetTick();
00653
00654   /* Get the status of the Interrupt */
00655   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
00656   {
00657     if(Timeout != HAL_MAX_DELAY)
00658     {
00659       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00660       {
00661         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00662         return HAL_TIMEOUT;
00663       }
00664     }
00665   }
00666
00667   /* Clear the Tamper Flag */
00668   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00669
00670   /* Change RTC state */
00671   hrtc->State = HAL_RTC_STATE_READY;
00672
00673   return HAL_OK;
00674 }
00675
00676 /**
00677   * @brief  This function handles Tamper2 Polling.
00678   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00679   *                the configuration information for RTC.
00680   * @param  Timeout: Timeout duration
00681   * @retval HAL status
00682   */
00683 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00684 {
00685   uint32_t tickstart = 0U;
00686
00687   /* Get tick */
00688   tickstart = HAL_GetTick();
00689
00690   /* Get the status of the Interrupt */
00691   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
00692   {
00693     if(Timeout != HAL_MAX_DELAY)
00694     {
00695       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00696       {
00697         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00698         return HAL_TIMEOUT;
00699       }
00700     }
00701   }
00702
00703   /* Clear the Tamper Flag */
00704   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
00705
00706   /* Change RTC state */
00707   hrtc->State = HAL_RTC_STATE_READY;
00708
00709   return HAL_OK;
00710 }
00711
00712 /**
00713   * @}
00714   */
00715
00716 /** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
00717  *  @brief   RTC Wake-up functions
00718  *
00719 @verbatim
00720  ===============================================================================
00721                         ##### RTC Wake-up functions #####
00722  ===============================================================================
00723
00724  [..] This section provides functions allowing to configure Wake-up feature
00725
00726 @endverbatim
00727   * @{
00728   */
00729
00730 /**
00731   * @brief  Sets wake up timer.
00732   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00733   *                the configuration information for RTC.
00734   * @param  WakeUpCounter: Wake up counter
00735   * @param  WakeUpClock: Wake up clock
00736   * @retval HAL status
00737   */
00738 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00739 {
00740   uint32_t tickstart = 0U;
00741
00742   /* Check the parameters */
00743   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00744   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00745
00746   /* Process Locked */
00747   __HAL_LOCK(hrtc);
00748
00749   hrtc->State = HAL_RTC_STATE_BUSY;
00750
00751   /* Disable the write protection for RTC registers */
00752   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00753
00754   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
00755   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
00756   {
00757     tickstart = HAL_GetTick();
00758
00759     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
00760     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
00761     {
00762       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00763       {
00764         /* Enable the write protection for RTC registers */
00765         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00766
00767         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00768
00769         /* Process Unlocked */
00770         __HAL_UNLOCK(hrtc);
00771
00772         return HAL_TIMEOUT;
00773       }
00774     }
00775   }
00776
00777   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00778
00779   tickstart = HAL_GetTick();
00780
00781   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00782   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00783   {
00784     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00785     {
00786       /* Enable the write protection for RTC registers */
00787       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00788
00789       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00790
00791       /* Process Unlocked */
00792       __HAL_UNLOCK(hrtc);
00793
00794       return HAL_TIMEOUT;
00795     }
00796   }
00797
00798   /* Clear the Wake-up Timer clock source bits in CR register */
00799   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
00800
00801   /* Configure the clock source */
00802   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
00803
00804   /* Configure the Wake-up Timer counter */
00805   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
00806
00807    /* Enable the Wake-up Timer */
00808   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
00809
00810   /* Enable the write protection for RTC registers */
00811   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00812
00813   hrtc->State = HAL_RTC_STATE_READY;
00814
00815   /* Process Unlocked */
00816   __HAL_UNLOCK(hrtc);
00817
00818   return HAL_OK;
00819 }
00820
00821 /**
00822   * @brief  Sets wake up timer with interrupt
00823   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00824   *                the configuration information for RTC.
00825   * @param  WakeUpCounter: Wake up counter
00826   * @param  WakeUpClock: Wake up clock
00827   * @retval HAL status
00828   */
00829 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00830 {
00831   uint32_t tickstart = 0U;
00832
00833   /* Check the parameters */
00834   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
00835   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
00836
00837   /* Process Locked */
00838   __HAL_LOCK(hrtc);
00839
00840   hrtc->State = HAL_RTC_STATE_BUSY;
00841
00842   /* Disable the write protection for RTC registers */
00843   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00844
00845   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
00846   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
00847   {
00848     tickstart = HAL_GetTick();
00849
00850     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
00851     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
00852     {
00853       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00854       {
00855        /* Enable the write protection for RTC registers */
00856        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00857
00858        hrtc->State = HAL_RTC_STATE_TIMEOUT;
00859
00860        /* Process Unlocked */
00861        __HAL_UNLOCK(hrtc);
00862
00863        return HAL_TIMEOUT;
00864       }
00865     }
00866   }
00867
00868   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00869
00870   tickstart = HAL_GetTick();
00871
00872   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00873   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00874   {
00875     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00876     {
00877       /* Enable the write protection for RTC registers */
00878       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00879
00880       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00881
00882       /* Process Unlocked */
00883       __HAL_UNLOCK(hrtc);
00884
00885       return HAL_TIMEOUT;
00886     }
00887   }
00888
00889   /* Configure the Wake-up Timer counter */
00890   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
00891
00892   /* Clear the Wake-up Timer clock source bits in CR register */
00893   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
00894
00895   /* Configure the clock source */
00896   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
00897
00898   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
00899   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
00900
00901   EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
00902
00903   /* Configure the Interrupt in the RTC_CR register */
00904   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
00905
00906   /* Enable the Wake-up Timer */
00907   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
00908
00909   /* Enable the write protection for RTC registers */
00910   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00911
00912   hrtc->State = HAL_RTC_STATE_READY;
00913
00914   /* Process Unlocked */
00915   __HAL_UNLOCK(hrtc);
00916
00917   return HAL_OK;
00918 }
00919
00920 /**
00921   * @brief  Deactivates wake up timer counter.
00922   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00923   *                the configuration information for RTC.
00924   * @retval HAL status
00925   */
00926 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
00927 {
00928   uint32_t tickstart = 0U;
00929
00930   /* Process Locked */
00931   __HAL_LOCK(hrtc);
00932
00933   hrtc->State = HAL_RTC_STATE_BUSY;
00934
00935   /* Disable the write protection for RTC registers */
00936   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00937
00938   /* Disable the Wake-up Timer */
00939   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
00940
00941   /* In case of interrupt mode is used, the interrupt source must disabled */
00942   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
00943
00944   /* Get tick */
00945   tickstart = HAL_GetTick();
00946
00947   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
00948   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
00949   {
00950     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00951     {
00952       /* Enable the write protection for RTC registers */
00953       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00954
00955       hrtc->State = HAL_RTC_STATE_TIMEOUT;
00956
00957       /* Process Unlocked */
00958       __HAL_UNLOCK(hrtc);
00959
00960       return HAL_TIMEOUT;
00961     }
00962   }
00963
00964   /* Enable the write protection for RTC registers */
00965   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00966
00967   hrtc->State = HAL_RTC_STATE_READY;
00968
00969   /* Process Unlocked */
00970   __HAL_UNLOCK(hrtc);
00971
00972   return HAL_OK;
00973 }
00974
00975 /**
00976   * @brief  Gets wake up timer counter.
00977   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00978   *                the configuration information for RTC.
00979   * @retval Counter value
00980   */
00981 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
00982 {
00983   /* Get the counter value */
00984   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
00985 }
00986
00987 /**
00988   * @brief  This function handles Wake Up Timer interrupt request.
00989   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00990   *                the configuration information for RTC.
00991   * @retval None
00992   */
00993 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
00994 {
00995   if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
00996   {
00997     /* Get the status of the Interrupt */
00998     if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
00999     {
01000       /* WAKEUPTIMER callback */
01001       HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
01002
01003       /* Clear the WAKEUPTIMER interrupt pending bit */
01004       __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01005     }
01006   }
01007
01008   /* Clear the EXTI's line Flag for RTC WakeUpTimer */
01009   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
01010
01011   /* Change RTC state */
01012   hrtc->State = HAL_RTC_STATE_READY;
01013 }
01014
01015 /**
01016   * @brief  Wake Up Timer callback.
01017   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01018   *                the configuration information for RTC.
01019   * @retval None
01020   */
01021 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
01022 {
01023   /* Prevent unused argument(s) compilation warning */
01024   UNUSED(hrtc);
01025   /* NOTE : This function Should not be modified, when the callback is needed,
01026             the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
01027    */
01028 }
01029
01030 /**
01031   * @brief  This function handles Wake Up Timer Polling.
01032   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01033   *                the configuration information for RTC.
01034   * @param  Timeout: Timeout duration
01035   * @retval HAL status
01036   */
01037 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01038 {
01039   uint32_t tickstart = 0U;
01040
01041   /* Get tick */
01042   tickstart = HAL_GetTick();
01043
01044   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
01045   {
01046     if(Timeout != HAL_MAX_DELAY)
01047     {
01048       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01049       {
01050         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01051
01052         return HAL_TIMEOUT;
01053       }
01054     }
01055   }
01056
01057   /* Clear the WAKEUPTIMER Flag */
01058   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01059
01060   /* Change RTC state */
01061   hrtc->State = HAL_RTC_STATE_READY;
01062
01063   return HAL_OK;
01064 }
01065
01066 /**
01067   * @}
01068   */
01069
01070
01071 /** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
01072  *  @brief   Extension Peripheral Control functions
01073  *
01074 @verbatim
01075  ===============================================================================
01076               ##### Extension Peripheral Control functions #####
01077  ===============================================================================
01078     [..]
01079     This subsection provides functions allowing to
01080       (+) Write a data in a specified RTC Backup data register
01081       (+) Read a data in a specified RTC Backup data register
01082       (+) Set the Coarse calibration parameters.
01083       (+) Deactivate the Coarse calibration parameters
01084       (+) Set the Smooth calibration parameters.
01085       (+) Configure the Synchronization Shift Control Settings.
01086       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01087       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01088       (+) Enable the RTC reference clock detection.
01089       (+) Disable the RTC reference clock detection.
01090       (+) Enable the Bypass Shadow feature.
01091       (+) Disable the Bypass Shadow feature.
01092
01093 @endverbatim
01094   * @{
01095   */
01096
01097 /**
01098   * @brief  Writes a data in a specified RTC Backup data register.
01099   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01100   *                the configuration information for RTC.
01101   * @param  BackupRegister: RTC Backup data Register number.
01102   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01103   *                                 specify the register.
01104   * @param  Data: Data to be written in the specified RTC Backup data register.
01105   * @retval None
01106   */
01107 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
01108 {
01109   uint32_t tmp = 0U;
01110
01111   /* Check the parameters */
01112   assert_param(IS_RTC_BKP(BackupRegister));
01113
01114   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01115   tmp += (BackupRegister * 4U);
01116
01117   /* Write the specified register */
01118   *(__IO uint32_t *)tmp = (uint32_t)Data;
01119 }
01120
01121 /**
01122   * @brief  Reads data from the specified RTC Backup data Register.
01123   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01124   *                the configuration information for RTC.
01125   * @param  BackupRegister: RTC Backup data Register number.
01126   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01127   *                                 specify the register.
01128   * @retval Read value
01129   */
01130 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
01131 {
01132   uint32_t tmp = 0U;
01133
01134   /* Check the parameters */
01135   assert_param(IS_RTC_BKP(BackupRegister));
01136
01137   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01138   tmp += (BackupRegister * 4U);
01139
01140   /* Read the specified register */
01141   return (*(__IO uint32_t *)tmp);
01142 }
01143
01144 /**
01145   * @brief  Sets the Coarse calibration parameters.
01146   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01147   *                the configuration information for RTC.
01148   * @param  CalibSign: Specifies the sign of the coarse calibration value.
01149   *          This parameter can be  one of the following values :
01150   *             @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive
01151   *             @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
01152   * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
01153   *
01154   * @note   This Calibration value should be between 0 and 63 when using negative
01155   *         sign with a 2-ppm step.
01156   *
01157   * @note   This Calibration value should be between 0 and 126 when using positive
01158   *         sign with a 4-ppm step.
01159   * @retval HAL status
01160   */
01161 HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value)
01162 {
01163   /* Check the parameters */
01164   assert_param(IS_RTC_CALIB_SIGN(CalibSign));
01165   assert_param(IS_RTC_CALIB_VALUE(Value));
01166
01167   /* Process Locked */
01168   __HAL_LOCK(hrtc);
01169
01170   hrtc->State = HAL_RTC_STATE_BUSY;
01171
01172   /* Disable the write protection for RTC registers */
01173   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01174
01175   /* Set Initialization mode */
01176   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01177   {
01178     /* Enable the write protection for RTC registers */
01179     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01180
01181     /* Set RTC state*/
01182     hrtc->State = HAL_RTC_STATE_ERROR;
01183
01184     /* Process Unlocked */
01185     __HAL_UNLOCK(hrtc);
01186
01187     return HAL_ERROR;
01188   }
01189   else
01190   {
01191     /* Enable the Coarse Calibration */
01192     __HAL_RTC_COARSE_CALIB_ENABLE(hrtc);
01193
01194     /* Set the coarse calibration value */
01195     hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value);
01196
01197     /* Exit Initialization mode */
01198     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01199   }
01200
01201   /* Enable the write protection for RTC registers */
01202   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01203
01204   /* Change state */
01205   hrtc->State = HAL_RTC_STATE_READY;
01206
01207   /* Process Unlocked */
01208   __HAL_UNLOCK(hrtc);
01209
01210   return HAL_OK;
01211 }
01212
01213 /**
01214   * @brief  Deactivates the Coarse calibration parameters.
01215   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01216   *                the configuration information for RTC.
01217   * @retval HAL status
01218   */
01219 HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
01220 {
01221   /* Process Locked */
01222   __HAL_LOCK(hrtc);
01223
01224   hrtc->State = HAL_RTC_STATE_BUSY;
01225
01226   /* Disable the write protection for RTC registers */
01227   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01228
01229   /* Set Initialization mode */
01230   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01231   {
01232     /* Enable the write protection for RTC registers */
01233     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01234
01235     /* Set RTC state*/
01236     hrtc->State = HAL_RTC_STATE_ERROR;
01237
01238     /* Process Unlocked */
01239     __HAL_UNLOCK(hrtc);
01240
01241     return HAL_ERROR;
01242   }
01243   else
01244   {
01245     /* Enable the Coarse Calibration */
01246     __HAL_RTC_COARSE_CALIB_DISABLE(hrtc);
01247
01248     /* Exit Initialization mode */
01249     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01250   }
01251
01252   /* Enable the write protection for RTC registers */
01253   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01254
01255   /* Change state */
01256   hrtc->State = HAL_RTC_STATE_READY;
01257
01258   /* Process Unlocked */
01259   __HAL_UNLOCK(hrtc);
01260
01261   return HAL_OK;
01262 }
01263
01264 /**
01265   * @brief  Sets the Smooth calibration parameters.
01266   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01267   *                the configuration information for RTC.
01268   * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
01269   *          This parameter can be can be one of the following values :
01270   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
01271   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
01272   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
01273   * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
01274   *          This parameter can be one of the following values:
01275   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
01276   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
01277   * @param  SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
01278   *          This parameter can be one any value from 0 to 0x000001FF.
01279   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
01280   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
01281   *         SmouthCalibMinusPulsesValue must be equal to 0.
01282   * @retval HAL status
01283   */
01284 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
01285 {
01286   uint32_t tickstart = 0U;
01287
01288   /* Check the parameters */
01289   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
01290   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
01291   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
01292
01293   /* Process Locked */
01294   __HAL_LOCK(hrtc);
01295
01296   hrtc->State = HAL_RTC_STATE_BUSY;
01297
01298   /* Disable the write protection for RTC registers */
01299   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01300
01301   /* check if a calibration is pending*/
01302   if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01303   {
01304   /* Get tick */
01305   tickstart = HAL_GetTick();
01306
01307     /* check if a calibration is pending*/
01308     while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01309     {
01310       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01311       {
01312         /* Enable the write protection for RTC registers */
01313         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01314
01315         /* Change RTC state */
01316         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01317
01318         /* Process Unlocked */
01319         __HAL_UNLOCK(hrtc);
01320
01321         return HAL_TIMEOUT;
01322       }
01323     }
01324   }
01325
01326   /* Configure the Smooth calibration settings */
01327   hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
01328
01329   /* Enable the write protection for RTC registers */
01330   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01331
01332   /* Change RTC state */
01333   hrtc->State = HAL_RTC_STATE_READY;
01334
01335   /* Process Unlocked */
01336   __HAL_UNLOCK(hrtc);
01337
01338   return HAL_OK;
01339 }
01340
01341 /**
01342   * @brief  Configures the Synchronization Shift Control Settings.
01343   * @note   When REFCKON is set, firmware must not write to Shift control register.
01344   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01345   *                the configuration information for RTC.
01346   * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
01347   *          This parameter can be one of the following values :
01348   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
01349   *             @arg RTC_SHIFTADD1S_RESET: No effect.
01350   * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
01351   *          This parameter can be one any value from 0 to 0x7FFF.
01352   * @retval HAL status
01353   */
01354 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
01355 {
01356   uint32_t tickstart = 0U;
01357
01358   /* Check the parameters */
01359   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
01360   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
01361
01362   /* Process Locked */
01363   __HAL_LOCK(hrtc);
01364
01365   hrtc->State = HAL_RTC_STATE_BUSY;
01366
01367   /* Disable the write protection for RTC registers */
01368   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01369
01370   /* Get tick */
01371   tickstart = HAL_GetTick();
01372
01373     /* Wait until the shift is completed*/
01374     while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
01375     {
01376       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01377       {
01378         /* Enable the write protection for RTC registers */
01379         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01380
01381         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01382
01383         /* Process Unlocked */
01384         __HAL_UNLOCK(hrtc);
01385
01386         return HAL_TIMEOUT;
01387       }
01388     }
01389
01390     /* Check if the reference clock detection is disabled */
01391     if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
01392     {
01393       /* Configure the Shift settings */
01394       hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
01395
01396       /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
01397       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
01398       {
01399         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01400         {
01401           /* Enable the write protection for RTC registers */
01402           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01403
01404           hrtc->State = HAL_RTC_STATE_ERROR;
01405
01406           /* Process Unlocked */
01407           __HAL_UNLOCK(hrtc);
01408
01409           return HAL_ERROR;
01410         }
01411       }
01412     }
01413     else
01414     {
01415       /* Enable the write protection for RTC registers */
01416       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01417
01418       /* Change RTC state */
01419       hrtc->State = HAL_RTC_STATE_ERROR;
01420
01421       /* Process Unlocked */
01422       __HAL_UNLOCK(hrtc);
01423
01424       return HAL_ERROR;
01425     }
01426
01427   /* Enable the write protection for RTC registers */
01428   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01429
01430   /* Change RTC state */
01431   hrtc->State = HAL_RTC_STATE_READY;
01432
01433   /* Process Unlocked */
01434   __HAL_UNLOCK(hrtc);
01435
01436   return HAL_OK;
01437 }
01438
01439 /**
01440   * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01441   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01442   *                the configuration information for RTC.
01443   * @param  CalibOutput: Select the Calibration output Selection .
01444   *          This parameter can be one of the following values:
01445   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01446   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01447   * @retval HAL status
01448   */
01449 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
01450 {
01451   /* Check the parameters */
01452   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01453
01454   /* Process Locked */
01455   __HAL_LOCK(hrtc);
01456
01457   hrtc->State = HAL_RTC_STATE_BUSY;
01458
01459   /* Disable the write protection for RTC registers */
01460   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01461
01462   /* Clear flags before config */
01463   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
01464
01465   /* Configure the RTC_CR register */
01466   hrtc->Instance->CR |= (uint32_t)CalibOutput;
01467
01468   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
01469
01470   /* Enable the write protection for RTC registers */
01471   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01472
01473   /* Change RTC state */
01474   hrtc->State = HAL_RTC_STATE_READY;
01475
01476   /* Process Unlocked */
01477   __HAL_UNLOCK(hrtc);
01478
01479   return HAL_OK;
01480 }
01481
01482 /**
01483   * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01484   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01485   *                the configuration information for RTC.
01486   * @retval HAL status
01487   */
01488 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
01489 {
01490   /* Process Locked */
01491   __HAL_LOCK(hrtc);
01492
01493   hrtc->State = HAL_RTC_STATE_BUSY;
01494
01495   /* Disable the write protection for RTC registers */
01496   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01497
01498   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
01499
01500   /* Enable the write protection for RTC registers */
01501   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01502
01503   /* Change RTC state */
01504   hrtc->State = HAL_RTC_STATE_READY;
01505
01506   /* Process Unlocked */
01507   __HAL_UNLOCK(hrtc);
01508
01509   return HAL_OK;
01510 }
01511
01512 /**
01513   * @brief  Enables the RTC reference clock detection.
01514   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01515   *                the configuration information for RTC.
01516   * @retval HAL status
01517   */
01518 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
01519 {
01520   /* Process Locked */
01521   __HAL_LOCK(hrtc);
01522
01523   hrtc->State = HAL_RTC_STATE_BUSY;
01524
01525   /* Disable the write protection for RTC registers */
01526   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01527
01528   /* Set Initialization mode */
01529   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01530   {
01531     /* Enable the write protection for RTC registers */
01532     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01533
01534     /* Set RTC state*/
01535     hrtc->State = HAL_RTC_STATE_ERROR;
01536
01537     /* Process Unlocked */
01538     __HAL_UNLOCK(hrtc);
01539
01540     return HAL_ERROR;
01541   }
01542   else
01543   {
01544     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
01545
01546     /* Exit Initialization mode */
01547     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01548   }
01549
01550   /* Enable the write protection for RTC registers */
01551   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01552
01553    /* Change RTC state */
01554   hrtc->State = HAL_RTC_STATE_READY;
01555
01556   /* Process Unlocked */
01557   __HAL_UNLOCK(hrtc);
01558
01559   return HAL_OK;
01560 }
01561
01562 /**
01563   * @brief  Disable the RTC reference clock detection.
01564   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01565   *                the configuration information for RTC.
01566   * @retval HAL status
01567   */
01568 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
01569 {
01570   /* Process Locked */
01571   __HAL_LOCK(hrtc);
01572
01573   hrtc->State = HAL_RTC_STATE_BUSY;
01574
01575   /* Disable the write protection for RTC registers */
01576   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01577
01578   /* Set Initialization mode */
01579   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01580   {
01581     /* Enable the write protection for RTC registers */
01582     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01583
01584     /* Set RTC state*/
01585     hrtc->State = HAL_RTC_STATE_ERROR;
01586
01587     /* Process Unlocked */
01588     __HAL_UNLOCK(hrtc);
01589
01590     return HAL_ERROR;
01591   }
01592   else
01593   {
01594     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
01595
01596     /* Exit Initialization mode */
01597     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01598   }
01599
01600   /* Enable the write protection for RTC registers */
01601   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01602
01603   /* Change RTC state */
01604   hrtc->State = HAL_RTC_STATE_READY;
01605
01606   /* Process Unlocked */
01607   __HAL_UNLOCK(hrtc);
01608
01609   return HAL_OK;
01610 }
01611
01612 /**
01613   * @brief  Enables the Bypass Shadow feature.
01614   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01615   *                the configuration information for RTC.
01616   * @note   When the Bypass Shadow is enabled the calendar value are taken
01617   *         directly from the Calendar counter.
01618   * @retval HAL status
01619   */
01620 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
01621 {
01622   /* Process Locked */
01623   __HAL_LOCK(hrtc);
01624
01625   hrtc->State = HAL_RTC_STATE_BUSY;
01626
01627   /* Disable the write protection for RTC registers */
01628   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01629
01630   /* Set the BYPSHAD bit */
01631   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
01632
01633   /* Enable the write protection for RTC registers */
01634   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01635
01636   /* Change RTC state */
01637   hrtc->State = HAL_RTC_STATE_READY;
01638
01639   /* Process Unlocked */
01640   __HAL_UNLOCK(hrtc);
01641
01642   return HAL_OK;
01643 }
01644
01645 /**
01646   * @brief  Disables the Bypass Shadow feature.
01647   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01648   *                the configuration information for RTC.
01649   * @note   When the Bypass Shadow is enabled the calendar value are taken
01650   *         directly from the Calendar counter.
01651   * @retval HAL status
01652   */
01653 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
01654 {
01655   /* Process Locked */
01656   __HAL_LOCK(hrtc);
01657
01658   hrtc->State = HAL_RTC_STATE_BUSY;
01659
01660   /* Disable the write protection for RTC registers */
01661   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01662
01663   /* Reset the BYPSHAD bit */
01664   hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
01665
01666   /* Enable the write protection for RTC registers */
01667   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01668
01669   /* Change RTC state */
01670   hrtc->State = HAL_RTC_STATE_READY;
01671
01672   /* Process Unlocked */
01673   __HAL_UNLOCK(hrtc);
01674
01675   return HAL_OK;
01676 }
01677
01678 /**
01679   * @}
01680   */
01681
01682   /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
01683  *  @brief    Extended features functions
01684  *
01685 @verbatim
01686  ===============================================================================
01687                  ##### Extended features functions #####
01688  ===============================================================================
01689     [..]  This section provides functions allowing to:
01690       (+) RTC Alarm B callback
01691       (+) RTC Poll for Alarm B request
01692
01693 @endverbatim
01694   * @{
01695   */
01696
01697 /**
01698   * @brief  Alarm B callback.
01699   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01700   *                the configuration information for RTC.
01701   * @retval None
01702   */
01703 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01704 {
01705   /* Prevent unused argument(s) compilation warning */
01706   UNUSED(hrtc);
01707   /* NOTE : This function Should not be modified, when the callback is needed,
01708             the HAL_RTC_AlarmBEventCallback could be implemented in the user file
01709    */
01710 }
01711
01712 /**
01713   * @brief  This function handles AlarmB Polling request.
01714   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
01715   *                the configuration information for RTC.
01716   * @param  Timeout: Timeout duration
01717   * @retval HAL status
01718   */
01719 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01720 {
01721   uint32_t tickstart = 0U;
01722
01723   /* Get tick */
01724   tickstart = HAL_GetTick();
01725
01726   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
01727   {
01728     if(Timeout != HAL_MAX_DELAY)
01729     {
01730       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01731       {
01732         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01733         return HAL_TIMEOUT;
01734       }
01735     }
01736   }
01737
01738   /* Clear the Alarm Flag */
01739   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01740
01741   /* Change RTC state */
01742   hrtc->State = HAL_RTC_STATE_READY;
01743
01744   return HAL_OK;
01745 }
01746
01747 /**
01748   * @}
01749   */
01750
01751 /**
01752   * @}
01753   */
01754
01755 #endif /* HAL_RTC_MODULE_ENABLED */
01756 /**
01757   * @}
01758   */
01759
01760 /**
01761   * @}
01762   */
01763
01764 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_rtc_ex.h Source File

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stm32f4xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of RTC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_RTC_EX_H
00040 #define __STM32F4xx_HAL_RTC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  RTC Tamper structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00068                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
00069
00070   uint32_t PinSelection;                /*!< Specifies the Tamper Pin.
00071                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Selection */
00072
00073   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00074                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
00075
00076   uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
00077                                              This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
00078
00079   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00080                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
00081
00082   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00083                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
00084
00085   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00086                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
00087
00088   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00089                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00090 }RTC_TamperTypeDef;
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported constants --------------------------------------------------------*/
00096 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00097   * @{
00098   */
00099
00100 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
00101   * @{
00102   */
00103 #define RTC_BKP_DR0                       ((uint32_t)0x00000000U)
00104 #define RTC_BKP_DR1                       ((uint32_t)0x00000001U)
00105 #define RTC_BKP_DR2                       ((uint32_t)0x00000002U)
00106 #define RTC_BKP_DR3                       ((uint32_t)0x00000003U)
00107 #define RTC_BKP_DR4                       ((uint32_t)0x00000004U)
00108 #define RTC_BKP_DR5                       ((uint32_t)0x00000005U)
00109 #define RTC_BKP_DR6                       ((uint32_t)0x00000006U)
00110 #define RTC_BKP_DR7                       ((uint32_t)0x00000007U)
00111 #define RTC_BKP_DR8                       ((uint32_t)0x00000008U)
00112 #define RTC_BKP_DR9                       ((uint32_t)0x00000009U)
00113 #define RTC_BKP_DR10                      ((uint32_t)0x0000000AU)
00114 #define RTC_BKP_DR11                      ((uint32_t)0x0000000BU)
00115 #define RTC_BKP_DR12                      ((uint32_t)0x0000000CU)
00116 #define RTC_BKP_DR13                      ((uint32_t)0x0000000DU)
00117 #define RTC_BKP_DR14                      ((uint32_t)0x0000000EU)
00118 #define RTC_BKP_DR15                      ((uint32_t)0x0000000FU)
00119 #define RTC_BKP_DR16                      ((uint32_t)0x00000010U)
00120 #define RTC_BKP_DR17                      ((uint32_t)0x00000011U)
00121 #define RTC_BKP_DR18                      ((uint32_t)0x00000012U)
00122 #define RTC_BKP_DR19                      ((uint32_t)0x00000013U)
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
00128   * @{
00129   */
00130 #define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000U)
00131 #define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008U)
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
00137   * @{
00138   */
00139 #define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
00140 #define RTC_TAMPER_2                    RTC_TAFCR_TAMP2E
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
00146   * @{
00147   */
00148 #define RTC_TAMPERPIN_DEFAULT               ((uint32_t)0x00000000U)
00149 #define RTC_TAMPERPIN_POS1                  ((uint32_t)0x00010000U)
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
00155   * @{
00156   */
00157 #define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000U)
00158 #define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00020000U)
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
00164   * @{
00165   */
00166 #define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000U)
00167 #define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002U)
00168 #define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
00169 #define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
00175   * @{
00176   */
00177 #define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
00178
00179 #define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800U)  /*!< Tamper is activated after 2
00180                                                                 consecutive samples at the active level */
00181 #define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000U)  /*!< Tamper is activated after 4
00182                                                                 consecutive samples at the active level */
00183 #define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800U)  /*!< Tamper is activated after 8
00184                                                                 consecutive samples at the active level. */
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
00190   * @{
00191   */
00192 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000U)  /*!< Each of the tamper inputs are sampled
00193                                                                              with a frequency =  RTCCLK / 32768 */
00194 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100U)  /*!< Each of the tamper inputs are sampled
00195                                                                              with a frequency =  RTCCLK / 16384 */
00196 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200U)  /*!< Each of the tamper inputs are sampled
00197                                                                              with a frequency =  RTCCLK / 8192  */
00198 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300U)  /*!< Each of the tamper inputs are sampled
00199                                                                              with a frequency =  RTCCLK / 4096  */
00200 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400U)  /*!< Each of the tamper inputs are sampled
00201                                                                              with a frequency =  RTCCLK / 2048  */
00202 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500U)  /*!< Each of the tamper inputs are sampled
00203                                                                              with a frequency =  RTCCLK / 1024  */
00204 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600U)  /*!< Each of the tamper inputs are sampled
00205                                                                              with a frequency =  RTCCLK / 512   */
00206 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700U)  /*!< Each of the tamper inputs are sampled
00207                                                                              with a frequency =  RTCCLK / 256   */
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
00213   * @{
00214   */
00215 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)  /*!< Tamper pins are pre-charged before
00216                                                                          sampling during 1 RTCCLK cycle */
00217 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)  /*!< Tamper pins are pre-charged before
00218                                                                          sampling during 2 RTCCLK cycles */
00219 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)  /*!< Tamper pins are pre-charged before
00220                                                                          sampling during 4 RTCCLK cycles */
00221 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)  /*!< Tamper pins are pre-charged before
00222                                                                          sampling during 8 RTCCLK cycles */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
00228   * @{
00229   */
00230 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAFCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
00231 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)        /*!< TimeStamp on Tamper Detection event is not saved */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup  RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
00237   * @{
00238   */
00239 #define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000U)            /*!< TimeStamp on Tamper Detection event saved        */
00240 #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
00246   * @{
00247   */
00248 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000U)
00249 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001U)
00250 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002U)
00251 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003U)
00252 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004U)
00253 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006U)
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
00259   * @{
00260   */
00261 #define RTC_CALIBSIGN_POSITIVE            ((uint32_t)0x00000000U)
00262 #define RTC_CALIBSIGN_NEGATIVE            ((uint32_t)0x00000080U)
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
00268   * @{
00269   */
00270 #define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00271                                                                     period is 32s,  else 2exp20 RTCCLK seconds */
00272 #define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00273                                                                     period is 16s, else 2exp19 RTCCLK seconds */
00274 #define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00275                                                                     period is 8s, else 2exp18 RTCCLK seconds */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
00281   * @{
00282   */
00283 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000U)  /*!< The number of RTCCLK pulses added
00284                                                                        during a X -second window = Y - CALM[8:0]
00285                                                                        with Y = 512, 256, 128 when X = 32, 16, 8 */
00286 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000U)  /*!< The number of RTCCLK pulses subbstited
00287                                                                        during a 32-second window = CALM[8:0] */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
00293   * @{
00294   */
00295 #define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000U)
00296 #define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000U)
00297 /**
00298   * @}
00299   */
00300
00301
00302  /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
00303   * @{
00304   */
00305 #define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000U)
00306 #define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000U)
00307 /**
00308   * @}
00309   */
00310
00311 /**
00312   * @}
00313   */
00314
00315 /* Exported macro ------------------------------------------------------------*/
00316 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00317   * @{
00318   */
00319
00320 /* ---------------------------------WAKEUPTIMER---------------------------------*/
00321 /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
00322   * @{
00323   */
00324
00325 /**
00326   * @brief  Enable the RTC WakeUp Timer peripheral.
00327   * @param  __HANDLE__: specifies the RTC handle.
00328   * @retval None
00329   */
00330 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00331
00332 /**
00333   * @brief  Disable the RTC Wake-up Timer peripheral.
00334   * @param  __HANDLE__: specifies the RTC handle.
00335   * @retval None
00336   */
00337 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00338
00339 /**
00340   * @brief  Enable the RTC WakeUpTimer interrupt.
00341   * @param  __HANDLE__: specifies the RTC handle.
00342   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
00343   *         This parameter can be:
00344   *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
00345   * @retval None
00346   */
00347 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00348
00349 /**
00350   * @brief  Disable the RTC WakeUpTimer interrupt.
00351   * @param  __HANDLE__: specifies the RTC handle.
00352   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
00353   *         This parameter can be:
00354   *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
00355   * @retval None
00356   */
00357 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00358
00359 /**
00360   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00361   * @param  __HANDLE__: specifies the RTC handle.
00362   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
00363   *         This parameter can be:
00364   *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
00365   * @retval None
00366   */
00367 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
00368
00369 /**
00370   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
00371   * @param  __HANDLE__: specifies the RTC handle.
00372   * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
00373   *         This parameter can be:
00374   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00375   * @retval None
00376   */
00377 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00378
00379 /**
00380   * @brief  Get the selected RTC WakeUpTimer's flag status.
00381   * @param  __HANDLE__: specifies the RTC handle.
00382   * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to check.
00383   *          This parameter can be:
00384   *             @arg RTC_FLAG_WUTF
00385   *             @arg RTC_FLAG_WUTWF
00386   * @retval None
00387   */
00388 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)          (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00389
00390 /**
00391   * @brief  Clear the RTC Wake Up timer's pending flags.
00392   * @param  __HANDLE__: specifies the RTC handle.
00393   * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
00394   *         This parameter can be:
00395   *            @arg RTC_FLAG_WUTF
00396   * @retval None
00397   */
00398 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00399
00400 /**
00401   * @brief  Enable interrupt on the RTC Wake-up Timer associated Exti line.
00402   * @retval None
00403   */
00404 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00405
00406 /**
00407   * @brief  Disable interrupt on the RTC Wake-up Timer associated Exti line.
00408   * @retval None
00409   */
00410 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00411
00412 /**
00413   * @brief  Enable event on the RTC Wake-up Timer associated Exti line.
00414   * @retval None.
00415   */
00416 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00417
00418 /**
00419   * @brief  Disable event on the RTC Wake-up Timer associated Exti line.
00420   * @retval None.
00421   */
00422 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00423
00424 /**
00425   * @brief  Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
00426   * @retval None.
00427   */
00428 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00429
00430 /**
00431   * @brief  Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
00432   * @retval None.
00433   */
00434 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00435
00436 /**
00437   * @brief  Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
00438   * @retval None.
00439   */
00440 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00441
00442 /**
00443   * @brief  Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
00444   * @retval None.
00445   */
00446 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00447
00448 /**
00449   * @brief  Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
00450   * @retval None.
00451   */
00452 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
00453                                                                      __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
00454                                                                    } while(0)
00455
00456 /**
00457   * @brief  Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
00458   * This parameter can be:
00459   * @retval None.
00460   */
00461 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
00462                                                                       __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
00463                                                                     } while(0)
00464
00465 /**
00466   * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
00467   * @retval Line Status.
00468   */
00469 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00470
00471 /**
00472   * @brief Clear the RTC Wake-up Timer associated Exti line flag.
00473   * @retval None.
00474   */
00475 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00476
00477 /**
00478   * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
00479   * @retval None.
00480   */
00481 #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00482
00483 /**
00484   * @}
00485   */
00486
00487 /* ---------------------------------TIMESTAMP---------------------------------*/
00488 /** @defgroup RTCEx_Timestamp RTC Timestamp
00489   * @{
00490   */
00491
00492 /**
00493   * @brief  Enable the RTC TimeStamp peripheral.
00494   * @param  __HANDLE__: specifies the RTC handle.
00495   * @retval None
00496   */
00497 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00498
00499 /**
00500   * @brief  Disable the RTC TimeStamp peripheral.
00501   * @param  __HANDLE__: specifies the RTC handle.
00502   * @retval None
00503   */
00504 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00505
00506 /**
00507   * @brief  Enable the RTC TimeStamp interrupt.
00508   * @param  __HANDLE__: specifies the RTC handle.
00509   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
00510   *         This parameter can be:
00511   *            @arg RTC_IT_TS: TimeStamp interrupt
00512   * @retval None
00513   */
00514 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00515
00516 /**
00517   * @brief  Disable the RTC TimeStamp interrupt.
00518   * @param  __HANDLE__: specifies the RTC handle.
00519   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
00520   *         This parameter can be:
00521   *            @arg RTC_IT_TS: TimeStamp interrupt
00522   * @retval None
00523   */
00524 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00525
00526 /**
00527   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00528   * @param  __HANDLE__: specifies the RTC handle.
00529   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
00530   *         This parameter can be:
00531   *            @arg RTC_IT_TS: TimeStamp interrupt
00532   * @retval None
00533   */
00534 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)         (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
00535
00536 /**
00537   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
00538   * @param  __HANDLE__: specifies the RTC handle.
00539   * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
00540   *         This parameter can be:
00541   *            @arg RTC_IT_TS: TimeStamp interrupt
00542   * @retval None
00543   */
00544 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00545
00546 /**
00547   * @brief  Get the selected RTC TimeStamp's flag status.
00548   * @param  __HANDLE__: specifies the RTC handle.
00549   * @param  __FLAG__: specifies the RTC TimeStamp flag to check.
00550   *         This parameter can be:
00551   *            @arg RTC_FLAG_TSF
00552   *            @arg RTC_FLAG_TSOVF
00553   * @retval None
00554   */
00555 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00556
00557 /**
00558   * @brief  Clear the RTC Time Stamp's pending flags.
00559   * @param  __HANDLE__: specifies the RTC handle.
00560   * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
00561   *          This parameter can be:
00562   *             @arg RTC_FLAG_TSF
00563   * @retval None
00564   */
00565 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)          ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00566
00567 /**
00568   * @}
00569   */
00570
00571 /* ---------------------------------TAMPER------------------------------------*/
00572 /** @defgroup RTCEx_Tamper RTC Tamper
00573   * @{
00574   */
00575
00576 /**
00577   * @brief  Enable the RTC Tamper1 input detection.
00578   * @param  __HANDLE__: specifies the RTC handle.
00579   * @retval None
00580   */
00581 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
00582
00583 /**
00584   * @brief  Disable the RTC Tamper1 input detection.
00585   * @param  __HANDLE__: specifies the RTC handle.
00586   * @retval None
00587   */
00588 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
00589
00590 /**
00591   * @brief  Enable the RTC Tamper2 input detection.
00592   * @param  __HANDLE__: specifies the RTC handle.
00593   * @retval None
00594   */
00595 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
00596
00597 /**
00598   * @brief  Disable the RTC Tamper2 input detection.
00599   * @param  __HANDLE__: specifies the RTC handle.
00600   * @retval None
00601   */
00602 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
00603
00604 /**
00605   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
00606   * @param  __HANDLE__: specifies the RTC handle.
00607   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
00608   *         This parameter can be:
00609   *            @arg  RTC_IT_TAMP1
00610   *            @arg  RTC_IT_TAMP2
00611   * @retval None
00612   */
00613 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
00614
00615 /**
00616   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
00617   * @param  __HANDLE__: specifies the RTC handle.
00618   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
00619   *         This parameter can be:
00620   *            @arg RTC_IT_TAMP: Tamper interrupt
00621   * @retval None
00622   */
00623 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00624
00625 /**
00626   * @brief  Get the selected RTC Tamper's flag status.
00627   * @param  __HANDLE__: specifies the RTC handle.
00628   * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
00629   *          This parameter can be:
00630   *             @arg RTC_FLAG_TAMP1F
00631   *             @arg RTC_FLAG_TAMP2F
00632   * @retval None
00633   */
00634 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00635
00636 /**
00637   * @brief  Clear the RTC Tamper's pending flags.
00638   * @param  __HANDLE__: specifies the RTC handle.
00639   * @param  __FLAG__: specifies the RTC Tamper Flag to clear.
00640   *          This parameter can be:
00641   *             @arg RTC_FLAG_TAMP1F
00642   *             @arg RTC_FLAG_TAMP2F
00643   * @retval None
00644   */
00645 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00646 /**
00647   * @}
00648   */
00649
00650 /* --------------------------TAMPER/TIMESTAMP---------------------------------*/
00651 /** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
00652   * @{
00653   */
00654
00655 /**
00656   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
00657   * @retval None
00658   */
00659 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00660
00661 /**
00662   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
00663   * @retval None
00664   */
00665 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00666
00667 /**
00668   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
00669   * @retval None.
00670   */
00671 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00672
00673 /**
00674   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
00675   * @retval None.
00676   */
00677 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00678
00679 /**
00680   * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00681   * @retval None.
00682   */
00683 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00684
00685 /**
00686   * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00687   * @retval None.
00688   */
00689 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00690
00691 /**
00692   * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00693   * @retval None.
00694   */
00695 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00696
00697 /**
00698   * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00699   * @retval None.
00700   */
00701 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00702
00703 /**
00704   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00705   * @retval None.
00706   */
00707 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
00708                                                                           __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
00709                                                                         } while(0)
00710
00711 /**
00712   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00713   * This parameter can be:
00714   * @retval None.
00715   */
00716 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
00717                                                                            __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
00718                                                                          } while(0)
00719
00720 /**
00721   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
00722   * @retval Line Status.
00723   */
00724 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00725
00726 /**
00727   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
00728   * @retval None.
00729   */
00730 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00731
00732 /**
00733   * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
00734   * @retval None.
00735   */
00736 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00737 /**
00738   * @}
00739   */
00740
00741 /* ------------------------------Calibration----------------------------------*/
00742 /** @defgroup RTCEx_Calibration RTC Calibration
00743   * @{
00744   */
00745
00746 /**
00747   * @brief  Enable the Coarse calibration process.
00748   * @param  __HANDLE__: specifies the RTC handle.
00749   * @retval None
00750   */
00751 #define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
00752
00753 /**
00754   * @brief  Disable the Coarse calibration process.
00755   * @param  __HANDLE__: specifies the RTC handle.
00756   * @retval None
00757   */
00758 #define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
00759
00760 /**
00761   * @brief  Enable the RTC calibration output.
00762   * @param  __HANDLE__: specifies the RTC handle.
00763   * @retval None
00764   */
00765 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
00766
00767 /**
00768   * @brief  Disable the calibration output.
00769   * @param  __HANDLE__: specifies the RTC handle.
00770   * @retval None
00771   */
00772 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
00773
00774 /**
00775   * @brief  Enable the clock reference detection.
00776   * @param  __HANDLE__: specifies the RTC handle.
00777   * @retval None
00778   */
00779 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
00780
00781 /**
00782   * @brief  Disable the clock reference detection.
00783   * @param  __HANDLE__: specifies the RTC handle.
00784   * @retval None
00785   */
00786 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
00787
00788 /**
00789   * @brief  Get the selected RTC shift operation's flag status.
00790   * @param  __HANDLE__: specifies the RTC handle.
00791   * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
00792   *          This parameter can be:
00793   *             @arg RTC_FLAG_SHPF
00794   * @retval None
00795   */
00796 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
00797 /**
00798   * @}
00799   */
00800
00801 /**
00802   * @}
00803   */
00804
00805 /* Exported functions --------------------------------------------------------*/
00806 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00807   * @{
00808   */
00809
00810 /** @addtogroup RTCEx_Exported_Functions_Group1
00811   * @{
00812   */
00813 /* RTC TimeStamp and Tamper functions *****************************************/
00814 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00815 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00816 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
00817 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
00818
00819 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00820 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00821 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
00822 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
00823
00824 void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
00825 void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
00826 void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
00827 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00828 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00829 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00830 /**
00831   * @}
00832   */
00833
00834 /** @addtogroup RTCEx_Exported_Functions_Group2
00835   * @{
00836   */
00837 /* RTC Wake-up functions ******************************************************/
00838 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00839 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00840 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
00841 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
00842 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
00843 void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
00844 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00845 /**
00846   * @}
00847   */
00848
00849 /** @addtogroup RTCEx_Exported_Functions_Group3
00850   * @{
00851   */
00852 /* Extension Control functions ************************************************/
00853 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
00854 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
00855
00856 HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
00857 HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
00858 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
00859 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
00860 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
00861 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
00862 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
00863 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
00864 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
00865 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
00866 /**
00867   * @}
00868   */
00869
00870 /** @addtogroup RTCEx_Exported_Functions_Group4
00871   * @{
00872   */
00873 /* Extension RTC features functions *******************************************/
00874 void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
00875 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00876 /**
00877   * @}
00878   */
00879
00880 /**
00881   * @}
00882   */
00883
00884 /* Private types -------------------------------------------------------------*/
00885 /* Private variables ---------------------------------------------------------*/
00886 /* Private constants ---------------------------------------------------------*/
00887 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
00888   * @{
00889   */
00890 #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_MR21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
00891 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_MR22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */
00892 /**
00893   * @}
00894   */
00895
00896 /* Private macros ------------------------------------------------------------*/
00897 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
00898   * @{
00899   */
00900
00901 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
00902   * @{
00903   */
00904 #define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0)  || \
00905                                            ((BKP) == RTC_BKP_DR1)  || \
00906                                            ((BKP) == RTC_BKP_DR2)  || \
00907                                            ((BKP) == RTC_BKP_DR3)  || \
00908                                            ((BKP) == RTC_BKP_DR4)  || \
00909                                            ((BKP) == RTC_BKP_DR5)  || \
00910                                            ((BKP) == RTC_BKP_DR6)  || \
00911                                            ((BKP) == RTC_BKP_DR7)  || \
00912                                            ((BKP) == RTC_BKP_DR8)  || \
00913                                            ((BKP) == RTC_BKP_DR9)  || \
00914                                            ((BKP) == RTC_BKP_DR10) || \
00915                                            ((BKP) == RTC_BKP_DR11) || \
00916                                            ((BKP) == RTC_BKP_DR12) || \
00917                                            ((BKP) == RTC_BKP_DR13) || \
00918                                            ((BKP) == RTC_BKP_DR14) || \
00919                                            ((BKP) == RTC_BKP_DR15) || \
00920                                            ((BKP) == RTC_BKP_DR16) || \
00921                                            ((BKP) == RTC_BKP_DR17) || \
00922                                            ((BKP) == RTC_BKP_DR18) || \
00923                                            ((BKP) == RTC_BKP_DR19))
00924 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
00925                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
00926 #define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
00927
00928 #define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
00929                                 ((PIN) == RTC_TAMPERPIN_POS1))
00930
00931 #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
00932                                    ((PIN) == RTC_TIMESTAMPPIN_POS1))
00933
00934 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
00935                                         ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
00936                                         ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
00937                                         ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
00938 #define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
00939                                        ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
00940                                        ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
00941                                        ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
00942 #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
00943                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
00944                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
00945                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
00946                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
00947                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
00948                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
00949                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
00950 #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
00951                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
00952                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
00953                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
00954 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
00955                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
00956 #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
00957                                            ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
00958 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
00959                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
00960                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
00961                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
00962                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
00963                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
00964
00965 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFFU)
00966 #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
00967                                  ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
00968
00969 #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
00970
00971 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
00972                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
00973                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
00974 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
00975                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
00976
00977 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
00978 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
00979                                  ((SEL) == RTC_SHIFTADD1S_SET))
00980 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
00981 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
00982                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
00983 /**
00984   * @}
00985   */
00986
00987 /**
00988   * @}
00989   */
00990
00991 /**
00992   * @}
00993   */
00994
00995 /**
00996   * @}
00997   */
00998
00999 #ifdef __cplusplus
01000 }
01001 #endif
01002
01003 #endif /* __STM32F4xx_HAL_RTC_EX_H */
01004
01005 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai.c Source File

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stm32f4xx_hal_sai.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sai.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   SAI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Audio Interface (SAI) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + I/O operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                   ##### How to use this driver #####
00018   ==============================================================================
00019
00020   [..]
00021     The SAI HAL driver can be used as follows:
00022
00023     (#) Declare a SAI_HandleTypeDef handle structure.
00024     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
00025         (##) Enable the SAI interface clock.
00026         (##) SAI pins configuration:
00027             (+++) Enable the clock for the SAI GPIOs.
00028             (+++) Configure these SAI pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
00030              and HAL_SAI_Receive_IT() APIs):
00031             (+++) Configure the SAI interrupt priority.
00032             (+++) Enable the NVIC SAI IRQ handle.
00033
00034         (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
00035              and HAL_SAI_Receive_DMA() APIs):
00036             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00037             (+++) Enable the DMAx interface clock.
00038             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx Stream.
00040             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00042                 DMA Tx/Rx Stream.
00043
00044    (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00045        using HAL_SAI_Init() function.
00046
00047    -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
00048        will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
00049        inside the transmit and receive process.
00050
00051   [..]
00052    (@) SAI Clock Source configuration is managed differently depending on the selected
00053        STM32F4 devices :
00054        (+@) For STM32F446xx devices, the configuration is managed through RCCEx_PeriphCLKConfig()
00055             function in the HAL RCC drivers
00056        (+@) For STM32F439xx/STM32F437xx/STM32F429xx/STM32F427xx devices, the configuration
00057             is managed within HAL SAI drivers through HAL_SAI_Init() function using
00058             ClockSource field of SAI_InitTypeDef structure.
00059   [..]
00060    (@) Make sure that either:
00061        (+@) I2S PLL is configured or
00062        (+@) SAI PLL is configured or
00063        (+@) External clock source is configured after setting correctly
00064             the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
00065
00066   [..]
00067     (@) In master Tx mode: enabling the audio block immediately generates the bit clock
00068         for the external slaves even if there is no data in the FIFO, However FS signal
00069         generation is conditioned by the presence of data in the FIFO.
00070
00071   [..]
00072     (@) In master Rx mode: enabling the audio block immediately generates the bit clock
00073         and FS signal for the external slaves.
00074
00075   [..]
00076     (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
00077         (+@)  First bit Offset <= (SLOT size - Data size)
00078         (+@)  Data size <= SLOT size
00079         (+@)  Number of SLOT x SLOT size = Frame length
00080         (+@)  The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
00081
00082   [..]
00083      Three operation modes are available within this driver:
00084
00085    *** Polling mode IO operation ***
00086    =================================
00087    [..]
00088      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
00089      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
00090
00091    *** Interrupt mode IO operation ***
00092    ===================================
00093    [..]
00094      (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT()
00095      (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
00096          add his own code by customization of function pointer HAL_SAI_TxCpltCallback
00097      (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT()
00098      (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
00099          add his own code by customization of function pointer HAL_SAI_RxCpltCallback
00100      (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
00101          add his own code by customization of function pointer HAL_SAI_ErrorCallback
00102
00103    *** DMA mode IO operation ***
00104    ==============================
00105    [..]
00106      (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA()
00107      (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can
00108          add his own code by customization of function pointer HAL_SAI_TxCpltCallback
00109      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA()
00110      (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can
00111          add his own code by customization of function pointer HAL_SAI_RxCpltCallback
00112      (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can
00113          add his own code by customization of function pointer HAL_SAI_ErrorCallback
00114      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
00115      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
00116      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
00117
00118    *** SAI HAL driver macros list ***
00119    =============================================
00120    [..]
00121      Below the list of most used macros in USART HAL driver :
00122
00123       (+) __HAL_SAI_ENABLE: Enable the SAI peripheral
00124       (+) __HAL_SAI_DISABLE: Disable the SAI peripheral
00125       (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts
00126       (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts
00127       (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is
00128           enabled or disabled
00129       (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not
00130
00131   @endverbatim
00132   ******************************************************************************
00133   * @attention
00134   *
00135   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00136   *
00137   * Redistribution and use in source and binary forms, with or without modification,
00138   * are permitted provided that the following conditions are met:
00139   *   1. Redistributions of source code must retain the above copyright notice,
00140   *      this list of conditions and the following disclaimer.
00141   *   2. Redistributions in binary form must reproduce the above copyright notice,
00142   *      this list of conditions and the following disclaimer in the documentation
00143   *      and/or other materials provided with the distribution.
00144   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00145   *      may be used to endorse or promote products derived from this software
00146   *      without specific prior written permission.
00147   *
00148   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00149   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00150   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00151   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00152   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00153   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00154   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00155   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00156   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00157   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00158   *
00159   ******************************************************************************
00160   */
00161
00162 /* Includes ------------------------------------------------------------------*/
00163 #include "stm32f4xx_hal.h"
00164
00165 /** @addtogroup STM32F4xx_HAL_Driver
00166   * @{
00167   */
00168
00169 /** @defgroup SAI SAI
00170   * @brief SAI HAL module driver
00171   * @{
00172   */
00173
00174 #ifdef HAL_SAI_MODULE_ENABLED
00175
00176 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00177     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00178
00179 /* Private typedef -----------------------------------------------------------*/
00180 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
00181   * @{
00182   */
00183 typedef enum {
00184   SAI_MODE_DMA,
00185   SAI_MODE_IT
00186 }SAI_ModeTypedef;
00187 /**
00188   * @}
00189   */
00190 /* Private define ------------------------------------------------------------*/
00191 /** @defgroup SAI_Private_Constants  SAI Private Constants
00192   * @{
00193   */
00194 #define SAI_FIFO_SIZE       8U
00195 #define SAI_DEFAULT_TIMEOUT 4U
00196 #define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
00197 /**
00198   * @}
00199   */
00200
00201 /* SAI registers Masks */
00202 #define CR1_CLEAR_MASK            ((uint32_t)0xFF04C010U)
00203 #define FRCR_CLEAR_MASK           ((uint32_t)0xFFF88000U)
00204 #define SLOTR_CLEAR_MASK          ((uint32_t)0x0000F020U)
00205
00206 #define SAI_TIMEOUT_VALUE         10U
00207 /* Private macro -------------------------------------------------------------*/
00208 /* Private variables ---------------------------------------------------------*/
00209 /* Private function prototypes -----------------------------------------------*/
00210 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
00211 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
00212 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00213 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00214
00215 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
00216 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
00217 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
00218 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
00219 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
00220 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
00221 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
00222
00223 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
00224 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00225 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
00226 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00227 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
00228
00229 /* Exported functions ---------------------------------------------------------*/
00230
00231 /** @defgroup SAI_Exported_Functions  SAI Exported Functions
00232   * @{
00233   */
00234
00235 /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
00236  *  @brief    Initialization and Configuration functions
00237  *
00238 @verbatim
00239  ===============================================================================
00240               ##### Initialization and de-initialization functions #####
00241  ===============================================================================
00242     [..]  This subsection provides a set of functions allowing to initialize and
00243           de-initialize the SAIx peripheral:
00244
00245       (+) User must implement HAL_SAI_MspInit() function in which he configures
00246           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00247
00248       (+) Call the function HAL_SAI_Init() to configure the selected device with
00249           the selected configuration:
00250         (++) Mode (Master/slave TX/RX)
00251         (++) Protocol
00252         (++) Data Size
00253         (++) MCLK Output
00254         (++) Audio frequency
00255         (++) FIFO Threshold
00256         (++) Frame Config
00257         (++) Slot Config
00258
00259       (+) Call the function HAL_SAI_DeInit() to restore the default configuration
00260           of the selected SAI peripheral.
00261
00262 @endverbatim
00263   * @{
00264   */
00265
00266 /**
00267   * @brief  Initializes the structure FrameInit, SlotInit and the low part of
00268   *         Init according to the specified parameters and call the function
00269   *         HAL_SAI_Init to initialize the SAI block.
00270   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
00271   *               the configuration information for SAI module.
00272   * @param  protocol : one of the supported protocol @ref SAI_Protocol
00273   * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
00274   *                the configuration information for SAI module.
00275   * @param  nbslot   : Number of slot.
00276   * @retval HAL status
00277   */
00278 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
00279 {
00280   HAL_StatusTypeDef status = HAL_OK;
00281
00282   /* Check the parameters */
00283   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
00284   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
00285
00286   switch(protocol)
00287   {
00288   case SAI_I2S_STANDARD :
00289   case SAI_I2S_MSBJUSTIFIED :
00290   case SAI_I2S_LSBJUSTIFIED :
00291     status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
00292     break;
00293   case SAI_PCM_LONG :
00294   case SAI_PCM_SHORT :
00295     status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
00296     break;
00297   default :
00298     status = HAL_ERROR;
00299     break;
00300   }
00301
00302   if(status == HAL_OK)
00303   {
00304     status = HAL_SAI_Init(hsai);
00305   }
00306
00307   return status;
00308 }
00309
00310 /**
00311   * @brief  Initializes the SAI according to the specified parameters
00312   *         in the SAI_InitTypeDef and create the associated handle.
00313   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00314   *                the configuration information for SAI module.
00315   * @retval HAL status
00316   */
00317 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
00318 {
00319   uint32_t tmpclock = 0U;
00320
00321   /* This variable used to store the SAI_CK_x (value in Hz) */
00322   uint32_t freq = 0U;
00323
00324   /* This variable is used to compute CKSTR bits of SAI CR1 according to
00325      ClockStrobing and AudioMode fields */
00326   uint32_t ckstr_bits = 0U;
00327
00328   uint32_t syncen_bits = 0U;
00329
00330   /* Check the SAI handle allocation */
00331   if(hsai == NULL)
00332   {
00333     return HAL_ERROR;
00334   }
00335
00336   /* Check the SAI Block parameters */
00337   assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
00338   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
00339   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
00340   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
00341   assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
00342   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
00343   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
00344   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
00345   assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
00346   assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
00347   assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
00348   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
00349   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
00350   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
00351
00352   /* Check the SAI Block Frame parameters */
00353   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
00354   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
00355   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
00356   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
00357   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
00358
00359   /* Check the SAI Block Slot parameters */
00360   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
00361   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
00362   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
00363   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
00364
00365   if(hsai->State == HAL_SAI_STATE_RESET)
00366   {
00367     /* Allocate lock resource and initialize it */
00368     hsai->Lock = HAL_UNLOCKED;
00369
00370     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00371     HAL_SAI_MspInit(hsai);
00372   }
00373
00374   hsai->State = HAL_SAI_STATE_BUSY;
00375
00376   /* Disable the selected SAI peripheral */
00377   SAI_Disable(hsai);
00378
00379   /* SAI Block Synchro Configuration -----------------------------------------*/
00380   SAI_BlockSynchroConfig(hsai);
00381
00382   /* Configure Master Clock using the following formula :
00383      MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
00384      FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
00385      MCKDIV[3:0] = SAI_CK_x / FS * 512 */
00386   if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
00387   {
00388   /* Get SAI clock source based on Source clock selection from RCC */
00389   freq = SAI_GetInputClock(hsai);
00390
00391     /* (saiclocksource x 10) to keep Significant digits */
00392     tmpclock = (((freq * 10U) / ((hsai->Init.AudioFrequency) * 512U)));
00393
00394     hsai->Init.Mckdiv = tmpclock / 10U;
00395
00396         /* Round result to the nearest integer */
00397     if((tmpclock % 10U) > 8U)
00398     {
00399       hsai->Init.Mckdiv+= 1U;
00400     }
00401   }
00402
00403   /* Compute CKSTR bits of SAI CR1 according to ClockStrobing and AudioMode */
00404   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
00405   {
00406     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U: SAI_xCR1_CKSTR;
00407   }
00408   else
00409   {
00410     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR: 0U;
00411   }
00412
00413   /* SAI Block Configuration -------------------------------------------------*/
00414   switch(hsai->Init.Synchro)
00415   {
00416   case SAI_ASYNCHRONOUS :
00417     {
00418       syncen_bits = 0U;
00419     }
00420     break;
00421   case SAI_SYNCHRONOUS :
00422     {
00423       syncen_bits = SAI_xCR1_SYNCEN_0;
00424     }
00425     break;
00426   case SAI_SYNCHRONOUS_EXT_SAI1 :
00427   case SAI_SYNCHRONOUS_EXT_SAI2 :
00428     {
00429       syncen_bits = SAI_xCR1_SYNCEN_1;
00430     }
00431     break;
00432   default:
00433     syncen_bits = 0U;
00434     break;
00435   }
00436   /* SAI CR1 Configuration */
00437   hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00438                            SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
00439                            SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00440                            SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
00441
00442   hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00443                           hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00444                           ckstr_bits | syncen_bits |                             \
00445                           hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00446                           hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20U));
00447
00448   /* SAI CR2 Configuration */
00449   hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
00450   hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
00451
00452   /* SAI Frame Configuration -----------------------------------------*/
00453   hsai->Instance->FRCR &= ~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
00454                            SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF);
00455   hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U)  | \
00456                             hsai->FrameInit.FSOffset |          \
00457                             hsai->FrameInit.FSDefinition |      \
00458                             hsai->FrameInit.FSPolarity   |      \
00459                             ((hsai->FrameInit.ActiveFrameLength - 1U) << 8U));
00460
00461   /* SAI Block_x SLOT Configuration ------------------------------------------*/
00462   /* This register has no meaning in AC 97 and SPDIF audio protocol */
00463   hsai->Instance->SLOTR &= ~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
00464                              SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN );
00465
00466   hsai->Instance->SLOTR |=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize  | \
00467                            (hsai->SlotInit.SlotActive << 16U) | ((hsai->SlotInit.SlotNumber - 1U) <<  8U);
00468
00469   /* Initialize the error code */
00470   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00471
00472   /* Initialize the SAI state */
00473   hsai->State= HAL_SAI_STATE_READY;
00474
00475   /* Release Lock */
00476   __HAL_UNLOCK(hsai);
00477
00478   return HAL_OK;
00479 }
00480
00481 /**
00482   * @brief  DeInitializes the SAI peripheral.
00483   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00484   *                the configuration information for SAI module.
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
00488 {
00489   /* Check the SAI handle allocation */
00490   if(hsai == NULL)
00491   {
00492     return HAL_ERROR;
00493   }
00494
00495   hsai->State = HAL_SAI_STATE_BUSY;
00496
00497   /* Disabled All interrupt and clear all the flag */
00498   hsai->Instance->IMR = 0U;
00499   hsai->Instance->CLRFR = 0xFFFFFFFFU;
00500
00501   /* Disable the SAI */
00502   SAI_Disable(hsai);
00503
00504   /* Flush the fifo */
00505   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00506
00507   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00508   HAL_SAI_MspDeInit(hsai);
00509
00510   /* Initialize the error code */
00511   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00512
00513   /* Initialize the SAI state */
00514   hsai->State = HAL_SAI_STATE_RESET;
00515
00516   /* Release Lock */
00517   __HAL_UNLOCK(hsai);
00518
00519   return HAL_OK;
00520 }
00521
00522 /**
00523   * @brief SAI MSP Init.
00524   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00525   *                the configuration information for SAI module.
00526   * @retval None
00527   */
00528 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
00529 {
00530   /* Prevent unused argument(s) compilation warning */
00531   UNUSED(hsai);
00532
00533   /* NOTE : This function should not be modified, when the callback is needed,
00534             the HAL_SAI_MspInit could be implemented in the user file
00535    */
00536 }
00537
00538 /**
00539   * @brief SAI MSP DeInit.
00540   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00541   *                the configuration information for SAI module.
00542   * @retval None
00543   */
00544 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
00545 {
00546   /* Prevent unused argument(s) compilation warning */
00547   UNUSED(hsai);
00548
00549   /* NOTE : This function should not be modified, when the callback is needed,
00550             the HAL_SAI_MspDeInit could be implemented in the user file
00551    */
00552 }
00553
00554 /**
00555   * @}
00556   */
00557
00558 /** @defgroup SAI_Exported_Functions_Group2 IO operation functions
00559  *  @brief   Data transfers functions
00560  *
00561 @verbatim
00562   ==============================================================================
00563                       ##### IO operation functions #####
00564   ==============================================================================
00565     [..]
00566     This subsection provides a set of functions allowing to manage the SAI data
00567     transfers.
00568
00569     (+) There are two modes of transfer:
00570        (++) Blocking mode : The communication is performed in the polling mode.
00571             The status of all data processing is returned by the same function
00572             after finishing transfer.
00573        (++) No-Blocking mode : The communication is performed using Interrupts
00574             or DMA. These functions return the status of the transfer startup.
00575             The end of the data processing will be indicated through the
00576             dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
00577             using DMA mode.
00578
00579     (+) Blocking mode functions are :
00580         (++) HAL_SAI_Transmit()
00581         (++) HAL_SAI_Receive()
00582         (++) HAL_SAI_TransmitReceive()
00583
00584     (+) Non Blocking mode functions with Interrupt are :
00585         (++) HAL_SAI_Transmit_IT()
00586         (++) HAL_SAI_Receive_IT()
00587         (++) HAL_SAI_TransmitReceive_IT()
00588
00589     (+) Non Blocking mode functions with DMA are :
00590         (++) HAL_SAI_Transmit_DMA()
00591         (++) HAL_SAI_Receive_DMA()
00592         (++) HAL_SAI_TransmitReceive_DMA()
00593
00594     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00595         (++) HAL_SAI_TxCpltCallback()
00596         (++) HAL_SAI_RxCpltCallback()
00597         (++) HAL_SAI_ErrorCallback()
00598
00599 @endverbatim
00600   * @{
00601   */
00602
00603 /**
00604   * @brief  Transmits an amount of data in blocking mode.
00605   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00606   *                the configuration information for SAI module.
00607   * @param  pData: Pointer to data buffer
00608   * @param  Size: Amount of data to be sent
00609   * @param  Timeout: Timeout duration
00610   * @retval HAL status
00611   */
00612 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
00613 {
00614   uint32_t tickstart = HAL_GetTick();
00615
00616   if((pData == NULL ) || (Size == 0U))
00617   {
00618     return  HAL_ERROR;
00619   }
00620
00621   if(hsai->State == HAL_SAI_STATE_READY)
00622   {
00623     /* Process Locked */
00624     __HAL_LOCK(hsai);
00625
00626     hsai->XferSize = Size;
00627     hsai->XferCount = Size;
00628     hsai->pBuffPtr = pData;
00629     hsai->State = HAL_SAI_STATE_BUSY_TX;
00630     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00631
00632     /* Check if the SAI is already enabled */
00633     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00634     {
00635       /* fill the fifo with data before to enabled the SAI */
00636       SAI_FillFifo(hsai);
00637       /* Enable SAI peripheral */
00638       __HAL_SAI_ENABLE(hsai);
00639     }
00640
00641     while(hsai->XferCount > 0U)
00642     {
00643       /* Write data if the FIFO is not full */
00644       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
00645       {
00646         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00647         {
00648           hsai->Instance->DR = (*hsai->pBuffPtr++);
00649         }
00650         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00651         {
00652           hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
00653           hsai->pBuffPtr+= 2U;
00654         }
00655         else
00656         {
00657           hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
00658           hsai->pBuffPtr+= 4U;
00659         }
00660         hsai->XferCount--;
00661       }
00662       else
00663       {
00664         /* Check for the Timeout */
00665         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)))
00666         {
00667           /* Update error code */
00668           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00669           /* Change the SAI state */
00670           hsai->State = HAL_SAI_STATE_TIMEOUT;
00671
00672           return HAL_TIMEOUT;
00673         }
00674       }
00675     }
00676
00677     hsai->State = HAL_SAI_STATE_READY;
00678
00679     /* Process Unlocked */
00680     __HAL_UNLOCK(hsai);
00681
00682     return HAL_OK;
00683   }
00684   else
00685   {
00686     return HAL_BUSY;
00687   }
00688 }
00689
00690 /**
00691   * @brief  Receives an amount of data in blocking mode.
00692   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00693   *                the configuration information for SAI module.
00694   * @param  pData: Pointer to data buffer
00695   * @param  Size: Amount of data to be received
00696   * @param  Timeout: Timeout duration
00697   * @retval HAL status
00698   */
00699 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00700 {
00701   uint32_t tickstart = HAL_GetTick();
00702
00703   if((pData == NULL ) || (Size == 0U))
00704   {
00705     return  HAL_ERROR;
00706   }
00707
00708   if(hsai->State == HAL_SAI_STATE_READY)
00709   {
00710     /* Process Locked */
00711     __HAL_LOCK(hsai);
00712
00713     hsai->pBuffPtr = pData;
00714     hsai->XferSize = Size;
00715     hsai->XferCount = Size;
00716     hsai->State = HAL_SAI_STATE_BUSY_RX;
00717     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00718
00719     /* Check if the SAI is already enabled */
00720     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00721     {
00722       /* Enable SAI peripheral */
00723       __HAL_SAI_ENABLE(hsai);
00724     }
00725
00726     /* Receive data */
00727     while(hsai->XferCount > 0U)
00728     {
00729       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
00730       {
00731         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00732         {
00733           (*hsai->pBuffPtr++) = hsai->Instance->DR;
00734         }
00735         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00736         {
00737           *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00738           hsai->pBuffPtr+= 2U;
00739         }
00740         else
00741         {
00742           *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00743           hsai->pBuffPtr+= 4U;
00744         }
00745         hsai->XferCount--;
00746       }
00747       else
00748       {
00749         /* Check for the Timeout */
00750         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)))
00751         {
00752           /* Update error code */
00753           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00754           /* Change the SAI state */
00755           hsai->State = HAL_SAI_STATE_TIMEOUT;
00756
00757           return HAL_TIMEOUT;
00758         }
00759       }
00760     }
00761
00762     hsai->State = HAL_SAI_STATE_READY;
00763
00764     /* Process Unlocked */
00765     __HAL_UNLOCK(hsai);
00766
00767     return HAL_OK;
00768   }
00769   else
00770   {
00771     return HAL_BUSY;
00772   }
00773 }
00774
00775 /**
00776   * @brief  Transmits an amount of data in no-blocking mode with Interrupt.
00777   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00778   *                the configuration information for SAI module.
00779   * @param  pData: Pointer to data buffer
00780   * @param  Size: Amount of data to be sent
00781   * @retval HAL status
00782   */
00783 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
00784 {
00785   if((pData == NULL) || (Size == 0U))
00786   {
00787     return  HAL_ERROR;
00788   }
00789
00790   if(hsai->State == HAL_SAI_STATE_READY)
00791   {
00792     /* Process Locked */
00793     __HAL_LOCK(hsai);
00794
00795     hsai->pBuffPtr = pData;
00796     hsai->XferSize = Size;
00797     hsai->XferCount = Size;
00798     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00799     hsai->State = HAL_SAI_STATE_BUSY_TX;
00800
00801     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00802     {
00803       hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
00804     }
00805     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00806     {
00807       hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
00808     }
00809     else
00810     {
00811       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
00812     }
00813
00814     /* Fill the fifo before starting the communication */
00815     SAI_FillFifo(hsai);
00816
00817     /* Enable FRQ and OVRUDR interrupts */
00818     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
00819
00820     /* Check if the SAI is already enabled */
00821     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00822     {
00823       /* Enable SAI peripheral */
00824       __HAL_SAI_ENABLE(hsai);
00825     }
00826     /* Process Unlocked */
00827     __HAL_UNLOCK(hsai);
00828
00829     return HAL_OK;
00830   }
00831   else
00832   {
00833     return HAL_BUSY;
00834   }
00835 }
00836
00837 /**
00838   * @brief  Receives an amount of data in no-blocking mode with Interrupt.
00839   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00840   *                the configuration information for SAI module.
00841   * @param  pData: Pointer to data buffer
00842   * @param  Size: Amount of data to be received
00843   * @retval HAL status
00844   */
00845 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
00846 {
00847   if((pData == NULL) || (Size == 0U))
00848   {
00849     return  HAL_ERROR;
00850   }
00851
00852   if(hsai->State == HAL_SAI_STATE_READY)
00853   {
00854     /* Process Locked */
00855     __HAL_LOCK(hsai);
00856
00857     hsai->pBuffPtr = pData;
00858     hsai->XferSize = Size;
00859     hsai->XferCount = Size;
00860     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00861     hsai->State = HAL_SAI_STATE_BUSY_RX;
00862
00863     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00864     {
00865       hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
00866     }
00867     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00868     {
00869       hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
00870     }
00871     else
00872     {
00873       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
00874     }
00875
00876     /* Enable TXE and OVRUDR interrupts */
00877     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
00878
00879     /* Check if the SAI is already enabled */
00880     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00881     {
00882       /* Enable SAI peripheral */
00883       __HAL_SAI_ENABLE(hsai);
00884     }
00885
00886     /* Process Unlocked */
00887     __HAL_UNLOCK(hsai);
00888
00889     return HAL_OK;
00890   }
00891   else
00892   {
00893     return HAL_BUSY;
00894   }
00895 }
00896
00897 /**
00898   * @brief Pauses the audio stream playing from the Media.
00899   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00900   *                the configuration information for SAI module.
00901   * @retval HAL status
00902   */
00903 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
00904 {
00905   /* Process Locked */
00906   __HAL_LOCK(hsai);
00907
00908   /* Pause the audio file playing by disabling the SAI DMA requests */
00909   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
00910
00911   /* Process Unlocked */
00912   __HAL_UNLOCK(hsai);
00913
00914   return HAL_OK;
00915 }
00916
00917 /**
00918   * @brief Resumes the audio stream playing from the Media.
00919   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00920   *                the configuration information for SAI module.
00921   * @retval HAL status
00922   */
00923 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
00924 {
00925   /* Process Locked */
00926   __HAL_LOCK(hsai);
00927
00928   /* Enable the SAI DMA requests */
00929   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
00930
00931   /* If the SAI peripheral is still not enabled, enable it */
00932   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00933   {
00934     /* Enable SAI peripheral */
00935     __HAL_SAI_ENABLE(hsai);
00936   }
00937
00938   /* Process Unlocked */
00939   __HAL_UNLOCK(hsai);
00940
00941   return HAL_OK;
00942 }
00943
00944 /**
00945   * @brief Stops the audio stream playing from the Media.
00946   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
00947   *                the configuration information for SAI module.
00948   * @retval HAL status
00949   */
00950 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
00951 {
00952   /* Process Locked */
00953   __HAL_LOCK(hsai);
00954
00955   /* Disable the SAI DMA request */
00956   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
00957
00958   /* Abort the SAI DMA Tx Stream */
00959   if(hsai->hdmatx != NULL)
00960   {
00961     if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
00962     {
00963       return HAL_ERROR;
00964     }
00965   }
00966   /* Abort the SAI DMA Rx Stream */
00967   if(hsai->hdmarx != NULL)
00968   {
00969     if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
00970     {
00971       return HAL_ERROR;
00972     }
00973   }
00974
00975   /* Disable SAI peripheral */
00976   SAI_Disable(hsai);
00977
00978   hsai->State = HAL_SAI_STATE_READY;
00979
00980   /* Process Unlocked */
00981   __HAL_UNLOCK(hsai);
00982
00983   return HAL_OK;
00984 }
00985
00986 /**
00987   * @brief Abort the current transfer and disbaled the SAI.
00988   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
00989   *                the configuration information for SAI module.
00990   * @retval HAL status
00991   */
00992 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
00993 {
00994   /* Disable the SAI DMA request */
00995   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
00996
00997   /* Abort the SAI DMA Tx Stream */
00998   if(hsai->hdmatx != NULL)
00999   {
01000     if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
01001     {
01002       return HAL_ERROR;
01003     }
01004   }
01005   /* Abort the SAI DMA Rx Stream */
01006   if(hsai->hdmarx != NULL)
01007   {
01008     if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
01009     {
01010       return HAL_ERROR;
01011     }
01012   }
01013
01014   /* Disabled All interrupt and clear all the flag */
01015   hsai->Instance->IMR = 0U;
01016   hsai->Instance->CLRFR = 0xFFFFFFFFU;
01017
01018   /* Disable SAI peripheral */
01019   SAI_Disable(hsai);
01020
01021   /* Flush the fifo */
01022   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01023
01024   hsai->State = HAL_SAI_STATE_READY;
01025
01026   /* Process Unlocked */
01027   __HAL_UNLOCK(hsai);
01028
01029   return HAL_OK;
01030 }
01031
01032 /**
01033   * @brief  Transmits an amount of data in no-blocking mode with DMA.
01034   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01035   *                the configuration information for SAI module.
01036   * @param  pData: Pointer to data buffer
01037   * @param  Size: Amount of data to be sent
01038   * @retval HAL status
01039   */
01040 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01041 {
01042   uint32_t *tmp;
01043
01044   if((pData == NULL) || (Size == 0U))
01045   {
01046     return  HAL_ERROR;
01047   }
01048
01049   if(hsai->State == HAL_SAI_STATE_READY)
01050   {
01051     /* Process Locked */
01052     __HAL_LOCK(hsai);
01053
01054     hsai->pBuffPtr = pData;
01055     hsai->XferSize = Size;
01056     hsai->XferCount = Size;
01057     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01058     hsai->State = HAL_SAI_STATE_BUSY_TX;
01059
01060     /* Set the SAI Tx DMA Half transfer complete callback */
01061     hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
01062
01063     /* Set the SAI TxDMA transfer complete callback */
01064     hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
01065
01066     /* Set the DMA error callback */
01067     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
01068
01069     /* Enable the Tx DMA Stream */
01070     tmp = (uint32_t*)&pData;
01071     HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize);
01072
01073     /* Check if the SAI is already enabled */
01074     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01075     {
01076       /* Enable SAI peripheral */
01077       __HAL_SAI_ENABLE(hsai);
01078     }
01079
01080     /* Enable the interrupts for error handling */
01081     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01082
01083     /* Enable SAI Tx DMA Request */
01084     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01085
01086     /* Process Unlocked */
01087     __HAL_UNLOCK(hsai);
01088
01089     return HAL_OK;
01090   }
01091   else
01092   {
01093     return HAL_BUSY;
01094   }
01095 }
01096
01097 /**
01098   * @brief  Receives an amount of data in no-blocking mode with DMA.
01099   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01100   *                the configuration information for SAI module.
01101   * @param  pData: Pointer to data buffer
01102   * @param  Size: Amount of data to be received
01103   * @retval HAL status
01104   */
01105 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01106 {
01107   uint32_t *tmp;
01108
01109   if((pData == NULL) || (Size == 0U))
01110   {
01111     return  HAL_ERROR;
01112   }
01113
01114   if(hsai->State == HAL_SAI_STATE_READY)
01115   {
01116     /* Process Locked */
01117     __HAL_LOCK(hsai);
01118
01119     hsai->pBuffPtr = pData;
01120     hsai->XferSize = Size;
01121     hsai->XferCount = Size;
01122     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01123     hsai->State = HAL_SAI_STATE_BUSY_RX;
01124
01125     /* Set the SAI Rx DMA Half transfer complete callback */
01126     hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
01127
01128     /* Set the SAI Rx DMA transfer complete callback */
01129     hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
01130
01131     /* Set the DMA error callback */
01132     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
01133
01134     /* Enable the Rx DMA Stream */
01135     tmp = (uint32_t*)&pData;
01136     HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize);
01137
01138     /* Check if the SAI is already enabled */
01139     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01140     {
01141       /* Enable SAI peripheral */
01142       __HAL_SAI_ENABLE(hsai);
01143     }
01144
01145     /* Enable the interrupts for error handling */
01146     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01147
01148     /* Enable SAI Rx DMA Request */
01149     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01150
01151     /* Process Unlocked */
01152     __HAL_UNLOCK(hsai);
01153
01154     return HAL_OK;
01155   }
01156   else
01157   {
01158     return HAL_BUSY;
01159   }
01160 }
01161
01162 /**
01163   * @brief  Enable the tx mute mode.
01164   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01165   *                the configuration information for SAI module.
01166   * @param  val :  value sent during the mute @ref SAI_Block_Mute_Value
01167   * @retval HAL status
01168   */
01169 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
01170 {
01171   assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
01172
01173   if(hsai->State != HAL_SAI_STATE_RESET)
01174   {
01175     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01176     SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
01177     return HAL_OK;
01178   }
01179   return HAL_ERROR;
01180 }
01181
01182 /**
01183   * @brief  Disable the tx mute mode.
01184   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01185   *                the configuration information for SAI module.
01186   * @retval HAL status
01187   */
01188 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
01189 {
01190   if(hsai->State != HAL_SAI_STATE_RESET)
01191   {
01192     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01193     return HAL_OK;
01194   }
01195   return HAL_ERROR;
01196 }
01197
01198 /**
01199   * @brief  Enable the rx mute detection.
01200   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01201   *                the configuration information for SAI module.
01202   * @param  callback : function called when the mute is detected
01203   * @param  counter : number a data before mute detection max 63.
01204   * @retval HAL status
01205   */
01206 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
01207 {
01208   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
01209
01210   if(hsai->State != HAL_SAI_STATE_RESET)
01211   {
01212     /* set the mute counter */
01213     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
01214     SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
01215     hsai->mutecallback = callback;
01216     /* enable the IT interrupt */
01217     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
01218     return HAL_OK;
01219   }
01220   return HAL_ERROR;
01221 }
01222
01223 /**
01224   * @brief  Disable the rx mute detection.
01225   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01226   *                the configuration information for SAI module.
01227   * @retval HAL status
01228   */
01229 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
01230 {
01231   if(hsai->State != HAL_SAI_STATE_RESET)
01232   {
01233     /* set the mutecallback to NULL */
01234     hsai->mutecallback = (SAIcallback)NULL;
01235     /* enable the IT interrupt */
01236     __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
01237     return HAL_OK;
01238   }
01239   return HAL_ERROR;
01240 }
01241
01242 /**
01243   * @brief  This function handles SAI interrupt request.
01244   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01245   *                the configuration information for SAI module.
01246   * @retval HAL status
01247   */
01248 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
01249 {
01250   if(hsai->State != HAL_SAI_STATE_RESET)
01251   {
01252     uint32_t tmpFlag = hsai->Instance->SR;
01253     uint32_t tmpItSource = hsai->Instance->IMR;
01254
01255     if(((tmpFlag & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((tmpItSource & SAI_IT_FREQ) == SAI_IT_FREQ))
01256     {
01257       hsai->InterruptServiceRoutine(hsai);
01258     }
01259
01260     /* check the flag only if one of them is set */
01261     if(tmpFlag != 0x00000000U)
01262     {
01263       /* SAI Overrun error interrupt occurred --------------------------------*/
01264       if(((tmpFlag & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((tmpItSource & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
01265       {
01266         /* Clear the SAI Overrun flag */
01267         __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01268         /* Change the SAI error code */
01269         hsai->ErrorCode = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
01270         /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01271         HAL_SAI_ErrorCallback(hsai);
01272       }
01273
01274       /* SAI mutedet interrupt occurred --------------------------------------*/
01275       if(((tmpFlag & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((tmpItSource & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
01276       {
01277         /* Clear the SAI mutedet flag */
01278         __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
01279         /* call the call back function */
01280         if(hsai->mutecallback != (SAIcallback)NULL)
01281         {
01282           /* inform the user that an RX mute event has been detected */
01283           hsai->mutecallback();
01284         }
01285       }
01286
01287       /* SAI AFSDET interrupt occurred ---------------------------------------*/
01288       if(((tmpFlag & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((tmpItSource & SAI_IT_AFSDET) == SAI_IT_AFSDET))
01289       {
01290         /* Change the SAI error code */
01291         hsai->ErrorCode = HAL_SAI_ERROR_AFSDET;
01292         HAL_SAI_Abort(hsai);
01293         HAL_SAI_ErrorCallback(hsai);
01294       }
01295
01296       /* SAI LFSDET interrupt occurred ---------------------------------------*/
01297       if(((tmpFlag & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((tmpItSource & SAI_IT_LFSDET) == SAI_IT_LFSDET))
01298       {
01299         /* Change the SAI error code */
01300         hsai->ErrorCode = HAL_SAI_ERROR_LFSDET;
01301         HAL_SAI_Abort(hsai);
01302         HAL_SAI_ErrorCallback(hsai);
01303       }
01304
01305       /* SAI WCKCFG interrupt occurred ---------------------------------------*/
01306       if(((tmpFlag & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((tmpItSource & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
01307       {
01308         /* Change the SAI error code */
01309         hsai->ErrorCode = HAL_SAI_ERROR_WCKCFG;
01310         HAL_SAI_Abort(hsai);
01311         HAL_SAI_ErrorCallback(hsai);
01312       }
01313       /* SAI CNRDY interrupt occurred ----------------------------------------*/
01314       if(((tmpFlag & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((tmpItSource & SAI_IT_CNRDY) == SAI_IT_CNRDY))
01315       {
01316         /* Clear the SAI CNRDY flag */
01317         __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
01318         /* Change the SAI error code */
01319         hsai->ErrorCode = HAL_SAI_ERROR_CNREADY;
01320         /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01321         HAL_SAI_ErrorCallback(hsai);
01322       }
01323     }
01324   }
01325 }
01326
01327 /**
01328   * @brief Tx Transfer completed callbacks.
01329   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01330   *                the configuration information for SAI module.
01331   * @retval None
01332   */
01333  __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
01334 {
01335   /* Prevent unused argument(s) compilation warning */
01336   UNUSED(hsai);
01337
01338   /* NOTE : This function Should not be modified, when the callback is needed,
01339             the HAL_SAI_TxCpltCallback could be implemented in the user file
01340    */
01341 }
01342
01343 /**
01344   * @brief Tx Transfer Half completed callbacks
01345   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01346   *                the configuration information for SAI module.
01347   * @retval None
01348   */
01349  __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01350 {
01351   /* Prevent unused argument(s) compilation warning */
01352   UNUSED(hsai);
01353
01354   /* NOTE : This function Should not be modified, when the callback is needed,
01355             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
01356    */
01357 }
01358
01359 /**
01360   * @brief Rx Transfer completed callbacks.
01361   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01362   *                the configuration information for SAI module.
01363   * @retval None
01364   */
01365 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
01366 {
01367   /* Prevent unused argument(s) compilation warning */
01368   UNUSED(hsai);
01369
01370   /* NOTE : This function Should not be modified, when the callback is needed,
01371             the HAL_SAI_RxCpltCallback could be implemented in the user file
01372    */
01373 }
01374
01375 /**
01376   * @brief Rx Transfer half completed callbacks
01377   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01378   *                the configuration information for SAI module.
01379   * @retval None
01380   */
01381 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01382 {
01383   /* Prevent unused argument(s) compilation warning */
01384   UNUSED(hsai);
01385
01386   /* NOTE : This function Should not be modified, when the callback is needed,
01387             the HAL_SAI_RxCpltCallback could be implemented in the user file
01388    */
01389 }
01390
01391 /**
01392   * @brief SAI error callbacks.
01393   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01394   *                the configuration information for SAI module.
01395   * @retval None
01396   */
01397 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
01398 {
01399   /* Prevent unused argument(s) compilation warning */
01400   UNUSED(hsai);
01401
01402   /* NOTE : This function Should not be modified, when the callback is needed,
01403             the HAL_SAI_ErrorCallback could be implemented in the user file
01404    */
01405 }
01406
01407 /**
01408   * @}
01409   */
01410
01411 /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
01412   *  @brief   Peripheral State functions
01413   *
01414 @verbatim
01415  ===============================================================================
01416                 ##### Peripheral State and Errors functions #####
01417  ===============================================================================
01418     [..]
01419     This subsection permits to get in run-time the status of the peripheral
01420     and the data flow.
01421
01422 @endverbatim
01423   * @{
01424   */
01425
01426 /**
01427   * @brief  Returns the SAI state.
01428   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01429   *                the configuration information for SAI module.
01430   * @retval HAL state
01431   */
01432 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
01433 {
01434   return hsai->State;
01435 }
01436
01437 /**
01438   * @brief  Return the SAI error code
01439   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01440   *              the configuration information for the specified SAI Block.
01441   * @retval SAI Error Code
01442   */
01443 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
01444 {
01445   return hsai->ErrorCode;
01446 }
01447 /**
01448   * @}
01449   */
01450
01451 /**
01452   * @brief  Initializes the SAI I2S protocol according to the specified parameters
01453   *         in the SAI_InitTypeDef and create the associated handle.
01454   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01455   *                the configuration information for SAI module.
01456   * @param  protocol : one of the supported protocol
01457   * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
01458   *                the configuration information for SAI module.
01459   * @param  nbslot : number of slot minimum value is 2 and max is 16.
01460   *                    the value must be a multiple of 2.
01461   * @retval HAL status
01462   */
01463 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01464 {
01465   /* Check the parameters */
01466   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
01467   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
01468
01469   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01470   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01471   /* Compute ClockStrobing according AudioMode */
01472   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01473   { /* Transmit */
01474     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01475   }
01476   else
01477   { /* Receive */
01478     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01479   }
01480   hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
01481   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01482   hsai->SlotInit.FirstBitOffset  = 0U;
01483   hsai->SlotInit.SlotNumber      = nbslot;
01484
01485   /* in IS2 the number of slot must be even */
01486   if((nbslot & 0x1U) != 0U)
01487   {
01488     return HAL_ERROR;
01489   }
01490
01491   switch(protocol)
01492   {
01493   case SAI_I2S_STANDARD :
01494     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
01495     hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
01496     break;
01497   case SAI_I2S_MSBJUSTIFIED :
01498   case SAI_I2S_LSBJUSTIFIED :
01499     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
01500     hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
01501     break;
01502   default :
01503     return HAL_ERROR;
01504   }
01505
01506   /* Frame definition */
01507   switch(datasize)
01508   {
01509   case SAI_PROTOCOL_DATASIZE_16BIT:
01510     hsai->Init.DataSize = SAI_DATASIZE_16;
01511     hsai->FrameInit.FrameLength = 32U*(nbslot/2U);
01512     hsai->FrameInit.ActiveFrameLength = 16U*(nbslot/2U);
01513     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01514     break;
01515   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01516     hsai->Init.DataSize = SAI_DATASIZE_16;
01517     hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
01518     hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
01519     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01520     break;
01521   case SAI_PROTOCOL_DATASIZE_24BIT:
01522     hsai->Init.DataSize = SAI_DATASIZE_24;
01523     hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
01524     hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
01525     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01526     break;
01527   case SAI_PROTOCOL_DATASIZE_32BIT:
01528     hsai->Init.DataSize = SAI_DATASIZE_32;
01529     hsai->FrameInit.FrameLength = 64U*(nbslot/2U);
01530     hsai->FrameInit.ActiveFrameLength = 32U*(nbslot/2U);
01531     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01532     break;
01533   default :
01534     return HAL_ERROR;
01535   }
01536   if(protocol == SAI_I2S_LSBJUSTIFIED)
01537   {
01538     if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
01539     {
01540       hsai->SlotInit.FirstBitOffset = 16U;
01541     }
01542     if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
01543     {
01544       hsai->SlotInit.FirstBitOffset = 8U;
01545     }
01546   }
01547   return HAL_OK;
01548 }
01549
01550 /**
01551   * @brief  Initializes the SAI PCM protocol according to the specified parameters
01552   *         in the SAI_InitTypeDef and create the associated handle.
01553   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01554   *                the configuration information for SAI module.
01555   * @param  protocol : one of the supported protocol
01556   * @param  datasize : one of the supported datasize @ref SAI_Protocol_DataSize
01557   * @param  nbslot : number of slot minimum value is 1 and the max is 16.
01558   * @retval HAL status
01559   */
01560 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01561 {
01562   /* Check the parameters */
01563   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
01564   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
01565
01566   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01567   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01568   /* Compute ClockStrobing according AudioMode */
01569   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01570   { /* Transmit */
01571     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01572   }
01573   else
01574   { /* Receive */
01575     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01576   }
01577   hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
01578   hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
01579   hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
01580   hsai->SlotInit.FirstBitOffset  = 0U;
01581   hsai->SlotInit.SlotNumber      = nbslot;
01582   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01583
01584   switch(protocol)
01585   {
01586   case SAI_PCM_SHORT :
01587     hsai->FrameInit.ActiveFrameLength = 1U;
01588     break;
01589   case SAI_PCM_LONG :
01590     hsai->FrameInit.ActiveFrameLength = 13U;
01591     break;
01592   default :
01593     return HAL_ERROR;
01594   }
01595
01596   switch(datasize)
01597   {
01598   case SAI_PROTOCOL_DATASIZE_16BIT:
01599     hsai->Init.DataSize = SAI_DATASIZE_16;
01600     hsai->FrameInit.FrameLength = 16U * nbslot;
01601     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01602     break;
01603   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01604     hsai->Init.DataSize = SAI_DATASIZE_16;
01605     hsai->FrameInit.FrameLength = 32U * nbslot;
01606     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01607     break;
01608   case SAI_PROTOCOL_DATASIZE_24BIT :
01609     hsai->Init.DataSize = SAI_DATASIZE_24;
01610     hsai->FrameInit.FrameLength = 32U * nbslot;
01611     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01612     break;
01613   case SAI_PROTOCOL_DATASIZE_32BIT:
01614     hsai->Init.DataSize = SAI_DATASIZE_32;
01615     hsai->FrameInit.FrameLength = 32U * nbslot;
01616     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01617     break;
01618   default :
01619     return HAL_ERROR;
01620   }
01621
01622   return HAL_OK;
01623 }
01624
01625 /**
01626   * @brief  Fill the fifo
01627   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01628   *                the configuration information for SAI module.
01629   * @retval None.
01630   */
01631 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
01632 {
01633   /* fill the fifo with data before to enabled the SAI */
01634   while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
01635   {
01636     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01637     {
01638       hsai->Instance->DR = (*hsai->pBuffPtr++);
01639     }
01640     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
01641     {
01642       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01643       hsai->pBuffPtr+= 2U;
01644     }
01645     else
01646     {
01647       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01648       hsai->pBuffPtr+= 4U;
01649     }
01650     hsai->XferCount--;
01651   }
01652 }
01653
01654 /**
01655   * @brief  return the interrupt flag to set according the SAI setup
01656   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01657   *                the configuration information for SAI module.
01658   * @param  mode : SAI_MODE_DMA or SAI_MODE_IT
01659   * @retval the list of the IT flag to enable
01660  */
01661 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
01662 {
01663   uint32_t tmpIT = SAI_IT_OVRUDR;
01664
01665   if(mode == SAI_MODE_IT)
01666   {
01667     tmpIT|= SAI_IT_FREQ;
01668   }
01669
01670   if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
01671     ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
01672   {
01673     tmpIT|= SAI_IT_CNRDY;
01674   }
01675
01676   if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01677   {
01678     tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
01679   }
01680   else
01681   {
01682     /* hsai has been configured in master mode */
01683     tmpIT|= SAI_IT_WCKCFG;
01684   }
01685   return tmpIT;
01686 }
01687
01688 /**
01689   * @brief  disable the SAI and wait the disabling
01690   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01691   *                the configuration information for SAI module.
01692   * @retval None.
01693   */
01694 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
01695 {
01696   uint32_t tickstart = HAL_GetTick();
01697   HAL_StatusTypeDef status = HAL_OK;
01698
01699   __HAL_SAI_DISABLE(hsai);
01700   while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)
01701   {
01702     /* Check for the Timeout */
01703     if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)
01704     {
01705       /* Update error code */
01706       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01707
01708       return HAL_TIMEOUT;
01709     }
01710   }
01711   return status;
01712 }
01713
01714 /**
01715   * @brief  Tx Handler for Transmit in Interrupt mode 8Bit transfer
01716   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01717   *                the configuration information for SAI module.
01718   * @retval None.
01719   */
01720 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
01721 {
01722   if(hsai->XferCount == 0U)
01723   {
01724     /* Handle the end of the transmission */
01725     /* Disable FREQ and OVRUDR interrupts */
01726     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01727     hsai->State = HAL_SAI_STATE_READY;
01728     HAL_SAI_TxCpltCallback(hsai);
01729   }
01730   else
01731   {
01732     /* Write data on DR register */
01733     hsai->Instance->DR = (*hsai->pBuffPtr++);
01734     hsai->XferCount--;
01735   }
01736 }
01737
01738 /**
01739   * @brief  Tx Handler for Transmit in Interrupt mode for 16Bit transfer
01740   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01741   *                the configuration information for SAI module.
01742   * @retval None.
01743   */
01744 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
01745 {
01746   if(hsai->XferCount == 0U)
01747   {
01748     /* Handle the end of the transmission */
01749     /* Disable FREQ and OVRUDR interrupts */
01750     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01751     hsai->State = HAL_SAI_STATE_READY;
01752     HAL_SAI_TxCpltCallback(hsai);
01753   }
01754   else
01755   {
01756     /* Write data on DR register */
01757     hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
01758     hsai->pBuffPtr+=2U;
01759     hsai->XferCount--;
01760   }
01761 }
01762
01763 /**
01764   * @brief  Tx Handler for Transmit in Interrupt mode for 32Bit transfer
01765   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01766   *                the configuration information for SAI module.
01767   * @retval None.
01768   */
01769 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
01770 {
01771   if(hsai->XferCount == 0U)
01772   {
01773     /* Handle the end of the transmission */
01774     /* Disable FREQ and OVRUDR interrupts */
01775     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01776     hsai->State = HAL_SAI_STATE_READY;
01777     HAL_SAI_TxCpltCallback(hsai);
01778   }
01779   else
01780   {
01781     /* Write data on DR register */
01782     hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
01783     hsai->pBuffPtr+=4U;
01784     hsai->XferCount--;
01785   }
01786 }
01787
01788 /**
01789   * @brief  Rx Handler for Receive in Interrupt mode 8Bit transfer
01790   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01791   *                the configuration information for SAI module.
01792   * @retval None.
01793   */
01794 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
01795 {
01796   /* Receive data */
01797   (*hsai->pBuffPtr++) = hsai->Instance->DR;
01798   hsai->XferCount--;
01799
01800   /* Check end of the transfer */
01801   if(hsai->XferCount == 0U)
01802   {
01803     /* Disable TXE and OVRUDR interrupts */
01804     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01805
01806     /* Clear the SAI Overrun flag */
01807     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01808
01809     hsai->State = HAL_SAI_STATE_READY;
01810     HAL_SAI_RxCpltCallback(hsai);
01811   }
01812 }
01813
01814 /**
01815   * @brief  Rx Handler for Receive in Interrupt mode for 16Bit transfer
01816   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01817   *                the configuration information for SAI module.
01818   * @retval None.
01819   */
01820 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
01821 {
01822   /* Receive data */
01823   *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
01824   hsai->pBuffPtr+=2U;
01825   hsai->XferCount--;
01826
01827   /* Check end of the transfer */
01828   if(hsai->XferCount == 0U)
01829   {
01830     /* Disable TXE and OVRUDR interrupts */
01831     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01832
01833     /* Clear the SAI Overrun flag */
01834     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01835
01836     hsai->State = HAL_SAI_STATE_READY;
01837     HAL_SAI_RxCpltCallback(hsai);
01838   }
01839 }
01840
01841 /**
01842   * @brief  Rx Handler for Receive in Interrupt mode for 32Bit transfer
01843   * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
01844   *                the configuration information for SAI module.
01845   * @retval None.
01846   */
01847 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
01848 {
01849   /* Receive data */
01850   *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
01851   hsai->pBuffPtr+=4U;
01852   hsai->XferCount--;
01853
01854   /* Check end of the transfer */
01855   if(hsai->XferCount == 0U)
01856   {
01857     /* Disable TXE and OVRUDR interrupts */
01858     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01859
01860     /* Clear the SAI Overrun flag */
01861     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01862
01863     hsai->State = HAL_SAI_STATE_READY;
01864     HAL_SAI_RxCpltCallback(hsai);
01865   }
01866 }
01867
01868 /**
01869   * @brief DMA SAI transmit process complete callback.
01870   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01871   *                the configuration information for the specified DMA module.
01872   * @retval None
01873   */
01874 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
01875 {
01876   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
01877
01878   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01879   {
01880     hsai->XferCount = 0U;
01881
01882     /* Disable SAI Tx DMA Request */
01883     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
01884
01885     /* Stop the interrupts error handling */
01886     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01887
01888     hsai->State= HAL_SAI_STATE_READY;
01889   }
01890   HAL_SAI_TxCpltCallback(hsai);
01891 }
01892
01893 /**
01894   * @brief DMA SAI transmit process half complete callback
01895   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01896   *                the configuration information for the specified DMA module.
01897   * @retval None
01898   */
01899 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01900 {
01901   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01902
01903   HAL_SAI_TxHalfCpltCallback(hsai);
01904 }
01905
01906 /**
01907   * @brief DMA SAI receive process complete callback.
01908   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01909   *                the configuration information for the specified DMA module.
01910   * @retval None
01911   */
01912 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
01913 {
01914   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01915   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01916   {
01917     /* Disable Rx DMA Request */
01918     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
01919     hsai->XferCount = 0U;
01920
01921     /* Stop the interrupts error handling */
01922     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01923
01924     hsai->State = HAL_SAI_STATE_READY;
01925   }
01926   HAL_SAI_RxCpltCallback(hsai);
01927 }
01928
01929 /**
01930   * @brief DMA SAI receive process half complete callback
01931   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01932   *                the configuration information for the specified DMA module.
01933   * @retval None
01934   */
01935 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01936 {
01937   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01938
01939   HAL_SAI_RxHalfCpltCallback(hsai);
01940 }
01941
01942 /**
01943   * @brief DMA SAI communication error callback.
01944   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01945   *                the configuration information for the specified DMA module.
01946   * @retval None
01947   */
01948 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
01949 {
01950   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01951
01952   /* Stop the DMA transfer */
01953   HAL_SAI_DMAStop(hsai);
01954
01955   /* Set the SAI state ready to be able to start again the process */
01956   hsai->State= HAL_SAI_STATE_READY;
01957   HAL_SAI_ErrorCallback(hsai);
01958
01959   hsai->XferCount = 0U;
01960 }
01961
01962 /**
01963   * @}
01964   */
01965
01966 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
01967 #endif /* HAL_SAI_MODULE_ENABLED */
01968 /**
01969   * @}
01970   */
01971
01972 /**
01973   * @}
01974   */
01975
01976 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai.h Source File

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stm32f4xx_hal_sai.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sai.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SAI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SAI_H
00040 #define __STM32F4xx_HAL_SAI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00053     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00054
00055 /** @addtogroup SAI
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup SAI_Exported_Types SAI Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  HAL State structures definition
00066   */
00067 typedef enum
00068 {
00069   HAL_SAI_STATE_RESET      = 0x00U,  /*!< SAI not yet initialized or disabled                */
00070   HAL_SAI_STATE_READY      = 0x01U,  /*!< SAI initialized and ready for use                  */
00071   HAL_SAI_STATE_BUSY       = 0x02U,  /*!< SAI internal process is ongoing                    */
00072   HAL_SAI_STATE_BUSY_TX    = 0x12U,  /*!< Data transmission process is ongoing               */
00073   HAL_SAI_STATE_BUSY_RX    = 0x22U,  /*!< Data reception process is ongoing                  */
00074   HAL_SAI_STATE_TIMEOUT    = 0x03U,  /*!< SAI timeout state                                  */
00075   HAL_SAI_STATE_ERROR      = 0x04U   /*!< SAI error state                                    */
00076 }HAL_SAI_StateTypeDef;
00077
00078 /**
00079   * @brief  SAI Callback prototype
00080   */
00081 typedef void (*SAIcallback)(void);
00082
00083 /**
00084   * @brief  SAI Init Structure definition
00085   */
00086 typedef struct
00087 {
00088   uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
00089                                      This parameter can be a value of @ref SAI_Block_Mode                      */
00090
00091   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
00092                                      This parameter can be a value of @ref SAI_Block_Synchronization           */
00093
00094   uint32_t SynchroExt;          /*!< Specifies SAI Block synchronization, this setup is common
00095                                      for BLOCKA and BLOCKB
00096                                      This parameter can be a value of @ref SAI_Block_SyncExt                   */
00097
00098   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
00099                                      This parameter can be a value of @ref SAI_Block_Output_Drive
00100                                      @note this value has to be set before enabling the audio block
00101                                      but after the audio block configuration.                                  */
00102
00103   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
00104                                      This parameter can be a value of @ref SAI_Block_NoDivider
00105                                      @note  If bit NODIV in the SAI_xCR1 register is cleared, the frame length
00106                                             should be aligned to a number equal to a power of 2, from 8 to 256.
00107                                             If bit NODIV in the SAI_xCR1 register is set, the frame length can
00108                                             take any of the values without constraint since the input clock of
00109                                             the audio block should be equal to the bit clock.
00110                                              There is no MCLK_x clock which can be output.                     */
00111
00112   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
00113                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold            */
00114
00115   uint32_t ClockSource;         /*!< Specifies the SAI Block x Clock source.
00116                                      This parameter is not used for STM32F446xx devices.                       */
00117
00118   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
00119                                      This parameter can be a value of @ref SAI_Audio_Frequency                 */
00120
00121   uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
00122                                      AudioFrequency the user choice
00123                                      This parameter must be a number between Min_Data = 0 and Max_Data = 15    */
00124
00125   uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
00126                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode                */
00127
00128   uint32_t CompandingMode;      /*!< Specifies the companding mode type.
00129                                      This parameter can be a value of @ref SAI_Block_Companding_Mode           */
00130
00131   uint32_t TriState;            /*!< Specifies the companding mode type.
00132                                      This parameter can be a value of @ref SAI_TRIState_Management             */
00133
00134   /* This part of the structure is automatically filled if your are using the high level intialisation
00135      function HAL_SAI_InitProtocol                                                                             */
00136
00137   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
00138                                  This parameter can be a value of @ref SAI_Block_Protocol                      */
00139
00140   uint32_t DataSize;        /*!< Specifies the SAI Block data size.
00141                                  This parameter can be a value of @ref SAI_Block_Data_Size                     */
00142
00143   uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
00144                                  This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission          */
00145
00146   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
00147                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing                */
00148 }SAI_InitTypeDef;
00149
00150 /**
00151   * @brief  SAI Block Frame Init structure definition
00152   */
00153
00154 typedef struct
00155 {
00156   uint32_t FrameLength;         /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
00157                                      This parameter must be a number between Min_Data = 8 and Max_Data = 256.
00158                                      @note  If master clock MCLK_x pin is declared as an output, the frame length
00159                                             should be aligned to a number equal to power of 2 in order to keep
00160                                             in an audio frame, an integer number of MCLK pulses by bit Clock. */
00161
00162   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
00163                                     This Parameter specifies the length in number of bit clock (SCK + 1)
00164                                     of the active level of FS signal in audio frame.
00165                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
00166
00167   uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
00168                                     This parameter can be a value of @ref SAI_Block_FS_Definition             */
00169
00170   uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
00171                                     This parameter can be a value of @ref SAI_Block_FS_Polarity               */
00172
00173   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
00174                                     This parameter can be a value of @ref SAI_Block_FS_Offset                 */
00175 }SAI_FrameInitTypeDef;
00176
00177 /**
00178   * @brief   SAI Block Slot Init Structure definition
00179   */
00180
00181 typedef struct
00182 {
00183   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
00184                                  This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
00185
00186   uint32_t SlotSize;        /*!< Specifies the Slot Size.
00187                                  This parameter can be a value of @ref SAI_Block_Slot_Size              */
00188
00189   uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
00190                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00191
00192   uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
00193                                  This parameter can be a value of @ref SAI_Block_Slot_Active            */
00194 }SAI_SlotInitTypeDef;
00195
00196 /**
00197   * @brief  SAI handle Structure definition
00198   */
00199 typedef struct __SAI_HandleTypeDef
00200 {
00201   SAI_Block_TypeDef         *Instance;  /*!< SAI Blockx registers base address        */
00202
00203   SAI_InitTypeDef           Init;       /*!< SAI communication parameters             */
00204
00205   SAI_FrameInitTypeDef      FrameInit;  /*!< SAI Frame configuration parameters       */
00206
00207   SAI_SlotInitTypeDef       SlotInit;   /*!< SAI Slot configuration parameters        */
00208
00209   uint8_t                  *pBuffPtr;  /*!< Pointer to SAI transfer Buffer            */
00210
00211   uint16_t                  XferSize;  /*!< SAI transfer size                         */
00212
00213   uint16_t                  XferCount; /*!< SAI transfer counter                      */
00214
00215   DMA_HandleTypeDef         *hdmatx;     /*!< SAI Tx DMA handle parameters            */
00216
00217   DMA_HandleTypeDef         *hdmarx;     /*!< SAI Rx DMA handle parameters            */
00218
00219   SAIcallback               mutecallback;/*!< SAI mute callback                       */
00220
00221   void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler   */
00222
00223   HAL_LockTypeDef           Lock;        /*!< SAI locking object                      */
00224
00225   __IO HAL_SAI_StateTypeDef State;       /*!< SAI communication state                 */
00226
00227   __IO uint32_t             ErrorCode;   /*!< SAI Error code                          */
00228 }SAI_HandleTypeDef;
00229
00230 /**
00231   * @}
00232   */
00233
00234 /* Exported constants --------------------------------------------------------*/
00235
00236 /** @defgroup SAI_Exported_Constants SAI Exported Constants
00237   * @{
00238   */
00239
00240 /** @defgroup SAI_Error_Code SAI Error Code
00241   * @{
00242   */
00243 #define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error                                    */
00244 #define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error                               */
00245 #define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error                              */
00246 #define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */
00247 #define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection        */
00248 #define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready                             */
00249 #define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration                   */
00250 #define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error                               */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
00256   * @{
00257   */
00258 #define SAI_SYNCEXT_DISABLE           ((uint32_t)0x00000000U)
00259 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE  ((uint32_t)0x00000001U)
00260 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE  ((uint32_t)0x00000002U)
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SAI_Protocol SAI Supported protocol
00266   * @{
00267   */
00268 #define SAI_I2S_STANDARD      ((uint32_t)0x00000000U)
00269 #define SAI_I2S_MSBJUSTIFIED  ((uint32_t)0x00000001U)
00270 #define SAI_I2S_LSBJUSTIFIED  ((uint32_t)0x00000002U)
00271 #define SAI_PCM_LONG          ((uint32_t)0x00000004U)
00272 #define SAI_PCM_SHORT         ((uint32_t)0x00000008U)
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
00278   * @{
00279   */
00280 #define SAI_PROTOCOL_DATASIZE_16BIT          ((uint32_t)0x00000000U)
00281 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED  ((uint32_t)0x00000001U)
00282 #define SAI_PROTOCOL_DATASIZE_24BIT          ((uint32_t)0x00000002U)
00283 #define SAI_PROTOCOL_DATASIZE_32BIT          ((uint32_t)0x00000004U)
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup SAI_Clock_Source  SAI Clock Source
00289   * @{
00290   */
00291 #define SAI_CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)
00292 #define SAI_CLKSOURCE_PLLI2S             ((uint32_t)0x00100000U)
00293 #define SAI_CLKSOURCE_EXT                ((uint32_t)0x00200000U)
00294 #define SAI_CLKSOURCE_NA                 ((uint32_t)0x00400000U) /*!< No applicable for STM32F446xx  */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
00300   * @{
00301   */
00302 #define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)
00303 #define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)
00304 #define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)
00305 #define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)
00306 #define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)
00307 #define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)
00308 #define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)
00309 #define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)
00310 #define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)
00311 #define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup SAI_Block_Mode SAI Block Mode
00317   * @{
00318   */
00319 #define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)
00320 #define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
00321 #define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
00322 #define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup SAI_Block_Protocol SAI Block Protocol
00328   * @{
00329   */
00330 #define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)
00331 #define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
00332 #define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
00338   * @{
00339   */
00340 #define SAI_DATASIZE_8                   ((uint32_t)SAI_xCR1_DS_1)
00341 #define SAI_DATASIZE_10                  ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00342 #define SAI_DATASIZE_16                  ((uint32_t)SAI_xCR1_DS_2)
00343 #define SAI_DATASIZE_20                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
00344 #define SAI_DATASIZE_24                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
00345 #define SAI_DATASIZE_32                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
00351   * @{
00352   */
00353 #define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)
00354 #define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
00360   * @{
00361   */
00362 #define SAI_CLOCKSTROBING_FALLINGEDGE     ((uint32_t)0x00000000U)
00363 #define SAI_CLOCKSTROBING_RISINGEDGE      ((uint32_t)0x00000001U)
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
00369   * @{
00370   */
00371 #define SAI_ASYNCHRONOUS                  ((uint32_t)0x00000000U) /*!< Asynchronous */
00372 #define SAI_SYNCHRONOUS                   ((uint32_t)0x00000001U) /*!< Synchronous with other block of same SAI */
00373 #define SAI_SYNCHRONOUS_EXT_SAI1          ((uint32_t)0x00000002U) /*!< Synchronous with other SAI, SAI1 */
00374 #define SAI_SYNCHRONOUS_EXT_SAI2          ((uint32_t)0x00000003U) /*!< Synchronous with other SAI, SAI2 */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
00380   * @{
00381   */
00382 #define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)
00383 #define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
00389   * @{
00390   */
00391 #define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)
00392 #define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
00398   * @{
00399   */
00400 #define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)
00401 #define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
00407   * @{
00408   */
00409 #define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)
00410 #define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPO)
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
00416   * @{
00417   */
00418 #define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)
00419 #define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
00425   * @{
00426   */
00427 #define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)
00428 #define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
00429 #define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
00435   * @{
00436   */
00437 #define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)
00438 #define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)
00439 #define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)
00440 #define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)
00441 #define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)
00442 #define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)
00443 #define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)
00444 #define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)
00445 #define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)
00446 #define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)
00447 #define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)
00448 #define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)
00449 #define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)
00450 #define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)
00451 #define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)
00452 #define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)
00453 #define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)
00454 #define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
00460   * @{
00461   */
00462 #define SAI_STEREOMODE                    ((uint32_t)0x00000000U)
00463 #define SAI_MONOMODE                      ((uint32_t)SAI_xCR1_MONO)
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup SAI_TRIState_Management SAI TRIState Management
00469   * @{
00470   */
00471 #define SAI_OUTPUT_NOTRELEASED              ((uint32_t)0x00000000U)
00472 #define SAI_OUTPUT_RELEASED                 ((uint32_t)SAI_xCR2_TRIS)
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
00478   * @{
00479   */
00480 #define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)
00481 #define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)SAI_xCR2_FTH_0)
00482 #define SAI_FIFOTHRESHOLD_HF     ((uint32_t)SAI_xCR2_FTH_1)
00483 #define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
00484 #define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)SAI_xCR2_FTH_2)
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
00490   * @{
00491   */
00492 #define SAI_NOCOMPANDING                  ((uint32_t)0x00000000U)
00493 #define SAI_ULAW_1CPL_COMPANDING          ((uint32_t)SAI_xCR2_COMP_1)
00494 #define SAI_ALAW_1CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
00495 #define SAI_ULAW_2CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
00496 #define SAI_ALAW_2CPL_COMPANDING          ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
00497 /**
00498   * @}
00499   */
00500
00501 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
00502   * @{
00503   */
00504 #define SAI_ZERO_VALUE                      ((uint32_t)0x00000000U)
00505 #define SAI_LAST_SENT_VALUE                 ((uint32_t)SAI_xCR2_MUTEVAL)
00506 /**
00507   * @}
00508   */
00509
00510 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
00511   * @{
00512   */
00513 #define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
00514 #define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
00515 #define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
00516 #define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
00517 #define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
00518 #define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
00519 #define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
00520 /**
00521   * @}
00522   */
00523
00524 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
00525   * @{
00526   */
00527 #define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
00528 #define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
00529 #define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
00530 #define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
00531 #define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
00532 #define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
00533 #define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
00534 /**
00535   * @}
00536   */
00537
00538 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
00539   * @{
00540   */
00541 #define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)
00542 #define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)
00543 #define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)
00544 #define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)
00545 #define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)
00546 #define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)
00547 /**
00548   * @}
00549   */
00550
00551 /**
00552   * @}
00553   */
00554
00555 /* Exported macro ------------------------------------------------------------*/
00556
00557 /** @defgroup SAI_Exported_Macros SAI Exported Macros
00558  *  @brief macros to handle interrupts and specific configurations
00559  * @{
00560  */
00561
00562 /** @brief Reset SAI handle state
00563   * @param  __HANDLE__: specifies the SAI Handle.
00564   * @retval None
00565   */
00566 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
00567
00568 /** @brief  Enable or disable the specified SAI interrupts.
00569   * @param  __HANDLE__: specifies the SAI Handle.
00570   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00571   *         This parameter can be one of the following values:
00572   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00573   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00574   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00575   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00576   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00577   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00578   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
00579   * @retval None
00580   */
00581 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00582 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
00583
00584 /** @brief  Check if the specified SAI interrupt source is enabled or disabled.
00585   * @param  __HANDLE__: specifies the SAI Handle.
00586   *         This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
00587   * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
00588   *         This parameter can be one of the following values:
00589   *            @arg SAI_IT_TXE: Tx buffer empty interrupt enable.
00590   *            @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable.
00591   *            @arg SAI_IT_ERR: Error interrupt enable.
00592   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00593   */
00594 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00595
00596 /** @brief  Check whether the specified SAI flag is set or not.
00597   * @param  __HANDLE__: specifies the SAI Handle.
00598   * @param  __FLAG__: specifies the flag to check.
00599   *         This parameter can be one of the following values:
00600   *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
00601   *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
00602   *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
00603   *            @arg SAI_FLAG_FREQ: FIFO request flag.
00604   *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
00605   *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
00606   *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
00607   * @retval The new state of __FLAG__ (TRUE or FALSE).
00608   */
00609 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00610
00611 /** @brief  Clears the specified SAI pending flag.
00612   * @param  __HANDLE__: specifies the SAI Handle.
00613   * @param  __FLAG__: specifies the flag to check.
00614   *          This parameter can be any combination of the following values:
00615   *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
00616   *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
00617   *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
00618   *            @arg SAI_FLAG_FREQ: Clear FIFO request
00619   *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
00620   *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
00621   *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
00622   * @retval None
00623   */
00624 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00625
00626 /** @brief  Enable SAI
00627   * @param  __HANDLE__: specifies the SAI Handle.
00628   * @retval None
00629   */
00630 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
00631
00632 /** @brief  Disable SAI
00633   * @param  __HANDLE__: specifies the SAI Handle.
00634   * @retval None
00635   */
00636 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
00637
00638  /**
00639   * @}
00640   */
00641
00642 /* Include RCC SAI Extension module */
00643 #include "stm32f4xx_hal_sai_ex.h"
00644
00645 /* Exported functions --------------------------------------------------------*/
00646
00647 /** @addtogroup SAI_Exported_Functions
00648   * @{
00649   */
00650
00651 /* Initialization/de-initialization functions  **********************************/
00652 /** @addtogroup SAI_Exported_Functions_Group1
00653   * @{
00654   */
00655 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00656 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
00657 HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
00658 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
00659 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
00660
00661 /**
00662   * @}
00663   */
00664
00665 /* I/O operation functions  *****************************************************/
00666 /** @addtogroup SAI_Exported_Functions_Group2
00667   * @{
00668   */
00669 /* Blocking mode: Polling */
00670 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00671 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00672
00673 /* Non-Blocking mode: Interrupt */
00674 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00675 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00676
00677 /* Non-Blocking mode: DMA */
00678 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00679 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00680 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
00681 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
00682 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
00683
00684 /* Abort function */
00685 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
00686
00687 /* Mute management */
00688 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
00689 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
00690 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
00691 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
00692
00693 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00694 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
00695 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00696 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
00697 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00698 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
00699 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
00700 /**
00701   * @}
00702   */
00703
00704 /** @addtogroup SAI_Exported_Functions_Group3
00705   * @{
00706   */
00707 /* Peripheral State functions  ************************************************/
00708 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
00709 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
00710 /**
00711   * @}
00712   */
00713
00714 /**
00715   * @}
00716   */
00717
00718 /* Private types -------------------------------------------------------------*/
00719 /** @defgroup SAI_Private_Types SAI Private Types
00720   * @{
00721   */
00722
00723 /**
00724   * @}
00725   */
00726
00727 /* Private variables ---------------------------------------------------------*/
00728 /** @defgroup SAI_Private_Variables SAI Private Variables
00729   * @{
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 /* Private constants ---------------------------------------------------------*/
00737 /** @defgroup SAI_Private_Constants SAI Private Constants
00738   * @{
00739   */
00740
00741 /**
00742   * @}
00743   */
00744
00745 /* Private macros ------------------------------------------------------------*/
00746 /** @addtogroup SAI_Private_Macros
00747   * @{
00748   */
00749 #define IS_SAI_BLOCK_SYNCEXT(STATE)   (((STATE) == SAI_SYNCEXT_DISABLE)           ||\
00750                                        ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE)  ||\
00751                                        ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
00752
00753 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
00754                                                ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
00755                                                ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
00756                                                ((PROTOCOL) == SAI_PCM_LONG)         ||\
00757                                                ((PROTOCOL) == SAI_PCM_SHORT))
00758
00759 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
00760                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
00761                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
00762                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
00763
00764 #define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
00765                                    ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
00766                                    ((SOURCE) == SAI_CLKSOURCE_EXT))
00767
00768 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
00769                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
00770                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
00771                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
00772                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
00773
00774 #define IS_SAI_BLOCK_MODE(MODE)    (((MODE) == SAI_MODEMASTER_TX) || \
00775                                     ((MODE) == SAI_MODEMASTER_RX) || \
00776                                     ((MODE) == SAI_MODESLAVE_TX)  || \
00777                                     ((MODE) == SAI_MODESLAVE_RX))
00778
00779 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
00780                                          ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
00781                                          ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
00782
00783 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
00784                                          ((DATASIZE) == SAI_DATASIZE_10) || \
00785                                          ((DATASIZE) == SAI_DATASIZE_16) || \
00786                                          ((DATASIZE) == SAI_DATASIZE_20) || \
00787                                          ((DATASIZE) == SAI_DATASIZE_24) || \
00788                                          ((DATASIZE) == SAI_DATASIZE_32))
00789
00790 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
00791                                      ((BIT) == SAI_FIRSTBIT_LSB))
00792
00793 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
00794                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
00795
00796 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
00797                                        ((SYNCHRO) == SAI_SYNCHRONOUS)  || \
00798                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
00799                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
00800
00801 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
00802                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
00803
00804 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
00805                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
00806
00807 #define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOSTATUS_LESS1QUARTERFULL ) || \
00808                                           ((STATUS) == SAI_FIFOSTATUS_HALFFULL)          || \
00809                                           ((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL)      || \
00810                                           ((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL)     || \
00811                                           ((STATUS) == SAI_FIFOSTATUS_FULL)              || \
00812                                           ((STATUS) == SAI_FIFOSTATUS_EMPTY))
00813
00814 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
00815
00816 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
00817                                            ((VALUE) == SAI_LAST_SENT_VALUE))
00818
00819 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
00820                                                ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
00821                                                ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
00822                                                ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
00823                                                ((MODE) == SAI_ALAW_2CPL_COMPANDING))
00824
00825 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
00826                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
00827                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
00828                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
00829                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
00830
00831 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
00832                                                  ((STATE) == SAI_OUTPUT_RELEASED))
00833
00834 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
00835                                        ((MODE) == SAI_STEREOMODE))
00836
00837 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
00838
00839 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
00840
00841 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
00842                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
00843                                       ((SIZE) == SAI_SLOTSIZE_32B))
00844
00845 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
00846
00847 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
00848                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
00849
00850 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
00851                                             ((POLARITY) == SAI_FS_ACTIVE_HIGH))
00852
00853 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
00854                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
00855
00856 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)
00857
00858 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
00859
00860 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
00861
00862 /**
00863   * @}
00864   */
00865
00866 /* Private functions ---------------------------------------------------------*/
00867 /** @defgroup SAI_Private_Functions SAI Private Functions
00868   * @{
00869   */
00870
00871 /**
00872   * @}
00873   */
00874
00875 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00876 /**
00877   * @}
00878   */
00879
00880 /**
00881   * @}
00882   */
00883
00884 #ifdef __cplusplus
00885 }
00886 #endif
00887
00888 #endif /* __STM32F4xx_HAL_SAI_H */
00889
00890 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai_ex.c Source File

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stm32f4xx_hal_sai_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sai_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   SAI Extension HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of SAI extension peripheral:
00010   *           + Extension features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### SAI peripheral extension features  #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the SAI interface for STM32F446xx
00018        devices contains the following additional features :
00019
00020        (+) Possibility to be clocked from PLLR
00021
00022                      ##### How to use this driver #####
00023   ==============================================================================
00024   [..] This driver provides functions to manage several sources to clock SAI
00025
00026   @endverbatim
00027   ******************************************************************************
00028   * @attention
00029   *
00030   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00031   *
00032   * Redistribution and use in source and binary forms, with or without modification,
00033   * are permitted provided that the following conditions are met:
00034   *   1. Redistributions of source code must retain the above copyright notice,
00035   *      this list of conditions and the following disclaimer.
00036   *   2. Redistributions in binary form must reproduce the above copyright notice,
00037   *      this list of conditions and the following disclaimer in the documentation
00038   *      and/or other materials provided with the distribution.
00039   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00040   *      may be used to endorse or promote products derived from this software
00041   *      without specific prior written permission.
00042   *
00043   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00044   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00045   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00046   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00047   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00048   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00049   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00050   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00051   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00052   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00053   *
00054   ******************************************************************************
00055   */
00056
00057 /* Includes ------------------------------------------------------------------*/
00058 #include "stm32f4xx_hal.h"
00059
00060 /** @addtogroup STM32F4xx_HAL_Driver
00061   * @{
00062   */
00063
00064 /** @defgroup SAIEx SAIEx
00065   * @brief SAI Extension HAL module driver
00066   * @{
00067   */
00068
00069 #ifdef HAL_SAI_MODULE_ENABLED
00070
00071 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00072     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00073
00074 /* Private typedef -----------------------------------------------------------*/
00075 /* Private define ------------------------------------------------------------*/
00076 /* SAI registers Masks */
00077 /* Private macro -------------------------------------------------------------*/
00078 /* Private variables ---------------------------------------------------------*/
00079 /* Private function prototypes -----------------------------------------------*/
00080 /* Private functions ---------------------------------------------------------*/
00081
00082 /** @defgroup SAI_Private_Functions  SAI Private Functions
00083   * @{
00084   */
00085  /**
00086   * @}
00087   */
00088
00089 /* Exported functions --------------------------------------------------------*/
00090 /** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
00091   * @{
00092   */
00093
00094 /** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
00095   *  @brief   Extension features functions
00096   *
00097 @verbatim
00098  ===============================================================================
00099                        ##### Extension features Functions #####
00100  ===============================================================================
00101     [..]
00102     This subsection provides a set of functions allowing to manage the possible
00103     SAI clock sources.
00104
00105 @endverbatim
00106   * @{
00107   */
00108
00109 /**
00110   * @brief  Configure SAI Block synchronization mode
00111   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00112   *               the configuration information for SAI module.
00113   * @retval SAI Clock Input
00114   */
00115 void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
00116 {
00117   uint32_t tmpregisterGCR = 0U;
00118
00119 #if defined(STM32F446xx)
00120   /* This setting must be done with both audio block (A & B) disabled         */
00121   switch(hsai->Init.SynchroExt)
00122   {
00123     case SAI_SYNCEXT_DISABLE :
00124       tmpregisterGCR = 0U;
00125       break;
00126     case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
00127       tmpregisterGCR = SAI_GCR_SYNCOUT_0;
00128       break;
00129     case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
00130       tmpregisterGCR = SAI_GCR_SYNCOUT_1;
00131       break;
00132   default:
00133     tmpregisterGCR = 0U;
00134     break;
00135   }
00136
00137   if((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
00138   {
00139         tmpregisterGCR |= SAI_GCR_SYNCIN_0;
00140   }
00141
00142   if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00143   {
00144     SAI1->GCR = tmpregisterGCR;
00145   }
00146   else
00147   {
00148     SAI2->GCR = tmpregisterGCR;
00149   }
00150 #endif /* STM32F446xx */
00151 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00152     defined(STM32F469xx) || defined(STM32F479xx)
00153   /* This setting must be done with both audio block (A & B) disabled         */
00154   switch(hsai->Init.SynchroExt)
00155   {
00156   case SAI_SYNCEXT_DISABLE :
00157     tmpregisterGCR = 0U;
00158     break;
00159   case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
00160     tmpregisterGCR = SAI_GCR_SYNCOUT_0;
00161     break;
00162   case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
00163     tmpregisterGCR = SAI_GCR_SYNCOUT_1;
00164     break;
00165   default:
00166     tmpregisterGCR = 0U;
00167     break;
00168   }
00169   SAI1->GCR = tmpregisterGCR;
00170 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00171 }
00172   /**
00173   * @brief  Get SAI Input Clock based on SAI source clock selection
00174   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00175   *               the configuration information for SAI module.
00176   * @retval SAI Clock Input
00177   */
00178 uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
00179 {
00180   /* This variable used to store the SAI_CK_x (value in Hz) */
00181   uint32_t saiclocksource = 0U;
00182
00183 #if defined(STM32F446xx)
00184   if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00185   {
00186     saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00187   }
00188   else /* SAI2_Block_A || SAI2_Block_B*/
00189   {
00190     saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
00191   }
00192 #endif /* STM32F446xx */
00193 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00194     defined(STM32F469xx) || defined(STM32F479xx)
00195   uint32_t vcoinput = 0U, tmpreg = 0U;
00196
00197   /* Check the SAI Block parameters */
00198   assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
00199
00200   /* SAI Block clock source selection */
00201   if(hsai->Instance == SAI1_Block_A)
00202   {
00203      __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
00204   }
00205   else
00206   {
00207      __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2U));
00208   }
00209
00210   /* VCO Input Clock value calculation */
00211   if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
00212   {
00213     /* In Case the PLL Source is HSI (Internal Clock) */
00214     vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
00215   }
00216   else
00217   {
00218     /* In Case the PLL Source is HSE (External Clock) */
00219     vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
00220   }
00221
00222   /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
00223   if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
00224   {
00225     /* Configure the PLLI2S division factor */
00226     /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
00227     /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
00228     /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
00229     tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
00230     saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg);
00231
00232     /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
00233     tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
00234     saiclocksource = saiclocksource/(tmpreg);
00235
00236   }
00237   else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
00238   {
00239     /* Configure the PLLI2S division factor */
00240     /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
00241     /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
00242     /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
00243     tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
00244     saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg);
00245
00246     /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
00247     tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
00248     saiclocksource = saiclocksource/(tmpreg);
00249   }
00250   else /* sConfig->ClockSource == SAI_CLKSource_Ext */
00251   {
00252     /* Enable the External Clock selection */
00253     __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
00254
00255     saiclocksource = EXTERNAL_CLOCK_VALUE;
00256   }
00257 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
00258        /* the return result is the value of SAI clock */
00259   return saiclocksource;
00260 }
00261
00262 /**
00263   * @}
00264   */
00265
00266 /**
00267   * @}
00268   */
00269
00270 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx  || STM32F446xx || STM32F469xx || STM32F479xx */
00271 #endif /* HAL_SAI_MODULE_ENABLED */
00272 /**
00273   * @}
00274   */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sai_ex.h Source File

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stm32f4xx_hal_sai_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sai_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SAI Extension HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SAI_EX_H
00040 #define __STM32F4xx_HAL_SAI_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SAIEx
00054   * @{
00055   */
00056
00057 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00058     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /* Exported constants --------------------------------------------------------*/
00062 /* Exported functions --------------------------------------------------------*/
00063 /** @addtogroup SAIEx_Exported_Functions
00064   * @{
00065   */
00066
00067 /** @addtogroup SAIEx_Exported_Functions_Group1
00068   * @{
00069   */
00070
00071 /* Extended features functions ************************************************/
00072 void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
00073 uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
00074 /**
00075   * @}
00076   */
00077
00078 /**
00079   * @}
00080   */
00081 /* Private types -------------------------------------------------------------*/
00082 /* Private variables ---------------------------------------------------------*/
00083 /* Private constants ---------------------------------------------------------*/
00084 /* Private macros ------------------------------------------------------------*/
00085 /* Private functions ---------------------------------------------------------*/
00086
00087 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00088 /**
00089   * @}
00090   */
00091
00092 /**
00093   * @}
00094   */
00095
00096 #ifdef __cplusplus
00097 }
00098 #endif
00099
00100 #endif /* __STM32F4xx_HAL_SAI_EX_H */
00101
00102 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sd.c Source File

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stm32f4xx_hal_sd.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sd.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   SD card HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (SD) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     This driver implements a high level communication layer for read and write from/to
00021     this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
00022     the user in HAL_SD_MspInit() function (MSP layer).
00023     Basically, the MSP layer configuration should be the same as we provide in the
00024     examples.
00025     You can easily tailor this configuration according to hardware resources.
00026
00027   [..]
00028     This driver is a generic layered driver for SDIO memories which uses the HAL
00029     SDIO driver functions to interface with SD and uSD cards devices.
00030     It is used as follows:
00031
00032     (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
00033         (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
00034         (##) SDIO pins configuration for SD card
00035             (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00036             (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
00037                   and according to your pin assignment;
00038         (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
00039              and HAL_SD_WriteBlocks_DMA() APIs).
00040             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
00041             (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
00042         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
00043             (+++) Configure the SDIO and DMA interrupt priorities using functions
00044                   HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
00045             (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
00046             (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT()
00047                   and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
00048             (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
00049                   and __HAL_SD_SDIO_CLEAR_IT()
00050     (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
00051
00052
00053   *** SD Card Initialization and configuration ***
00054   ================================================
00055   [..]
00056     To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes
00057     the SD Card and put it into Standby State (Ready for data transfer).
00058     This function provide the following operations:
00059
00060     (#) Apply the SD Card initialization process at 400KHz and check the SD Card
00061         type (Standard Capacity or High Capacity). You can change or adapt this
00062         frequency by adjusting the "ClockDiv" field.
00063         The SD Card frequency (SDIO_CK) is computed as follows:
00064
00065            SDIO_CK = SDIOCLK / (ClockDiv + 2)
00066
00067         In initialization mode and according to the SD Card standard,
00068         make sure that the SDIO_CK frequency doesn't exceed 400KHz.
00069
00070     (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
00071         structure. This structure provide also ready computed SD Card capacity
00072         and Block size.
00073
00074         -@- These information are stored in SD handle structure in case of future use.
00075
00076     (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
00077         frequency is set to 24MHz. You can change or adapt this frequency by adjusting
00078         the "ClockDiv" field.
00079         In transfer mode and according to the SD Card standard, make sure that the
00080         SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
00081         To be able to use a frequency higher than 24MHz, you should use the SDIO
00082         peripheral in bypass mode. Refer to the corresponding reference manual
00083         for more details.
00084
00085     (#) Select the corresponding SD Card according to the address read with the step 2.
00086
00087     (#) Configure the SD Card in wide bus mode: 4-bits data.
00088
00089   *** SD Card Read operation ***
00090   ==============================
00091   [..]
00092     (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
00093         This function support only 512-bytes block length (the block size should be
00094         chosen as 512 bytes).
00095         You can choose either one block read operation or multiple block read operation
00096         by adjusting the "NumberOfBlocks" parameter.
00097
00098     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
00099         This function support only 512-bytes block length (the block size should be
00100         chosen as 512 bytes).
00101         You can choose either one block read operation or multiple block read operation
00102         by adjusting the "NumberOfBlocks" parameter.
00103         After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
00104         that the read transfer is done correctly in both DMA and SD sides.
00105
00106   *** SD Card Write operation ***
00107   ===============================
00108   [..]
00109     (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
00110         This function support only 512-bytes block length (the block size should be
00111         chosen as 512 bytes).
00112         You can choose either one block read operation or multiple block read operation
00113         by adjusting the "NumberOfBlocks" parameter.
00114
00115     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
00116         This function support only 512-bytes block length (the block size should be
00117         chosen as 512 byte).
00118         You can choose either one block read operation or multiple block read operation
00119         by adjusting the "NumberOfBlocks" parameter.
00120         After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
00121         that the write transfer is done correctly in both DMA and SD sides.
00122
00123   *** SD card status ***
00124   ======================
00125   [..]
00126     (+) At any time, you can check the SD Card status and get the SD card state
00127         by using the HAL_SD_GetStatus() function. This function checks first if the
00128         SD card is still connected and then get the internal SD Card transfer state.
00129     (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
00130         function.
00131
00132   *** SD HAL driver macros list ***
00133   ==================================
00134   [..]
00135     Below the list of most used macros in SD HAL driver.
00136
00137     (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
00138     (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
00139     (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
00140     (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
00141     (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
00142     (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
00143     (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
00144     (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags
00145
00146     (@) You can refer to the SD HAL driver header file for more useful macros
00147
00148   @endverbatim
00149   ******************************************************************************
00150   * @attention
00151   *
00152   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00153   *
00154   * Redistribution and use in source and binary forms, with or without modification,
00155   * are permitted provided that the following conditions are met:
00156   *   1. Redistributions of source code must retain the above copyright notice,
00157   *      this list of conditions and the following disclaimer.
00158   *   2. Redistributions in binary form must reproduce the above copyright notice,
00159   *      this list of conditions and the following disclaimer in the documentation
00160   *      and/or other materials provided with the distribution.
00161   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00162   *      may be used to endorse or promote products derived from this software
00163   *      without specific prior written permission.
00164   *
00165   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00166   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00167   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00168   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00169   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00170   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00171   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00172   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00173   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00174   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00175   *
00176   ******************************************************************************
00177   */
00178
00179 /* Includes ------------------------------------------------------------------*/
00180 #include "stm32f4xx_hal.h"
00181
00182 #ifdef HAL_SD_MODULE_ENABLED
00183 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00184     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00185     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00186     defined(STM32F469xx) || defined(STM32F479xx)
00187 /** @addtogroup STM32F4xx_HAL_Driver
00188   * @{
00189   */
00190
00191 /** @addtogroup SD
00192   * @{
00193   */
00194
00195 /* Private typedef -----------------------------------------------------------*/
00196 /* Private define ------------------------------------------------------------*/
00197 /** @addtogroup SD_Private_Defines
00198   * @{
00199   */
00200 /**
00201   * @brief  SDIO Data block size
00202   */
00203 #define DATA_BLOCK_SIZE                  ((uint32_t)(9U << 4U))
00204 /**
00205   * @brief  SDIO Static flags, Timeout, FIFO Address
00206   */
00207 #define SDIO_STATIC_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
00208                                                     SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
00209                                                     SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
00210                                                     SDIO_FLAG_DBCKEND))
00211
00212 #define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000U)
00213
00214 /**
00215   * @brief  Mask for errors Card Status R1 (OCR Register)
00216   */
00217 #define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)
00218 #define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)
00219 #define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)
00220 #define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)
00221 #define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)
00222 #define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)
00223 #define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)
00224 #define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)
00225 #define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)
00226 #define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)
00227 #define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000U)
00228 #define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)
00229 #define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)
00230 #define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)
00231 #define SD_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)
00232 #define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)
00233 #define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)
00234 #define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000U)
00235 #define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)
00236 #define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)
00237
00238 /**
00239   * @brief  Masks for R6 Response
00240   */
00241 #define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)
00242 #define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)
00243 #define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)
00244
00245 #define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)
00246 #define SD_HIGH_CAPACITY                ((uint32_t)0x40000000U)
00247 #define SD_STD_CAPACITY                 ((uint32_t)0x00000000U)
00248 #define SD_CHECK_PATTERN                ((uint32_t)0x000001AAU)
00249
00250 #define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
00251 #define SD_ALLZERO                      ((uint32_t)0x00000000U)
00252
00253 #define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)
00254 #define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
00255 #define SD_CARD_LOCKED                  ((uint32_t)0x02000000U)
00256
00257 #define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
00258 #define SD_0TO7BITS                     ((uint32_t)0x000000FFU)
00259 #define SD_8TO15BITS                    ((uint32_t)0x0000FF00U)
00260 #define SD_16TO23BITS                   ((uint32_t)0x00FF0000U)
00261 #define SD_24TO31BITS                   ((uint32_t)0xFF000000U)
00262 #define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)
00263
00264 #define SD_HALFFIFO                     ((uint32_t)0x00000008U)
00265 #define SD_HALFFIFOBYTES                ((uint32_t)0x00000020U)
00266
00267 /**
00268   * @brief  Command Class Supported
00269   */
00270 #define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080U)
00271 #define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040U)
00272 #define SD_CCCC_ERASE                   ((uint32_t)0x00000020U)
00273
00274 /**
00275   * @brief  Following commands are SD Card Specific commands.
00276   *         SDIO_APP_CMD should be sent before sending these commands.
00277   */
00278 #define SD_SDIO_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
00279
00280 /**
00281   * @}
00282   */
00283
00284 /* Private macro -------------------------------------------------------------*/
00285 /* Private variables ---------------------------------------------------------*/
00286 /* Private function prototypes -----------------------------------------------*/
00287 /** @addtogroup SD_Private_Functions_Prototypes
00288   * @{
00289   */
00290 static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
00291 static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
00292 static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd);
00293 static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
00294 static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
00295 static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
00296 static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
00297 static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
00298 static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
00299 static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
00300 static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
00301 static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
00302 static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
00303 static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
00304 static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
00305 static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
00306 static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
00307 static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
00308 static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
00309 static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
00310 /**
00311   * @}
00312   */
00313 /* Exported functions --------------------------------------------------------*/
00314 /** @addtogroup SD_Exported_Functions
00315   * @{
00316   */
00317
00318 /** @addtogroup SD_Exported_Functions_Group1
00319  *  @brief   Initialization and de-initialization functions
00320  *
00321 @verbatim
00322   ==============================================================================
00323           ##### Initialization and de-initialization functions #####
00324   ==============================================================================
00325   [..]
00326     This section provides functions allowing to initialize/de-initialize the SD
00327     card device to be ready for use.
00328
00329
00330 @endverbatim
00331   * @{
00332   */
00333
00334 /**
00335   * @brief  Initializes the SD card according to the specified parameters in the
00336             SD_HandleTypeDef and create the associated handle.
00337   * @param  hsd: SD handle
00338   * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information
00339   * @retval HAL SD error state
00340   */
00341 HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
00342 {
00343   __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
00344   SD_InitTypeDef tmpinit;
00345
00346   /* Allocate lock resource and initialize it */
00347   hsd->Lock = HAL_UNLOCKED;
00348   /* Initialize the low level hardware (MSP) */
00349   HAL_SD_MspInit(hsd);
00350
00351   /* Default SDIO peripheral configuration for SD card initialization */
00352   tmpinit.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
00353   tmpinit.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
00354   tmpinit.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
00355   tmpinit.BusWide             = SDIO_BUS_WIDE_1B;
00356   tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
00357   tmpinit.ClockDiv            = SDIO_INIT_CLK_DIV;
00358
00359   /* Initialize SDIO peripheral interface with default configuration */
00360   SDIO_Init(hsd->Instance, tmpinit);
00361
00362   /* Identify card operating voltage */
00363   errorstate = SD_PowerON(hsd);
00364
00365   if(errorstate != SD_OK)
00366   {
00367     return errorstate;
00368   }
00369
00370   /* Initialize the present SDIO card(s) and put them in idle state */
00371   errorstate = SD_Initialize_Cards(hsd);
00372
00373   if (errorstate != SD_OK)
00374   {
00375     return errorstate;
00376   }
00377
00378   /* Read CSD/CID MSD registers */
00379   errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
00380
00381   if (errorstate == SD_OK)
00382   {
00383     /* Select the Card */
00384     errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16U));
00385   }
00386
00387   /* Configure SDIO peripheral interface */
00388   SDIO_Init(hsd->Instance, hsd->Init);
00389
00390   return errorstate;
00391 }
00392
00393 /**
00394   * @brief  De-Initializes the SD card.
00395   * @param  hsd: SD handle
00396   * @retval HAL status
00397   */
00398 HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
00399 {
00400
00401   /* Set SD power state to off */
00402   SD_PowerOFF(hsd);
00403
00404   /* De-Initialize the MSP layer */
00405   HAL_SD_MspDeInit(hsd);
00406
00407   return HAL_OK;
00408 }
00409
00410
00411 /**
00412   * @brief  Initializes the SD MSP.
00413   * @param  hsd: SD handle
00414   * @retval None
00415   */
00416 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
00417 {
00418   /* Prevent unused argument(s) compilation warning */
00419   UNUSED(hsd);
00420   /* NOTE : This function Should not be modified, when the callback is needed,
00421             the HAL_SD_MspInit could be implemented in the user file
00422    */
00423 }
00424
00425 /**
00426   * @brief  De-Initialize SD MSP.
00427   * @param  hsd: SD handle
00428   * @retval None
00429   */
00430 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
00431 {
00432   /* Prevent unused argument(s) compilation warning */
00433   UNUSED(hsd);
00434   /* NOTE : This function Should not be modified, when the callback is needed,
00435             the HAL_SD_MspDeInit could be implemented in the user file
00436    */
00437 }
00438
00439 /**
00440   * @}
00441   */
00442
00443 /** @addtogroup SD_Exported_Functions_Group2
00444  *  @brief   Data transfer functions
00445  *
00446 @verbatim
00447   ==============================================================================
00448                         ##### IO operation functions #####
00449   ==============================================================================
00450   [..]
00451     This subsection provides a set of functions allowing to manage the data
00452     transfer from/to SD card.
00453
00454 @endverbatim
00455   * @{
00456   */
00457
00458 /**
00459   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00460   *         is managed by polling mode.
00461   * @param  hsd: SD handle
00462   * @param  pReadBuffer: pointer to the buffer that will contain the received data
00463   * @param  ReadAddr: Address from where data is to be read
00464   * @param  BlockSize: SD card Data block size
00465   * @note   BlockSize must be 512 bytes.
00466   * @param  NumberOfBlocks: Number of SD blocks to read
00467   * @retval SD Card error state
00468   */
00469 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00470 {
00471   SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
00472   SDIO_DataInitTypeDef sdio_datainitstructure;
00473   HAL_SD_ErrorTypedef errorstate = SD_OK;
00474   uint32_t count = 0U, *tempbuff = (uint32_t *)pReadBuffer;
00475
00476   /* Initialize data control register */
00477   hsd->Instance->DCTRL = 0U;
00478
00479   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00480   {
00481     BlockSize = 512U;
00482     ReadAddr /= 512U;
00483   }
00484
00485   /* Set Block Size for Card */
00486   sdio_cmdinitstructure.Argument         = (uint32_t) BlockSize;
00487   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00488   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
00489   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
00490   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
00491   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
00492
00493   /* Check for error conditions */
00494   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00495
00496   if (errorstate != SD_OK)
00497   {
00498     return errorstate;
00499   }
00500
00501   /* Configure the SD DPSM (Data Path State Machine) */
00502   sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00503   sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
00504   sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
00505   sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
00506   sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
00507   sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
00508   SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
00509
00510   if(NumberOfBlocks > 1U)
00511   {
00512     /* Send CMD18 READ_MULT_BLOCK with argument data address */
00513     sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
00514   }
00515   else
00516   {
00517     /* Send CMD17 READ_SINGLE_BLOCK */
00518     sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
00519   }
00520
00521   sdio_cmdinitstructure.Argument         = (uint32_t)ReadAddr;
00522   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
00523
00524   /* Read block(s) in polling mode */
00525   if(NumberOfBlocks > 1U)
00526   {
00527     /* Check for error conditions */
00528     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
00529
00530     if (errorstate != SD_OK)
00531     {
00532       return errorstate;
00533     }
00534
00535     /* Poll on SDIO flags */
00536 #ifdef SDIO_STA_STBITERR
00537     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
00538 #else /* SDIO_STA_STBITERR not defined */
00539     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
00540 #endif /* SDIO_STA_STBITERR */
00541     {
00542       if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
00543       {
00544         /* Read data from SDIO Rx FIFO */
00545         for (count = 0U; count < 8U; count++)
00546         {
00547           *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
00548         }
00549
00550         tempbuff += 8U;
00551       }
00552     }
00553   }
00554   else
00555   {
00556     /* Check for error conditions */
00557     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
00558
00559     if (errorstate != SD_OK)
00560     {
00561       return errorstate;
00562     }
00563
00564     /* In case of single block transfer, no need of stop transfer at all */
00565 #ifdef SDIO_STA_STBITERR
00566     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
00567 #else /* SDIO_STA_STBITERR not defined */
00568     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
00569 #endif /* SDIO_STA_STBITERR */
00570     {
00571       if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
00572       {
00573         /* Read data from SDIO Rx FIFO */
00574         for (count = 0U; count < 8U; count++)
00575         {
00576           *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
00577         }
00578
00579         tempbuff += 8U;
00580       }
00581     }
00582   }
00583
00584   /* Send stop transmission command in case of multiblock read */
00585   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00586   {
00587     if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
00588       (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
00589         (hsd->CardType == HIGH_CAPACITY_SD_CARD))
00590     {
00591       /* Send stop transmission command */
00592       errorstate = HAL_SD_StopTransfer(hsd);
00593     }
00594   }
00595
00596   /* Get error state */
00597   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
00598   {
00599     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
00600
00601     errorstate = SD_DATA_TIMEOUT;
00602
00603     return errorstate;
00604   }
00605   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
00606   {
00607     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
00608
00609     errorstate = SD_DATA_CRC_FAIL;
00610
00611     return errorstate;
00612   }
00613   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
00614   {
00615     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
00616
00617     errorstate = SD_RX_OVERRUN;
00618
00619     return errorstate;
00620   }
00621 #ifdef SDIO_STA_STBITERR
00622   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
00623   {
00624     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
00625
00626     errorstate = SD_START_BIT_ERR;
00627
00628     return errorstate;
00629   }
00630 #endif /* SDIO_STA_STBITERR */
00631   else
00632   {
00633     /* No error flag set */
00634   }
00635
00636   count = SD_DATATIMEOUT;
00637
00638   /* Empty FIFO if there is still any data */
00639   while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0U))
00640   {
00641     *tempbuff = SDIO_ReadFIFO(hsd->Instance);
00642     tempbuff++;
00643     count--;
00644   }
00645
00646   /* Clear all the static flags */
00647   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00648
00649   return errorstate;
00650 }
00651
00652 /**
00653   * @brief  Allows to write block(s) to a specified address in a card. The Data
00654   *         transfer is managed by polling mode.
00655   * @param  hsd: SD handle
00656   * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
00657   * @param  WriteAddr: Address from where data is to be written
00658   * @param  BlockSize: SD card Data block size
00659   * @note   BlockSize must be 512 bytes.
00660   * @param  NumberOfBlocks: Number of SD blocks to write
00661   * @retval SD Card error state
00662   */
00663 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00664 {
00665   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
00666   SDIO_DataInitTypeDef sdio_datainitstructure;
00667   HAL_SD_ErrorTypedef errorstate = SD_OK;
00668   uint32_t totalnumberofbytes = 0U, bytestransferred = 0U, count = 0U, restwords = 0U;
00669   uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
00670   uint8_t cardstate  = 0U;
00671
00672   /* Initialize data control register */
00673   hsd->Instance->DCTRL = 0U;
00674
00675   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00676   {
00677     BlockSize = 512U;
00678     WriteAddr /= 512U;
00679   }
00680
00681   /* Set Block Size for Card */
00682   sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
00683   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00684   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
00685   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
00686   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
00687   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
00688
00689   /* Check for error conditions */
00690   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00691
00692   if (errorstate != SD_OK)
00693   {
00694     return errorstate;
00695   }
00696
00697   if(NumberOfBlocks > 1U)
00698   {
00699     /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
00700     sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
00701   }
00702   else
00703   {
00704     /* Send CMD24 WRITE_SINGLE_BLOCK */
00705     sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
00706   }
00707
00708   sdio_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
00709   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
00710
00711   /* Check for error conditions */
00712   if(NumberOfBlocks > 1U)
00713   {
00714     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
00715   }
00716   else
00717   {
00718     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
00719   }
00720
00721   if (errorstate != SD_OK)
00722   {
00723     return errorstate;
00724   }
00725
00726   /* Set total number of bytes to write */
00727   totalnumberofbytes = NumberOfBlocks * BlockSize;
00728
00729   /* Configure the SD DPSM (Data Path State Machine) */
00730   sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00731   sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
00732   sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
00733   sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
00734   sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
00735   sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
00736   SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
00737
00738   /* Write block(s) in polling mode */
00739   if(NumberOfBlocks > 1U)
00740   {
00741 #ifdef SDIO_STA_STBITERR
00742     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
00743 #else /* SDIO_STA_STBITERR not defined */
00744     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
00745 #endif /* SDIO_STA_STBITERR */
00746     {
00747       if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
00748       {
00749         if ((totalnumberofbytes - bytestransferred) < 32U)
00750         {
00751           restwords = ((totalnumberofbytes - bytestransferred) % 4U == 0U) ? ((totalnumberofbytes - bytestransferred) / 4U) : (( totalnumberofbytes -  bytestransferred) / 4U + 1U);
00752
00753           /* Write data to SDIO Tx FIFO */
00754           for (count = 0U; count < restwords; count++)
00755           {
00756             SDIO_WriteFIFO(hsd->Instance, tempbuff);
00757             tempbuff++;
00758             bytestransferred += 4U;
00759           }
00760         }
00761         else
00762         {
00763           /* Write data to SDIO Tx FIFO */
00764           for (count = 0U; count < 8U; count++)
00765           {
00766             SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
00767           }
00768
00769           tempbuff += 8U;
00770           bytestransferred += 32U;
00771         }
00772       }
00773     }
00774   }
00775   else
00776   {
00777     /* In case of single data block transfer no need of stop command at all */
00778 #ifdef SDIO_STA_STBITERR
00779     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
00780 #else /* SDIO_STA_STBITERR not defined */
00781     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
00782 #endif /* SDIO_STA_STBITERR */
00783     {
00784       if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
00785       {
00786         if ((totalnumberofbytes - bytestransferred) < 32U)
00787         {
00788           restwords = ((totalnumberofbytes - bytestransferred) % 4U == 0U) ? ((totalnumberofbytes - bytestransferred) / 4U) : (( totalnumberofbytes -  bytestransferred) / 4U + 1U);
00789
00790           /* Write data to SDIO Tx FIFO */
00791           for (count = 0U; count < restwords; count++)
00792           {
00793             SDIO_WriteFIFO(hsd->Instance, tempbuff);
00794             tempbuff++;
00795             bytestransferred += 4U;
00796           }
00797         }
00798         else
00799         {
00800           /* Write data to SDIO Tx FIFO */
00801           for (count = 0U; count < 8U; count++)
00802           {
00803             SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
00804           }
00805
00806           tempbuff += 8U;
00807           bytestransferred += 32U;
00808         }
00809       }
00810     }
00811   }
00812
00813   /* Send stop transmission command in case of multiblock write */
00814   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00815   {
00816     if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
00817       (hsd->CardType == HIGH_CAPACITY_SD_CARD))
00818     {
00819       /* Send stop transmission command */
00820       errorstate = HAL_SD_StopTransfer(hsd);
00821     }
00822   }
00823
00824   /* Get error state */
00825   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
00826   {
00827     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
00828
00829     errorstate = SD_DATA_TIMEOUT;
00830
00831     return errorstate;
00832   }
00833   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
00834   {
00835     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
00836
00837     errorstate = SD_DATA_CRC_FAIL;
00838
00839     return errorstate;
00840   }
00841   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
00842   {
00843     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
00844
00845     errorstate = SD_TX_UNDERRUN;
00846
00847     return errorstate;
00848   }
00849 #ifdef SDIO_STA_STBITERR
00850   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
00851   {
00852     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
00853
00854     errorstate = SD_START_BIT_ERR;
00855
00856     return errorstate;
00857   }
00858 #endif /* SDIO_STA_STBITERR */
00859   else
00860   {
00861     /* No error flag set */
00862   }
00863
00864   /* Clear all the static flags */
00865   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00866
00867   /* Wait till the card is in programming state */
00868   errorstate = SD_IsCardProgramming(hsd, &cardstate);
00869
00870   while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
00871   {
00872     errorstate = SD_IsCardProgramming(hsd, &cardstate);
00873   }
00874
00875   return errorstate;
00876 }
00877
00878 /**
00879   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00880   *         is managed by DMA mode.
00881   * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
00882   *         to check the completion of the read process
00883   * @param  hsd: SD handle
00884   * @param  pReadBuffer: Pointer to the buffer that will contain the received data
00885   * @param  ReadAddr: Address from where data is to be read
00886   * @param  BlockSize: SD card Data block size
00887   * @note   BlockSize must be 512 bytes.
00888   * @param  NumberOfBlocks: Number of blocks to read.
00889   * @retval SD Card error state
00890   */
00891 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00892 {
00893   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
00894   SDIO_DataInitTypeDef sdio_datainitstructure;
00895   HAL_SD_ErrorTypedef errorstate = SD_OK;
00896
00897   /* Initialize data control register */
00898   hsd->Instance->DCTRL = 0U;
00899
00900   /* Initialize handle flags */
00901   hsd->SdTransferCplt  = 0U;
00902   hsd->DmaTransferCplt = 0U;
00903   hsd->SdTransferErr   = SD_OK;
00904
00905   /* Initialize SD Read operation */
00906   if(NumberOfBlocks > 1U)
00907   {
00908     hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
00909   }
00910   else
00911   {
00912     hsd->SdOperation = SD_READ_SINGLE_BLOCK;
00913   }
00914
00915   /* Enable transfer interrupts */
00916 #ifdef SDIO_STA_STBITERR
00917   __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
00918                                 SDIO_IT_DTIMEOUT |\
00919                                 SDIO_IT_DATAEND  |\
00920                                 SDIO_IT_RXOVERR  |\
00921                                 SDIO_IT_STBITERR));
00922 #else /* SDIO_STA_STBITERR not defined */
00923   __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
00924                                 SDIO_IT_DTIMEOUT |\
00925                                 SDIO_IT_DATAEND  |\
00926                                 SDIO_IT_RXOVERR));
00927 #endif /* SDIO_STA_STBITERR */
00928
00929   /* Enable SDIO DMA transfer */
00930   __HAL_SD_SDIO_DMA_ENABLE();
00931
00932   /* Configure DMA user callbacks */
00933   hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
00934   hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
00935
00936   /* Enable the DMA Stream */
00937   HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
00938
00939   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00940   {
00941     BlockSize = 512U;
00942     ReadAddr /= 512U;
00943   }
00944
00945   /* Set Block Size for Card */
00946   sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
00947   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00948   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
00949   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
00950   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
00951   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
00952
00953   /* Check for error conditions */
00954   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00955
00956   if (errorstate != SD_OK)
00957   {
00958     return errorstate;
00959   }
00960
00961   /* Configure the SD DPSM (Data Path State Machine) */
00962   sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00963   sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
00964   sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
00965   sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
00966   sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
00967   sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
00968   SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
00969
00970   /* Check number of blocks command */
00971   if(NumberOfBlocks > 1U)
00972   {
00973     /* Send CMD18 READ_MULT_BLOCK with argument data address */
00974     sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
00975   }
00976   else
00977   {
00978     /* Send CMD17 READ_SINGLE_BLOCK */
00979     sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
00980   }
00981
00982   sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
00983   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
00984
00985   /* Check for error conditions */
00986   if(NumberOfBlocks > 1U)
00987   {
00988     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
00989   }
00990   else
00991   {
00992     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
00993   }
00994
00995   /* Update the SD transfer error in SD handle */
00996   hsd->SdTransferErr = errorstate;
00997
00998   return errorstate;
00999 }
01000
01001
01002 /**
01003   * @brief  Writes block(s) to a specified address in a card. The Data transfer
01004   *         is managed by DMA mode.
01005   * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
01006   *         to check the completion of the write process (by SD current status polling).
01007   * @param  hsd: SD handle
01008   * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
01009   * @param  WriteAddr: Address from where data is to be read
01010   * @param  BlockSize: the SD card Data block size
01011   * @note   BlockSize must be 512 bytes.
01012   * @param  NumberOfBlocks: Number of blocks to write
01013   * @retval SD Card error state
01014   */
01015 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
01016 {
01017   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
01018   SDIO_DataInitTypeDef sdio_datainitstructure;
01019   HAL_SD_ErrorTypedef errorstate = SD_OK;
01020
01021   /* Initialize data control register */
01022   hsd->Instance->DCTRL = 0U;
01023
01024   /* Initialize handle flags */
01025   hsd->SdTransferCplt  = 0U;
01026   hsd->DmaTransferCplt = 0U;
01027   hsd->SdTransferErr   = SD_OK;
01028
01029   /* Initialize SD Write operation */
01030   if(NumberOfBlocks > 1U)
01031   {
01032     hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
01033   }
01034   else
01035   {
01036     hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
01037   }
01038
01039   /* Enable transfer interrupts */
01040 #ifdef SDIO_STA_STBITERR
01041   __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
01042                                 SDIO_IT_DTIMEOUT |\
01043                                 SDIO_IT_DATAEND  |\
01044                                 SDIO_IT_TXUNDERR |\
01045                                 SDIO_IT_STBITERR));
01046 #else /* SDIO_STA_STBITERR not defined */
01047   __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
01048                                 SDIO_IT_DTIMEOUT |\
01049                                 SDIO_IT_DATAEND  |\
01050                                 SDIO_IT_TXUNDERR));
01051 #endif /* SDIO_STA_STBITERR */
01052
01053   /* Configure DMA user callbacks */
01054   hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
01055   hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
01056
01057   /* Enable the DMA Stream */
01058   HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
01059
01060   /* Enable SDIO DMA transfer */
01061   __HAL_SD_SDIO_DMA_ENABLE();
01062
01063   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01064   {
01065     BlockSize = 512U;
01066     WriteAddr /= 512U;
01067   }
01068
01069   /* Set Block Size for Card */
01070   sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
01071   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01072   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
01073   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
01074   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
01075   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01076
01077   /* Check for error conditions */
01078   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01079
01080   if (errorstate != SD_OK)
01081   {
01082     return errorstate;
01083   }
01084
01085   /* Check number of blocks command */
01086   if(NumberOfBlocks <= 1U)
01087   {
01088     /* Send CMD24 WRITE_SINGLE_BLOCK */
01089     sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
01090   }
01091   else
01092   {
01093     /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
01094     sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
01095   }
01096
01097   sdio_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
01098   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01099
01100   /* Check for error conditions */
01101   if(NumberOfBlocks > 1U)
01102   {
01103     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
01104   }
01105   else
01106   {
01107     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
01108   }
01109
01110   if (errorstate != SD_OK)
01111   {
01112     return errorstate;
01113   }
01114
01115   /* Configure the SD DPSM (Data Path State Machine) */
01116   sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
01117   sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
01118   sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
01119   sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
01120   sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
01121   sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
01122   SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
01123
01124   hsd->SdTransferErr = errorstate;
01125
01126   return errorstate;
01127 }
01128
01129 /**
01130   * @brief  This function waits until the SD DMA data read transfer is finished.
01131   *         This API should be called after HAL_SD_ReadBlocks_DMA() function
01132   *         to insure that all data sent by the card is already transferred by the
01133   *         DMA controller.
01134   * @param  hsd: SD handle
01135   * @param  Timeout: Timeout duration
01136   * @retval SD Card error state
01137   */
01138 HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
01139 {
01140   HAL_SD_ErrorTypedef errorstate = SD_OK;
01141   uint32_t timeout = Timeout;
01142   uint32_t tmp1, tmp2;
01143   HAL_SD_ErrorTypedef tmp3;
01144
01145   /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
01146   tmp1 = hsd->DmaTransferCplt;
01147   tmp2 = hsd->SdTransferCplt;
01148   tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01149
01150   while ((tmp1 == 0U) && (tmp2 == 0U) && (tmp3 == SD_OK) && (timeout > 0U))
01151   {
01152     tmp1 = hsd->DmaTransferCplt;
01153     tmp2 = hsd->SdTransferCplt;
01154     tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01155     timeout--;
01156   }
01157
01158   timeout = Timeout;
01159
01160   /* Wait until the Rx transfer is no longer active */
01161   while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0U))
01162   {
01163     timeout--;
01164   }
01165
01166   /* Send stop command in multiblock read */
01167   if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
01168   {
01169     errorstate = HAL_SD_StopTransfer(hsd);
01170   }
01171
01172   if ((timeout == 0U) && (errorstate == SD_OK))
01173   {
01174     errorstate = SD_DATA_TIMEOUT;
01175   }
01176
01177   /* Clear all the static flags */
01178   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01179
01180   /* Return error state */
01181   if (hsd->SdTransferErr != SD_OK)
01182   {
01183     return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
01184   }
01185
01186   return errorstate;
01187 }
01188
01189 /**
01190   * @brief  This function waits until the SD DMA data write transfer is finished.
01191   *         This API should be called after HAL_SD_WriteBlocks_DMA() function
01192   *         to insure that all data sent by the card is already transferred by the
01193   *         DMA controller.
01194   * @param  hsd: SD handle
01195   * @param  Timeout: Timeout duration
01196   * @retval SD Card error state
01197   */
01198 HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
01199 {
01200   HAL_SD_ErrorTypedef errorstate = SD_OK;
01201   uint32_t timeout = Timeout;
01202   uint32_t tmp1, tmp2;
01203   HAL_SD_ErrorTypedef tmp3;
01204
01205   /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
01206   tmp1 = hsd->DmaTransferCplt;
01207   tmp2 = hsd->SdTransferCplt;
01208   tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01209
01210   while ((tmp1 == 0U) && (tmp2 == 0U) && (tmp3 == SD_OK) && (timeout > 0U))
01211   {
01212     tmp1 = hsd->DmaTransferCplt;
01213     tmp2 = hsd->SdTransferCplt;
01214     tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01215     timeout--;
01216   }
01217
01218   timeout = Timeout;
01219
01220   /* Wait until the Tx transfer is no longer active */
01221   while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT))  && (timeout > 0U))
01222   {
01223     timeout--;
01224   }
01225
01226   /* Send stop command in multiblock write */
01227   if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
01228   {
01229     errorstate = HAL_SD_StopTransfer(hsd);
01230   }
01231
01232   if ((timeout == 0U) && (errorstate == SD_OK))
01233   {
01234     errorstate = SD_DATA_TIMEOUT;
01235   }
01236
01237   /* Clear all the static flags */
01238   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01239
01240   /* Return error state */
01241   if (hsd->SdTransferErr != SD_OK)
01242   {
01243     return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
01244   }
01245
01246   /* Wait until write is complete */
01247   while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
01248   {
01249   }
01250
01251   return errorstate;
01252 }
01253
01254 /**
01255   * @brief  Erases the specified memory area of the given SD card.
01256   * @param  hsd: SD handle
01257   * @param  startaddr: Start byte address
01258   * @param  endaddr: End byte address
01259   * @retval SD Card error state
01260   */
01261 HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
01262 {
01263   HAL_SD_ErrorTypedef errorstate = SD_OK;
01264   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
01265
01266   uint32_t delay         = 0U;
01267   __IO uint32_t maxdelay = 0U;
01268   uint8_t cardstate      = 0U;
01269
01270   /* Check if the card command class supports erase command */
01271   if (((hsd->CSD[1U] >> 20U) & SD_CCCC_ERASE) == 0U)
01272   {
01273     errorstate = SD_REQUEST_NOT_APPLICABLE;
01274
01275     return errorstate;
01276   }
01277
01278   /* Get max delay value */
01279   maxdelay = 120000U / (((hsd->Instance->CLKCR) & 0xFFU) + 2U);
01280
01281   if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
01282   {
01283     errorstate = SD_LOCK_UNLOCK_FAILED;
01284
01285     return errorstate;
01286   }
01287
01288   /* Get start and end block for high capacity cards */
01289   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01290   {
01291     startaddr /= 512U;
01292     endaddr   /= 512U;
01293   }
01294
01295   /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
01296   if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
01297     (hsd->CardType == HIGH_CAPACITY_SD_CARD))
01298   {
01299     /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
01300     sdio_cmdinitstructure.Argument         =(uint32_t)startaddr;
01301     sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
01302     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
01303     sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
01304     sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
01305     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01306
01307     /* Check for error conditions */
01308     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
01309
01310     if (errorstate != SD_OK)
01311     {
01312       return errorstate;
01313     }
01314
01315     /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
01316     sdio_cmdinitstructure.Argument         = (uint32_t)endaddr;
01317     sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
01318     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01319
01320     /* Check for error conditions */
01321     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
01322
01323     if (errorstate != SD_OK)
01324     {
01325       return errorstate;
01326     }
01327   }
01328
01329   /* Send CMD38 ERASE */
01330   sdio_cmdinitstructure.Argument         = 0U;
01331   sdio_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
01332   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01333
01334   /* Check for error conditions */
01335   errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
01336
01337   if (errorstate != SD_OK)
01338   {
01339     return errorstate;
01340   }
01341
01342   for (; delay < maxdelay; delay++)
01343   {
01344   }
01345
01346   /* Wait until the card is in programming state */
01347   errorstate = SD_IsCardProgramming(hsd, &cardstate);
01348
01349   delay = SD_DATATIMEOUT;
01350
01351   while ((delay > 0U) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
01352   {
01353     errorstate = SD_IsCardProgramming(hsd, &cardstate);
01354     delay--;
01355   }
01356
01357   return errorstate;
01358 }
01359
01360 /**
01361   * @brief  This function handles SD card interrupt request.
01362   * @param  hsd: SD handle
01363   * @retval None
01364   */
01365 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
01366 {
01367   /* Check for SDIO interrupt flags */
01368   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND))
01369   {
01370     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND);
01371
01372     /* SD transfer is complete */
01373     hsd->SdTransferCplt = 1U;
01374
01375     /* No transfer error */
01376     hsd->SdTransferErr  = SD_OK;
01377
01378     HAL_SD_XferCpltCallback(hsd);
01379   }
01380   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL))
01381   {
01382     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
01383
01384     hsd->SdTransferErr = SD_DATA_CRC_FAIL;
01385
01386     HAL_SD_XferErrorCallback(hsd);
01387
01388   }
01389   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT))
01390   {
01391     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
01392
01393     hsd->SdTransferErr = SD_DATA_TIMEOUT;
01394
01395     HAL_SD_XferErrorCallback(hsd);
01396   }
01397   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR))
01398   {
01399     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
01400
01401     hsd->SdTransferErr = SD_RX_OVERRUN;
01402
01403     HAL_SD_XferErrorCallback(hsd);
01404   }
01405   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR))
01406   {
01407     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
01408
01409     hsd->SdTransferErr = SD_TX_UNDERRUN;
01410
01411     HAL_SD_XferErrorCallback(hsd);
01412   }
01413 #ifdef SDIO_STA_STBITERR
01414   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
01415   {
01416     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
01417
01418     hsd->SdTransferErr = SD_START_BIT_ERR;
01419
01420     HAL_SD_XferErrorCallback(hsd);
01421   }
01422 #endif /* SDIO_STA_STBITERR */
01423   else
01424   {
01425     /* No error flag set */
01426   }
01427
01428   /* Disable all SDIO peripheral interrupt sources */
01429 #ifdef SDIO_STA_STBITERR
01430   __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND  |\
01431                                 SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
01432                                 SDIO_IT_RXOVERR  | SDIO_IT_STBITERR);
01433 #else /* SDIO_STA_STBITERR not defined */
01434   __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND  |\
01435                                 SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
01436                                 SDIO_IT_RXOVERR);
01437 #endif /* SDIO_STA_STBITERR */
01438 }
01439
01440
01441 /**
01442   * @brief  SD end of transfer callback.
01443   * @param  hsd: SD handle
01444   * @retval None
01445   */
01446 __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
01447 {
01448   /* Prevent unused argument(s) compilation warning */
01449   UNUSED(hsd);
01450   /* NOTE : This function Should not be modified, when the callback is needed,
01451             the HAL_SD_XferCpltCallback could be implemented in the user file
01452    */
01453 }
01454
01455 /**
01456   * @brief  SD Transfer Error callback.
01457   * @param  hsd: SD handle
01458   * @retval None
01459   */
01460 __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
01461 {
01462   /* Prevent unused argument(s) compilation warning */
01463   UNUSED(hsd);
01464   /* NOTE : This function Should not be modified, when the callback is needed,
01465             the HAL_SD_XferErrorCallback could be implemented in the user file
01466    */
01467 }
01468
01469 /**
01470   * @brief  SD Transfer complete Rx callback in non blocking mode.
01471   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01472   *                the configuration information for the specified DMA module.
01473   * @retval None
01474   */
01475 __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
01476 {
01477   /* Prevent unused argument(s) compilation warning */
01478   UNUSED(hdma);
01479   /* NOTE : This function Should not be modified, when the callback is needed,
01480             the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
01481    */
01482 }
01483
01484 /**
01485   * @brief  SD DMA transfer complete Rx error callback.
01486   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01487   *                the configuration information for the specified DMA module.
01488   * @retval None
01489   */
01490 __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
01491 {
01492   /* Prevent unused argument(s) compilation warning */
01493   UNUSED(hdma);
01494   /* NOTE : This function Should not be modified, when the callback is needed,
01495             the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
01496    */
01497 }
01498
01499 /**
01500   * @brief  SD Transfer complete Tx callback in non blocking mode.
01501   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01502   *                the configuration information for the specified DMA module.
01503   * @retval None
01504   */
01505 __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
01506 {
01507   /* Prevent unused argument(s) compilation warning */
01508   UNUSED(hdma);
01509   /* NOTE : This function Should not be modified, when the callback is needed,
01510             the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
01511    */
01512 }
01513
01514 /**
01515   * @brief  SD DMA transfer complete error Tx callback.
01516   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01517   *                the configuration information for the specified DMA module.
01518   * @retval None
01519   */
01520 __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
01521 {
01522   /* Prevent unused argument(s) compilation warning */
01523   UNUSED(hdma);
01524   /* NOTE : This function Should not be modified, when the callback is needed,
01525             the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
01526    */
01527 }
01528
01529 /**
01530   * @}
01531   */
01532
01533 /** @addtogroup SD_Exported_Functions_Group3
01534  *  @brief   management functions
01535  *
01536 @verbatim
01537   ==============================================================================
01538                       ##### Peripheral Control functions #####
01539   ==============================================================================
01540   [..]
01541     This subsection provides a set of functions allowing to control the SD card
01542     operations.
01543
01544 @endverbatim
01545   * @{
01546   */
01547
01548 /**
01549   * @brief  Returns information about specific card.
01550   * @param  hsd: SD handle
01551   * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that
01552   *         contains all SD cardinformation
01553   * @retval SD Card error state
01554   */
01555 HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
01556 {
01557   HAL_SD_ErrorTypedef errorstate = SD_OK;
01558   uint32_t tmp = 0U;
01559
01560   pCardInfo->CardType = (uint8_t)(hsd->CardType);
01561   pCardInfo->RCA      = (uint16_t)(hsd->RCA);
01562
01563   /* Byte 0 */
01564   tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U;
01565   pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0U) >> 6U);
01566   pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
01567   pCardInfo->SD_csd.Reserved1      = tmp & 0x03U;
01568
01569   /* Byte 1 */
01570   tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U;
01571   pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
01572
01573   /* Byte 2 */
01574   tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U;
01575   pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
01576
01577   /* Byte 3 */
01578   tmp = hsd->CSD[0U] & 0x000000FFU;
01579   pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
01580
01581   /* Byte 4 */
01582   tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U;
01583   pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4U);
01584
01585   /* Byte 5 */
01586   tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U;
01587   pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4U);
01588   pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0FU);
01589
01590   /* Byte 6 */
01591   tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U;
01592   pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80U) >> 7U);
01593   pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
01594   pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
01595   pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10U) >> 4U);
01596   pCardInfo->SD_csd.Reserved2       = 0U; /*!< Reserved */
01597
01598   if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
01599   {
01600     pCardInfo->SD_csd.DeviceSize = (tmp & 0x03U) << 10U;
01601
01602     /* Byte 7 */
01603     tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
01604     pCardInfo->SD_csd.DeviceSize |= (tmp) << 2U;
01605
01606     /* Byte 8 */
01607     tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
01608     pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0U) >> 6U;
01609
01610     pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
01611     pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07U);
01612
01613     /* Byte 9 */
01614     tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
01615     pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
01616     pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
01617     pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03U) << 1U;
01618     /* Byte 10 */
01619     tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
01620     pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80U) >> 7U;
01621
01622     pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1U) ;
01623     pCardInfo->CardCapacity *= (1U << (pCardInfo->SD_csd.DeviceSizeMul + 2U));
01624     pCardInfo->CardBlockSize = 1U << (pCardInfo->SD_csd.RdBlockLen);
01625     pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
01626   }
01627   else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01628   {
01629     /* Byte 7 */
01630     tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
01631     pCardInfo->SD_csd.DeviceSize = (tmp & 0x3FU) << 16U;
01632
01633     /* Byte 8 */
01634     tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
01635
01636     pCardInfo->SD_csd.DeviceSize |= (tmp << 8U);
01637
01638     /* Byte 9 */
01639     tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
01640
01641     pCardInfo->SD_csd.DeviceSize |= (tmp);
01642
01643     /* Byte 10 */
01644     tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
01645
01646     pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1U)) * 512U * 1024U);
01647     pCardInfo->CardBlockSize = 512U;
01648   }
01649   else
01650   {
01651     /* Not supported card type */
01652     errorstate = SD_ERROR;
01653   }
01654
01655   pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40U) >> 6U;
01656   pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3FU) << 1U;
01657
01658   /* Byte 11 */
01659   tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU);
01660   pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80U) >> 7U;
01661   pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7FU);
01662
01663   /* Byte 12 */
01664   tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U);
01665   pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80U) >> 7U;
01666   pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60U) >> 5U;
01667   pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1CU) >> 2U;
01668   pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03U) << 2U;
01669
01670   /* Byte 13 */
01671   tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U);
01672   pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0U) >> 6U;
01673   pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
01674   pCardInfo->SD_csd.Reserved3           = 0U;
01675   pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01U);
01676
01677   /* Byte 14 */
01678   tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U);
01679   pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80U) >> 7U;
01680   pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40U) >> 6U;
01681   pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20U) >> 5U;
01682   pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10U) >> 4U;
01683   pCardInfo->SD_csd.FileFormat       = (tmp & 0x0CU) >> 2U;
01684   pCardInfo->SD_csd.ECC              = (tmp & 0x03U);
01685
01686   /* Byte 15 */
01687   tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU);
01688   pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFEU) >> 1U;
01689   pCardInfo->SD_csd.Reserved4 = 1U;
01690
01691   /* Byte 0 */
01692   tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U);
01693   pCardInfo->SD_cid.ManufacturerID = tmp;
01694
01695   /* Byte 1 */
01696   tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U);
01697   pCardInfo->SD_cid.OEM_AppliID = tmp << 8U;
01698
01699   /* Byte 2 */
01700   tmp = (uint8_t)((hsd->CID[0U] & 0x0000FF00U) >> 8U);
01701   pCardInfo->SD_cid.OEM_AppliID |= tmp;
01702
01703   /* Byte 3 */
01704   tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU);
01705   pCardInfo->SD_cid.ProdName1 = tmp << 24U;
01706
01707   /* Byte 4 */
01708   tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U);
01709   pCardInfo->SD_cid.ProdName1 |= tmp << 16U;
01710
01711   /* Byte 5 */
01712   tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U);
01713   pCardInfo->SD_cid.ProdName1 |= tmp << 8U;
01714
01715   /* Byte 6 */
01716   tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U);
01717   pCardInfo->SD_cid.ProdName1 |= tmp;
01718
01719   /* Byte 7 */
01720   tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU);
01721   pCardInfo->SD_cid.ProdName2 = tmp;
01722
01723   /* Byte 8 */
01724   tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U);
01725   pCardInfo->SD_cid.ProdRev = tmp;
01726
01727   /* Byte 9 */
01728   tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U);
01729   pCardInfo->SD_cid.ProdSN = tmp << 24U;
01730
01731   /* Byte 10 */
01732   tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U);
01733   pCardInfo->SD_cid.ProdSN |= tmp << 16U;
01734
01735   /* Byte 11 */
01736   tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU);
01737   pCardInfo->SD_cid.ProdSN |= tmp << 8U;
01738
01739   /* Byte 12 */
01740   tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U);
01741   pCardInfo->SD_cid.ProdSN |= tmp;
01742
01743   /* Byte 13 */
01744   tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U);
01745   pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0U) >> 4U;
01746   pCardInfo->SD_cid.ManufactDate = (tmp & 0x0FU) << 8U;
01747
01748   /* Byte 14 */
01749   tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U);
01750   pCardInfo->SD_cid.ManufactDate |= tmp;
01751
01752   /* Byte 15 */
01753   tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU);
01754   pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFEU) >> 1U;
01755   pCardInfo->SD_cid.Reserved2 = 1U;
01756
01757   return errorstate;
01758 }
01759
01760 /**
01761   * @brief  Enables wide bus operation for the requested card if supported by
01762   *         card.
01763   * @param  hsd: SD handle
01764   * @param  WideMode: Specifies the SD card wide bus mode
01765   *          This parameter can be one of the following values:
01766   *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
01767   *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
01768   *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
01769   * @retval SD Card error state
01770   */
01771 HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
01772 {
01773   HAL_SD_ErrorTypedef errorstate = SD_OK;
01774   SDIO_InitTypeDef tmpinit;
01775
01776   /* MMC Card does not support this feature */
01777   if (hsd->CardType == MULTIMEDIA_CARD)
01778   {
01779     errorstate = SD_UNSUPPORTED_FEATURE;
01780
01781     return errorstate;
01782   }
01783   else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
01784     (hsd->CardType == HIGH_CAPACITY_SD_CARD))
01785   {
01786     if (WideMode == SDIO_BUS_WIDE_8B)
01787     {
01788       errorstate = SD_UNSUPPORTED_FEATURE;
01789     }
01790     else if (WideMode == SDIO_BUS_WIDE_4B)
01791     {
01792       errorstate = SD_WideBus_Enable(hsd);
01793     }
01794     else if (WideMode == SDIO_BUS_WIDE_1B)
01795     {
01796       errorstate = SD_WideBus_Disable(hsd);
01797     }
01798     else
01799     {
01800       /* WideMode is not a valid argument*/
01801       errorstate = SD_INVALID_PARAMETER;
01802     }
01803
01804     if (errorstate == SD_OK)
01805     {
01806       /* Configure the SDIO peripheral */
01807       tmpinit.ClockEdge           = hsd->Init.ClockEdge;
01808       tmpinit.ClockBypass         = hsd->Init.ClockBypass;
01809       tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;
01810       tmpinit.BusWide             = WideMode;
01811       tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
01812       tmpinit.ClockDiv            = hsd->Init.ClockDiv;
01813       SDIO_Init(hsd->Instance, tmpinit);
01814     }
01815   }
01816
01817   return errorstate;
01818 }
01819
01820 /**
01821   * @brief  Aborts an ongoing data transfer.
01822   * @param  hsd: SD handle
01823   * @retval SD Card error state
01824   */
01825 HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
01826 {
01827   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
01828   HAL_SD_ErrorTypedef errorstate = SD_OK;
01829
01830   /* Send CMD12 STOP_TRANSMISSION  */
01831   sdio_cmdinitstructure.Argument         = 0U;
01832   sdio_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
01833   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
01834   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
01835   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
01836   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01837
01838   /* Check for error conditions */
01839   errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
01840
01841   return errorstate;
01842 }
01843
01844 /**
01845   * @brief  Switches the SD card to High Speed mode.
01846   *         This API must be used after "Transfer State"
01847   * @note   This operation should be followed by the configuration
01848   *         of PLL to have SDIOCK clock between 67 and 75 MHz
01849   * @param  hsd: SD handle
01850   * @retval SD Card error state
01851   */
01852 HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
01853 {
01854   HAL_SD_ErrorTypedef errorstate = SD_OK;
01855   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
01856   SDIO_DataInitTypeDef sdio_datainitstructure;
01857
01858   uint8_t SD_hs[64U]  = {0U};
01859   uint32_t SD_scr[2U] = {0U, 0U};
01860   uint32_t SD_SPEC    = 0U;
01861   uint32_t count = 0U, *tempbuff = (uint32_t *)SD_hs;
01862
01863   /* Initialize the Data control register */
01864   hsd->Instance->DCTRL = 0U;
01865
01866   /* Get SCR Register */
01867   errorstate = SD_FindSCR(hsd, SD_scr);
01868
01869   if (errorstate != SD_OK)
01870   {
01871     return errorstate;
01872   }
01873
01874   /* Test the Version supported by the card*/
01875   SD_SPEC = (SD_scr[1U]  & 0x01000000U) | (SD_scr[1U]  & 0x02000000U);
01876
01877   if (SD_SPEC != SD_ALLZERO)
01878   {
01879     /* Set Block Size for Card */
01880     sdio_cmdinitstructure.Argument         = (uint32_t)64U;
01881     sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01882     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
01883     sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
01884     sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
01885     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01886
01887     /* Check for error conditions */
01888     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01889
01890     if (errorstate != SD_OK)
01891     {
01892       return errorstate;
01893     }
01894
01895     /* Configure the SD DPSM (Data Path State Machine) */
01896     sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
01897     sdio_datainitstructure.DataLength    = 64U;
01898     sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
01899     sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
01900     sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
01901     sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
01902     SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
01903
01904     /* Send CMD6 switch mode */
01905     sdio_cmdinitstructure.Argument         = 0x80FFFF01U;
01906     sdio_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
01907     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
01908
01909     /* Check for error conditions */
01910     errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
01911
01912     if (errorstate != SD_OK)
01913     {
01914       return errorstate;
01915     }
01916 #ifdef SDIO_STA_STBITERR
01917     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
01918 #else /* SDIO_STA_STBITERR */
01919     while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
01920 #endif /* SDIO_STA_STBITERR */
01921     {
01922       if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
01923       {
01924         for (count = 0U; count < 8U; count++)
01925         {
01926           *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
01927         }
01928
01929         tempbuff += 8U;
01930       }
01931     }
01932
01933     if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
01934     {
01935       __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
01936
01937       errorstate = SD_DATA_TIMEOUT;
01938
01939       return errorstate;
01940     }
01941     else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
01942     {
01943       __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
01944
01945       errorstate = SD_DATA_CRC_FAIL;
01946
01947       return errorstate;
01948     }
01949     else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
01950     {
01951       __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
01952
01953       errorstate = SD_RX_OVERRUN;
01954
01955       return errorstate;
01956     }
01957 #ifdef SDIO_STA_STBITERR
01958     else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
01959     {
01960       __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
01961
01962       errorstate = SD_START_BIT_ERR;
01963
01964       return errorstate;
01965     }
01966 #endif /* SDIO_STA_STBITERR */
01967     else
01968     {
01969       /* No error flag set */
01970     }
01971
01972     count = SD_DATATIMEOUT;
01973
01974     while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0U))
01975     {
01976       *tempbuff = SDIO_ReadFIFO(hsd->Instance);
01977       tempbuff++;
01978       count--;
01979     }
01980
01981     /* Clear all the static flags */
01982     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01983
01984     /* Test if the switch mode HS is ok */
01985     if ((SD_hs[13U]& 2U) != 2U)
01986     {
01987       errorstate = SD_UNSUPPORTED_FEATURE;
01988     }
01989   }
01990
01991   return errorstate;
01992 }
01993
01994 /**
01995   * @}
01996   */
01997
01998 /** @addtogroup SD_Exported_Functions_Group4
01999  *  @brief   Peripheral State functions
02000  *
02001 @verbatim
02002   ==============================================================================
02003                       ##### Peripheral State functions #####
02004   ==============================================================================
02005   [..]
02006     This subsection permits to get in runtime the status of the peripheral
02007     and the data flow.
02008
02009 @endverbatim
02010   * @{
02011   */
02012
02013 /**
02014   * @brief  Returns the current SD card's status.
02015   * @param  hsd: SD handle
02016   * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
02017   *         SD Status register)
02018   * @retval SD Card error state
02019   */
02020 HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
02021 {
02022   SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
02023   SDIO_DataInitTypeDef sdio_datainitstructure;
02024   HAL_SD_ErrorTypedef errorstate = SD_OK;
02025   uint32_t count = 0U;
02026
02027   /* Check SD response */
02028   if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
02029   {
02030     errorstate = SD_LOCK_UNLOCK_FAILED;
02031
02032     return errorstate;
02033   }
02034
02035   /* Set block size for card if it is not equal to current block size for card */
02036   sdio_cmdinitstructure.Argument         = 64U;
02037   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
02038   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
02039   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
02040   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
02041   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02042
02043   /* Check for error conditions */
02044   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
02045
02046   if (errorstate != SD_OK)
02047   {
02048     return errorstate;
02049   }
02050
02051   /* Send CMD55 */
02052   sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
02053   sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
02054   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02055
02056   /* Check for error conditions */
02057   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
02058
02059   if (errorstate != SD_OK)
02060   {
02061     return errorstate;
02062   }
02063
02064   /* Configure the SD DPSM (Data Path State Machine) */
02065   sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
02066   sdio_datainitstructure.DataLength    = 64U;
02067   sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
02068   sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
02069   sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
02070   sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
02071   SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
02072
02073   /* Send ACMD13 (SD_APP_STATUS)  with argument as card's RCA */
02074   sdio_cmdinitstructure.Argument         = 0U;
02075   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;
02076   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02077
02078   /* Check for error conditions */
02079   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
02080
02081   if (errorstate != SD_OK)
02082   {
02083     return errorstate;
02084   }
02085
02086   /* Get status data */
02087 #ifdef SDIO_STA_STBITERR
02088   while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
02089 #else /* SDIO_STA_STBITERR not defined */
02090   while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
02091 #endif /* SDIO_STA_STBITERR */
02092   {
02093     if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
02094     {
02095       for (count = 0U; count < 8U; count++)
02096       {
02097         *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
02098       }
02099
02100       pSDstatus += 8U;
02101     }
02102   }
02103
02104   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
02105   {
02106     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
02107
02108     errorstate = SD_DATA_TIMEOUT;
02109
02110     return errorstate;
02111   }
02112   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
02113   {
02114     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
02115
02116     errorstate = SD_DATA_CRC_FAIL;
02117
02118     return errorstate;
02119   }
02120   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
02121   {
02122     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
02123
02124     errorstate = SD_RX_OVERRUN;
02125
02126     return errorstate;
02127   }
02128 #ifdef SDIO_STA_STBITERR
02129   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
02130   {
02131     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
02132
02133     errorstate = SD_START_BIT_ERR;
02134
02135     return errorstate;
02136   }
02137 #endif /* SDIO_STA_STBITERR */
02138   else
02139   {
02140     /* No error flag set */
02141   }
02142
02143   count = SD_DATATIMEOUT;
02144   while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0U))
02145   {
02146     *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
02147     pSDstatus++;
02148     count--;
02149   }
02150
02151   /* Clear all the static status flags*/
02152   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02153
02154   return errorstate;
02155 }
02156
02157 /**
02158   * @brief  Gets the current sd card data status.
02159   * @param  hsd: SD handle
02160   * @retval Data Transfer state
02161   */
02162 HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
02163 {
02164   HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
02165
02166   /* Get SD card state */
02167   cardstate = SD_GetState(hsd);
02168
02169   /* Find SD status according to card state*/
02170   if (cardstate == SD_CARD_TRANSFER)
02171   {
02172     return SD_TRANSFER_OK;
02173   }
02174   else if(cardstate == SD_CARD_ERROR)
02175   {
02176     return SD_TRANSFER_ERROR;
02177   }
02178   else
02179   {
02180     return SD_TRANSFER_BUSY;
02181   }
02182 }
02183
02184 /**
02185   * @brief  Gets the SD card status.
02186   * @param  hsd: SD handle
02187   * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
02188   *         will contain the SD card status information
02189   * @retval SD Card error state
02190   */
02191 HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
02192 {
02193   HAL_SD_ErrorTypedef errorstate = SD_OK;
02194   uint32_t tmp = 0U;
02195   uint32_t sd_status[16U];
02196
02197   errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
02198
02199   if (errorstate  != SD_OK)
02200   {
02201     return errorstate;
02202   }
02203
02204   /* Byte 0 */
02205   tmp = (sd_status[0U] & 0xC0U) >> 6U;
02206   pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
02207
02208   /* Byte 0 */
02209   tmp = (sd_status[0U] & 0x20U) >> 5U;
02210   pCardStatus->SECURED_MODE = (uint8_t)tmp;
02211
02212   /* Byte 2 */
02213   tmp = (sd_status[2U] & 0xFFU);
02214   pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8U);
02215
02216   /* Byte 3 */
02217   tmp = (sd_status[3U] & 0xFFU);
02218   pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
02219
02220   /* Byte 4 */
02221   tmp = (sd_status[4U] & 0xFFU);
02222   pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24U);
02223
02224   /* Byte 5 */
02225   tmp = (sd_status[5U] & 0xFFU);
02226   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16U);
02227
02228   /* Byte 6 */
02229   tmp = (sd_status[6U] & 0xFFU);
02230   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8U);
02231
02232   /* Byte 7 */
02233   tmp = (sd_status[7U] & 0xFFU);
02234   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
02235
02236   /* Byte 8 */
02237   tmp = (sd_status[8U] & 0xFFU);
02238   pCardStatus->SPEED_CLASS = (uint8_t)tmp;
02239
02240   /* Byte 9 */
02241   tmp = (sd_status[9U] & 0xFFU);
02242   pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
02243
02244   /* Byte 10 */
02245   tmp = (sd_status[10U] & 0xF0U) >> 4U;
02246   pCardStatus->AU_SIZE = (uint8_t)tmp;
02247
02248   /* Byte 11 */
02249   tmp = (sd_status[11U] & 0xFFU);
02250   pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8U);
02251
02252   /* Byte 12 */
02253   tmp = (sd_status[12U] & 0xFFU);
02254   pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
02255
02256   /* Byte 13 */
02257   tmp = (sd_status[13U] & 0xFCU) >> 2U;
02258   pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
02259
02260   /* Byte 13 */
02261   tmp = (sd_status[13U] & 0x3U);
02262   pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
02263
02264   return errorstate;
02265 }
02266
02267 /**
02268   * @}
02269   */
02270
02271 /**
02272   * @}
02273   */
02274
02275 /* Private function ----------------------------------------------------------*/
02276 /** @addtogroup SD_Private_Functions
02277   * @{
02278   */
02279
02280 /**
02281   * @brief  SD DMA transfer complete Rx callback.
02282   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02283   *                the configuration information for the specified DMA module.
02284   * @retval None
02285   */
02286 static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
02287 {
02288   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02289
02290   /* DMA transfer is complete */
02291   hsd->DmaTransferCplt = 1U;
02292
02293   /* Wait until SD transfer is complete */
02294   while(hsd->SdTransferCplt == 0U)
02295   {
02296   }
02297
02298   /* Disable the DMA channel */
02299   HAL_DMA_Abort(hdma);
02300
02301   /* Transfer complete user callback */
02302   HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
02303 }
02304
02305 /**
02306   * @brief  SD DMA transfer Error Rx callback.
02307   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02308   *                the configuration information for the specified DMA module.
02309   * @retval None
02310   */
02311 static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
02312 {
02313   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02314
02315   /* Transfer complete user callback */
02316   HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
02317 }
02318
02319 /**
02320   * @brief  SD DMA transfer complete Tx callback.
02321   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02322   *                the configuration information for the specified DMA module.
02323   * @retval None
02324   */
02325 static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
02326 {
02327   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02328
02329   /* DMA transfer is complete */
02330   hsd->DmaTransferCplt = 1U;
02331
02332   /* Wait until SD transfer is complete */
02333   while(hsd->SdTransferCplt == 0U)
02334   {
02335   }
02336
02337   /* Disable the DMA channel */
02338   HAL_DMA_Abort(hdma);
02339
02340   /* Transfer complete user callback */
02341   HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
02342 }
02343
02344 /**
02345   * @brief  SD DMA transfer Error Tx callback.
02346   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02347   *                the configuration information for the specified DMA module.
02348   * @retval None
02349   */
02350 static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
02351 {
02352   SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02353
02354   /* Transfer complete user callback */
02355   HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
02356 }
02357
02358 /**
02359   * @brief  Returns the SD current state.
02360   * @param  hsd: SD handle
02361   * @retval SD card current state
02362   */
02363 static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
02364 {
02365   uint32_t resp1 = 0U;
02366
02367   if (SD_SendStatus(hsd, &resp1) != SD_OK)
02368   {
02369     return SD_CARD_ERROR;
02370   }
02371   else
02372   {
02373     return (HAL_SD_CardStateTypedef)((resp1 >> 9U) & 0x0FU);
02374   }
02375 }
02376
02377 /**
02378   * @brief  Initializes all cards or single card as the case may be Card(s) come
02379   *         into standby state.
02380   * @param  hsd: SD handle
02381   * @retval SD Card error state
02382   */
02383 static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
02384 {
02385   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
02386   HAL_SD_ErrorTypedef errorstate = SD_OK;
02387   uint16_t sd_rca = 1U;
02388
02389   if(SDIO_GetPowerState(hsd->Instance) == 0U) /* Power off */
02390   {
02391     errorstate = SD_REQUEST_NOT_APPLICABLE;
02392
02393     return errorstate;
02394   }
02395
02396   if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
02397   {
02398     /* Send CMD2 ALL_SEND_CID */
02399     sdio_cmdinitstructure.Argument         = 0U;
02400     sdio_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
02401     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
02402     sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
02403     sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
02404     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02405
02406     /* Check for error conditions */
02407     errorstate = SD_CmdResp2Error(hsd);
02408
02409     if(errorstate != SD_OK)
02410     {
02411       return errorstate;
02412     }
02413
02414     /* Get Card identification number data */
02415     hsd->CID[0U] = SDIO_GetResponse(SDIO_RESP1);
02416     hsd->CID[1U] = SDIO_GetResponse(SDIO_RESP2);
02417     hsd->CID[2U] = SDIO_GetResponse(SDIO_RESP3);
02418     hsd->CID[3U] = SDIO_GetResponse(SDIO_RESP4);
02419   }
02420
02421   if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
02422      (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
02423   {
02424     /* Send CMD3 SET_REL_ADDR with argument 0 */
02425     /* SD Card publishes its RCA. */
02426     sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
02427     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
02428     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02429
02430     /* Check for error conditions */
02431     errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
02432
02433     if(errorstate != SD_OK)
02434     {
02435       return errorstate;
02436     }
02437   }
02438
02439   if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
02440   {
02441     /* Get the SD card RCA */
02442     hsd->RCA = sd_rca;
02443
02444     /* Send CMD9 SEND_CSD with argument as card's RCA */
02445     sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
02446     sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
02447     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
02448     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02449
02450     /* Check for error conditions */
02451     errorstate = SD_CmdResp2Error(hsd);
02452
02453     if(errorstate != SD_OK)
02454     {
02455       return errorstate;
02456     }
02457
02458     /* Get Card Specific Data */
02459     hsd->CSD[0U] = SDIO_GetResponse(SDIO_RESP1);
02460     hsd->CSD[1U] = SDIO_GetResponse(SDIO_RESP2);
02461     hsd->CSD[2U] = SDIO_GetResponse(SDIO_RESP3);
02462     hsd->CSD[3U] = SDIO_GetResponse(SDIO_RESP4);
02463   }
02464
02465   /* All cards are initialized */
02466   return errorstate;
02467 }
02468
02469 /**
02470   * @brief  Selects of Deselects the corresponding card.
02471   * @param  hsd: SD handle
02472   * @param  addr: Address of the card to be selected
02473   * @retval SD Card error state
02474   */
02475 static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
02476 {
02477   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
02478   HAL_SD_ErrorTypedef errorstate = SD_OK;
02479
02480   /* Send CMD7 SDIO_SEL_DESEL_CARD */
02481   sdio_cmdinitstructure.Argument         = (uint32_t)addr;
02482   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
02483   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
02484   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
02485   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
02486   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02487
02488   /* Check for error conditions */
02489   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
02490
02491   return errorstate;
02492 }
02493
02494 /**
02495   * @brief  Enquires cards about their operating voltage and configures clock
02496   *         controls and stores SD information that will be needed in future
02497   *         in the SD handle.
02498   * @param  hsd: SD handle
02499   * @retval SD Card error state
02500   */
02501 static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
02502 {
02503   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
02504   __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
02505   uint32_t response = 0U, count = 0U, validvoltage = 0U;
02506   uint32_t sdtype = SD_STD_CAPACITY;
02507
02508   /* Power ON Sequence -------------------------------------------------------*/
02509   /* Disable SDIO Clock */
02510   __HAL_SD_SDIO_DISABLE();
02511
02512   /* Set Power State to ON */
02513   SDIO_PowerState_ON(hsd->Instance);
02514
02515   /* 1ms: required power up waiting time before starting the SD initialization
02516      sequence */
02517   HAL_Delay(1);
02518
02519   /* Enable SDIO Clock */
02520   __HAL_SD_SDIO_ENABLE();
02521
02522   /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
02523   /* No CMD response required */
02524   sdio_cmdinitstructure.Argument         = 0U;
02525   sdio_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
02526   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_NO;
02527   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
02528   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
02529   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02530
02531   /* Check for error conditions */
02532   errorstate = SD_CmdError(hsd);
02533
02534   if(errorstate != SD_OK)
02535   {
02536     /* CMD Response Timeout (wait for CMDSENT flag) */
02537     return errorstate;
02538   }
02539
02540   /* CMD8: SEND_IF_COND ------------------------------------------------------*/
02541   /* Send CMD8 to verify SD card interface operating condition */
02542   /* Argument: - [31:12]: Reserved (shall be set to '0')
02543   - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
02544   - [7:0]: Check Pattern (recommended 0xAA) */
02545   /* CMD Response: R7 */
02546   sdio_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
02547   sdio_cmdinitstructure.CmdIndex         = SD_SDIO_SEND_IF_COND;
02548   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
02549   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02550
02551   /* Check for error conditions */
02552   errorstate = SD_CmdResp7Error(hsd);
02553
02554   if (errorstate == SD_OK)
02555   {
02556     /* SD Card 2.0 */
02557     hsd->CardType = STD_CAPACITY_SD_CARD_V2_0;
02558     sdtype        = SD_HIGH_CAPACITY;
02559   }
02560
02561   /* Send CMD55 */
02562   sdio_cmdinitstructure.Argument         = 0U;
02563   sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
02564   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02565
02566   /* Check for error conditions */
02567   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
02568
02569   /* If errorstate is Command Timeout, it is a MMC card */
02570   /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
02571      or SD card 1.x */
02572   if(errorstate == SD_OK)
02573   {
02574     /* SD CARD */
02575     /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
02576     while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
02577     {
02578
02579       /* SEND CMD55 APP_CMD with RCA as 0 */
02580       sdio_cmdinitstructure.Argument         = 0U;
02581       sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
02582       sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
02583       sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
02584       sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
02585       SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02586
02587       /* Check for error conditions */
02588       errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
02589
02590       if(errorstate != SD_OK)
02591       {
02592         return errorstate;
02593       }
02594
02595       /* Send CMD41 */
02596       sdio_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
02597       sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
02598       sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
02599       sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
02600       sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
02601       SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02602
02603       /* Check for error conditions */
02604       errorstate = SD_CmdResp3Error(hsd);
02605
02606       if(errorstate != SD_OK)
02607       {
02608         return errorstate;
02609       }
02610
02611       /* Get command response */
02612       response = SDIO_GetResponse(SDIO_RESP1);
02613
02614       /* Get operating voltage*/
02615       validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
02616
02617       count++;
02618     }
02619
02620     if(count >= SD_MAX_VOLT_TRIAL)
02621     {
02622       errorstate = SD_INVALID_VOLTRANGE;
02623
02624       return errorstate;
02625     }
02626
02627     if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
02628     {
02629       hsd->CardType = HIGH_CAPACITY_SD_CARD;
02630     }
02631
02632   } /* else MMC Card */
02633
02634   return errorstate;
02635 }
02636
02637 /**
02638   * @brief  Turns the SDIO output signals off.
02639   * @param  hsd: SD handle
02640   * @retval SD Card error state
02641   */
02642 static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
02643 {
02644   HAL_SD_ErrorTypedef errorstate = SD_OK;
02645
02646   /* Set Power State to OFF */
02647   SDIO_PowerState_OFF(hsd->Instance);
02648
02649   return errorstate;
02650 }
02651
02652 /**
02653   * @brief  Returns the current card's status.
02654   * @param  hsd: SD handle
02655   * @param  pCardStatus: pointer to the buffer that will contain the SD card
02656   *         status (Card Status register)
02657   * @retval SD Card error state
02658   */
02659 static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
02660 {
02661   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
02662   HAL_SD_ErrorTypedef errorstate = SD_OK;
02663
02664   if(pCardStatus == NULL)
02665   {
02666     errorstate = SD_INVALID_PARAMETER;
02667
02668     return errorstate;
02669   }
02670
02671   /* Send Status command */
02672   sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
02673   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
02674   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
02675   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
02676   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
02677   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
02678
02679   /* Check for error conditions */
02680   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
02681
02682   if(errorstate != SD_OK)
02683   {
02684     return errorstate;
02685   }
02686
02687   /* Get SD card status */
02688   *pCardStatus = SDIO_GetResponse(SDIO_RESP1);
02689
02690   return errorstate;
02691 }
02692
02693 /**
02694   * @brief  Checks for error conditions for CMD0.
02695   * @param  hsd: SD handle
02696   * @retval SD Card error state
02697   */
02698 static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
02699 {
02700   HAL_SD_ErrorTypedef errorstate = SD_OK;
02701   uint32_t timeout, tmp;
02702
02703   timeout = SDIO_CMD0TIMEOUT;
02704
02705   tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
02706
02707   while((timeout > 0U) && (!tmp))
02708   {
02709     tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
02710     timeout--;
02711   }
02712
02713   if(timeout == 0U)
02714   {
02715     errorstate = SD_CMD_RSP_TIMEOUT;
02716     return errorstate;
02717   }
02718
02719   /* Clear all the static flags */
02720   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02721
02722   return errorstate;
02723 }
02724
02725 /**
02726   * @brief  Checks for error conditions for R7 response.
02727   * @param  hsd: SD handle
02728   * @retval SD Card error state
02729   */
02730 static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
02731 {
02732   HAL_SD_ErrorTypedef errorstate = SD_ERROR;
02733   uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
02734
02735   tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
02736
02737   while((!tmp) && (timeout > 0U))
02738   {
02739     tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
02740     timeout--;
02741   }
02742
02743   tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
02744
02745   if((timeout == 0U) || tmp)
02746   {
02747     /* Card is not V2.0 compliant or card does not support the set voltage range */
02748     errorstate = SD_CMD_RSP_TIMEOUT;
02749
02750     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
02751
02752     return errorstate;
02753   }
02754
02755   if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
02756   {
02757     /* Card is SD V2.0 compliant */
02758     errorstate = SD_OK;
02759
02760     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
02761
02762     return errorstate;
02763   }
02764
02765   return errorstate;
02766 }
02767
02768 /**
02769   * @brief  Checks for error conditions for R1 response.
02770   * @param  hsd: SD handle
02771   * @param  SD_CMD: The sent command index
02772   * @retval SD Card error state
02773   */
02774 static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
02775 {
02776   HAL_SD_ErrorTypedef errorstate = SD_OK;
02777   uint32_t response_r1;
02778
02779   while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
02780   {
02781   }
02782
02783   if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
02784   {
02785     errorstate = SD_CMD_RSP_TIMEOUT;
02786
02787     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
02788
02789     return errorstate;
02790   }
02791   else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
02792   {
02793     errorstate = SD_CMD_CRC_FAIL;
02794
02795     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
02796
02797     return errorstate;
02798   }
02799
02800   /* Check response received is of desired command */
02801   if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
02802   {
02803     errorstate = SD_ILLEGAL_CMD;
02804
02805     return errorstate;
02806   }
02807
02808   /* Clear all the static flags */
02809   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02810
02811   /* We have received response, retrieve it for analysis  */
02812   response_r1 = SDIO_GetResponse(SDIO_RESP1);
02813
02814   if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
02815   {
02816     return errorstate;
02817   }
02818
02819   if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
02820   {
02821     return(SD_ADDR_OUT_OF_RANGE);
02822   }
02823
02824   if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
02825   {
02826     return(SD_ADDR_MISALIGNED);
02827   }
02828
02829   if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
02830   {
02831     return(SD_BLOCK_LEN_ERR);
02832   }
02833
02834   if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
02835   {
02836     return(SD_ERASE_SEQ_ERR);
02837   }
02838
02839   if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
02840   {
02841     return(SD_BAD_ERASE_PARAM);
02842   }
02843
02844   if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
02845   {
02846     return(SD_WRITE_PROT_VIOLATION);
02847   }
02848
02849   if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
02850   {
02851     return(SD_LOCK_UNLOCK_FAILED);
02852   }
02853
02854   if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
02855   {
02856     return(SD_COM_CRC_FAILED);
02857   }
02858
02859   if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
02860   {
02861     return(SD_ILLEGAL_CMD);
02862   }
02863
02864   if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
02865   {
02866     return(SD_CARD_ECC_FAILED);
02867   }
02868
02869   if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
02870   {
02871     return(SD_CC_ERROR);
02872   }
02873
02874   if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
02875   {
02876     return(SD_GENERAL_UNKNOWN_ERROR);
02877   }
02878
02879   if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
02880   {
02881     return(SD_STREAM_READ_UNDERRUN);
02882   }
02883
02884   if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
02885   {
02886     return(SD_STREAM_WRITE_OVERRUN);
02887   }
02888
02889   if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
02890   {
02891     return(SD_CID_CSD_OVERWRITE);
02892   }
02893
02894   if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
02895   {
02896     return(SD_WP_ERASE_SKIP);
02897   }
02898
02899   if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
02900   {
02901     return(SD_CARD_ECC_DISABLED);
02902   }
02903
02904   if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
02905   {
02906     return(SD_ERASE_RESET);
02907   }
02908
02909   if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
02910   {
02911     return(SD_AKE_SEQ_ERROR);
02912   }
02913
02914   return errorstate;
02915 }
02916
02917 /**
02918   * @brief  Checks for error conditions for R3 (OCR) response.
02919   * @param  hsd: SD handle
02920   * @retval SD Card error state
02921   */
02922 static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
02923 {
02924   HAL_SD_ErrorTypedef errorstate = SD_OK;
02925
02926   while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
02927   {
02928   }
02929
02930   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
02931   {
02932     errorstate = SD_CMD_RSP_TIMEOUT;
02933
02934     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
02935
02936     return errorstate;
02937   }
02938
02939   /* Clear all the static flags */
02940   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02941
02942   return errorstate;
02943 }
02944
02945 /**
02946   * @brief  Checks for error conditions for R2 (CID or CSD) response.
02947   * @param  hsd: SD handle
02948   * @retval SD Card error state
02949   */
02950 static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
02951 {
02952   HAL_SD_ErrorTypedef errorstate = SD_OK;
02953
02954   while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
02955   {
02956   }
02957
02958   if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
02959   {
02960     errorstate = SD_CMD_RSP_TIMEOUT;
02961
02962     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
02963
02964     return errorstate;
02965   }
02966   else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
02967   {
02968     errorstate = SD_CMD_CRC_FAIL;
02969
02970     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
02971
02972     return errorstate;
02973   }
02974   else
02975   {
02976     /* No error flag set */
02977   }
02978
02979   /* Clear all the static flags */
02980   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02981
02982   return errorstate;
02983 }
02984
02985 /**
02986   * @brief  Checks for error conditions for R6 (RCA) response.
02987   * @param  hsd: SD handle
02988   * @param  SD_CMD: The sent command index
02989   * @param  pRCA: Pointer to the variable that will contain the SD card relative
02990   *         address RCA
02991   * @retval SD Card error state
02992   */
02993 static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
02994 {
02995   HAL_SD_ErrorTypedef errorstate = SD_OK;
02996   uint32_t response_r1;
02997
02998   while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
02999   {
03000   }
03001
03002   if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
03003   {
03004     errorstate = SD_CMD_RSP_TIMEOUT;
03005
03006     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
03007
03008     return errorstate;
03009   }
03010   else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
03011   {
03012     errorstate = SD_CMD_CRC_FAIL;
03013
03014     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
03015
03016     return errorstate;
03017   }
03018   else
03019   {
03020     /* No error flag set */
03021   }
03022
03023   /* Check response received is of desired command */
03024   if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
03025   {
03026     errorstate = SD_ILLEGAL_CMD;
03027
03028     return errorstate;
03029   }
03030
03031   /* Clear all the static flags */
03032   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
03033
03034   /* We have received response, retrieve it.  */
03035   response_r1 = SDIO_GetResponse(SDIO_RESP1);
03036
03037   if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
03038   {
03039     *pRCA = (uint16_t) (response_r1 >> 16U);
03040
03041     return errorstate;
03042   }
03043
03044   if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
03045   {
03046     return(SD_GENERAL_UNKNOWN_ERROR);
03047   }
03048
03049   if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
03050   {
03051     return(SD_ILLEGAL_CMD);
03052   }
03053
03054   if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
03055   {
03056     return(SD_COM_CRC_FAILED);
03057   }
03058
03059   return errorstate;
03060 }
03061
03062 /**
03063   * @brief  Enables the SDIO wide bus mode.
03064   * @param  hsd: SD handle
03065   * @retval SD Card error state
03066   */
03067 static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
03068 {
03069   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
03070   HAL_SD_ErrorTypedef errorstate = SD_OK;
03071
03072   uint32_t scr[2U] = {0U, 0U};
03073
03074   if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
03075   {
03076     errorstate = SD_LOCK_UNLOCK_FAILED;
03077
03078     return errorstate;
03079   }
03080
03081   /* Get SCR Register */
03082   errorstate = SD_FindSCR(hsd, scr);
03083
03084   if(errorstate != SD_OK)
03085   {
03086     return errorstate;
03087   }
03088
03089   /* If requested card supports wide bus operation */
03090   if((scr[1U] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
03091   {
03092     /* Send CMD55 APP_CMD with argument as card's RCA.*/
03093     sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
03094     sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03095     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
03096     sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
03097     sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
03098     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03099
03100     /* Check for error conditions */
03101     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03102
03103     if(errorstate != SD_OK)
03104     {
03105       return errorstate;
03106     }
03107
03108     /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
03109     sdio_cmdinitstructure.Argument         = 2U;
03110     sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
03111     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03112
03113     /* Check for error conditions */
03114     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
03115
03116     if(errorstate != SD_OK)
03117     {
03118       return errorstate;
03119     }
03120
03121     return errorstate;
03122   }
03123   else
03124   {
03125     errorstate = SD_REQUEST_NOT_APPLICABLE;
03126
03127     return errorstate;
03128   }
03129 }
03130
03131 /**
03132   * @brief  Disables the SDIO wide bus mode.
03133   * @param  hsd: SD handle
03134   * @retval SD Card error state
03135   */
03136 static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
03137 {
03138   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
03139   HAL_SD_ErrorTypedef errorstate = SD_OK;
03140
03141   uint32_t scr[2U] = {0U, 0U};
03142
03143   if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
03144   {
03145     errorstate = SD_LOCK_UNLOCK_FAILED;
03146
03147     return errorstate;
03148   }
03149
03150   /* Get SCR Register */
03151   errorstate = SD_FindSCR(hsd, scr);
03152
03153   if(errorstate != SD_OK)
03154   {
03155     return errorstate;
03156   }
03157
03158   /* If requested card supports 1 bit mode operation */
03159   if((scr[1U] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
03160   {
03161     /* Send CMD55 APP_CMD with argument as card's RCA */
03162     sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
03163     sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03164     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
03165     sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
03166     sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
03167     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03168
03169     /* Check for error conditions */
03170     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03171
03172     if(errorstate != SD_OK)
03173     {
03174       return errorstate;
03175     }
03176
03177     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
03178     sdio_cmdinitstructure.Argument         = 0U;
03179     sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
03180     SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03181
03182     /* Check for error conditions */
03183     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
03184
03185     if(errorstate != SD_OK)
03186     {
03187       return errorstate;
03188     }
03189
03190     return errorstate;
03191   }
03192   else
03193   {
03194     errorstate = SD_REQUEST_NOT_APPLICABLE;
03195
03196     return errorstate;
03197   }
03198 }
03199
03200
03201 /**
03202   * @brief  Finds the SD card SCR register value.
03203   * @param  hsd: SD handle
03204   * @param  pSCR: pointer to the buffer that will contain the SCR value
03205   * @retval SD Card error state
03206   */
03207 static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
03208 {
03209   SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
03210   SDIO_DataInitTypeDef sdio_datainitstructure;
03211   HAL_SD_ErrorTypedef errorstate = SD_OK;
03212   uint32_t index = 0U;
03213   uint32_t tempscr[2U] = {0U, 0U};
03214
03215   /* Set Block Size To 8 Bytes */
03216   /* Send CMD55 APP_CMD with argument as card's RCA */
03217   sdio_cmdinitstructure.Argument         = (uint32_t)8U;
03218   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
03219   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
03220   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
03221   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
03222   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03223
03224   /* Check for error conditions */
03225   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
03226
03227   if(errorstate != SD_OK)
03228   {
03229     return errorstate;
03230   }
03231
03232   /* Send CMD55 APP_CMD with argument as card's RCA */
03233   sdio_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16U);
03234   sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03235   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03236
03237   /* Check for error conditions */
03238   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03239
03240   if(errorstate != SD_OK)
03241   {
03242     return errorstate;
03243   }
03244   sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
03245   sdio_datainitstructure.DataLength    = 8U;
03246   sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
03247   sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
03248   sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
03249   sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
03250   SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
03251
03252   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
03253   sdio_cmdinitstructure.Argument         = 0U;
03254   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
03255   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03256
03257   /* Check for error conditions */
03258   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
03259
03260   if(errorstate != SD_OK)
03261   {
03262     return errorstate;
03263   }
03264 #ifdef SDIO_STA_STBITERR
03265   while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
03266 #else /* SDIO_STA_STBITERR not defined */
03267   while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
03268 #endif /* SDIO_STA_STBITERR */
03269   {
03270     if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
03271     {
03272       *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
03273       index++;
03274     }
03275   }
03276
03277   if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
03278   {
03279     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
03280
03281     errorstate = SD_DATA_TIMEOUT;
03282
03283     return errorstate;
03284   }
03285   else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
03286   {
03287     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
03288
03289     errorstate = SD_DATA_CRC_FAIL;
03290
03291     return errorstate;
03292   }
03293   else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
03294   {
03295     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
03296
03297     errorstate = SD_RX_OVERRUN;
03298
03299     return errorstate;
03300   }
03301 #ifdef SDIO_STA_STBITERR
03302   else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
03303   {
03304     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
03305
03306     errorstate = SD_START_BIT_ERR;
03307
03308     return errorstate;
03309   }
03310 #endif /* SDIO_STA_STBITERR */
03311   else
03312   {
03313     /* No error flag set */
03314   }
03315
03316   /* Clear all the static flags */
03317   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
03318
03319   *(pSCR + 1U) = ((tempscr[0U] & SD_0TO7BITS) << 24U)  | ((tempscr[0U] & SD_8TO15BITS) << 8U) |\
03320     ((tempscr[0U] & SD_16TO23BITS) >> 8U) | ((tempscr[0U] & SD_24TO31BITS) >> 24U);
03321
03322   *(pSCR) = ((tempscr[1U] & SD_0TO7BITS) << 24U)  | ((tempscr[1U] & SD_8TO15BITS) << 8U) |\
03323     ((tempscr[1U] & SD_16TO23BITS) >> 8U) | ((tempscr[1U] & SD_24TO31BITS) >> 24U);
03324
03325   return errorstate;
03326 }
03327
03328 /**
03329   * @brief  Checks if the SD card is in programming state.
03330   * @param  hsd: SD handle
03331   * @param  pStatus: pointer to the variable that will contain the SD card state
03332   * @retval SD Card error state
03333   */
03334 static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
03335 {
03336   SDIO_CmdInitTypeDef sdio_cmdinitstructure;
03337   HAL_SD_ErrorTypedef errorstate = SD_OK;
03338   __IO uint32_t responseR1 = 0U;
03339
03340   sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16U);
03341   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
03342   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
03343   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
03344   sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
03345   SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
03346
03347   while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
03348   {
03349   }
03350
03351   if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
03352   {
03353     errorstate = SD_CMD_RSP_TIMEOUT;
03354
03355     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
03356
03357     return errorstate;
03358   }
03359   else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
03360   {
03361     errorstate = SD_CMD_CRC_FAIL;
03362
03363     __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
03364
03365     return errorstate;
03366   }
03367   else
03368   {
03369     /* No error flag set */
03370   }
03371
03372   /* Check response received is of desired command */
03373   if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
03374   {
03375     errorstate = SD_ILLEGAL_CMD;
03376
03377     return errorstate;
03378   }
03379
03380   /* Clear all the static flags */
03381   __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
03382
03383
03384   /* We have received response, retrieve it for analysis */
03385   responseR1 = SDIO_GetResponse(SDIO_RESP1);
03386
03387   /* Find out card status */
03388   *pStatus = (uint8_t)((responseR1 >> 9U) & 0x0000000FU);
03389
03390   if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
03391   {
03392     return errorstate;
03393   }
03394
03395   if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
03396   {
03397     return(SD_ADDR_OUT_OF_RANGE);
03398   }
03399
03400   if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
03401   {
03402     return(SD_ADDR_MISALIGNED);
03403   }
03404
03405   if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
03406   {
03407     return(SD_BLOCK_LEN_ERR);
03408   }
03409
03410   if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
03411   {
03412     return(SD_ERASE_SEQ_ERR);
03413   }
03414
03415   if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
03416   {
03417     return(SD_BAD_ERASE_PARAM);
03418   }
03419
03420   if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
03421   {
03422     return(SD_WRITE_PROT_VIOLATION);
03423   }
03424
03425   if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
03426   {
03427     return(SD_LOCK_UNLOCK_FAILED);
03428   }
03429
03430   if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
03431   {
03432     return(SD_COM_CRC_FAILED);
03433   }
03434
03435   if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
03436   {
03437     return(SD_ILLEGAL_CMD);
03438   }
03439
03440   if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
03441   {
03442     return(SD_CARD_ECC_FAILED);
03443   }
03444
03445   if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
03446   {
03447     return(SD_CC_ERROR);
03448   }
03449
03450   if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
03451   {
03452     return(SD_GENERAL_UNKNOWN_ERROR);
03453   }
03454
03455   if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
03456   {
03457     return(SD_STREAM_READ_UNDERRUN);
03458   }
03459
03460   if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
03461   {
03462     return(SD_STREAM_WRITE_OVERRUN);
03463   }
03464
03465   if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
03466   {
03467     return(SD_CID_CSD_OVERWRITE);
03468   }
03469
03470   if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
03471   {
03472     return(SD_WP_ERASE_SKIP);
03473   }
03474
03475   if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
03476   {
03477     return(SD_CARD_ECC_DISABLED);
03478   }
03479
03480   if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
03481   {
03482     return(SD_ERASE_RESET);
03483   }
03484
03485   if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
03486   {
03487     return(SD_AKE_SEQ_ERROR);
03488   }
03489
03490   return errorstate;
03491 }
03492
03493 /**
03494   * @}
03495   */
03496 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
03497           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
03498 #endif /* HAL_SD_MODULE_ENABLED */
03499
03500 /**
03501   * @}
03502   */
03503
03504 /**
03505   * @}
03506   */
03507
03508 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sd.h Source File

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stm32f4xx_hal_sd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sd.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SD_H
00040 #define __STM32F4xx_HAL_SD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
00046     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
00047     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
00048     defined(STM32F469xx) || defined(STM32F479xx)
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_ll_sdmmc.h"
00051
00052 /** @addtogroup STM32F4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @defgroup SD SD
00057   * @brief SD HAL module driver
00058   * @{
00059   */
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 /** @defgroup SD_Exported_Types SD Exported Types
00063   * @{
00064   */
00065
00066 /** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
00067   * @{
00068   */
00069 #define SD_InitTypeDef      SDIO_InitTypeDef
00070 #define SD_TypeDef          SDIO_TypeDef
00071
00072 typedef struct
00073 {
00074   SD_TypeDef                   *Instance;        /*!< SDIO register base address                     */
00075
00076   SD_InitTypeDef               Init;             /*!< SD required parameters                         */
00077
00078   HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
00079
00080   uint32_t                     CardType;         /*!< SD card type                                   */
00081
00082   uint32_t                     RCA;              /*!< SD relative card address                       */
00083
00084   uint32_t                     CSD[4];           /*!< SD card specific data table                    */
00085
00086   uint32_t                     CID[4];           /*!< SD card identification number table            */
00087
00088   __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
00089
00090   __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
00091
00092   __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
00093
00094   __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
00095
00096   DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
00097
00098   DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
00099
00100 }SD_HandleTypeDef;
00101 /**
00102   * @}
00103   */
00104
00105 /** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
00106   * @{
00107   */
00108 typedef struct
00109 {
00110   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00111   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00112   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00113   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00114   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00115   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00116   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00117   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00118   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00119   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00120   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00121   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00122   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00123   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00124   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00125   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00126   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00127   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00128   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00129   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00130   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00131   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00132   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00133   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00134   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00135   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00136   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00137   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00138   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00139   __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
00140   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00141   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00142   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00143   __IO uint8_t  FileFormat;           /*!< File format                           */
00144   __IO uint8_t  ECC;                  /*!< ECC code                              */
00145   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00146   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00147
00148 }HAL_SD_CSDTypedef;
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
00154   * @{
00155   */
00156 typedef struct
00157 {
00158   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00159   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00160   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00161   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00162   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00163   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00164   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00165   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00166   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00167   __IO uint8_t  Reserved2;       /*!< Always 1              */
00168
00169 }HAL_SD_CIDTypedef;
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
00175   * @{
00176   */
00177 typedef struct
00178 {
00179   __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
00180   __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
00181   __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
00182   __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
00183   __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
00184   __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
00185   __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
00186   __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
00187   __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
00188   __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
00189
00190 }HAL_SD_CardStatusTypedef;
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup SD_Exported_Types_Group5 SD Card information structure
00196   * @{
00197   */
00198 typedef struct
00199 {
00200   HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
00201   HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
00202   uint64_t            CardCapacity;   /*!< Card capacity                          */
00203   uint32_t            CardBlockSize;  /*!< Card block size                        */
00204   uint16_t            RCA;            /*!< SD relative card address               */
00205   uint8_t             CardType;       /*!< SD card type                           */
00206
00207 }HAL_SD_CardInfoTypedef;
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
00213   * @{
00214   */
00215 typedef enum
00216 {
00217 /**
00218   * @brief  SD specific error defines
00219   */
00220   SD_CMD_CRC_FAIL                    = (1U),   /*!< Command response received (but CRC check failed)              */
00221   SD_DATA_CRC_FAIL                   = (2U),   /*!< Data block sent/received (CRC check failed)                   */
00222   SD_CMD_RSP_TIMEOUT                 = (3U),   /*!< Command response timeout                                      */
00223   SD_DATA_TIMEOUT                    = (4U),   /*!< Data timeout                                                  */
00224   SD_TX_UNDERRUN                     = (5U),   /*!< Transmit FIFO underrun                                        */
00225   SD_RX_OVERRUN                      = (6U),   /*!< Receive FIFO overrun                                          */
00226   SD_START_BIT_ERR                   = (7U),   /*!< Start bit not detected on all data signals in wide bus mode   */
00227   SD_CMD_OUT_OF_RANGE                = (8U),   /*!< Command's argument was out of range.                          */
00228   SD_ADDR_MISALIGNED                 = (9U),   /*!< Misaligned address                                            */
00229   SD_BLOCK_LEN_ERR                   = (10U),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
00230   SD_ERASE_SEQ_ERR                   = (11U),  /*!< An error in the sequence of erase command occurs.            */
00231   SD_BAD_ERASE_PARAM                 = (12U),  /*!< An invalid selection for erase groups                        */
00232   SD_WRITE_PROT_VIOLATION            = (13U),  /*!< Attempt to program a write protect block                     */
00233   SD_LOCK_UNLOCK_FAILED              = (14U),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
00234   SD_COM_CRC_FAILED                  = (15U),  /*!< CRC check of the previous command failed                     */
00235   SD_ILLEGAL_CMD                     = (16U),  /*!< Command is not legal for the card state                      */
00236   SD_CARD_ECC_FAILED                 = (17U),  /*!< Card internal ECC was applied but failed to correct the data */
00237   SD_CC_ERROR                        = (18U),  /*!< Internal card controller error                               */
00238   SD_GENERAL_UNKNOWN_ERROR           = (19U),  /*!< General or unknown error                                     */
00239   SD_STREAM_READ_UNDERRUN            = (20U),  /*!< The card could not sustain data transfer in stream read operation. */
00240   SD_STREAM_WRITE_OVERRUN            = (21U),  /*!< The card could not sustain data programming in stream mode   */
00241   SD_CID_CSD_OVERWRITE               = (22U),  /*!< CID/CSD overwrite error                                      */
00242   SD_WP_ERASE_SKIP                   = (23U),  /*!< Only partial address space was erased                        */
00243   SD_CARD_ECC_DISABLED               = (24U),  /*!< Command has been executed without using internal ECC         */
00244   SD_ERASE_RESET                     = (25U),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
00245   SD_AKE_SEQ_ERROR                   = (26U),  /*!< Error in sequence of authentication.                         */
00246   SD_INVALID_VOLTRANGE               = (27U),
00247   SD_ADDR_OUT_OF_RANGE               = (28U),
00248   SD_SWITCH_ERROR                    = (29U),
00249   SD_SDIO_DISABLED                   = (30U),
00250   SD_SDIO_FUNCTION_BUSY              = (31U),
00251   SD_SDIO_FUNCTION_FAILED            = (32U),
00252   SD_SDIO_UNKNOWN_FUNCTION           = (33U),
00253
00254 /**
00255   * @brief  Standard error defines
00256   */
00257   SD_INTERNAL_ERROR                  = (34U),
00258   SD_NOT_CONFIGURED                  = (35U),
00259   SD_REQUEST_PENDING                 = (36U),
00260   SD_REQUEST_NOT_APPLICABLE          = (37U),
00261   SD_INVALID_PARAMETER               = (38U),
00262   SD_UNSUPPORTED_FEATURE             = (39U),
00263   SD_UNSUPPORTED_HW                  = (40U),
00264   SD_ERROR                           = (41U),
00265   SD_OK                              = (0U)
00266
00267 }HAL_SD_ErrorTypedef;
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
00273   * @{
00274   */
00275 typedef enum
00276 {
00277   SD_TRANSFER_OK    = 0U,  /*!< Transfer success      */
00278   SD_TRANSFER_BUSY  = 1U,  /*!< Transfer is occurring */
00279   SD_TRANSFER_ERROR = 2U   /*!< Transfer failed       */
00280
00281 }HAL_SD_TransferStateTypedef;
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
00287   * @{
00288   */
00289 typedef enum
00290 {
00291   SD_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */
00292   SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */
00293   SD_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */
00294   SD_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */
00295   SD_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */
00296   SD_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */
00297   SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */
00298   SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */
00299   SD_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card is in error state                  */
00300
00301 }HAL_SD_CardStateTypedef;
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
00307   * @{
00308   */
00309 typedef enum
00310 {
00311   SD_READ_SINGLE_BLOCK    = 0U,  /*!< Read single block operation      */
00312   SD_READ_MULTIPLE_BLOCK  = 1U,  /*!< Read multiple blocks operation   */
00313   SD_WRITE_SINGLE_BLOCK   = 2U,  /*!< Write single block operation     */
00314   SD_WRITE_MULTIPLE_BLOCK = 3U   /*!< Write multiple blocks operation  */
00315
00316 }HAL_SD_OperationTypedef;
00317 /**
00318   * @}
00319   */
00320
00321 /**
00322   * @}
00323   */
00324
00325 /* Exported constants --------------------------------------------------------*/
00326 /** @defgroup SD_Exported_Constants SD Exported Constants
00327   * @{
00328   */
00329
00330 /**
00331   * @brief SD Commands Index
00332   */
00333 #define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */
00334 #define SD_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */
00335 #define SD_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
00336 #define SD_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
00337 #define SD_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
00338 #define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
00339                                                                        operating condition register (OCR) content in the response on the CMD line.              */
00340 #define SD_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
00341 #define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
00342 #define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
00343                                                                        and asks the card whether card supports voltage.                                         */
00344 #define SD_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
00345 #define SD_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
00346 #define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11U)  /*!< SD card doesn't support it.                                                              */
00347 #define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */
00348 #define SD_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
00349 #define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)
00350 #define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
00351 #define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands
00352                                                                        (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
00353                                                                        for SDHS and SDXC.                                                                       */
00354 #define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
00355                                                                        fixed 512 bytes in case of SDHC and SDXC.                                                */
00356 #define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by
00357                                                                        STOP_TRANSMISSION command.                                                               */
00358 #define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
00359 #define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
00360 #define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
00361 #define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
00362                                                                        fixed 512 bytes in case of SDHC and SDXC.                                                */
00363 #define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
00364 #define SD_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
00365 #define SD_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
00366 #define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */
00367 #define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */
00368 #define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
00369 #define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
00370 #define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
00371 #define SD_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command
00372                                                                        system set by switch function command (CMD6).                                            */
00373 #define SD_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased.
00374                                                                        Reserved for each command system set by switch function command (CMD6).                  */
00375 #define SD_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
00376 #define SD_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
00377 #define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
00378 #define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
00379                                                                        the SET_BLOCK_LEN command.                                                               */
00380 #define SD_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather
00381                                                                        than a standard command.                                                                 */
00382 #define SD_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card
00383                                                                        for general purpose/application specific commands.                                       */
00384 #define SD_CMD_NO_CMD                              ((uint8_t)64U)
00385
00386 /**
00387   * @brief Following commands are SD Card Specific commands.
00388   *        SDIO_APP_CMD should be sent before sending these commands.
00389   */
00390 #define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
00391                                                                        widths are given in SCR register.                                                          */
00392 #define SD_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                              */
00393 #define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
00394                                                                        32bit+CRC data block.                                                                      */
00395 #define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
00396                                                                        send its operating condition register (OCR) content in the response on the CMD line.       */
00397 #define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
00398 #define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                                 */
00399 #define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                                 */
00400 #define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                                 */
00401
00402 /**
00403   * @brief Following commands are SD Card Specific security commands.
00404   *        SD_CMD_APP_CMD should be sent before sending these commands.
00405   */
00406 #define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)  /*!< For SD card only */
00407 #define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44U)  /*!< For SD card only */
00408 #define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)  /*!< For SD card only */
00409 #define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)  /*!< For SD card only */
00410 #define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)  /*!< For SD card only */
00411 #define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)  /*!< For SD card only */
00412 #define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)  /*!< For SD card only */
00413 #define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)  /*!< For SD card only */
00414 #define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)  /*!< For SD card only */
00415 #define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)  /*!< For SD card only */
00416 #define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)  /*!< For SD card only */
00417
00418 /**
00419   * @brief Supported SD Memory Cards
00420   */
00421 #define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000U)
00422 #define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001U)
00423 #define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002U)
00424 #define MULTIMEDIA_CARD                       ((uint32_t)0x00000003U)
00425 #define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004U)
00426 #define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005U)
00427 #define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006U)
00428 #define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007U)
00429 /**
00430   * @}
00431   */
00432
00433 /* Exported macro ------------------------------------------------------------*/
00434 /** @defgroup SD_Exported_macros SD Exported Macros
00435   * @brief macros to handle interrupts and specific clock configurations
00436   * @{
00437   */
00438
00439 /**
00440   * @brief  Enable the SD device.
00441   * @retval None
00442   */
00443 #define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
00444
00445 /**
00446   * @brief  Disable the SD device.
00447   * @retval None
00448   */
00449 #define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
00450
00451 /**
00452   * @brief  Enable the SDIO DMA transfer.
00453   * @retval None
00454   */
00455 #define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
00456
00457 /**
00458   * @brief  Disable the SDIO DMA transfer.
00459   * @retval None
00460   */
00461 #define __HAL_SD_SDIO_DMA_DISABLE()  __SDIO_DMA_DISABLE()
00462
00463 /**
00464   * @brief  Enable the SD device interrupt.
00465   * @param  __HANDLE__: SD Handle
00466   * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
00467   *         This parameter can be one or a combination of the following values:
00468   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00469   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00470   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00471   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00472   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00473   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00474   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00475   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00476   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00477   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00478   *                                   bus mode interrupt
00479   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00480   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00481   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00482   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00483   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00484   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00485   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00486   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00487   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00488   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00489   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00490   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00491   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00492   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
00493   * @retval None
00494   */
00495 #define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00496
00497 /**
00498   * @brief  Disable the SD device interrupt.
00499   * @param  __HANDLE__: SD Handle
00500   * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
00501   *          This parameter can be one or a combination of the following values:
00502   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00503   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00504   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00505   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00506   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00507   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00508   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00509   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00510   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00511   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00512   *                                   bus mode interrupt
00513   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00514   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00515   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00516   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00517   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00518   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00519   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00520   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00521   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00522   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00523   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00524   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00525   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00526   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
00527   * @retval None
00528   */
00529 #define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00530
00531 /**
00532   * @brief  Check whether the specified SD flag is set or not.
00533   * @param  __HANDLE__: SD Handle
00534   * @param  __FLAG__: specifies the flag to check.
00535   *          This parameter can be one of the following values:
00536   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00537   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00538   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00539   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
00540   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00541   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00542   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00543   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00544   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00545   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
00546   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00547   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
00548   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
00549   *            @arg SDIO_FLAG_RXACT:    Data receive in progress
00550   *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
00551   *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
00552   *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
00553   *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
00554   *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
00555   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
00556   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
00557   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
00558   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00559   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
00560   * @retval The new state of SD FLAG (SET or RESET).
00561   */
00562 #define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00563
00564 /**
00565   * @brief  Clear the SD's pending flags.
00566   * @param  __HANDLE__: SD Handle
00567   * @param  __FLAG__: specifies the flag to clear.
00568   *          This parameter can be one or a combination of the following values:
00569   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00570   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00571   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00572   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
00573   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00574   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00575   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00576   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00577   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00578   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
00579   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00580   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00581   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
00582   * @retval None
00583   */
00584 #define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00585
00586 /**
00587   * @brief  Check whether the specified SD interrupt has occurred or not.
00588   * @param  __HANDLE__: SD Handle
00589   * @param  __INTERRUPT__: specifies the SDIO interrupt source to check.
00590   *          This parameter can be one of the following values:
00591   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00592   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00593   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00594   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00595   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00596   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00597   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00598   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00599   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00600   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00601   *                                   bus mode interrupt
00602   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00603   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00604   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00605   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00606   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00607   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00608   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00609   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00610   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00611   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00612   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00613   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00614   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00615   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
00616   * @retval The new state of SD IT (SET or RESET).
00617   */
00618 #define __HAL_SD_SDIO_GET_IT  (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT  ((__HANDLE__)->Instance, __INTERRUPT__)
00619
00620 /**
00621   * @brief  Clear the SD's interrupt pending bits.
00622   * @param  __HANDLE__: SD Handle
00623   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00624   *          This parameter can be one or a combination of the following values:
00625   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00626   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00627   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00628   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00629   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00630   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00631   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00632   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00633   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
00634   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
00635   *                                   bus mode interrupt
00636   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00637   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
00638   * @retval None
00639   */
00640 #define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00641 /**
00642   * @}
00643   */
00644
00645 /* Exported functions --------------------------------------------------------*/
00646 /** @defgroup SD_Exported_Functions SD Exported Functions
00647   * @{
00648   */
00649
00650 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
00651   * @{
00652   */
00653 HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
00654 HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
00655 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
00656 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup SD_Exported_Functions_Group2 I/O operation functions
00662   * @{
00663   */
00664 /* Blocking mode: Polling */
00665 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00666 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00667 HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
00668
00669 /* Non-Blocking mode: Interrupt */
00670 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
00671
00672 /* Callback in non blocking modes (DMA) */
00673 void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
00674 void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
00675 void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
00676 void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
00677 void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
00678 void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
00679
00680 /* Non-Blocking mode: DMA */
00681 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00682 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00683 HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
00684 HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
00685 /**
00686   * @}
00687   */
00688
00689 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
00690   * @{
00691   */
00692 HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
00693 HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
00694 HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
00695 HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
00696 /**
00697   * @}
00698   */
00699
00700 /* Peripheral State functions  ************************************************/
00701 /** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
00702   * @{
00703   */
00704 HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00705 HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
00706 HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
00707 /**
00708   * @}
00709   */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /* Private types -------------------------------------------------------------*/
00716 /** @defgroup SD_Private_Types SD Private Types
00717   * @{
00718   */
00719
00720 /**
00721   * @}
00722   */
00723
00724 /* Private defines -----------------------------------------------------------*/
00725 /** @defgroup SD_Private_Defines SD Private Defines
00726   * @{
00727   */
00728
00729 /**
00730   * @}
00731   */
00732
00733 /* Private variables ---------------------------------------------------------*/
00734 /** @defgroup SD_Private_Variables SD Private Variables
00735   * @{
00736   */
00737
00738 /**
00739   * @}
00740   */
00741
00742 /* Private constants ---------------------------------------------------------*/
00743 /** @defgroup SD_Private_Constants SD Private Constants
00744   * @{
00745   */
00746
00747 /**
00748   * @}
00749   */
00750
00751 /* Private macros ------------------------------------------------------------*/
00752 /** @defgroup SD_Private_Macros SD Private Macros
00753   * @{
00754   */
00755
00756 /**
00757   * @}
00758   */
00759
00760 /* Private functions prototypes ----------------------------------------------*/
00761 /** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
00762   * @{
00763   */
00764
00765 /**
00766   * @}
00767   */
00768
00769 /* Private functions ---------------------------------------------------------*/
00770 /** @defgroup SD_Private_Functions SD Private Functions
00771   * @{
00772   */
00773
00774 /**
00775   * @}
00776   */
00777
00778 /**
00779   * @}
00780   */
00781
00782 /**
00783   * @}
00784   */
00785 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
00786           STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
00787 #ifdef __cplusplus
00788 }
00789 #endif
00790
00791 #endif /* __STM32F4xx_HAL_SD_H */
00792
00793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sdram.c Source File

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stm32f4xx_hal_sdram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sdram.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   SDRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SDRAM memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                        ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SDRAM memories. It uses the FMC layer functions to interface
00018     with SDRAM devices.
00019     The following sequence should be followed to configure the FMC to interface
00020     with SDRAM memories:
00021
00022    (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
00023           SDRAM_HandleTypeDef  hdsram
00024
00025        (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SDRAM device
00030
00031    (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
00032           FMC_SDRAM_TimingTypeDef  Timing;
00033       and fill its fields with the allowed values of the structure member.
00034
00035    (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
00036        performs the following sequence:
00037
00038        (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
00039        (##) Control register configuration using the FMC SDRAM interface function
00040             FMC_SDRAM_Init()
00041        (##) Timing register configuration using the FMC SDRAM interface function
00042             FMC_SDRAM_Timing_Init()
00043        (##) Program the SDRAM external device by applying its initialization sequence
00044             according to the device plugged in your hardware. This step is mandatory
00045             for accessing the SDRAM device.
00046
00047    (#) At this stage you can perform read/write accesses from/to the memory connected
00048        to the SDRAM Bank. You can perform either polling or DMA transfer using the
00049        following APIs:
00050        (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
00051        (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
00052
00053    (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
00054        HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
00055        the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
00056        device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
00057        structure.
00058
00059    (#) You can continuously monitor the SDRAM device HAL state by calling the function
00060        HAL_SDRAM_GetState()
00061
00062   @endverbatim
00063   ******************************************************************************
00064   * @attention
00065   *
00066   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00067   *
00068   * Redistribution and use in source and binary forms, with or without modification,
00069   * are permitted provided that the following conditions are met:
00070   *   1. Redistributions of source code must retain the above copyright notice,
00071   *      this list of conditions and the following disclaimer.
00072   *   2. Redistributions in binary form must reproduce the above copyright notice,
00073   *      this list of conditions and the following disclaimer in the documentation
00074   *      and/or other materials provided with the distribution.
00075   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00076   *      may be used to endorse or promote products derived from this software
00077   *      without specific prior written permission.
00078   *
00079   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00080   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00081   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00082   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00083   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00084   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00085   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00086   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00087   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00088   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32f4xx_hal.h"
00095
00096 /** @addtogroup STM32F4xx_HAL_Driver
00097   * @{
00098   */
00099
00100 /** @defgroup SDRAM SDRAM
00101   * @brief SDRAM driver modules
00102   * @{
00103   */
00104 #ifdef HAL_SDRAM_MODULE_ENABLED
00105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00106     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00107
00108 /* Private typedef -----------------------------------------------------------*/
00109 /* Private define ------------------------------------------------------------*/
00110 /* Private macro -------------------------------------------------------------*/
00111 /* Private variables ---------------------------------------------------------*/
00112 /* Private functions ---------------------------------------------------------*/
00113 /* Exported functions --------------------------------------------------------*/
00114 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
00115   * @{
00116   */
00117
00118 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00119   * @brief    Initialization and Configuration functions
00120   *
00121   @verbatim
00122   ==============================================================================
00123            ##### SDRAM Initialization and de_initialization functions #####
00124   ==============================================================================
00125   [..]
00126     This section provides functions allowing to initialize/de-initialize
00127     the SDRAM memory
00128
00129 @endverbatim
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  Performs the SDRAM device initialization sequence.
00135   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00136   *                the configuration information for SDRAM module.
00137   * @param  Timing: Pointer to SDRAM control timing structure
00138   * @retval HAL status
00139   */
00140 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
00141 {
00142   /* Check the SDRAM handle parameter */
00143   if(hsdram == NULL)
00144   {
00145     return HAL_ERROR;
00146   }
00147
00148   if(hsdram->State == HAL_SDRAM_STATE_RESET)
00149   {
00150     /* Allocate lock resource and initialize it */
00151     hsdram->Lock = HAL_UNLOCKED;
00152     /* Initialize the low level hardware (MSP) */
00153     HAL_SDRAM_MspInit(hsdram);
00154   }
00155
00156   /* Initialize the SDRAM controller state */
00157   hsdram->State = HAL_SDRAM_STATE_BUSY;
00158
00159   /* Initialize SDRAM control Interface */
00160   FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
00161
00162   /* Initialize SDRAM timing Interface */
00163   FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
00164
00165   /* Update the SDRAM controller state */
00166   hsdram->State = HAL_SDRAM_STATE_READY;
00167
00168   return HAL_OK;
00169 }
00170
00171 /**
00172   * @brief  Perform the SDRAM device initialization sequence.
00173   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00174   *                the configuration information for SDRAM module.
00175   * @retval HAL status
00176   */
00177 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
00178 {
00179   /* Initialize the low level hardware (MSP) */
00180   HAL_SDRAM_MspDeInit(hsdram);
00181
00182   /* Configure the SDRAM registers with their reset values */
00183   FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
00184
00185   /* Reset the SDRAM controller state */
00186   hsdram->State = HAL_SDRAM_STATE_RESET;
00187
00188   /* Release Lock */
00189   __HAL_UNLOCK(hsdram);
00190
00191   return HAL_OK;
00192 }
00193
00194 /**
00195   * @brief  SDRAM MSP Init.
00196   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00197   *                the configuration information for SDRAM module.
00198   * @retval None
00199   */
00200 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
00201 {
00202   /* Prevent unused argument(s) compilation warning */
00203   UNUSED(hsdram);
00204   /* NOTE: This function Should not be modified, when the callback is needed,
00205             the HAL_SDRAM_MspInit could be implemented in the user file
00206    */
00207 }
00208
00209 /**
00210   * @brief  SDRAM MSP DeInit.
00211   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00212   *                the configuration information for SDRAM module.
00213   * @retval None
00214   */
00215 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
00216 {
00217   /* Prevent unused argument(s) compilation warning */
00218   UNUSED(hsdram);
00219   /* NOTE: This function Should not be modified, when the callback is needed,
00220             the HAL_SDRAM_MspDeInit could be implemented in the user file
00221    */
00222 }
00223
00224 /**
00225   * @brief  This function handles SDRAM refresh error interrupt request.
00226   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00227   *                the configuration information for SDRAM module.
00228   * @retval HAL status
00229 */
00230 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
00231 {
00232   /* Check SDRAM interrupt Rising edge flag */
00233   if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
00234   {
00235     /* SDRAM refresh error interrupt callback */
00236     HAL_SDRAM_RefreshErrorCallback(hsdram);
00237
00238     /* Clear SDRAM refresh error interrupt pending bit */
00239     __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
00240   }
00241 }
00242
00243 /**
00244   * @brief  SDRAM Refresh error callback.
00245   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00246   *                the configuration information for SDRAM module.
00247   * @retval None
00248   */
00249 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
00250 {
00251   /* Prevent unused argument(s) compilation warning */
00252   UNUSED(hsdram);
00253   /* NOTE: This function Should not be modified, when the callback is needed,
00254             the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
00255    */
00256 }
00257
00258 /**
00259   * @brief  DMA transfer complete callback.
00260   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00261   *                the configuration information for the specified DMA module.
00262   * @retval None
00263   */
00264 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(hdma);
00268   /* NOTE: This function Should not be modified, when the callback is needed,
00269             the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
00270    */
00271 }
00272
00273 /**
00274   * @brief  DMA transfer complete error callback.
00275   * @param  hdma: DMA handle
00276   * @retval None
00277   */
00278 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00279 {
00280   /* Prevent unused argument(s) compilation warning */
00281   UNUSED(hdma);
00282   /* NOTE: This function Should not be modified, when the callback is needed,
00283             the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
00284    */
00285 }
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
00291   * @brief    Input Output and memory control functions
00292   *
00293   @verbatim
00294   ==============================================================================
00295                     ##### SDRAM Input and Output functions #####
00296   ==============================================================================
00297   [..]
00298     This section provides functions allowing to use and control the SDRAM memory
00299
00300 @endverbatim
00301   * @{
00302   */
00303
00304 /**
00305   * @brief  Reads 8-bit data buffer from the SDRAM memory.
00306   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00307   *                the configuration information for SDRAM module.
00308   * @param  pAddress: Pointer to read start address
00309   * @param  pDstBuffer: Pointer to destination buffer
00310   * @param  BufferSize: Size of the buffer to read from memory
00311   * @retval HAL status
00312   */
00313 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00314 {
00315   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00316
00317   /* Process Locked */
00318   __HAL_LOCK(hsdram);
00319
00320   /* Check the SDRAM controller state */
00321   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00322   {
00323     return HAL_BUSY;
00324   }
00325   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00326   {
00327     return  HAL_ERROR;
00328   }
00329
00330   /* Read data from source */
00331   for(; BufferSize != 0U; BufferSize--)
00332   {
00333     *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
00334     pDstBuffer++;
00335     pSdramAddress++;
00336   }
00337
00338   /* Process Unlocked */
00339   __HAL_UNLOCK(hsdram);
00340
00341   return HAL_OK;
00342 }
00343
00344 /**
00345   * @brief  Writes 8-bit data buffer to SDRAM memory.
00346   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00347   *                the configuration information for SDRAM module.
00348   * @param  pAddress: Pointer to write start address
00349   * @param  pSrcBuffer: Pointer to source buffer to write
00350   * @param  BufferSize: Size of the buffer to write to memory
00351   * @retval HAL status
00352   */
00353 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00354 {
00355   __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
00356   uint32_t tmp = 0U;
00357
00358   /* Process Locked */
00359   __HAL_LOCK(hsdram);
00360
00361   /* Check the SDRAM controller state */
00362   tmp = hsdram->State;
00363
00364   if(tmp == HAL_SDRAM_STATE_BUSY)
00365   {
00366     return HAL_BUSY;
00367   }
00368   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00369   {
00370     return  HAL_ERROR;
00371   }
00372
00373   /* Write data to memory */
00374   for(; BufferSize != 0U; BufferSize--)
00375   {
00376     *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
00377     pSrcBuffer++;
00378     pSdramAddress++;
00379   }
00380
00381   /* Process Unlocked */
00382   __HAL_UNLOCK(hsdram);
00383
00384   return HAL_OK;
00385 }
00386
00387 /**
00388   * @brief  Reads 16-bit data buffer from the SDRAM memory.
00389   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00390   *                the configuration information for SDRAM module.
00391   * @param  pAddress: Pointer to read start address
00392   * @param  pDstBuffer: Pointer to destination buffer
00393   * @param  BufferSize: Size of the buffer to read from memory
00394   * @retval HAL status
00395   */
00396 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00397 {
00398   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
00399
00400   /* Process Locked */
00401   __HAL_LOCK(hsdram);
00402
00403   /* Check the SDRAM controller state */
00404   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00405   {
00406     return HAL_BUSY;
00407   }
00408   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00409   {
00410     return  HAL_ERROR;
00411   }
00412
00413   /* Read data from source */
00414   for(; BufferSize != 0U; BufferSize--)
00415   {
00416     *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
00417     pDstBuffer++;
00418     pSdramAddress++;
00419   }
00420
00421   /* Process Unlocked */
00422   __HAL_UNLOCK(hsdram);
00423
00424   return HAL_OK;
00425 }
00426
00427 /**
00428   * @brief  Writes 16-bit data buffer to SDRAM memory.
00429   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00430   *                the configuration information for SDRAM module.
00431   * @param  pAddress: Pointer to write start address
00432   * @param  pSrcBuffer: Pointer to source buffer to write
00433   * @param  BufferSize: Size of the buffer to write to memory
00434   * @retval HAL status
00435   */
00436 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00437 {
00438   __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
00439   uint32_t tmp = 0U;
00440
00441   /* Process Locked */
00442   __HAL_LOCK(hsdram);
00443
00444   /* Check the SDRAM controller state */
00445   tmp = hsdram->State;
00446
00447   if(tmp == HAL_SDRAM_STATE_BUSY)
00448   {
00449     return HAL_BUSY;
00450   }
00451   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00452   {
00453     return  HAL_ERROR;
00454   }
00455
00456   /* Write data to memory */
00457   for(; BufferSize != 0U; BufferSize--)
00458   {
00459     *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
00460     pSrcBuffer++;
00461     pSdramAddress++;
00462   }
00463
00464   /* Process Unlocked */
00465   __HAL_UNLOCK(hsdram);
00466
00467   return HAL_OK;
00468 }
00469
00470 /**
00471   * @brief  Reads 32-bit data buffer from the SDRAM memory.
00472   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00473   *                the configuration information for SDRAM module.
00474   * @param  pAddress: Pointer to read start address
00475   * @param  pDstBuffer: Pointer to destination buffer
00476   * @param  BufferSize: Size of the buffer to read from memory
00477   * @retval HAL status
00478   */
00479 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00480 {
00481   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
00482
00483   /* Process Locked */
00484   __HAL_LOCK(hsdram);
00485
00486   /* Check the SDRAM controller state */
00487   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00488   {
00489     return HAL_BUSY;
00490   }
00491   else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
00492   {
00493     return  HAL_ERROR;
00494   }
00495
00496   /* Read data from source */
00497   for(; BufferSize != 0U; BufferSize--)
00498   {
00499     *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
00500     pDstBuffer++;
00501     pSdramAddress++;
00502   }
00503
00504   /* Process Unlocked */
00505   __HAL_UNLOCK(hsdram);
00506
00507   return HAL_OK;
00508 }
00509
00510 /**
00511   * @brief  Writes 32-bit data buffer to SDRAM memory.
00512   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00513   *                the configuration information for SDRAM module.
00514   * @param  pAddress: Pointer to write start address
00515   * @param  pSrcBuffer: Pointer to source buffer to write
00516   * @param  BufferSize: Size of the buffer to write to memory
00517   * @retval HAL status
00518   */
00519 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00520 {
00521   __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
00522   uint32_t tmp = 0U;
00523
00524   /* Process Locked */
00525   __HAL_LOCK(hsdram);
00526
00527   /* Check the SDRAM controller state */
00528   tmp = hsdram->State;
00529
00530   if(tmp == HAL_SDRAM_STATE_BUSY)
00531   {
00532     return HAL_BUSY;
00533   }
00534   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00535   {
00536     return  HAL_ERROR;
00537   }
00538
00539   /* Write data to memory */
00540   for(; BufferSize != 0U; BufferSize--)
00541   {
00542     *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
00543     pSrcBuffer++;
00544     pSdramAddress++;
00545   }
00546
00547   /* Process Unlocked */
00548   __HAL_UNLOCK(hsdram);
00549
00550   return HAL_OK;
00551 }
00552
00553 /**
00554   * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
00555   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00556   *                the configuration information for SDRAM module.
00557   * @param  pAddress: Pointer to read start address
00558   * @param  pDstBuffer: Pointer to destination buffer
00559   * @param  BufferSize: Size of the buffer to read from memory
00560   * @retval HAL status
00561   */
00562 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00563 {
00564   uint32_t tmp = 0U;
00565
00566   /* Process Locked */
00567   __HAL_LOCK(hsdram);
00568
00569   /* Check the SDRAM controller state */
00570   tmp = hsdram->State;
00571
00572   if(tmp == HAL_SDRAM_STATE_BUSY)
00573   {
00574     return HAL_BUSY;
00575   }
00576   else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
00577   {
00578     return  HAL_ERROR;
00579   }
00580
00581   /* Configure DMA user callbacks */
00582   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
00583   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00584
00585   /* Enable the DMA Stream */
00586   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00587
00588   /* Process Unlocked */
00589   __HAL_UNLOCK(hsdram);
00590
00591   return HAL_OK;
00592 }
00593
00594 /**
00595   * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
00596   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00597   *                the configuration information for SDRAM module.
00598   * @param  pAddress: Pointer to write start address
00599   * @param  pSrcBuffer: Pointer to source buffer to write
00600   * @param  BufferSize: Size of the buffer to write to memory
00601   * @retval HAL status
00602   */
00603 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00604 {
00605   uint32_t tmp = 0U;
00606
00607   /* Process Locked */
00608   __HAL_LOCK(hsdram);
00609
00610   /* Check the SDRAM controller state */
00611   tmp = hsdram->State;
00612
00613   if(tmp == HAL_SDRAM_STATE_BUSY)
00614   {
00615     return HAL_BUSY;
00616   }
00617   else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
00618   {
00619     return  HAL_ERROR;
00620   }
00621
00622   /* Configure DMA user callbacks */
00623   hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
00624   hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
00625
00626   /* Enable the DMA Stream */
00627   HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00628
00629   /* Process Unlocked */
00630   __HAL_UNLOCK(hsdram);
00631
00632   return HAL_OK;
00633 }
00634 /**
00635   * @}
00636   */
00637
00638 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
00639  *  @brief   management functions
00640  *
00641 @verbatim
00642   ==============================================================================
00643                          ##### SDRAM Control functions #####
00644   ==============================================================================
00645   [..]
00646     This subsection provides a set of functions allowing to control dynamically
00647     the SDRAM interface.
00648
00649 @endverbatim
00650   * @{
00651   */
00652
00653 /**
00654   * @brief  Enables dynamically SDRAM write protection.
00655   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00656   *                the configuration information for SDRAM module.
00657   * @retval HAL status
00658   */
00659 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
00660 {
00661   /* Check the SDRAM controller state */
00662   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00663   {
00664     return HAL_BUSY;
00665   }
00666
00667   /* Update the SDRAM state */
00668   hsdram->State = HAL_SDRAM_STATE_BUSY;
00669
00670   /* Enable write protection */
00671   FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
00672
00673   /* Update the SDRAM state */
00674   hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
00675
00676   return HAL_OK;
00677 }
00678
00679 /**
00680   * @brief  Disables dynamically SDRAM write protection.
00681   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00682   *                the configuration information for SDRAM module.
00683   * @retval HAL status
00684   */
00685 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
00686 {
00687   /* Check the SDRAM controller state */
00688   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00689   {
00690     return HAL_BUSY;
00691   }
00692
00693   /* Update the SDRAM state */
00694   hsdram->State = HAL_SDRAM_STATE_BUSY;
00695
00696   /* Disable write protection */
00697   FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
00698
00699   /* Update the SDRAM state */
00700   hsdram->State = HAL_SDRAM_STATE_READY;
00701
00702   return HAL_OK;
00703 }
00704
00705 /**
00706   * @brief  Sends Command to the SDRAM bank.
00707   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00708   *                the configuration information for SDRAM module.
00709   * @param  Command: SDRAM command structure
00710   * @param  Timeout: Timeout duration
00711   * @retval HAL status
00712   */
00713 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
00714 {
00715   /* Check the SDRAM controller state */
00716   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00717   {
00718     return HAL_BUSY;
00719   }
00720
00721   /* Update the SDRAM state */
00722   hsdram->State = HAL_SDRAM_STATE_BUSY;
00723
00724   /* Send SDRAM command */
00725   FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
00726
00727   /* Update the SDRAM controller state */
00728   if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
00729   {
00730     hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
00731   }
00732   else
00733   {
00734     hsdram->State = HAL_SDRAM_STATE_READY;
00735   }
00736
00737   return HAL_OK;
00738 }
00739
00740 /**
00741   * @brief  Programs the SDRAM Memory Refresh rate.
00742   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00743   *                the configuration information for SDRAM module.
00744   * @param  RefreshRate: The SDRAM refresh rate value
00745   * @retval HAL status
00746   */
00747 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
00748 {
00749   /* Check the SDRAM controller state */
00750   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00751   {
00752     return HAL_BUSY;
00753   }
00754
00755   /* Update the SDRAM state */
00756   hsdram->State = HAL_SDRAM_STATE_BUSY;
00757
00758   /* Program the refresh rate */
00759   FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
00760
00761   /* Update the SDRAM state */
00762   hsdram->State = HAL_SDRAM_STATE_READY;
00763
00764   return HAL_OK;
00765 }
00766
00767 /**
00768   * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
00769   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00770   *                the configuration information for SDRAM module.
00771   * @param  AutoRefreshNumber: The SDRAM auto Refresh number
00772   * @retval HAL status
00773   */
00774 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
00775 {
00776   /* Check the SDRAM controller state */
00777   if(hsdram->State == HAL_SDRAM_STATE_BUSY)
00778   {
00779     return HAL_BUSY;
00780   }
00781
00782   /* Update the SDRAM state */
00783   hsdram->State = HAL_SDRAM_STATE_BUSY;
00784
00785   /* Set the Auto-Refresh number */
00786   FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
00787
00788   /* Update the SDRAM state */
00789   hsdram->State = HAL_SDRAM_STATE_READY;
00790
00791   return HAL_OK;
00792 }
00793
00794 /**
00795   * @brief  Returns the SDRAM memory current mode.
00796   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00797   *                the configuration information for SDRAM module.
00798   * @retval The SDRAM memory mode.
00799   */
00800 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
00801 {
00802   /* Return the SDRAM memory current mode */
00803   return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
00804 }
00805
00806 /**
00807   * @}
00808   */
00809
00810 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
00811  *  @brief   Peripheral State functions
00812  *
00813 @verbatim
00814   ==============================================================================
00815                       ##### SDRAM State functions #####
00816   ==============================================================================
00817   [..]
00818     This subsection permits to get in run-time the status of the SDRAM controller
00819     and the data flow.
00820
00821 @endverbatim
00822   * @{
00823   */
00824
00825 /**
00826   * @brief  Returns the SDRAM state.
00827   * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
00828   *                the configuration information for SDRAM module.
00829   * @retval HAL state
00830   */
00831 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
00832 {
00833   return hsdram->State;
00834 }
00835
00836 /**
00837   * @}
00838   */
00839
00840 /**
00841   * @}
00842   */
00843 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00844 #endif /* HAL_SDRAM_MODULE_ENABLED */
00845 /**
00846   * @}
00847   */
00848
00849 /**
00850   * @}
00851   */
00852
00853 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sdram.h Source File

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stm32f4xx_hal_sdram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sdram.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SDRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SDRAM_H
00040 #define __STM32F4xx_HAL_SDRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00047     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f4xx_ll_fmc.h"
00051
00052 /** @addtogroup STM32F4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup SDRAM
00057   * @{
00058   */
00059
00060 /* Exported typedef ----------------------------------------------------------*/
00061 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  HAL SDRAM State structure definition
00067   */
00068 typedef enum
00069 {
00070   HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */
00071   HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */
00072   HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */
00073   HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */
00074   HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */
00075   HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */
00076
00077 }HAL_SDRAM_StateTypeDef;
00078
00079 /**
00080   * @brief  SDRAM handle Structure definition
00081   */
00082 typedef struct
00083 {
00084   FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */
00085
00086   FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */
00087
00088   __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */
00089
00090   HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */
00091
00092   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                   */
00093
00094 }SDRAM_HandleTypeDef;
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100 /* Exported macro ------------------------------------------------------------*/
00101 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
00102   * @{
00103   */
00104
00105 /** @brief Reset SDRAM handle state
00106   * @param  __HANDLE__: specifies the SDRAM handle.
00107   * @retval None
00108   */
00109 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
00116   * @{
00117   */
00118
00119 /** @addtogroup SDRAM_Exported_Functions_Group1
00120   * @{
00121   */
00122
00123 /* Initialization/de-initialization functions *********************************/
00124 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
00125 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
00126 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
00127 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
00128
00129 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
00130 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
00131 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00132 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00133 /**
00134   * @}
00135   */
00136
00137 /** @addtogroup SDRAM_Exported_Functions_Group2
00138   * @{
00139   */
00140 /* I/O operation functions ****************************************************/
00141 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00142 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00143 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00144 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00145 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00146 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00147
00148 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00149 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00150 /**
00151   * @}
00152   */
00153
00154 /** @addtogroup SDRAM_Exported_Functions_Group3
00155   * @{
00156   */
00157 /* SDRAM Control functions  *****************************************************/
00158 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
00159 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
00160 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
00161 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
00162 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
00163 uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
00164 /**
00165   * @}
00166   */
00167
00168 /** @addtogroup SDRAM_Exported_Functions_Group4
00169   * @{
00170   */
00171 /* SDRAM State functions ********************************************************/
00172 HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
00173 /**
00174   * @}
00175   */
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00186
00187 /**
00188   * @}
00189   */
00190
00191 #ifdef __cplusplus
00192 }
00193 #endif
00194
00195 #endif /* __STM32F4xx_HAL_SDRAM_H */
00196
00197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_smartcard.c Source File

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stm32f4xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   SMARTCARD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the SMARTCARD peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       The SMARTCARD HAL driver can be used as follows:
00020
00021     (#) Declare a SMARTCARD_HandleTypeDef handle structure.
00022     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00023         (##) Enable the USARTx interface clock.
00024         (##) SMARTCARD pins configuration:
00025             (+++) Enable the clock for the SMARTCARD GPIOs.
00026             (+++) Configure these SMARTCARD pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00028              and HAL_SMARTCARD_Receive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031         (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00032              and HAL_SMARTCARD_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036             (+++) Configure the DMA Tx/Rx Stream.
00037             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
00039
00040     (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
00041         flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
00042
00043     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00044         (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00045              by calling the customized HAL_SMARTCARD_MspInit() API.
00046     [..]
00047     (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00048         RXNE interrupt and Error Interrupts) will be managed using the macros
00049         __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00050
00051     [..]
00052     Three operation modes are available within this driver :
00053
00054     *** Polling mode IO operation ***
00055     =================================
00056     [..]
00057       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00058       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00059
00060     *** Interrupt mode IO operation ***
00061     ===================================
00062     [..]
00063       (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
00064       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
00065           add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
00066       (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
00067       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
00068           add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
00069       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00070           add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
00071
00072     *** DMA mode IO operation ***
00073     ==============================
00074     [..]
00075       (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00076       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
00077           add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
00078       (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00079       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
00080           add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
00081       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00082           add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
00083
00084     *** SMARTCARD HAL driver macros list ***
00085     =============================================
00086     [..]
00087       Below the list of most used macros in SMARTCARD HAL driver.
00088
00089       (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
00090       (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
00091       (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
00092       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00093       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00094       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00095
00096     [..]
00097       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00098
00099   @endverbatim
00100   ******************************************************************************
00101   * @attention
00102   *
00103   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00104   *
00105   * Redistribution and use in source and binary forms, with or without modification,
00106   * are permitted provided that the following conditions are met:
00107   *   1. Redistributions of source code must retain the above copyright notice,
00108   *      this list of conditions and the following disclaimer.
00109   *   2. Redistributions in binary form must reproduce the above copyright notice,
00110   *      this list of conditions and the following disclaimer in the documentation
00111   *      and/or other materials provided with the distribution.
00112   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00113   *      may be used to endorse or promote products derived from this software
00114   *      without specific prior written permission.
00115   *
00116   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00117   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00118   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00119   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00120   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00121   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00122   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00123   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00124   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00125   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00126   *
00127   ******************************************************************************
00128   */
00129
00130 /* Includes ------------------------------------------------------------------*/
00131 #include "stm32f4xx_hal.h"
00132
00133 /** @addtogroup STM32F4xx_HAL_Driver
00134   * @{
00135   */
00136
00137 /** @defgroup SMARTCARD SMARTCARD
00138   * @brief HAL USART SMARTCARD module driver
00139   * @{
00140   */
00141 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00142 /* Private typedef -----------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /** @addtogroup SMARTCARD_Private_Constants
00145   * @{
00146   */
00147 /**
00148   * @}
00149   */
00150 /* Private macro -------------------------------------------------------------*/
00151 /* Private variables ---------------------------------------------------------*/
00152 /* Private function prototypes -----------------------------------------------*/
00153 /** @addtogroup SMARTCARD_Private_Functions
00154   * @{
00155   */
00156 static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
00157 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
00158 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00159 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
00160 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00161 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00162 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00163 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00164 /**
00165   * @}
00166   */
00167 /* Exported functions --------------------------------------------------------*/
00168 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00169   * @{
00170   */
00171
00172 /** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
00173   *  @brief    Initialization and Configuration functions
00174   *
00175 @verbatim
00176   ==============================================================================
00177               ##### Initialization and Configuration functions #####
00178   ==============================================================================
00179   [..]
00180   This subsection provides a set of functions allowing to initialize the USART
00181   in Smartcard mode.
00182   [..]
00183   The Smartcard interface is designed to support asynchronous protocol Smartcards as
00184   defined in the ISO 7816-3 standard.
00185   [..]
00186   The USART can provide a clock to the smartcard through the SCLK output.
00187   In smartcard mode, SCLK is not associated to the communication but is simply derived
00188   from the internal peripheral input clock through a 5-bit prescaler.
00189   [..]
00190   (+) For the Smartcard mode only these parameters can be configured:
00191       (++) Baud Rate
00192       (++) Word Length => Should be 9 bits (8 bits + parity)
00193       (++) Stop Bit
00194       (++) Parity: => Should be enabled
00195
00196       (+++) +-------------------------------------------------------------+
00197       (+++) |   M bit |  PCE bit  |        SMARTCARD frame                |
00198       (+++) |---------------------|---------------------------------------|
00199       (+++) |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00200       (+++) +-------------------------------------------------------------+
00201
00202       (++) USART polarity
00203       (++) USART phase
00204       (++) USART LastBit
00205       (++) Receiver/transmitter modes
00206       (++) Prescaler
00207       (++) GuardTime
00208       (++) NACKState: The Smartcard NACK state
00209
00210      (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
00211         (++) Word Length = 9 Bits
00212         (++) 1.5 Stop Bit
00213         (++) Even parity
00214         (++) BaudRate = 12096 baud
00215         (++) Tx and Rx enabled
00216   [..]
00217   Please refer to the ISO 7816-3 specification for more details.
00218
00219     -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
00220         to use 1.5 stop bits for both transmitting and receiving to avoid switching
00221         between the two configurations.
00222   [..]
00223     The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration
00224     procedure (details for the procedure are available in reference manual (RM0329)).
00225
00226 @endverbatim
00227   * @{
00228   */
00229
00230 /**
00231   * @brief Initializes the SmartCard mode according to the specified
00232   *         parameters in the SMARTCARD_InitTypeDef and create the associated handle .
00233   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00234   *                the configuration information for SMARTCARD module.
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
00238 {
00239   /* Check the SMARTCARD handle allocation */
00240   if(hsc == NULL)
00241   {
00242     return HAL_ERROR;
00243   }
00244
00245   /* Check the parameters */
00246   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
00247   assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
00248
00249   if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
00250   {
00251     /* Allocate lock resource and initialize it */
00252     hsc->Lock = HAL_UNLOCKED;
00253     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00254     HAL_SMARTCARD_MspInit(hsc);
00255   }
00256
00257   hsc->gState = HAL_SMARTCARD_STATE_BUSY;
00258
00259   /* Set the Prescaler */
00260   MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
00261
00262   /* Set the Guard Time */
00263   MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8));
00264
00265   /* Set the Smartcard Communication parameters */
00266   SMARTCARD_SetConfig(hsc);
00267
00268   /* In SmartCard mode, the following bits must be kept cleared:
00269   - LINEN bit in the USART_CR2 register
00270   - HDSEL and IREN bits in the USART_CR3 register.*/
00271   hsc->Instance->CR2 &= ~USART_CR2_LINEN;
00272   hsc->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_HDSEL);
00273
00274   /* Enable the SMARTCARD Parity Error Interrupt */
00275   __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
00276
00277   /* Enable the SMARTCARD Framing Error Interrupt */
00278   __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
00279
00280   /* Enable the Peripheral */
00281   __HAL_SMARTCARD_ENABLE(hsc);
00282
00283   /* Configure the Smartcard NACK state */
00284   MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
00285
00286   /* Enable the SC mode by setting the SCEN bit in the CR3 register */
00287   hsc->Instance->CR3 |= (USART_CR3_SCEN);
00288
00289   /* Initialize the SMARTCARD state*/
00290   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00291   hsc->gState= HAL_SMARTCARD_STATE_READY;
00292   hsc->RxState= HAL_SMARTCARD_STATE_READY;
00293
00294   return HAL_OK;
00295 }
00296
00297 /**
00298   * @brief DeInitializes the USART SmartCard peripheral
00299   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00300   *                the configuration information for SMARTCARD module.
00301   * @retval HAL status
00302   */
00303 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
00304 {
00305   /* Check the SMARTCARD handle allocation */
00306   if(hsc == NULL)
00307   {
00308     return HAL_ERROR;
00309   }
00310
00311   /* Check the parameters */
00312   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
00313
00314   hsc->gState = HAL_SMARTCARD_STATE_BUSY;
00315
00316   /* Disable the Peripheral */
00317   __HAL_SMARTCARD_DISABLE(hsc);
00318
00319   /* DeInit the low level hardware */
00320   HAL_SMARTCARD_MspDeInit(hsc);
00321
00322   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00323   hsc->gState = HAL_SMARTCARD_STATE_RESET;
00324   hsc->RxState = HAL_SMARTCARD_STATE_RESET;
00325
00326   /* Release Lock */
00327   __HAL_UNLOCK(hsc);
00328
00329   return HAL_OK;
00330 }
00331
00332 /**
00333   * @brief SMARTCARD MSP Init
00334   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00335   *                the configuration information for SMARTCARD module.
00336   * @retval None
00337   */
00338  __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
00339 {
00340   /* Prevent unused argument(s) compilation warning */
00341   UNUSED(hsc);
00342   /* NOTE : This function Should not be modified, when the callback is needed,
00343             the HAL_SMARTCARD_MspInit could be implemented in the user file
00344    */
00345 }
00346
00347 /**
00348   * @brief SMARTCARD MSP DeInit
00349   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00350   *                the configuration information for SMARTCARD module.
00351   * @retval None
00352   */
00353  __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hsc);
00357   /* NOTE : This function Should not be modified, when the callback is needed,
00358             the HAL_SMARTCARD_MspDeInit could be implemented in the user file
00359    */
00360 }
00361
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00367   *  @brief   SMARTCARD Transmit and Receive functions
00368   *
00369 @verbatim
00370  ===============================================================================
00371                       ##### IO operation functions #####
00372  ===============================================================================
00373     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00374     [..]
00375     Smartcard is a single wire half duplex communication protocol.
00376     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00377     defined in the ISO 7816-3 standard. The USART should be configured as:
00378     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00379     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00380
00381     (#) There are two modes of transfer:
00382        (++) Blocking mode: The communication is performed in polling mode.
00383             The HAL status of all data processing is returned by the same function
00384             after finishing transfer.
00385        (++) Non Blocking mode: The communication is performed using Interrupts
00386            or DMA, These APIs return the HAL status.
00387            The end of the data processing will be indicated through the
00388            dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00389            using DMA mode.
00390            The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00391            will be executed respectively at the end of the Transmit or Receive process
00392            The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
00393
00394     (#) Blocking mode APIs are :
00395         (++) HAL_SMARTCARD_Transmit()
00396         (++) HAL_SMARTCARD_Receive()
00397
00398     (#) Non Blocking mode APIs with Interrupt are :
00399         (++) HAL_SMARTCARD_Transmit_IT()
00400         (++) HAL_SMARTCARD_Receive_IT()
00401         (++) HAL_SMARTCARD_IRQHandler()
00402
00403     (#) Non Blocking mode functions with DMA are :
00404         (++) HAL_SMARTCARD_Transmit_DMA()
00405         (++) HAL_SMARTCARD_Receive_DMA()
00406
00407     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00408         (++) HAL_SMARTCARD_TxCpltCallback()
00409         (++) HAL_SMARTCARD_RxCpltCallback()
00410         (++) HAL_SMARTCARD_ErrorCallback()
00411
00412 @endverbatim
00413   * @{
00414   */
00415
00416 /**
00417   * @brief Send an amount of data in blocking mode
00418   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00419   *                the configuration information for SMARTCARD module.
00420   * @param pData: pointer to data buffer
00421   * @param Size: amount of data to be sent
00422   * @param Timeout: Timeout duration
00423   * @retval HAL status
00424   */
00425 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00426 {
00427   uint16_t* tmp;
00428
00429   if(hsc->gState == HAL_SMARTCARD_STATE_READY)
00430   {
00431     if((pData == NULL) || (Size == 0U))
00432     {
00433       return  HAL_ERROR;
00434     }
00435
00436     /* Process Locked */
00437     __HAL_LOCK(hsc);
00438
00439     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00440     hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00441
00442     hsc->TxXferSize = Size;
00443     hsc->TxXferCount = Size;
00444     while(hsc->TxXferCount > 0U)
00445     {
00446       hsc->TxXferCount--;
00447       if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
00448       {
00449         return HAL_TIMEOUT;
00450       }
00451       tmp = (uint16_t*) pData;
00452       hsc->Instance->DR = (*tmp & (uint16_t)0x01FFU);
00453       pData +=1U;
00454     }
00455
00456     if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
00457     {
00458       return HAL_TIMEOUT;
00459     }
00460
00461         /* At end of Tx process, restore hsc->gState to Ready */
00462     hsc->gState = HAL_SMARTCARD_STATE_READY;
00463
00464     /* Process Unlocked */
00465     __HAL_UNLOCK(hsc);
00466
00467     return HAL_OK;
00468   }
00469   else
00470   {
00471     return HAL_BUSY;
00472   }
00473 }
00474
00475 /**
00476   * @brief Receive an amount of data in blocking mode
00477   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00478   *                the configuration information for SMARTCARD module.
00479   * @param pData: pointer to data buffer
00480   * @param Size: amount of data to be received
00481   * @param Timeout: Timeout duration
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00485 {
00486   uint16_t* tmp;
00487
00488   if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
00489   {
00490     if((pData == NULL) || (Size == 0U))
00491     {
00492       return  HAL_ERROR;
00493     }
00494
00495     /* Process Locked */
00496     __HAL_LOCK(hsc);
00497
00498     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00499     hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
00500
00501     hsc->RxXferSize = Size;
00502     hsc->RxXferCount = Size;
00503
00504     /* Check the remain data to be received */
00505     while(hsc->RxXferCount > 0U)
00506     {
00507       hsc->RxXferCount--;
00508       if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00509       {
00510         return HAL_TIMEOUT;
00511       }
00512       tmp = (uint16_t*) pData;
00513       *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FFU);
00514       pData +=1U;
00515     }
00516
00517         /* At end of Rx process, restore hsc->RxState to Ready */
00518     hsc->RxState = HAL_SMARTCARD_STATE_READY;
00519
00520     /* Process Unlocked */
00521     __HAL_UNLOCK(hsc);
00522
00523     return HAL_OK;
00524   }
00525   else
00526   {
00527     return HAL_BUSY;
00528   }
00529 }
00530
00531 /**
00532   * @brief Send an amount of data in non blocking mode
00533   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00534   *                the configuration information for SMARTCARD module.
00535   * @param pData: pointer to data buffer
00536   * @param Size: amount of data to be sent
00537   * @retval HAL status
00538   */
00539 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00540 {
00541   /* Check that a Tx process is not already ongoing */
00542   if(hsc->gState == HAL_SMARTCARD_STATE_READY)
00543   {
00544     if((pData == NULL) || (Size == 0U))
00545     {
00546       return HAL_ERROR;
00547     }
00548
00549     /* Process Locked */
00550     __HAL_LOCK(hsc);
00551
00552     hsc->pTxBuffPtr = pData;
00553     hsc->TxXferSize = Size;
00554     hsc->TxXferCount = Size;
00555
00556     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00557     hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00558
00559     /* Process Unlocked */
00560     __HAL_UNLOCK(hsc);
00561
00562     /* Enable the SMARTCARD Parity Error Interrupt */
00563     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
00564
00565     /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00566     __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
00567
00568     /* Enable the SMARTCARD Transmit data register empty Interrupt */
00569     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
00570
00571     return HAL_OK;
00572   }
00573   else
00574   {
00575     return HAL_BUSY;
00576   }
00577 }
00578
00579 /**
00580   * @brief Receive an amount of data in non blocking mode
00581   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00582   *                the configuration information for SMARTCARD module.
00583   * @param pData: pointer to data buffer
00584   * @param Size: amount of data to be received
00585   * @retval HAL status
00586   */
00587 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00588 {
00589   /* Check that a Rx process is not already ongoing */
00590   if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
00591   {
00592     if((pData == NULL) || (Size == 0U))
00593     {
00594       return HAL_ERROR;
00595     }
00596
00597     /* Process Locked */
00598     __HAL_LOCK(hsc);
00599
00600     hsc->pRxBuffPtr = pData;
00601     hsc->RxXferSize = Size;
00602     hsc->RxXferCount = Size;
00603
00604     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00605     hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
00606
00607     /* Process Unlocked */
00608     __HAL_UNLOCK(hsc);
00609
00610     /* Enable the SMARTCARD Data Register not empty Interrupt */
00611     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
00612
00613     /* Enable the SMARTCARD Parity Error Interrupt */
00614     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
00615
00616     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00617     __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
00618
00619     return HAL_OK;
00620   }
00621   else
00622   {
00623     return HAL_BUSY;
00624   }
00625 }
00626
00627 /**
00628   * @brief Send an amount of data in non blocking mode
00629   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00630   *                the configuration information for SMARTCARD module.
00631   * @param pData: pointer to data buffer
00632   * @param Size: amount of data to be sent
00633   * @retval HAL status
00634   */
00635 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00636 {
00637   uint32_t *tmp;
00638
00639   /* Check that a Tx process is not already ongoing */
00640   if(hsc->gState == HAL_SMARTCARD_STATE_READY)
00641   {
00642     if((pData == NULL) || (Size == 0U))
00643     {
00644       return HAL_ERROR;
00645     }
00646
00647     /* Process Locked */
00648     __HAL_LOCK(hsc);
00649
00650     hsc->pTxBuffPtr = pData;
00651     hsc->TxXferSize = Size;
00652     hsc->TxXferCount = Size;
00653
00654     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00655     hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00656
00657     /* Set the SMARTCARD DMA transfer complete callback */
00658     hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
00659
00660     /* Set the DMA error callback */
00661     hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
00662
00663     /* Enable the SMARTCARD transmit DMA Stream */
00664     tmp = (uint32_t*)&pData;
00665     HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
00666
00667      /* Clear the TC flag in the SR register by writing 0 to it */
00668     __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
00669
00670     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00671     in the SMARTCARD CR3 register */
00672     hsc->Instance->CR3 |= USART_CR3_DMAT;
00673
00674     /* Process Unlocked */
00675     __HAL_UNLOCK(hsc);
00676
00677     return HAL_OK;
00678   }
00679   else
00680   {
00681     return HAL_BUSY;
00682   }
00683 }
00684
00685 /**
00686   * @brief Receive an amount of data in non blocking mode
00687   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00688   *                the configuration information for SMARTCARD module.
00689   * @param pData: pointer to data buffer
00690   * @param Size: amount of data to be received
00691   * @note   When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
00692   * @retval HAL status
00693   */
00694 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00695 {
00696   uint32_t *tmp;
00697
00698   /* Check that a Rx process is not already ongoing */
00699   if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
00700   {
00701     if((pData == NULL) || (Size == 0U))
00702     {
00703       return HAL_ERROR;
00704     }
00705
00706     /* Process Locked */
00707     __HAL_LOCK(hsc);
00708
00709     hsc->pRxBuffPtr = pData;
00710     hsc->RxXferSize = Size;
00711
00712     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00713     hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
00714
00715     /* Set the SMARTCARD DMA transfer complete callback */
00716     hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
00717
00718     /* Set the DMA error callback */
00719     hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
00720
00721     /* Enable the DMA Stream */
00722     tmp = (uint32_t*)&pData;
00723     HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
00724
00725     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00726     in the SMARTCARD CR3 register */
00727     hsc->Instance->CR3 |= USART_CR3_DMAR;
00728
00729     /* Process Unlocked */
00730     __HAL_UNLOCK(hsc);
00731
00732     return HAL_OK;
00733   }
00734   else
00735   {
00736     return HAL_BUSY;
00737   }
00738 }
00739
00740 /**
00741   * @brief This function handles SMARTCARD interrupt request.
00742   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00743   *                the configuration information for SMARTCARD module.
00744   * @retval None
00745   */
00746 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
00747 {
00748   uint32_t tmp1 = 0U, tmp2 = 0U;
00749
00750   tmp1 = hsc->Instance->SR;
00751   tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
00752
00753   /* SMARTCARD parity error interrupt occurred --------------------------------*/
00754   if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
00755   {
00756     __HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
00757     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
00758   }
00759
00760   tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
00761   /* SMARTCARD frame error interrupt occurred ---------------------------------*/
00762   if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
00763   {
00764     __HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
00765     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
00766   }
00767
00768   tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
00769   /* SMARTCARD noise error interrupt occurred ---------------------------------*/
00770   if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
00771   {
00772     __HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
00773     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
00774   }
00775
00776   tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
00777   /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/
00778   if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
00779   {
00780     __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
00781     hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
00782   }
00783
00784   tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
00785   /* SMARTCARD in mode Receiver ----------------------------------------------*/
00786   if(((tmp1 & SMARTCARD_FLAG_RXNE) != RESET) && (tmp2 != RESET))
00787   {
00788     SMARTCARD_Receive_IT(hsc);
00789   }
00790
00791   tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE);
00792   /* SMARTCARD in mode Transmitter -------------------------------------------*/
00793   if(((tmp1 & SMARTCARD_FLAG_TXE) != RESET) && (tmp2 != RESET))
00794   {
00795     SMARTCARD_Transmit_IT(hsc);
00796   }
00797
00798   tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
00799   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
00800   if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
00801   {
00802     SMARTCARD_EndTransmit_IT(hsc);
00803   }
00804
00805   /* Call the Error call Back in case of Errors */
00806   if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
00807   {
00808     /* Set the SMARTCARD state ready to be able to start again the process */
00809     hsc->gState= HAL_SMARTCARD_STATE_READY;
00810     hsc->RxState= HAL_SMARTCARD_STATE_READY;
00811     HAL_SMARTCARD_ErrorCallback(hsc);
00812   }
00813 }
00814
00815 /**
00816   * @brief Tx Transfer completed callbacks
00817   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00818   *                the configuration information for SMARTCARD module.
00819   * @retval None
00820   */
00821  __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
00822 {
00823   /* Prevent unused argument(s) compilation warning */
00824   UNUSED(hsc);
00825   /* NOTE : This function Should not be modified, when the callback is needed,
00826             the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
00827    */
00828 }
00829
00830 /**
00831   * @brief Rx Transfer completed callbacks
00832   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00833   *                the configuration information for SMARTCARD module.
00834   * @retval None
00835   */
00836 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
00837 {
00838   /* Prevent unused argument(s) compilation warning */
00839   UNUSED(hsc);
00840   /* NOTE : This function Should not be modified, when the callback is needed,
00841             the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
00842    */
00843 }
00844
00845 /**
00846   * @brief SMARTCARD error callbacks
00847   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00848   *                the configuration information for SMARTCARD module.
00849   * @retval None
00850   */
00851  __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
00852 {
00853   /* Prevent unused argument(s) compilation warning */
00854   UNUSED(hsc);
00855   /* NOTE : This function Should not be modified, when the callback is needed,
00856             the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
00857    */
00858 }
00859
00860 /**
00861   * @}
00862   */
00863
00864 /** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
00865   *  @brief   SMARTCARD State and Errors functions
00866   *
00867 @verbatim
00868  ===============================================================================
00869                 ##### Peripheral State and Errors functions #####
00870  ===============================================================================
00871     [..]
00872     This subsection provides a set of functions allowing to control the SmartCard.
00873      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
00874      (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
00875 @endverbatim
00876   * @{
00877   */
00878
00879 /**
00880   * @brief return the SMARTCARD state
00881   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00882   *                the configuration information for SMARTCARD module.
00883   * @retval HAL state
00884   */
00885 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
00886 {
00887   uint32_t temp1= 0x00U, temp2 = 0x00U;
00888   temp1 = hsc->gState;
00889   temp2 = hsc->RxState;
00890
00891   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
00892 }
00893
00894 /**
00895   * @brief  Return the SMARTCARD error code
00896   * @param  hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
00897   *              the configuration information for the specified SMARTCARD.
00898   * @retval SMARTCARD Error Code
00899   */
00900 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
00901 {
00902   return hsc->ErrorCode;
00903 }
00904
00905 /**
00906   * @}
00907   */
00908
00909 /**
00910   * @brief DMA SMARTCARD transmit process complete callback
00911   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00912   *                the configuration information for the specified DMA module.
00913   * @retval None
00914   */
00915 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
00916 {
00917   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00918
00919   hsc->TxXferCount = 0U;
00920
00921   /* Disable the DMA transfer for transmit request by setting the DMAT bit
00922   in the USART CR3 register */
00923   hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
00924
00925   /* Enable the SMARTCARD Transmit Complete Interrupt */
00926   __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
00927 }
00928
00929 /**
00930   * @brief DMA SMARTCARD receive process complete callback
00931   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00932   *                the configuration information for the specified DMA module.
00933   * @retval None
00934   */
00935 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
00936 {
00937   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00938
00939   hsc->RxXferCount = 0U;
00940
00941   /* Disable the DMA transfer for the receiver request by setting the DMAR bit
00942   in the USART CR3 register */
00943   hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
00944
00945   /* At end of Rx process, restore hsc->RxState to Ready */
00946   hsc->RxState = HAL_SMARTCARD_STATE_READY;
00947
00948   HAL_SMARTCARD_RxCpltCallback(hsc);
00949 }
00950
00951 /**
00952   * @brief DMA SMARTCARD communication error callback
00953   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00954   *                the configuration information for the specified DMA module.
00955   * @retval None
00956   */
00957 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
00958 {
00959   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00960
00961   hsc->RxXferCount = 0U;
00962   hsc->TxXferCount = 0U;
00963   hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
00964   hsc->gState= HAL_SMARTCARD_STATE_READY;
00965   hsc->RxState= HAL_SMARTCARD_STATE_READY;
00966
00967   HAL_SMARTCARD_ErrorCallback(hsc);
00968 }
00969
00970 /**
00971   * @brief  This function handles SMARTCARD Communication Timeout.
00972   * @param  hsc: SMARTCARD handle
00973   * @param  Flag: specifies the SMARTCARD flag to check.
00974   * @param  Status: The new Flag status (SET or RESET).
00975   * @param  Timeout: Timeout duration
00976   * @retval HAL status
00977   */
00978 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
00979 {
00980   uint32_t tickstart = 0U;
00981
00982   /* Get tick */
00983   tickstart = HAL_GetTick();
00984
00985   /* Wait until flag is set */
00986   if(Status == RESET)
00987   {
00988     while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
00989     {
00990       /* Check for the Timeout */
00991       if(Timeout != HAL_MAX_DELAY)
00992       {
00993         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00994         {
00995           /* Disable TXE and RXNE interrupts for the interrupt process */
00996           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
00997           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
00998
00999           hsc->gState= HAL_SMARTCARD_STATE_READY;
01000                   hsc->RxState= HAL_SMARTCARD_STATE_READY;
01001
01002           /* Process Unlocked */
01003           __HAL_UNLOCK(hsc);
01004
01005           return HAL_TIMEOUT;
01006         }
01007       }
01008     }
01009   }
01010   else
01011   {
01012     while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
01013     {
01014       /* Check for the Timeout */
01015       if(Timeout != HAL_MAX_DELAY)
01016       {
01017         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01018         {
01019           /* Disable TXE and RXNE interrupts for the interrupt process */
01020           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
01021           __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
01022
01023           hsc->gState= HAL_SMARTCARD_STATE_READY;
01024                   hsc->RxState= HAL_SMARTCARD_STATE_READY;
01025
01026           /* Process Unlocked */
01027           __HAL_UNLOCK(hsc);
01028
01029           return HAL_TIMEOUT;
01030         }
01031       }
01032     }
01033   }
01034   return HAL_OK;
01035 }
01036
01037 /**
01038   * @brief Send an amount of data in non blocking mode
01039   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01040   *                the configuration information for SMARTCARD module.
01041   * @retval HAL status
01042   */
01043 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
01044 {
01045   uint16_t* tmp;
01046
01047   /* Check that a Tx process is ongoing */
01048   if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
01049   {
01050     tmp = (uint16_t*) hsc->pTxBuffPtr;
01051     hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
01052     hsc->pTxBuffPtr += 1U;
01053
01054     if(--hsc->TxXferCount == 0U)
01055     {
01056       /* Disable the SMARTCARD Transmit data register empty Interrupt */
01057       __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
01058
01059       /* Enable the SMARTCARD Transmit Complete Interrupt */
01060       __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
01061     }
01062
01063     return HAL_OK;
01064   }
01065   else
01066   {
01067     return HAL_BUSY;
01068   }
01069 }
01070
01071 /**
01072   * @brief  Wraps up transmission in non blocking mode.
01073   * @param  hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
01074   *                the configuration information for the specified SMARTCARD module.
01075   * @retval HAL status
01076   */
01077 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01078 {
01079   /* Disable the SMARTCARD Transmit Complete Interrupt */
01080   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
01081
01082   /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01083   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
01084
01085   /* Tx process is ended, restore hsmartcard->gState to Ready */
01086   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01087
01088   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
01089
01090   return HAL_OK;
01091 }
01092
01093 /**
01094   * @brief Receive an amount of data in non blocking mode
01095   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01096   *                the configuration information for SMARTCARD module.
01097   * @retval HAL status
01098   */
01099 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
01100 {
01101   uint16_t* tmp;
01102
01103   /* Check that a Rx process is ongoing */
01104   if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
01105   {
01106     tmp = (uint16_t*) hsc->pRxBuffPtr;
01107     *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FFU);
01108     hsc->pRxBuffPtr += 1U;
01109
01110     if(--hsc->RxXferCount == 0U)
01111     {
01112       __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
01113
01114       /* Disable the SMARTCARD Parity Error Interrupt */
01115       __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
01116
01117       /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01118       __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
01119
01120           /* Rx process is completed, restore hsc->RxState to Ready */
01121       hsc->RxState = HAL_SMARTCARD_STATE_READY;
01122
01123       HAL_SMARTCARD_RxCpltCallback(hsc);
01124
01125       return HAL_OK;
01126     }
01127     return HAL_OK;
01128   }
01129   else
01130   {
01131     return HAL_BUSY;
01132   }
01133 }
01134
01135 /**
01136   * @brief Configure the SMARTCARD peripheral
01137   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01138   *                the configuration information for SMARTCARD module.
01139   * @retval None
01140   */
01141 static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
01142 {
01143   uint32_t tmpreg = 0x00U;
01144
01145   /* Check the parameters */
01146   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
01147   assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
01148   assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
01149   assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
01150   assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
01151   assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
01152   assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
01153   assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
01154   assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
01155   assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
01156
01157   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
01158      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
01159   hsc->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
01160
01161   /*---------------------------- USART CR2 Configuration ---------------------*/
01162   tmpreg = hsc->Instance->CR2;
01163   /* Clear CLKEN, CPOL, CPHA and LBCL bits */
01164   tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
01165   /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
01166   /* Set CPOL bit according to hsc->Init.CLKPolarity value */
01167   /* Set CPHA bit according to hsc->Init.CLKPhase value */
01168   /* Set LBCL bit according to hsc->Init.CLKLastBit value */
01169   /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
01170   tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
01171                       hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
01172   /* Write to USART CR2 */
01173   hsc->Instance->CR2 = (uint32_t)tmpreg;
01174
01175   tmpreg = hsc->Instance->CR2;
01176
01177   /* Clear STOP[13:12] bits */
01178   tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
01179
01180   /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
01181   tmpreg |= (uint32_t)(hsc->Init.StopBits);
01182
01183   /* Write to USART CR2 */
01184   hsc->Instance->CR2 = (uint32_t)tmpreg;
01185
01186   /*-------------------------- USART CR1 Configuration -----------------------*/
01187   tmpreg = hsc->Instance->CR1;
01188
01189   /* Clear M, PCE, PS, TE and RE bits */
01190   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
01191                                    USART_CR1_RE));
01192
01193   /* Configure the SMARTCARD Word Length, Parity and mode:
01194      Set the M bits according to hsc->Init.WordLength value
01195      Set PCE and PS bits according to hsc->Init.Parity value
01196      Set TE and RE bits according to hsc->Init.Mode value */
01197   tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
01198
01199   /* Write to USART CR1 */
01200   hsc->Instance->CR1 = (uint32_t)tmpreg;
01201
01202   /*-------------------------- USART CR3 Configuration -----------------------*/
01203   /* Clear CTSE and RTSE bits */
01204   hsc->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
01205
01206   /*-------------------------- USART BRR Configuration -----------------------*/
01207   if((hsc->Instance == USART1) || (hsc->Instance == USART6))
01208   {
01209     hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
01210   }
01211   else
01212   {
01213     hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
01214   }
01215 }
01216
01217 /**
01218   * @}
01219   */
01220
01221 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
01222 /**
01223   * @}
01224   */
01225
01226 /**
01227   * @}
01228   */
01229
01230 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_smartcard.h Source File

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stm32f4xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SMARTCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SMARTCARD_H
00040 #define __STM32F4xx_HAL_SMARTCARD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARD
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SMARTCARD Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                            - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
00070                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
00071
00072   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00073                                            This parameter can be a value of @ref SMARTCARD_Word_Length */
00074
00075   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00076                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits */
00077
00078   uint32_t Parity;                   /*!< Specifies the parity mode.
00079                                            This parameter can be a value of @ref SMARTCARD_Parity
00080                                            @note When parity is enabled, the computed parity is inserted
00081                                                  at the MSB position of the transmitted data (9th bit when
00082                                                  the word length is set to 9 data bits; 8th bit when the
00083                                                  word length is set to 8 data bits).*/
00084
00085   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00086                                            This parameter can be a value of @ref SMARTCARD_Mode */
00087
00088   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00089                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00090
00091   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00092                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00093
00094   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00095                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00096                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00097
00098   uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
00099                                            to provide the smartcard clock. The value given in the register (5 significant bits)
00100                                            is multiplied by 2 to give the division factor of the source clock frequency.
00101                                            This parameter can be a value of @ref SMARTCARD_Prescaler */
00102
00103   uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
00104
00105   uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state.
00106                                            This parameter can be a value of @ref SMARTCARD_NACK_State */
00107 }SMARTCARD_InitTypeDef;
00108
00109 /**
00110   * @brief HAL SMARTCARD State structures definition
00111   * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
00112   *        - gState contains SMARTCARD state information related to global Handle management
00113   *          and also information related to Tx operations.
00114   *          gState value coding follow below described bitmap :
00115   *          b7-b6  Error information
00116   *             00 : No Error
00117   *             01 : (Not Used)
00118   *             10 : Timeout
00119   *             11 : Error
00120   *          b5     IP initilisation status
00121   *             0  : Reset (IP not initialized)
00122   *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
00123   *          b4-b3  (not used)
00124   *             xx : Should be set to 00
00125   *          b2     Intrinsic process state
00126   *             0  : Ready
00127   *             1  : Busy (IP busy with some configuration or internal operations)
00128   *          b1     (not used)
00129   *             x  : Should be set to 0
00130   *          b0     Tx state
00131   *             0  : Ready (no Tx operation ongoing)
00132   *             1  : Busy (Tx operation ongoing)
00133   *        - RxState contains information related to Rx operations.
00134   *          RxState value coding follow below described bitmap :
00135   *          b7-b6  (not used)
00136   *             xx : Should be set to 00
00137   *          b5     IP initilisation status
00138   *             0  : Reset (IP not initialized)
00139   *             1  : Init done (IP not initialized)
00140   *          b4-b2  (not used)
00141   *            xxx : Should be set to 000
00142   *          b1     Rx state
00143   *             0  : Ready (no Rx operation ongoing)
00144   *             1  : Busy (Rx operation ongoing)
00145   *          b0     (not used)
00146   *             x  : Should be set to 0.
00147   */
00148 typedef enum
00149 {
00150   HAL_SMARTCARD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00151                                                         Value is allowed for gState and RxState */
00152   HAL_SMARTCARD_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00153                                                         Value is allowed for gState and RxState */
00154   HAL_SMARTCARD_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
00155                                                         Value is allowed for gState only */
00156   HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00157                                                         Value is allowed for gState only */
00158   HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00159                                                         Value is allowed for RxState only */
00160   HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
00161                                                         Not to be used for neither gState nor RxState.
00162                                                         Value is result of combination (Or) between gState and RxState values */
00163   HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
00164                                                         Value is allowed for gState only */
00165   HAL_SMARTCARD_STATE_ERROR             = 0xE0U     /*!< Error
00166                                                         Value is allowed for gState only */
00167 }HAL_SMARTCARD_StateTypeDef;
00168
00169 /**
00170   * @brief  SMARTCARD handle Structure definition
00171   */
00172 typedef struct
00173 {
00174   USART_TypeDef                    *Instance;        /* USART registers base address */
00175
00176   SMARTCARD_InitTypeDef            Init;             /* SmartCard communication parameters */
00177
00178   uint8_t                          *pTxBuffPtr;      /* Pointer to SmartCard Tx transfer Buffer */
00179
00180   uint16_t                         TxXferSize;       /* SmartCard Tx Transfer size */
00181
00182   uint16_t                         TxXferCount;      /* SmartCard Tx Transfer Counter */
00183
00184   uint8_t                          *pRxBuffPtr;      /* Pointer to SmartCard Rx transfer Buffer */
00185
00186   uint16_t                         RxXferSize;       /* SmartCard Rx Transfer size */
00187
00188   uint16_t                         RxXferCount;      /* SmartCard Rx Transfer Counter */
00189
00190   DMA_HandleTypeDef                *hdmatx;          /* SmartCard Tx DMA Handle parameters */
00191
00192   DMA_HandleTypeDef                *hdmarx;          /* SmartCard Rx DMA Handle parameters */
00193
00194   HAL_LockTypeDef                  Lock;             /* Locking object */
00195
00196   __IO HAL_SMARTCARD_StateTypeDef  gState;           /* SmartCard state information related to global Handle management
00197                                                         and also related to Tx operations.
00198                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00199
00200   __IO HAL_SMARTCARD_StateTypeDef  RxState;          /* SmartCard state information related to Rx operations.
00201                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00202
00203   __IO uint32_t  ErrorCode;                          /* SmartCard Error code */
00204
00205 }SMARTCARD_HandleTypeDef;
00206
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported constants --------------------------------------------------------*/
00212 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
00213   * @{
00214   */
00215 /** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
00216   * @brief    SMARTCARD Error Code
00217   * @{
00218   */
00219 #define HAL_SMARTCARD_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
00220 #define HAL_SMARTCARD_ERROR_PE           ((uint32_t)0x00000001U)   /*!< Parity error        */
00221 #define HAL_SMARTCARD_ERROR_NE           ((uint32_t)0x00000002U)   /*!< Noise error         */
00222 #define HAL_SMARTCARD_ERROR_FE           ((uint32_t)0x00000004U)   /*!< Frame error         */
00223 #define HAL_SMARTCARD_ERROR_ORE          ((uint32_t)0x00000008U)   /*!< Overrun error       */
00224 #define HAL_SMARTCARD_ERROR_DMA          ((uint32_t)0x00000010U)   /*!< DMA transfer error  */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00230   * @{
00231   */
00232 #define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00238   * @{
00239   */
00240 #define SMARTCARD_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
00241 #define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00247   * @{
00248   */
00249 #define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00250 #define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup SMARTCARD_Mode SMARTCARD Mode
00256   * @{
00257   */
00258 #define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
00259 #define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
00260 #define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00266   * @{
00267   */
00268 #define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x00000000U)
00269 #define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase
00275   * @{
00276   */
00277 #define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x00000000U)
00278 #define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
00284   * @{
00285   */
00286 #define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x00000000U)
00287 #define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State
00293   * @{
00294   */
00295 #define SMARTCARD_NACK_ENABLE                  ((uint32_t)USART_CR3_NACK)
00296 #define SMARTCARD_NACK_DISABLE                 ((uint32_t)0x00000000U)
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup SMARTCARD_DMA_Requests   SMARTCARD DMA requests
00302   * @{
00303   */
00304 #define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
00305 #define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
00311   * @{
00312   */
00313 #define SMARTCARD_PRESCALER_SYSCLK_DIV2         ((uint32_t)0x00000001U)          /*!< SYSCLK divided by 2 */
00314 #define SMARTCARD_PRESCALER_SYSCLK_DIV4         ((uint32_t)0x00000002U)          /*!< SYSCLK divided by 4 */
00315 #define SMARTCARD_PRESCALER_SYSCLK_DIV6         ((uint32_t)0x00000003U)          /*!< SYSCLK divided by 6 */
00316 #define SMARTCARD_PRESCALER_SYSCLK_DIV8         ((uint32_t)0x00000004U)          /*!< SYSCLK divided by 8 */
00317 #define SMARTCARD_PRESCALER_SYSCLK_DIV10        ((uint32_t)0x00000005U)          /*!< SYSCLK divided by 10 */
00318 #define SMARTCARD_PRESCALER_SYSCLK_DIV12        ((uint32_t)0x00000006U)          /*!< SYSCLK divided by 12 */
00319 #define SMARTCARD_PRESCALER_SYSCLK_DIV14        ((uint32_t)0x00000007U)          /*!< SYSCLK divided by 14 */
00320 #define SMARTCARD_PRESCALER_SYSCLK_DIV16        ((uint32_t)0x00000008U)          /*!< SYSCLK divided by 16 */
00321 #define SMARTCARD_PRESCALER_SYSCLK_DIV18        ((uint32_t)0x00000009U)          /*!< SYSCLK divided by 18 */
00322 #define SMARTCARD_PRESCALER_SYSCLK_DIV20        ((uint32_t)0x0000000AU)          /*!< SYSCLK divided by 20 */
00323 #define SMARTCARD_PRESCALER_SYSCLK_DIV22        ((uint32_t)0x0000000BU)          /*!< SYSCLK divided by 22 */
00324 #define SMARTCARD_PRESCALER_SYSCLK_DIV24        ((uint32_t)0x0000000CU)          /*!< SYSCLK divided by 24 */
00325 #define SMARTCARD_PRESCALER_SYSCLK_DIV26        ((uint32_t)0x0000000DU)          /*!< SYSCLK divided by 26 */
00326 #define SMARTCARD_PRESCALER_SYSCLK_DIV28        ((uint32_t)0x0000000EU)          /*!< SYSCLK divided by 28 */
00327 #define SMARTCARD_PRESCALER_SYSCLK_DIV30        ((uint32_t)0x0000000FU)          /*!< SYSCLK divided by 30 */
00328 #define SMARTCARD_PRESCALER_SYSCLK_DIV32        ((uint32_t)0x00000010U)          /*!< SYSCLK divided by 32 */
00329 #define SMARTCARD_PRESCALER_SYSCLK_DIV34        ((uint32_t)0x00000011U)          /*!< SYSCLK divided by 34 */
00330 #define SMARTCARD_PRESCALER_SYSCLK_DIV36        ((uint32_t)0x00000012U)          /*!< SYSCLK divided by 36 */
00331 #define SMARTCARD_PRESCALER_SYSCLK_DIV38        ((uint32_t)0x00000013U)          /*!< SYSCLK divided by 38 */
00332 #define SMARTCARD_PRESCALER_SYSCLK_DIV40        ((uint32_t)0x00000014U)          /*!< SYSCLK divided by 40 */
00333 #define SMARTCARD_PRESCALER_SYSCLK_DIV42        ((uint32_t)0x00000015U)          /*!< SYSCLK divided by 42 */
00334 #define SMARTCARD_PRESCALER_SYSCLK_DIV44        ((uint32_t)0x00000016U)          /*!< SYSCLK divided by 44 */
00335 #define SMARTCARD_PRESCALER_SYSCLK_DIV46        ((uint32_t)0x00000017U)          /*!< SYSCLK divided by 46 */
00336 #define SMARTCARD_PRESCALER_SYSCLK_DIV48        ((uint32_t)0x00000018U)          /*!< SYSCLK divided by 48 */
00337 #define SMARTCARD_PRESCALER_SYSCLK_DIV50        ((uint32_t)0x00000019U)          /*!< SYSCLK divided by 50 */
00338 #define SMARTCARD_PRESCALER_SYSCLK_DIV52        ((uint32_t)0x0000001AU)          /*!< SYSCLK divided by 52 */
00339 #define SMARTCARD_PRESCALER_SYSCLK_DIV54        ((uint32_t)0x0000001BU)          /*!< SYSCLK divided by 54 */
00340 #define SMARTCARD_PRESCALER_SYSCLK_DIV56        ((uint32_t)0x0000001CU)          /*!< SYSCLK divided by 56 */
00341 #define SMARTCARD_PRESCALER_SYSCLK_DIV58        ((uint32_t)0x0000001DU)          /*!< SYSCLK divided by 58 */
00342 #define SMARTCARD_PRESCALER_SYSCLK_DIV60        ((uint32_t)0x0000001EU)          /*!< SYSCLK divided by 60 */
00343 #define SMARTCARD_PRESCALER_SYSCLK_DIV62        ((uint32_t)0x0000001FU)          /*!< SYSCLK divided by 62 */
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup SmartCard_Flags SMARTCARD Flags
00349   *        Elements values convention: 0xXXXX
00350   *           - 0xXXXX  : Flag mask in the SR register
00351   * @{
00352   */
00353 #define SMARTCARD_FLAG_TXE                       ((uint32_t)0x00000080U)
00354 #define SMARTCARD_FLAG_TC                        ((uint32_t)0x00000040U)
00355 #define SMARTCARD_FLAG_RXNE                      ((uint32_t)0x00000020U)
00356 #define SMARTCARD_FLAG_IDLE                      ((uint32_t)0x00000010U)
00357 #define SMARTCARD_FLAG_ORE                       ((uint32_t)0x00000008U)
00358 #define SMARTCARD_FLAG_NE                        ((uint32_t)0x00000004U)
00359 #define SMARTCARD_FLAG_FE                        ((uint32_t)0x00000002U)
00360 #define SMARTCARD_FLAG_PE                        ((uint32_t)0x00000001U)
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
00366   *        Elements values convention: 0xY000XXXX
00367   *           - XXXX  : Interrupt mask in the XX register
00368   *           - Y  : Interrupt source register (2bits)
00369   *                 - 01: CR1 register
00370   *                 - 10: CR3 register
00371   * @{
00372   */
00373 #define SMARTCARD_IT_PE                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00374 #define SMARTCARD_IT_TXE                        ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00375 #define SMARTCARD_IT_TC                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00376 #define SMARTCARD_IT_RXNE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00377 #define SMARTCARD_IT_IDLE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00378 #define SMARTCARD_IT_ERR                        ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00379 /**
00380   * @}
00381   */
00382
00383 /**
00384   * @}
00385   */
00386
00387 /* Exported macro ------------------------------------------------------------*/
00388 /** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
00389   * @{
00390   */
00391
00392 /** @brief Reset SMARTCARD handle gstate & RxState
00393   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00394   * @retval None
00395   */
00396 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                        \
00397                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
00398                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
00399                                                           } while(0)
00400
00401 /** @brief  Flushs the Smartcard DR register
00402   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00403   */
00404 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
00405
00406 /** @brief  Checks whether the specified Smartcard flag is set or not.
00407   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00408   * @param  __FLAG__: specifies the flag to check.
00409   *        This parameter can be one of the following values:
00410   *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
00411   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
00412   *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
00413   *            @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
00414   *            @arg SMARTCARD_FLAG_ORE:  Overrun Error flag
00415   *            @arg SMARTCARD_FLAG_NE:   Noise Error flag
00416   *            @arg SMARTCARD_FLAG_FE:   Framing Error flag
00417   *            @arg SMARTCARD_FLAG_PE:   Parity Error flag
00418   * @retval The new state of __FLAG__ (TRUE or FALSE).
00419   */
00420 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00421
00422 /** @brief  Clears the specified Smartcard pending flags.
00423   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00424   * @param  __FLAG__: specifies the flag to check.
00425   *          This parameter can be any combination of the following values:
00426   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
00427   *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
00428   *
00429   * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
00430   *          error) flags are cleared by software sequence: a read operation to
00431   *          USART_SR register followed by a read operation to USART_DR register.
00432   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00433   * @note   TC flag can be also cleared by software sequence: a read operation to
00434   *          USART_SR register followed by a write operation to USART_DR register.
00435   * @note   TXE flag is cleared only by a write to the USART_DR register.
00436   */
00437 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00438
00439 /** @brief  Clear the SMARTCARD PE pending flag.
00440   * @param  __HANDLE__: specifies the USART Handle.
00441   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00442   *         UART peripheral.
00443   * @retval None
00444   */
00445 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)     \
00446   do{                                                \
00447     __IO uint32_t tmpreg = 0x00U;                    \
00448     tmpreg = (__HANDLE__)->Instance->SR;             \
00449     tmpreg = (__HANDLE__)->Instance->DR;             \
00450     UNUSED(tmpreg);                                  \
00451   } while(0)
00452
00453 /** @brief  Clear the SMARTCARD FE pending flag.
00454   * @param  __HANDLE__: specifies the USART Handle.
00455   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00456   *         UART peripheral.
00457   * @retval None
00458   */
00459 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00460
00461 /** @brief  Clear the SMARTCARD NE pending flag.
00462   * @param  __HANDLE__: specifies the USART Handle.
00463   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00464   *         UART peripheral.
00465   * @retval None
00466   */
00467 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00468
00469 /** @brief  Clear the SMARTCARD ORE pending flag.
00470   * @param  __HANDLE__: specifies the USART Handle.
00471   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00472   *         UART peripheral.
00473   * @retval None
00474   */
00475 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00476
00477 /** @brief  Clear the SMARTCARD IDLE pending flag.
00478   * @param  __HANDLE__: specifies the USART Handle.
00479   *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00480   *         UART peripheral.
00481   * @retval None
00482   */
00483 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00484
00485 /** @brief  Enables or disables the specified SmartCard interrupts.
00486   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00487   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
00488   *          This parameter can be one of the following values:
00489   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
00490   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
00491   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00492   *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
00493   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
00494   *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00495   */
00496 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
00497                                                                  ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
00498 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
00499                                                                  ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
00500
00501 /** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
00502   * @param  __HANDLE__: specifies the SmartCard Handle.
00503   * @param  __IT__: specifies the SMARTCARD interrupt source to check.
00504   *          This parameter can be one of the following values:
00505   *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
00506   *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
00507   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00508   *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
00509   *            @arg SMARTCARD_IT_ERR: Error interrupt
00510   *            @arg SMARTCARD_IT_PE: Parity Error interrupt
00511   * @retval The new state of __IT__ (TRUE or FALSE).
00512   */
00513 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
00514
00515 /** @brief  Macro to enable the SMARTCARD's one bit sample method
00516   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00517   * @retval None
00518   */
00519 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00520
00521 /** @brief  Macro to disable the SMARTCARD's one bit sample method
00522   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00523   * @retval None
00524   */
00525 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
00526
00527 /** @brief  Enable the USART associated to the SMARTCARD Handle
00528   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00529   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00530   * @retval None
00531   */
00532 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00533
00534 /** @brief  Disable the USART associated to the SMARTCARD Handle
00535   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00536   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00537   * @retval None
00538   */
00539 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00540
00541 /** @brief  Macros to enable or disable the SmartCard DMA request.
00542   * @param  __HANDLE__: specifies the SmartCard Handle.
00543   * @param  __REQUEST__: specifies the SmartCard DMA request.
00544   *          This parameter can be one of the following values:
00545   *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
00546   *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
00547   */
00548 #define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
00549 #define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
00550
00551 /**
00552   * @}
00553   */
00554
00555 /* Exported functions --------------------------------------------------------*/
00556 /** @addtogroup SMARTCARD_Exported_Functions
00557   * @{
00558   */
00559
00560 /** @addtogroup SMARTCARD_Exported_Functions_Group1
00561   * @{
00562   */
00563 /* Initialization/de-initialization functions  **********************************/
00564 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
00565 HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
00566 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
00567 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
00568 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
00569 /**
00570   * @}
00571   */
00572
00573 /** @addtogroup SMARTCARD_Exported_Functions_Group2
00574   * @{
00575   */
00576 /* IO operation functions *******************************************************/
00577 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00578 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00579 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00580 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00581 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00582 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00583 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
00584 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00585 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00586 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
00587 /**
00588   * @}
00589   */
00590
00591 /** @addtogroup SMARTCARD_Exported_Functions_Group3
00592   * @{
00593   */
00594 /* Peripheral State functions  **************************************************/
00595 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
00596 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
00597
00598 /**
00599   * @}
00600   */
00601
00602 /**
00603   * @}
00604   */
00605 /* Private types -------------------------------------------------------------*/
00606 /* Private variables ---------------------------------------------------------*/
00607 /* Private constants ---------------------------------------------------------*/
00608 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00609   * @{
00610   */
00611
00612 /** @brief SMARTCARD interruptions flag mask
00613   *
00614   */
00615 #define SMARTCARD_IT_MASK   ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
00616                                         USART_CR1_IDLEIE | USART_CR3_EIE )
00617
00618 #define SMARTCARD_DIV(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
00619 #define SMARTCARD_DIVMANT(_PCLK_, _BAUD_)        (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
00620 #define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_)        (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00621 /* UART BRR = mantissa + overflow + fraction
00622             = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
00623 #define SMARTCARD_BRR(_PCLK_, _BAUD_)            (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
00624                                                   (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
00625                                                   (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
00626
00627 #define SMARTCARD_CR1_REG_INDEX                 1U
00628 #define SMARTCARD_CR3_REG_INDEX                 3U
00629 /**
00630   * @}
00631   */
00632
00633 /* Private macros --------------------------------------------------------*/
00634 /** @defgroup SMARTCARD_Private_Macros   SMARTCARD Private Macros
00635   * @{
00636   */
00637 #define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
00638 #define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
00639                                          ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
00640 #define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
00641                                      ((PARITY) == SMARTCARD_PARITY_ODD))
00642 #define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x000000U))
00643 #define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
00644 #define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
00645 #define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
00646                                        ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
00647 #define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
00648                                        ((NACK) == SMARTCARD_NACK_DISABLE))
00649 #define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
00650 /**
00651   * @}
00652   */
00653
00654 /* Private functions ---------------------------------------------------------*/
00655 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
00656   * @{
00657   */
00658
00659 /**
00660   * @}
00661   */
00662
00663 /**
00664   * @}
00665   */
00666
00667 /**
00668   * @}
00669   */
00670 #ifdef __cplusplus
00671 }
00672 #endif
00673
00674 #endif /* __STM32F4xx_HAL_SMARTCARD_H */
00675
00676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spdifrx.c Source File

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stm32f4xx_hal_spdifrx.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_spdifrx.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the SPDIFRX audio interface:
00009   *           + Initialization and Configuration
00010   *           + Data transfers functions
00011   *           + DMA transfers management
00012   *           + Interrupts and flags management
00013   @verbatim
00014  ===============================================================================
00015                   ##### How to use this driver #####
00016  ===============================================================================
00017  [..]
00018     The SPDIFRX HAL driver can be used as follow:
00019
00020     (#) Declare SPDIFRX_HandleTypeDef handle structure.
00021     (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
00022         (##) Enable the SPDIFRX interface clock.
00023         (##) SPDIFRX pins configuration:
00024             (+++) Enable the clock for the SPDIFRX GPIOs.
00025             (+++) Configure these SPDIFRX pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
00027             (+++) Configure the SPDIFRX interrupt priority.
00028             (+++) Enable the NVIC SPDIFRX IRQ handle.
00029         (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).
00030             (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
00031                       (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
00032             (+++) Enable the DMAx interface clock.
00033             (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
00034             (+++) Configure the DMA Channel.
00035             (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
00036             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00037                 DMA CtrlRx/DataRx channel.
00038
00039    (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
00040        using HAL_SPDIFRX_Init() function.
00041
00042    -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
00043        __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
00044    -@- Make sure that ck_spdif clock is configured.
00045
00046    (#) Three operation modes are available within this driver :
00047
00048    *** Polling mode for reception operation (for debug purpose) ***
00049    ================================================================
00050    [..]
00051      (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
00052          (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
00053
00054    *** Interrupt mode for reception operation ***
00055    =========================================
00056    [..]
00057      (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
00058          (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
00059      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00060          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00061      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00062          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00063      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00064          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00065
00066    *** DMA mode for reception operation ***
00067    ========================================
00068    [..]
00069      (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
00070          (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
00071      (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
00072          add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
00073      (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
00074          add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
00075      (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
00076          add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
00077      (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
00078
00079    *** SPDIFRX HAL driver macros list ***
00080    =============================================
00081    [..]
00082      Below the list of most used macros in SPDIFRX HAL driver.
00083       (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
00084       (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
00085       (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
00086       (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
00087       (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
00088       (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
00089
00090     [..]
00091       (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
00092
00093   @endverbatim
00094   ******************************************************************************
00095   * @attention
00096   *
00097   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00098   *
00099   * Redistribution and use in source and binary forms, with or without modification,
00100   * are permitted provided that the following conditions are met:
00101   *   1. Redistributions of source code must retain the above copyright notice,
00102   *      this list of conditions and the following disclaimer.
00103   *   2. Redistributions in binary form must reproduce the above copyright notice,
00104   *      this list of conditions and the following disclaimer in the documentation
00105   *      and/or other materials provided with the distribution.
00106   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00107   *      may be used to endorse or promote products derived from this software
00108   *      without specific prior written permission.
00109   *
00110   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00111   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00112   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00113   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00114   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00115   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00116   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00117   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00118   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00119   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00120   *
00121   ******************************************************************************
00122   */
00123
00124 /* Includes ------------------------------------------------------------------*/
00125 #include "stm32f4xx_hal.h"
00126
00127 /** @addtogroup STM32F4xx_HAL_Driver
00128   * @{
00129   */
00130 /** @defgroup SPDIFRX SPDIFRX
00131   * @brief SPDIFRX HAL module driver
00132   * @{
00133   */
00134
00135 #ifdef HAL_SPDIFRX_MODULE_ENABLED
00136
00137 #if defined(STM32F446xx)
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141 #define SPDIFRX_TIMEOUT_VALUE  0xFFFF
00142
00143 /* Private macro -------------------------------------------------------------*/
00144 /* Private variables ---------------------------------------------------------*/
00145 /* Private function prototypes -----------------------------------------------*/
00146 /** @addtogroup SPDIFRX_Private_Functions
00147   * @{
00148   */
00149 static void  SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
00150 static void  SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00151 static void  SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
00152 static void  SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
00153 static void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
00154 static void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00155 static void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
00156 static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00157 /**
00158   * @}
00159   */
00160 /* Exported functions ---------------------------------------------------------*/
00161
00162 /** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
00163   * @{
00164   */
00165
00166 /** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
00167   *  @brief    Initialization and Configuration functions
00168   *
00169   @verbatim
00170   ===============================================================================
00171   ##### Initialization and de-initialization functions #####
00172   ===============================================================================
00173   [..]  This subsection provides a set of functions allowing to initialize and
00174   de-initialize the SPDIFRX peripheral:
00175
00176   (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
00177   all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00178
00179   (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
00180   the selected configuration:
00181   (++) Input Selection (IN0, IN1,...)
00182   (++) Maximum allowed re-tries during synchronization phase
00183   (++) Wait for activity on SPDIF selected input
00184   (++) Channel status selection (from channel A or B)
00185   (++) Data format (LSB, MSB, ...)
00186   (++) Stereo mode
00187   (++) User bits masking (PT,C,U,V,...)
00188
00189   (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
00190   of the selected SPDIFRXx peripheral.
00191   @endverbatim
00192   * @{
00193   */
00194
00195 /**
00196   * @brief Initializes the SPDIFRX according to the specified parameters
00197   *        in the SPDIFRX_InitTypeDef and create the associated handle.
00198   * @param hspdif: SPDIFRX handle
00199   * @retval HAL status
00200   */
00201 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
00202 {
00203   uint32_t tmpreg = 0U;
00204
00205   /* Check the SPDIFRX handle allocation */
00206   if(hspdif == NULL)
00207   {
00208     return HAL_ERROR;
00209   }
00210
00211   /* Check the SPDIFRX parameters */
00212   assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
00213   assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
00214   assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
00215   assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
00216   assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
00217   assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
00218   assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
00219   assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
00220   assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
00221   assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
00222
00223   if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
00224   {
00225     /* Allocate lock resource and initialize it */
00226     hspdif->Lock = HAL_UNLOCKED;
00227     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00228     HAL_SPDIFRX_MspInit(hspdif);
00229   }
00230
00231      /* SPDIFRX peripheral state is BUSY*/
00232    hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00233
00234   /* Disable SPDIFRX interface (IDLE State) */
00235   __HAL_SPDIFRX_IDLE(hspdif);
00236
00237   /* Reset the old SPDIFRX CR configuration */
00238   tmpreg = hspdif->Instance->CR;
00239
00240   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00241                          SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK  |
00242                          SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
00243                          SPDIFRX_CR_INSEL);
00244
00245   /* Sets the new configuration of the SPDIFRX peripheral */
00246   tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
00247                         hspdif->Init.InputSelection |
00248                         hspdif->Init.Retries |
00249                         hspdif->Init.WaitForActivity |
00250                         hspdif->Init.ChannelSelection |
00251                         hspdif->Init.DataFormat |
00252                         hspdif->Init.PreambleTypeMask |
00253                         hspdif->Init.ChannelStatusMask |
00254                         hspdif->Init.ValidityBitMask |
00255                         hspdif->Init.ParityErrorMask);
00256
00257   hspdif->Instance->CR = tmpreg;
00258
00259   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00260
00261     /* SPDIFRX peripheral state is READY*/
00262   hspdif->State = HAL_SPDIFRX_STATE_READY;
00263
00264   return HAL_OK;
00265 }
00266
00267 /**
00268   * @brief DeInitializes the SPDIFRX peripheral
00269   * @param hspdif: SPDIFRX handle
00270   * @retval HAL status
00271   */
00272 HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
00273 {
00274   /* Check the SPDIFRX handle allocation */
00275   if(hspdif == NULL)
00276   {
00277     return HAL_ERROR;
00278   }
00279
00280   /* Check the parameters */
00281   assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
00282
00283   hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00284
00285   /* Disable SPDIFRX interface (IDLE state) */
00286   __HAL_SPDIFRX_IDLE(hspdif);
00287
00288   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00289   HAL_SPDIFRX_MspDeInit(hspdif);
00290
00291   hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00292
00293     /* SPDIFRX peripheral state is RESET*/
00294   hspdif->State = HAL_SPDIFRX_STATE_RESET;
00295
00296   /* Release Lock */
00297   __HAL_UNLOCK(hspdif);
00298
00299   return HAL_OK;
00300 }
00301
00302 /**
00303   * @brief SPDIFRX MSP Init
00304   * @param hspdif: SPDIFRX handle
00305   * @retval None
00306   */
00307 __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
00308 {
00309   /* Prevent unused argument(s) compilation warning */
00310   UNUSED(hspdif);
00311   /* NOTE : This function Should not be modified, when the callback is needed,
00312   the HAL_SPDIFRX_MspInit could be implemented in the user file
00313   */
00314 }
00315
00316 /**
00317   * @brief SPDIFRX MSP DeInit
00318   * @param hspdif: SPDIFRX handle
00319   * @retval None
00320   */
00321 __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
00322 {
00323   /* Prevent unused argument(s) compilation warning */
00324   UNUSED(hspdif);
00325   /* NOTE : This function Should not be modified, when the callback is needed,
00326   the HAL_SPDIFRX_MspDeInit could be implemented in the user file
00327   */
00328 }
00329
00330 /**
00331   * @brief Sets the SPDIFRX  dtat format according to the specified parameters
00332   *        in the SPDIFRX_InitTypeDef.
00333   * @param hspdif: SPDIFRX handle
00334   * @param sDataFormat: SPDIFRX data format
00335   * @retval HAL status
00336   */
00337 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat)
00338 {
00339   uint32_t tmpreg = 0U;
00340
00341   /* Check the SPDIFRX handle allocation */
00342   if(hspdif == NULL)
00343   {
00344     return HAL_ERROR;
00345   }
00346
00347   /* Check the SPDIFRX parameters */
00348   assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
00349   assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
00350   assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
00351   assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
00352   assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
00353   assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
00354
00355   /* Reset the old SPDIFRX CR configuration */
00356   tmpreg = hspdif->Instance->CR;
00357
00358   if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
00359     (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
00360     ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
00361   {
00362       return HAL_ERROR;
00363   }
00364
00365   tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
00366                          SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
00367
00368   /* Sets the new configuration of the SPDIFRX peripheral */
00369   tmpreg |= ((uint16_t) sDataFormat.StereoMode |
00370                         sDataFormat.DataFormat |
00371                         sDataFormat.PreambleTypeMask |
00372                         sDataFormat.ChannelStatusMask |
00373                         sDataFormat.ValidityBitMask |
00374                         sDataFormat.ParityErrorMask);
00375
00376   hspdif->Instance->CR = tmpreg;
00377
00378   return HAL_OK;
00379 }
00380
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
00386   *  @brief Data transfers functions
00387   *
00388 @verbatim
00389 ===============================================================================
00390 ##### IO operation functions #####
00391 ===============================================================================
00392     [..]
00393     This subsection provides a set of functions allowing to manage the SPDIFRX data
00394     transfers.
00395
00396     (#) There is two mode of transfer:
00397         (++) Blocking mode : The communication is performed in the polling mode.
00398              The status of all data processing is returned by the same function
00399              after finishing transfer.
00400         (++) No-Blocking mode : The communication is performed using Interrupts
00401              or DMA. These functions return the status of the transfer start-up.
00402              The end of the data processing will be indicated through the
00403              dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
00404              using DMA mode.
00405
00406     (#) Blocking mode functions are :
00407         (++) HAL_SPDIFRX_ReceiveDataFlow()
00408         (++) HAL_SPDIFRX_ReceiveControlFlow()
00409                 (+@) Do not use blocking mode to receive both control and data flow at the same time.
00410
00411     (#) No-Blocking mode functions with Interrupt are :
00412         (++) HAL_SPDIFRX_ReceiveControlFlow_IT()
00413         (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
00414
00415     (#) No-Blocking mode functions with DMA are :
00416         (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()
00417         (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
00418
00419     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00420         (++) HAL_SPDIFRX_RxCpltCallback()
00421         (++) HAL_SPDIFRX_ErrorCallback()
00422
00423 @endverbatim
00424   * @{
00425   */
00426
00427 /**
00428   * @brief  Receives an amount of data (Data Flow) in blocking mode.
00429   * @param  hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains
00430   *                 the configuration information for SPDIFRX module.
00431   * @param  pData: Pointer to data buffer
00432   * @param  Size: Amount of data to be received
00433   * @param  Timeout: Timeout duration
00434   * @retval HAL status
00435   */
00436 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00437 {
00438
00439   if((pData == NULL ) || (Size == 0U))
00440   {
00441     return  HAL_ERROR;
00442   }
00443
00444   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00445   {
00446     /* Process Locked */
00447     __HAL_LOCK(hspdif);
00448
00449      hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00450
00451         /* Start synchronisation */
00452         __HAL_SPDIFRX_SYNC(hspdif);
00453
00454             /* Wait until SYNCD flag is set */
00455       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
00456       {
00457         return HAL_TIMEOUT;
00458       }
00459
00460             /* Start reception */
00461       __HAL_SPDIFRX_RCV(hspdif);
00462
00463     /* Receive data flow */
00464     while(Size > 0U)
00465     {
00466       /* Wait until RXNE flag is set */
00467       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00468       {
00469         return HAL_TIMEOUT;
00470       }
00471
00472       (*pData++) = hspdif->Instance->DR;
00473       Size--;
00474     }
00475
00476     /* SPDIFRX ready */
00477     hspdif->State = HAL_SPDIFRX_STATE_READY;
00478
00479     /* Process Unlocked */
00480     __HAL_UNLOCK(hspdif);
00481
00482     return HAL_OK;
00483   }
00484   else
00485   {
00486     return HAL_BUSY;
00487   }
00488 }
00489
00490 /**
00491   * @brief  Receives an amount of data (Control Flow) in blocking mode.
00492   * @param  hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains
00493   *                 the configuration information for SPDIFRX module.
00494   * @param  pData: Pointer to data buffer
00495   * @param  Size: Amount of data to be received
00496   * @param  Timeout: Timeout duration
00497   * @retval HAL status
00498   */
00499 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00500 {
00501
00502   if((pData == NULL ) || (Size == 0U))
00503   {
00504     return  HAL_ERROR;
00505   }
00506
00507   if(hspdif->State == HAL_SPDIFRX_STATE_READY)
00508   {
00509     /* Process Locked */
00510     __HAL_LOCK(hspdif);
00511
00512      hspdif->State = HAL_SPDIFRX_STATE_BUSY;
00513
00514         /* Start synchronization */
00515         __HAL_SPDIFRX_SYNC(hspdif);
00516
00517         /* Wait until SYNCD flag is set */
00518       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
00519       {
00520         return HAL_TIMEOUT;
00521       }
00522
00523         /* Start reception */
00524       __HAL_SPDIFRX_RCV(hspdif);
00525
00526         /* Receive control flow */
00527     while(Size > 0U)
00528     {
00529       /* Wait until CSRNE flag is set */
00530       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)
00531       {
00532         return HAL_TIMEOUT;
00533       }
00534
00535       (*pData++) = hspdif->Instance->CSR;
00536       Size--;
00537     }
00538
00539     /* SPDIFRX ready */
00540     hspdif->State = HAL_SPDIFRX_STATE_READY;
00541
00542     /* Process Unlocked */
00543     __HAL_UNLOCK(hspdif);
00544
00545     return HAL_OK;
00546   }
00547   else
00548   {
00549     return HAL_BUSY;
00550   }
00551 }
00552 /**
00553   * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
00554   * @param hspdif: SPDIFRX handle
00555   * @param pData: a 32-bit pointer to the Receive data buffer.
00556   * @param Size: number of data sample to be received .
00557   * @retval HAL status
00558   */
00559 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00560 {
00561  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
00562   {
00563     if((pData == NULL) || (Size == 0U))
00564     {
00565       return HAL_ERROR;
00566     }
00567
00568     /* Process Locked */
00569     __HAL_LOCK(hspdif);
00570
00571     hspdif->pRxBuffPtr = pData;
00572     hspdif->RxXferSize = Size;
00573     hspdif->RxXferCount = Size;
00574
00575     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00576
00577     /* Check if a receive process is ongoing or not */
00578      hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
00579
00580
00581     /* Enable the SPDIFRX  PE Error Interrupt */
00582     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00583
00584     /* Enable the SPDIFRX  OVR Error Interrupt */
00585     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00586
00587     /* Process Unlocked */
00588     __HAL_UNLOCK(hspdif);
00589
00590     /* Enable the SPDIFRX RXNE interrupt */
00591     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
00592
00593         if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
00594         {
00595         /* Start synchronization */
00596         __HAL_SPDIFRX_SYNC(hspdif);
00597
00598         /* Wait until SYNCD flag is set */
00599       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00600       {
00601         return HAL_TIMEOUT;
00602       }
00603
00604         /* Start reception */
00605       __HAL_SPDIFRX_RCV(hspdif);
00606         }
00607
00608     return HAL_OK;
00609   }
00610   else
00611   {
00612     return HAL_BUSY;
00613   }
00614 }
00615
00616 /**
00617   * @brief Receive an amount of data (Control Flow) with Interrupt
00618   * @param hspdif: SPDIFRX handle
00619   * @param pData: a 32-bit pointer to the Receive data buffer.
00620   * @param Size: number of data sample (Control Flow) to be received :
00621   * @retval HAL status
00622   */
00623 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00624 {
00625  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
00626   {
00627     if((pData == NULL ) || (Size == 0U))
00628     {
00629       return HAL_ERROR;
00630     }
00631
00632     /* Process Locked */
00633     __HAL_LOCK(hspdif);
00634
00635     hspdif->pCsBuffPtr = pData;
00636     hspdif->CsXferSize = Size;
00637     hspdif->CsXferCount = Size;
00638
00639     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00640
00641     /* Check if a receive process is ongoing or not */
00642      hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
00643
00644
00645     /* Enable the SPDIFRX PE Error Interrupt */
00646      __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
00647
00648     /* Enable the SPDIFRX OVR Error Interrupt */
00649      __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
00650
00651     /* Process Unlocked */
00652     __HAL_UNLOCK(hspdif);
00653
00654     /* Enable the SPDIFRX CSRNE interrupt */
00655     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
00656
00657         if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
00658         {
00659         /* Start synchronization */
00660         __HAL_SPDIFRX_SYNC(hspdif);
00661
00662         /* Wait until SYNCD flag is set */
00663       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00664       {
00665         return HAL_TIMEOUT;
00666       }
00667
00668         /* Start reception */
00669       __HAL_SPDIFRX_RCV(hspdif);
00670       }
00671
00672     return HAL_OK;
00673   }
00674   else
00675   {
00676     return HAL_BUSY;
00677   }
00678 }
00679
00680 /**
00681   * @brief Receive an amount of data (Data Flow) mode with DMA
00682   * @param hspdif: SPDIFRX handle
00683   * @param pData: a 32-bit pointer to the Receive data buffer.
00684   * @param Size: number of data sample to be received :
00685   * @retval HAL status
00686   */
00687 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00688 {
00689
00690   if((pData == NULL) || (Size == 0U))
00691   {
00692     return  HAL_ERROR;
00693   }
00694
00695   if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
00696   {
00697     hspdif->pRxBuffPtr = pData;
00698     hspdif->RxXferSize = Size;
00699     hspdif->RxXferCount = Size;
00700
00701     /* Process Locked */
00702     __HAL_LOCK(hspdif);
00703
00704     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00705     hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
00706
00707     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
00708     hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
00709
00710     /* Set the SPDIFRX Rx DMA transfer complete callback */
00711     hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
00712
00713     /* Set the DMA error callback */
00714     hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
00715
00716     /* Enable the DMA request */
00717     HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
00718
00719     /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
00720      hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
00721
00722         if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
00723         {
00724         /* Start synchronization */
00725         __HAL_SPDIFRX_SYNC(hspdif);
00726
00727         /* Wait until SYNCD flag is set */
00728       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00729       {
00730         return HAL_TIMEOUT;
00731       }
00732
00733         /* Start reception */
00734       __HAL_SPDIFRX_RCV(hspdif);
00735         }
00736
00737     /* Process Unlocked */
00738     __HAL_UNLOCK(hspdif);
00739
00740     return HAL_OK;
00741   }
00742   else
00743   {
00744     return HAL_BUSY;
00745   }
00746 }
00747
00748 /**
00749   * @brief Receive an amount of data (Control Flow) with DMA
00750   * @param hspdif: SPDIFRX handle
00751   * @param pData: a 32-bit pointer to the Receive data buffer.
00752   * @param Size: number of data (Control Flow) sample to be received :
00753   * @retval HAL status
00754   */
00755 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
00756 {
00757   if((pData == NULL) || (Size == 0U))
00758   {
00759     return  HAL_ERROR;
00760   }
00761
00762  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
00763   {
00764     hspdif->pCsBuffPtr = pData;
00765     hspdif->CsXferSize = Size;
00766     hspdif->CsXferCount = Size;
00767
00768     /* Process Locked */
00769     __HAL_LOCK(hspdif);
00770
00771     hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
00772     hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
00773
00774     /* Set the SPDIFRX Rx DMA Half transfer complete callback */
00775     hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
00776
00777     /* Set the SPDIFRX Rx DMA transfer complete callback */
00778     hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
00779
00780     /* Set the DMA error callback */
00781     hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
00782
00783     /* Enable the DMA request */
00784     HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
00785
00786     /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
00787     hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
00788
00789         if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
00790         {
00791         /* Start synchronization */
00792         __HAL_SPDIFRX_SYNC(hspdif);
00793
00794         /* Wait until SYNCD flag is set */
00795       if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)
00796       {
00797         return HAL_TIMEOUT;
00798       }
00799
00800         /* Start reception */
00801       __HAL_SPDIFRX_RCV(hspdif);
00802         }
00803
00804     /* Process Unlocked */
00805     __HAL_UNLOCK(hspdif);
00806
00807     return HAL_OK;
00808   }
00809   else
00810   {
00811     return HAL_BUSY;
00812   }
00813 }
00814
00815 /**
00816   * @brief stop the audio stream receive from the Media.
00817   * @param hspdif: SPDIFRX handle
00818   * @retval None
00819   */
00820 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
00821 {
00822   /* Process Locked */
00823   __HAL_LOCK(hspdif);
00824
00825   /* Disable the SPDIFRX DMA requests */
00826   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
00827   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
00828
00829   /* Disable the SPDIFRX DMA channel */
00830   __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
00831   __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
00832
00833   /* Disable SPDIFRX peripheral */
00834   __HAL_SPDIFRX_IDLE(hspdif);
00835
00836   hspdif->State = HAL_SPDIFRX_STATE_READY;
00837
00838   /* Process Unlocked */
00839   __HAL_UNLOCK(hspdif);
00840
00841   return HAL_OK;
00842 }
00843
00844 /**
00845   * @brief  This function handles SPDIFRX interrupt request.
00846   * @param  hspdif: SPDIFRX handle
00847   * @retval HAL status
00848   */
00849 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
00850 {
00851   /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
00852   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
00853   {
00854       __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
00855     SPDIFRX_ReceiveDataFlow_IT(hspdif);
00856   }
00857
00858    /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
00859   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
00860   {
00861         __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
00862     SPDIFRX_ReceiveControlFlow_IT(hspdif);
00863   }
00864
00865   /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
00866   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
00867   {
00868     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
00869
00870         /* Change the SPDIFRX error code */
00871     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
00872
00873         /* the transfer is not stopped */
00874     HAL_SPDIFRX_ErrorCallback(hspdif);
00875   }
00876
00877       /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
00878   if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
00879   {
00880     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
00881
00882         /* Change the SPDIFRX error code */
00883     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
00884
00885         /* the transfer is not stopped */
00886     HAL_SPDIFRX_ErrorCallback(hspdif);
00887   }
00888
00889 }
00890
00891 /**
00892   * @brief Rx Transfer (Data flow) half completed callbacks
00893   * @param hspdif: SPDIFRX handle
00894   * @retval None
00895   */
00896 __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00897 {
00898   /* Prevent unused argument(s) compilation warning */
00899   UNUSED(hspdif);
00900   /* NOTE : This function Should not be modified, when the callback is needed,
00901   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00902   */
00903 }
00904
00905 /**
00906   * @brief Rx Transfer (Data flow) completed callbacks
00907   * @param hspdif: SPDIFRX handle
00908   * @retval None
00909   */
00910 __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00911 {
00912   /* Prevent unused argument(s) compilation warning */
00913   UNUSED(hspdif);
00914   /* NOTE : This function Should not be modified, when the callback is needed,
00915   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00916   */
00917 }
00918
00919 /**
00920   * @brief Rx (Control flow) Transfer half completed callbacks
00921   * @param hspdif: SPDIFRX handle
00922   * @retval None
00923   */
00924 __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00925 {
00926   /* Prevent unused argument(s) compilation warning */
00927   UNUSED(hspdif);
00928   /* NOTE : This function Should not be modified, when the callback is needed,
00929   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00930   */
00931 }
00932
00933 /**
00934   * @brief Rx Transfer (Control flow) completed callbacks
00935   * @param hspdif: SPDIFRX handle
00936   * @retval None
00937   */
00938 __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
00939 {
00940   /* Prevent unused argument(s) compilation warning */
00941   UNUSED(hspdif);
00942   /* NOTE : This function Should not be modified, when the callback is needed,
00943   the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
00944   */
00945 }
00946
00947 /**
00948   * @brief SPDIFRX error callbacks
00949   * @param hspdif: SPDIFRX handle
00950   * @retval None
00951   */
00952 __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
00953 {
00954   /* Prevent unused argument(s) compilation warning */
00955   UNUSED(hspdif);
00956   /* NOTE : This function Should not be modified, when the callback is needed,
00957   the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
00958   */
00959 }
00960
00961 /**
00962   * @}
00963   */
00964
00965 /** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
00966   *  @brief   Peripheral State functions
00967   *
00968 @verbatim
00969 ===============================================================================
00970 ##### Peripheral State and Errors functions #####
00971 ===============================================================================
00972 [..]
00973 This subsection permit to get in run-time the status of the peripheral
00974 and the data flow.
00975
00976 @endverbatim
00977   * @{
00978   */
00979
00980 /**
00981   * @brief  Return the SPDIFRX state
00982   * @param  hspdif : SPDIFRX handle
00983   * @retval HAL state
00984   */
00985 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
00986 {
00987   return hspdif->State;
00988 }
00989
00990 /**
00991   * @brief  Return the SPDIFRX error code
00992   * @param  hspdif : SPDIFRX handle
00993   * @retval SPDIFRX Error Code
00994   */
00995 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
00996 {
00997   return hspdif->ErrorCode;
00998 }
00999
01000 /**
01001   * @}
01002   */
01003
01004 /**
01005   * @brief DMA SPDIFRX receive process (Data flow) complete callback
01006   * @param hdma : DMA handle
01007   * @retval None
01008   */
01009 static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
01010 {
01011   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01012
01013   /* Disable Rx DMA Request */
01014   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
01015   hspdif->RxXferCount = 0U;
01016
01017   hspdif->State = HAL_SPDIFRX_STATE_READY;
01018   HAL_SPDIFRX_RxCpltCallback(hspdif);
01019 }
01020
01021 /**
01022   * @brief DMA SPDIFRX receive process (Data flow) half complete callback
01023   * @param hdma : DMA handle
01024   * @retval None
01025   */
01026 static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01027 {
01028   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01029
01030   HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
01031 }
01032
01033
01034 /**
01035   * @brief DMA SPDIFRX receive process (Control flow) complete callback
01036   * @param hdma : DMA handle
01037   * @retval None
01038   */
01039 static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
01040 {
01041   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01042
01043   /* Disable Cb DMA Request */
01044   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
01045   hspdif->CsXferCount = 0U;
01046
01047   hspdif->State = HAL_SPDIFRX_STATE_READY;
01048   HAL_SPDIFRX_CxCpltCallback(hspdif);
01049 }
01050
01051 /**
01052   * @brief DMA SPDIFRX receive process (Control flow) half complete callback
01053   * @param hdma : DMA handle
01054   * @retval None
01055   */
01056 static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
01057 {
01058   SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01059
01060   HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
01061 }
01062
01063 /**
01064   * @brief DMA SPDIFRX communication error callback
01065   * @param hdma : DMA handle
01066   * @retval None
01067   */
01068 static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
01069 {
01070   SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01071
01072   /* Disable Rx and Cb DMA Request */
01073   hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
01074   hspdif->RxXferCount = 0U;
01075
01076   hspdif->State= HAL_SPDIFRX_STATE_READY;
01077
01078   /* Set the error code and execute error callback*/
01079   hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
01080   HAL_SPDIFRX_ErrorCallback(hspdif);
01081 }
01082
01083
01084 /**
01085   * @brief Receive an amount of data (Data Flow) with Interrupt
01086   * @param hspdif: SPDIFRX handle
01087   * @retval None
01088   */
01089 static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01090 {
01091     /* Receive data */
01092     (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
01093     hspdif->RxXferCount--;
01094
01095     if(hspdif->RxXferCount == 0U)
01096     {
01097       /* Disable RXNE/PE and OVR interrupts */
01098       __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
01099
01100       hspdif->State = HAL_SPDIFRX_STATE_READY;
01101
01102       /* Process Unlocked */
01103       __HAL_UNLOCK(hspdif);
01104
01105       HAL_SPDIFRX_RxCpltCallback(hspdif);
01106     }
01107 }
01108
01109 /**
01110   * @brief Receive an amount of data (Control Flow) with Interrupt
01111   * @param hspdif: SPDIFRX handle
01112   * @retval None
01113   */
01114 static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
01115 {
01116     /* Receive data */
01117     (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
01118     hspdif->CsXferCount--;
01119
01120     if(hspdif->CsXferCount == 0U)
01121     {
01122       /* Disable CSRNE interrupt */
01123       __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01124
01125        hspdif->State = HAL_SPDIFRX_STATE_READY;
01126
01127       /* Process Unlocked */
01128       __HAL_UNLOCK(hspdif);
01129
01130       HAL_SPDIFRX_CxCpltCallback(hspdif);
01131     }
01132 }
01133
01134 /**
01135   * @brief This function handles SPDIFRX Communication Timeout.
01136   * @param hspdif: SPDIFRX handle
01137   * @param Flag: Flag checked
01138   * @param Status: Value of the flag expected
01139   * @param Timeout: Duration of the timeout
01140   * @retval HAL status
01141   */
01142 static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01143 {
01144   uint32_t tickstart = 0U;
01145
01146   /* Get tick */
01147   tickstart = HAL_GetTick();
01148
01149   /* Wait until flag is set */
01150   if(Status == RESET)
01151   {
01152     while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
01153     {
01154       /* Check for the Timeout */
01155       if(Timeout != HAL_MAX_DELAY)
01156       {
01157         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01158         {
01159           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01160           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01161           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01162           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01163           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01164           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01165           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01166           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01167
01168           hspdif->State= HAL_SPDIFRX_STATE_READY;
01169
01170           /* Process Unlocked */
01171           __HAL_UNLOCK(hspdif);
01172
01173           return HAL_TIMEOUT;
01174         }
01175       }
01176     }
01177   }
01178   else
01179   {
01180     while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
01181     {
01182       /* Check for the Timeout */
01183       if(Timeout != HAL_MAX_DELAY)
01184       {
01185         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01186         {
01187           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01188           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
01189           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
01190           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
01191           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
01192                     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
01193           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
01194           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
01195
01196           hspdif->State= HAL_SPDIFRX_STATE_READY;
01197
01198           /* Process Unlocked */
01199           __HAL_UNLOCK(hspdif);
01200
01201           return HAL_TIMEOUT;
01202         }
01203       }
01204     }
01205   }
01206   return HAL_OK;
01207 }
01208
01209 /**
01210   * @}
01211   */
01212 #endif /* STM32F446xx */
01213
01214 #endif /* HAL_SPDIFRX_MODULE_ENABLED */
01215 /**
01216   * @}
01217   */
01218
01219 /**
01220   * @}
01221   */
01222
01223 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01224
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spdifrx.h Source File

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stm32f4xx_hal_spdifrx.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_spdifrx.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SPDIFRX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SPDIFRX_H
00040 #define __STM32F4xx_HAL_SPDIFRX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F446xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f4xx_hal_def.h"
00050
00051 /** @addtogroup STM32F4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup SPDIFRX
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief SPDIFRX Init structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.
00070                                           This parameter can be a value of @ref SPDIFRX_Input_Selection */
00071
00072   uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.
00073                                           This parameter can be a value of @ref SPDIFRX_Max_Retries */
00074
00075   uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.
00076                                           This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
00077
00078   uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.
00079                                           This parameter can be a value of @ref SPDIFRX_Channel_Selection */
00080
00081   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00082                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00083
00084   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00085                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00086
00087     uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00088                                                                                    This parameter can be a value of @ref SPDIFRX_PT_Mask */
00089
00090     uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00091                                                                                   This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00092
00093     uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00094                                                                                   This parameter can be a value of @ref SPDIFRX_V_Mask */
00095
00096     uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00097                                                                                   This parameter can be a value of @ref SPDIFRX_PE_Mask */
00098 }SPDIFRX_InitTypeDef;
00099
00100 /**
00101   * @brief SPDIFRX SetDataFormat structure definition
00102   */
00103 typedef struct
00104 {
00105   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
00106                                           This parameter can be a value of @ref SPDIFRX_Data_Format */
00107
00108   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
00109                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
00110
00111   uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
00112                                                                                    This parameter can be a value of @ref SPDIFRX_PT_Mask */
00113
00114   uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
00115                                                                                   This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
00116
00117   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
00118                                                                                   This parameter can be a value of @ref SPDIFRX_V_Mask */
00119
00120   uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
00121                                                                                   This parameter can be a value of @ref SPDIFRX_PE_Mask */
00122 }SPDIFRX_SetDataFormatTypeDef;
00123
00124 /**
00125   * @brief  HAL State structures definition
00126   */
00127 typedef enum
00128 {
00129   HAL_SPDIFRX_STATE_RESET      = 0x00U,  /*!< SPDIFRX not yet initialized or disabled                */
00130   HAL_SPDIFRX_STATE_READY      = 0x01U,  /*!< SPDIFRX initialized and ready for use                  */
00131   HAL_SPDIFRX_STATE_BUSY       = 0x02U,  /*!< SPDIFRX internal process is ongoing                    */
00132   HAL_SPDIFRX_STATE_BUSY_RX    = 0x03U,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */
00133   HAL_SPDIFRX_STATE_BUSY_CX    = 0x04U,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */
00134   HAL_SPDIFRX_STATE_ERROR      = 0x07U   /*!< SPDIFRX error state                                    */
00135 }HAL_SPDIFRX_StateTypeDef;
00136
00137 /**
00138   * @brief SPDIFRX handle Structure definition
00139   */
00140 typedef struct
00141 {
00142   SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */
00143
00144   SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */
00145
00146   uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */
00147
00148     uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */
00149
00150   __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */
00151
00152   __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter
00153                                               (This field is initialized at the
00154                                                same value as transfer size at the
00155                                                beginning of the transfer and
00156                                                decremented when a sample is received.
00157                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00158
00159   __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */
00160
00161   __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter
00162                                               (This field is initialized at the
00163                                                same value as transfer size at the
00164                                                beginning of the transfer and
00165                                                decremented when a sample is received.
00166                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00167
00168   DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
00169
00170   DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */
00171
00172   __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */
00173
00174   __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */
00175
00176   __IO uint32_t  ErrorCode;                /* SPDIFRX Error code                 */
00177 }SPDIFRX_HandleTypeDef;
00178 /**
00179   * @}
00180   */
00181
00182 /* Exported constants --------------------------------------------------------*/
00183 /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
00184   * @{
00185   */
00186 /** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
00187   * @{
00188   */
00189 #define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */
00190 #define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */
00191 #define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */
00192 #define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004U)  /*!< Parity error       */
00193 #define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */
00194 #define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010U)  /*!< Unknown Error error */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
00200   * @{
00201   */
00202 #define SPDIFRX_INPUT_IN0               ((uint32_t)0x00000000U)
00203 #define SPDIFRX_INPUT_IN1               ((uint32_t)0x00010000U)
00204 #define SPDIFRX_INPUT_IN2               ((uint32_t)0x00020000U)
00205 #define SPDIFRX_INPUT_IN3               ((uint32_t)0x00030000U)
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
00211   * @{
00212   */
00213 #define SPDIFRX_MAXRETRIES_NONE            ((uint32_t)0x00000000U)
00214 #define SPDIFRX_MAXRETRIES_3               ((uint32_t)0x00001000U)
00215 #define SPDIFRX_MAXRETRIES_15              ((uint32_t)0x00002000U)
00216 #define SPDIFRX_MAXRETRIES_63              ((uint32_t)0x00003000U)
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
00222   * @{
00223   */
00224 #define SPDIFRX_WAITFORACTIVITY_OFF                   ((uint32_t)0x00000000U)
00225 #define SPDIFRX_WAITFORACTIVITY_ON                    ((uint32_t)SPDIFRX_CR_WFA)
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
00231 * @{
00232 */
00233 #define SPDIFRX_PREAMBLETYPEMASK_OFF                   ((uint32_t)0x00000000U)
00234 #define SPDIFRX_PREAMBLETYPEMASK_ON                    ((uint32_t)SPDIFRX_CR_PTMSK)
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask
00240 * @{
00241 */
00242 #define SPDIFRX_CHANNELSTATUS_OFF                 ((uint32_t)0x00000000U)        /* The channel status and user bits are copied into the SPDIF_DR */
00243 #define SPDIFRX_CHANNELSTATUS_ON                  ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
00249 * @{
00250 */
00251 #define SPDIFRX_VALIDITYMASK_OFF                   ((uint32_t)0x00000000U)
00252 #define SPDIFRX_VALIDITYMASK_ON                    ((uint32_t)SPDIFRX_CR_VMSK)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask
00258 * @{
00259 */
00260 #define SPDIFRX_PARITYERRORMASK_OFF                   ((uint32_t)0x00000000U)
00261 #define SPDIFRX_PARITYERRORMASK_ON                    ((uint32_t)SPDIFRX_CR_PMSK)
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection
00267   * @{
00268   */
00269 #define SPDIFRX_CHANNEL_A      ((uint32_t)0x00000000U)
00270 #define SPDIFRX_CHANNEL_B      ((uint32_t)SPDIFRX_CR_CHSEL)
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
00276   * @{
00277   */
00278 #define SPDIFRX_DATAFORMAT_LSB                   ((uint32_t)0x00000000U)
00279 #define SPDIFRX_DATAFORMAT_MSB                   ((uint32_t)0x00000010U)
00280 #define SPDIFRX_DATAFORMAT_32BITS                ((uint32_t)0x00000020U)
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
00286   * @{
00287   */
00288 #define SPDIFRX_STEREOMODE_DISABLE           ((uint32_t)0x00000000U)
00289 #define SPDIFRX_STEREOMODE_ENABLE           ((uint32_t)SPDIFRX_CR_RXSTEO)
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup SPDIFRX_State SPDIFRX State
00295   * @{
00296   */
00297
00298 #define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFCU)
00299 #define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001U)
00300 #define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFEN)
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
00306   * @{
00307   */
00308 #define SPDIFRX_IT_RXNE                       ((uint32_t)SPDIFRX_IMR_RXNEIE)
00309 #define SPDIFRX_IT_CSRNE                      ((uint32_t)SPDIFRX_IMR_CSRNEIE)
00310 #define SPDIFRX_IT_PERRIE                     ((uint32_t)SPDIFRX_IMR_PERRIE)
00311 #define SPDIFRX_IT_OVRIE                      ((uint32_t)SPDIFRX_IMR_OVRIE)
00312 #define SPDIFRX_IT_SBLKIE                     ((uint32_t)SPDIFRX_IMR_SBLKIE)
00313 #define SPDIFRX_IT_SYNCDIE                    ((uint32_t)SPDIFRX_IMR_SYNCDIE)
00314 #define SPDIFRX_IT_IFEIE                      ((uint32_t)SPDIFRX_IMR_IFEIE )
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
00320   * @{
00321   */
00322 #define SPDIFRX_FLAG_RXNE                   ((uint32_t)SPDIFRX_SR_RXNE)
00323 #define SPDIFRX_FLAG_CSRNE                  ((uint32_t)SPDIFRX_SR_CSRNE)
00324 #define SPDIFRX_FLAG_PERR                   ((uint32_t)SPDIFRX_SR_PERR)
00325 #define SPDIFRX_FLAG_OVR                    ((uint32_t)SPDIFRX_SR_OVR)
00326 #define SPDIFRX_FLAG_SBD                    ((uint32_t)SPDIFRX_SR_SBD)
00327 #define SPDIFRX_FLAG_SYNCD                  ((uint32_t)SPDIFRX_SR_SYNCD)
00328 #define SPDIFRX_FLAG_FERR                   ((uint32_t)SPDIFRX_SR_FERR)
00329 #define SPDIFRX_FLAG_SERR                   ((uint32_t)SPDIFRX_SR_SERR)
00330 #define SPDIFRX_FLAG_TERR                   ((uint32_t)SPDIFRX_SR_TERR)
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 /* Exported macros -----------------------------------------------------------*/
00340 /** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
00341   * @{
00342   */
00343
00344 /** @brief  Reset SPDIFRX handle state
00345   * @param  __HANDLE__: SPDIFRX handle.
00346   * @retval None
00347   */
00348 #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
00349
00350 /** @brief  Disable the specified SPDIFRX peripheral (IDLE State).
00351   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00352   * @retval None
00353   */
00354 #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
00355
00356 /** @brief  Enable the specified SPDIFRX peripheral (SYNC State).
00357   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00358   * @retval None
00359   */
00360 #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
00361
00362
00363 /** @brief  Enable the specified SPDIFRX peripheral (RCV State).
00364   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00365   * @retval None
00366   */
00367 #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
00368
00369 /** @brief  Enable or disable the specified SPDIFRX interrupts.
00370   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00371   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00372   *        This parameter can be one of the following values:
00373   *            @arg SPDIFRX_IT_RXNE
00374   *            @arg SPDIFRX_IT_CSRNE
00375   *            @arg SPDIFRX_IT_PERRIE
00376   *            @arg SPDIFRX_IT_OVRIE
00377   *            @arg SPDIFRX_IT_SBLKIE
00378   *            @arg SPDIFRX_IT_SYNCDIE
00379   *            @arg SPDIFRX_IT_IFEIE
00380   * @retval None
00381   */
00382 #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00383 #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
00384
00385 /** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.
00386   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00387   * @param  __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
00388   *          This parameter can be one of the following values:
00389   *            @arg SPDIFRX_IT_RXNE
00390   *            @arg SPDIFRX_IT_CSRNE
00391   *            @arg SPDIFRX_IT_PERRIE
00392   *            @arg SPDIFRX_IT_OVRIE
00393   *            @arg SPDIFRX_IT_SBLKIE
00394   *            @arg SPDIFRX_IT_SYNCDIE
00395   *            @arg SPDIFRX_IT_IFEIE
00396   * @retval The new state of __IT__ (TRUE or FALSE).
00397   */
00398 #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00399
00400 /** @brief  Checks whether the specified SPDIFRX flag is set or not.
00401   * @param  __HANDLE__: specifies the SPDIFRX Handle.
00402   * @param  __FLAG__: specifies the flag to check.
00403   *        This parameter can be one of the following values:
00404   *            @arg SPDIFRX_FLAG_RXNE
00405   *            @arg SPDIFRX_FLAG_CSRNE
00406   *            @arg SPDIFRX_FLAG_PERR
00407   *            @arg SPDIFRX_FLAG_OVR
00408   *            @arg SPDIFRX_FLAG_SBD
00409   *            @arg SPDIFRX_FLAG_SYNCD
00410   *            @arg SPDIFRX_FLAG_FERR
00411   *            @arg SPDIFRX_FLAG_SERR
00412   *            @arg SPDIFRX_FLAG_TERR
00413   * @retval The new state of __FLAG__ (TRUE or FALSE).
00414   */
00415 #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00416
00417 /** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
00418   * @param  __HANDLE__: specifies the USART Handle.
00419   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00420   *                       to clear the corresponding interrupt
00421   *          This parameter can be one of the following values:
00422   *            @arg SPDIFRX_FLAG_PERR
00423   *            @arg SPDIFRX_FLAG_OVR
00424   *            @arg SPDIFRX_SR_SBD
00425   *            @arg SPDIFRX_SR_SYNCD
00426   * @retval None
00427   */
00428 #define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
00429
00430 /**
00431   * @}
00432   */
00433
00434 /* Exported functions --------------------------------------------------------*/
00435 /** @addtogroup SPDIFRX_Exported_Functions
00436   * @{
00437   */
00438
00439 /** @addtogroup SPDIFRX_Exported_Functions_Group1
00440   * @{
00441   */
00442 /* Initialization/de-initialization functions  **********************************/
00443 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
00444 HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
00445 void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
00446 void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
00447 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);
00448 /**
00449   * @}
00450   */
00451
00452 /** @addtogroup SPDIFRX_Exported_Functions_Group2
00453   * @{
00454   */
00455 /* I/O operation functions  ***************************************************/
00456  /* Blocking mode: Polling */
00457 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00458 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00459
00460  /* Non-Blocking mode: Interrupt */
00461 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00462 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00463 void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
00464
00465 /* Non-Blocking mode: DMA */
00466 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00467 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
00468
00469 HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
00470
00471 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00472 void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00473 void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00474 void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
00475 void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00476 void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
00477 /**
00478   * @}
00479   */
00480
00481 /** @addtogroup SPDIFRX_Exported_Functions_Group3
00482   * @{
00483   */
00484 /* Peripheral Control and State functions  ************************************/
00485 HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
00486 uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
00487 /**
00488   * @}
00489   */
00490
00491 /**
00492   * @}
00493   */
00494 /* Private types -------------------------------------------------------------*/
00495 /* Private variables ---------------------------------------------------------*/
00496 /* Private constants ---------------------------------------------------------*/
00497 /* Private macros ------------------------------------------------------------*/
00498 /** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
00499   * @{
00500   */
00501 #define IS_SPDIFRX_INPUT_SELECT(INPUT)  (((INPUT) == SPDIFRX_INPUT_IN1) || \
00502                                          ((INPUT) == SPDIFRX_INPUT_IN2) || \
00503                                          ((INPUT) == SPDIFRX_INPUT_IN3)  || \
00504                                          ((INPUT) == SPDIFRX_INPUT_IN0))
00505 #define IS_SPDIFRX_MAX_RETRIES(RET)   (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
00506                                       ((RET) == SPDIFRX_MAXRETRIES_3)  || \
00507                                       ((RET) == SPDIFRX_MAXRETRIES_15) || \
00508                                       ((RET) == SPDIFRX_MAXRETRIES_63))
00509 #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)    (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
00510                                                ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
00511 #define IS_PREAMBLE_TYPE_MASK(VAL)           (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
00512                                              ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
00513 #define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
00514                                              ((VAL) == SPDIFRX_VALIDITYMASK_ON))
00515 #define IS_PARITY_ERROR_MASK(VAL)            (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
00516                                              ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
00517 #define IS_SPDIFRX_CHANNEL(CHANNEL)   (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
00518                                        ((CHANNEL) == SPDIFRX_CHANNEL_B))
00519 #define IS_SPDIFRX_DATA_FORMAT(FORMAT)           (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
00520                                                  ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
00521                                                  ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
00522 #define IS_STEREO_MODE(MODE)                 (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
00523                                              ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
00524
00525 #define IS_CHANNEL_STATUS_MASK(VAL)          (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
00526                                               ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
00527 /**
00528   * @}
00529   */
00530
00531 /* Private functions ---------------------------------------------------------*/
00532 /** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
00533   * @{
00534   */
00535 /**
00536   * @}
00537   */
00538
00539 /**
00540   * @}
00541   */
00542
00543 /**
00544   * @}
00545   */
00546 #endif /* STM32F446xx */
00547
00548 #ifdef __cplusplus
00549 }
00550 #endif
00551
00552
00553 #endif /* __STM32F4xx_HAL_SPDIFRX_H */
00554
00555 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spi.c Source File

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stm32f4xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   SPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The SPI HAL driver can be used as follows:
00021
00022       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00023           SPI_HandleTypeDef  hspi;
00024
00025       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00026           (##) Enable the SPIx interface clock
00027           (##) SPI pins configuration
00028               (+++) Enable the clock for the SPI GPIOs
00029               (+++) Configure these SPI pins as alternate function push-pull
00030           (##) NVIC configuration if you need to use interrupt process
00031               (+++) Configure the SPIx interrupt priority
00032               (+++) Enable the NVIC SPI IRQ handle
00033           (##) DMA Configuration if you need to use DMA process
00034               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
00035               (+++) Enable the DMAx clock
00036               (+++) Configure the DMA handle parameters
00037               (+++) Configure the DMA Tx or Rx stream
00038               (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
00039               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream
00040
00041       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00042           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00043
00044       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00045           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00046               by calling the customized HAL_SPI_MspInit() API.
00047      [..]
00048        Circular mode restriction:
00049       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00050           (##) Master 2Lines RxOnly
00051           (##) Master 1Line Rx
00052       (#) The CRC feature is not managed when the DMA circular mode is enabled
00053       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00054           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00055      [..]
00056        Master Receive mode restriction:
00057       (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
00058           bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
00059           does not initiate a new transfer the following procedure has to be respected:
00060           (##) HAL_SPI_DeInit()
00061           (##) HAL_SPI_Init()
00062      [..]
00063        Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
00064        the following table resume the max SPI frequency reached with data size 8bits/16bits,
00065        according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
00066
00067        DataSize = SPI_DATASIZE_8BIT:
00068        +----------------------------------------------------------------------------------------------+
00069        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00070        | Process | Tranfert mode  |---------------------|----------------------|----------------------|
00071        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00072        |==============================================================================================|
00073        |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00074        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00075        |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00076        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00077        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00078        |=========|================|==========|==========|===========|==========|===========|==========|
00079        |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
00080        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00081        |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
00082        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00083        |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
00084        |=========|================|==========|==========|===========|==========|===========|==========|
00085        |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
00086        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00087        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
00088        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00089        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
00090        +----------------------------------------------------------------------------------------------+
00091
00092        DataSize = SPI_DATASIZE_16BIT:
00093        +----------------------------------------------------------------------------------------------+
00094        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00095        | Process | Tranfert mode  |---------------------|----------------------|----------------------|
00096        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00097        |==============================================================================================|
00098        |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00099        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00100        |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
00101        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00102        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00103        |=========|================|==========|==========|===========|==========|===========|==========|
00104        |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
00105        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00106        |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
00107        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00108        |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
00109        |=========|================|==========|==========|===========|==========|===========|==========|
00110        |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
00111        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00112        |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
00113        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00114        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
00115        +----------------------------------------------------------------------------------------------+
00116        @note The max SPI frequency depend on SPI data size (8bits, 16bits),
00117              SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
00118        @note
00119             (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
00120             (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
00121             (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
00122
00123   @endverbatim
00124   ******************************************************************************
00125   * @attention
00126   *
00127   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00128   *
00129   * Redistribution and use in source and binary forms, with or without modification,
00130   * are permitted provided that the following conditions are met:
00131   *   1. Redistributions of source code must retain the above copyright notice,
00132   *      this list of conditions and the following disclaimer.
00133   *   2. Redistributions in binary form must reproduce the above copyright notice,
00134   *      this list of conditions and the following disclaimer in the documentation
00135   *      and/or other materials provided with the distribution.
00136   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00137   *      may be used to endorse or promote products derived from this software
00138   *      without specific prior written permission.
00139   *
00140   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00141   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00142   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00143   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00144   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00145   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00146   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00147   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00148   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00149   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00150   *
00151   ******************************************************************************
00152   */
00153
00154 /* Includes ------------------------------------------------------------------*/
00155 #include "stm32f4xx_hal.h"
00156
00157 /** @addtogroup STM32F4xx_HAL_Driver
00158   * @{
00159   */
00160
00161 /** @defgroup SPI SPI
00162   * @brief SPI HAL module driver
00163   * @{
00164   */
00165 #ifdef HAL_SPI_MODULE_ENABLED
00166
00167 /* Private typedef -----------------------------------------------------------*/
00168 /* Private defines -----------------------------------------------------------*/
00169 /** @defgroup SPI_Private_Constants SPI Private Constants
00170   * @{
00171   */
00172 #define SPI_DEFAULT_TIMEOUT 100U
00173 /**
00174   * @}
00175   */
00176
00177 /* Private macros ------------------------------------------------------------*/
00178 /* Private variables ---------------------------------------------------------*/
00179 /* Private function prototypes -----------------------------------------------*/
00180 /** @addtogroup SPI_Private_Functions
00181   * @{
00182   */
00183 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00184 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00185 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00186 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00187 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00188 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00189 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00190 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
00191 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00192 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00193 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00194 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00195 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00196 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00197 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00198 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00199 #ifdef USE_SPI_CRC
00200 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00201 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00202 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00203 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00204 #endif
00205 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00206 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00207 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00208 static HAL_StatusTypeDef SPI_CheckForDisablingSPI(SPI_HandleTypeDef *hspi);
00209 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00210 /**
00211   * @}
00212   */
00213
00214 /* Exported functions --------------------------------------------------------*/
00215 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00216   * @{
00217   */
00218
00219 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00220  *  @brief    Initialization and Configuration functions
00221  *
00222 @verbatim
00223  ===============================================================================
00224               ##### Initialization and de-initialization functions #####
00225  ===============================================================================
00226     [..]  This subsection provides a set of functions allowing to initialize and
00227           de-initialize the SPIx peripheral:
00228
00229       (+) User must implement HAL_SPI_MspInit() function in which he configures
00230           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00231
00232       (+) Call the function HAL_SPI_Init() to configure the selected device with
00233           the selected configuration:
00234         (++) Mode
00235         (++) Direction
00236         (++) Data Size
00237         (++) Clock Polarity and Phase
00238         (++) NSS Management
00239         (++) BaudRate Prescaler
00240         (++) FirstBit
00241         (++) TIMode
00242         (++) CRC Calculation
00243         (++) CRC Polynomial if CRC enabled
00244
00245       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00246           of the selected SPIx peripheral.
00247
00248 @endverbatim
00249   * @{
00250   */
00251
00252 /**
00253   * @brief  Initialize the SPI according to the specified parameters
00254   *         in the SPI_InitTypeDef and initialize the associated handle.
00255   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00256   *               the configuration information for SPI module.
00257   * @retval HAL status
00258   */
00259 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00260 {
00261   /* Check the SPI handle allocation */
00262   if(hspi == NULL)
00263   {
00264     return HAL_ERROR;
00265   }
00266
00267   /* Check the parameters */
00268   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00269   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00270   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00271   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00272   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00273   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00274   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00275   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00276   if(hspi->Init.TIMode == SPI_TIMODE_DISABLE)
00277   {
00278     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00279     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00280   }
00281 #ifdef USE_SPI_CRC
00282   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00283   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00284   {
00285     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00286   }
00287 #else
00288   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00289 #endif
00290
00291   if(hspi->State == HAL_SPI_STATE_RESET)
00292   {
00293     /* Allocate lock resource and initialize it */
00294     hspi->Lock = HAL_UNLOCKED;
00295
00296     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00297     HAL_SPI_MspInit(hspi);
00298   }
00299
00300   hspi->State = HAL_SPI_STATE_BUSY;
00301
00302   /* Disable the selected SPI peripheral */
00303   __HAL_SPI_DISABLE(hspi);
00304
00305   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00306   /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
00307   Communication speed, First bit and CRC calculation state */
00308   WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
00309                                   hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
00310                                   hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation) );
00311
00312   /* Configure : NSS management */
00313   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
00314
00315 #ifdef USE_SPI_CRC
00316   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00317   /* Configure : CRC Polynomial */
00318   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00319   {
00320     WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
00321   }
00322 #endif
00323
00324 #if defined(SPI_I2SCFGR_I2SMOD)
00325   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00326   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00327 #endif
00328
00329   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00330   hspi->State     = HAL_SPI_STATE_READY;
00331
00332   return HAL_OK;
00333 }
00334
00335 /**
00336   * @brief  De Initialize the SPI peripheral.
00337   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00338   *               the configuration information for SPI module.
00339   * @retval HAL status
00340   */
00341 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00342 {
00343   /* Check the SPI handle allocation */
00344   if(hspi == NULL)
00345   {
00346     return HAL_ERROR;
00347   }
00348
00349   /* Check SPI Instance parameter */
00350   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00351
00352   hspi->State = HAL_SPI_STATE_BUSY;
00353
00354   /* Disable the SPI Peripheral Clock */
00355   __HAL_SPI_DISABLE(hspi);
00356
00357   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00358   HAL_SPI_MspDeInit(hspi);
00359
00360   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00361   hspi->State = HAL_SPI_STATE_RESET;
00362
00363   /* Release Lock */
00364   __HAL_UNLOCK(hspi);
00365
00366   return HAL_OK;
00367 }
00368
00369 /**
00370   * @brief  Initialize the SPI MSP.
00371   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00372   *               the configuration information for SPI module.
00373   * @retval None
00374   */
00375 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00376 {
00377   /* Prevent unused argument(s) compilation warning */
00378   UNUSED(hspi);
00379   /* NOTE : This function should not be modified, when the callback is needed,
00380             the HAL_SPI_MspInit should be implemented in the user file
00381   */
00382 }
00383
00384
00385 /**
00386   * @brief  De-Initialize the SPI MSP.
00387   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00388   *               the configuration information for SPI module.
00389   * @retval None
00390   */
00391 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00392 {
00393   /* Prevent unused argument(s) compilation warning */
00394   UNUSED(hspi);
00395   /* NOTE : This function should not be modified, when the callback is needed,
00396             the HAL_SPI_MspDeInit should be implemented in the user file
00397   */
00398 }
00399
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00405  *  @brief   Data transfers functions
00406  *
00407 @verbatim
00408   ==============================================================================
00409                       ##### IO operation functions #####
00410  ===============================================================================
00411  [..]
00412     This subsection provides a set of functions allowing to manage the SPI
00413     data transfers.
00414
00415     [..] The SPI supports master and slave mode :
00416
00417     (#) There are two modes of transfer:
00418        (++) Blocking mode: The communication is performed in polling mode.
00419             The HAL status of all data processing is returned by the same function
00420             after finishing transfer.
00421        (++) No-Blocking mode: The communication is performed using Interrupts
00422             or DMA, These APIs return the HAL status.
00423             The end of the data processing will be indicated through the
00424             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00425             using DMA mode.
00426             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00427             will be executed respectively at the end of the transmit or Receive process
00428             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00429
00430     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00431         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00432
00433 @endverbatim
00434   * @{
00435   */
00436
00437 /**
00438   * @brief  Transmit an amount of data in blocking mode.
00439   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00440   *               the configuration information for SPI module.
00441   * @param  pData: pointer to data buffer
00442   * @param  Size: amount of data to be sent
00443   * @param  Timeout: Timeout duration
00444   * @retval HAL status
00445   */
00446 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00447 {
00448   uint32_t tickstart = 0U;
00449   HAL_StatusTypeDef errorcode = HAL_OK;
00450
00451   /* Check Direction parameter */
00452   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00453
00454   /* Process Locked */
00455   __HAL_LOCK(hspi);
00456
00457   /* Init tickstart for timeout managment*/
00458   tickstart = HAL_GetTick();
00459
00460   if(hspi->State != HAL_SPI_STATE_READY)
00461   {
00462     errorcode = HAL_BUSY;
00463     goto error;
00464   }
00465
00466   if((pData == NULL ) || (Size == 0U))
00467   {
00468     errorcode = HAL_ERROR;
00469     goto error;
00470   }
00471
00472   /* Set the transaction information */
00473   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00474   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00475   hspi->pTxBuffPtr  = (uint8_t *)pData;
00476   hspi->TxXferSize  = Size;
00477   hspi->TxXferCount = Size;
00478
00479   /*Init field not used in handle to zero */
00480   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00481   hspi->RxXferSize  = 0U;
00482   hspi->RxXferCount = 0U;
00483   hspi->TxISR       = NULL;
00484   hspi->RxISR       = NULL;
00485
00486   /* Configure communication direction : 1Line */
00487   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00488   {
00489     SPI_1LINE_TX(hspi);
00490   }
00491
00492 #ifdef USE_SPI_CRC
00493   /* Reset CRC Calculation */
00494   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00495   {
00496     SPI_RESET_CRC(hspi);
00497   }
00498 #endif
00499
00500   /* Check if the SPI is already enabled */
00501   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00502   {
00503     /* Enable SPI peripheral */
00504     __HAL_SPI_ENABLE(hspi);
00505   }
00506
00507   /* Transmit data in 16 Bit mode */
00508   if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00509   {
00510     /* Transmit data in 16 Bit mode */
00511     while (hspi->TxXferCount > 0U)
00512     {
00513       /* Wait until TXE flag is set to send data */
00514       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00515       {
00516           hspi->Instance->DR = *((uint16_t *)pData);
00517           pData += sizeof(uint16_t);
00518           hspi->TxXferCount--;
00519       }
00520       else
00521       {
00522         /* Timeout management */
00523         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00524         {
00525           errorcode = HAL_TIMEOUT;
00526           goto error;
00527         }
00528       }
00529     }
00530   }
00531   /* Transmit data in 8 Bit mode */
00532   else
00533   {
00534     while (hspi->TxXferCount > 0U)
00535     {
00536       /* Wait until TXE flag is set to send data */
00537       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00538       {
00539         *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
00540         pData += sizeof(uint8_t);
00541         hspi->TxXferCount--;
00542       }
00543       else
00544       {
00545         /* Timeout management */
00546         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00547         {
00548           errorcode = HAL_TIMEOUT;
00549           goto error;
00550         }
00551       }
00552     }
00553   }
00554
00555 #ifdef USE_SPI_CRC
00556   /* Enable CRC Transmission */
00557   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00558   {
00559      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00560   }
00561 #endif
00562
00563   /* Check the end of the transaction */
00564   if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
00565   {
00566     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
00567   }
00568
00569   /* Clear overrun flag in 2 Lines communication mode because received is not read */
00570   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
00571   {
00572     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00573   }
00574
00575   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00576   {
00577     errorcode = HAL_ERROR;
00578   }
00579
00580 error:
00581   hspi->State = HAL_SPI_STATE_READY;
00582   /* Process Unlocked */
00583   __HAL_UNLOCK(hspi);
00584   return errorcode;
00585 }
00586
00587 /**
00588   * @brief  Receive an amount of data in blocking mode.
00589   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00590   *               the configuration information for SPI module.
00591   * @param  pData: pointer to data buffer
00592   * @param  Size: amount of data to be received
00593   * @param  Timeout: Timeout duration
00594   * @retval HAL status
00595   */
00596 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00597 {
00598 #ifdef USE_SPI_CRC
00599   __IO uint16_t tmpreg = 0U;
00600 #endif
00601   uint32_t tickstart = 0U;
00602   HAL_StatusTypeDef errorcode = HAL_OK;
00603
00604   if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00605   {
00606      hspi->State = HAL_SPI_STATE_BUSY_RX;
00607      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
00608     return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
00609   }
00610
00611   /* Process Locked */
00612   __HAL_LOCK(hspi);
00613
00614   /* Init tickstart for timeout managment*/
00615   tickstart = HAL_GetTick();
00616
00617   if(hspi->State != HAL_SPI_STATE_READY)
00618   {
00619     errorcode = HAL_BUSY;
00620     goto error;
00621   }
00622
00623   if((pData == NULL ) || (Size == 0U))
00624   {
00625     errorcode = HAL_ERROR;
00626     goto error;
00627   }
00628
00629   /* Set the transaction information */
00630   hspi->State       = HAL_SPI_STATE_BUSY_RX;
00631   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00632   hspi->pRxBuffPtr  = (uint8_t *)pData;
00633   hspi->RxXferSize  = Size;
00634   hspi->RxXferCount = Size;
00635
00636   /*Init field not used in handle to zero */
00637   hspi->pTxBuffPtr  = (uint8_t *)NULL;
00638   hspi->TxXferSize  = 0U;
00639   hspi->TxXferCount = 0U;
00640   hspi->RxISR       = NULL;
00641   hspi->TxISR       = NULL;
00642
00643 #ifdef USE_SPI_CRC
00644   /* Reset CRC Calculation */
00645   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00646   {
00647     SPI_RESET_CRC(hspi);
00648     /* this is done to handle the CRCNEXT before the latest data */
00649     hspi->RxXferCount--;
00650   }
00651 #endif
00652
00653   /* Configure communication direction: 1Line */
00654   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00655   {
00656     SPI_1LINE_RX(hspi);
00657   }
00658
00659   /* Check if the SPI is already enabled */
00660   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00661   {
00662     /* Enable SPI peripheral */
00663     __HAL_SPI_ENABLE(hspi);
00664   }
00665
00666     /* Receive data in 8 Bit mode */
00667   if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
00668   {
00669     /* Transfer loop */
00670     while(hspi->RxXferCount > 0U)
00671     {
00672       /* Check the RXNE flag */
00673       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00674       {
00675         /* read the received data */
00676         (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
00677         pData += sizeof(uint8_t);
00678         hspi->RxXferCount--;
00679       }
00680       else
00681       {
00682         /* Timeout management */
00683         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00684         {
00685           errorcode = HAL_TIMEOUT;
00686           goto error;
00687         }
00688       }
00689     }
00690   }
00691   else
00692   {
00693     /* Transfer loop */
00694     while(hspi->RxXferCount > 0U)
00695     {
00696       /* Check the RXNE flag */
00697       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00698       {
00699         *((uint16_t*)pData) = hspi->Instance->DR;
00700         pData += sizeof(uint16_t);
00701         hspi->RxXferCount--;
00702       }
00703       else
00704       {
00705         /* Timeout management */
00706         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00707         {
00708           errorcode = HAL_TIMEOUT;
00709           goto error;
00710         }
00711       }
00712     }
00713   }
00714
00715 #ifdef USE_SPI_CRC
00716   /* Handle the CRC Transmission */
00717   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00718   {
00719     /* freeze the CRC before the latest data */
00720     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00721
00722     /* Read the latest data */
00723     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00724     {
00725       /* the latest data has not been received */
00726       errorcode = HAL_TIMEOUT;
00727       goto error;
00728     }
00729
00730     /* Receive last data in 16 Bit mode */
00731     if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00732     {
00733       *((uint16_t*)pData) = hspi->Instance->DR;
00734     }
00735     /* Receive last data in 8 Bit mode */
00736     else
00737     {
00738       (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
00739     }
00740
00741     /* Wait the CRC data */
00742     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00743     {
00744       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00745       errorcode = HAL_TIMEOUT;
00746       goto error;
00747     }
00748
00749     /* Read CRC to Flush DR and RXNE flag */
00750     tmpreg = hspi->Instance->DR;
00751     /* To avoid GCC warning */
00752     UNUSED(tmpreg);
00753   }
00754 #endif
00755
00756   /* Check the end of the transaction */
00757   if(SPI_CheckForDisablingSPI(hspi) != HAL_OK)
00758   {
00759     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
00760   }
00761
00762   /* Control the BSY flag */
00763   if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
00764   {
00765     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
00766     errorcode = HAL_ERROR;
00767   }
00768
00769 #ifdef USE_SPI_CRC
00770   /* Check if CRC error occurred */
00771   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
00772   {
00773     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00774     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00775   }
00776 #endif
00777
00778   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00779   {
00780     errorcode = HAL_ERROR;
00781   }
00782
00783 error :
00784   hspi->State = HAL_SPI_STATE_READY;
00785   __HAL_UNLOCK(hspi);
00786   return errorcode;
00787 }
00788
00789 /**
00790   * @brief  Transmit and Receive an amount of data in blocking mode.
00791   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00792   *               the configuration information for SPI module.
00793   * @param  pTxData: pointer to transmission data buffer
00794   * @param  pRxData: pointer to reception data buffer
00795   * @param  Size: amount of data to be sent and received
00796   * @param  Timeout: Timeout duration
00797   * @retval HAL status
00798   */
00799 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00800 {
00801 #ifdef USE_SPI_CRC
00802   __IO uint16_t tmpreg = 0U;
00803 #endif
00804   uint32_t tickstart = 0U;
00805   HAL_StatusTypeDef errorcode = HAL_OK;
00806
00807   /* Check Direction parameter */
00808   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
00809
00810   /* Process Locked */
00811   __HAL_LOCK(hspi);
00812
00813   /* Init tickstart for timeout managment*/
00814   tickstart = HAL_GetTick();
00815
00816   if(!((hspi->State == HAL_SPI_STATE_READY) || \
00817     ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
00818   {
00819     errorcode = HAL_BUSY;
00820     goto error;
00821   }
00822
00823   if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00824   {
00825     errorcode = HAL_ERROR;
00826     goto error;
00827   }
00828
00829   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
00830   if(hspi->State == HAL_SPI_STATE_READY)
00831   {
00832     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
00833   }
00834
00835   /* Set the transaction information */
00836   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00837   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
00838   hspi->RxXferCount = Size;
00839   hspi->RxXferSize  = Size;
00840   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
00841   hspi->TxXferCount = Size;
00842   hspi->TxXferSize  = Size;
00843
00844   /*Init field not used in handle to zero */
00845   hspi->RxISR       = NULL;
00846   hspi->TxISR       = NULL;
00847
00848 #ifdef USE_SPI_CRC
00849   /* Reset CRC Calculation */
00850   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00851   {
00852     SPI_RESET_CRC(hspi);
00853   }
00854 #endif
00855
00856   /* Check if the SPI is already enabled */
00857   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
00858   {
00859     /* Enable SPI peripheral */
00860     __HAL_SPI_ENABLE(hspi);
00861   }
00862
00863   /* Transmit and Receive data in 16 Bit mode */
00864   if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00865   {
00866     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
00867     {
00868       /* Check TXE flag */
00869       if((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
00870       {
00871         hspi->Instance->DR = *((uint16_t *)pTxData);
00872         pTxData += sizeof(uint16_t);
00873         hspi->TxXferCount--;
00874
00875 #ifdef USE_SPI_CRC
00876         /* Enable CRC Transmission */
00877         if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00878         {
00879           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00880         }
00881 #endif
00882       }
00883
00884       /* Check RXNE flag */
00885       if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
00886       {
00887         *((uint16_t *)pRxData) = hspi->Instance->DR;
00888         pRxData += sizeof(uint16_t);
00889         hspi->RxXferCount--;
00890       }
00891       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
00892       {
00893         errorcode = HAL_TIMEOUT;
00894         goto error;
00895       }
00896     }
00897   }
00898   /* Transmit and Receive data in 8 Bit mode */
00899   else
00900   {
00901     while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
00902     {
00903       /* check TXE flag */
00904       if((hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
00905       {
00906         *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
00907         hspi->TxXferCount--;
00908
00909 #ifdef USE_SPI_CRC
00910         /* Enable CRC Transmission */
00911         if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00912         {
00913           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00914         }
00915 #endif
00916       }
00917
00918       /* Wait until RXNE flag is reset */
00919       if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
00920       {
00921         (*(uint8_t *)pRxData++) = hspi->Instance->DR;
00922         hspi->RxXferCount--;
00923       }
00924       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
00925       {
00926         errorcode = HAL_TIMEOUT;
00927         goto error;
00928       }
00929     }
00930   }
00931
00932 #ifdef USE_SPI_CRC
00933   /* Read CRC from DR to close CRC calculation process */
00934   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00935   {
00936     /* Wait until TXE flag */
00937     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00938     {
00939       /* Error on the CRC reception */
00940       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00941       errorcode = HAL_TIMEOUT;
00942       goto error;
00943     }
00944     /* Read CRC */
00945     tmpreg = hspi->Instance->DR;
00946     /* To avoid GCC warning */
00947     UNUSED(tmpreg);
00948   }
00949
00950   /* Check if CRC error occurred */
00951   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
00952   {
00953     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00954     /* Clear CRC Flag */
00955     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00956
00957     errorcode = HAL_ERROR;
00958   }
00959 #endif
00960
00961   /* Check the end of the transaction */
00962   if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
00963   {
00964     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
00965     errorcode = HAL_ERROR;
00966   }
00967
00968 error :
00969   hspi->State = HAL_SPI_STATE_READY;
00970   __HAL_UNLOCK(hspi);
00971   return errorcode;
00972 }
00973
00974 /**
00975   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
00976   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00977   *               the configuration information for SPI module.
00978   * @param  pData: pointer to data buffer
00979   * @param  Size: amount of data to be sent
00980   * @retval HAL status
00981   */
00982 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
00983 {
00984   HAL_StatusTypeDef errorcode = HAL_OK;
00985
00986   /* Check Direction parameter */
00987   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00988
00989   /* Process Locked */
00990   __HAL_LOCK(hspi);
00991
00992   if((pData == NULL) || (Size == 0U))
00993   {
00994     errorcode = HAL_ERROR;
00995     goto error;
00996   }
00997
00998   if(hspi->State != HAL_SPI_STATE_READY)
00999   {
01000     errorcode = HAL_BUSY;
01001     goto error;
01002   }
01003
01004   /* Set the transaction information */
01005   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01006   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01007   hspi->pTxBuffPtr  = (uint8_t *)pData;
01008   hspi->TxXferSize  = Size;
01009   hspi->TxXferCount = Size;
01010
01011   /* Init field not used in handle to zero */
01012   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01013   hspi->RxXferSize  = 0U;
01014   hspi->RxXferCount = 0U;
01015   hspi->RxISR       = NULL;
01016
01017   /* Set the function for IT treatment */
01018   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01019   {
01020     hspi->TxISR = SPI_TxISR_16BIT;
01021   }
01022   else
01023   {
01024     hspi->TxISR = SPI_TxISR_8BIT;
01025   }
01026
01027   /* Configure communication direction : 1Line */
01028   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01029   {
01030     SPI_1LINE_TX(hspi);
01031   }
01032
01033 #ifdef USE_SPI_CRC
01034   /* Reset CRC Calculation */
01035   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01036   {
01037     SPI_RESET_CRC(hspi);
01038   }
01039 #endif
01040
01041   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
01042   {
01043     /* Enable TXE interrupt */
01044     __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
01045   }
01046   else
01047   {
01048     /* Enable TXE and ERR interrupt */
01049     __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
01050   }
01051
01052   /* Check if the SPI is already enabled */
01053   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01054   {
01055     /* Enable SPI peripheral */
01056     __HAL_SPI_ENABLE(hspi);
01057   }
01058
01059 error :
01060   __HAL_UNLOCK(hspi);
01061   return errorcode;
01062 }
01063
01064 /**
01065   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01066   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01067   *               the configuration information for SPI module.
01068   * @param  pData: pointer to data buffer
01069   * @param  Size: amount of data to be sent
01070   * @retval HAL status
01071   */
01072 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01073 {
01074   HAL_StatusTypeDef errorcode = HAL_OK;
01075
01076   if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01077   {
01078      hspi->State = HAL_SPI_STATE_BUSY_RX;
01079      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01080      return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01081   }
01082
01083   /* Process Locked */
01084   __HAL_LOCK(hspi);
01085
01086   if(hspi->State != HAL_SPI_STATE_READY)
01087   {
01088     errorcode = HAL_BUSY;
01089     goto error;
01090   }
01091   if((pData == NULL) || (Size == 0U))
01092   {
01093     errorcode = HAL_ERROR;
01094     goto error;
01095   }
01096
01097   /* Set the transaction information */
01098   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01099   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01100   hspi->pRxBuffPtr  = (uint8_t *)pData;
01101   hspi->RxXferSize  = Size;
01102   hspi->RxXferCount = Size;
01103
01104   /* Init field not used in handle to zero */
01105   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01106   hspi->TxXferSize  = 0U;
01107   hspi->TxXferCount = 0U;
01108   hspi->TxISR       = NULL;
01109
01110   /* Set the function for IT treatment */
01111   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01112   {
01113     hspi->RxISR = SPI_RxISR_16BIT;
01114   }
01115   else
01116   {
01117     hspi->RxISR = SPI_RxISR_8BIT;
01118   }
01119
01120   /* Configure communication direction : 1Line */
01121   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01122   {
01123     SPI_1LINE_RX(hspi);
01124   }
01125
01126 #ifdef USE_SPI_CRC
01127   /* Reset CRC Calculation */
01128   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01129   {
01130     SPI_RESET_CRC(hspi);
01131   }
01132 #endif
01133
01134   /* Enable TXE and ERR interrupt */
01135   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01136
01137   /* Note : The SPI must be enabled after unlocking current process
01138             to avoid the risk of SPI interrupt handle execution before current
01139             process unlock */
01140
01141   /* Check if the SPI is already enabled */
01142   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01143   {
01144     /* Enable SPI peripheral */
01145     __HAL_SPI_ENABLE(hspi);
01146   }
01147
01148 error :
01149   /* Process Unlocked */
01150   __HAL_UNLOCK(hspi);
01151   return errorcode;
01152 }
01153
01154 /**
01155   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01156   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01157   *               the configuration information for SPI module.
01158   * @param  pTxData: pointer to transmission data buffer
01159   * @param  pRxData: pointer to reception data buffer
01160   * @param  Size: amount of data to be sent and received
01161   * @retval HAL status
01162   */
01163 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01164 {
01165   HAL_StatusTypeDef errorcode = HAL_OK;
01166
01167   /* Check Direction parameter */
01168   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01169
01170   /* Process locked */
01171   __HAL_LOCK(hspi);
01172
01173   if(!((hspi->State == HAL_SPI_STATE_READY) || \
01174     ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
01175   {
01176     errorcode = HAL_BUSY;
01177     goto error;
01178   }
01179
01180   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
01181   {
01182     errorcode = HAL_ERROR;
01183     goto error;
01184   }
01185
01186   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01187   if(hspi->State == HAL_SPI_STATE_READY)
01188   {
01189     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01190   }
01191
01192   /* Set the transaction information */
01193   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01194   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01195   hspi->TxXferSize  = Size;
01196   hspi->TxXferCount = Size;
01197   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01198   hspi->RxXferSize  = Size;
01199   hspi->RxXferCount = Size;
01200
01201   /* Set the function for IT treatment */
01202   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01203   {
01204     hspi->RxISR     = SPI_2linesRxISR_16BIT;
01205     hspi->TxISR     = SPI_2linesTxISR_16BIT;
01206   }
01207   else
01208   {
01209     hspi->RxISR     = SPI_2linesRxISR_8BIT;
01210     hspi->TxISR     = SPI_2linesTxISR_8BIT;
01211   }
01212
01213 #ifdef USE_SPI_CRC
01214   /* Reset CRC Calculation */
01215   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01216   {
01217     SPI_RESET_CRC(hspi);
01218   }
01219 #endif
01220
01221   /* Enable TXE, RXNE and ERR interrupt */
01222   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01223
01224   /* Check if the SPI is already enabled */
01225   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01226   {
01227     /* Enable SPI peripheral */
01228     __HAL_SPI_ENABLE(hspi);
01229   }
01230
01231 error :
01232   /* Process Unlocked */
01233   __HAL_UNLOCK(hspi);
01234   return errorcode;
01235 }
01236
01237 /**
01238   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01239   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01240   *               the configuration information for SPI module.
01241   * @param  pData: pointer to data buffer
01242   * @param  Size: amount of data to be sent
01243   * @retval HAL status
01244   */
01245 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01246 {
01247   HAL_StatusTypeDef errorcode = HAL_OK;
01248
01249   /* Check Direction parameter */
01250   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01251
01252   /* Process Locked */
01253   __HAL_LOCK(hspi);
01254
01255   if(hspi->State != HAL_SPI_STATE_READY)
01256   {
01257     errorcode = HAL_BUSY;
01258     goto error;
01259   }
01260
01261   if((pData == NULL) || (Size == 0U))
01262   {
01263     errorcode = HAL_ERROR;
01264     goto error;
01265   }
01266
01267   /* Set the transaction information */
01268   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01269   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01270   hspi->pTxBuffPtr  = (uint8_t *)pData;
01271   hspi->TxXferSize  = Size;
01272   hspi->TxXferCount = Size;
01273
01274   /* Init field not used in handle to zero */
01275   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01276   hspi->TxISR       = NULL;
01277   hspi->RxISR       = NULL;
01278   hspi->RxXferSize  = 0U;
01279   hspi->RxXferCount = 0U;
01280
01281   /* Configure communication direction : 1Line */
01282   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01283   {
01284     SPI_1LINE_TX(hspi);
01285   }
01286
01287 #ifdef USE_SPI_CRC
01288   /* Reset CRC Calculation */
01289   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01290   {
01291     SPI_RESET_CRC(hspi);
01292   }
01293 #endif
01294
01295   /* Set the SPI TxDMA Half transfer complete callback */
01296   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01297
01298   /* Set the SPI TxDMA transfer complete callback */
01299   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01300
01301   /* Set the DMA error callback */
01302   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01303
01304   /* Enable the Tx DMA Stream */
01305   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01306
01307   /* Check if the SPI is already enabled */
01308   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01309   {
01310     /* Enable SPI peripheral */
01311     __HAL_SPI_ENABLE(hspi);
01312   }
01313
01314   /* Enable Tx DMA Request */
01315   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01316
01317 error :
01318   /* Process Unlocked */
01319   __HAL_UNLOCK(hspi);
01320   return errorcode;
01321 }
01322
01323 /**
01324   * @brief  Receive an amount of data in non-blocking mode with DMA.
01325   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01326   *               the configuration information for SPI module.
01327   * @param  pData: pointer to data buffer
01328   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
01329   * @param  Size: amount of data to be sent
01330   * @retval HAL status
01331   */
01332 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01333 {
01334   HAL_StatusTypeDef errorcode = HAL_OK;
01335
01336   if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
01337   {
01338      hspi->State = HAL_SPI_STATE_BUSY_RX;
01339      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01340      return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
01341   }
01342
01343   /* Process Locked */
01344   __HAL_LOCK(hspi);
01345
01346   if(hspi->State != HAL_SPI_STATE_READY)
01347   {
01348     errorcode = HAL_BUSY;
01349     goto error;
01350   }
01351
01352   if((pData == NULL) || (Size == 0U))
01353   {
01354     errorcode = HAL_ERROR;
01355     goto error;
01356   }
01357
01358   /* Set the transaction information */
01359   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01360   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01361   hspi->pRxBuffPtr  = (uint8_t *)pData;
01362   hspi->RxXferSize  = Size;
01363   hspi->RxXferCount = Size;
01364
01365   /*Init field not used in handle to zero */
01366   hspi->RxISR       = NULL;
01367   hspi->TxISR       = NULL;
01368   hspi->TxXferSize  = 0U;
01369   hspi->TxXferCount = 0U;
01370
01371   /* Configure communication direction : 1Line */
01372   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01373   {
01374     SPI_1LINE_RX(hspi);
01375   }
01376
01377 #ifdef USE_SPI_CRC
01378   /* Reset CRC Calculation */
01379   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01380   {
01381     SPI_RESET_CRC(hspi);
01382   }
01383 #endif
01384
01385   /* Set the SPI RxDMA Half transfer complete callback */
01386   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01387
01388   /* Set the SPI Rx DMA transfer complete callback */
01389   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01390
01391   /* Set the DMA error callback */
01392   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01393
01394   /* Enable the Rx DMA Stream */
01395   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01396
01397   /* Check if the SPI is already enabled */
01398   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01399   {
01400     /* Enable SPI peripheral */
01401     __HAL_SPI_ENABLE(hspi);
01402   }
01403
01404   /* Enable Rx DMA Request */
01405   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01406
01407 error:
01408   /* Process Unlocked */
01409   __HAL_UNLOCK(hspi);
01410   return errorcode;
01411 }
01412
01413 /**
01414   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
01415   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01416   *               the configuration information for SPI module.
01417   * @param  pTxData: pointer to transmission data buffer
01418   * @param  pRxData: pointer to reception data buffer
01419   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
01420   * @param  Size: amount of data to be sent
01421   * @retval HAL status
01422   */
01423 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01424 {
01425   HAL_StatusTypeDef errorcode = HAL_OK;
01426
01427   /* Check Direction parameter */
01428   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01429
01430   /* Process locked */
01431   __HAL_LOCK(hspi);
01432
01433   if(!((hspi->State == HAL_SPI_STATE_READY) ||
01434       ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
01435   {
01436     errorcode = HAL_BUSY;
01437     goto error;
01438   }
01439
01440   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
01441   {
01442     errorcode = HAL_ERROR;
01443     goto error;
01444   }
01445
01446   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01447   if(hspi->State == HAL_SPI_STATE_READY)
01448   {
01449     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01450   }
01451
01452   /* Set the transaction information */
01453   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01454   hspi->pTxBuffPtr  = (uint8_t*)pTxData;
01455   hspi->TxXferSize  = Size;
01456   hspi->TxXferCount = Size;
01457   hspi->pRxBuffPtr  = (uint8_t*)pRxData;
01458   hspi->RxXferSize  = Size;
01459   hspi->RxXferCount = Size;
01460
01461   /* Init field not used in handle to zero */
01462   hspi->RxISR       = NULL;
01463   hspi->TxISR       = NULL;
01464
01465 #ifdef USE_SPI_CRC
01466   /* Reset CRC Calculation */
01467   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01468   {
01469     SPI_RESET_CRC(hspi);
01470   }
01471 #endif
01472
01473   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
01474   if(hspi->State == HAL_SPI_STATE_BUSY_RX)
01475   {
01476     /* Set the SPI Rx DMA Half transfer complete callback */
01477     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01478     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
01479   }
01480   else
01481   {
01482     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
01483     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
01484     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
01485   }
01486
01487   /* Set the DMA error callback */
01488   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01489
01490   /* Enable the Rx DMA Stream */
01491   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01492
01493   /* Enable Rx DMA Request */
01494   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01495
01496   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
01497   is performed in DMA reception complete callback  */
01498   hspi->hdmatx->XferHalfCpltCallback = NULL;
01499   hspi->hdmatx->XferCpltCallback = NULL;
01500
01501   /* Set the DMA error callback */
01502   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01503
01504   /* Enable the Tx DMA Stream */
01505   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01506
01507   /* Check if the SPI is already enabled */
01508   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01509   {
01510     /* Enable SPI peripheral */
01511     __HAL_SPI_ENABLE(hspi);
01512   }
01513
01514   /* Enable Tx DMA Request */
01515   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01516
01517 error :
01518   /* Process Unlocked */
01519   __HAL_UNLOCK(hspi);
01520   return errorcode;
01521 }
01522
01523 /**
01524   * @brief  Pause the DMA Transfer.
01525   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01526   *               the configuration information for the specified SPI module.
01527   * @retval HAL status
01528   */
01529 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
01530 {
01531   /* Process Locked */
01532   __HAL_LOCK(hspi);
01533
01534   /* Disable the SPI DMA Tx & Rx requests */
01535   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01536
01537   /* Process Unlocked */
01538   __HAL_UNLOCK(hspi);
01539
01540   return HAL_OK;
01541 }
01542
01543 /**
01544   * @brief  Resume the DMA Transfer.
01545   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01546   *               the configuration information for the specified SPI module.
01547   * @retval HAL status
01548   */
01549 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
01550 {
01551   /* Process Locked */
01552   __HAL_LOCK(hspi);
01553
01554   /* Enable the SPI DMA Tx & Rx requests */
01555   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01556
01557   /* Process Unlocked */
01558   __HAL_UNLOCK(hspi);
01559
01560   return HAL_OK;
01561 }
01562
01563 /**
01564   * @brief Stop the DMA Transfer.
01565   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01566   *               the configuration information for the specified SPI module.
01567   * @retval HAL status
01568   */
01569 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
01570 {
01571   /* The Lock is not implemented on this API to allow the user application
01572      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
01573      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01574      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
01575      */
01576
01577   /* Abort the SPI DMA tx Stream */
01578   if(hspi->hdmatx != NULL)
01579   {
01580     HAL_DMA_Abort(hspi->hdmatx);
01581   }
01582   /* Abort the SPI DMA rx Stream */
01583   if(hspi->hdmarx != NULL)
01584   {
01585     HAL_DMA_Abort(hspi->hdmarx);
01586   }
01587
01588   /* Disable the SPI DMA Tx & Rx requests */
01589   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01590   hspi->State = HAL_SPI_STATE_READY;
01591   return HAL_OK;
01592 }
01593
01594 /**
01595   * @brief  Handle SPI interrupt request.
01596   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01597   *               the configuration information for the specified SPI module.
01598   * @retval None
01599   */
01600 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
01601 {
01602   uint32_t itsource = hspi->Instance->CR2;
01603   uint32_t itflag   = hspi->Instance->SR;
01604
01605   /* SPI in mode Receiver ----------------------------------------------------*/
01606   if(((itflag & SPI_FLAG_OVR) == RESET) &&
01607      ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
01608   {
01609     hspi->RxISR(hspi);
01610     return;
01611   }
01612
01613   /* SPI in mode Transmitter ---------------------------------------------------*/
01614   if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
01615   {
01616     hspi->TxISR(hspi);
01617     return;
01618   }
01619
01620   /* SPI in Error Treatment ---------------------------------------------------*/
01621  if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
01622   {
01623     /* SPI Overrun error interrupt occurred -------------------------------------*/
01624     if((itflag & SPI_FLAG_OVR) != RESET)
01625     {
01626       if(hspi->State != HAL_SPI_STATE_BUSY_TX)
01627       {
01628         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
01629         __HAL_SPI_CLEAR_OVRFLAG(hspi);
01630       }
01631       else
01632       {
01633         return;
01634       }
01635     }
01636
01637     /* SPI Mode Fault error interrupt occurred -------------------------------------*/
01638     if((itflag & SPI_FLAG_MODF) != RESET)
01639     {
01640       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
01641       __HAL_SPI_CLEAR_MODFFLAG(hspi);
01642     }
01643
01644     /* SPI Frame error interrupt occurred ----------------------------------------*/
01645     if((itflag & SPI_FLAG_FRE) != RESET)
01646     {
01647       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
01648       __HAL_SPI_CLEAR_FREFLAG(hspi);
01649     }
01650
01651     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
01652     hspi->State = HAL_SPI_STATE_READY;
01653     HAL_SPI_ErrorCallback(hspi);
01654     return;
01655   }
01656 }
01657
01658 /**
01659   * @brief Tx Transfer completed callback.
01660   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01661   *               the configuration information for SPI module.
01662   * @retval None
01663   */
01664 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
01665 {
01666   /* Prevent unused argument(s) compilation warning */
01667   UNUSED(hspi);
01668   /* NOTE : This function should not be modified, when the callback is needed,
01669             the HAL_SPI_TxCpltCallback should be implemented in the user file
01670   */
01671 }
01672
01673 /**
01674   * @brief Rx Transfer completed callback.
01675   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01676   *               the configuration information for SPI module.
01677   * @retval None
01678   */
01679 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
01680 {
01681   /* Prevent unused argument(s) compilation warning */
01682   UNUSED(hspi);
01683   /* NOTE : This function should not be modified, when the callback is needed,
01684             the HAL_SPI_RxCpltCallback should be implemented in the user file
01685   */
01686 }
01687
01688 /**
01689   * @brief Tx and Rx Transfer completed callback.
01690   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01691   *               the configuration information for SPI module.
01692   * @retval None
01693   */
01694 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
01695 {
01696   /* Prevent unused argument(s) compilation warning */
01697   UNUSED(hspi);
01698   /* NOTE : This function should not be modified, when the callback is needed,
01699             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
01700   */
01701 }
01702
01703 /**
01704   * @brief Tx Half Transfer completed callback.
01705   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01706   *               the configuration information for SPI module.
01707   * @retval None
01708   */
01709 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01710 {
01711   /* Prevent unused argument(s) compilation warning */
01712   UNUSED(hspi);
01713   /* NOTE : This function should not be modified, when the callback is needed,
01714             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
01715   */
01716 }
01717
01718 /**
01719   * @brief Rx Half Transfer completed callback.
01720   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01721   *               the configuration information for SPI module.
01722   * @retval None
01723   */
01724 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01725 {
01726   /* Prevent unused argument(s) compilation warning */
01727   UNUSED(hspi);
01728   /* NOTE : This function should not be modified, when the callback is needed,
01729             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
01730   */
01731 }
01732
01733 /**
01734   * @brief Tx and Rx Half Transfer callback.
01735   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01736   *               the configuration information for SPI module.
01737   * @retval None
01738   */
01739 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01740 {
01741   /* Prevent unused argument(s) compilation warning */
01742   UNUSED(hspi);
01743   /* NOTE : This function should not be modified, when the callback is needed,
01744             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
01745   */
01746 }
01747
01748 /**
01749   * @brief SPI error callback.
01750   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01751   *               the configuration information for SPI module.
01752   * @retval None
01753   */
01754  __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
01755 {
01756   /* Prevent unused argument(s) compilation warning */
01757   UNUSED(hspi);
01758   /* NOTE : This function should not be modified, when the callback is needed,
01759             the HAL_SPI_ErrorCallback should be implemented in the user file
01760    */
01761   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
01762             and user can use HAL_SPI_GetError() API to check the latest error occurred
01763   */
01764 }
01765
01766 /**
01767   * @}
01768   */
01769
01770 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
01771   * @brief   SPI control functions
01772   *
01773 @verbatim
01774  ===============================================================================
01775                       ##### Peripheral State and Errors functions #####
01776  ===============================================================================
01777     [..]
01778     This subsection provides a set of functions allowing to control the SPI.
01779      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
01780      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
01781 @endverbatim
01782   * @{
01783   */
01784
01785 /**
01786   * @brief  Return the SPI handle state.
01787   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01788   *               the configuration information for SPI module.
01789   * @retval SPI state
01790   */
01791 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
01792 {
01793   /* Return SPI handle state */
01794   return hspi->State;
01795 }
01796
01797 /**
01798   * @brief  Return the SPI error code.
01799   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01800   *               the configuration information for SPI module.
01801   * @retval SPI error code in bitmap format
01802   */
01803 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
01804 {
01805   /* Return SPI ErrorCode */
01806   return hspi->ErrorCode;
01807 }
01808
01809 /**
01810   * @}
01811   */
01812
01813 /**
01814   * @}
01815   */
01816
01817 /** @addtogroup SPI_Private_Functions
01818   * @brief   Private functions
01819   * @{
01820   */
01821
01822 /**
01823   * @brief DMA SPI transmit process complete callback.
01824   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01825   *               the configuration information for the specified DMA module.
01826   * @retval None
01827   */
01828 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01829 {
01830   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01831   uint32_t tickstart = 0U;
01832
01833   /* Init tickstart for timeout managment*/
01834   tickstart = HAL_GetTick();
01835
01836   /* DMA Normal Mode */
01837   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01838   {
01839     /* Disable Tx DMA Request */
01840     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01841
01842     /* Check the end of the transaction */
01843     if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
01844     {
01845       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
01846     }
01847
01848     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
01849     if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
01850     {
01851       __HAL_SPI_CLEAR_OVRFLAG(hspi);
01852     }
01853
01854     hspi->TxXferCount = 0U;
01855     hspi->State = HAL_SPI_STATE_READY;
01856
01857     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01858     {
01859       HAL_SPI_ErrorCallback(hspi);
01860       return;
01861     }
01862   }
01863   HAL_SPI_TxCpltCallback(hspi);
01864 }
01865
01866 /**
01867   * @brief DMA SPI receive process complete callback.
01868   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01869   *               the configuration information for the specified DMA module.
01870   * @retval None
01871   */
01872 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01873 {
01874   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01875 #ifdef USE_SPI_CRC
01876   uint32_t tickstart = 0U;
01877   __IO uint16_t tmpreg = 0U;
01878
01879   /* Init tickstart for timeout managment*/
01880   tickstart = HAL_GetTick();
01881 #endif
01882
01883   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01884   {
01885 #ifdef USE_SPI_CRC
01886     /* CRC handling */
01887     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01888     {
01889       /* Wait until TXE flag */
01890       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
01891       {
01892         /* Error on the CRC reception */
01893         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01894       }
01895       /* Read CRC */
01896       tmpreg = hspi->Instance->DR;
01897       /* To avoid GCC warning */
01898       UNUSED(tmpreg);
01899     }
01900 #endif
01901
01902     /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
01903     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01904
01905     /* Check the end of the transaction */
01906     if(SPI_CheckForDisablingSPI(hspi)!=HAL_OK)
01907     {
01908       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
01909     }
01910
01911     hspi->RxXferCount = 0U;
01912     hspi->State = HAL_SPI_STATE_READY;
01913
01914 #ifdef USE_SPI_CRC
01915     /* Check if CRC error occurred */
01916     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01917     {
01918       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01919       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01920     }
01921 #endif
01922
01923     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01924     {
01925       HAL_SPI_ErrorCallback(hspi);
01926       return;
01927     }
01928   }
01929   HAL_SPI_RxCpltCallback(hspi);
01930 }
01931
01932 /**
01933   * @brief  DMA SPI transmit receive process complete callback.
01934   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01935   *               the configuration information for the specified DMA module.
01936   * @retval None
01937   */
01938 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
01939 {
01940   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01941   uint32_t tickstart = 0U;
01942 #ifdef USE_SPI_CRC
01943   __IO int16_t tmpreg = 0U;
01944 #endif
01945
01946   /* Init tickstart for timeout managment*/
01947   tickstart = HAL_GetTick();
01948
01949   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01950   {
01951 #ifdef USE_SPI_CRC
01952     /* CRC handling */
01953     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01954     {
01955       /* Wait the CRC data */
01956       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
01957       {
01958         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01959       }
01960       /* Read CRC to Flush DR and RXNE flag */
01961       tmpreg = hspi->Instance->DR;
01962       /* To avoid GCC warning */
01963       UNUSED(tmpreg);
01964     }
01965 #endif
01966
01967     /* Check the end of the transaction */
01968     if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
01969     {
01970       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
01971     }
01972
01973     /* Disable Rx/Tx DMA Request */
01974     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01975
01976     hspi->TxXferCount = 0U;
01977     hspi->RxXferCount = 0U;
01978     hspi->State = HAL_SPI_STATE_READY;
01979
01980 #ifdef USE_SPI_CRC
01981     /* Check if CRC error occurred */
01982     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01983     {
01984       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01985       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01986     }
01987 #endif
01988
01989     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01990     {
01991       HAL_SPI_ErrorCallback(hspi);
01992       return;
01993     }
01994   }
01995   HAL_SPI_TxRxCpltCallback(hspi);
01996 }
01997
01998 /**
01999   * @brief  DMA SPI half transmit process complete callback.
02000   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02001   *               the configuration information for the specified DMA module.
02002   * @retval None
02003   */
02004 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
02005 {
02006   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02007
02008   HAL_SPI_TxHalfCpltCallback(hspi);
02009 }
02010
02011 /**
02012   * @brief  DMA SPI half receive process complete callback
02013   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02014   *               the configuration information for the specified DMA module.
02015   * @retval None
02016   */
02017 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
02018 {
02019   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02020
02021   HAL_SPI_RxHalfCpltCallback(hspi);
02022 }
02023
02024 /**
02025   * @brief  DMA SPI half transmit receive process complete callback.
02026   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02027   *               the configuration information for the specified DMA module.
02028   * @retval None
02029   */
02030 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02031 {
02032   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02033
02034   HAL_SPI_TxRxHalfCpltCallback(hspi);
02035 }
02036
02037 /**
02038   * @brief  DMA SPI communication error callback.
02039   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02040   *               the configuration information for the specified DMA module.
02041   * @retval None
02042   */
02043 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
02044 {
02045   SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02046
02047 /* Stop the disable DMA transfer on SPI side */
02048   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02049
02050   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02051   hspi->State = HAL_SPI_STATE_READY;
02052   HAL_SPI_ErrorCallback(hspi);
02053 }
02054
02055 /**
02056   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
02057   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02058   *               the configuration information for SPI module.
02059   * @retval None
02060   */
02061 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02062 {
02063   /* Receive data in 8bit mode */
02064   *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
02065   hspi->RxXferCount--;
02066
02067   /* check end of the reception */
02068   if(hspi->RxXferCount == 0U)
02069   {
02070 #ifdef USE_SPI_CRC
02071     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02072     {
02073       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
02074       return;
02075     }
02076 #endif
02077
02078     /* Disable RXNE interrupt */
02079     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02080
02081     if(hspi->TxXferCount == 0U)
02082     {
02083       SPI_CloseRxTx_ISR(hspi);
02084     }
02085   }
02086 }
02087
02088 #ifdef USE_SPI_CRC
02089 /**
02090   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
02091   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02092   *               the configuration information for SPI module.
02093   * @retval None
02094   */
02095 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02096 {
02097   __IO uint8_t tmpreg = 0U;
02098
02099   /* Read data register to flush CRC */
02100   tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
02101
02102   /* To avoid GCC warning */
02103
02104   UNUSED(tmpreg);
02105
02106    /* Disable RXNE interrupt */
02107   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02108
02109   if(hspi->TxXferCount == 0U)
02110   {
02111     SPI_CloseRxTx_ISR(hspi);
02112   }
02113 }
02114 #endif
02115
02116 /**
02117   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
02118   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02119   *               the configuration information for SPI module.
02120   * @retval None
02121   */
02122 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02123 {
02124   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02125   hspi->TxXferCount--;
02126
02127   /* check the end of the transmission */
02128   if(hspi->TxXferCount == 0U)
02129   {
02130 #ifdef USE_SPI_CRC
02131     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02132     {
02133       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02134     }
02135 #endif
02136
02137     /* Disable TXE interrupt */
02138     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02139
02140     if(hspi->RxXferCount == 0U)
02141     {
02142       SPI_CloseRxTx_ISR(hspi);
02143     }
02144   }
02145 }
02146
02147 /**
02148   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
02149   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02150   *               the configuration information for SPI module.
02151   * @retval None
02152   */
02153 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02154 {
02155   /* Receive data in 16 Bit mode */
02156   *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
02157   hspi->pRxBuffPtr += sizeof(uint16_t);
02158   hspi->RxXferCount--;
02159
02160   if(hspi->RxXferCount == 0U)
02161   {
02162 #ifdef USE_SPI_CRC
02163     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02164     {
02165       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
02166       return;
02167     }
02168 #endif
02169
02170     /* Disable RXNE interrupt */
02171     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02172
02173     if(hspi->TxXferCount == 0U)
02174     {
02175       SPI_CloseRxTx_ISR(hspi);
02176     }
02177   }
02178 }
02179
02180 #ifdef USE_SPI_CRC
02181 /**
02182   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
02183   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02184   *               the configuration information for SPI module.
02185   * @retval None
02186   */
02187 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02188 {
02189   /* Receive data in 16 Bit mode */
02190   __IO uint16_t tmpreg = 0U;
02191
02192   /* Read data register to flush CRC */
02193   tmpreg = hspi->Instance->DR;
02194
02195   /* To avoid GCC warning */
02196   UNUSED(tmpreg);
02197
02198   /* Disable RXNE interrupt */
02199   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02200
02201   SPI_CloseRxTx_ISR(hspi);
02202 }
02203 #endif
02204
02205 /**
02206   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
02207   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02208   *               the configuration information for SPI module.
02209   * @retval None
02210   */
02211 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02212 {
02213   /* Transmit data in 16 Bit mode */
02214   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02215   hspi->pTxBuffPtr += sizeof(uint16_t);
02216   hspi->TxXferCount--;
02217
02218   /* Enable CRC Transmission */
02219   if(hspi->TxXferCount == 0U)
02220   {
02221 #ifdef USE_SPI_CRC
02222     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02223     {
02224       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02225     }
02226 #endif
02227
02228     /* Disable TXE interrupt */
02229     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02230
02231     if(hspi->RxXferCount == 0U)
02232     {
02233       SPI_CloseRxTx_ISR(hspi);
02234     }
02235   }
02236 }
02237
02238 #ifdef USE_SPI_CRC
02239 /**
02240   * @brief  Manage the CRC 8-bit receive in Interrupt context.
02241   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02242   *               the configuration information for SPI module.
02243   * @retval None
02244   */
02245 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02246 {
02247   __IO uint8_t tmpreg = 0U;
02248
02249   /* Read data register to flush CRC */
02250   tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
02251
02252   /* To avoid GCC warning */
02253   UNUSED(tmpreg);
02254
02255   SPI_CloseRx_ISR(hspi);
02256 }
02257 #endif
02258
02259 /**
02260   * @brief  Manage the receive 8-bit in Interrupt context.
02261   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02262   *               the configuration information for SPI module.
02263   * @retval None
02264   */
02265 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02266 {
02267   *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
02268   hspi->RxXferCount--;
02269
02270 #ifdef USE_SPI_CRC
02271   /* Enable CRC Transmission */
02272   if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02273   {
02274     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02275   }
02276 #endif
02277
02278   if(hspi->RxXferCount == 0U)
02279   {
02280 #ifdef USE_SPI_CRC
02281     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02282     {
02283       hspi->RxISR =  SPI_RxISR_8BITCRC;
02284       return;
02285     }
02286 #endif
02287     SPI_CloseRx_ISR(hspi);
02288   }
02289 }
02290
02291 #ifdef USE_SPI_CRC
02292 /**
02293   * @brief  Manage the CRC 16-bit receive in Interrupt context.
02294   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02295   *               the configuration information for SPI module.
02296   * @retval None
02297   */
02298 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02299 {
02300   __IO uint16_t tmpreg = 0U;
02301
02302   /* Read data register to flush CRC */
02303   tmpreg = hspi->Instance->DR;
02304
02305   /* To avoid GCC warning */
02306   UNUSED(tmpreg);
02307
02308   /* Disable RXNE and ERR interrupt */
02309   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02310
02311   SPI_CloseRx_ISR(hspi);
02312 }
02313 #endif
02314
02315 /**
02316   * @brief  Manage the 16-bit receive in Interrupt context.
02317   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02318   *               the configuration information for SPI module.
02319   * @retval None
02320   */
02321 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02322 {
02323   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
02324   hspi->pRxBuffPtr += sizeof(uint16_t);
02325   hspi->RxXferCount--;
02326
02327 #ifdef USE_SPI_CRC
02328   /* Enable CRC Transmission */
02329   if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02330   {
02331     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02332   }
02333 #endif
02334
02335   if(hspi->RxXferCount == 0U)
02336   {
02337 #ifdef USE_SPI_CRC
02338     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02339     {
02340       hspi->RxISR = SPI_RxISR_16BITCRC;
02341       return;
02342     }
02343 #endif
02344     SPI_CloseRx_ISR(hspi);
02345   }
02346 }
02347
02348 /**
02349   * @brief  Handle the data 8-bit transmit in Interrupt mode.
02350   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02351   *               the configuration information for SPI module.
02352   * @retval None
02353   */
02354 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02355 {
02356   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02357   hspi->TxXferCount--;
02358
02359   if(hspi->TxXferCount == 0U)
02360   {
02361 #ifdef USE_SPI_CRC
02362     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02363     {
02364       /* Enable CRC Transmission */
02365       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02366     }
02367 #endif
02368     SPI_CloseTx_ISR(hspi);
02369   }
02370 }
02371
02372 /**
02373   * @brief  Handle the data 16-bit transmit in Interrupt mode.
02374   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02375   *               the configuration information for SPI module.
02376   * @retval None
02377   */
02378 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02379 {
02380   /* Transmit data in 16 Bit mode */
02381   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02382   hspi->pTxBuffPtr += sizeof(uint16_t);
02383   hspi->TxXferCount--;
02384
02385   if(hspi->TxXferCount == 0U)
02386   {
02387 #ifdef USE_SPI_CRC
02388     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02389     {
02390       /* Enable CRC Transmission */
02391       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02392     }
02393 #endif
02394     SPI_CloseTx_ISR(hspi);
02395   }
02396 }
02397
02398 /**
02399   * @brief Handle SPI Communication Timeout.
02400   * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
02401   *              the configuration information for SPI module.
02402   * @param Flag: SPI flag to check
02403   * @param State: flag state to check
02404   * @param Timeout: Timeout duration
02405   * @param Tickstart: tick start value
02406   * @retval HAL status
02407   */
02408 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
02409 {
02410   while((hspi->Instance->SR & Flag) != State)
02411   {
02412     if(Timeout != HAL_MAX_DELAY)
02413     {
02414       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
02415       {
02416         /* Disable the SPI and reset the CRC: the CRC value should be cleared
02417         on both master and slave sides in order to resynchronize the master
02418         and slave for their respective CRC calculation */
02419
02420         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
02421         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
02422
02423         if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02424         {
02425           /* Disable SPI peripheral */
02426           __HAL_SPI_DISABLE(hspi);
02427         }
02428
02429         /* Reset CRC Calculation */
02430         if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02431         {
02432           SPI_RESET_CRC(hspi);
02433         }
02434
02435         hspi->State= HAL_SPI_STATE_READY;
02436
02437         /* Process Unlocked */
02438         __HAL_UNLOCK(hspi);
02439
02440         return HAL_TIMEOUT;
02441       }
02442     }
02443   }
02444
02445   return HAL_OK;
02446 }
02447
02448 /**
02449   * @brief  Handle to disable SPI in specific condition.
02450   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02451   *               the configuration information for SPI module.
02452   * @retval HAL status
02453   */
02454 static HAL_StatusTypeDef SPI_CheckForDisablingSPI(SPI_HandleTypeDef *hspi)
02455 {
02456   if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02457   {
02458     /* Disable SPI peripheral */
02459     __HAL_SPI_DISABLE(hspi);
02460   }
02461   return HAL_OK;
02462 }
02463
02464 /**
02465   * @brief Handle to check BSY flag before start a new transaction.
02466   * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
02467   *              the configuration information for SPI module.
02468   * @param Timeout: Timeout duration
02469   * @param Tickstart: tick start value
02470   * @retval HAL status
02471   */
02472 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
02473 {
02474   /* Control the BSY flag */
02475   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
02476   {
02477     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02478     return HAL_TIMEOUT;
02479   }
02480   return HAL_OK;
02481 }
02482
02483 /**
02484   * @brief  Handle the end of the RXTX transaction.
02485   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02486   *               the configuration information for SPI module.
02487   * @retval None
02488   */
02489 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
02490 {
02491   uint32_t tickstart = 0U;
02492
02493   /* Init tickstart for timeout managment*/
02494   tickstart = HAL_GetTick();
02495
02496   /* Disable ERR interrupt */
02497   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02498
02499   /* Check the end of the transaction */
02500   if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
02501   {
02502     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02503   }
02504
02505 #ifdef USE_SPI_CRC
02506   /* Check if CRC error occurred */
02507   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02508   {
02509     hspi->State = HAL_SPI_STATE_READY;
02510     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02511     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02512     HAL_SPI_ErrorCallback(hspi);
02513   }
02514   else
02515   {
02516 #endif
02517     if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
02518     {
02519       if(hspi->State == HAL_SPI_STATE_BUSY_RX)
02520       {
02521         hspi->State = HAL_SPI_STATE_READY;
02522         HAL_SPI_RxCpltCallback(hspi);
02523       }
02524       else
02525       {
02526         hspi->State = HAL_SPI_STATE_READY;
02527         HAL_SPI_TxRxCpltCallback(hspi);
02528       }
02529     }
02530     else
02531     {
02532       hspi->State = HAL_SPI_STATE_READY;
02533       HAL_SPI_ErrorCallback(hspi);
02534     }
02535 #ifdef USE_SPI_CRC
02536   }
02537 #endif
02538 }
02539
02540 /**
02541   * @brief  Handle the end of the RX transaction.
02542   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02543   *               the configuration information for SPI module.
02544   * @retval None
02545   */
02546 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
02547 {
02548     /* Disable RXNE and ERR interrupt */
02549     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02550
02551     /* Check the end of the transaction */
02552     if(SPI_CheckForDisablingSPI(hspi)!=HAL_OK)
02553     {
02554       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02555     }
02556     hspi->State = HAL_SPI_STATE_READY;
02557
02558 #ifdef USE_SPI_CRC
02559     /* Check if CRC error occurred */
02560     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02561     {
02562       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02563       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02564       HAL_SPI_ErrorCallback(hspi);
02565     }
02566     else
02567     {
02568 #endif
02569       if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
02570       {
02571         HAL_SPI_RxCpltCallback(hspi);
02572       }
02573       else
02574       {
02575         HAL_SPI_ErrorCallback(hspi);
02576       }
02577 #ifdef USE_SPI_CRC
02578     }
02579 #endif
02580 }
02581
02582 /**
02583   * @brief  Handle the end of the TX transaction.
02584   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02585   *               the configuration information for SPI module.
02586   * @retval None
02587   */
02588 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
02589 {
02590   uint32_t tickstart = 0U;
02591
02592   /* Init tickstart for timeout managment*/
02593   tickstart = HAL_GetTick();
02594
02595   /* Disable TXE and ERR interrupt */
02596   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
02597
02598   /* Check the end of the transaction */
02599   if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
02600   {
02601     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02602   }
02603
02604   /* Clear overrun flag in 2 Lines communication mode because received is not read */
02605   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
02606   {
02607     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02608   }
02609
02610   hspi->State = HAL_SPI_STATE_READY;
02611   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02612   {
02613     HAL_SPI_ErrorCallback(hspi);
02614   }
02615   else
02616   {
02617     HAL_SPI_TxCpltCallback(hspi);
02618   }
02619 }
02620
02621 /**
02622   * @}
02623   */
02624
02625 #endif /* HAL_SPI_MODULE_ENABLED */
02626
02627 /**
02628   * @}
02629   */
02630
02631 /**
02632   * @}
02633   */
02634
02635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_spi.h Source File

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stm32f4xx_hal_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SPI_H
00040 #define __STM32F4xx_HAL_SPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SPI_Exported_Types SPI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  SPI Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Mode;               /*!< Specifies the SPI operating mode.
00068                                      This parameter can be a value of @ref SPI_Mode */
00069
00070   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
00071                                      This parameter can be a value of @ref SPI_Direction */
00072
00073   uint32_t DataSize;           /*!< Specifies the SPI data size.
00074                                      This parameter can be a value of @ref SPI_Data_Size */
00075
00076   uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
00077                                     This parameter can be a value of @ref SPI_Clock_Polarity */
00078
00079   uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
00080                                     This parameter can be a value of @ref SPI_Clock_Phase */
00081
00082   uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
00083                                     hardware (NSS pin) or by software using the SSI bit.
00084                                     This parameter can be a value of @ref SPI_Slave_Select_management */
00085
00086   uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
00087                                     used to configure the transmit and receive SCK clock.
00088                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
00089                                     @note The communication clock is derived from the master
00090                                      clock. The slave clock does not need to be set. */
00091
00092   uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
00093                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00094
00095   uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
00096                                     This parameter can be a value of @ref SPI_TI_mode */
00097
00098   uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
00099                                     This parameter can be a value of @ref SPI_CRC_Calculation */
00100
00101   uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
00102                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
00103 }SPI_InitTypeDef;
00104
00105 /**
00106   * @brief  HAL SPI State structure definition
00107   */
00108 typedef enum
00109 {
00110   HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
00111   HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00112   HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00113   HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
00114   HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
00115   HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
00116   HAL_SPI_STATE_ERROR      = 0x06U     /*!< SPI error state                                    */
00117 }HAL_SPI_StateTypeDef;
00118
00119 /**
00120   * @brief  SPI handle Structure definition
00121   */
00122 typedef struct __SPI_HandleTypeDef
00123 {
00124   SPI_TypeDef                *Instance;    /* SPI registers base address */
00125
00126   SPI_InitTypeDef            Init;         /* SPI communication parameters */
00127
00128   uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
00129
00130   uint16_t                   TxXferSize;   /* SPI Tx Transfer size */
00131
00132   uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
00133
00134   uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
00135
00136   uint16_t                   RxXferSize;   /* SPI Rx Transfer size */
00137
00138   uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
00139
00140   void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
00141
00142   void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
00143
00144   DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA Handle parameters   */
00145
00146   DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA Handle parameters   */
00147
00148   HAL_LockTypeDef            Lock;         /* Locking object                 */
00149
00150   __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
00151
00152   __IO uint32_t              ErrorCode;    /* SPI Error code */
00153
00154 }SPI_HandleTypeDef;
00155
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported constants --------------------------------------------------------*/
00161 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00162   * @{
00163   */
00164
00165 /** @defgroup SPI_Error_Code SPI Error Code
00166   * @{
00167   */
00168 #define HAL_SPI_ERROR_NONE              ((uint32_t)0x00000000U)   /*!< No error             */
00169 #define HAL_SPI_ERROR_MODF              ((uint32_t)0x00000001U)   /*!< MODF error           */
00170 #define HAL_SPI_ERROR_CRC               ((uint32_t)0x00000002U)   /*!< CRC error            */
00171 #define HAL_SPI_ERROR_OVR               ((uint32_t)0x00000004U)   /*!< OVR error            */
00172 #define HAL_SPI_ERROR_FRE               ((uint32_t)0x00000008U)   /*!< FRE error            */
00173 #define HAL_SPI_ERROR_DMA               ((uint32_t)0x00000010U)   /*!< DMA transfer error   */
00174 #define HAL_SPI_ERROR_FLAG              ((uint32_t)0x00000020U)   /*!< Flag: RXNE,TXE, BSY  */
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup SPI_Mode SPI Mode
00180   * @{
00181   */
00182 #define SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)
00183 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup SPI_Direction SPI Direction Mode
00189   * @{
00190   */
00191 #define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000U)
00192 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00193 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup SPI_Data_Size SPI Data Size
00199   * @{
00200   */
00201 #define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000U)
00202 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00208   * @{
00209   */
00210 #define SPI_POLARITY_LOW                ((uint32_t)0x00000000U)
00211 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00217   * @{
00218   */
00219 #define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)
00220 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
00226   * @{
00227   */
00228 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00229 #define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)
00230 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000U)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00236   * @{
00237   */
00238 #define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000U)
00239 #define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008U)
00240 #define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010U)
00241 #define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018U)
00242 #define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020U)
00243 #define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028U)
00244 #define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030U)
00245 #define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038U)
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
00251   * @{
00252   */
00253 #define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000U)
00254 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup SPI_TI_mode SPI TI Mode
00260   * @{
00261   */
00262 #define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000U)
00263 #define SPI_TIMODE_ENABLE              SPI_CR2_FRF
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00269   * @{
00270   */
00271 #define SPI_CRCCALCULATION_DISABLE     ((uint32_t)0x00000000U)
00272 #define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00278   * @{
00279   */
00280 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00281 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00282 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup SPI_Flags_definition SPI Flags Definition
00288   * @{
00289   */
00290 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
00291 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
00292 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
00293 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
00294 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
00295 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
00296 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
00297 /**
00298   * @}
00299   */
00300
00301 /**
00302   * @}
00303   */
00304
00305 /* Exported macro ------------------------------------------------------------*/
00306 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00307   * @{
00308   */
00309
00310 /** @brief  Reset SPI handle state.
00311   * @param  __HANDLE__: specifies the SPI Handle.
00312   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00313   * @retval None
00314   */
00315 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00316
00317 /** @brief  Enable or disable the specified SPI interrupts.
00318   * @param  __HANDLE__: specifies the SPI Handle.
00319   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00320   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00321   *         This parameter can be one of the following values:
00322   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00323   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00324   *            @arg SPI_IT_ERR: Error interrupt enable
00325   * @retval None
00326   */
00327 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00328 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
00329
00330 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00331   * @param  __HANDLE__: specifies the SPI Handle.
00332   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00333   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
00334   *          This parameter can be one of the following values:
00335   *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00336   *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00337   *             @arg SPI_IT_ERR: Error interrupt enable
00338   * @retval The new state of __IT__ (TRUE or FALSE).
00339   */
00340 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00341
00342 /** @brief  Check whether the specified SPI flag is set or not.
00343   * @param  __HANDLE__: specifies the SPI Handle.
00344   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00345   * @param  __FLAG__: specifies the flag to check.
00346   *         This parameter can be one of the following values:
00347   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00348   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00349   *            @arg SPI_FLAG_CRCERR: CRC error flag
00350   *            @arg SPI_FLAG_MODF: Mode fault flag
00351   *            @arg SPI_FLAG_OVR: Overrun flag
00352   *            @arg SPI_FLAG_BSY: Busy flag
00353   *            @arg SPI_FLAG_FRE: Frame format error flag
00354   * @retval The new state of __FLAG__ (TRUE or FALSE).
00355   */
00356 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00357
00358 /** @brief  Clear the SPI CRCERR pending flag.
00359   * @param  __HANDLE__: specifies the SPI Handle.
00360   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00361   * @retval None
00362   */
00363 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00364
00365 /** @brief  Clear the SPI MODF pending flag.
00366   * @param  __HANDLE__: specifies the SPI Handle.
00367   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00368   * @retval None
00369   */
00370 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \
00371   do{                                              \
00372     __IO uint32_t tmpreg = 0x00U;                  \
00373     tmpreg = (__HANDLE__)->Instance->SR;           \
00374     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
00375     UNUSED(tmpreg);                                \
00376   } while(0)
00377
00378 /** @brief  Clear the SPI OVR pending flag.
00379   * @param  __HANDLE__: specifies the SPI Handle.
00380   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00381   * @retval None
00382   */
00383 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
00384   do{                                              \
00385     __IO uint32_t tmpreg = 0x00U;                  \
00386     tmpreg = (__HANDLE__)->Instance->DR;           \
00387     tmpreg = (__HANDLE__)->Instance->SR;           \
00388     UNUSED(tmpreg);                                \
00389   } while(0)
00390
00391 /** @brief  Clear the SPI FRE pending flag.
00392   * @param  __HANDLE__: specifies the SPI Handle.
00393   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00394   * @retval None
00395   */
00396 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
00397   do{                                              \
00398   __IO uint32_t tmpreg = 0x00U;                    \
00399   tmpreg = (__HANDLE__)->Instance->SR;             \
00400   UNUSED(tmpreg);                                  \
00401   }while(0)
00402
00403 /** @brief  Enable the SPI peripheral.
00404   * @param  __HANDLE__: specifies the SPI Handle.
00405   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00406   * @retval None
00407   */
00408 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
00409
00410 /** @brief  Disable the SPI peripheral.
00411   * @param  __HANDLE__: specifies the SPI Handle.
00412   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00413   * @retval None
00414   */
00415 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
00416 /**
00417   * @}
00418   */
00419
00420 /* Exported functions --------------------------------------------------------*/
00421 /** @addtogroup SPI_Exported_Functions
00422   * @{
00423   */
00424
00425 /** @addtogroup SPI_Exported_Functions_Group1
00426   * @{
00427   */
00428 /* Initialization/de-initialization functions  **********************************/
00429 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00430 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
00431 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00432 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00433 /**
00434   * @}
00435   */
00436
00437 /** @addtogroup SPI_Exported_Functions_Group2
00438   * @{
00439   */
00440 /* I/O operation functions  *****************************************************/
00441 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00442 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00443 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00444 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00445 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00446 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00447 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00448 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00449 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00450 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00451 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00452 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00453
00454 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00455 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00456 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00457 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00458 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00459 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00460 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00461 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00462 /**
00463   * @}
00464   */
00465
00466 /** @addtogroup SPI_Exported_Functions_Group3
00467   * @{
00468   */
00469 /* Peripheral State and Error functions ***************************************/
00470 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00471 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00472 /**
00473   * @}
00474   */
00475
00476 /**
00477   * @}
00478   */
00479
00480 /* Private types -------------------------------------------------------------*/
00481 /* Private variables ---------------------------------------------------------*/
00482 /* Private constants ---------------------------------------------------------*/
00483
00484 /* Private macros ------------------------------------------------------------*/
00485 /** @defgroup SPI_Private_Macros SPI Private Macros
00486   * @{
00487   */
00488
00489 /** @brief  Set the SPI transmit-only mode.
00490   * @param  __HANDLE__: specifies the SPI Handle.
00491   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00492   * @retval None
00493   */
00494 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
00495
00496 /** @brief  Set the SPI receive-only mode.
00497   * @param  __HANDLE__: specifies the SPI Handle.
00498   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00499   * @retval None
00500   */
00501 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
00502
00503 /** @brief  Reset the CRC calculation of the SPI.
00504   * @param  __HANDLE__: specifies the SPI Handle.
00505   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00506   * @retval None
00507   */
00508 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
00509                                      (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
00510
00511 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
00512                            ((MODE) == SPI_MODE_MASTER))
00513
00514 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
00515                                 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
00516                                 ((MODE) == SPI_DIRECTION_1LINE))
00517
00518 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
00519
00520 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
00521                                                 ((MODE) == SPI_DIRECTION_1LINE))
00522
00523 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
00524                                    ((DATASIZE) == SPI_DATASIZE_8BIT))
00525
00526 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
00527                            ((CPOL) == SPI_POLARITY_HIGH))
00528
00529 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
00530                            ((CPHA) == SPI_PHASE_2EDGE))
00531
00532 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
00533                          ((NSS) == SPI_NSS_HARD_INPUT) || \
00534                          ((NSS) == SPI_NSS_HARD_OUTPUT))
00535
00536 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
00537                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
00538                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
00539                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
00540                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
00541                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
00542                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00543                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00544
00545 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00546                                ((BIT) == SPI_FIRSTBIT_LSB))
00547
00548 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
00549                              ((MODE) == SPI_TIMODE_ENABLE))
00550
00551 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
00552                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
00553
00554 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
00555
00556 /**
00557   * @}
00558   */
00559
00560 /* Private functions ---------------------------------------------------------*/
00561 /** @defgroup SPI_Private_Functions SPI Private Functions
00562   * @{
00563   */
00564
00565 /**
00566   * @}
00567   */
00568
00569 /**
00570   * @}
00571   */
00572
00573 /**
00574   * @}
00575   */
00576
00577 #ifdef __cplusplus
00578 }
00579 #endif
00580
00581 #endif /* __STM32F4xx_HAL_SPI_H */
00582
00583 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sram.c Source File

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stm32f4xx_hal_sram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   SRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SRAM memories
00009   *          mounted as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                           ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SRAM memories. It uses the FMC layer functions to interface
00018     with SRAM devices.
00019     The following sequence should be followed to configure the FMC/FSMC to interface
00020     with SRAM/PSRAM memories:
00021
00022    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00023           SRAM_HandleTypeDef  hsram; and:
00024
00025        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SRAM device
00030
00031        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00032             base register instance for NOR or SRAM extended mode
00033
00034    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00035        mode timings; for example:
00036           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00037       and fill its fields with the allowed values of the structure member.
00038
00039    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00040        performs the following sequence:
00041
00042        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00043        (##) Control register configuration using the FMC NORSRAM interface function
00044             FMC_NORSRAM_Init()
00045        (##) Timing register configuration using the FMC NORSRAM interface function
00046             FMC_NORSRAM_Timing_Init()
00047        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
00048             FMC_NORSRAM_Extended_Timing_Init()
00049        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
00050
00051    (#) At this stage you can perform read/write accesses from/to the memory connected
00052        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00053        following APIs:
00054        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00055        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00056
00057    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00058        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00059
00060    (#) You can continuously monitor the SRAM device HAL state by calling the function
00061        HAL_SRAM_GetState()
00062
00063   @endverbatim
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00068   *
00069   * Redistribution and use in source and binary forms, with or without modification,
00070   * are permitted provided that the following conditions are met:
00071   *   1. Redistributions of source code must retain the above copyright notice,
00072   *      this list of conditions and the following disclaimer.
00073   *   2. Redistributions in binary form must reproduce the above copyright notice,
00074   *      this list of conditions and the following disclaimer in the documentation
00075   *      and/or other materials provided with the distribution.
00076   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00077   *      may be used to endorse or promote products derived from this software
00078   *      without specific prior written permission.
00079   *
00080   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00081   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00082   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00083   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00084   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00085   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00086   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00087   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00088   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00089   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00090   *
00091   ******************************************************************************
00092   */
00093
00094 /* Includes ------------------------------------------------------------------*/
00095 #include "stm32f4xx_hal.h"
00096
00097 /** @addtogroup STM32F4xx_HAL_Driver
00098   * @{
00099   */
00100
00101 /** @defgroup SRAM SRAM
00102   * @brief SRAM driver modules
00103   * @{
00104   */
00105 #ifdef HAL_SRAM_MODULE_ENABLED
00106
00107 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00108     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00109     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00110
00111 /* Private typedef -----------------------------------------------------------*/
00112 /* Private define ------------------------------------------------------------*/
00113 /* Private macro -------------------------------------------------------------*/
00114 /* Private variables ---------------------------------------------------------*/
00115 /* Private functions ---------------------------------------------------------*/
00116
00117 /* Exported functions --------------------------------------------------------*/
00118 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00119   * @{
00120   */
00121 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00122   * @brief    Initialization and Configuration functions
00123   *
00124   @verbatim
00125   ==============================================================================
00126            ##### SRAM Initialization and de_initialization functions #####
00127   ==============================================================================
00128     [..]  This section provides functions allowing to initialize/de-initialize
00129           the SRAM memory
00130
00131 @endverbatim
00132   * @{
00133   */
00134
00135 /**
00136   * @brief  Performs the SRAM device initialization sequence
00137   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00138   *                the configuration information for SRAM module.
00139   * @param  Timing: Pointer to SRAM control timing structure
00140   * @param  ExtTiming: Pointer to SRAM extended mode timing structure
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00144 {
00145   /* Check the SRAM handle parameter */
00146   if(hsram == NULL)
00147   {
00148      return HAL_ERROR;
00149   }
00150
00151   if(hsram->State == HAL_SRAM_STATE_RESET)
00152   {
00153     /* Allocate lock resource and initialize it */
00154     hsram->Lock = HAL_UNLOCKED;
00155     /* Initialize the low level hardware (MSP) */
00156     HAL_SRAM_MspInit(hsram);
00157   }
00158
00159   /* Initialize SRAM control Interface */
00160   FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00161
00162   /* Initialize SRAM timing Interface */
00163   FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00164
00165   /* Initialize SRAM extended mode timing Interface */
00166   FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
00167
00168   /* Enable the NORSRAM device */
00169   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00170
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  Performs the SRAM device De-initialization sequence.
00176   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00177   *                the configuration information for SRAM module.
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00181 {
00182   /* De-Initialize the low level hardware (MSP) */
00183   HAL_SRAM_MspDeInit(hsram);
00184
00185   /* Configure the SRAM registers with their reset values */
00186   FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00187
00188   hsram->State = HAL_SRAM_STATE_RESET;
00189
00190   /* Release Lock */
00191   __HAL_UNLOCK(hsram);
00192
00193   return HAL_OK;
00194 }
00195
00196 /**
00197   * @brief  SRAM MSP Init.
00198   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00199   *                the configuration information for SRAM module.
00200   * @retval None
00201   */
00202 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00203 {
00204   /* Prevent unused argument(s) compilation warning */
00205   UNUSED(hsram);
00206     /* NOTE : This function Should not be modified, when the callback is needed,
00207             the HAL_SRAM_MspInit could be implemented in the user file
00208    */
00209 }
00210
00211 /**
00212   * @brief  SRAM MSP DeInit.
00213   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00214   *                the configuration information for SRAM module.
00215   * @retval None
00216   */
00217 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00218 {
00219   /* Prevent unused argument(s) compilation warning */
00220   UNUSED(hsram);
00221   /* NOTE : This function Should not be modified, when the callback is needed,
00222             the HAL_SRAM_MspDeInit could be implemented in the user file
00223    */
00224 }
00225
00226 /**
00227   * @brief  DMA transfer complete callback.
00228   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00229   *                the configuration information for SRAM module.
00230   * @retval None
00231   */
00232 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00233 {
00234   /* Prevent unused argument(s) compilation warning */
00235   UNUSED(hdma);
00236   /* NOTE : This function Should not be modified, when the callback is needed,
00237             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00238    */
00239 }
00240
00241 /**
00242   * @brief  DMA transfer complete error callback.
00243   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00244   *                the configuration information for SRAM module.
00245   * @retval None
00246   */
00247 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00248 {
00249   /* Prevent unused argument(s) compilation warning */
00250   UNUSED(hdma);
00251     /* NOTE : This function Should not be modified, when the callback is needed,
00252             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00253    */
00254 }
00255
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
00261   * @brief    Input Output and memory control functions
00262   *
00263   @verbatim
00264   ==============================================================================
00265                   ##### SRAM Input and Output functions #####
00266   ==============================================================================
00267   [..]
00268     This section provides functions allowing to use and control the SRAM memory
00269
00270 @endverbatim
00271   * @{
00272   */
00273
00274 /**
00275   * @brief  Reads 8-bit buffer from SRAM memory.
00276   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00277   *                the configuration information for SRAM module.
00278   * @param  pAddress: Pointer to read start address
00279   * @param  pDstBuffer: Pointer to destination buffer
00280   * @param  BufferSize: Size of the buffer to read from memory
00281   * @retval HAL status
00282   */
00283 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00284 {
00285   __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
00286
00287   /* Process Locked */
00288   __HAL_LOCK(hsram);
00289
00290   /* Update the SRAM controller state */
00291   hsram->State = HAL_SRAM_STATE_BUSY;
00292
00293   /* Read data from memory */
00294   for(; BufferSize != 0U; BufferSize--)
00295   {
00296     *pDstBuffer = *(__IO uint8_t *)pSramAddress;
00297     pDstBuffer++;
00298     pSramAddress++;
00299   }
00300
00301   /* Update the SRAM controller state */
00302   hsram->State = HAL_SRAM_STATE_READY;
00303
00304   /* Process unlocked */
00305   __HAL_UNLOCK(hsram);
00306
00307   return HAL_OK;
00308 }
00309
00310 /**
00311   * @brief  Writes 8-bit buffer to SRAM memory.
00312   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00313   *                the configuration information for SRAM module.
00314   * @param  pAddress: Pointer to write start address
00315   * @param  pSrcBuffer: Pointer to source buffer to write
00316   * @param  BufferSize: Size of the buffer to write to memory
00317   * @retval HAL status
00318   */
00319 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00320 {
00321   __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
00322
00323   /* Check the SRAM controller state */
00324   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00325   {
00326     return  HAL_ERROR;
00327   }
00328
00329   /* Process Locked */
00330   __HAL_LOCK(hsram);
00331
00332   /* Update the SRAM controller state */
00333   hsram->State = HAL_SRAM_STATE_BUSY;
00334
00335   /* Write data to memory */
00336   for(; BufferSize != 0U; BufferSize--)
00337   {
00338     *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
00339     pSrcBuffer++;
00340     pSramAddress++;
00341   }
00342
00343   /* Update the SRAM controller state */
00344   hsram->State = HAL_SRAM_STATE_READY;
00345
00346   /* Process unlocked */
00347   __HAL_UNLOCK(hsram);
00348
00349   return HAL_OK;
00350 }
00351
00352 /**
00353   * @brief  Reads 16-bit buffer from SRAM memory.
00354   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00355   *                the configuration information for SRAM module.
00356   * @param  pAddress: Pointer to read start address
00357   * @param  pDstBuffer: Pointer to destination buffer
00358   * @param  BufferSize: Size of the buffer to read from memory
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00362 {
00363   __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
00364
00365   /* Process Locked */
00366   __HAL_LOCK(hsram);
00367
00368   /* Update the SRAM controller state */
00369   hsram->State = HAL_SRAM_STATE_BUSY;
00370
00371   /* Read data from memory */
00372   for(; BufferSize != 0U; BufferSize--)
00373   {
00374     *pDstBuffer = *(__IO uint16_t *)pSramAddress;
00375     pDstBuffer++;
00376     pSramAddress++;
00377   }
00378
00379   /* Update the SRAM controller state */
00380   hsram->State = HAL_SRAM_STATE_READY;
00381
00382   /* Process unlocked */
00383   __HAL_UNLOCK(hsram);
00384
00385   return HAL_OK;
00386 }
00387
00388 /**
00389   * @brief  Writes 16-bit buffer to SRAM memory.
00390   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00391   *                the configuration information for SRAM module.
00392   * @param  pAddress: Pointer to write start address
00393   * @param  pSrcBuffer: Pointer to source buffer to write
00394   * @param  BufferSize: Size of the buffer to write to memory
00395   * @retval HAL status
00396   */
00397 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00398 {
00399   __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
00400
00401   /* Check the SRAM controller state */
00402   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00403   {
00404     return  HAL_ERROR;
00405   }
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hsram);
00409
00410   /* Update the SRAM controller state */
00411   hsram->State = HAL_SRAM_STATE_BUSY;
00412
00413   /* Write data to memory */
00414   for(; BufferSize != 0U; BufferSize--)
00415   {
00416     *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
00417     pSrcBuffer++;
00418     pSramAddress++;
00419   }
00420
00421   /* Update the SRAM controller state */
00422   hsram->State = HAL_SRAM_STATE_READY;
00423
00424   /* Process unlocked */
00425   __HAL_UNLOCK(hsram);
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief  Reads 32-bit buffer from SRAM memory.
00432   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00433   *                the configuration information for SRAM module.
00434   * @param  pAddress: Pointer to read start address
00435   * @param  pDstBuffer: Pointer to destination buffer
00436   * @param  BufferSize: Size of the buffer to read from memory
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00440 {
00441   /* Process Locked */
00442   __HAL_LOCK(hsram);
00443
00444   /* Update the SRAM controller state */
00445   hsram->State = HAL_SRAM_STATE_BUSY;
00446
00447   /* Read data from memory */
00448   for(; BufferSize != 0U; BufferSize--)
00449   {
00450     *pDstBuffer = *(__IO uint32_t *)pAddress;
00451     pDstBuffer++;
00452     pAddress++;
00453   }
00454
00455   /* Update the SRAM controller state */
00456   hsram->State = HAL_SRAM_STATE_READY;
00457
00458   /* Process unlocked */
00459   __HAL_UNLOCK(hsram);
00460
00461   return HAL_OK;
00462 }
00463
00464 /**
00465   * @brief  Writes 32-bit buffer to SRAM memory.
00466   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00467   *                the configuration information for SRAM module.
00468   * @param  pAddress: Pointer to write start address
00469   * @param  pSrcBuffer: Pointer to source buffer to write
00470   * @param  BufferSize: Size of the buffer to write to memory
00471   * @retval HAL status
00472   */
00473 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00474 {
00475   /* Check the SRAM controller state */
00476   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00477   {
00478     return  HAL_ERROR;
00479   }
00480
00481   /* Process Locked */
00482   __HAL_LOCK(hsram);
00483
00484   /* Update the SRAM controller state */
00485   hsram->State = HAL_SRAM_STATE_BUSY;
00486
00487   /* Write data to memory */
00488   for(; BufferSize != 0U; BufferSize--)
00489   {
00490     *(__IO uint32_t *)pAddress = *pSrcBuffer;
00491     pSrcBuffer++;
00492     pAddress++;
00493   }
00494
00495   /* Update the SRAM controller state */
00496   hsram->State = HAL_SRAM_STATE_READY;
00497
00498   /* Process unlocked */
00499   __HAL_UNLOCK(hsram);
00500
00501   return HAL_OK;
00502 }
00503
00504 /**
00505   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
00506   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00507   *                the configuration information for SRAM module.
00508   * @param  pAddress: Pointer to read start address
00509   * @param  pDstBuffer: Pointer to destination buffer
00510   * @param  BufferSize: Size of the buffer to read from memory
00511   * @retval HAL status
00512   */
00513 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00514 {
00515   /* Process Locked */
00516   __HAL_LOCK(hsram);
00517
00518   /* Update the SRAM controller state */
00519   hsram->State = HAL_SRAM_STATE_BUSY;
00520
00521   /* Configure DMA user callbacks */
00522   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00523   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00524
00525   /* Enable the DMA Stream */
00526   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00527
00528   /* Update the SRAM controller state */
00529   hsram->State = HAL_SRAM_STATE_READY;
00530
00531   /* Process unlocked */
00532   __HAL_UNLOCK(hsram);
00533
00534   return HAL_OK;
00535 }
00536
00537 /**
00538   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
00539   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00540   *                the configuration information for SRAM module.
00541   * @param  pAddress: Pointer to write start address
00542   * @param  pSrcBuffer: Pointer to source buffer to write
00543   * @param  BufferSize: Size of the buffer to write to memory
00544   * @retval HAL status
00545   */
00546 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00547 {
00548   /* Check the SRAM controller state */
00549   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00550   {
00551     return  HAL_ERROR;
00552   }
00553
00554   /* Process Locked */
00555   __HAL_LOCK(hsram);
00556
00557   /* Update the SRAM controller state */
00558   hsram->State = HAL_SRAM_STATE_BUSY;
00559
00560   /* Configure DMA user callbacks */
00561   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00562   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00563
00564   /* Enable the DMA Stream */
00565   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00566
00567   /* Update the SRAM controller state */
00568   hsram->State = HAL_SRAM_STATE_READY;
00569
00570   /* Process unlocked */
00571   __HAL_UNLOCK(hsram);
00572
00573   return HAL_OK;
00574 }
00575
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00581  *  @brief   management functions
00582  *
00583 @verbatim
00584   ==============================================================================
00585                         ##### SRAM Control functions #####
00586   ==============================================================================
00587   [..]
00588     This subsection provides a set of functions allowing to control dynamically
00589     the SRAM interface.
00590
00591 @endverbatim
00592   * @{
00593   */
00594
00595 /**
00596   * @brief  Enables dynamically SRAM write operation.
00597   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00598   *                the configuration information for SRAM module.
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00602 {
00603   /* Process Locked */
00604   __HAL_LOCK(hsram);
00605
00606   /* Enable write operation */
00607   FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00608
00609   /* Update the SRAM controller state */
00610   hsram->State = HAL_SRAM_STATE_READY;
00611
00612   /* Process unlocked */
00613   __HAL_UNLOCK(hsram);
00614
00615   return HAL_OK;
00616 }
00617
00618 /**
00619   * @brief  Disables dynamically SRAM write operation.
00620   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00621   *                the configuration information for SRAM module.
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00625 {
00626   /* Process Locked */
00627   __HAL_LOCK(hsram);
00628
00629   /* Update the SRAM controller state */
00630   hsram->State = HAL_SRAM_STATE_BUSY;
00631
00632   /* Disable write operation */
00633   FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00634
00635   /* Update the SRAM controller state */
00636   hsram->State = HAL_SRAM_STATE_PROTECTED;
00637
00638   /* Process unlocked */
00639   __HAL_UNLOCK(hsram);
00640
00641   return HAL_OK;
00642 }
00643
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup SRAM_Exported_Functions_Group4 State functions
00649  *  @brief   Peripheral State functions
00650  *
00651 @verbatim
00652   ==============================================================================
00653                       ##### SRAM State functions #####
00654   ==============================================================================
00655   [..]
00656     This subsection permits to get in run-time the status of the SRAM controller
00657     and the data flow.
00658
00659 @endverbatim
00660   * @{
00661   */
00662
00663 /**
00664   * @brief  Returns the SRAM controller state
00665   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00666   *                the configuration information for SRAM module.
00667   * @retval HAL state
00668   */
00669 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
00670 {
00671   return hsram->State;
00672 }
00673 /**
00674   * @}
00675   */
00676
00677 /**
00678   * @}
00679   */
00680 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00681           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00682 #endif /* HAL_SRAM_MODULE_ENABLED */
00683 /**
00684   * @}
00685   */
00686
00687 /**
00688   * @}
00689   */
00690
00691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_sram.h Source File

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stm32f4xx_hal_sram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of SRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_SRAM_H
00040 #define __STM32F4xx_HAL_SRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
00048   #include "stm32f4xx_ll_fsmc.h"
00049 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
00050
00051 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
00052  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00053   #include "stm32f4xx_ll_fmc.h"
00054 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00055
00056
00057 /** @addtogroup STM32F4xx_HAL_Driver
00058   * @{
00059   */
00060
00061 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
00062     defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
00063     defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
00064
00065 /** @addtogroup SRAM
00066   * @{
00067   */
00068
00069 /* Exported typedef ----------------------------------------------------------*/
00070
00071 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00072   * @{
00073   */
00074 /**
00075   * @brief  HAL SRAM State structures definition
00076   */
00077 typedef enum
00078 {
00079   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
00080   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
00081   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
00082   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
00083   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
00084
00085 }HAL_SRAM_StateTypeDef;
00086
00087 /**
00088   * @brief  SRAM handle Structure definition
00089   */
00090 typedef struct
00091 {
00092   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00093
00094   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00095
00096   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00097
00098   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00099
00100   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00101
00102   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
00103
00104 }SRAM_HandleTypeDef;
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported constants --------------------------------------------------------*/
00111 /* Exported macro ------------------------------------------------------------*/
00112
00113 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00114   * @{
00115   */
00116 /** @brief Reset SRAM handle state
00117   * @param  __HANDLE__: SRAM handle
00118   * @retval None
00119   */
00120 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00121
00122 /**
00123   * @}
00124   */
00125 /* Exported functions --------------------------------------------------------*/
00126
00127 /** @addtogroup SRAM_Exported_Functions
00128  *  @{
00129  */
00130
00131 /** @addtogroup SRAM_Exported_Functions_Group1
00132  *  @{
00133  */
00134 /* Initialization/de-initialization functions  **********************************/
00135 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00136 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00137 void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00138 void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00139
00140 void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00141 void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00142 /**
00143   * @}
00144   */
00145
00146 /** @addtogroup SRAM_Exported_Functions_Group2
00147  *  @{
00148  */
00149 /* I/O operation functions  *****************************************************/
00150 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00151 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00152 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00153 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00154 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00155 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00156 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00157 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00158 /**
00159   * @}
00160   */
00161
00162 /** @addtogroup SRAM_Exported_Functions_Group3
00163  *  @{
00164  */
00165 /* SRAM Control functions  ******************************************************/
00166 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00167 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00168 /**
00169   * @}
00170   */
00171
00172 /** @addtogroup SRAM_Exported_Functions_Group4
00173  *  @{
00174  */
00175 /* SRAM State functions *********************************************************/
00176 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /* Private types -------------------------------------------------------------*/
00186 /* Private variables ---------------------------------------------------------*/
00187 /* Private constants ---------------------------------------------------------*/
00188 /* Private macros ------------------------------------------------------------*/
00189 /* Private functions ---------------------------------------------------------*/
00190 /**
00191   * @}
00192   */
00193
00194 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
00195           STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
00196 /**
00197   * @}
00198   */
00199 #ifdef __cplusplus
00200 }
00201 #endif
00202
00203 #endif /* __STM32F4xx_HAL_SRAM_H */
00204
00205 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim.c Source File

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stm32f4xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer (TIM) peripheral:
00010   *           + Time Base Initialization
00011   *           + Time Base Start
00012   *           + Time Base Start Interruption
00013   *           + Time Base Start DMA
00014   *           + Time Output Compare/PWM Initialization
00015   *           + Time Output Compare/PWM Channel Configuration
00016   *           + Time Output Compare/PWM  Start
00017   *           + Time Output Compare/PWM  Start Interruption
00018   *           + Time Output Compare/PWM Start DMA
00019   *           + Time Input Capture Initialization
00020   *           + Time Input Capture Channel Configuration
00021   *           + Time Input Capture Start
00022   *           + Time Input Capture Start Interruption
00023   *           + Time Input Capture Start DMA
00024   *           + Time One Pulse Initialization
00025   *           + Time One Pulse Channel Configuration
00026   *           + Time One Pulse Start
00027   *           + Time Encoder Interface Initialization
00028   *           + Time Encoder Interface Start
00029   *           + Time Encoder Interface Start Interruption
00030   *           + Time Encoder Interface Start DMA
00031   *           + Commutation Event configuration with Interruption and DMA
00032   *           + Time OCRef clear configuration
00033   *           + Time External Clock configuration
00034   @verbatim
00035   ==============================================================================
00036                       ##### TIMER Generic features #####
00037   ==============================================================================
00038   [..] The Timer features include:
00039        (#) 16-bit up, down, up/down auto-reload counter.
00040        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00041            counter clock frequency either by any factor between 1 and 65536.
00042        (#) Up to 4 independent channels for:
00043            (++) Input Capture
00044            (++) Output Compare
00045            (++) PWM generation (Edge and Center-aligned Mode)
00046            (++) One-pulse mode output
00047
00048                         ##### How to use this driver #####
00049   ==============================================================================
00050     [..]
00051      (#) Initialize the TIM low level resources by implementing the following functions
00052          depending from feature used :
00053            (++) Time Base : HAL_TIM_Base_MspInit()
00054            (++) Input Capture : HAL_TIM_IC_MspInit()
00055            (++) Output Compare : HAL_TIM_OC_MspInit()
00056            (++) PWM generation : HAL_TIM_PWM_MspInit()
00057            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00058            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00059
00060      (#) Initialize the TIM low level resources :
00061         (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
00062         (##) TIM pins configuration
00063             (+++) Enable the clock for the TIM GPIOs using the following function:
00064                  __GPIOx_CLK_ENABLE();
00065             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00066
00067      (#) The external Clock can be configured, if needed (the default clock is the
00068          internal clock from the APBx), using the following function:
00069          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00070          any start function.
00071
00072      (#) Configure the TIM in the desired functioning mode using one of the
00073          initialization function of this driver:
00074          (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00075          (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00076               Output Compare signal.
00077          (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00078               PWM signal.
00079          (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00080               external signal.
00081          (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00082               in One Pulse Mode.
00083          (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00084
00085      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00086            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00087            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00088            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00089            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00090            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00091            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00092
00093      (#) The DMA Burst is managed with the two following functions:
00094          HAL_TIM_DMABurst_WriteStart()
00095          HAL_TIM_DMABurst_ReadStart()
00096
00097   @endverbatim
00098   ******************************************************************************
00099   * @attention
00100   *
00101   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00102   *
00103   * Redistribution and use in source and binary forms, with or without modification,
00104   * are permitted provided that the following conditions are met:
00105   *   1. Redistributions of source code must retain the above copyright notice,
00106   *      this list of conditions and the following disclaimer.
00107   *   2. Redistributions in binary form must reproduce the above copyright notice,
00108   *      this list of conditions and the following disclaimer in the documentation
00109   *      and/or other materials provided with the distribution.
00110   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00111   *      may be used to endorse or promote products derived from this software
00112   *      without specific prior written permission.
00113   *
00114   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00115   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00116   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00117   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00118   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00119   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00120   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00121   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00122   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00123   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00124   *
00125   ******************************************************************************
00126   */
00127
00128 /* Includes ------------------------------------------------------------------*/
00129 #include "stm32f4xx_hal.h"
00130
00131 /** @addtogroup STM32F4xx_HAL_Driver
00132   * @{
00133   */
00134
00135 /** @defgroup TIM TIM
00136   * @brief TIM HAL module driver
00137   * @{
00138   */
00139
00140 #ifdef HAL_TIM_MODULE_ENABLED
00141
00142 /* Private typedef -----------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /* Private macro -------------------------------------------------------------*/
00145 /* Private variables ---------------------------------------------------------*/
00146 /** @addtogroup TIM_Private_Functions
00147   * @{
00148   */
00149 /* Private function prototypes -----------------------------------------------*/
00150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00153
00154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00156                        uint32_t TIM_ICFilter);
00157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00159                        uint32_t TIM_ICFilter);
00160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00161                        uint32_t TIM_ICFilter);
00162
00163 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
00164                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
00165
00166 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
00167 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00168 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00169 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00170                                      TIM_SlaveConfigTypeDef * sSlaveConfig);
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported functions --------------------------------------------------------*/
00176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00177   * @{
00178   */
00179
00180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
00181  *  @brief    Time Base functions
00182  *
00183 @verbatim
00184   ==============================================================================
00185               ##### Time Base functions #####
00186   ==============================================================================
00187   [..]
00188     This section provides functions allowing to:
00189     (+) Initialize and configure the TIM base.
00190     (+) De-initialize the TIM base.
00191     (+) Start the Time Base.
00192     (+) Stop the Time Base.
00193     (+) Start the Time Base and enable interrupt.
00194     (+) Stop the Time Base and disable interrupt.
00195     (+) Start the Time Base and enable DMA transfer.
00196     (+) Stop the Time Base and disable DMA transfer.
00197
00198 @endverbatim
00199   * @{
00200   */
00201 /**
00202   * @brief  Initializes the TIM Time base Unit according to the specified
00203   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00204   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00205   *                the configuration information for TIM module.
00206   * @retval HAL status
00207   */
00208 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00209 {
00210   /* Check the TIM handle allocation */
00211   if(htim == NULL)
00212   {
00213     return HAL_ERROR;
00214   }
00215
00216   /* Check the parameters */
00217   assert_param(IS_TIM_INSTANCE(htim->Instance));
00218   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00219   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00220
00221   if(htim->State == HAL_TIM_STATE_RESET)
00222   {
00223     /* Allocate lock resource and initialize it */
00224     htim->Lock = HAL_UNLOCKED;
00225     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00226     HAL_TIM_Base_MspInit(htim);
00227   }
00228
00229   /* Set the TIM state */
00230   htim->State= HAL_TIM_STATE_BUSY;
00231
00232   /* Set the Time Base configuration */
00233   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00234
00235   /* Initialize the TIM state*/
00236   htim->State= HAL_TIM_STATE_READY;
00237
00238   return HAL_OK;
00239 }
00240
00241 /**
00242   * @brief  DeInitializes the TIM Base peripheral
00243   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00244   *                the configuration information for TIM module.
00245   * @retval HAL status
00246   */
00247 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00248 {
00249   /* Check the parameters */
00250   assert_param(IS_TIM_INSTANCE(htim->Instance));
00251
00252   htim->State = HAL_TIM_STATE_BUSY;
00253
00254   /* Disable the TIM Peripheral Clock */
00255   __HAL_TIM_DISABLE(htim);
00256
00257   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00258   HAL_TIM_Base_MspDeInit(htim);
00259
00260   /* Change TIM state */
00261   htim->State = HAL_TIM_STATE_RESET;
00262
00263   /* Release Lock */
00264   __HAL_UNLOCK(htim);
00265
00266   return HAL_OK;
00267 }
00268
00269 /**
00270   * @brief  Initializes the TIM Base MSP.
00271   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00272   *                the configuration information for TIM module.
00273   * @retval None
00274   */
00275 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00276 {
00277   /* Prevent unused argument(s) compilation warning */
00278   UNUSED(htim);
00279   /* NOTE : This function Should not be modified, when the callback is needed,
00280             the HAL_TIM_Base_MspInit could be implemented in the user file
00281    */
00282 }
00283
00284 /**
00285   * @brief  DeInitializes TIM Base MSP.
00286   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00287   *                the configuration information for TIM module.
00288   * @retval None
00289   */
00290 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00291 {
00292   /* Prevent unused argument(s) compilation warning */
00293   UNUSED(htim);
00294   /* NOTE : This function Should not be modified, when the callback is needed,
00295             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00296    */
00297 }
00298
00299 /**
00300   * @brief  Starts the TIM Base generation.
00301   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00302   *                the configuration information for TIM module.
00303   * @retval HAL status
00304   */
00305 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00306 {
00307   /* Check the parameters */
00308   assert_param(IS_TIM_INSTANCE(htim->Instance));
00309
00310   /* Set the TIM state */
00311   htim->State= HAL_TIM_STATE_BUSY;
00312
00313   /* Enable the Peripheral */
00314   __HAL_TIM_ENABLE(htim);
00315
00316   /* Change the TIM state*/
00317   htim->State= HAL_TIM_STATE_READY;
00318
00319   /* Return function status */
00320   return HAL_OK;
00321 }
00322
00323 /**
00324   * @brief  Stops the TIM Base generation.
00325   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00326   *                the configuration information for TIM module.
00327   * @retval HAL status
00328   */
00329 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00330 {
00331   /* Check the parameters */
00332   assert_param(IS_TIM_INSTANCE(htim->Instance));
00333
00334   /* Set the TIM state */
00335   htim->State= HAL_TIM_STATE_BUSY;
00336
00337   /* Disable the Peripheral */
00338   __HAL_TIM_DISABLE(htim);
00339
00340   /* Change the TIM state*/
00341   htim->State= HAL_TIM_STATE_READY;
00342
00343   /* Return function status */
00344   return HAL_OK;
00345 }
00346
00347 /**
00348   * @brief  Starts the TIM Base generation in interrupt mode.
00349   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00350   *                the configuration information for TIM module.
00351   * @retval HAL status
00352   */
00353 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00354 {
00355   /* Check the parameters */
00356   assert_param(IS_TIM_INSTANCE(htim->Instance));
00357
00358   /* Enable the TIM Update interrupt */
00359   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00360
00361   /* Enable the Peripheral */
00362   __HAL_TIM_ENABLE(htim);
00363
00364   /* Return function status */
00365   return HAL_OK;
00366 }
00367
00368 /**
00369   * @brief  Stops the TIM Base generation in interrupt mode.
00370   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00371   *                the configuration information for TIM module.
00372   * @retval HAL status
00373   */
00374 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00375 {
00376   /* Check the parameters */
00377   assert_param(IS_TIM_INSTANCE(htim->Instance));
00378   /* Disable the TIM Update interrupt */
00379   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00380
00381   /* Disable the Peripheral */
00382   __HAL_TIM_DISABLE(htim);
00383
00384   /* Return function status */
00385   return HAL_OK;
00386 }
00387
00388 /**
00389   * @brief  Starts the TIM Base generation in DMA mode.
00390   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00391   *                the configuration information for TIM module.
00392   * @param  pData: The source Buffer address.
00393   * @param  Length: The length of data to be transferred from memory to peripheral.
00394   * @retval HAL status
00395   */
00396 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00397 {
00398   /* Check the parameters */
00399   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00400
00401   if((htim->State == HAL_TIM_STATE_BUSY))
00402   {
00403      return HAL_BUSY;
00404   }
00405   else if((htim->State == HAL_TIM_STATE_READY))
00406   {
00407     if((pData == 0U) && (Length > 0U))
00408     {
00409       return HAL_ERROR;
00410     }
00411     else
00412     {
00413       htim->State = HAL_TIM_STATE_BUSY;
00414     }
00415   }
00416   /* Set the DMA Period elapsed callback */
00417   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00418
00419   /* Set the DMA error callback */
00420   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00421
00422   /* Enable the DMA Stream */
00423   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
00424
00425   /* Enable the TIM Update DMA request */
00426   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00427
00428   /* Enable the Peripheral */
00429   __HAL_TIM_ENABLE(htim);
00430
00431   /* Return function status */
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @brief  Stops the TIM Base generation in DMA mode.
00437   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00438   *                the configuration information for TIM module.
00439   * @retval HAL status
00440   */
00441 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00442 {
00443   /* Check the parameters */
00444   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00445
00446   /* Disable the TIM Update DMA request */
00447   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00448
00449   /* Disable the Peripheral */
00450   __HAL_TIM_DISABLE(htim);
00451
00452   /* Change the htim state */
00453   htim->State = HAL_TIM_STATE_READY;
00454
00455   /* Return function status */
00456   return HAL_OK;
00457 }
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
00463  *  @brief    Time Output Compare functions
00464  *
00465 @verbatim
00466   ==============================================================================
00467                   ##### Time Output Compare functions #####
00468   ==============================================================================
00469   [..]
00470     This section provides functions allowing to:
00471     (+) Initialize and configure the TIM Output Compare.
00472     (+) De-initialize the TIM Output Compare.
00473     (+) Start the Time Output Compare.
00474     (+) Stop the Time Output Compare.
00475     (+) Start the Time Output Compare and enable interrupt.
00476     (+) Stop the Time Output Compare and disable interrupt.
00477     (+) Start the Time Output Compare and enable DMA transfer.
00478     (+) Stop the Time Output Compare and disable DMA transfer.
00479
00480 @endverbatim
00481   * @{
00482   */
00483 /**
00484   * @brief  Initializes the TIM Output Compare according to the specified
00485   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00486   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00487   *                the configuration information for TIM module.
00488   * @retval HAL status
00489   */
00490 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
00491 {
00492   /* Check the TIM handle allocation */
00493   if(htim == NULL)
00494   {
00495     return HAL_ERROR;
00496   }
00497
00498   /* Check the parameters */
00499   assert_param(IS_TIM_INSTANCE(htim->Instance));
00500   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00501   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00502
00503   if(htim->State == HAL_TIM_STATE_RESET)
00504   {
00505     /* Allocate lock resource and initialize it */
00506     htim->Lock = HAL_UNLOCKED;
00507     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00508     HAL_TIM_OC_MspInit(htim);
00509   }
00510
00511   /* Set the TIM state */
00512   htim->State= HAL_TIM_STATE_BUSY;
00513
00514   /* Init the base time for the Output Compare */
00515   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00516
00517   /* Initialize the TIM state*/
00518   htim->State= HAL_TIM_STATE_READY;
00519
00520   return HAL_OK;
00521 }
00522
00523 /**
00524   * @brief  DeInitializes the TIM peripheral
00525   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00526   *                the configuration information for TIM module.
00527   * @retval HAL status
00528   */
00529 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00530 {
00531   /* Check the parameters */
00532   assert_param(IS_TIM_INSTANCE(htim->Instance));
00533
00534    htim->State = HAL_TIM_STATE_BUSY;
00535
00536   /* Disable the TIM Peripheral Clock */
00537   __HAL_TIM_DISABLE(htim);
00538
00539   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00540   HAL_TIM_OC_MspDeInit(htim);
00541
00542   /* Change TIM state */
00543   htim->State = HAL_TIM_STATE_RESET;
00544
00545   /* Release Lock */
00546   __HAL_UNLOCK(htim);
00547
00548   return HAL_OK;
00549 }
00550
00551 /**
00552   * @brief  Initializes the TIM Output Compare MSP.
00553   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00554   *                the configuration information for TIM module.
00555   * @retval None
00556   */
00557 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00558 {
00559   /* Prevent unused argument(s) compilation warning */
00560   UNUSED(htim);
00561   /* NOTE : This function Should not be modified, when the callback is needed,
00562             the HAL_TIM_OC_MspInit could be implemented in the user file
00563    */
00564 }
00565
00566 /**
00567   * @brief  DeInitializes TIM Output Compare MSP.
00568   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00569   *                the configuration information for TIM module.
00570   * @retval None
00571   */
00572 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00573 {
00574   /* Prevent unused argument(s) compilation warning */
00575   UNUSED(htim);
00576   /* NOTE : This function Should not be modified, when the callback is needed,
00577             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00578    */
00579 }
00580
00581 /**
00582   * @brief  Starts the TIM Output Compare signal generation.
00583   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00584   *                the configuration information for TIM module.
00585   * @param  Channel: TIM Channel to be enabled.
00586   *          This parameter can be one of the following values:
00587   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00588   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00589   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00590   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00591   * @retval HAL status
00592   */
00593 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00594 {
00595   /* Check the parameters */
00596   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00597
00598   /* Enable the Output compare channel */
00599   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00600
00601   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00602   {
00603     /* Enable the main output */
00604     __HAL_TIM_MOE_ENABLE(htim);
00605   }
00606
00607   /* Enable the Peripheral */
00608   __HAL_TIM_ENABLE(htim);
00609
00610   /* Return function status */
00611   return HAL_OK;
00612 }
00613
00614 /**
00615   * @brief  Stops the TIM Output Compare signal generation.
00616   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00617   *                the configuration information for TIM module.
00618   * @param  Channel: TIM Channel to be disabled.
00619   *          This parameter can be one of the following values:
00620   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00621   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00622   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00623   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00624   * @retval HAL status
00625   */
00626 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00627 {
00628   /* Check the parameters */
00629   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00630
00631   /* Disable the Output compare channel */
00632   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00633
00634   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00635   {
00636     /* Disable the Main Output */
00637     __HAL_TIM_MOE_DISABLE(htim);
00638   }
00639
00640   /* Disable the Peripheral */
00641   __HAL_TIM_DISABLE(htim);
00642
00643   /* Return function status */
00644   return HAL_OK;
00645 }
00646
00647 /**
00648   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00649   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00650   *                the configuration information for TIM module.
00651   * @param  Channel: TIM Channel to be enabled.
00652   *          This parameter can be one of the following values:
00653   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00654   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00655   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00656   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00657   * @retval HAL status
00658   */
00659 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00660 {
00661   /* Check the parameters */
00662   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00663
00664   switch (Channel)
00665   {
00666     case TIM_CHANNEL_1:
00667     {
00668       /* Enable the TIM Capture/Compare 1 interrupt */
00669       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00670     }
00671     break;
00672
00673     case TIM_CHANNEL_2:
00674     {
00675       /* Enable the TIM Capture/Compare 2 interrupt */
00676       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00677     }
00678     break;
00679
00680     case TIM_CHANNEL_3:
00681     {
00682       /* Enable the TIM Capture/Compare 3 interrupt */
00683       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00684     }
00685     break;
00686
00687     case TIM_CHANNEL_4:
00688     {
00689       /* Enable the TIM Capture/Compare 4 interrupt */
00690       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00691     }
00692     break;
00693
00694     default:
00695     break;
00696   }
00697
00698   /* Enable the Output compare channel */
00699   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00700
00701   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00702   {
00703     /* Enable the main output */
00704     __HAL_TIM_MOE_ENABLE(htim);
00705   }
00706
00707   /* Enable the Peripheral */
00708   __HAL_TIM_ENABLE(htim);
00709
00710   /* Return function status */
00711   return HAL_OK;
00712 }
00713
00714 /**
00715   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00716   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00717   *                the configuration information for TIM module.
00718   * @param  Channel: TIM Channel to be disabled.
00719   *          This parameter can be one of the following values:
00720   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00721   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00722   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00723   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00724   * @retval HAL status
00725   */
00726 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00727 {
00728   /* Check the parameters */
00729   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00730
00731   switch (Channel)
00732   {
00733     case TIM_CHANNEL_1:
00734     {
00735       /* Disable the TIM Capture/Compare 1 interrupt */
00736       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00737     }
00738     break;
00739
00740     case TIM_CHANNEL_2:
00741     {
00742       /* Disable the TIM Capture/Compare 2 interrupt */
00743       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00744     }
00745     break;
00746
00747     case TIM_CHANNEL_3:
00748     {
00749       /* Disable the TIM Capture/Compare 3 interrupt */
00750       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00751     }
00752     break;
00753
00754     case TIM_CHANNEL_4:
00755     {
00756       /* Disable the TIM Capture/Compare 4 interrupt */
00757       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00758     }
00759     break;
00760
00761     default:
00762     break;
00763   }
00764
00765   /* Disable the Output compare channel */
00766   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00767
00768   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00769   {
00770     /* Disable the Main Output */
00771     __HAL_TIM_MOE_DISABLE(htim);
00772   }
00773
00774   /* Disable the Peripheral */
00775   __HAL_TIM_DISABLE(htim);
00776
00777   /* Return function status */
00778   return HAL_OK;
00779 }
00780
00781 /**
00782   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00783   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00784   *                the configuration information for TIM module.
00785   * @param  Channel: TIM Channel to be enabled.
00786   *          This parameter can be one of the following values:
00787   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00788   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00789   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00790   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00791   * @param  pData: The source Buffer address.
00792   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00793   * @retval HAL status
00794   */
00795 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00796 {
00797   /* Check the parameters */
00798   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00799
00800   if((htim->State == HAL_TIM_STATE_BUSY))
00801   {
00802      return HAL_BUSY;
00803   }
00804   else if((htim->State == HAL_TIM_STATE_READY))
00805   {
00806     if(((uint32_t)pData == 0U) && (Length > 0U))
00807     {
00808       return HAL_ERROR;
00809     }
00810     else
00811     {
00812       htim->State = HAL_TIM_STATE_BUSY;
00813     }
00814   }
00815   switch (Channel)
00816   {
00817     case TIM_CHANNEL_1:
00818     {
00819       /* Set the DMA Period elapsed callback */
00820       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00821
00822       /* Set the DMA error callback */
00823       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00824
00825       /* Enable the DMA Stream */
00826       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00827
00828       /* Enable the TIM Capture/Compare 1 DMA request */
00829       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00830     }
00831     break;
00832
00833     case TIM_CHANNEL_2:
00834     {
00835       /* Set the DMA Period elapsed callback */
00836       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00837
00838       /* Set the DMA error callback */
00839       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00840
00841       /* Enable the DMA Stream */
00842       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00843
00844       /* Enable the TIM Capture/Compare 2 DMA request */
00845       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00846     }
00847     break;
00848
00849     case TIM_CHANNEL_3:
00850     {
00851       /* Set the DMA Period elapsed callback */
00852       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00853
00854       /* Set the DMA error callback */
00855       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00856
00857       /* Enable the DMA Stream */
00858       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00859
00860       /* Enable the TIM Capture/Compare 3 DMA request */
00861       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00862     }
00863     break;
00864
00865     case TIM_CHANNEL_4:
00866     {
00867      /* Set the DMA Period elapsed callback */
00868       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00869
00870       /* Set the DMA error callback */
00871       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00872
00873       /* Enable the DMA Stream */
00874       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00875
00876       /* Enable the TIM Capture/Compare 4 DMA request */
00877       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00878     }
00879     break;
00880
00881     default:
00882     break;
00883   }
00884
00885   /* Enable the Output compare channel */
00886   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00887
00888   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00889   {
00890     /* Enable the main output */
00891     __HAL_TIM_MOE_ENABLE(htim);
00892   }
00893
00894   /* Enable the Peripheral */
00895   __HAL_TIM_ENABLE(htim);
00896
00897   /* Return function status */
00898   return HAL_OK;
00899 }
00900
00901 /**
00902   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
00903   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00904   *                the configuration information for TIM module.
00905   * @param  Channel: TIM Channel to be disabled.
00906   *          This parameter can be one of the following values:
00907   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00908   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00909   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00910   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00914 {
00915   /* Check the parameters */
00916   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00917
00918   switch (Channel)
00919   {
00920     case TIM_CHANNEL_1:
00921     {
00922       /* Disable the TIM Capture/Compare 1 DMA request */
00923       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00924     }
00925     break;
00926
00927     case TIM_CHANNEL_2:
00928     {
00929       /* Disable the TIM Capture/Compare 2 DMA request */
00930       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00931     }
00932     break;
00933
00934     case TIM_CHANNEL_3:
00935     {
00936       /* Disable the TIM Capture/Compare 3 DMA request */
00937       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00938     }
00939     break;
00940
00941     case TIM_CHANNEL_4:
00942     {
00943       /* Disable the TIM Capture/Compare 4 interrupt */
00944       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00945     }
00946     break;
00947
00948     default:
00949     break;
00950   }
00951
00952   /* Disable the Output compare channel */
00953   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00954
00955   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
00956   {
00957     /* Disable the Main Output */
00958     __HAL_TIM_MOE_DISABLE(htim);
00959   }
00960
00961   /* Disable the Peripheral */
00962   __HAL_TIM_DISABLE(htim);
00963
00964   /* Change the htim state */
00965   htim->State = HAL_TIM_STATE_READY;
00966
00967   /* Return function status */
00968   return HAL_OK;
00969 }
00970 /**
00971   * @}
00972   */
00973
00974 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
00975  *  @brief    Time PWM functions
00976  *
00977 @verbatim
00978   ==============================================================================
00979                           ##### Time PWM functions #####
00980   ==============================================================================
00981   [..]
00982     This section provides functions allowing to:
00983     (+) Initialize and configure the TIM OPWM.
00984     (+) De-initialize the TIM PWM.
00985     (+) Start the Time PWM.
00986     (+) Stop the Time PWM.
00987     (+) Start the Time PWM and enable interrupt.
00988     (+) Stop the Time PWM and disable interrupt.
00989     (+) Start the Time PWM and enable DMA transfer.
00990     (+) Stop the Time PWM and disable DMA transfer.
00991
00992 @endverbatim
00993   * @{
00994   */
00995 /**
00996   * @brief  Initializes the TIM PWM Time Base according to the specified
00997   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00998   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00999   *                the configuration information for TIM module.
01000   * @retval HAL status
01001   */
01002 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
01003 {
01004   /* Check the TIM handle allocation */
01005   if(htim == NULL)
01006   {
01007     return HAL_ERROR;
01008   }
01009
01010   /* Check the parameters */
01011   assert_param(IS_TIM_INSTANCE(htim->Instance));
01012   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01013   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01014
01015   if(htim->State == HAL_TIM_STATE_RESET)
01016   {
01017     /* Allocate lock resource and initialize it */
01018     htim->Lock = HAL_UNLOCKED;
01019     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01020     HAL_TIM_PWM_MspInit(htim);
01021   }
01022
01023   /* Set the TIM state */
01024   htim->State= HAL_TIM_STATE_BUSY;
01025
01026   /* Init the base time for the PWM */
01027   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01028
01029   /* Initialize the TIM state*/
01030   htim->State= HAL_TIM_STATE_READY;
01031
01032   return HAL_OK;
01033 }
01034
01035 /**
01036   * @brief  DeInitializes the TIM peripheral
01037   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01038   *                the configuration information for TIM module.
01039   * @retval HAL status
01040   */
01041 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01042 {
01043   /* Check the parameters */
01044   assert_param(IS_TIM_INSTANCE(htim->Instance));
01045
01046   htim->State = HAL_TIM_STATE_BUSY;
01047
01048   /* Disable the TIM Peripheral Clock */
01049   __HAL_TIM_DISABLE(htim);
01050
01051   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01052   HAL_TIM_PWM_MspDeInit(htim);
01053
01054   /* Change TIM state */
01055   htim->State = HAL_TIM_STATE_RESET;
01056
01057   /* Release Lock */
01058   __HAL_UNLOCK(htim);
01059
01060   return HAL_OK;
01061 }
01062
01063 /**
01064   * @brief  Initializes the TIM PWM MSP.
01065   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01066   *                the configuration information for TIM module.
01067   * @retval None
01068   */
01069 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01070 {
01071   /* Prevent unused argument(s) compilation warning */
01072   UNUSED(htim);
01073   /* NOTE : This function Should not be modified, when the callback is needed,
01074             the HAL_TIM_PWM_MspInit could be implemented in the user file
01075    */
01076 }
01077
01078 /**
01079   * @brief  DeInitializes TIM PWM MSP.
01080   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01081   *                the configuration information for TIM module.
01082   * @retval None
01083   */
01084 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01085 {
01086   /* Prevent unused argument(s) compilation warning */
01087   UNUSED(htim);
01088   /* NOTE : This function Should not be modified, when the callback is needed,
01089             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01090    */
01091 }
01092
01093 /**
01094   * @brief  Starts the PWM signal generation.
01095   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01096   *                the configuration information for TIM module.
01097   * @param  Channel: TIM Channels to be enabled.
01098   *          This parameter can be one of the following values:
01099   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01100   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01101   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01102   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01103   * @retval HAL status
01104   */
01105 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01106 {
01107   /* Check the parameters */
01108   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01109
01110   /* Enable the Capture compare channel */
01111   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01112
01113   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01114   {
01115     /* Enable the main output */
01116     __HAL_TIM_MOE_ENABLE(htim);
01117   }
01118
01119   /* Enable the Peripheral */
01120   __HAL_TIM_ENABLE(htim);
01121
01122   /* Return function status */
01123   return HAL_OK;
01124 }
01125
01126 /**
01127   * @brief  Stops the PWM signal generation.
01128   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01129   *                the configuration information for TIM module.
01130   * @param  Channel: TIM Channels to be disabled.
01131   *          This parameter can be one of the following values:
01132   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01133   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01134   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01135   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01136   * @retval HAL status
01137   */
01138 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01139 {
01140   /* Check the parameters */
01141   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01142
01143   /* Disable the Capture compare channel */
01144   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01145
01146   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01147   {
01148     /* Disable the Main Output */
01149     __HAL_TIM_MOE_DISABLE(htim);
01150   }
01151
01152   /* Disable the Peripheral */
01153   __HAL_TIM_DISABLE(htim);
01154
01155   /* Change the htim state */
01156   htim->State = HAL_TIM_STATE_READY;
01157
01158   /* Return function status */
01159   return HAL_OK;
01160 }
01161
01162 /**
01163   * @brief  Starts the PWM signal generation in interrupt mode.
01164   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01165   *                the configuration information for TIM module.
01166   * @param  Channel: TIM Channel to be disabled.
01167   *          This parameter can be one of the following values:
01168   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01169   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01170   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01171   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01172   * @retval HAL status
01173   */
01174 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01175 {
01176   /* Check the parameters */
01177   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01178
01179   switch (Channel)
01180   {
01181     case TIM_CHANNEL_1:
01182     {
01183       /* Enable the TIM Capture/Compare 1 interrupt */
01184       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01185     }
01186     break;
01187
01188     case TIM_CHANNEL_2:
01189     {
01190       /* Enable the TIM Capture/Compare 2 interrupt */
01191       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01192     }
01193     break;
01194
01195     case TIM_CHANNEL_3:
01196     {
01197       /* Enable the TIM Capture/Compare 3 interrupt */
01198       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01199     }
01200     break;
01201
01202     case TIM_CHANNEL_4:
01203     {
01204       /* Enable the TIM Capture/Compare 4 interrupt */
01205       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01206     }
01207     break;
01208
01209     default:
01210     break;
01211   }
01212
01213   /* Enable the Capture compare channel */
01214   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01215
01216   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01217   {
01218     /* Enable the main output */
01219     __HAL_TIM_MOE_ENABLE(htim);
01220   }
01221
01222   /* Enable the Peripheral */
01223   __HAL_TIM_ENABLE(htim);
01224
01225   /* Return function status */
01226   return HAL_OK;
01227 }
01228
01229 /**
01230   * @brief  Stops the PWM signal generation in interrupt mode.
01231   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01232   *                the configuration information for TIM module.
01233   * @param  Channel: TIM Channels to be disabled.
01234   *          This parameter can be one of the following values:
01235   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01236   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01237   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01238   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01239   * @retval HAL status
01240   */
01241 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01242 {
01243   /* Check the parameters */
01244   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01245
01246   switch (Channel)
01247   {
01248     case TIM_CHANNEL_1:
01249     {
01250       /* Disable the TIM Capture/Compare 1 interrupt */
01251       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01252     }
01253     break;
01254
01255     case TIM_CHANNEL_2:
01256     {
01257       /* Disable the TIM Capture/Compare 2 interrupt */
01258       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01259     }
01260     break;
01261
01262     case TIM_CHANNEL_3:
01263     {
01264       /* Disable the TIM Capture/Compare 3 interrupt */
01265       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01266     }
01267     break;
01268
01269     case TIM_CHANNEL_4:
01270     {
01271       /* Disable the TIM Capture/Compare 4 interrupt */
01272       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01273     }
01274     break;
01275
01276     default:
01277     break;
01278   }
01279
01280   /* Disable the Capture compare channel */
01281   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01282
01283   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01284   {
01285     /* Disable the Main Output */
01286     __HAL_TIM_MOE_DISABLE(htim);
01287   }
01288
01289   /* Disable the Peripheral */
01290   __HAL_TIM_DISABLE(htim);
01291
01292   /* Return function status */
01293   return HAL_OK;
01294 }
01295
01296 /**
01297   * @brief  Starts the TIM PWM signal generation in DMA mode.
01298   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01299   *                the configuration information for TIM module.
01300   * @param  Channel: TIM Channels to be enabled.
01301   *          This parameter can be one of the following values:
01302   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01303   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01304   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01305   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01306   * @param  pData: The source Buffer address.
01307   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01308   * @retval HAL status
01309   */
01310 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01311 {
01312   /* Check the parameters */
01313   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01314
01315   if((htim->State == HAL_TIM_STATE_BUSY))
01316   {
01317      return HAL_BUSY;
01318   }
01319   else if((htim->State == HAL_TIM_STATE_READY))
01320   {
01321     if(((uint32_t)pData == 0U) && (Length > 0U))
01322     {
01323       return HAL_ERROR;
01324     }
01325     else
01326     {
01327       htim->State = HAL_TIM_STATE_BUSY;
01328     }
01329   }
01330   switch (Channel)
01331   {
01332     case TIM_CHANNEL_1:
01333     {
01334       /* Set the DMA Period elapsed callback */
01335       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01336
01337       /* Set the DMA error callback */
01338       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01339
01340       /* Enable the DMA Stream */
01341       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01342
01343       /* Enable the TIM Capture/Compare 1 DMA request */
01344       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01345     }
01346     break;
01347
01348     case TIM_CHANNEL_2:
01349     {
01350       /* Set the DMA Period elapsed callback */
01351       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01352
01353       /* Set the DMA error callback */
01354       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01355
01356       /* Enable the DMA Stream */
01357       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01358
01359       /* Enable the TIM Capture/Compare 2 DMA request */
01360       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01361     }
01362     break;
01363
01364     case TIM_CHANNEL_3:
01365     {
01366       /* Set the DMA Period elapsed callback */
01367       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01368
01369       /* Set the DMA error callback */
01370       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01371
01372       /* Enable the DMA Stream */
01373       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01374
01375       /* Enable the TIM Output Capture/Compare 3 request */
01376       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01377     }
01378     break;
01379
01380     case TIM_CHANNEL_4:
01381     {
01382      /* Set the DMA Period elapsed callback */
01383       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01384
01385       /* Set the DMA error callback */
01386       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01387
01388       /* Enable the DMA Stream */
01389       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01390
01391       /* Enable the TIM Capture/Compare 4 DMA request */
01392       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01393     }
01394     break;
01395
01396     default:
01397     break;
01398   }
01399
01400   /* Enable the Capture compare channel */
01401   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01402
01403   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01404   {
01405     /* Enable the main output */
01406     __HAL_TIM_MOE_ENABLE(htim);
01407   }
01408
01409   /* Enable the Peripheral */
01410   __HAL_TIM_ENABLE(htim);
01411
01412   /* Return function status */
01413   return HAL_OK;
01414 }
01415
01416 /**
01417   * @brief  Stops the TIM PWM signal generation in DMA mode.
01418   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01419   *                the configuration information for TIM module.
01420   * @param  Channel: TIM Channels to be disabled.
01421   *          This parameter can be one of the following values:
01422   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01423   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01424   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01425   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01426   * @retval HAL status
01427   */
01428 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01429 {
01430   /* Check the parameters */
01431   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01432
01433   switch (Channel)
01434   {
01435     case TIM_CHANNEL_1:
01436     {
01437       /* Disable the TIM Capture/Compare 1 DMA request */
01438       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01439     }
01440     break;
01441
01442     case TIM_CHANNEL_2:
01443     {
01444       /* Disable the TIM Capture/Compare 2 DMA request */
01445       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01446     }
01447     break;
01448
01449     case TIM_CHANNEL_3:
01450     {
01451       /* Disable the TIM Capture/Compare 3 DMA request */
01452       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01453     }
01454     break;
01455
01456     case TIM_CHANNEL_4:
01457     {
01458       /* Disable the TIM Capture/Compare 4 interrupt */
01459       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01460     }
01461     break;
01462
01463     default:
01464     break;
01465   }
01466
01467   /* Disable the Capture compare channel */
01468   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01469
01470   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
01471   {
01472     /* Disable the Main Output */
01473     __HAL_TIM_MOE_DISABLE(htim);
01474   }
01475
01476   /* Disable the Peripheral */
01477   __HAL_TIM_DISABLE(htim);
01478
01479   /* Change the htim state */
01480   htim->State = HAL_TIM_STATE_READY;
01481
01482   /* Return function status */
01483   return HAL_OK;
01484 }
01485 /**
01486   * @}
01487   */
01488
01489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
01490  *  @brief    Time Input Capture functions
01491  *
01492 @verbatim
01493   ==============================================================================
01494               ##### Time Input Capture functions #####
01495   ==============================================================================
01496  [..]
01497    This section provides functions allowing to:
01498    (+) Initialize and configure the TIM Input Capture.
01499    (+) De-initialize the TIM Input Capture.
01500    (+) Start the Time Input Capture.
01501    (+) Stop the Time Input Capture.
01502    (+) Start the Time Input Capture and enable interrupt.
01503    (+) Stop the Time Input Capture and disable interrupt.
01504    (+) Start the Time Input Capture and enable DMA transfer.
01505    (+) Stop the Time Input Capture and disable DMA transfer.
01506
01507 @endverbatim
01508   * @{
01509   */
01510 /**
01511   * @brief  Initializes the TIM Input Capture Time base according to the specified
01512   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01513   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01514   *                the configuration information for TIM module.
01515   * @retval HAL status
01516   */
01517 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01518 {
01519   /* Check the TIM handle allocation */
01520   if(htim == NULL)
01521   {
01522     return HAL_ERROR;
01523   }
01524
01525   /* Check the parameters */
01526   assert_param(IS_TIM_INSTANCE(htim->Instance));
01527   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01528   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01529
01530   if(htim->State == HAL_TIM_STATE_RESET)
01531   {
01532     /* Allocate lock resource and initialize it */
01533     htim->Lock = HAL_UNLOCKED;
01534     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01535     HAL_TIM_IC_MspInit(htim);
01536   }
01537
01538   /* Set the TIM state */
01539   htim->State= HAL_TIM_STATE_BUSY;
01540
01541   /* Init the base time for the input capture */
01542   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01543
01544   /* Initialize the TIM state*/
01545   htim->State= HAL_TIM_STATE_READY;
01546
01547   return HAL_OK;
01548 }
01549
01550 /**
01551   * @brief  DeInitializes the TIM peripheral
01552   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01553   *                the configuration information for TIM module.
01554   * @retval HAL status
01555   */
01556 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01557 {
01558   /* Check the parameters */
01559   assert_param(IS_TIM_INSTANCE(htim->Instance));
01560
01561   htim->State = HAL_TIM_STATE_BUSY;
01562
01563   /* Disable the TIM Peripheral Clock */
01564   __HAL_TIM_DISABLE(htim);
01565
01566   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01567   HAL_TIM_IC_MspDeInit(htim);
01568
01569   /* Change TIM state */
01570   htim->State = HAL_TIM_STATE_RESET;
01571
01572   /* Release Lock */
01573   __HAL_UNLOCK(htim);
01574
01575   return HAL_OK;
01576 }
01577
01578 /**
01579   * @brief  Initializes the TIM INput Capture MSP.
01580   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01581   *                the configuration information for TIM module.
01582   * @retval None
01583   */
01584 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01585 {
01586   /* Prevent unused argument(s) compilation warning */
01587   UNUSED(htim);
01588   /* NOTE : This function Should not be modified, when the callback is needed,
01589             the HAL_TIM_IC_MspInit could be implemented in the user file
01590    */
01591 }
01592
01593 /**
01594   * @brief  DeInitializes TIM Input Capture MSP.
01595   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01596   *                the configuration information for TIM module.
01597   * @retval None
01598   */
01599 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01600 {
01601   /* Prevent unused argument(s) compilation warning */
01602   UNUSED(htim);
01603   /* NOTE : This function Should not be modified, when the callback is needed,
01604             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01605    */
01606 }
01607
01608 /**
01609   * @brief  Starts the TIM Input Capture measurement.
01610   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01611   *                the configuration information for TIM module.
01612   * @param  Channel: TIM Channels to be enabled.
01613   *          This parameter can be one of the following values:
01614   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01615   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01616   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01617   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01618   * @retval HAL status
01619   */
01620 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
01621 {
01622   /* Check the parameters */
01623   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01624
01625   /* Enable the Input Capture channel */
01626   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01627
01628   /* Enable the Peripheral */
01629   __HAL_TIM_ENABLE(htim);
01630
01631   /* Return function status */
01632   return HAL_OK;
01633 }
01634
01635 /**
01636   * @brief  Stops the TIM Input Capture measurement.
01637   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01638   *                the configuration information for TIM module.
01639   * @param  Channel: TIM Channels to be disabled.
01640   *          This parameter can be one of the following values:
01641   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01642   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01643   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01644   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01645   * @retval HAL status
01646   */
01647 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01648 {
01649   /* Check the parameters */
01650   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01651
01652   /* Disable the Input Capture channel */
01653   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01654
01655   /* Disable the Peripheral */
01656   __HAL_TIM_DISABLE(htim);
01657
01658   /* Return function status */
01659   return HAL_OK;
01660 }
01661
01662 /**
01663   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01664   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01665   *                the configuration information for TIM module.
01666   * @param  Channel: TIM Channels to be enabled.
01667   *          This parameter can be one of the following values:
01668   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01669   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01670   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01671   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01672   * @retval HAL status
01673   */
01674 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01675 {
01676   /* Check the parameters */
01677   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01678
01679   switch (Channel)
01680   {
01681     case TIM_CHANNEL_1:
01682     {
01683       /* Enable the TIM Capture/Compare 1 interrupt */
01684       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01685     }
01686     break;
01687
01688     case TIM_CHANNEL_2:
01689     {
01690       /* Enable the TIM Capture/Compare 2 interrupt */
01691       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01692     }
01693     break;
01694
01695     case TIM_CHANNEL_3:
01696     {
01697       /* Enable the TIM Capture/Compare 3 interrupt */
01698       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01699     }
01700     break;
01701
01702     case TIM_CHANNEL_4:
01703     {
01704       /* Enable the TIM Capture/Compare 4 interrupt */
01705       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01706     }
01707     break;
01708
01709     default:
01710     break;
01711   }
01712   /* Enable the Input Capture channel */
01713   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01714
01715   /* Enable the Peripheral */
01716   __HAL_TIM_ENABLE(htim);
01717
01718   /* Return function status */
01719   return HAL_OK;
01720 }
01721
01722 /**
01723   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01724   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01725   *                the configuration information for TIM module.
01726   * @param  Channel: TIM Channels to be disabled.
01727   *          This parameter can be one of the following values:
01728   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01729   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01730   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01731   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01732   * @retval HAL status
01733   */
01734 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01735 {
01736   /* Check the parameters */
01737   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01738
01739   switch (Channel)
01740   {
01741     case TIM_CHANNEL_1:
01742     {
01743       /* Disable the TIM Capture/Compare 1 interrupt */
01744       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01745     }
01746     break;
01747
01748     case TIM_CHANNEL_2:
01749     {
01750       /* Disable the TIM Capture/Compare 2 interrupt */
01751       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01752     }
01753     break;
01754
01755     case TIM_CHANNEL_3:
01756     {
01757       /* Disable the TIM Capture/Compare 3 interrupt */
01758       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01759     }
01760     break;
01761
01762     case TIM_CHANNEL_4:
01763     {
01764       /* Disable the TIM Capture/Compare 4 interrupt */
01765       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01766     }
01767     break;
01768
01769     default:
01770     break;
01771   }
01772
01773   /* Disable the Input Capture channel */
01774   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01775
01776   /* Disable the Peripheral */
01777   __HAL_TIM_DISABLE(htim);
01778
01779   /* Return function status */
01780   return HAL_OK;
01781 }
01782
01783 /**
01784   * @brief  Starts the TIM Input Capture measurement on in DMA mode.
01785   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01786   *                the configuration information for TIM module.
01787   * @param  Channel: TIM Channels to be enabled.
01788   *          This parameter can be one of the following values:
01789   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01790   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01791   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01792   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01793   * @param  pData: The destination Buffer address.
01794   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
01795   * @retval HAL status
01796   */
01797 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01798 {
01799   /* Check the parameters */
01800   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01801   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01802
01803   if((htim->State == HAL_TIM_STATE_BUSY))
01804   {
01805      return HAL_BUSY;
01806   }
01807   else if((htim->State == HAL_TIM_STATE_READY))
01808   {
01809     if((pData == 0U) && (Length > 0U))
01810     {
01811       return HAL_ERROR;
01812     }
01813     else
01814     {
01815       htim->State = HAL_TIM_STATE_BUSY;
01816     }
01817   }
01818
01819   switch (Channel)
01820   {
01821     case TIM_CHANNEL_1:
01822     {
01823       /* Set the DMA Period elapsed callback */
01824       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
01825
01826       /* Set the DMA error callback */
01827       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01828
01829       /* Enable the DMA Stream */
01830       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
01831
01832       /* Enable the TIM Capture/Compare 1 DMA request */
01833       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01834     }
01835     break;
01836
01837     case TIM_CHANNEL_2:
01838     {
01839       /* Set the DMA Period elapsed callback */
01840       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
01841
01842       /* Set the DMA error callback */
01843       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01844
01845       /* Enable the DMA Stream */
01846       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
01847
01848       /* Enable the TIM Capture/Compare 2  DMA request */
01849       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01850     }
01851     break;
01852
01853     case TIM_CHANNEL_3:
01854     {
01855       /* Set the DMA Period elapsed callback */
01856       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
01857
01858       /* Set the DMA error callback */
01859       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01860
01861       /* Enable the DMA Stream */
01862       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
01863
01864       /* Enable the TIM Capture/Compare 3  DMA request */
01865       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01866     }
01867     break;
01868
01869     case TIM_CHANNEL_4:
01870     {
01871       /* Set the DMA Period elapsed callback */
01872       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
01873
01874       /* Set the DMA error callback */
01875       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01876
01877       /* Enable the DMA Stream */
01878       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
01879
01880       /* Enable the TIM Capture/Compare 4  DMA request */
01881       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01882     }
01883     break;
01884
01885     default:
01886     break;
01887   }
01888
01889   /* Enable the Input Capture channel */
01890   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01891
01892   /* Enable the Peripheral */
01893   __HAL_TIM_ENABLE(htim);
01894
01895   /* Return function status */
01896   return HAL_OK;
01897 }
01898
01899 /**
01900   * @brief  Stops the TIM Input Capture measurement on in DMA mode.
01901   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01902   *                the configuration information for TIM module.
01903   * @param  Channel: TIM Channels to be disabled.
01904   *          This parameter can be one of the following values:
01905   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01906   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01907   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01908   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01909   * @retval HAL status
01910   */
01911 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01912 {
01913   /* Check the parameters */
01914   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01915   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01916
01917   switch (Channel)
01918   {
01919     case TIM_CHANNEL_1:
01920     {
01921       /* Disable the TIM Capture/Compare 1 DMA request */
01922       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01923     }
01924     break;
01925
01926     case TIM_CHANNEL_2:
01927     {
01928       /* Disable the TIM Capture/Compare 2 DMA request */
01929       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01930     }
01931     break;
01932
01933     case TIM_CHANNEL_3:
01934     {
01935       /* Disable the TIM Capture/Compare 3  DMA request */
01936       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01937     }
01938     break;
01939
01940     case TIM_CHANNEL_4:
01941     {
01942       /* Disable the TIM Capture/Compare 4  DMA request */
01943       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01944     }
01945     break;
01946
01947     default:
01948     break;
01949   }
01950
01951   /* Disable the Input Capture channel */
01952   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01953
01954   /* Disable the Peripheral */
01955   __HAL_TIM_DISABLE(htim);
01956
01957   /* Change the htim state */
01958   htim->State = HAL_TIM_STATE_READY;
01959
01960   /* Return function status */
01961   return HAL_OK;
01962 }
01963 /**
01964   * @}
01965   */
01966
01967 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
01968  *  @brief    Time One Pulse functions
01969  *
01970 @verbatim
01971   ==============================================================================
01972                         ##### Time One Pulse functions #####
01973   ==============================================================================
01974   [..]
01975     This section provides functions allowing to:
01976     (+) Initialize and configure the TIM One Pulse.
01977     (+) De-initialize the TIM One Pulse.
01978     (+) Start the Time One Pulse.
01979     (+) Stop the Time One Pulse.
01980     (+) Start the Time One Pulse and enable interrupt.
01981     (+) Stop the Time One Pulse and disable interrupt.
01982     (+) Start the Time One Pulse and enable DMA transfer.
01983     (+) Stop the Time One Pulse and disable DMA transfer.
01984
01985 @endverbatim
01986   * @{
01987   */
01988 /**
01989   * @brief  Initializes the TIM One Pulse Time Base according to the specified
01990   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01991   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01992   *                the configuration information for TIM module.
01993   * @param  OnePulseMode: Select the One pulse mode.
01994   *         This parameter can be one of the following values:
01995   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
01996   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
01997   * @retval HAL status
01998   */
01999 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
02000 {
02001   /* Check the TIM handle allocation */
02002   if(htim == NULL)
02003   {
02004     return HAL_ERROR;
02005   }
02006
02007   /* Check the parameters */
02008   assert_param(IS_TIM_INSTANCE(htim->Instance));
02009   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02010   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02011   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
02012
02013   if(htim->State == HAL_TIM_STATE_RESET)
02014   {
02015     /* Allocate lock resource and initialize it */
02016     htim->Lock = HAL_UNLOCKED;
02017     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02018     HAL_TIM_OnePulse_MspInit(htim);
02019   }
02020
02021   /* Set the TIM state */
02022   htim->State= HAL_TIM_STATE_BUSY;
02023
02024   /* Configure the Time base in the One Pulse Mode */
02025   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02026
02027   /* Reset the OPM Bit */
02028   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02029
02030   /* Configure the OPM Mode */
02031   htim->Instance->CR1 |= OnePulseMode;
02032
02033   /* Initialize the TIM state*/
02034   htim->State= HAL_TIM_STATE_READY;
02035
02036   return HAL_OK;
02037 }
02038
02039 /**
02040   * @brief  DeInitializes the TIM One Pulse
02041   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02042   *                the configuration information for TIM module.
02043   * @retval HAL status
02044   */
02045 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02046 {
02047   /* Check the parameters */
02048   assert_param(IS_TIM_INSTANCE(htim->Instance));
02049
02050   htim->State = HAL_TIM_STATE_BUSY;
02051
02052   /* Disable the TIM Peripheral Clock */
02053   __HAL_TIM_DISABLE(htim);
02054
02055   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02056   HAL_TIM_OnePulse_MspDeInit(htim);
02057
02058   /* Change TIM state */
02059   htim->State = HAL_TIM_STATE_RESET;
02060
02061   /* Release Lock */
02062   __HAL_UNLOCK(htim);
02063
02064   return HAL_OK;
02065 }
02066
02067 /**
02068   * @brief  Initializes the TIM One Pulse MSP.
02069   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02070   *                the configuration information for TIM module.
02071   * @retval None
02072   */
02073 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02074 {
02075   /* Prevent unused argument(s) compilation warning */
02076   UNUSED(htim);
02077   /* NOTE : This function Should not be modified, when the callback is needed,
02078             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02079    */
02080 }
02081
02082 /**
02083   * @brief  DeInitializes TIM One Pulse MSP.
02084   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02085   *                the configuration information for TIM module.
02086   * @retval None
02087   */
02088 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02089 {
02090   /* Prevent unused argument(s) compilation warning */
02091   UNUSED(htim);
02092   /* NOTE : This function Should not be modified, when the callback is needed,
02093             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02094    */
02095 }
02096
02097 /**
02098   * @brief  Starts the TIM One Pulse signal generation.
02099   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02100   *                the configuration information for TIM module.
02101   * @param  OutputChannel : TIM Channels to be enabled.
02102   *          This parameter can be one of the following values:
02103   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02104   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02105   * @retval HAL status
02106   */
02107 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02108 {
02109   /* Enable the Capture compare and the Input Capture channels
02110     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02111     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02112     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02113     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02114
02115     No need to enable the counter, it's enabled automatically by hardware
02116     (the counter starts in response to a stimulus and generate a pulse */
02117
02118   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02119   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02120
02121   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02122   {
02123     /* Enable the main output */
02124     __HAL_TIM_MOE_ENABLE(htim);
02125   }
02126
02127   /* Return function status */
02128   return HAL_OK;
02129 }
02130
02131 /**
02132   * @brief  Stops the TIM One Pulse signal generation.
02133   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02134   *                the configuration information for TIM module.
02135   * @param  OutputChannel : TIM Channels to be disable.
02136   *          This parameter can be one of the following values:
02137   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02138   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02139   * @retval HAL status
02140   */
02141 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02142 {
02143   /* Disable the Capture compare and the Input Capture channels
02144   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02145   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02146   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02147   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02148
02149   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02150   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02151
02152   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02153   {
02154     /* Disable the Main Output */
02155     __HAL_TIM_MOE_DISABLE(htim);
02156   }
02157
02158   /* Disable the Peripheral */
02159   __HAL_TIM_DISABLE(htim);
02160
02161   /* Return function status */
02162   return HAL_OK;
02163 }
02164
02165 /**
02166   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02167   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02168   *                the configuration information for TIM module.
02169   * @param  OutputChannel : TIM Channels to be enabled.
02170   *          This parameter can be one of the following values:
02171   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02172   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02173   * @retval HAL status
02174   */
02175 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02176 {
02177   /* Enable the Capture compare and the Input Capture channels
02178     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02179     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02180     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02181     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02182
02183     No need to enable the counter, it's enabled automatically by hardware
02184     (the counter starts in response to a stimulus and generate a pulse */
02185
02186   /* Enable the TIM Capture/Compare 1 interrupt */
02187   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02188
02189   /* Enable the TIM Capture/Compare 2 interrupt */
02190   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02191
02192   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02193   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02194
02195   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02196   {
02197     /* Enable the main output */
02198     __HAL_TIM_MOE_ENABLE(htim);
02199   }
02200
02201   /* Return function status */
02202   return HAL_OK;
02203 }
02204
02205 /**
02206   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02207   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02208   *                the configuration information for TIM module.
02209   * @param  OutputChannel : TIM Channels to be enabled.
02210   *          This parameter can be one of the following values:
02211   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02212   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02213   * @retval HAL status
02214   */
02215 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02216 {
02217   /* Disable the TIM Capture/Compare 1 interrupt */
02218   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02219
02220   /* Disable the TIM Capture/Compare 2 interrupt */
02221   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02222
02223   /* Disable the Capture compare and the Input Capture channels
02224   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02225   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02226   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02227   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02228   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02229   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02230
02231   if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
02232   {
02233     /* Disable the Main Output */
02234     __HAL_TIM_MOE_DISABLE(htim);
02235   }
02236
02237   /* Disable the Peripheral */
02238    __HAL_TIM_DISABLE(htim);
02239
02240   /* Return function status */
02241   return HAL_OK;
02242 }
02243 /**
02244   * @}
02245   */
02246
02247 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
02248  *  @brief    Time Encoder functions
02249  *
02250 @verbatim
02251   ==============================================================================
02252                           ##### Time Encoder functions #####
02253   ==============================================================================
02254   [..]
02255     This section provides functions allowing to:
02256     (+) Initialize and configure the TIM Encoder.
02257     (+) De-initialize the TIM Encoder.
02258     (+) Start the Time Encoder.
02259     (+) Stop the Time Encoder.
02260     (+) Start the Time Encoder and enable interrupt.
02261     (+) Stop the Time Encoder and disable interrupt.
02262     (+) Start the Time Encoder and enable DMA transfer.
02263     (+) Stop the Time Encoder and disable DMA transfer.
02264
02265 @endverbatim
02266   * @{
02267   */
02268 /**
02269   * @brief  Initializes the TIM Encoder Interface and create the associated handle.
02270   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02271   *                the configuration information for TIM module.
02272   * @param  sConfig: TIM Encoder Interface configuration structure
02273   * @retval HAL status
02274   */
02275 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
02276 {
02277   uint32_t tmpsmcr = 0U;
02278   uint32_t tmpccmr1 = 0U;
02279   uint32_t tmpccer = 0U;
02280
02281   /* Check the TIM handle allocation */
02282   if(htim == NULL)
02283   {
02284     return HAL_ERROR;
02285   }
02286
02287   /* Check the parameters */
02288   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02289   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02290   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02291   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02292   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
02293   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
02294   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02295   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02296   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02297   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02298
02299   if(htim->State == HAL_TIM_STATE_RESET)
02300   {
02301     /* Allocate lock resource and initialize it */
02302     htim->Lock = HAL_UNLOCKED;
02303     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02304     HAL_TIM_Encoder_MspInit(htim);
02305   }
02306
02307   /* Set the TIM state */
02308   htim->State= HAL_TIM_STATE_BUSY;
02309
02310   /* Reset the SMS bits */
02311   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
02312
02313   /* Configure the Time base in the Encoder Mode */
02314   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02315
02316   /* Get the TIMx SMCR register value */
02317   tmpsmcr = htim->Instance->SMCR;
02318
02319   /* Get the TIMx CCMR1 register value */
02320   tmpccmr1 = htim->Instance->CCMR1;
02321
02322   /* Get the TIMx CCER register value */
02323   tmpccer = htim->Instance->CCER;
02324
02325   /* Set the encoder Mode */
02326   tmpsmcr |= sConfig->EncoderMode;
02327
02328   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02329   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02330   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
02331
02332   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02333   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02334   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02335   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
02336   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
02337
02338   /* Set the TI1 and the TI2 Polarities */
02339   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02340   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02341   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
02342
02343   /* Write to TIMx SMCR */
02344   htim->Instance->SMCR = tmpsmcr;
02345
02346   /* Write to TIMx CCMR1 */
02347   htim->Instance->CCMR1 = tmpccmr1;
02348
02349   /* Write to TIMx CCER */
02350   htim->Instance->CCER = tmpccer;
02351
02352   /* Initialize the TIM state*/
02353   htim->State= HAL_TIM_STATE_READY;
02354
02355   return HAL_OK;
02356 }
02357
02358 /**
02359   * @brief  DeInitializes the TIM Encoder interface
02360   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02361   *                the configuration information for TIM module.
02362   * @retval HAL status
02363   */
02364 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02365 {
02366   /* Check the parameters */
02367   assert_param(IS_TIM_INSTANCE(htim->Instance));
02368
02369   htim->State = HAL_TIM_STATE_BUSY;
02370
02371   /* Disable the TIM Peripheral Clock */
02372   __HAL_TIM_DISABLE(htim);
02373
02374   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02375   HAL_TIM_Encoder_MspDeInit(htim);
02376
02377   /* Change TIM state */
02378   htim->State = HAL_TIM_STATE_RESET;
02379
02380   /* Release Lock */
02381   __HAL_UNLOCK(htim);
02382
02383   return HAL_OK;
02384 }
02385
02386 /**
02387   * @brief  Initializes the TIM Encoder Interface MSP.
02388   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02389   *                the configuration information for TIM module.
02390   * @retval None
02391   */
02392 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02393 {
02394   /* Prevent unused argument(s) compilation warning */
02395   UNUSED(htim);
02396   /* NOTE : This function Should not be modified, when the callback is needed,
02397             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02398    */
02399 }
02400
02401 /**
02402   * @brief  DeInitializes TIM Encoder Interface MSP.
02403   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02404   *                the configuration information for TIM module.
02405   * @retval None
02406   */
02407 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02408 {
02409   /* Prevent unused argument(s) compilation warning */
02410   UNUSED(htim);
02411   /* NOTE : This function Should not be modified, when the callback is needed,
02412             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02413    */
02414 }
02415
02416 /**
02417   * @brief  Starts the TIM Encoder Interface.
02418   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02419   *                the configuration information for TIM module.
02420   * @param  Channel: TIM Channels to be enabled.
02421   *          This parameter can be one of the following values:
02422   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02423   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02424   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02425   * @retval HAL status
02426   */
02427 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02428 {
02429   /* Check the parameters */
02430   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02431
02432   /* Enable the encoder interface channels */
02433   switch (Channel)
02434   {
02435     case TIM_CHANNEL_1:
02436     {
02437       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02438       break;
02439     }
02440     case TIM_CHANNEL_2:
02441     {
02442       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02443       break;
02444     }
02445     default :
02446     {
02447      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02448      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02449      break;
02450     }
02451   }
02452   /* Enable the Peripheral */
02453   __HAL_TIM_ENABLE(htim);
02454
02455   /* Return function status */
02456   return HAL_OK;
02457 }
02458
02459 /**
02460   * @brief  Stops the TIM Encoder Interface.
02461   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02462   *                the configuration information for TIM module.
02463   * @param  Channel: TIM Channels to be disabled.
02464   *          This parameter can be one of the following values:
02465   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02466   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02467   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02468   * @retval HAL status
02469   */
02470 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02471 {
02472   /* Check the parameters */
02473     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02474
02475    /* Disable the Input Capture channels 1 and 2
02476     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02477   switch (Channel)
02478   {
02479     case TIM_CHANNEL_1:
02480     {
02481       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02482       break;
02483     }
02484     case TIM_CHANNEL_2:
02485     {
02486       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02487       break;
02488     }
02489     default :
02490     {
02491      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02492      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02493      break;
02494     }
02495   }
02496   /* Disable the Peripheral */
02497   __HAL_TIM_DISABLE(htim);
02498
02499   /* Return function status */
02500   return HAL_OK;
02501 }
02502
02503 /**
02504   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02505   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02506   *                the configuration information for TIM module.
02507   * @param  Channel: TIM Channels to be enabled.
02508   *          This parameter can be one of the following values:
02509   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02510   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02511   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02512   * @retval HAL status
02513   */
02514 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02515 {
02516   /* Check the parameters */
02517   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02518
02519   /* Enable the encoder interface channels */
02520   /* Enable the capture compare Interrupts 1 and/or 2 */
02521   switch (Channel)
02522   {
02523     case TIM_CHANNEL_1:
02524     {
02525       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02526       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02527       break;
02528     }
02529     case TIM_CHANNEL_2:
02530     {
02531       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02532       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02533       break;
02534     }
02535     default :
02536     {
02537      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02538      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02539      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02540      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02541      break;
02542     }
02543   }
02544
02545   /* Enable the Peripheral */
02546   __HAL_TIM_ENABLE(htim);
02547
02548   /* Return function status */
02549   return HAL_OK;
02550 }
02551
02552 /**
02553   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02554   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02555   *                the configuration information for TIM module.
02556   * @param  Channel: TIM Channels to be disabled.
02557   *          This parameter can be one of the following values:
02558   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02559   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02560   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02561   * @retval HAL status
02562   */
02563 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02564 {
02565   /* Check the parameters */
02566   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02567
02568   /* Disable the Input Capture channels 1 and 2
02569     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02570   if(Channel == TIM_CHANNEL_1)
02571   {
02572     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02573
02574     /* Disable the capture compare Interrupts 1 */
02575   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02576   }
02577   else if(Channel == TIM_CHANNEL_2)
02578   {
02579     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02580
02581     /* Disable the capture compare Interrupts 2 */
02582   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02583   }
02584   else
02585   {
02586     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02587     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02588
02589     /* Disable the capture compare Interrupts 1 and 2 */
02590     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02591     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02592   }
02593
02594   /* Disable the Peripheral */
02595   __HAL_TIM_DISABLE(htim);
02596
02597   /* Change the htim state */
02598   htim->State = HAL_TIM_STATE_READY;
02599
02600   /* Return function status */
02601   return HAL_OK;
02602 }
02603
02604 /**
02605   * @brief  Starts the TIM Encoder Interface in DMA mode.
02606   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02607   *                the configuration information for TIM module.
02608   * @param  Channel: TIM Channels to be enabled.
02609   *          This parameter can be one of the following values:
02610   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02611   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02612   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02613   * @param  pData1: The destination Buffer address for IC1.
02614   * @param  pData2: The destination Buffer address for IC2.
02615   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
02616   * @retval HAL status
02617   */
02618 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
02619 {
02620   /* Check the parameters */
02621   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02622
02623   if((htim->State == HAL_TIM_STATE_BUSY))
02624   {
02625      return HAL_BUSY;
02626   }
02627   else if((htim->State == HAL_TIM_STATE_READY))
02628   {
02629     if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
02630     {
02631       return HAL_ERROR;
02632     }
02633     else
02634     {
02635       htim->State = HAL_TIM_STATE_BUSY;
02636     }
02637   }
02638
02639   switch (Channel)
02640   {
02641     case TIM_CHANNEL_1:
02642     {
02643       /* Set the DMA Period elapsed callback */
02644       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02645
02646       /* Set the DMA error callback */
02647       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02648
02649       /* Enable the DMA Stream */
02650       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
02651
02652       /* Enable the TIM Input Capture DMA request */
02653       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02654
02655       /* Enable the Peripheral */
02656       __HAL_TIM_ENABLE(htim);
02657
02658       /* Enable the Capture compare channel */
02659       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02660     }
02661     break;
02662
02663     case TIM_CHANNEL_2:
02664     {
02665       /* Set the DMA Period elapsed callback */
02666       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02667
02668       /* Set the DMA error callback */
02669       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
02670       /* Enable the DMA Stream */
02671       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02672
02673       /* Enable the TIM Input Capture  DMA request */
02674       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02675
02676       /* Enable the Peripheral */
02677       __HAL_TIM_ENABLE(htim);
02678
02679       /* Enable the Capture compare channel */
02680       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02681     }
02682     break;
02683
02684     case TIM_CHANNEL_ALL:
02685     {
02686       /* Set the DMA Period elapsed callback */
02687       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02688
02689       /* Set the DMA error callback */
02690       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02691
02692       /* Enable the DMA Stream */
02693       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
02694
02695       /* Set the DMA Period elapsed callback */
02696       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02697
02698       /* Set the DMA error callback */
02699       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02700
02701       /* Enable the DMA Stream */
02702       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02703
02704      /* Enable the Peripheral */
02705       __HAL_TIM_ENABLE(htim);
02706
02707       /* Enable the Capture compare channel */
02708       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02709       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02710
02711       /* Enable the TIM Input Capture  DMA request */
02712       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02713       /* Enable the TIM Input Capture  DMA request */
02714       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02715     }
02716     break;
02717
02718     default:
02719     break;
02720   }
02721   /* Return function status */
02722   return HAL_OK;
02723 }
02724
02725 /**
02726   * @brief  Stops the TIM Encoder Interface in DMA mode.
02727   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02728   *                the configuration information for TIM module.
02729   * @param  Channel: TIM Channels to be enabled.
02730   *          This parameter can be one of the following values:
02731   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02732   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02733   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02734   * @retval HAL status
02735   */
02736 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02737 {
02738   /* Check the parameters */
02739   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02740
02741   /* Disable the Input Capture channels 1 and 2
02742     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02743   if(Channel == TIM_CHANNEL_1)
02744   {
02745     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02746
02747     /* Disable the capture compare DMA Request 1 */
02748     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02749   }
02750   else if(Channel == TIM_CHANNEL_2)
02751   {
02752     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02753
02754     /* Disable the capture compare DMA Request 2 */
02755     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02756   }
02757   else
02758   {
02759     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02760     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02761
02762     /* Disable the capture compare DMA Request 1 and 2 */
02763     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02764     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02765   }
02766
02767   /* Disable the Peripheral */
02768   __HAL_TIM_DISABLE(htim);
02769
02770   /* Change the htim state */
02771   htim->State = HAL_TIM_STATE_READY;
02772
02773   /* Return function status */
02774   return HAL_OK;
02775 }
02776 /**
02777   * @}
02778   */
02779
02780 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02781  *  @brief    IRQ handler management
02782  *
02783 @verbatim
02784   ==============================================================================
02785                         ##### IRQ handler management #####
02786   ==============================================================================
02787   [..]
02788     This section provides Timer IRQ handler function.
02789
02790 @endverbatim
02791   * @{
02792   */
02793 /**
02794   * @brief  This function handles TIM interrupts requests.
02795   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02796   *                the configuration information for TIM module.
02797   * @retval None
02798   */
02799 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
02800 {
02801   /* Capture compare 1 event */
02802   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
02803   {
02804     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
02805     {
02806       {
02807         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
02808         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02809
02810         /* Input capture event */
02811         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
02812         {
02813           HAL_TIM_IC_CaptureCallback(htim);
02814         }
02815         /* Output compare event */
02816         else
02817         {
02818           HAL_TIM_OC_DelayElapsedCallback(htim);
02819           HAL_TIM_PWM_PulseFinishedCallback(htim);
02820         }
02821         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02822       }
02823     }
02824   }
02825   /* Capture compare 2 event */
02826   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
02827   {
02828     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
02829     {
02830       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
02831       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02832       /* Input capture event */
02833       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
02834       {
02835         HAL_TIM_IC_CaptureCallback(htim);
02836       }
02837       /* Output compare event */
02838       else
02839       {
02840         HAL_TIM_OC_DelayElapsedCallback(htim);
02841         HAL_TIM_PWM_PulseFinishedCallback(htim);
02842       }
02843       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02844     }
02845   }
02846   /* Capture compare 3 event */
02847   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
02848   {
02849     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
02850     {
02851       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
02852       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02853       /* Input capture event */
02854       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
02855       {
02856         HAL_TIM_IC_CaptureCallback(htim);
02857       }
02858       /* Output compare event */
02859       else
02860       {
02861         HAL_TIM_OC_DelayElapsedCallback(htim);
02862         HAL_TIM_PWM_PulseFinishedCallback(htim);
02863       }
02864       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02865     }
02866   }
02867   /* Capture compare 4 event */
02868   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
02869   {
02870     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
02871     {
02872       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
02873       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02874       /* Input capture event */
02875       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
02876       {
02877         HAL_TIM_IC_CaptureCallback(htim);
02878       }
02879       /* Output compare event */
02880       else
02881       {
02882         HAL_TIM_OC_DelayElapsedCallback(htim);
02883         HAL_TIM_PWM_PulseFinishedCallback(htim);
02884       }
02885       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02886     }
02887   }
02888   /* TIM Update event */
02889   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
02890   {
02891     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
02892     {
02893       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
02894       HAL_TIM_PeriodElapsedCallback(htim);
02895     }
02896   }
02897   /* TIM Break input event */
02898   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
02899   {
02900     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02901     {
02902       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02903       HAL_TIMEx_BreakCallback(htim);
02904     }
02905   }
02906   /* TIM Trigger detection event */
02907   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
02908   {
02909     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
02910     {
02911       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
02912       HAL_TIM_TriggerCallback(htim);
02913     }
02914   }
02915   /* TIM commutation event */
02916   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
02917   {
02918     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
02919     {
02920       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
02921       HAL_TIMEx_CommutationCallback(htim);
02922     }
02923   }
02924 }
02925 /**
02926   * @}
02927   */
02928
02929 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
02930  *  @brief      Peripheral Control functions
02931  *
02932 @verbatim
02933   ==============================================================================
02934                    ##### Peripheral Control functions #####
02935   ==============================================================================
02936  [..]
02937    This section provides functions allowing to:
02938    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
02939    (+) Configure External Clock source.
02940    (+) Configure Complementary channels, break features and dead time.
02941    (+) Configure Master and the Slave synchronization.
02942    (+) Configure the DMA Burst Mode.
02943
02944 @endverbatim
02945   * @{
02946   */
02947
02948 /**
02949   * @brief  Initializes the TIM Output Compare Channels according to the specified
02950   *         parameters in the TIM_OC_InitTypeDef.
02951   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
02952   *                the configuration information for TIM module.
02953   * @param  sConfig: TIM Output Compare configuration structure
02954   * @param  Channel: TIM Channels to be enabled.
02955   *          This parameter can be one of the following values:
02956   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02957   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02958   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02959   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02960   * @retval HAL status
02961   */
02962 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
02963 {
02964   /* Check the parameters */
02965   assert_param(IS_TIM_CHANNELS(Channel));
02966   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
02967   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
02968
02969   /* Check input state */
02970   __HAL_LOCK(htim);
02971
02972   htim->State = HAL_TIM_STATE_BUSY;
02973
02974   switch (Channel)
02975   {
02976     case TIM_CHANNEL_1:
02977     {
02978       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02979       /* Configure the TIM Channel 1 in Output Compare */
02980       TIM_OC1_SetConfig(htim->Instance, sConfig);
02981     }
02982     break;
02983
02984     case TIM_CHANNEL_2:
02985     {
02986       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02987       /* Configure the TIM Channel 2 in Output Compare */
02988       TIM_OC2_SetConfig(htim->Instance, sConfig);
02989     }
02990     break;
02991
02992     case TIM_CHANNEL_3:
02993     {
02994        assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
02995       /* Configure the TIM Channel 3 in Output Compare */
02996       TIM_OC3_SetConfig(htim->Instance, sConfig);
02997     }
02998     break;
02999
03000     case TIM_CHANNEL_4:
03001     {
03002       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03003       /* Configure the TIM Channel 4 in Output Compare */
03004       TIM_OC4_SetConfig(htim->Instance, sConfig);
03005     }
03006     break;
03007
03008     default:
03009     break;
03010   }
03011   htim->State = HAL_TIM_STATE_READY;
03012
03013   __HAL_UNLOCK(htim);
03014
03015   return HAL_OK;
03016 }
03017
03018 /**
03019   * @brief  Initializes the TIM Input Capture Channels according to the specified
03020   *         parameters in the TIM_IC_InitTypeDef.
03021   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03022   *                the configuration information for TIM module.
03023   * @param  sConfig: TIM Input Capture configuration structure
03024   * @param  Channel: TIM Channels to be enabled.
03025   *          This parameter can be one of the following values:
03026   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03027   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03028   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03029   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03030   * @retval HAL status
03031   */
03032 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
03033 {
03034   /* Check the parameters */
03035   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03036   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
03037   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
03038   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
03039   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03040
03041   __HAL_LOCK(htim);
03042
03043   htim->State = HAL_TIM_STATE_BUSY;
03044
03045   if (Channel == TIM_CHANNEL_1)
03046   {
03047     /* TI1 Configuration */
03048     TIM_TI1_SetConfig(htim->Instance,
03049                sConfig->ICPolarity,
03050                sConfig->ICSelection,
03051                sConfig->ICFilter);
03052
03053     /* Reset the IC1PSC Bits */
03054     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03055
03056     /* Set the IC1PSC value */
03057     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03058   }
03059   else if (Channel == TIM_CHANNEL_2)
03060   {
03061     /* TI2 Configuration */
03062     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03063
03064     TIM_TI2_SetConfig(htim->Instance,
03065                       sConfig->ICPolarity,
03066                       sConfig->ICSelection,
03067                       sConfig->ICFilter);
03068
03069     /* Reset the IC2PSC Bits */
03070     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03071
03072     /* Set the IC2PSC value */
03073     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
03074   }
03075   else if (Channel == TIM_CHANNEL_3)
03076   {
03077     /* TI3 Configuration */
03078     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03079
03080     TIM_TI3_SetConfig(htim->Instance,
03081                sConfig->ICPolarity,
03082                sConfig->ICSelection,
03083                sConfig->ICFilter);
03084
03085     /* Reset the IC3PSC Bits */
03086     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03087
03088     /* Set the IC3PSC value */
03089     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03090   }
03091   else
03092   {
03093     /* TI4 Configuration */
03094     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03095
03096     TIM_TI4_SetConfig(htim->Instance,
03097                sConfig->ICPolarity,
03098                sConfig->ICSelection,
03099                sConfig->ICFilter);
03100
03101     /* Reset the IC4PSC Bits */
03102     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03103
03104     /* Set the IC4PSC value */
03105     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
03106   }
03107
03108   htim->State = HAL_TIM_STATE_READY;
03109
03110   __HAL_UNLOCK(htim);
03111
03112   return HAL_OK;
03113 }
03114
03115 /**
03116   * @brief  Initializes the TIM PWM  channels according to the specified
03117   *         parameters in the TIM_OC_InitTypeDef.
03118   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03119   *                the configuration information for TIM module.
03120   * @param  sConfig: TIM PWM configuration structure
03121   * @param  Channel: TIM Channels to be enabled.
03122   *          This parameter can be one of the following values:
03123   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03124   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03125   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03126   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03127   * @retval HAL status
03128   */
03129 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
03130 {
03131   __HAL_LOCK(htim);
03132
03133   /* Check the parameters */
03134   assert_param(IS_TIM_CHANNELS(Channel));
03135   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03136   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03137   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03138
03139   htim->State = HAL_TIM_STATE_BUSY;
03140
03141   switch (Channel)
03142   {
03143     case TIM_CHANNEL_1:
03144     {
03145       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03146       /* Configure the Channel 1 in PWM mode */
03147       TIM_OC1_SetConfig(htim->Instance, sConfig);
03148
03149       /* Set the Preload enable bit for channel1 */
03150       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03151
03152       /* Configure the Output Fast mode */
03153       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03154       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03155     }
03156     break;
03157
03158     case TIM_CHANNEL_2:
03159     {
03160       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03161       /* Configure the Channel 2 in PWM mode */
03162       TIM_OC2_SetConfig(htim->Instance, sConfig);
03163
03164       /* Set the Preload enable bit for channel2 */
03165       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03166
03167       /* Configure the Output Fast mode */
03168       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03169       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
03170     }
03171     break;
03172
03173     case TIM_CHANNEL_3:
03174     {
03175       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03176       /* Configure the Channel 3 in PWM mode */
03177       TIM_OC3_SetConfig(htim->Instance, sConfig);
03178
03179       /* Set the Preload enable bit for channel3 */
03180       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03181
03182      /* Configure the Output Fast mode */
03183       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03184       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03185     }
03186     break;
03187
03188     case TIM_CHANNEL_4:
03189     {
03190       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03191       /* Configure the Channel 4 in PWM mode */
03192       TIM_OC4_SetConfig(htim->Instance, sConfig);
03193
03194       /* Set the Preload enable bit for channel4 */
03195       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03196
03197      /* Configure the Output Fast mode */
03198       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03199       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
03200     }
03201     break;
03202
03203     default:
03204     break;
03205   }
03206
03207   htim->State = HAL_TIM_STATE_READY;
03208
03209   __HAL_UNLOCK(htim);
03210
03211   return HAL_OK;
03212 }
03213
03214 /**
03215   * @brief  Initializes the TIM One Pulse Channels according to the specified
03216   *         parameters in the TIM_OnePulse_InitTypeDef.
03217   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03218   *                the configuration information for TIM module.
03219   * @param  sConfig: TIM One Pulse configuration structure
03220   * @param  OutputChannel: TIM Channels to be enabled.
03221   *          This parameter can be one of the following values:
03222   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03223   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03224   * @param  InputChannel: TIM Channels to be enabled.
03225   *          This parameter can be one of the following values:
03226   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03227   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03228   * @retval HAL status
03229   */
03230 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
03231 {
03232   TIM_OC_InitTypeDef temp1;
03233
03234   /* Check the parameters */
03235   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03236   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03237
03238   if(OutputChannel != InputChannel)
03239   {
03240     __HAL_LOCK(htim);
03241
03242     htim->State = HAL_TIM_STATE_BUSY;
03243
03244     /* Extract the Output compare configuration from sConfig structure */
03245     temp1.OCMode = sConfig->OCMode;
03246     temp1.Pulse = sConfig->Pulse;
03247     temp1.OCPolarity = sConfig->OCPolarity;
03248     temp1.OCNPolarity = sConfig->OCNPolarity;
03249     temp1.OCIdleState = sConfig->OCIdleState;
03250     temp1.OCNIdleState = sConfig->OCNIdleState;
03251
03252     switch (OutputChannel)
03253     {
03254       case TIM_CHANNEL_1:
03255       {
03256         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03257
03258         TIM_OC1_SetConfig(htim->Instance, &temp1);
03259       }
03260       break;
03261       case TIM_CHANNEL_2:
03262       {
03263         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03264
03265         TIM_OC2_SetConfig(htim->Instance, &temp1);
03266       }
03267       break;
03268       default:
03269       break;
03270     }
03271     switch (InputChannel)
03272     {
03273       case TIM_CHANNEL_1:
03274       {
03275         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03276
03277         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03278                         sConfig->ICSelection, sConfig->ICFilter);
03279
03280         /* Reset the IC1PSC Bits */
03281         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03282
03283         /* Select the Trigger source */
03284         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03285         htim->Instance->SMCR |= TIM_TS_TI1FP1;
03286
03287         /* Select the Slave Mode */
03288         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03289         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03290       }
03291       break;
03292       case TIM_CHANNEL_2:
03293       {
03294         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03295
03296         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03297                  sConfig->ICSelection, sConfig->ICFilter);
03298
03299         /* Reset the IC2PSC Bits */
03300         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03301
03302         /* Select the Trigger source */
03303         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03304         htim->Instance->SMCR |= TIM_TS_TI2FP2;
03305
03306         /* Select the Slave Mode */
03307         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03308         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03309       }
03310       break;
03311
03312       default:
03313       break;
03314     }
03315
03316     htim->State = HAL_TIM_STATE_READY;
03317
03318     __HAL_UNLOCK(htim);
03319
03320     return HAL_OK;
03321   }
03322   else
03323   {
03324     return HAL_ERROR;
03325   }
03326 }
03327
03328 /**
03329   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03330   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03331   *                the configuration information for TIM module.
03332   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
03333   *         This parameters can be on of the following values:
03334   *            @arg TIM_DMABASE_CR1
03335   *            @arg TIM_DMABASE_CR2
03336   *            @arg TIM_DMABASE_SMCR
03337   *            @arg TIM_DMABASE_DIER
03338   *            @arg TIM_DMABASE_SR
03339   *            @arg TIM_DMABASE_EGR
03340   *            @arg TIM_DMABASE_CCMR1
03341   *            @arg TIM_DMABASE_CCMR2
03342   *            @arg TIM_DMABASE_CCER
03343   *            @arg TIM_DMABASE_CNT
03344   *            @arg TIM_DMABASE_PSC
03345   *            @arg TIM_DMABASE_ARR
03346   *            @arg TIM_DMABASE_RCR
03347   *            @arg TIM_DMABASE_CCR1
03348   *            @arg TIM_DMABASE_CCR2
03349   *            @arg TIM_DMABASE_CCR3
03350   *            @arg TIM_DMABASE_CCR4
03351   *            @arg TIM_DMABASE_BDTR
03352   *            @arg TIM_DMABASE_DCR
03353   * @param  BurstRequestSrc: TIM DMA Request sources.
03354   *         This parameters can be on of the following values:
03355   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03356   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03357   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03358   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03359   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03360   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03361   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03362   * @param  BurstBuffer: The Buffer address.
03363   * @param  BurstLength: DMA Burst length. This parameter can be one value
03364   *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03365   * @retval HAL status
03366   */
03367 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03368                                               uint32_t* BurstBuffer, uint32_t  BurstLength)
03369 {
03370   /* Check the parameters */
03371   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03372   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03373   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03374   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03375
03376   if((htim->State == HAL_TIM_STATE_BUSY))
03377   {
03378      return HAL_BUSY;
03379   }
03380   else if((htim->State == HAL_TIM_STATE_READY))
03381   {
03382     if((BurstBuffer == 0U) && (BurstLength > 0U))
03383     {
03384       return HAL_ERROR;
03385     }
03386     else
03387     {
03388       htim->State = HAL_TIM_STATE_BUSY;
03389     }
03390   }
03391   switch(BurstRequestSrc)
03392   {
03393     case TIM_DMA_UPDATE:
03394     {
03395       /* Set the DMA Period elapsed callback */
03396       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03397
03398       /* Set the DMA error callback */
03399       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03400
03401       /* Enable the DMA Stream */
03402       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03403     }
03404     break;
03405     case TIM_DMA_CC1:
03406     {
03407       /* Set the DMA Period elapsed callback */
03408       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
03409
03410       /* Set the DMA error callback */
03411       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03412
03413       /* Enable the DMA Stream */
03414       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03415     }
03416     break;
03417     case TIM_DMA_CC2:
03418     {
03419       /* Set the DMA Period elapsed callback */
03420       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
03421
03422       /* Set the DMA error callback */
03423       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03424
03425       /* Enable the DMA Stream */
03426       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03427     }
03428     break;
03429     case TIM_DMA_CC3:
03430     {
03431       /* Set the DMA Period elapsed callback */
03432       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
03433
03434       /* Set the DMA error callback */
03435       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03436
03437       /* Enable the DMA Stream */
03438       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03439     }
03440     break;
03441     case TIM_DMA_CC4:
03442     {
03443       /* Set the DMA Period elapsed callback */
03444       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
03445
03446       /* Set the DMA error callback */
03447       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03448
03449       /* Enable the DMA Stream */
03450       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03451     }
03452     break;
03453     case TIM_DMA_COM:
03454     {
03455       /* Set the DMA Period elapsed callback */
03456       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
03457
03458       /* Set the DMA error callback */
03459       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03460
03461       /* Enable the DMA Stream */
03462       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03463     }
03464     break;
03465     case TIM_DMA_TRIGGER:
03466     {
03467       /* Set the DMA Period elapsed callback */
03468       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03469
03470       /* Set the DMA error callback */
03471       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03472
03473       /* Enable the DMA Stream */
03474       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03475     }
03476     break;
03477     default:
03478     break;
03479   }
03480    /* configure the DMA Burst Mode */
03481    htim->Instance->DCR = BurstBaseAddress | BurstLength;
03482
03483    /* Enable the TIM DMA Request */
03484    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03485
03486    htim->State = HAL_TIM_STATE_READY;
03487
03488   /* Return function status */
03489   return HAL_OK;
03490 }
03491
03492 /**
03493   * @brief  Stops the TIM DMA Burst mode
03494   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03495   *                the configuration information for TIM module.
03496   * @param  BurstRequestSrc: TIM DMA Request sources to disable
03497   * @retval HAL status
03498   */
03499 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03500 {
03501   /* Check the parameters */
03502   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03503
03504   /* Abort the DMA transfer (at least disable the DMA channel) */
03505   switch(BurstRequestSrc)
03506   {
03507     case TIM_DMA_UPDATE:
03508     {
03509       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03510     }
03511     break;
03512     case TIM_DMA_CC1:
03513     {
03514       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03515     }
03516     break;
03517     case TIM_DMA_CC2:
03518     {
03519       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03520     }
03521     break;
03522     case TIM_DMA_CC3:
03523     {
03524       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03525     }
03526     break;
03527     case TIM_DMA_CC4:
03528     {
03529       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03530     }
03531     break;
03532     case TIM_DMA_COM:
03533     {
03534       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03535     }
03536     break;
03537     case TIM_DMA_TRIGGER:
03538     {
03539       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03540     }
03541     break;
03542     default:
03543     break;
03544   }
03545
03546   /* Disable the TIM Update DMA request */
03547   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03548
03549   /* Return function status */
03550   return HAL_OK;
03551 }
03552
03553 /**
03554   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
03555   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03556   *                the configuration information for TIM module.
03557   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
03558   *         This parameters can be on of the following values:
03559   *            @arg TIM_DMABASE_CR1
03560   *            @arg TIM_DMABASE_CR2
03561   *            @arg TIM_DMABASE_SMCR
03562   *            @arg TIM_DMABASE_DIER
03563   *            @arg TIM_DMABASE_SR
03564   *            @arg TIM_DMABASE_EGR
03565   *            @arg TIM_DMABASE_CCMR1
03566   *            @arg TIM_DMABASE_CCMR2
03567   *            @arg TIM_DMABASE_CCER
03568   *            @arg TIM_DMABASE_CNT
03569   *            @arg TIM_DMABASE_PSC
03570   *            @arg TIM_DMABASE_ARR
03571   *            @arg TIM_DMABASE_RCR
03572   *            @arg TIM_DMABASE_CCR1
03573   *            @arg TIM_DMABASE_CCR2
03574   *            @arg TIM_DMABASE_CCR3
03575   *            @arg TIM_DMABASE_CCR4
03576   *            @arg TIM_DMABASE_BDTR
03577   *            @arg TIM_DMABASE_DCR
03578   * @param  BurstRequestSrc: TIM DMA Request sources.
03579   *         This parameters can be on of the following values:
03580   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03581   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03582   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03583   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03584   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03585   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03586   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03587   * @param  BurstBuffer: The Buffer address.
03588   * @param  BurstLength: DMA Burst length. This parameter can be one value
03589   *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03590   * @retval HAL status
03591   */
03592 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03593                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
03594 {
03595   /* Check the parameters */
03596   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03597   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03598   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03599   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03600
03601   if((htim->State == HAL_TIM_STATE_BUSY))
03602   {
03603      return HAL_BUSY;
03604   }
03605   else if((htim->State == HAL_TIM_STATE_READY))
03606   {
03607     if((BurstBuffer == 0U) && (BurstLength > 0U))
03608     {
03609       return HAL_ERROR;
03610     }
03611     else
03612     {
03613       htim->State = HAL_TIM_STATE_BUSY;
03614     }
03615   }
03616   switch(BurstRequestSrc)
03617   {
03618     case TIM_DMA_UPDATE:
03619     {
03620       /* Set the DMA Period elapsed callback */
03621       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03622
03623       /* Set the DMA error callback */
03624       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03625
03626       /* Enable the DMA Stream */
03627        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03628     }
03629     break;
03630     case TIM_DMA_CC1:
03631     {
03632       /* Set the DMA Period elapsed callback */
03633       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03634
03635       /* Set the DMA error callback */
03636       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03637
03638       /* Enable the DMA Stream */
03639       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03640     }
03641     break;
03642     case TIM_DMA_CC2:
03643     {
03644       /* Set the DMA Period elapsed callback */
03645       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03646
03647       /* Set the DMA error callback */
03648       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03649
03650       /* Enable the DMA Stream */
03651       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03652     }
03653     break;
03654     case TIM_DMA_CC3:
03655     {
03656       /* Set the DMA Period elapsed callback */
03657       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
03658
03659       /* Set the DMA error callback */
03660       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03661
03662       /* Enable the DMA Stream */
03663       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03664     }
03665     break;
03666     case TIM_DMA_CC4:
03667     {
03668       /* Set the DMA Period elapsed callback */
03669       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
03670
03671       /* Set the DMA error callback */
03672       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03673
03674       /* Enable the DMA Stream */
03675       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03676     }
03677     break;
03678     case TIM_DMA_COM:
03679     {
03680       /* Set the DMA Period elapsed callback */
03681       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
03682
03683       /* Set the DMA error callback */
03684       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03685
03686       /* Enable the DMA Stream */
03687       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03688     }
03689     break;
03690     case TIM_DMA_TRIGGER:
03691     {
03692       /* Set the DMA Period elapsed callback */
03693       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03694
03695       /* Set the DMA error callback */
03696       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03697
03698       /* Enable the DMA Stream */
03699       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
03700     }
03701     break;
03702     default:
03703     break;
03704   }
03705
03706   /* configure the DMA Burst Mode */
03707   htim->Instance->DCR = BurstBaseAddress | BurstLength;
03708
03709   /* Enable the TIM DMA Request */
03710   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03711
03712   htim->State = HAL_TIM_STATE_READY;
03713
03714   /* Return function status */
03715   return HAL_OK;
03716 }
03717
03718 /**
03719   * @brief  Stop the DMA burst reading
03720   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03721   *                the configuration information for TIM module.
03722   * @param  BurstRequestSrc: TIM DMA Request sources to disable.
03723   * @retval HAL status
03724   */
03725 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03726 {
03727   /* Check the parameters */
03728   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03729
03730   /* Abort the DMA transfer (at least disable the DMA channel) */
03731   switch(BurstRequestSrc)
03732   {
03733     case TIM_DMA_UPDATE:
03734     {
03735       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03736     }
03737     break;
03738     case TIM_DMA_CC1:
03739     {
03740       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03741     }
03742     break;
03743     case TIM_DMA_CC2:
03744     {
03745       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03746     }
03747     break;
03748     case TIM_DMA_CC3:
03749     {
03750       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03751     }
03752     break;
03753     case TIM_DMA_CC4:
03754     {
03755       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03756     }
03757     break;
03758     case TIM_DMA_COM:
03759     {
03760       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03761     }
03762     break;
03763     case TIM_DMA_TRIGGER:
03764     {
03765       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03766     }
03767     break;
03768     default:
03769     break;
03770   }
03771
03772   /* Disable the TIM Update DMA request */
03773   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03774
03775   /* Return function status */
03776   return HAL_OK;
03777 }
03778
03779 /**
03780   * @brief  Generate a software event
03781   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03782   *                the configuration information for TIM module.
03783   * @param  EventSource: specifies the event source.
03784   *          This parameter can be one of the following values:
03785   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
03786   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
03787   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
03788   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
03789   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
03790   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
03791   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
03792   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
03793   * @note   TIM6 and TIM7 can only generate an update event.
03794   * @note   TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
03795   * @retval HAL status
03796   */
03797
03798 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
03799 {
03800   /* Check the parameters */
03801   assert_param(IS_TIM_INSTANCE(htim->Instance));
03802   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
03803
03804   /* Process Locked */
03805   __HAL_LOCK(htim);
03806
03807   /* Change the TIM state */
03808   htim->State = HAL_TIM_STATE_BUSY;
03809
03810   /* Set the event sources */
03811   htim->Instance->EGR = EventSource;
03812
03813   /* Change the TIM state */
03814   htim->State = HAL_TIM_STATE_READY;
03815
03816   __HAL_UNLOCK(htim);
03817
03818   /* Return function status */
03819   return HAL_OK;
03820 }
03821
03822 /**
03823   * @brief  Configures the OCRef clear feature
03824   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03825   *                the configuration information for TIM module.
03826   * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
03827   *         contains the OCREF clear feature and parameters for the TIM peripheral.
03828   * @param  Channel: specifies the TIM Channel.
03829   *          This parameter can be one of the following values:
03830   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03831   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03832   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03833   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03834   * @retval HAL status
03835   */
03836 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
03837 {
03838   /* Check the parameters */
03839   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03840   assert_param(IS_TIM_CHANNELS(Channel));
03841   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
03842   assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
03843   assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
03844   assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
03845
03846   /* Process Locked */
03847   __HAL_LOCK(htim);
03848
03849   htim->State = HAL_TIM_STATE_BUSY;
03850
03851   if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
03852   {
03853     TIM_ETR_SetConfig(htim->Instance,
03854                       sClearInputConfig->ClearInputPrescaler,
03855                       sClearInputConfig->ClearInputPolarity,
03856                       sClearInputConfig->ClearInputFilter);
03857   }
03858
03859   switch (Channel)
03860   {
03861     case TIM_CHANNEL_1:
03862     {
03863       if(sClearInputConfig->ClearInputState != RESET)
03864       {
03865         /* Enable the Ocref clear feature for Channel 1 */
03866         htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
03867       }
03868       else
03869       {
03870         /* Disable the Ocref clear feature for Channel 1 */
03871         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
03872       }
03873     }
03874     break;
03875     case TIM_CHANNEL_2:
03876     {
03877       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03878       if(sClearInputConfig->ClearInputState != RESET)
03879       {
03880         /* Enable the Ocref clear feature for Channel 2 */
03881         htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
03882       }
03883       else
03884       {
03885         /* Disable the Ocref clear feature for Channel 2 */
03886         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
03887       }
03888     }
03889     break;
03890     case TIM_CHANNEL_3:
03891     {
03892       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03893       if(sClearInputConfig->ClearInputState != RESET)
03894       {
03895         /* Enable the Ocref clear feature for Channel 3 */
03896         htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
03897       }
03898       else
03899       {
03900         /* Disable the Ocref clear feature for Channel 3 */
03901         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
03902       }
03903     }
03904     break;
03905     case TIM_CHANNEL_4:
03906     {
03907       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03908       if(sClearInputConfig->ClearInputState != RESET)
03909       {
03910         /* Enable the Ocref clear feature for Channel 4 */
03911         htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
03912       }
03913       else
03914       {
03915         /* Disable the Ocref clear feature for Channel 4 */
03916         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
03917       }
03918     }
03919     break;
03920     default:
03921     break;
03922   }
03923
03924   htim->State = HAL_TIM_STATE_READY;
03925
03926   __HAL_UNLOCK(htim);
03927
03928   return HAL_OK;
03929 }
03930
03931 /**
03932   * @brief   Configures the clock source to be used
03933   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
03934   *                the configuration information for TIM module.
03935   * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
03936   *         contains the clock source information for the TIM peripheral.
03937   * @retval HAL status
03938   */
03939 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
03940 {
03941   uint32_t tmpsmcr = 0U;
03942
03943   /* Process Locked */
03944   __HAL_LOCK(htim);
03945
03946   htim->State = HAL_TIM_STATE_BUSY;
03947
03948   /* Check the parameters */
03949   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
03950
03951   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
03952   tmpsmcr = htim->Instance->SMCR;
03953   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
03954   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03955   htim->Instance->SMCR = tmpsmcr;
03956
03957   switch (sClockSourceConfig->ClockSource)
03958   {
03959     case TIM_CLOCKSOURCE_INTERNAL:
03960     {
03961       assert_param(IS_TIM_INSTANCE(htim->Instance));
03962
03963       /* Disable slave mode to clock the prescaler directly with the internal clock */
03964       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03965     }
03966     break;
03967
03968     case TIM_CLOCKSOURCE_ETRMODE1:
03969     {
03970       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
03971
03972       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03973       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
03974       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03975
03976       /* Configure the ETR Clock source */
03977       TIM_ETR_SetConfig(htim->Instance,
03978                         sClockSourceConfig->ClockPrescaler,
03979                         sClockSourceConfig->ClockPolarity,
03980                         sClockSourceConfig->ClockFilter);
03981       /* Get the TIMx SMCR register value */
03982       tmpsmcr = htim->Instance->SMCR;
03983       /* Reset the SMS and TS Bits */
03984       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
03985       /* Select the External clock mode1 and the ETRF trigger */
03986       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
03987       /* Write to TIMx SMCR */
03988       htim->Instance->SMCR = tmpsmcr;
03989     }
03990     break;
03991
03992     case TIM_CLOCKSOURCE_ETRMODE2:
03993     {
03994       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
03995
03996       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03997       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
03998       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03999
04000       /* Configure the ETR Clock source */
04001       TIM_ETR_SetConfig(htim->Instance,
04002                         sClockSourceConfig->ClockPrescaler,
04003                         sClockSourceConfig->ClockPolarity,
04004                         sClockSourceConfig->ClockFilter);
04005       /* Enable the External clock mode2 */
04006       htim->Instance->SMCR |= TIM_SMCR_ECE;
04007     }
04008     break;
04009
04010     case TIM_CLOCKSOURCE_TI1:
04011     {
04012       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04013
04014       /* Check TI1 input conditioning related parameters */
04015       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04016       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04017
04018       TIM_TI1_ConfigInputStage(htim->Instance,
04019                         sClockSourceConfig->ClockPolarity,
04020                         sClockSourceConfig->ClockFilter);
04021       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
04022     }
04023     break;
04024     case TIM_CLOCKSOURCE_TI2:
04025     {
04026       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04027
04028       /* Check TI1 input conditioning related parameters */
04029       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04030       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04031
04032       TIM_TI2_ConfigInputStage(htim->Instance,
04033                         sClockSourceConfig->ClockPolarity,
04034                         sClockSourceConfig->ClockFilter);
04035       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04036     }
04037     break;
04038     case TIM_CLOCKSOURCE_TI1ED:
04039     {
04040       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04041
04042       /* Check TI1 input conditioning related parameters */
04043       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04044       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04045
04046       TIM_TI1_ConfigInputStage(htim->Instance,
04047                         sClockSourceConfig->ClockPolarity,
04048                         sClockSourceConfig->ClockFilter);
04049       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04050     }
04051     break;
04052     case TIM_CLOCKSOURCE_ITR0:
04053     {
04054       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04055       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
04056     }
04057     break;
04058     case TIM_CLOCKSOURCE_ITR1:
04059     {
04060       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04061       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
04062     }
04063     break;
04064     case TIM_CLOCKSOURCE_ITR2:
04065     {
04066       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04067       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
04068     }
04069     break;
04070     case TIM_CLOCKSOURCE_ITR3:
04071     {
04072       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04073       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
04074     }
04075     break;
04076
04077     default:
04078     break;
04079   }
04080   htim->State = HAL_TIM_STATE_READY;
04081
04082   __HAL_UNLOCK(htim);
04083
04084   return HAL_OK;
04085 }
04086
04087 /**
04088   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04089   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04090   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04091   *                the configuration information for TIM module.
04092   * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
04093   *         output of a XOR gate.
04094   *         This parameter can be one of the following values:
04095   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04096   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04097   *            pins are connected to the TI1 input (XOR combination)
04098   * @retval HAL status
04099   */
04100 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04101 {
04102   uint32_t tmpcr2 = 0U;
04103
04104   /* Check the parameters */
04105   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04106   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04107
04108   /* Get the TIMx CR2 register value */
04109   tmpcr2 = htim->Instance->CR2;
04110
04111   /* Reset the TI1 selection */
04112   tmpcr2 &= ~TIM_CR2_TI1S;
04113
04114   /* Set the TI1 selection */
04115   tmpcr2 |= TI1_Selection;
04116
04117   /* Write to TIMxCR2 */
04118   htim->Instance->CR2 = tmpcr2;
04119
04120   return HAL_OK;
04121 }
04122
04123 /**
04124   * @brief  Configures the TIM in Slave mode
04125   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04126   *                the configuration information for TIM module.
04127   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04128   *         contains the selected trigger (internal trigger input, filtered
04129   *         timer input or external trigger input) and the ) and the Slave
04130   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04131   * @retval HAL status
04132   */
04133 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
04134 {
04135   /* Check the parameters */
04136   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04137   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04138   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04139
04140   __HAL_LOCK(htim);
04141
04142   htim->State = HAL_TIM_STATE_BUSY;
04143
04144   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04145
04146   /* Disable Trigger Interrupt */
04147   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04148
04149   /* Disable Trigger DMA request */
04150   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04151
04152   htim->State = HAL_TIM_STATE_READY;
04153
04154   __HAL_UNLOCK(htim);
04155
04156   return HAL_OK;
04157 }
04158
04159 /**
04160   * @brief  Configures the TIM in Slave mode in interrupt mode
04161   * @param  htim: TIM handle.
04162   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04163   *         contains the selected trigger (internal trigger input, filtered
04164   *         timer input or external trigger input) and the ) and the Slave
04165   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04166   * @retval HAL status
04167   */
04168 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
04169                                                         TIM_SlaveConfigTypeDef * sSlaveConfig)
04170 {
04171   /* Check the parameters */
04172   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04173   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04174   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04175
04176   __HAL_LOCK(htim);
04177
04178   htim->State = HAL_TIM_STATE_BUSY;
04179
04180   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04181
04182   /* Enable Trigger Interrupt */
04183   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04184
04185   /* Disable Trigger DMA request */
04186   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04187
04188   htim->State = HAL_TIM_STATE_READY;
04189
04190   __HAL_UNLOCK(htim);
04191
04192   return HAL_OK;
04193 }
04194
04195 /**
04196   * @brief  Read the captured value from Capture Compare unit
04197   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04198   *                the configuration information for TIM module.
04199   * @param  Channel: TIM Channels to be enabled.
04200   *          This parameter can be one of the following values:
04201   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04202   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04203   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04204   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04205   * @retval Captured value
04206   */
04207 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04208 {
04209   uint32_t tmpreg = 0U;
04210
04211   __HAL_LOCK(htim);
04212
04213   switch (Channel)
04214   {
04215     case TIM_CHANNEL_1:
04216     {
04217       /* Check the parameters */
04218       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04219
04220       /* Return the capture 1 value */
04221       tmpreg = htim->Instance->CCR1;
04222
04223       break;
04224     }
04225     case TIM_CHANNEL_2:
04226     {
04227       /* Check the parameters */
04228       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04229
04230       /* Return the capture 2 value */
04231       tmpreg = htim->Instance->CCR2;
04232
04233       break;
04234     }
04235
04236     case TIM_CHANNEL_3:
04237     {
04238       /* Check the parameters */
04239       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04240
04241       /* Return the capture 3 value */
04242       tmpreg = htim->Instance->CCR3;
04243
04244       break;
04245     }
04246
04247     case TIM_CHANNEL_4:
04248     {
04249       /* Check the parameters */
04250       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04251
04252       /* Return the capture 4 value */
04253       tmpreg = htim->Instance->CCR4;
04254
04255       break;
04256     }
04257
04258     default:
04259     break;
04260   }
04261
04262   __HAL_UNLOCK(htim);
04263   return tmpreg;
04264 }
04265 /**
04266   * @}
04267   */
04268
04269 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04270  *  @brief    TIM Callbacks functions
04271  *
04272 @verbatim
04273   ==============================================================================
04274                         ##### TIM Callbacks functions #####
04275   ==============================================================================
04276  [..]
04277    This section provides TIM callback functions:
04278    (+) Timer Period elapsed callback
04279    (+) Timer Output Compare callback
04280    (+) Timer Input capture callback
04281    (+) Timer Trigger callback
04282    (+) Timer Error callback
04283
04284 @endverbatim
04285   * @{
04286   */
04287
04288 /**
04289   * @brief  Period elapsed callback in non blocking mode
04290   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04291   *                the configuration information for TIM module.
04292   * @retval None
04293   */
04294 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04295 {
04296   /* Prevent unused argument(s) compilation warning */
04297   UNUSED(htim);
04298   /* NOTE : This function Should not be modified, when the callback is needed,
04299             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04300    */
04301 }
04302
04303 /**
04304   * @brief  Output Compare callback in non blocking mode
04305   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04306   *                the configuration information for TIM module.
04307   * @retval None
04308   */
04309 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
04310 {
04311   /* Prevent unused argument(s) compilation warning */
04312   UNUSED(htim);
04313   /* NOTE : This function Should not be modified, when the callback is needed,
04314             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
04315    */
04316 }
04317
04318 /**
04319   * @brief  Input Capture callback in non blocking mode
04320   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04321   *                the configuration information for TIM module.
04322   * @retval None
04323   */
04324 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
04325 {
04326   /* Prevent unused argument(s) compilation warning */
04327   UNUSED(htim);
04328   /* NOTE : This function Should not be modified, when the callback is needed,
04329             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
04330    */
04331 }
04332
04333 /**
04334   * @brief  PWM Pulse finished callback in non blocking mode
04335   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04336   *                the configuration information for TIM module.
04337   * @retval None
04338   */
04339 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
04340 {
04341   /* Prevent unused argument(s) compilation warning */
04342   UNUSED(htim);
04343   /* NOTE : This function Should not be modified, when the callback is needed,
04344             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
04345    */
04346 }
04347
04348 /**
04349   * @brief  Hall Trigger detection callback in non blocking mode
04350   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04351   *                the configuration information for TIM module.
04352   * @retval None
04353   */
04354 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
04355 {
04356   /* Prevent unused argument(s) compilation warning */
04357   UNUSED(htim);
04358   /* NOTE : This function Should not be modified, when the callback is needed,
04359             the HAL_TIM_TriggerCallback could be implemented in the user file
04360    */
04361 }
04362
04363 /**
04364   * @brief  Timer error callback in non blocking mode
04365   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04366   *                the configuration information for TIM module.
04367   * @retval None
04368   */
04369 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
04370 {
04371   /* Prevent unused argument(s) compilation warning */
04372   UNUSED(htim);
04373   /* NOTE : This function Should not be modified, when the callback is needed,
04374             the HAL_TIM_ErrorCallback could be implemented in the user file
04375    */
04376 }
04377 /**
04378   * @}
04379   */
04380
04381 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
04382  *  @brief   Peripheral State functions
04383  *
04384 @verbatim
04385   ==============================================================================
04386                         ##### Peripheral State functions #####
04387   ==============================================================================
04388   [..]
04389     This subsection permits to get in run-time the status of the peripheral
04390     and the data flow.
04391
04392 @endverbatim
04393   * @{
04394   */
04395
04396 /**
04397   * @brief  Return the TIM Base state
04398   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04399   *                the configuration information for TIM module.
04400   * @retval HAL state
04401   */
04402 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
04403 {
04404   return htim->State;
04405 }
04406
04407 /**
04408   * @brief  Return the TIM OC state
04409   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04410   *                the configuration information for TIM module.
04411   * @retval HAL state
04412   */
04413 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
04414 {
04415   return htim->State;
04416 }
04417
04418 /**
04419   * @brief  Return the TIM PWM state
04420   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04421   *                the configuration information for TIM module.
04422   * @retval HAL state
04423   */
04424 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
04425 {
04426   return htim->State;
04427 }
04428
04429 /**
04430   * @brief  Return the TIM Input Capture state
04431   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04432   *                the configuration information for TIM module.
04433   * @retval HAL state
04434   */
04435 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
04436 {
04437   return htim->State;
04438 }
04439
04440 /**
04441   * @brief  Return the TIM One Pulse Mode state
04442   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04443   *                the configuration information for TIM module.
04444   * @retval HAL state
04445   */
04446 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
04447 {
04448   return htim->State;
04449 }
04450
04451 /**
04452   * @brief  Return the TIM Encoder Mode state
04453   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04454   *                the configuration information for TIM module.
04455   * @retval HAL state
04456   */
04457 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
04458 {
04459   return htim->State;
04460 }
04461 /**
04462   * @}
04463   */
04464
04465 /**
04466   * @brief  Time Base configuration
04467   * @param  TIMx: TIM peripheral
04468   * @param  Structure: pointer on TIM Time Base required parameters
04469   * @retval None
04470   */
04471 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
04472 {
04473   uint32_t tmpcr1 = 0U;
04474   tmpcr1 = TIMx->CR1;
04475
04476   /* Set TIM Time Base Unit parameters ---------------------------------------*/
04477   if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
04478   {
04479     /* Select the Counter Mode */
04480     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
04481     tmpcr1 |= Structure->CounterMode;
04482   }
04483
04484   if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
04485   {
04486     /* Set the clock division */
04487     tmpcr1 &= ~TIM_CR1_CKD;
04488     tmpcr1 |= (uint32_t)Structure->ClockDivision;
04489   }
04490
04491   TIMx->CR1 = tmpcr1;
04492
04493   /* Set the Auto-reload value */
04494   TIMx->ARR = (uint32_t)Structure->Period ;
04495
04496   /* Set the Prescaler value */
04497   TIMx->PSC = (uint32_t)Structure->Prescaler;
04498
04499   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04500   {
04501     /* Set the Repetition Counter value */
04502     TIMx->RCR = Structure->RepetitionCounter;
04503   }
04504
04505   /* Generate an update event to reload the Prescaler
04506      and the repetition counter(only for TIM1 and TIM8) value immediately */
04507   TIMx->EGR = TIM_EGR_UG;
04508 }
04509
04510 /**
04511   * @brief  Configure the TI1 as Input.
04512   * @param  TIMx to select the TIM peripheral.
04513   * @param  TIM_ICPolarity : The Input Polarity.
04514   *          This parameter can be one of the following values:
04515   *            @arg TIM_ICPolarity_Rising
04516   *            @arg TIM_ICPolarity_Falling
04517   *            @arg TIM_ICPolarity_BothEdge
04518   * @param  TIM_ICSelection: specifies the input to be used.
04519   *          This parameter can be one of the following values:
04520   *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
04521   *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
04522   *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
04523   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
04524   *          This parameter must be a value between 0x00 and 0x0F.
04525   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
04526   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
04527   *        protected against un-initialized filter and polarity values.
04528   * @retval None
04529   */
04530 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
04531                        uint32_t TIM_ICFilter)
04532 {
04533   uint32_t tmpccmr1 = 0U;
04534   uint32_t tmpccer = 0U;
04535
04536   /* Disable the Channel 1: Reset the CC1E Bit */
04537   TIMx->CCER &= ~TIM_CCER_CC1E;
04538   tmpccmr1 = TIMx->CCMR1;
04539   tmpccer = TIMx->CCER;
04540
04541   /* Select the Input */
04542   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
04543   {
04544     tmpccmr1 &= ~TIM_CCMR1_CC1S;
04545     tmpccmr1 |= TIM_ICSelection;
04546   }
04547   else
04548   {
04549     tmpccmr1 &= ~TIM_CCMR1_CC1S;
04550     tmpccmr1 |= TIM_CCMR1_CC1S_0;
04551   }
04552
04553   /* Set the filter */
04554   tmpccmr1 &= ~TIM_CCMR1_IC1F;
04555   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
04556
04557   /* Select the Polarity and set the CC1E Bit */
04558   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
04559   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
04560
04561   /* Write to TIMx CCMR1 and CCER registers */
04562   TIMx->CCMR1 = tmpccmr1;
04563   TIMx->CCER = tmpccer;
04564 }
04565
04566 /**
04567   * @brief  Time Output Compare 2 configuration
04568   * @param  TIMx to select the TIM peripheral
04569   * @param  OC_Config: The output configuration structure
04570   * @retval None
04571   */
04572 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04573 {
04574   uint32_t tmpccmrx = 0U;
04575   uint32_t tmpccer = 0U;
04576   uint32_t tmpcr2 = 0U;
04577
04578   /* Disable the Channel 2: Reset the CC2E Bit */
04579   TIMx->CCER &= ~TIM_CCER_CC2E;
04580
04581   /* Get the TIMx CCER register value */
04582   tmpccer = TIMx->CCER;
04583   /* Get the TIMx CR2 register value */
04584   tmpcr2 = TIMx->CR2;
04585
04586   /* Get the TIMx CCMR1 register value */
04587   tmpccmrx = TIMx->CCMR1;
04588
04589   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04590   tmpccmrx &= ~TIM_CCMR1_OC2M;
04591   tmpccmrx &= ~TIM_CCMR1_CC2S;
04592
04593   /* Select the Output Compare Mode */
04594   tmpccmrx |= (OC_Config->OCMode << 8U);
04595
04596   /* Reset the Output Polarity level */
04597   tmpccer &= ~TIM_CCER_CC2P;
04598   /* Set the Output Compare Polarity */
04599   tmpccer |= (OC_Config->OCPolarity << 4U);
04600
04601   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04602   {
04603     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04604
04605     /* Reset the Output N Polarity level */
04606     tmpccer &= ~TIM_CCER_CC2NP;
04607     /* Set the Output N Polarity */
04608     tmpccer |= (OC_Config->OCNPolarity << 4U);
04609     /* Reset the Output N State */
04610     tmpccer &= ~TIM_CCER_CC2NE;
04611
04612     /* Reset the Output Compare and Output Compare N IDLE State */
04613     tmpcr2 &= ~TIM_CR2_OIS2;
04614     tmpcr2 &= ~TIM_CR2_OIS2N;
04615     /* Set the Output Idle state */
04616     tmpcr2 |= (OC_Config->OCIdleState << 2U);
04617     /* Set the Output N Idle state */
04618     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
04619   }
04620   /* Write to TIMx CR2 */
04621   TIMx->CR2 = tmpcr2;
04622
04623   /* Write to TIMx CCMR1 */
04624   TIMx->CCMR1 = tmpccmrx;
04625
04626   /* Set the Capture Compare Register value */
04627   TIMx->CCR2 = OC_Config->Pulse;
04628
04629   /* Write to TIMx CCER */
04630   TIMx->CCER = tmpccer;
04631 }
04632
04633 /**
04634   * @brief  TIM DMA Delay Pulse complete callback.
04635   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04636   *               the configuration information for the specified DMA module.
04637   * @retval None
04638   */
04639 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
04640 {
04641   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04642
04643   htim->State= HAL_TIM_STATE_READY;
04644
04645   if(hdma == htim->hdma[TIM_DMA_ID_CC1])
04646   {
04647     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04648   }
04649   else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
04650   {
04651     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04652   }
04653   else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
04654   {
04655     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04656   }
04657   else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
04658   {
04659     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04660   }
04661
04662   HAL_TIM_PWM_PulseFinishedCallback(htim);
04663
04664   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04665 }
04666
04667 /**
04668   * @brief  TIM DMA error callback
04669   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04670   *                the configuration information for the specified DMA module.
04671   * @retval None
04672   */
04673 void TIM_DMAError(DMA_HandleTypeDef *hdma)
04674 {
04675   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04676
04677   htim->State= HAL_TIM_STATE_READY;
04678
04679   HAL_TIM_ErrorCallback(htim);
04680 }
04681
04682 /**
04683   * @brief  TIM DMA Capture complete callback.
04684   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04685   *                the configuration information for the specified DMA module.
04686   * @retval None
04687   */
04688 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
04689 {
04690   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04691
04692   htim->State= HAL_TIM_STATE_READY;
04693
04694   if(hdma == htim->hdma[TIM_DMA_ID_CC1])
04695   {
04696     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04697   }
04698   else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
04699   {
04700     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04701   }
04702   else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
04703   {
04704     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04705   }
04706   else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
04707   {
04708     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04709   }
04710
04711   HAL_TIM_IC_CaptureCallback(htim);
04712
04713   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04714 }
04715
04716 /**
04717   * @brief  Enables or disables the TIM Capture Compare Channel x.
04718   * @param  TIMx to select the TIM peripheral
04719   * @param  Channel: specifies the TIM Channel
04720   *          This parameter can be one of the following values:
04721   *            @arg TIM_Channel_1: TIM Channel 1
04722   *            @arg TIM_Channel_2: TIM Channel 2
04723   *            @arg TIM_Channel_3: TIM Channel 3
04724   *            @arg TIM_Channel_4: TIM Channel 4
04725   * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
04726   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
04727   * @retval None
04728   */
04729 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
04730 {
04731   uint32_t tmp = 0U;
04732
04733   /* Check the parameters */
04734   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
04735   assert_param(IS_TIM_CHANNELS(Channel));
04736
04737   tmp = TIM_CCER_CC1E << Channel;
04738
04739   /* Reset the CCxE Bit */
04740   TIMx->CCER &= ~tmp;
04741
04742   /* Set or reset the CCxE Bit */
04743   TIMx->CCER |= (uint32_t)(ChannelState << Channel);
04744 }
04745
04746 /**
04747   * @brief  TIM DMA Period Elapse complete callback.
04748   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04749   *                the configuration information for the specified DMA module.
04750   * @retval None
04751   */
04752 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
04753 {
04754   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04755
04756   htim->State= HAL_TIM_STATE_READY;
04757
04758   HAL_TIM_PeriodElapsedCallback(htim);
04759 }
04760
04761 /**
04762   * @brief  TIM DMA Trigger callback.
04763   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
04764   *                the configuration information for the specified DMA module.
04765   * @retval None
04766   */
04767 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
04768 {
04769   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04770
04771   htim->State= HAL_TIM_STATE_READY;
04772
04773   HAL_TIM_TriggerCallback(htim);
04774 }
04775
04776 /**
04777   * @brief  Time Output Compare 1 configuration
04778   * @param  TIMx to select the TIM peripheral
04779   * @param  OC_Config: The output configuration structure
04780   * @retval None
04781   */
04782 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04783 {
04784   uint32_t tmpccmrx = 0U;
04785   uint32_t tmpccer = 0U;
04786   uint32_t tmpcr2 = 0U;
04787
04788   /* Disable the Channel 1: Reset the CC1E Bit */
04789   TIMx->CCER &= ~TIM_CCER_CC1E;
04790
04791   /* Get the TIMx CCER register value */
04792   tmpccer = TIMx->CCER;
04793   /* Get the TIMx CR2 register value */
04794   tmpcr2 = TIMx->CR2;
04795
04796   /* Get the TIMx CCMR1 register value */
04797   tmpccmrx = TIMx->CCMR1;
04798
04799   /* Reset the Output Compare Mode Bits */
04800   tmpccmrx &= ~TIM_CCMR1_OC1M;
04801   tmpccmrx &= ~TIM_CCMR1_CC1S;
04802   /* Select the Output Compare Mode */
04803   tmpccmrx |= OC_Config->OCMode;
04804
04805   /* Reset the Output Polarity level */
04806   tmpccer &= ~TIM_CCER_CC1P;
04807   /* Set the Output Compare Polarity */
04808   tmpccer |= OC_Config->OCPolarity;
04809
04810
04811   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04812   {
04813     /* Reset the Output N Polarity level */
04814     tmpccer &= ~TIM_CCER_CC1NP;
04815     /* Set the Output N Polarity */
04816     tmpccer |= OC_Config->OCNPolarity;
04817     /* Reset the Output N State */
04818     tmpccer &= ~TIM_CCER_CC1NE;
04819
04820     /* Reset the Output Compare and Output Compare N IDLE State */
04821     tmpcr2 &= ~TIM_CR2_OIS1;
04822     tmpcr2 &= ~TIM_CR2_OIS1N;
04823     /* Set the Output Idle state */
04824     tmpcr2 |= OC_Config->OCIdleState;
04825     /* Set the Output N Idle state */
04826     tmpcr2 |= OC_Config->OCNIdleState;
04827   }
04828   /* Write to TIMx CR2 */
04829   TIMx->CR2 = tmpcr2;
04830
04831   /* Write to TIMx CCMR1 */
04832   TIMx->CCMR1 = tmpccmrx;
04833
04834   /* Set the Capture Compare Register value */
04835   TIMx->CCR1 = OC_Config->Pulse;
04836
04837   /* Write to TIMx CCER */
04838   TIMx->CCER = tmpccer;
04839 }
04840
04841 /**
04842   * @brief  Time Output Compare 3 configuration
04843   * @param  TIMx to select the TIM peripheral
04844   * @param  OC_Config: The output configuration structure
04845   * @retval None
04846   */
04847 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04848 {
04849   uint32_t tmpccmrx = 0U;
04850   uint32_t tmpccer = 0U;
04851   uint32_t tmpcr2 = 0U;
04852
04853   /* Disable the Channel 3: Reset the CC2E Bit */
04854   TIMx->CCER &= ~TIM_CCER_CC3E;
04855
04856   /* Get the TIMx CCER register value */
04857   tmpccer = TIMx->CCER;
04858   /* Get the TIMx CR2 register value */
04859   tmpcr2 = TIMx->CR2;
04860
04861   /* Get the TIMx CCMR2 register value */
04862   tmpccmrx = TIMx->CCMR2;
04863
04864   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04865   tmpccmrx &= ~TIM_CCMR2_OC3M;
04866   tmpccmrx &= ~TIM_CCMR2_CC3S;
04867   /* Select the Output Compare Mode */
04868   tmpccmrx |= OC_Config->OCMode;
04869
04870   /* Reset the Output Polarity level */
04871   tmpccer &= ~TIM_CCER_CC3P;
04872   /* Set the Output Compare Polarity */
04873   tmpccer |= (OC_Config->OCPolarity << 8U);
04874
04875   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04876   {
04877     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04878     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04879     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04880
04881     /* Reset the Output N Polarity level */
04882     tmpccer &= ~TIM_CCER_CC3NP;
04883     /* Set the Output N Polarity */
04884     tmpccer |= (OC_Config->OCNPolarity << 8U);
04885     /* Reset the Output N State */
04886     tmpccer &= ~TIM_CCER_CC3NE;
04887
04888     /* Reset the Output Compare and Output Compare N IDLE State */
04889     tmpcr2 &= ~TIM_CR2_OIS3;
04890     tmpcr2 &= ~TIM_CR2_OIS3N;
04891     /* Set the Output Idle state */
04892     tmpcr2 |= (OC_Config->OCIdleState << 4U);
04893     /* Set the Output N Idle state */
04894     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
04895   }
04896   /* Write to TIMx CR2 */
04897   TIMx->CR2 = tmpcr2;
04898
04899   /* Write to TIMx CCMR2 */
04900   TIMx->CCMR2 = tmpccmrx;
04901
04902   /* Set the Capture Compare Register value */
04903   TIMx->CCR3 = OC_Config->Pulse;
04904
04905   /* Write to TIMx CCER */
04906   TIMx->CCER = tmpccer;
04907 }
04908
04909 /**
04910   * @brief  Time Output Compare 4 configuration
04911   * @param  TIMx to select the TIM peripheral
04912   * @param  OC_Config: The output configuration structure
04913   * @retval None
04914   */
04915 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04916 {
04917   uint32_t tmpccmrx = 0U;
04918   uint32_t tmpccer = 0U;
04919   uint32_t tmpcr2 = 0U;
04920
04921   /* Disable the Channel 4: Reset the CC4E Bit */
04922   TIMx->CCER &= ~TIM_CCER_CC4E;
04923
04924   /* Get the TIMx CCER register value */
04925   tmpccer = TIMx->CCER;
04926   /* Get the TIMx CR2 register value */
04927   tmpcr2 = TIMx->CR2;
04928
04929   /* Get the TIMx CCMR2 register value */
04930   tmpccmrx = TIMx->CCMR2;
04931
04932   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04933   tmpccmrx &= ~TIM_CCMR2_OC4M;
04934   tmpccmrx &= ~TIM_CCMR2_CC4S;
04935
04936   /* Select the Output Compare Mode */
04937   tmpccmrx |= (OC_Config->OCMode << 8U);
04938
04939   /* Reset the Output Polarity level */
04940   tmpccer &= ~TIM_CCER_CC4P;
04941   /* Set the Output Compare Polarity */
04942   tmpccer |= (OC_Config->OCPolarity << 12U);
04943
04944   /*if((TIMx == TIM1) || (TIMx == TIM8))*/
04945   if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
04946   {
04947     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04948     /* Reset the Output Compare IDLE State */
04949     tmpcr2 &= ~TIM_CR2_OIS4;
04950     /* Set the Output Idle state */
04951     tmpcr2 |= (OC_Config->OCIdleState << 6U);
04952   }
04953   /* Write to TIMx CR2 */
04954   TIMx->CR2 = tmpcr2;
04955
04956   /* Write to TIMx CCMR2 */
04957   TIMx->CCMR2 = tmpccmrx;
04958
04959   /* Set the Capture Compare Register value */
04960   TIMx->CCR4 = OC_Config->Pulse;
04961
04962   /* Write to TIMx CCER */
04963   TIMx->CCER = tmpccer;
04964 }
04965
04966 /**
04967   * @brief  Time Output Compare 4 configuration
04968   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04969   *                the configuration information for TIM module.
04970   * @param  sSlaveConfig: The slave configuration structure
04971   * @retval None
04972   */
04973 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
04974                               TIM_SlaveConfigTypeDef * sSlaveConfig)
04975 {
04976   uint32_t tmpsmcr = 0U;
04977   uint32_t tmpccmr1 = 0U;
04978   uint32_t tmpccer = 0U;
04979
04980  /* Get the TIMx SMCR register value */
04981   tmpsmcr = htim->Instance->SMCR;
04982
04983   /* Reset the Trigger Selection Bits */
04984   tmpsmcr &= ~TIM_SMCR_TS;
04985   /* Set the Input Trigger source */
04986   tmpsmcr |= sSlaveConfig->InputTrigger;
04987
04988   /* Reset the slave mode Bits */
04989   tmpsmcr &= ~TIM_SMCR_SMS;
04990   /* Set the slave mode */
04991   tmpsmcr |= sSlaveConfig->SlaveMode;
04992
04993   /* Write to TIMx SMCR */
04994   htim->Instance->SMCR = tmpsmcr;
04995
04996   /* Configure the trigger prescaler, filter, and polarity */
04997   switch (sSlaveConfig->InputTrigger)
04998   {
04999   case TIM_TS_ETRF:
05000     {
05001       /* Check the parameters */
05002       assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
05003       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
05004       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05005       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05006       /* Configure the ETR Trigger source */
05007       TIM_ETR_SetConfig(htim->Instance,
05008                         sSlaveConfig->TriggerPrescaler,
05009                         sSlaveConfig->TriggerPolarity,
05010                         sSlaveConfig->TriggerFilter);
05011     }
05012     break;
05013
05014   case TIM_TS_TI1F_ED:
05015     {
05016       /* Check the parameters */
05017       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05018       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05019
05020       /* Disable the Channel 1: Reset the CC1E Bit */
05021       tmpccer = htim->Instance->CCER;
05022       htim->Instance->CCER &= ~TIM_CCER_CC1E;
05023       tmpccmr1 = htim->Instance->CCMR1;
05024
05025       /* Set the filter */
05026       tmpccmr1 &= ~TIM_CCMR1_IC1F;
05027       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
05028
05029       /* Write to TIMx CCMR1 and CCER registers */
05030       htim->Instance->CCMR1 = tmpccmr1;
05031       htim->Instance->CCER = tmpccer;
05032
05033     }
05034     break;
05035
05036   case TIM_TS_TI1FP1:
05037     {
05038       /* Check the parameters */
05039       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05040       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05041       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05042
05043       /* Configure TI1 Filter and Polarity */
05044       TIM_TI1_ConfigInputStage(htim->Instance,
05045                                sSlaveConfig->TriggerPolarity,
05046                                sSlaveConfig->TriggerFilter);
05047     }
05048     break;
05049
05050   case TIM_TS_TI2FP2:
05051     {
05052       /* Check the parameters */
05053       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05054       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05055       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05056
05057       /* Configure TI2 Filter and Polarity */
05058       TIM_TI2_ConfigInputStage(htim->Instance,
05059                                 sSlaveConfig->TriggerPolarity,
05060                                 sSlaveConfig->TriggerFilter);
05061     }
05062     break;
05063
05064   case TIM_TS_ITR0:
05065     {
05066       /* Check the parameter */
05067       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05068     }
05069     break;
05070
05071   case TIM_TS_ITR1:
05072     {
05073       /* Check the parameter */
05074       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05075     }
05076     break;
05077
05078   case TIM_TS_ITR2:
05079     {
05080       /* Check the parameter */
05081       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05082     }
05083     break;
05084
05085   case TIM_TS_ITR3:
05086     {
05087       /* Check the parameter */
05088       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05089     }
05090     break;
05091
05092   default:
05093     break;
05094   }
05095 }
05096
05097
05098 /**
05099   * @brief  Configure the Polarity and Filter for TI1.
05100   * @param  TIMx to select the TIM peripheral.
05101   * @param  TIM_ICPolarity : The Input Polarity.
05102   *          This parameter can be one of the following values:
05103   *            @arg TIM_ICPolarity_Rising
05104   *            @arg TIM_ICPolarity_Falling
05105   *            @arg TIM_ICPolarity_BothEdge
05106   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05107   *          This parameter must be a value between 0x00 and 0x0F.
05108   * @retval None
05109   */
05110 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05111 {
05112   uint32_t tmpccmr1 = 0U;
05113   uint32_t tmpccer = 0U;
05114
05115   /* Disable the Channel 1: Reset the CC1E Bit */
05116   tmpccer = TIMx->CCER;
05117   TIMx->CCER &= ~TIM_CCER_CC1E;
05118   tmpccmr1 = TIMx->CCMR1;
05119
05120   /* Set the filter */
05121   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05122   tmpccmr1 |= (TIM_ICFilter << 4U);
05123
05124   /* Select the Polarity and set the CC1E Bit */
05125   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05126   tmpccer |= TIM_ICPolarity;
05127
05128   /* Write to TIMx CCMR1 and CCER registers */
05129   TIMx->CCMR1 = tmpccmr1;
05130   TIMx->CCER = tmpccer;
05131 }
05132
05133 /**
05134   * @brief  Configure the TI2 as Input.
05135   * @param  TIMx to select the TIM peripheral
05136   * @param  TIM_ICPolarity : The Input Polarity.
05137   *          This parameter can be one of the following values:
05138   *            @arg TIM_ICPolarity_Rising
05139   *            @arg TIM_ICPolarity_Falling
05140   *            @arg TIM_ICPolarity_BothEdge
05141   * @param  TIM_ICSelection: specifies the input to be used.
05142   *          This parameter can be one of the following values:
05143   *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
05144   *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
05145   *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
05146   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05147   *          This parameter must be a value between 0x00 and 0x0F.
05148   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
05149   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
05150   *        protected against un-initialized filter and polarity values.
05151   * @retval None
05152   */
05153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05154                        uint32_t TIM_ICFilter)
05155 {
05156   uint32_t tmpccmr1 = 0U;
05157   uint32_t tmpccer = 0U;
05158
05159   /* Disable the Channel 2: Reset the CC2E Bit */
05160   TIMx->CCER &= ~TIM_CCER_CC2E;
05161   tmpccmr1 = TIMx->CCMR1;
05162   tmpccer = TIMx->CCER;
05163
05164   /* Select the Input */
05165   tmpccmr1 &= ~TIM_CCMR1_CC2S;
05166   tmpccmr1 |= (TIM_ICSelection << 8U);
05167
05168   /* Set the filter */
05169   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05170   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
05171
05172   /* Select the Polarity and set the CC2E Bit */
05173   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05174   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
05175
05176   /* Write to TIMx CCMR1 and CCER registers */
05177   TIMx->CCMR1 = tmpccmr1 ;
05178   TIMx->CCER = tmpccer;
05179 }
05180
05181 /**
05182   * @brief  Configure the Polarity and Filter for TI2.
05183   * @param  TIMx to select the TIM peripheral.
05184   * @param  TIM_ICPolarity : The Input Polarity.
05185   *          This parameter can be one of the following values:
05186   *            @arg TIM_ICPolarity_Rising
05187   *            @arg TIM_ICPolarity_Falling
05188   *            @arg TIM_ICPolarity_BothEdge
05189   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05190   *          This parameter must be a value between 0x00 and 0x0F.
05191   * @retval None
05192   */
05193 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05194 {
05195   uint32_t tmpccmr1 = 0U;
05196   uint32_t tmpccer = 0U;
05197
05198   /* Disable the Channel 2: Reset the CC2E Bit */
05199   TIMx->CCER &= ~TIM_CCER_CC2E;
05200   tmpccmr1 = TIMx->CCMR1;
05201   tmpccer = TIMx->CCER;
05202
05203   /* Set the filter */
05204   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05205   tmpccmr1 |= (TIM_ICFilter << 12U);
05206
05207   /* Select the Polarity and set the CC2E Bit */
05208   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05209   tmpccer |= (TIM_ICPolarity << 4U);
05210
05211   /* Write to TIMx CCMR1 and CCER registers */
05212   TIMx->CCMR1 = tmpccmr1 ;
05213   TIMx->CCER = tmpccer;
05214 }
05215
05216 /**
05217   * @brief  Configure the TI3 as Input.
05218   * @param  TIMx to select the TIM peripheral
05219   * @param  TIM_ICPolarity : The Input Polarity.
05220   *          This parameter can be one of the following values:
05221   *            @arg TIM_ICPolarity_Rising
05222   *            @arg TIM_ICPolarity_Falling
05223   *            @arg TIM_ICPolarity_BothEdge
05224   * @param  TIM_ICSelection: specifies the input to be used.
05225   *          This parameter can be one of the following values:
05226   *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
05227   *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
05228   *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
05229   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05230   *          This parameter must be a value between 0x00 and 0x0F.
05231   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
05232   *       (on channel4 path) is used as the input signal. Therefore CCMR2 must be
05233   *        protected against un-initialized filter and polarity values.
05234   * @retval None
05235   */
05236 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05237                        uint32_t TIM_ICFilter)
05238 {
05239   uint32_t tmpccmr2 = 0U;
05240   uint32_t tmpccer = 0U;
05241
05242   /* Disable the Channel 3: Reset the CC3E Bit */
05243   TIMx->CCER &= ~TIM_CCER_CC3E;
05244   tmpccmr2 = TIMx->CCMR2;
05245   tmpccer = TIMx->CCER;
05246
05247   /* Select the Input */
05248   tmpccmr2 &= ~TIM_CCMR2_CC3S;
05249   tmpccmr2 |= TIM_ICSelection;
05250
05251   /* Set the filter */
05252   tmpccmr2 &= ~TIM_CCMR2_IC3F;
05253   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
05254
05255   /* Select the Polarity and set the CC3E Bit */
05256   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
05257   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
05258
05259   /* Write to TIMx CCMR2 and CCER registers */
05260   TIMx->CCMR2 = tmpccmr2;
05261   TIMx->CCER = tmpccer;
05262 }
05263
05264 /**
05265   * @brief  Configure the TI4 as Input.
05266   * @param  TIMx to select the TIM peripheral
05267   * @param  TIM_ICPolarity : The Input Polarity.
05268   *          This parameter can be one of the following values:
05269   *            @arg TIM_ICPolarity_Rising
05270   *            @arg TIM_ICPolarity_Falling
05271   *            @arg TIM_ICPolarity_BothEdge
05272   * @param  TIM_ICSelection: specifies the input to be used.
05273   *          This parameter can be one of the following values:
05274   *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
05275   *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
05276   *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
05277   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05278   *          This parameter must be a value between 0x00 and 0x0F.
05279   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
05280   *       (on channel3 path) is used as the input signal. Therefore CCMR2 must be
05281   *        protected against un-initialized filter and polarity values.
05282   * @retval None
05283   */
05284 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05285                        uint32_t TIM_ICFilter)
05286 {
05287   uint32_t tmpccmr2 = 0U;
05288   uint32_t tmpccer = 0U;
05289
05290   /* Disable the Channel 4: Reset the CC4E Bit */
05291   TIMx->CCER &= ~TIM_CCER_CC4E;
05292   tmpccmr2 = TIMx->CCMR2;
05293   tmpccer = TIMx->CCER;
05294
05295   /* Select the Input */
05296   tmpccmr2 &= ~TIM_CCMR2_CC4S;
05297   tmpccmr2 |= (TIM_ICSelection << 8U);
05298
05299   /* Set the filter */
05300   tmpccmr2 &= ~TIM_CCMR2_IC4F;
05301   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
05302
05303   /* Select the Polarity and set the CC4E Bit */
05304   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
05305   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
05306
05307   /* Write to TIMx CCMR2 and CCER registers */
05308   TIMx->CCMR2 = tmpccmr2;
05309   TIMx->CCER = tmpccer ;
05310 }
05311
05312 /**
05313   * @brief  Selects the Input Trigger source
05314   * @param  TIMx to select the TIM peripheral
05315   * @param  TIM_ITRx: The Input Trigger source.
05316   *          This parameter can be one of the following values:
05317   *            @arg TIM_TS_ITR0: Internal Trigger 0
05318   *            @arg TIM_TS_ITR1: Internal Trigger 1
05319   *            @arg TIM_TS_ITR2: Internal Trigger 2
05320   *            @arg TIM_TS_ITR3: Internal Trigger 3
05321   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
05322   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
05323   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
05324   *            @arg TIM_TS_ETRF: External Trigger input
05325   * @retval None
05326   */
05327 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
05328 {
05329   uint32_t tmpsmcr = 0U;
05330
05331    /* Get the TIMx SMCR register value */
05332    tmpsmcr = TIMx->SMCR;
05333    /* Reset the TS Bits */
05334    tmpsmcr &= ~TIM_SMCR_TS;
05335    /* Set the Input Trigger source and the slave mode*/
05336    tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
05337    /* Write to TIMx SMCR */
05338    TIMx->SMCR = tmpsmcr;
05339 }
05340
05341 /**
05342   * @brief  Configures the TIMx External Trigger (ETR).
05343   * @param  TIMx to select the TIM peripheral
05344   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
05345   *          This parameter can be one of the following values:
05346   *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
05347   *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
05348   *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
05349   *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
05350   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
05351   *          This parameter can be one of the following values:
05352   *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
05353   *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
05354   * @param  ExtTRGFilter: External Trigger Filter.
05355   *          This parameter must be a value between 0x00 and 0x0F
05356   * @retval None
05357   */
05358 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
05359                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
05360 {
05361   uint32_t tmpsmcr = 0U;
05362
05363   tmpsmcr = TIMx->SMCR;
05364
05365   /* Reset the ETR Bits */
05366   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05367
05368   /* Set the Prescaler, the Filter value and the Polarity */
05369   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
05370
05371   /* Write to TIMx SMCR */
05372   TIMx->SMCR = tmpsmcr;
05373 }
05374
05375 /**
05376   * @}
05377   */
05378
05379 #endif /* HAL_TIM_MODULE_ENABLED */
05380 /**
05381   * @}
05382   */
05383
05384 /**
05385   * @}
05386   */
05387 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim.h Source File

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stm32f4xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of TIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_TIM_H
00040 #define __STM32F4xx_HAL_TIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIM_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Time base Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00068                                    This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00069
00070   uint32_t CounterMode;       /*!< Specifies the counter mode.
00071                                    This parameter can be a value of @ref TIM_Counter_Mode */
00072
00073   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00074                                    Auto-Reload Register at the next update event.
00075                                    This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF.  */
00076
00077   uint32_t ClockDivision;     /*!< Specifies the clock division.
00078                                    This parameter can be a value of @ref TIM_ClockDivision */
00079
00080   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00081                                     reaches zero, an update event is generated and counting restarts
00082                                     from the RCR value (N).
00083                                     This means in PWM mode that (N+1) corresponds to:
00084                                         - the number of PWM periods in edge-aligned mode
00085                                         - the number of half PWM period in center-aligned mode
00086                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00087                                      @note This parameter is valid only for TIM1 and TIM8. */
00088 } TIM_Base_InitTypeDef;
00089
00090 /**
00091   * @brief  TIM Output Compare Configuration Structure definition
00092   */
00093
00094 typedef struct
00095 {
00096   uint32_t OCMode;        /*!< Specifies the TIM mode.
00097                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00098
00099   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00100                                This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00101
00102   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00103                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00104
00105   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00106                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00107                                @note This parameter is valid only for TIM1 and TIM8. */
00108
00109   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
00110                                This parameter can be a value of @ref TIM_Output_Fast_State
00111                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00112
00113
00114   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00115                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00116                                @note This parameter is valid only for TIM1 and TIM8. */
00117
00118   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00119                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00120                                @note This parameter is valid only for TIM1 and TIM8. */
00121 } TIM_OC_InitTypeDef;
00122
00123 /**
00124   * @brief  TIM One Pulse Mode Configuration Structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t OCMode;        /*!< Specifies the TIM mode.
00129                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00130
00131   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00132                                This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00133
00134   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00135                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00136
00137   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00138                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00139                                @note This parameter is valid only for TIM1 and TIM8. */
00140
00141   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00142                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00143                                @note This parameter is valid only for TIM1 and TIM8. */
00144
00145   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00146                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00147                                @note This parameter is valid only for TIM1 and TIM8. */
00148
00149   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00150                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00151
00152   uint32_t ICSelection;   /*!< Specifies the input.
00153                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00154
00155   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00156                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00157 } TIM_OnePulse_InitTypeDef;
00158
00159
00160 /**
00161   * @brief  TIM Input Capture Configuration Structure definition
00162   */
00163
00164 typedef struct
00165 {
00166   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
00167                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00168
00169   uint32_t ICSelection;  /*!< Specifies the input.
00170                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00171
00172   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00173                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00174
00175   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00176                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00177 } TIM_IC_InitTypeDef;
00178
00179 /**
00180   * @brief  TIM Encoder Configuration Structure definition
00181   */
00182
00183 typedef struct
00184 {
00185   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00186                                This parameter can be a value of @ref TIM_Encoder_Mode */
00187
00188   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00189                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00190
00191   uint32_t IC1Selection;  /*!< Specifies the input.
00192                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00193
00194   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00195                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00196
00197   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00198                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00199
00200   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00201                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00202
00203   uint32_t IC2Selection;  /*!< Specifies the input.
00204                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00205
00206   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00207                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00208
00209   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00210                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00211 } TIM_Encoder_InitTypeDef;
00212
00213 /**
00214   * @brief  Clock Configuration Handle Structure definition
00215   */
00216 typedef struct
00217 {
00218   uint32_t ClockSource;     /*!< TIM clock sources.
00219                                  This parameter can be a value of @ref TIM_Clock_Source */
00220   uint32_t ClockPolarity;   /*!< TIM clock polarity.
00221                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00222   uint32_t ClockPrescaler;  /*!< TIM clock prescaler.
00223                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00224   uint32_t ClockFilter;    /*!< TIM clock filter.
00225                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00226 }TIM_ClockConfigTypeDef;
00227
00228 /**
00229   * @brief  Clear Input Configuration Handle Structure definition
00230   */
00231 typedef struct
00232 {
00233   uint32_t ClearInputState;      /*!< TIM clear Input state.
00234                                       This parameter can be ENABLE or DISABLE */
00235   uint32_t ClearInputSource;     /*!< TIM clear Input sources.
00236                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00237   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity.
00238                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00239   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler.
00240                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
00241   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter.
00242                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00243 }TIM_ClearInputConfigTypeDef;
00244
00245 /**
00246   * @brief  TIM Slave configuration Structure definition
00247   */
00248 typedef struct {
00249   uint32_t  SlaveMode;         /*!< Slave mode selection
00250                                   This parameter can be a value of @ref TIM_Slave_Mode */
00251   uint32_t  InputTrigger;      /*!< Input Trigger source
00252                                   This parameter can be a value of @ref TIM_Trigger_Selection */
00253   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00254                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
00255   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00256                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
00257   uint32_t  TriggerFilter;     /*!< Input trigger filter
00258                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00259
00260 }TIM_SlaveConfigTypeDef;
00261
00262 /**
00263   * @brief  HAL State structures definition
00264   */
00265 typedef enum
00266 {
00267   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00268   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00269   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00270   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00271   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
00272 }HAL_TIM_StateTypeDef;
00273
00274 /**
00275   * @brief  HAL Active channel structures definition
00276   */
00277 typedef enum
00278 {
00279   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00280   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00281   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00282   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00283   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
00284 }HAL_TIM_ActiveChannel;
00285
00286 /**
00287   * @brief  TIM Time Base Handle Structure definition
00288   */
00289 typedef struct
00290 {
00291   TIM_TypeDef                 *Instance;     /*!< Register base address             */
00292   TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
00293   HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
00294   DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
00295                                              This array is accessed by a @ref DMA_Handle_index */
00296   HAL_LockTypeDef             Lock;          /*!< Locking object                    */
00297   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00298 }TIM_HandleTypeDef;
00299 /**
00300   * @}
00301   */
00302
00303 /* Exported constants --------------------------------------------------------*/
00304 /** @defgroup TIM_Exported_Constants  TIM Exported Constants
00305   * @{
00306   */
00307
00308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
00309   * @{
00310   */
00311 #define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000U)            /*!< Polarity for TIx source */
00312 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
00313 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup TIM_ETR_Polarity  TIM ETR Polarity
00319   * @{
00320   */
00321 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
00322 #define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x00000000U)                /*!< Polarity for ETR source */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup TIM_ETR_Prescaler  TIM ETR Prescaler
00328   * @{
00329   */
00330 #define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x00000000U)                /*!< No prescaler is used */
00331 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
00332 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
00333 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
00334 /**
00335   * @}
00336   */
00337
00338 /** @defgroup TIM_Counter_Mode  TIM Counter Mode
00339   * @{
00340   */
00341 #define TIM_COUNTERMODE_UP                 ((uint32_t)0x00000000U)
00342 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
00343 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
00344 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
00345 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup TIM_ClockDivision TIM Clock Division
00351   * @{
00352   */
00353 #define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x00000000U)
00354 #define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
00355 #define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup TIM_Output_Compare_and_PWM_modes  TIM Output Compare and PWM modes
00361   * @{
00362   */
00363 #define TIM_OCMODE_TIMING                   ((uint32_t)0x00000000U)
00364 #define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
00365 #define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
00366 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
00367 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
00368 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
00369 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
00370 #define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
00371
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup TIM_Output_Fast_State  TIM Output Fast State
00377   * @{
00378   */
00379 #define TIM_OCFAST_DISABLE                ((uint32_t)0x00000000U)
00380 #define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup TIM_Output_Compare_Polarity  TIM Output Compare Polarity
00386   * @{
00387   */
00388 #define TIM_OCPOLARITY_HIGH                ((uint32_t)0x00000000U)
00389 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup TIM_Output_Compare_N_Polarity  TIM Output CompareN Polarity
00395   * @{
00396   */
00397 #define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x00000000U)
00398 #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup TIM_Output_Compare_Idle_State  TIM Output Compare Idle State
00404   * @{
00405   */
00406 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
00407 #define TIM_OCIDLESTATE_RESET              ((uint32_t)0x00000000U)
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup TIM_Output_Compare_N_Idle_State  TIM Output Compare N Idle State
00413   * @{
00414   */
00415 #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
00416 #define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x00000000U)
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup TIM_Channel  TIM Channel
00422   * @{
00423   */
00424 #define TIM_CHANNEL_1                      ((uint32_t)0x00000000U)
00425 #define TIM_CHANNEL_2                      ((uint32_t)0x00000004U)
00426 #define TIM_CHANNEL_3                      ((uint32_t)0x00000008U)
00427 #define TIM_CHANNEL_4                      ((uint32_t)0x0000000CU)
00428 #define TIM_CHANNEL_ALL                    ((uint32_t)0x00000018U)
00429
00430 /**
00431   * @}
00432   */
00433
00434 /** @defgroup TIM_Input_Capture_Polarity  TIM Input Capture Polarity
00435   * @{
00436   */
00437 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
00438 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
00439 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup TIM_Input_Capture_Selection  TIM Input Capture Selection
00445   * @{
00446   */
00447 #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00448                                                                      connected to IC1, IC2, IC3 or IC4, respectively */
00449 #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00450                                                                      connected to IC2, IC1, IC4 or IC3, respectively */
00451 #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00452
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup TIM_Input_Capture_Prescaler  TIM Input Capture Prescaler
00458   * @{
00459   */
00460 #define TIM_ICPSC_DIV1                     ((uint32_t)0x00000000U)       /*!< Capture performed each time an edge is detected on the capture input */
00461 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
00462 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
00463 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00469   * @{
00470   */
00471 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
00472 #define TIM_OPMODE_REPETITIVE              ((uint32_t)0x00000000U)
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00478   * @{
00479   */
00480 #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
00481 #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
00482 #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
00483
00484 /**
00485   * @}
00486   */
00487
00488 /** @defgroup TIM_Interrupt_definition  TIM Interrupt definition
00489   * @{
00490   */
00491 #define TIM_IT_UPDATE           (TIM_DIER_UIE)
00492 #define TIM_IT_CC1              (TIM_DIER_CC1IE)
00493 #define TIM_IT_CC2              (TIM_DIER_CC2IE)
00494 #define TIM_IT_CC3              (TIM_DIER_CC3IE)
00495 #define TIM_IT_CC4              (TIM_DIER_CC4IE)
00496 #define TIM_IT_COM              (TIM_DIER_COMIE)
00497 #define TIM_IT_TRIGGER          (TIM_DIER_TIE)
00498 #define TIM_IT_BREAK            (TIM_DIER_BIE)
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00504   * @{
00505   */
00506 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
00507 #define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x00000000U)
00508 /**
00509   * @}
00510   */
00511
00512 /** @defgroup TIM_DMA_sources  TIM DMA sources
00513   * @{
00514   */
00515 #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
00516 #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
00517 #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
00518 #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
00519 #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
00520 #define TIM_DMA_COM                        (TIM_DIER_COMDE)
00521 #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup TIM_Event_Source  TIM Event Source
00527   * @{
00528   */
00529 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG
00530 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
00531 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
00532 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
00533 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
00534 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
00535 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG
00536 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG
00537
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup TIM_Flag_definition  TIM Flag definition
00543   * @{
00544   */
00545 #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
00546 #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
00547 #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
00548 #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
00549 #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
00550 #define TIM_FLAG_COM                       (TIM_SR_COMIF)
00551 #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
00552 #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
00553 #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
00554 #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
00555 #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
00556 #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup TIM_Clock_Source  TIM Clock Source
00562   * @{
00563   */
00564 #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
00565 #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
00566 #define TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x00000000U)
00567 #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
00568 #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
00569 #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
00570 #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
00571 #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
00572 #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00573 #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
00574 /**
00575   * @}
00576   */
00577
00578 /** @defgroup TIM_Clock_Polarity  TIM Clock Polarity
00579   * @{
00580   */
00581 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
00582 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
00583 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
00584 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00585 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup TIM_Clock_Prescaler  TIM Clock Prescaler
00591   * @{
00592   */
00593 #define TIM_CLOCKPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00594 #define TIM_CLOCKPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00595 #define TIM_CLOCKPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00596 #define TIM_CLOCKPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00597 /**
00598   * @}
00599   */
00600
00601 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
00602   * @{
00603   */
00604 #define TIM_CLEARINPUTSOURCE_ETR           ((uint32_t)0x00000001U)
00605 #define TIM_CLEARINPUTSOURCE_NONE          ((uint32_t)0x00000000U)
00606 /**
00607   * @}
00608   */
00609
00610 /** @defgroup TIM_ClearInput_Polarity  TIM Clear Input Polarity
00611   * @{
00612   */
00613 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
00614 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00620   * @{
00621   */
00622 #define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
00623 #define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00624 #define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00625 #define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00631   * @{
00632   */
00633 #define TIM_OSSR_ENABLE         (TIM_BDTR_OSSR)
00634 #define TIM_OSSR_DISABLE        ((uint32_t)0x00000000U)
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00640   * @{
00641   */
00642 #define TIM_OSSI_ENABLE             (TIM_BDTR_OSSI)
00643 #define TIM_OSSI_DISABLE            ((uint32_t)0x00000000U)
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup TIM_Lock_level  TIM Lock level
00649   * @{
00650   */
00651 #define TIM_LOCKLEVEL_OFF          ((uint32_t)0x00000000U)
00652 #define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
00653 #define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
00654 #define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
00655 /**
00656   * @}
00657   */
00658 /** @defgroup TIM_Break_Input_enable_disable  TIM Break Input State
00659   * @{
00660   */
00661 #define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
00662 #define TIM_BREAK_DISABLE         ((uint32_t)0x00000000U)
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup TIM_Break_Polarity  TIM Break Polarity
00668   * @{
00669   */
00670 #define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x00000000U)
00671 #define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
00672 /**
00673   * @}
00674   */
00675
00676 /** @defgroup TIM_AOE_Bit_Set_Reset  TIM AOE Bit State
00677   * @{
00678   */
00679 #define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
00680 #define TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x00000000U)
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00686   * @{
00687   */
00688 #define TIM_TRGO_RESET            ((uint32_t)0x00000000U)
00689 #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
00690 #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
00691 #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00692 #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
00693 #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
00694 #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
00695 #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00696 /**
00697   * @}
00698   */
00699
00700 /** @defgroup TIM_Slave_Mode TIM Slave Mode
00701   * @{
00702   */
00703 #define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x00000000U)
00704 #define TIM_SLAVEMODE_RESET                ((uint32_t)0x00000004U)
00705 #define TIM_SLAVEMODE_GATED                ((uint32_t)0x00000005U)
00706 #define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x00000006U)
00707 #define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x00000007U)
00708 /**
00709   * @}
00710   */
00711
00712 /** @defgroup TIM_Master_Slave_Mode  TIM Master Slave Mode
00713   * @{
00714   */
00715 #define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x00000080U)
00716 #define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x00000000U)
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup TIM_Trigger_Selection  TIM Trigger Selection
00722   * @{
00723   */
00724 #define TIM_TS_ITR0                        ((uint32_t)0x00000000U)
00725 #define TIM_TS_ITR1                        ((uint32_t)0x00000010U)
00726 #define TIM_TS_ITR2                        ((uint32_t)0x00000020U)
00727 #define TIM_TS_ITR3                        ((uint32_t)0x00000030U)
00728 #define TIM_TS_TI1F_ED                     ((uint32_t)0x00000040U)
00729 #define TIM_TS_TI1FP1                      ((uint32_t)0x00000050U)
00730 #define TIM_TS_TI2FP2                      ((uint32_t)0x00000060U)
00731 #define TIM_TS_ETRF                        ((uint32_t)0x00000070U)
00732 #define TIM_TS_NONE                        ((uint32_t)0x0000FFFFU)
00733 /**
00734   * @}
00735   */
00736
00737 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00738   * @{
00739   */
00740 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
00741 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
00742 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00743 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00744 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00745 /**
00746   * @}
00747   */
00748
00749 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
00750   * @{
00751   */
00752 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00753 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
00754 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
00755 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
00756 /**
00757   * @}
00758   */
00759
00760
00761 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
00762   * @{
00763   */
00764 #define TIM_TI1SELECTION_CH1                ((uint32_t)0x00000000U)
00765 #define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup TIM_DMA_Base_address  TIM DMA Base address
00771   * @{
00772   */
00773 #define TIM_DMABASE_CR1                    (0x00000000U)
00774 #define TIM_DMABASE_CR2                    (0x00000001U)
00775 #define TIM_DMABASE_SMCR                   (0x00000002U)
00776 #define TIM_DMABASE_DIER                   (0x00000003U)
00777 #define TIM_DMABASE_SR                     (0x00000004U)
00778 #define TIM_DMABASE_EGR                    (0x00000005U)
00779 #define TIM_DMABASE_CCMR1                  (0x00000006U)
00780 #define TIM_DMABASE_CCMR2                  (0x00000007U)
00781 #define TIM_DMABASE_CCER                   (0x00000008U)
00782 #define TIM_DMABASE_CNT                    (0x00000009U)
00783 #define TIM_DMABASE_PSC                    (0x0000000AU)
00784 #define TIM_DMABASE_ARR                    (0x0000000BU)
00785 #define TIM_DMABASE_RCR                    (0x0000000CU)
00786 #define TIM_DMABASE_CCR1                   (0x0000000DU)
00787 #define TIM_DMABASE_CCR2                   (0x0000000EU)
00788 #define TIM_DMABASE_CCR3                   (0x0000000FU)
00789 #define TIM_DMABASE_CCR4                   (0x00000010U)
00790 #define TIM_DMABASE_BDTR                   (0x00000011U)
00791 #define TIM_DMABASE_DCR                    (0x00000012U)
00792 #define TIM_DMABASE_OR                     (0x00000013U)
00793 /**
00794   * @}
00795   */
00796
00797 /** @defgroup TIM_DMA_Burst_Length  TIM DMA Burst Length
00798   * @{
00799   */
00800 #define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000U)
00801 #define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100U)
00802 #define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200U)
00803 #define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300U)
00804 #define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400U)
00805 #define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500U)
00806 #define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600U)
00807 #define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700U)
00808 #define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800U)
00809 #define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900U)
00810 #define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00U)
00811 #define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00U)
00812 #define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00U)
00813 #define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00U)
00814 #define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00U)
00815 #define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00U)
00816 #define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000U)
00817 #define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100U)
00818 /**
00819   * @}
00820   */
00821
00822 /** @defgroup DMA_Handle_index  DMA Handle index
00823   * @{
00824   */
00825 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000U)       /*!< Index of the DMA handle used for Update DMA requests */
00826 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001U)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
00827 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002U)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
00828 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003U)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
00829 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004U)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
00830 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005U)       /*!< Index of the DMA handle used for Commutation DMA requests */
00831 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006U)       /*!< Index of the DMA handle used for Trigger DMA requests */
00832 /**
00833   * @}
00834   */
00835
00836 /** @defgroup Channel_CC_State  Channel CC State
00837   * @{
00838   */
00839 #define TIM_CCx_ENABLE                   ((uint32_t)0x00000001U)
00840 #define TIM_CCx_DISABLE                  ((uint32_t)0x00000000U)
00841 #define TIM_CCxN_ENABLE                  ((uint32_t)0x00000004U)
00842 #define TIM_CCxN_DISABLE                 ((uint32_t)0x00000000U)
00843 /**
00844   * @}
00845   */
00846
00847 /**
00848   * @}
00849   */
00850
00851 /* Exported macro ------------------------------------------------------------*/
00852 /** @defgroup TIM_Exported_Macros TIM Exported Macros
00853   * @{
00854   */
00855 /** @brief Reset TIM handle state
00856   * @param  __HANDLE__: TIM handle
00857   * @retval None
00858   */
00859 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
00860
00861 /**
00862   * @brief  Enable the TIM peripheral.
00863   * @param  __HANDLE__: TIM handle
00864   * @retval None
00865  */
00866 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
00867
00868 /**
00869   * @brief  Enable the TIM main Output.
00870   * @param  __HANDLE__: TIM handle
00871   * @retval None
00872   */
00873 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
00874
00875
00876 /**
00877   * @brief  Disable the TIM peripheral.
00878   * @param  __HANDLE__: TIM handle
00879   * @retval None
00880   */
00881 #define __HAL_TIM_DISABLE(__HANDLE__) \
00882                         do { \
00883                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
00884                           { \
00885                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
00886                             { \
00887                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
00888                             } \
00889                           } \
00890                         } while(0)
00891
00892 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
00893    channels have been disabled */
00894 /**
00895   * @brief  Disable the TIM main Output.
00896   * @param  __HANDLE__: TIM handle
00897   * @retval None
00898   */
00899 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
00900                         do { \
00901                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
00902                           { \
00903                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
00904                             { \
00905                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
00906                             } \
00907                           } \
00908                         } while(0)
00909
00910 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
00911 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
00912 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
00913 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
00914 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
00915 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00916
00917 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00918 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
00919
00920 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
00921 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
00922
00923 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
00924 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
00925  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
00926  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
00927  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
00928
00929 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
00930 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
00931  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
00932  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
00933  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
00934
00935 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
00936 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
00937  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
00938  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
00939  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
00940
00941 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
00942 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
00943  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
00944  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
00945  ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
00946
00947 /**
00948   * @brief  Sets the TIM Capture Compare Register value on runtime without
00949   *         calling another time ConfigChannel function.
00950   * @param  __HANDLE__: TIM handle.
00951   * @param  __CHANNEL__ : TIM Channels to be configured.
00952   *          This parameter can be one of the following values:
00953   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00954   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00955   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00956   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00957   * @param  __COMPARE__: specifies the Capture Compare register new value.
00958   * @retval None
00959   */
00960 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
00961 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
00962
00963 /**
00964   * @brief  Gets the TIM Capture Compare Register value on runtime
00965   * @param  __HANDLE__: TIM handle.
00966   * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
00967   *          This parameter can be one of the following values:
00968   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
00969   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
00970   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
00971   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
00972   * @retval None
00973   */
00974 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
00975   (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
00976
00977 /**
00978   * @brief  Sets the TIM Counter Register value on runtime.
00979   * @param  __HANDLE__: TIM handle.
00980   * @param  __COUNTER__: specifies the Counter register new value.
00981   * @retval None
00982   */
00983 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
00984
00985 /**
00986   * @brief  Gets the TIM Counter Register value on runtime.
00987   * @param  __HANDLE__: TIM handle.
00988   * @retval None
00989   */
00990 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
00991
00992 /**
00993   * @brief  Sets the TIM Autoreload Register value on runtime without calling
00994   *         another time any Init function.
00995   * @param  __HANDLE__: TIM handle.
00996   * @param  __AUTORELOAD__: specifies the Counter register new value.
00997   * @retval None
00998   */
00999 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)                  \
01000                         do{                                                  \
01001                             (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01002                             (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01003                           } while(0)
01004 /**
01005   * @brief  Gets the TIM Autoreload Register value on runtime
01006   * @param  __HANDLE__: TIM handle.
01007   * @retval None
01008   */
01009 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
01010
01011 /**
01012   * @brief  Sets the TIM Clock Division value on runtime without calling
01013   *         another time any Init function.
01014   * @param  __HANDLE__: TIM handle.
01015   * @param  __CKD__: specifies the clock division value.
01016   *          This parameter can be one of the following value:
01017   *            @arg TIM_CLOCKDIVISION_DIV1
01018   *            @arg TIM_CLOCKDIVISION_DIV2
01019   *            @arg TIM_CLOCKDIVISION_DIV4
01020   * @retval None
01021   */
01022 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01023                         do{                                                             \
01024                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
01025                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
01026                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
01027                           } while(0)
01028 /**
01029   * @brief  Gets the TIM Clock Division value on runtime
01030   * @param  __HANDLE__: TIM handle.
01031   * @retval None
01032   */
01033 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01034
01035 /**
01036   * @brief  Sets the TIM Input Capture prescaler on runtime without calling
01037   *         another time HAL_TIM_IC_ConfigChannel() function.
01038   * @param  __HANDLE__: TIM handle.
01039   * @param  __CHANNEL__ : TIM Channels to be configured.
01040   *          This parameter can be one of the following values:
01041   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01042   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01043   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01044   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01045   * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
01046   *          This parameter can be one of the following values:
01047   *            @arg TIM_ICPSC_DIV1: no prescaler
01048   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01049   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01050   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01051   * @retval None
01052   */
01053 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01054                         do{                                                    \
01055                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01056                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01057                           } while(0)
01058
01059 /**
01060   * @brief  Gets the TIM Input Capture prescaler on runtime
01061   * @param  __HANDLE__: TIM handle.
01062   * @param  __CHANNEL__ : TIM Channels to be configured.
01063   *          This parameter can be one of the following values:
01064   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01065   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01066   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01067   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01068   * @retval None
01069   */
01070 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01071   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01072    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
01073    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01074    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
01075
01076 /**
01077   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
01078   * @param  __HANDLE__: TIM handle.
01079   * @note  When the USR bit of the TIMx_CR1 register is set, only counter
01080   *        overflow/underflow generates an update interrupt or DMA request (if
01081   *        enabled)
01082   * @retval None
01083   */
01084 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
01085     ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
01086
01087 /**
01088   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
01089   * @param  __HANDLE__: TIM handle.
01090   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
01091   *        following events generate an update interrupt or DMA request (if
01092   *        enabled):
01093   *          _ Counter overflow/underflow
01094   *          _ Setting the UG bit
01095   *          _ Update generation through the slave mode controller
01096   * @retval None
01097   */
01098 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
01099       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
01100
01101 /**
01102   * @brief  Sets the TIM Capture x input polarity on runtime.
01103   * @param  __HANDLE__: TIM handle.
01104   * @param  __CHANNEL__: TIM Channels to be configured.
01105   *          This parameter can be one of the following values:
01106   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01107   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01108   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01109   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01110   * @param  __POLARITY__: Polarity for TIx source
01111   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01112   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01113   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01114   * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.
01115   * @retval None
01116   */
01117 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                          \
01118                        do{                                                                            \
01119                            TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01120                            TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01121                          }while(0)
01122 /**
01123   * @}
01124   */
01125
01126 /* Include TIM HAL Extension module */
01127 #include "stm32f4xx_hal_tim_ex.h"
01128
01129 /* Exported functions --------------------------------------------------------*/
01130 /** @addtogroup TIM_Exported_Functions
01131   * @{
01132   */
01133
01134 /** @addtogroup TIM_Exported_Functions_Group1
01135   * @{
01136   */
01137
01138 /* Time Base functions ********************************************************/
01139 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01140 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01141 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01142 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01143 /* Blocking mode: Polling */
01144 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01145 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01146 /* Non-Blocking mode: Interrupt */
01147 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01148 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01149 /* Non-Blocking mode: DMA */
01150 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01151 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01152 /**
01153   * @}
01154   */
01155
01156 /** @addtogroup TIM_Exported_Functions_Group2
01157   * @{
01158   */
01159 /* Timer Output Compare functions **********************************************/
01160 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01161 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01162 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01163 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01164 /* Blocking mode: Polling */
01165 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01166 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01167 /* Non-Blocking mode: Interrupt */
01168 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01169 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01170 /* Non-Blocking mode: DMA */
01171 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01172 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01173
01174 /**
01175   * @}
01176   */
01177
01178 /** @addtogroup TIM_Exported_Functions_Group3
01179   * @{
01180   */
01181 /* Timer PWM functions *********************************************************/
01182 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
01183 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
01184 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
01185 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
01186 /* Blocking mode: Polling */
01187 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01188 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01189 /* Non-Blocking mode: Interrupt */
01190 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01191 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01192 /* Non-Blocking mode: DMA */
01193 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01194 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01195
01196 /**
01197   * @}
01198   */
01199
01200 /** @addtogroup TIM_Exported_Functions_Group4
01201   * @{
01202   */
01203 /* Timer Input Capture functions ***********************************************/
01204 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
01205 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
01206 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
01207 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
01208 /* Blocking mode: Polling */
01209 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01210 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01211 /* Non-Blocking mode: Interrupt */
01212 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01213 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01214 /* Non-Blocking mode: DMA */
01215 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01216 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01217
01218 /**
01219   * @}
01220   */
01221
01222 /** @addtogroup TIM_Exported_Functions_Group5
01223   * @{
01224   */
01225 /* Timer One Pulse functions ***************************************************/
01226 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
01227 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
01228 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
01229 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
01230 /* Blocking mode: Polling */
01231 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01232 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01233
01234 /* Non-Blocking mode: Interrupt */
01235 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01236 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01237
01238 /**
01239   * @}
01240   */
01241
01242 /** @addtogroup TIM_Exported_Functions_Group6
01243   * @{
01244   */
01245 /* Timer Encoder functions *****************************************************/
01246 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
01247 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
01248 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
01249 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
01250  /* Blocking mode: Polling */
01251 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01252 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01253 /* Non-Blocking mode: Interrupt */
01254 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01255 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01256 /* Non-Blocking mode: DMA */
01257 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
01258 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01259
01260 /**
01261   * @}
01262   */
01263
01264 /** @addtogroup TIM_Exported_Functions_Group7
01265   * @{
01266   */
01267 /* Interrupt Handler functions  **********************************************/
01268 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
01269
01270 /**
01271   * @}
01272   */
01273
01274 /** @addtogroup TIM_Exported_Functions_Group8
01275   * @{
01276   */
01277 /* Control functions  *********************************************************/
01278 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01279 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01280 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
01281 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
01282 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
01283 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
01284 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
01285 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01286 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01287 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01288                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01289 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01290 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01291                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01292 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01293 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
01294 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
01295
01296 /**
01297   * @}
01298   */
01299
01300 /** @addtogroup TIM_Exported_Functions_Group9
01301   * @{
01302   */
01303 /* Callback in non blocking modes (Interrupt and DMA) *************************/
01304 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
01305 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
01306 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
01307 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
01308 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
01309 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
01310
01311 /**
01312   * @}
01313   */
01314
01315 /** @addtogroup TIM_Exported_Functions_Group10
01316   * @{
01317   */
01318 /* Peripheral State functions  **************************************************/
01319 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
01320 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
01321 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
01322 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
01323 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
01324 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
01325
01326 /**
01327   * @}
01328   */
01329
01330 /**
01331   * @}
01332   */
01333
01334 /* Private macros ------------------------------------------------------------*/
01335 /** @defgroup TIM_Private_Macros TIM Private Macros
01336   * @{
01337   */
01338
01339 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
01340   * @{
01341   */
01342 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
01343                                    ((MODE) == TIM_COUNTERMODE_DOWN)            || \
01344                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01345                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01346                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
01347
01348 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
01349                                        ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
01350                                        ((DIV) == TIM_CLOCKDIVISION_DIV4))
01351
01352 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
01353                                ((MODE) == TIM_OCMODE_PWM2))
01354
01355 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
01356                           ((MODE) == TIM_OCMODE_ACTIVE)           || \
01357                           ((MODE) == TIM_OCMODE_INACTIVE)         || \
01358                           ((MODE) == TIM_OCMODE_TOGGLE)           || \
01359                           ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
01360                           ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
01361
01362 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
01363                                   ((STATE) == TIM_OCFAST_ENABLE))
01364
01365 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
01366                                       ((POLARITY) == TIM_OCPOLARITY_LOW))
01367
01368 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
01369                                        ((POLARITY) == TIM_OCNPOLARITY_LOW))
01370
01371 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
01372                                     ((STATE) == TIM_OCIDLESTATE_RESET))
01373
01374 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
01375                                     ((STATE) == TIM_OCNIDLESTATE_RESET))
01376
01377 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
01378                                   ((CHANNEL) == TIM_CHANNEL_2) || \
01379                                   ((CHANNEL) == TIM_CHANNEL_3) || \
01380                                   ((CHANNEL) == TIM_CHANNEL_4) || \
01381                                   ((CHANNEL) == TIM_CHANNEL_ALL))
01382
01383 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
01384                                       ((CHANNEL) == TIM_CHANNEL_2))
01385
01386 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
01387                                                 ((CHANNEL) == TIM_CHANNEL_2) || \
01388                                                 ((CHANNEL) == TIM_CHANNEL_3))
01389
01390 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
01391                                       ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
01392                                       ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
01393
01394 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
01395                                         ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
01396                                         ((SELECTION) == TIM_ICSELECTION_TRC))
01397
01398 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
01399                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \
01400                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \
01401                                         ((PRESCALER) == TIM_ICPSC_DIV8))
01402
01403 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
01404                                ((MODE) == TIM_OPMODE_REPETITIVE))
01405
01406 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
01407
01408 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
01409                                    ((MODE) == TIM_ENCODERMODE_TI2) || \
01410                                    ((MODE) == TIM_ENCODERMODE_TI12))
01411
01412 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
01413
01414 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
01415                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
01416                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
01417                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
01418                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
01419                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
01420                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
01421                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
01422                                    ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
01423                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
01424
01425 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
01426                                         ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01427                                         ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
01428                                         ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
01429                                         ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
01430
01431 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
01432                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
01433                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
01434                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
01435
01436 #define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0x0FU)
01437
01438 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE)  (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
01439                                          ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
01440
01441 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY)   (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01442                                                ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01443
01444 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01445                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01446                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01447                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
01448
01449 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
01450
01451 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
01452                                   ((STATE) == TIM_OSSR_DISABLE))
01453
01454 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
01455                                   ((STATE) == TIM_OSSI_DISABLE))
01456
01457 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
01458                                   ((LEVEL) == TIM_LOCKLEVEL_1) || \
01459                                   ((LEVEL) == TIM_LOCKLEVEL_2) || \
01460                                   ((LEVEL) == TIM_LOCKLEVEL_3))
01461
01462 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
01463                                    ((STATE) == TIM_BREAK_DISABLE))
01464
01465 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
01466                                          ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
01467
01468 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01469                                               ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
01470
01471 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
01472                                     ((SOURCE) == TIM_TRGO_ENABLE) || \
01473                                     ((SOURCE) == TIM_TRGO_UPDATE) || \
01474                                     ((SOURCE) == TIM_TRGO_OC1) || \
01475                                     ((SOURCE) == TIM_TRGO_OC1REF) || \
01476                                     ((SOURCE) == TIM_TRGO_OC2REF) || \
01477                                     ((SOURCE) == TIM_TRGO_OC3REF) || \
01478                                     ((SOURCE) == TIM_TRGO_OC4REF))
01479
01480 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
01481                                  ((MODE) == TIM_SLAVEMODE_GATED) || \
01482                                  ((MODE) == TIM_SLAVEMODE_RESET) || \
01483                                  ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
01484                                  ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
01485
01486 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
01487                                  ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
01488
01489 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
01490                                              ((SELECTION) == TIM_TS_ITR1) || \
01491                                              ((SELECTION) == TIM_TS_ITR2) || \
01492                                              ((SELECTION) == TIM_TS_ITR3) || \
01493                                              ((SELECTION) == TIM_TS_TI1F_ED) || \
01494                                              ((SELECTION) == TIM_TS_TI1FP1) || \
01495                                              ((SELECTION) == TIM_TS_TI2FP2) || \
01496                                              ((SELECTION) == TIM_TS_ETRF))
01497
01498 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
01499                                                            ((SELECTION) == TIM_TS_ITR1) || \
01500                                                            ((SELECTION) == TIM_TS_ITR2) || \
01501                                                            ((SELECTION) == TIM_TS_ITR3) || \
01502                                                            ((SELECTION) == TIM_TS_NONE))
01503
01504 #define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01505                                               ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01506                                               ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
01507                                               ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01508                                               ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01509
01510 #define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
01511                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
01512                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
01513                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
01514
01515 #define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0x0FU)
01516
01517 #define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
01518                                              ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
01519
01520 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
01521                                ((BASE) == TIM_DMABASE_CR2) || \
01522                                ((BASE) == TIM_DMABASE_SMCR) || \
01523                                ((BASE) == TIM_DMABASE_DIER) || \
01524                                ((BASE) == TIM_DMABASE_SR) || \
01525                                ((BASE) == TIM_DMABASE_EGR) || \
01526                                ((BASE) == TIM_DMABASE_CCMR1) || \
01527                                ((BASE) == TIM_DMABASE_CCMR2) || \
01528                                ((BASE) == TIM_DMABASE_CCER) || \
01529                                ((BASE) == TIM_DMABASE_CNT) || \
01530                                ((BASE) == TIM_DMABASE_PSC) || \
01531                                ((BASE) == TIM_DMABASE_ARR) || \
01532                                ((BASE) == TIM_DMABASE_RCR) || \
01533                                ((BASE) == TIM_DMABASE_CCR1) || \
01534                                ((BASE) == TIM_DMABASE_CCR2) || \
01535                                ((BASE) == TIM_DMABASE_CCR3) || \
01536                                ((BASE) == TIM_DMABASE_CCR4) || \
01537                                ((BASE) == TIM_DMABASE_BDTR) || \
01538                                ((BASE) == TIM_DMABASE_DCR) || \
01539                                ((BASE) == TIM_DMABASE_OR))
01540
01541 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01542                                    ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01543                                    ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01544                                    ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01545                                    ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01546                                    ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01547                                    ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01548                                    ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01549                                    ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01550                                    ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01551                                    ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01552                                    ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01553                                    ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01554                                    ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01555                                    ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01556                                    ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01557                                    ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01558                                    ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
01559
01560 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
01561 /**
01562   * @}
01563   */
01564
01565 /** @defgroup TIM_Mask_Definitions TIM Mask Definition
01566   * @{
01567   */
01568 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01569    channels have been disabled */
01570 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01571 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
01572 /**
01573   * @}
01574   */
01575
01576 /**
01577   * @}
01578   */
01579
01580 /* Private functions ---------------------------------------------------------*/
01581 /** @defgroup TIM_Private_Functions TIM Private Functions
01582   * @{
01583   */
01584 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
01585 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
01586 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01587 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
01588 void TIM_DMAError(DMA_HandleTypeDef *hdma);
01589 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
01590 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
01591 /**
01592   * @}
01593   */
01594
01595 /**
01596   * @}
01597   */
01598
01599 /**
01600   * @}
01601   */
01602
01603 #ifdef __cplusplus
01604 }
01605 #endif
01606
01607 #endif /* __STM32F4xx_HAL_TIM_H */
01608
01609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim_ex.c Source File

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stm32f4xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer extension peripheral:
00010   *           + Time Hall Sensor Interface Initialization
00011   *           + Time Hall Sensor Interface Start
00012   *           + Time Complementary signal bread and dead time configuration
00013   *           + Time Master and Slave synchronization configuration
00014   @verbatim
00015   ==============================================================================
00016                       ##### TIMER Extended features #####
00017   ==============================================================================
00018   [..]
00019     The Timer Extension features include:
00020     (#) Complementary outputs with programmable dead-time for :
00021         (++) Input Capture
00022         (++) Output Compare
00023         (++) PWM generation (Edge and Center-aligned Mode)
00024         (++) One-pulse mode output
00025     (#) Synchronization circuit to control the timer with external signals and to
00026         interconnect several timers together.
00027     (#) Break input to put the timer output signals in reset state or in a known state.
00028     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00029         positioning purposes
00030
00031                         ##### How to use this driver #####
00032   ==============================================================================
00033   [..]
00034      (#) Initialize the TIM low level resources by implementing the following functions
00035          depending from feature used :
00036            (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
00037            (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
00038            (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00039            (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
00040
00041      (#) Initialize the TIM low level resources :
00042         (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
00043         (##) TIM pins configuration
00044             (+++) Enable the clock for the TIM GPIOs using the following function:
00045                  __GPIOx_CLK_ENABLE();
00046             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00047
00048      (#) The external Clock can be configured, if needed (the default clock is the
00049          internal clock from the APBx), using the following function:
00050          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00051          any start function.
00052
00053     (#) Configure the TIM in the desired functioning mode using one of the
00054         initialization function of this driver:
00055         (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
00056              Timer Hall Sensor Interface and the commutation event with the corresponding
00057              Interrupt and DMA request if needed (Note that One Timer is used to interface
00058              with the Hall sensor Interface and another Timer should be used to use
00059              the commutation event).
00060
00061     (#) Activate the TIM peripheral using one of the start functions:
00062            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
00063            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00064            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00065            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00066
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097   */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f4xx_hal.h"
00101
00102 /** @addtogroup STM32F4xx_HAL_Driver
00103   * @{
00104   */
00105
00106 /** @defgroup TIMEx  TIMEx
00107   * @brief TIM HAL module driver
00108   * @{
00109   */
00110
00111 #ifdef HAL_TIM_MODULE_ENABLED
00112
00113 /* Private typedef -----------------------------------------------------------*/
00114 /* Private define ------------------------------------------------------------*/
00115 /* Private macro -------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /** @addtogroup TIMEx_Private_Functions
00118   * @{
00119   */
00120 /* Private function prototypes -----------------------------------------------*/
00121 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported functions --------------------------------------------------------*/
00127 /** @defgroup TIMEx_Exported_Functions TIM Exported Functions
00128   * @{
00129   */
00130
00131 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
00132  *  @brief    Timer Hall Sensor functions
00133  *
00134 @verbatim
00135   ==============================================================================
00136                       ##### Timer Hall Sensor functions #####
00137   ==============================================================================
00138   [..]
00139     This section provides functions allowing to:
00140     (+) Initialize and configure TIM HAL Sensor.
00141     (+) De-initialize TIM HAL Sensor.
00142     (+) Start the Hall Sensor Interface.
00143     (+) Stop the Hall Sensor Interface.
00144     (+) Start the Hall Sensor Interface and enable interrupts.
00145     (+) Stop the Hall Sensor Interface and disable interrupts.
00146     (+) Start the Hall Sensor Interface and enable DMA transfers.
00147     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00148
00149 @endverbatim
00150   * @{
00151   */
00152 /**
00153   * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
00154   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00155   *                the configuration information for TIM module.
00156   * @param  sConfig: TIM Hall Sensor configuration structure
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
00160 {
00161   TIM_OC_InitTypeDef OC_Config;
00162
00163   /* Check the TIM handle allocation */
00164   if(htim == NULL)
00165   {
00166     return HAL_ERROR;
00167   }
00168
00169   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00170   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00171   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00172   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00173   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00174   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00175
00176   /* Set the TIM state */
00177   htim->State= HAL_TIM_STATE_BUSY;
00178
00179   /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00180   HAL_TIMEx_HallSensor_MspInit(htim);
00181
00182   /* Configure the Time base in the Encoder Mode */
00183   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00184
00185   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00186   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00187
00188   /* Reset the IC1PSC Bits */
00189   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00190   /* Set the IC1PSC value */
00191   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00192
00193   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00194   htim->Instance->CR2 |= TIM_CR2_TI1S;
00195
00196   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00197   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00198   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00199
00200   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00201   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00202   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00203
00204   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00205   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00206   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00207   OC_Config.OCMode = TIM_OCMODE_PWM2;
00208   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00209   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00210   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00211   OC_Config.Pulse = sConfig->Commutation_Delay;
00212
00213   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00214
00215   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00216     register to 101 */
00217   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00218   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00219
00220   /* Initialize the TIM state*/
00221   htim->State= HAL_TIM_STATE_READY;
00222
00223   return HAL_OK;
00224 }
00225
00226 /**
00227   * @brief  DeInitializes the TIM Hall Sensor interface
00228   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00229   *                the configuration information for TIM module.
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00233 {
00234   /* Check the parameters */
00235   assert_param(IS_TIM_INSTANCE(htim->Instance));
00236
00237   htim->State = HAL_TIM_STATE_BUSY;
00238
00239   /* Disable the TIM Peripheral Clock */
00240   __HAL_TIM_DISABLE(htim);
00241
00242   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00243   HAL_TIMEx_HallSensor_MspDeInit(htim);
00244
00245   /* Change TIM state */
00246   htim->State = HAL_TIM_STATE_RESET;
00247
00248   /* Release Lock */
00249   __HAL_UNLOCK(htim);
00250
00251   return HAL_OK;
00252 }
00253
00254 /**
00255   * @brief  Initializes the TIM Hall Sensor MSP.
00256   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00257   *                the configuration information for TIM module.
00258   * @retval None
00259   */
00260 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00261 {
00262   /* Prevent unused argument(s) compilation warning */
00263   UNUSED(htim);
00264   /* NOTE : This function Should not be modified, when the callback is needed,
00265             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00266    */
00267 }
00268
00269 /**
00270   * @brief  DeInitializes TIM Hall Sensor MSP.
00271   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00272   *                the configuration information for TIM module.
00273   * @retval None
00274   */
00275 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00276 {
00277   /* Prevent unused argument(s) compilation warning */
00278   UNUSED(htim);
00279   /* NOTE : This function Should not be modified, when the callback is needed,
00280             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00281    */
00282 }
00283
00284 /**
00285   * @brief  Starts the TIM Hall Sensor Interface.
00286   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00287   *                the configuration information for TIM module.
00288   * @retval HAL status
00289   */
00290 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00291 {
00292   /* Check the parameters */
00293   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00294
00295   /* Enable the Input Capture channels 1
00296     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00297   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00298
00299   /* Enable the Peripheral */
00300   __HAL_TIM_ENABLE(htim);
00301
00302   /* Return function status */
00303   return HAL_OK;
00304 }
00305
00306 /**
00307   * @brief  Stops the TIM Hall sensor Interface.
00308   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00309   *                the configuration information for TIM module.
00310   * @retval HAL status
00311   */
00312 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00313 {
00314   /* Check the parameters */
00315   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00316
00317   /* Disable the Input Capture channels 1, 2 and 3
00318     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00319   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00320
00321   /* Disable the Peripheral */
00322   __HAL_TIM_DISABLE(htim);
00323
00324   /* Return function status */
00325   return HAL_OK;
00326 }
00327
00328 /**
00329   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00330   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00331   *                the configuration information for TIM module.
00332   * @retval HAL status
00333   */
00334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00335 {
00336   /* Check the parameters */
00337   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00338
00339   /* Enable the capture compare Interrupts 1 event */
00340   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00341
00342   /* Enable the Input Capture channels 1
00343     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00344   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00345
00346   /* Enable the Peripheral */
00347   __HAL_TIM_ENABLE(htim);
00348
00349   /* Return function status */
00350   return HAL_OK;
00351 }
00352
00353 /**
00354   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00355   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00356   *                the configuration information for TIM module.
00357   * @retval HAL status
00358   */
00359 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00360 {
00361   /* Check the parameters */
00362   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00363
00364   /* Disable the Input Capture channels 1
00365     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00366   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00367
00368   /* Disable the capture compare Interrupts event */
00369   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00370
00371   /* Disable the Peripheral */
00372   __HAL_TIM_DISABLE(htim);
00373
00374   /* Return function status */
00375   return HAL_OK;
00376 }
00377
00378 /**
00379   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00380   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00381   *                the configuration information for TIM module.
00382   * @param  pData: The destination Buffer address.
00383   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00387 {
00388   /* Check the parameters */
00389   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00390
00391    if((htim->State == HAL_TIM_STATE_BUSY))
00392   {
00393      return HAL_BUSY;
00394   }
00395   else if((htim->State == HAL_TIM_STATE_READY))
00396   {
00397     if(((uint32_t)pData == 0U) && (Length > 0U))
00398     {
00399       return HAL_ERROR;
00400     }
00401     else
00402     {
00403       htim->State = HAL_TIM_STATE_BUSY;
00404     }
00405   }
00406   /* Enable the Input Capture channels 1
00407     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00408   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00409
00410   /* Set the DMA Input Capture 1 Callback */
00411   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00412   /* Set the DMA error callback */
00413   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00414
00415   /* Enable the DMA Stream for Capture 1*/
00416   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
00417
00418   /* Enable the capture compare 1 Interrupt */
00419   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00420
00421   /* Enable the Peripheral */
00422   __HAL_TIM_ENABLE(htim);
00423
00424   /* Return function status */
00425   return HAL_OK;
00426 }
00427
00428 /**
00429   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00430   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00431   *                the configuration information for TIM module.
00432   * @retval HAL status
00433   */
00434 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00435 {
00436   /* Check the parameters */
00437   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00438
00439   /* Disable the Input Capture channels 1
00440     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00441   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00442
00443
00444   /* Disable the capture compare Interrupts 1 event */
00445   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00446
00447   /* Disable the Peripheral */
00448   __HAL_TIM_DISABLE(htim);
00449
00450   /* Return function status */
00451   return HAL_OK;
00452 }
00453 /**
00454   * @}
00455   */
00456
00457 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
00458  *  @brief    Timer Complementary Output Compare functions
00459  *
00460 @verbatim
00461   ==============================================================================
00462               ##### Timer Complementary Output Compare functions #####
00463   ==============================================================================
00464   [..]
00465     This section provides functions allowing to:
00466     (+) Start the Complementary Output Compare/PWM.
00467     (+) Stop the Complementary Output Compare/PWM.
00468     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00469     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00470     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00471     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00472
00473 @endverbatim
00474   * @{
00475   */
00476
00477 /**
00478   * @brief  Starts the TIM Output Compare signal generation on the complementary
00479   *         output.
00480   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00481   *                the configuration information for TIM module.
00482   * @param  Channel: TIM Channel to be enabled.
00483   *          This parameter can be one of the following values:
00484   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00485   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00486   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00487   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00488   * @retval HAL status
00489   */
00490 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00491 {
00492   /* Check the parameters */
00493   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00494
00495      /* Enable the Capture compare channel N */
00496      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00497
00498   /* Enable the Main Output */
00499     __HAL_TIM_MOE_ENABLE(htim);
00500
00501   /* Enable the Peripheral */
00502   __HAL_TIM_ENABLE(htim);
00503
00504   /* Return function status */
00505   return HAL_OK;
00506 }
00507
00508 /**
00509   * @brief  Stops the TIM Output Compare signal generation on the complementary
00510   *         output.
00511   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00512   *                the configuration information for TIM module.
00513   * @param  Channel: TIM Channel to be disabled.
00514   *          This parameter can be one of the following values:
00515   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00516   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00517   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00518   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00519   * @retval HAL status
00520   */
00521 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00522 {
00523   /* Check the parameters */
00524   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00525
00526     /* Disable the Capture compare channel N */
00527   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00528
00529   /* Disable the Main Output */
00530     __HAL_TIM_MOE_DISABLE(htim);
00531
00532   /* Disable the Peripheral */
00533   __HAL_TIM_DISABLE(htim);
00534
00535   /* Return function status */
00536   return HAL_OK;
00537 }
00538
00539 /**
00540   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00541   *         on the complementary output.
00542   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00543   *                the configuration information for TIM module.
00544   * @param  Channel: TIM Channel to be enabled.
00545   *          This parameter can be one of the following values:
00546   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00547   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00548   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00549   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00550   * @retval HAL status
00551   */
00552 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00553 {
00554   /* Check the parameters */
00555   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00556
00557   switch (Channel)
00558   {
00559     case TIM_CHANNEL_1:
00560     {
00561       /* Enable the TIM Output Compare interrupt */
00562       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00563     }
00564     break;
00565
00566     case TIM_CHANNEL_2:
00567     {
00568       /* Enable the TIM Output Compare interrupt */
00569       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00570     }
00571     break;
00572
00573     case TIM_CHANNEL_3:
00574     {
00575       /* Enable the TIM Output Compare interrupt */
00576       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00577     }
00578     break;
00579
00580     case TIM_CHANNEL_4:
00581     {
00582       /* Enable the TIM Output Compare interrupt */
00583       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00584     }
00585     break;
00586
00587     default:
00588     break;
00589   }
00590
00591   /* Enable the TIM Break interrupt */
00592   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00593
00594   /* Enable the Capture compare channel N */
00595   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00596
00597   /* Enable the Main Output */
00598   __HAL_TIM_MOE_ENABLE(htim);
00599
00600   /* Enable the Peripheral */
00601   __HAL_TIM_ENABLE(htim);
00602
00603   /* Return function status */
00604   return HAL_OK;
00605 }
00606
00607 /**
00608   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00609   *         on the complementary output.
00610   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00611   *                the configuration information for TIM module.
00612   * @param  Channel: TIM Channel to be disabled.
00613   *          This parameter can be one of the following values:
00614   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00615   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00616   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00617   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00618   * @retval HAL status
00619   */
00620 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00621 {
00622   /* Check the parameters */
00623   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00624
00625   switch (Channel)
00626   {
00627     case TIM_CHANNEL_1:
00628     {
00629       /* Disable the TIM Output Compare interrupt */
00630       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00631     }
00632     break;
00633
00634     case TIM_CHANNEL_2:
00635     {
00636       /* Disable the TIM Output Compare interrupt */
00637       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00638     }
00639     break;
00640
00641     case TIM_CHANNEL_3:
00642     {
00643       /* Disable the TIM Output Compare interrupt */
00644       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00645     }
00646     break;
00647
00648     case TIM_CHANNEL_4:
00649     {
00650       /* Disable the TIM Output Compare interrupt */
00651       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00652     }
00653     break;
00654
00655     default:
00656     break;
00657   }
00658
00659   /* Disable the Capture compare channel N */
00660   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00661
00662   /* Disable the TIM Break interrupt (only if no more channel is active) */
00663   if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
00664   {
00665     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00666   }
00667
00668   /* Disable the Main Output */
00669   __HAL_TIM_MOE_DISABLE(htim);
00670
00671   /* Disable the Peripheral */
00672   __HAL_TIM_DISABLE(htim);
00673
00674   /* Return function status */
00675   return HAL_OK;
00676 }
00677
00678 /**
00679   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00680   *         on the complementary output.
00681   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00682   *                the configuration information for TIM module.
00683   * @param  Channel: TIM Channel to be enabled.
00684   *          This parameter can be one of the following values:
00685   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00686   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00687   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00688   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00689   * @param  pData: The source Buffer address.
00690   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00691   * @retval HAL status
00692   */
00693 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00694 {
00695   /* Check the parameters */
00696   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00697
00698   if((htim->State == HAL_TIM_STATE_BUSY))
00699   {
00700      return HAL_BUSY;
00701   }
00702   else if((htim->State == HAL_TIM_STATE_READY))
00703   {
00704     if(((uint32_t)pData == 0U) && (Length > 0U))
00705     {
00706       return HAL_ERROR;
00707     }
00708     else
00709     {
00710       htim->State = HAL_TIM_STATE_BUSY;
00711     }
00712   }
00713   switch (Channel)
00714   {
00715     case TIM_CHANNEL_1:
00716     {
00717       /* Set the DMA Period elapsed callback */
00718       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00719
00720       /* Set the DMA error callback */
00721       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00722
00723       /* Enable the DMA Stream */
00724       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00725
00726       /* Enable the TIM Output Compare DMA request */
00727       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00728     }
00729     break;
00730
00731     case TIM_CHANNEL_2:
00732     {
00733       /* Set the DMA Period elapsed callback */
00734       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00735
00736       /* Set the DMA error callback */
00737       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00738
00739       /* Enable the DMA Stream */
00740       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00741
00742       /* Enable the TIM Output Compare DMA request */
00743       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00744     }
00745     break;
00746
00747     case TIM_CHANNEL_3:
00748 {
00749       /* Set the DMA Period elapsed callback */
00750       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00751
00752       /* Set the DMA error callback */
00753       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00754
00755       /* Enable the DMA Stream */
00756       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00757
00758       /* Enable the TIM Output Compare DMA request */
00759       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00760     }
00761     break;
00762
00763     case TIM_CHANNEL_4:
00764     {
00765      /* Set the DMA Period elapsed callback */
00766       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00767
00768       /* Set the DMA error callback */
00769       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00770
00771       /* Enable the DMA Stream */
00772       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00773
00774       /* Enable the TIM Output Compare DMA request */
00775       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00776     }
00777     break;
00778
00779     default:
00780     break;
00781   }
00782
00783   /* Enable the Capture compare channel N */
00784   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00785
00786   /* Enable the Main Output */
00787   __HAL_TIM_MOE_ENABLE(htim);
00788
00789   /* Enable the Peripheral */
00790   __HAL_TIM_ENABLE(htim);
00791
00792   /* Return function status */
00793   return HAL_OK;
00794 }
00795
00796 /**
00797   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00798   *         on the complementary output.
00799   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00800   *                the configuration information for TIM module.
00801   * @param  Channel: TIM Channel to be disabled.
00802   *          This parameter can be one of the following values:
00803   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00804   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00805   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00806   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00807   * @retval HAL status
00808   */
00809 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00810 {
00811   /* Check the parameters */
00812   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00813
00814   switch (Channel)
00815   {
00816     case TIM_CHANNEL_1:
00817     {
00818       /* Disable the TIM Output Compare DMA request */
00819       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00820     }
00821     break;
00822
00823     case TIM_CHANNEL_2:
00824     {
00825       /* Disable the TIM Output Compare DMA request */
00826       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00827     }
00828     break;
00829
00830     case TIM_CHANNEL_3:
00831     {
00832       /* Disable the TIM Output Compare DMA request */
00833       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00834     }
00835     break;
00836
00837     case TIM_CHANNEL_4:
00838     {
00839       /* Disable the TIM Output Compare interrupt */
00840       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00841     }
00842     break;
00843
00844     default:
00845     break;
00846   }
00847
00848   /* Disable the Capture compare channel N */
00849   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00850
00851   /* Disable the Main Output */
00852   __HAL_TIM_MOE_DISABLE(htim);
00853
00854   /* Disable the Peripheral */
00855   __HAL_TIM_DISABLE(htim);
00856
00857   /* Change the htim state */
00858   htim->State = HAL_TIM_STATE_READY;
00859
00860   /* Return function status */
00861   return HAL_OK;
00862 }
00863 /**
00864   * @}
00865   */
00866
00867 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
00868  *  @brief    Timer Complementary PWM functions
00869  *
00870 @verbatim
00871   ==============================================================================
00872                  ##### Timer Complementary PWM functions #####
00873   ==============================================================================
00874   [..]
00875     This section provides functions allowing to:
00876     (+) Start the Complementary PWM.
00877     (+) Stop the Complementary PWM.
00878     (+) Start the Complementary PWM and enable interrupts.
00879     (+) Stop the Complementary PWM and disable interrupts.
00880     (+) Start the Complementary PWM and enable DMA transfers.
00881     (+) Stop the Complementary PWM and disable DMA transfers.
00882     (+) Start the Complementary Input Capture measurement.
00883     (+) Stop the Complementary Input Capture.
00884     (+) Start the Complementary Input Capture and enable interrupts.
00885     (+) Stop the Complementary Input Capture and disable interrupts.
00886     (+) Start the Complementary Input Capture and enable DMA transfers.
00887     (+) Stop the Complementary Input Capture and disable DMA transfers.
00888     (+) Start the Complementary One Pulse generation.
00889     (+) Stop the Complementary One Pulse.
00890     (+) Start the Complementary One Pulse and enable interrupts.
00891     (+) Stop the Complementary One Pulse and disable interrupts.
00892
00893 @endverbatim
00894   * @{
00895   */
00896
00897 /**
00898   * @brief  Starts the PWM signal generation on the complementary output.
00899   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00900   *                the configuration information for TIM module.
00901   * @param  Channel: TIM Channel to be enabled.
00902   *          This parameter can be one of the following values:
00903   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00904   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00905   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00906   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00907   * @retval HAL status
00908   */
00909 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00910 {
00911   /* Check the parameters */
00912   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00913
00914   /* Enable the complementary PWM output  */
00915   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00916
00917   /* Enable the Main Output */
00918   __HAL_TIM_MOE_ENABLE(htim);
00919
00920   /* Enable the Peripheral */
00921   __HAL_TIM_ENABLE(htim);
00922
00923   /* Return function status */
00924   return HAL_OK;
00925 }
00926
00927 /**
00928   * @brief  Stops the PWM signal generation on the complementary output.
00929   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00930   *                the configuration information for TIM module.
00931   * @param  Channel: TIM Channel to be disabled.
00932   *          This parameter can be one of the following values:
00933   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00934   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00935   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00936   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00937   * @retval HAL status
00938   */
00939 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00940 {
00941   /* Check the parameters */
00942   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00943
00944   /* Disable the complementary PWM output  */
00945   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00946
00947   /* Disable the Main Output */
00948   __HAL_TIM_MOE_DISABLE(htim);
00949
00950   /* Disable the Peripheral */
00951   __HAL_TIM_DISABLE(htim);
00952
00953   /* Return function status */
00954   return HAL_OK;
00955 }
00956
00957 /**
00958   * @brief  Starts the PWM signal generation in interrupt mode on the
00959   *         complementary output.
00960   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
00961   *                the configuration information for TIM module.
00962   * @param  Channel: TIM Channel to be disabled.
00963   *          This parameter can be one of the following values:
00964   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00965   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00966   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00967   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00968   * @retval HAL status
00969   */
00970 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00971 {
00972   /* Check the parameters */
00973   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00974
00975   switch (Channel)
00976   {
00977     case TIM_CHANNEL_1:
00978     {
00979       /* Enable the TIM Capture/Compare 1 interrupt */
00980       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00981     }
00982     break;
00983
00984     case TIM_CHANNEL_2:
00985     {
00986       /* Enable the TIM Capture/Compare 2 interrupt */
00987       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00988     }
00989     break;
00990
00991     case TIM_CHANNEL_3:
00992     {
00993       /* Enable the TIM Capture/Compare 3 interrupt */
00994       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00995     }
00996     break;
00997
00998     case TIM_CHANNEL_4:
00999     {
01000       /* Enable the TIM Capture/Compare 4 interrupt */
01001       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01002     }
01003     break;
01004
01005     default:
01006     break;
01007   }
01008
01009   /* Enable the TIM Break interrupt */
01010   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01011
01012   /* Enable the complementary PWM output  */
01013   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01014
01015   /* Enable the Main Output */
01016   __HAL_TIM_MOE_ENABLE(htim);
01017
01018   /* Enable the Peripheral */
01019   __HAL_TIM_ENABLE(htim);
01020
01021   /* Return function status */
01022   return HAL_OK;
01023 }
01024
01025 /**
01026   * @brief  Stops the PWM signal generation in interrupt mode on the
01027   *         complementary output.
01028   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01029   *                the configuration information for TIM module.
01030   * @param  Channel: TIM Channel to be disabled.
01031   *          This parameter can be one of the following values:
01032   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01033   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01034   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01035   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01036   * @retval HAL status
01037   */
01038 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01039 {
01040   /* Check the parameters */
01041   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01042
01043   switch (Channel)
01044   {
01045     case TIM_CHANNEL_1:
01046     {
01047       /* Disable the TIM Capture/Compare 1 interrupt */
01048       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01049     }
01050     break;
01051
01052     case TIM_CHANNEL_2:
01053     {
01054       /* Disable the TIM Capture/Compare 2 interrupt */
01055       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01056     }
01057     break;
01058
01059     case TIM_CHANNEL_3:
01060     {
01061       /* Disable the TIM Capture/Compare 3 interrupt */
01062       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01063     }
01064     break;
01065
01066     case TIM_CHANNEL_4:
01067     {
01068       /* Disable the TIM Capture/Compare 3 interrupt */
01069       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01070     }
01071     break;
01072
01073     default:
01074     break;
01075   }
01076
01077   /* Disable the complementary PWM output  */
01078   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01079
01080   /* Disable the TIM Break interrupt (only if no more channel is active) */
01081   if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
01082   {
01083     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01084   }
01085
01086   /* Disable the Main Output */
01087   __HAL_TIM_MOE_DISABLE(htim);
01088
01089   /* Disable the Peripheral */
01090   __HAL_TIM_DISABLE(htim);
01091
01092   /* Return function status */
01093   return HAL_OK;
01094 }
01095
01096 /**
01097   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01098   *         complementary output
01099   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01100   *                the configuration information for TIM module.
01101   * @param  Channel: TIM Channel to be enabled.
01102   *          This parameter can be one of the following values:
01103   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01104   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01105   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01106   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01107   * @param  pData: The source Buffer address.
01108   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01109   * @retval HAL status
01110   */
01111 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01112 {
01113   /* Check the parameters */
01114   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01115
01116   if((htim->State == HAL_TIM_STATE_BUSY))
01117   {
01118      return HAL_BUSY;
01119   }
01120   else if((htim->State == HAL_TIM_STATE_READY))
01121   {
01122     if(((uint32_t)pData == 0U) && (Length > 0U))
01123     {
01124       return HAL_ERROR;
01125     }
01126     else
01127     {
01128       htim->State = HAL_TIM_STATE_BUSY;
01129     }
01130   }
01131   switch (Channel)
01132   {
01133     case TIM_CHANNEL_1:
01134     {
01135       /* Set the DMA Period elapsed callback */
01136       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01137
01138       /* Set the DMA error callback */
01139       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01140
01141       /* Enable the DMA Stream */
01142       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01143
01144       /* Enable the TIM Capture/Compare 1 DMA request */
01145       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01146     }
01147     break;
01148
01149     case TIM_CHANNEL_2:
01150     {
01151       /* Set the DMA Period elapsed callback */
01152       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01153
01154       /* Set the DMA error callback */
01155       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01156
01157       /* Enable the DMA Stream */
01158       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01159
01160       /* Enable the TIM Capture/Compare 2 DMA request */
01161       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01162     }
01163     break;
01164
01165     case TIM_CHANNEL_3:
01166     {
01167       /* Set the DMA Period elapsed callback */
01168       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01169
01170       /* Set the DMA error callback */
01171       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01172
01173       /* Enable the DMA Stream */
01174       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01175
01176       /* Enable the TIM Capture/Compare 3 DMA request */
01177       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01178     }
01179     break;
01180
01181     case TIM_CHANNEL_4:
01182     {
01183      /* Set the DMA Period elapsed callback */
01184       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01185
01186       /* Set the DMA error callback */
01187       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01188
01189       /* Enable the DMA Stream */
01190       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01191
01192       /* Enable the TIM Capture/Compare 4 DMA request */
01193       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01194     }
01195     break;
01196
01197     default:
01198     break;
01199   }
01200
01201   /* Enable the complementary PWM output  */
01202      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01203
01204   /* Enable the Main Output */
01205     __HAL_TIM_MOE_ENABLE(htim);
01206
01207   /* Enable the Peripheral */
01208   __HAL_TIM_ENABLE(htim);
01209
01210   /* Return function status */
01211   return HAL_OK;
01212 }
01213
01214 /**
01215   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01216   *         output
01217   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01218   *                the configuration information for TIM module.
01219   * @param  Channel: TIM Channel to be disabled.
01220   *          This parameter can be one of the following values:
01221   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01222   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01223   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01224   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01225   * @retval HAL status
01226   */
01227 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01228 {
01229   /* Check the parameters */
01230   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01231
01232   switch (Channel)
01233   {
01234     case TIM_CHANNEL_1:
01235     {
01236       /* Disable the TIM Capture/Compare 1 DMA request */
01237       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01238     }
01239     break;
01240
01241     case TIM_CHANNEL_2:
01242     {
01243       /* Disable the TIM Capture/Compare 2 DMA request */
01244       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01245     }
01246     break;
01247
01248     case TIM_CHANNEL_3:
01249     {
01250       /* Disable the TIM Capture/Compare 3 DMA request */
01251       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01252     }
01253     break;
01254
01255     case TIM_CHANNEL_4:
01256     {
01257       /* Disable the TIM Capture/Compare 4 DMA request */
01258       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01259     }
01260     break;
01261
01262     default:
01263     break;
01264   }
01265
01266   /* Disable the complementary PWM output */
01267     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01268
01269   /* Disable the Main Output */
01270     __HAL_TIM_MOE_DISABLE(htim);
01271
01272   /* Disable the Peripheral */
01273   __HAL_TIM_DISABLE(htim);
01274
01275   /* Change the htim state */
01276   htim->State = HAL_TIM_STATE_READY;
01277
01278   /* Return function status */
01279   return HAL_OK;
01280 }
01281
01282 /**
01283   * @}
01284   */
01285
01286 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
01287  *  @brief    Timer Complementary One Pulse functions
01288  *
01289 @verbatim
01290   ==============================================================================
01291                 ##### Timer Complementary One Pulse functions #####
01292   ==============================================================================
01293   [..]
01294     This section provides functions allowing to:
01295     (+) Start the Complementary One Pulse generation.
01296     (+) Stop the Complementary One Pulse.
01297     (+) Start the Complementary One Pulse and enable interrupts.
01298     (+) Stop the Complementary One Pulse and disable interrupts.
01299
01300 @endverbatim
01301   * @{
01302   */
01303
01304 /**
01305   * @brief  Starts the TIM One Pulse signal generation on the complementary
01306   *         output.
01307   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01308   *                the configuration information for TIM module.
01309   * @param  OutputChannel: TIM Channel to be enabled.
01310   *          This parameter can be one of the following values:
01311   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01312   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01313   * @retval HAL status
01314   */
01315 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01316   {
01317   /* Check the parameters */
01318   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01319
01320   /* Enable the complementary One Pulse output */
01321   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01322
01323   /* Enable the Main Output */
01324   __HAL_TIM_MOE_ENABLE(htim);
01325
01326   /* Return function status */
01327   return HAL_OK;
01328 }
01329
01330 /**
01331   * @brief  Stops the TIM One Pulse signal generation on the complementary
01332   *         output.
01333   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01334   *                the configuration information for TIM module.
01335   * @param  OutputChannel: TIM Channel to be disabled.
01336   *          This parameter can be one of the following values:
01337   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01338   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01339   * @retval HAL status
01340   */
01341 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01342 {
01343
01344   /* Check the parameters */
01345   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01346
01347   /* Disable the complementary One Pulse output */
01348     TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01349
01350   /* Disable the Main Output */
01351     __HAL_TIM_MOE_DISABLE(htim);
01352
01353   /* Disable the Peripheral */
01354   __HAL_TIM_DISABLE(htim);
01355
01356   /* Return function status */
01357   return HAL_OK;
01358 }
01359
01360 /**
01361   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01362   *         complementary channel.
01363   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01364   *                the configuration information for TIM module.
01365   * @param  OutputChannel: TIM Channel to be enabled.
01366   *          This parameter can be one of the following values:
01367   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01368   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01369   * @retval HAL status
01370   */
01371 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01372 {
01373   /* Check the parameters */
01374   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01375
01376   /* Enable the TIM Capture/Compare 1 interrupt */
01377   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01378
01379   /* Enable the TIM Capture/Compare 2 interrupt */
01380   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01381
01382   /* Enable the complementary One Pulse output */
01383   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01384
01385   /* Enable the Main Output */
01386   __HAL_TIM_MOE_ENABLE(htim);
01387
01388   /* Return function status */
01389   return HAL_OK;
01390   }
01391
01392 /**
01393   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01394   *         complementary channel.
01395   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01396   *                the configuration information for TIM module.
01397   * @param  OutputChannel: TIM Channel to be disabled.
01398   *          This parameter can be one of the following values:
01399   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01400   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01401   * @retval HAL status
01402   */
01403 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01404 {
01405   /* Check the parameters */
01406   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01407
01408   /* Disable the TIM Capture/Compare 1 interrupt */
01409   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01410
01411   /* Disable the TIM Capture/Compare 2 interrupt */
01412   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01413
01414   /* Disable the complementary One Pulse output */
01415   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01416
01417   /* Disable the Main Output */
01418   __HAL_TIM_MOE_DISABLE(htim);
01419
01420   /* Disable the Peripheral */
01421    __HAL_TIM_DISABLE(htim);
01422
01423   /* Return function status */
01424   return HAL_OK;
01425 }
01426 /**
01427   * @}
01428   */
01429
01430 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
01431  *  @brief      Peripheral Control functions
01432  *
01433 @verbatim
01434   ==============================================================================
01435                     ##### Peripheral Control functions #####
01436   ==============================================================================
01437   [..]
01438     This section provides functions allowing to:
01439     (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
01440     (+) Configure External Clock source.
01441     (+) Configure Complementary channels, break features and dead time.
01442     (+) Configure Master and the Slave synchronization.
01443     (+) Configure the commutation event in case of use of the Hall sensor interface.
01444     (+) Configure the DMA Burst Mode.
01445
01446 @endverbatim
01447   * @{
01448   */
01449 /**
01450   * @brief  Configure the TIM commutation event sequence.
01451   * @note  This function is mandatory to use the commutation event in order to
01452   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01453   *        the typical use of this feature is with the use of another Timer(interface Timer)
01454   *        configured in Hall sensor interface, this interface Timer will generate the
01455   *        commutation at its TRGO output (connected to Timer used in this function) each time
01456   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01457   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01458   *                the configuration information for TIM module.
01459   * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01460   *          This parameter can be one of the following values:
01461   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01462   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01463   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01464   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01465   *            @arg TIM_TS_NONE: No trigger is needed
01466   * @param  CommutationSource: the Commutation Event source.
01467   *          This parameter can be one of the following values:
01468   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01469   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01470   * @retval HAL status
01471   */
01472 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01473 {
01474   /* Check the parameters */
01475   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
01476   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01477
01478   __HAL_LOCK(htim);
01479
01480   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01481       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01482   {
01483     /* Select the Input trigger */
01484     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01485     htim->Instance->SMCR |= InputTrigger;
01486   }
01487
01488   /* Select the Capture Compare preload feature */
01489   htim->Instance->CR2 |= TIM_CR2_CCPC;
01490   /* Select the Commutation event source */
01491   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01492   htim->Instance->CR2 |= CommutationSource;
01493
01494   __HAL_UNLOCK(htim);
01495
01496   return HAL_OK;
01497 }
01498
01499 /**
01500   * @brief  Configure the TIM commutation event sequence with interrupt.
01501   * @note  This function is mandatory to use the commutation event in order to
01502   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01503   *        the typical use of this feature is with the use of another Timer(interface Timer)
01504   *        configured in Hall sensor interface, this interface Timer will generate the
01505   *        commutation at its TRGO output (connected to Timer used in this function) each time
01506   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01507   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01508   *                the configuration information for TIM module.
01509   * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01510   *          This parameter can be one of the following values:
01511   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01512   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01513   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01514   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01515   *            @arg TIM_TS_NONE: No trigger is needed
01516   * @param  CommutationSource: the Commutation Event source.
01517   *          This parameter can be one of the following values:
01518   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01519   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01520   * @retval HAL status
01521   */
01522 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01523 {
01524   /* Check the parameters */
01525   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
01526   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01527
01528   __HAL_LOCK(htim);
01529
01530   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01531       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01532   {
01533     /* Select the Input trigger */
01534     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01535     htim->Instance->SMCR |= InputTrigger;
01536   }
01537
01538   /* Select the Capture Compare preload feature */
01539   htim->Instance->CR2 |= TIM_CR2_CCPC;
01540   /* Select the Commutation event source */
01541   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01542   htim->Instance->CR2 |= CommutationSource;
01543
01544   /* Enable the Commutation Interrupt Request */
01545   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01546
01547   __HAL_UNLOCK(htim);
01548
01549   return HAL_OK;
01550 }
01551
01552 /**
01553   * @brief  Configure the TIM commutation event sequence with DMA.
01554   * @note  This function is mandatory to use the commutation event in order to
01555   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01556   *        the typical use of this feature is with the use of another Timer(interface Timer)
01557   *        configured in Hall sensor interface, this interface Timer will generate the
01558   *        commutation at its TRGO output (connected to Timer used in this function) each time
01559   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01560   * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
01561   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01562   *                the configuration information for TIM module.
01563   * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
01564   *          This parameter can be one of the following values:
01565   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01566   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01567   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01568   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01569   *            @arg TIM_TS_NONE: No trigger is needed
01570   * @param  CommutationSource: the Commutation Event source.
01571   *          This parameter can be one of the following values:
01572   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01573   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01574   * @retval HAL status
01575   */
01576 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01577 {
01578   /* Check the parameters */
01579   assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
01580   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01581
01582   __HAL_LOCK(htim);
01583
01584   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01585       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01586   {
01587     /* Select the Input trigger */
01588     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01589     htim->Instance->SMCR |= InputTrigger;
01590   }
01591
01592   /* Select the Capture Compare preload feature */
01593   htim->Instance->CR2 |= TIM_CR2_CCPC;
01594   /* Select the Commutation event source */
01595   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01596   htim->Instance->CR2 |= CommutationSource;
01597
01598   /* Enable the Commutation DMA Request */
01599   /* Set the DMA Commutation Callback */
01600   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01601   /* Set the DMA error callback */
01602   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01603
01604   /* Enable the Commutation DMA Request */
01605   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01606
01607   __HAL_UNLOCK(htim);
01608
01609   return HAL_OK;
01610 }
01611
01612 /**
01613   * @brief  Configures the TIM in master mode.
01614   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01615   *                the configuration information for TIM module.
01616   * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
01617   *         contains the selected trigger output (TRGO) and the Master/Slave
01618   *         mode.
01619   * @retval HAL status
01620   */
01621 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
01622 {
01623   /* Check the parameters */
01624   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
01625   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01626   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01627
01628   __HAL_LOCK(htim);
01629
01630   htim->State = HAL_TIM_STATE_BUSY;
01631
01632   /* Reset the MMS Bits */
01633   htim->Instance->CR2 &= ~TIM_CR2_MMS;
01634   /* Select the TRGO source */
01635   htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
01636
01637   /* Reset the MSM Bit */
01638   htim->Instance->SMCR &= ~TIM_SMCR_MSM;
01639   /* Set or Reset the MSM Bit */
01640   htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
01641
01642   htim->State = HAL_TIM_STATE_READY;
01643
01644   __HAL_UNLOCK(htim);
01645
01646   return HAL_OK;
01647 }
01648
01649 /**
01650   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01651   *         and the AOE(automatic output enable).
01652   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01653   *                the configuration information for TIM module.
01654   * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
01655   *         contains the BDTR Register configuration  information for the TIM peripheral.
01656   * @retval HAL status
01657   */
01658 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
01659                                               TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
01660 {
01661   /* Check the parameters */
01662   assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
01663   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
01664   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
01665   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
01666   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
01667   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
01668   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
01669   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
01670
01671   /* Process Locked */
01672   __HAL_LOCK(htim);
01673
01674   htim->State = HAL_TIM_STATE_BUSY;
01675
01676   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
01677      the OSSI State, the dead time value and the Automatic Output Enable Bit */
01678   htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode  |
01679                                    sBreakDeadTimeConfig->OffStateIDLEMode |
01680                                    sBreakDeadTimeConfig->LockLevel        |
01681                                    sBreakDeadTimeConfig->DeadTime         |
01682                                    sBreakDeadTimeConfig->BreakState       |
01683                                    sBreakDeadTimeConfig->BreakPolarity    |
01684                                    sBreakDeadTimeConfig->AutomaticOutput;
01685
01686
01687   htim->State = HAL_TIM_STATE_READY;
01688
01689   __HAL_UNLOCK(htim);
01690
01691   return HAL_OK;
01692 }
01693
01694 /**
01695   * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
01696   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01697   *                the configuration information for TIM module.
01698   * @param  Remap: specifies the TIM input remapping source.
01699   *          This parameter can be one of the following values:
01700   *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
01701   *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.
01702   *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
01703   *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
01704   *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
01705   *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
01706   *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
01707   *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
01708   *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default)
01709   *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
01710   *                                     (HSE divided by a programmable prescaler)
01711   * @retval HAL status
01712   */
01713 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
01714 {
01715   __HAL_LOCK(htim);
01716
01717   /* Check parameters */
01718   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
01719   assert_param(IS_TIM_REMAP(Remap));
01720
01721   /* Set the Timer remapping configuration */
01722   htim->Instance->OR = Remap;
01723
01724   htim->State = HAL_TIM_STATE_READY;
01725
01726   __HAL_UNLOCK(htim);
01727
01728   return HAL_OK;
01729 }
01730
01731 /**
01732   * @}
01733   */
01734
01735 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
01736  *  @brief   Extension Callbacks functions
01737  *
01738 @verbatim
01739   ==============================================================================
01740                     ##### Extension Callbacks functions #####
01741   ==============================================================================
01742   [..]
01743     This section provides Extension TIM callback functions:
01744     (+) Timer Commutation callback
01745     (+) Timer Break callback
01746
01747 @endverbatim
01748   * @{
01749   */
01750
01751 /**
01752   * @brief  Hall commutation changed callback in non blocking mode
01753   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01754   *                the configuration information for TIM module.
01755   * @retval None
01756   */
01757 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
01758 {
01759   /* Prevent unused argument(s) compilation warning */
01760   UNUSED(htim);
01761   /* NOTE : This function Should not be modified, when the callback is needed,
01762             the HAL_TIMEx_CommutationCallback could be implemented in the user file
01763    */
01764 }
01765
01766 /**
01767   * @brief  Hall Break detection callback in non blocking mode
01768   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01769   *                the configuration information for TIM module.
01770   * @retval None
01771   */
01772 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
01773 {
01774   /* Prevent unused argument(s) compilation warning */
01775   UNUSED(htim);
01776   /* NOTE : This function Should not be modified, when the callback is needed,
01777             the HAL_TIMEx_BreakCallback could be implemented in the user file
01778    */
01779 }
01780 /**
01781   * @}
01782   */
01783
01784 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
01785  *  @brief   Extension Peripheral State functions
01786  *
01787 @verbatim
01788   ==============================================================================
01789                 ##### Extension Peripheral State functions #####
01790   ==============================================================================
01791   [..]
01792     This subsection permits to get in run-time the status of the peripheral
01793     and the data flow.
01794
01795 @endverbatim
01796   * @{
01797   */
01798
01799 /**
01800   * @brief  Return the TIM Hall Sensor interface state
01801   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
01802   *                the configuration information for TIM module.
01803   * @retval HAL state
01804   */
01805 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
01806 {
01807   return htim->State;
01808 }
01809
01810 /**
01811   * @}
01812   */
01813
01814 /**
01815   * @brief  TIM DMA Commutation callback.
01816   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01817   *                the configuration information for the specified DMA module.
01818   * @retval None
01819   */
01820 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
01821 {
01822   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01823
01824   htim->State= HAL_TIM_STATE_READY;
01825
01826   HAL_TIMEx_CommutationCallback(htim);
01827 }
01828 /**
01829   * @}
01830   */
01831
01832 /**
01833   * @brief  Enables or disables the TIM Capture Compare Channel xN.
01834   * @param  TIMx to select the TIM peripheral
01835   * @param  Channel: specifies the TIM Channel
01836   *          This parameter can be one of the following values:
01837   *            @arg TIM_Channel_1: TIM Channel 1
01838   *            @arg TIM_Channel_2: TIM Channel 2
01839   *            @arg TIM_Channel_3: TIM Channel 3
01840   * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
01841   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
01842   * @retval None
01843   */
01844 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
01845 {
01846   uint32_t tmp = 0U;
01847
01848   /* Check the parameters */
01849   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01850   assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
01851
01852   tmp = TIM_CCER_CC1NE << Channel;
01853
01854   /* Reset the CCxNE Bit */
01855   TIMx->CCER &= ~tmp;
01856
01857   /* Set or reset the CCxNE Bit */
01858   TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
01859 }
01860
01861 /**
01862   * @}
01863   */
01864
01865 #endif /* HAL_TIM_MODULE_ENABLED */
01866 /**
01867   * @}
01868   */
01869
01870 /**
01871   * @}
01872   */
01873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_tim_ex.h Source File

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stm32f4xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of TIM HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_TIM_EX_H
00040 #define __STM32F4xx_HAL_TIM_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIMEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIMEx_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Hall sensor Configuration Structure definition
00064   */
00065
00066 typedef struct
00067 {
00068
00069   uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
00070                                         This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00071
00072   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00073                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00074
00075   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00076                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00077
00078   uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00079                                     This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
00080 } TIM_HallSensor_InitTypeDef;
00081
00082 /**
00083   * @brief  TIM Master configuration Structure definition
00084   */
00085 typedef struct {
00086   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection.
00087                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00088
00089   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection.
00090                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00091 }TIM_MasterConfigTypeDef;
00092
00093 /**
00094   * @brief  TIM Break and Dead time configuration Structure definition
00095   */
00096 typedef struct
00097 {
00098   uint32_t OffStateRunMode;            /*!< TIM off state in run mode.
00099                                          This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00100   uint32_t OffStateIDLEMode;          /*!< TIM off state in IDLE mode.
00101                                          This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00102   uint32_t LockLevel;                     /*!< TIM Lock level.
00103                                          This parameter can be a value of @ref TIM_Lock_level */
00104   uint32_t DeadTime;                     /*!< TIM dead Time.
00105                                          This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00106   uint32_t BreakState;                   /*!< TIM Break State.
00107                                          This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00108   uint32_t BreakPolarity;                 /*!< TIM Break input polarity.
00109                                          This parameter can be a value of @ref TIM_Break_Polarity */
00110   uint32_t AutomaticOutput;               /*!< TIM Automatic Output Enable state.
00111                                          This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00112 }TIM_BreakDeadTimeConfigTypeDef;
00113 /**
00114   * @}
00115   */
00116
00117 /* Exported constants --------------------------------------------------------*/
00118 /** @defgroup TIMEx_Exported_Constants  TIM Exported Constants
00119   * @{
00120   */
00121
00122 /** @defgroup TIMEx_Remap  TIM Remap
00123   * @{
00124   */
00125 #define TIM_TIM2_TIM8_TRGO                     (0x00000000U)
00126 #define TIM_TIM2_ETH_PTP                       (0x00000400U)
00127 #define TIM_TIM2_USBFS_SOF                     (0x00000800U)
00128 #define TIM_TIM2_USBHS_SOF                     (0x00000C00U)
00129 #define TIM_TIM5_GPIO                          (0x00000000U)
00130 #define TIM_TIM5_LSI                           (0x00000040U)
00131 #define TIM_TIM5_LSE                           (0x00000080U)
00132 #define TIM_TIM5_RTC                           (0x000000C0U)
00133 #define TIM_TIM11_GPIO                         (0x00000000U)
00134 #define TIM_TIM11_HSE                          (0x00000002U)
00135
00136 #if defined (STM32F446xx)
00137 #define TIM_TIM11_SPDIFRX                        (0x00000001U)
00138 #endif /* STM32F446xx */
00139 /**
00140   * @}
00141   */
00142
00143 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00144 /** @defgroup TIMEx_SystemBreakInput  TIM System Break Input
00145   * @{
00146   */
00147 #define TIM_SYSTEMBREAKINPUT_HARDFAULT     ((uint32_t)0x00000001U) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
00148 #define TIM_SYSTEMBREAKINPUT_PVD           ((uint32_t)0x00000004U) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
00149 #define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005U) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
00150 /**
00151   * @}
00152   */
00153 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00154
00155 /**
00156   * @}
00157   */
00158 /* Exported macro ------------------------------------------------------------*/
00159 /* Exported functions --------------------------------------------------------*/
00160 /** @addtogroup TIMEx_Exported_Functions
00161   * @{
00162   */
00163
00164 /** @addtogroup TIMEx_Exported_Functions_Group1
00165   * @{
00166   */
00167 /*  Timer Hall Sensor functions  **********************************************/
00168 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
00169 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
00170
00171 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
00172 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
00173
00174  /* Blocking mode: Polling */
00175 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
00176 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
00177 /* Non-Blocking mode: Interrupt */
00178 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
00179 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
00180 /* Non-Blocking mode: DMA */
00181 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
00182 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
00183 /**
00184   * @}
00185   */
00186
00187 /** @addtogroup TIMEx_Exported_Functions_Group2
00188   * @{
00189   */
00190 /*  Timer Complementary Output Compare functions  *****************************/
00191 /* Blocking mode: Polling */
00192 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
00193 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
00194
00195 /* Non-Blocking mode: Interrupt */
00196 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00197 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00198
00199 /* Non-Blocking mode: DMA */
00200 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00201 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
00202 /**
00203   * @}
00204   */
00205
00206 /** @addtogroup TIMEx_Exported_Functions_Group3
00207   * @{
00208   */
00209 /*  Timer Complementary PWM functions  ****************************************/
00210 /* Blocking mode: Polling */
00211 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
00212 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
00213
00214 /* Non-Blocking mode: Interrupt */
00215 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00216 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
00217 /* Non-Blocking mode: DMA */
00218 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00219 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
00220 /**
00221   * @}
00222   */
00223
00224 /** @addtogroup TIMEx_Exported_Functions_Group4
00225   * @{
00226   */
00227 /*  Timer Complementary One Pulse functions  **********************************/
00228 /* Blocking mode: Polling */
00229 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00230 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00231
00232 /* Non-Blocking mode: Interrupt */
00233 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00234 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
00235 /**
00236   * @}
00237   */
00238
00239 /** @addtogroup TIMEx_Exported_Functions_Group5
00240   * @{
00241   */
00242 /* Extension Control functions  ************************************************/
00243 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00244 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00245 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00246 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
00247 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00248 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
00249 /**
00250   * @}
00251   */
00252
00253 /** @addtogroup TIMEx_Exported_Functions_Group6
00254   * @{
00255   */
00256 /* Extension Callback *********************************************************/
00257 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
00258 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
00259 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00260 /**
00261   * @}
00262   */
00263
00264 /** @addtogroup TIMEx_Exported_Functions_Group7
00265   * @{
00266   */
00267 /* Extension Peripheral State functions  **************************************/
00268 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /* Private types -------------------------------------------------------------*/
00278 /* Private variables ---------------------------------------------------------*/
00279 /* Private constants ---------------------------------------------------------*/
00280 /* Private macros ------------------------------------------------------------*/
00281 /** @defgroup TIMEx_Private_Macros TIM Private Macros
00282   * @{
00283   */
00284 #if defined (STM32F446xx)
00285 #define IS_TIM_REMAP(TIM_REMAP)   (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
00286                                   ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
00287                                   ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
00288                                   ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
00289                                   ((TIM_REMAP) == TIM_TIM5_GPIO)||\
00290                                   ((TIM_REMAP) == TIM_TIM5_LSI)||\
00291                                   ((TIM_REMAP) == TIM_TIM5_LSE)||\
00292                                   ((TIM_REMAP) == TIM_TIM5_RTC)||\
00293                                   ((TIM_REMAP) == TIM_TIM11_GPIO)||\
00294                                   ((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
00295                                   ((TIM_REMAP) == TIM_TIM11_HSE))
00296 #else
00297 #define IS_TIM_REMAP(TIM_REMAP)   (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
00298                                   ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
00299                                   ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
00300                                   ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
00301                                   ((TIM_REMAP) == TIM_TIM5_GPIO)||\
00302                                   ((TIM_REMAP) == TIM_TIM5_LSI)||\
00303                                   ((TIM_REMAP) == TIM_TIM5_LSE)||\
00304                                   ((TIM_REMAP) == TIM_TIM5_RTC)||\
00305                                   ((TIM_REMAP) == TIM_TIM11_GPIO)||\
00306                                   ((TIM_REMAP) == TIM_TIM11_HSE))
00307 #endif /* STM32F446xx */
00308
00309 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
00310 #define IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT)   (((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\
00311                                                ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\
00312                                                ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD))
00313
00314 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
00315
00316 #define IS_TIM_DEADTIME(DEADTIME)      ((DEADTIME) <= 0xFFU)
00317 /**
00318   * @}
00319   */
00320
00321 /* Private functions ---------------------------------------------------------*/
00322 /** @defgroup TIMEx_Private_Functions TIM Private Functions
00323   * @{
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342 #endif /* __STM32F4xx_HAL_TIM_EX_H */
00343
00344 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_uart.c Source File

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stm32f4xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   UART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     The UART HAL driver can be used as follows:
00021
00022     (#) Declare a UART_HandleTypeDef handle structure.
00023
00024     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00025         (##) Enable the USARTx interface clock.
00026         (##) UART pins configuration:
00027             (+++) Enable the clock for the UART GPIOs.
00028             (+++) Configure these UART pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00030              and HAL_UART_Receive_IT() APIs):
00031             (+++) Configure the USARTx interrupt priority.
00032             (+++) Enable the NVIC USART IRQ handle.
00033         (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00034              and HAL_UART_Receive_DMA() APIs):
00035             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00036             (+++) Enable the DMAx interface clock.
00037             (+++) Configure the declared DMA handle structure with the required
00038                   Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx Stream.
00040             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete
00042                   interrupt on the DMA Tx/Rx Stream.
00043
00044     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00045         flow control and Mode(Receiver/Transmitter) in the Init structure.
00046
00047     (#) For the UART asynchronous mode, initialize the UART registers by calling
00048         the HAL_UART_Init() API.
00049
00050     (#) For the UART Half duplex mode, initialize the UART registers by calling
00051         the HAL_HalfDuplex_Init() API.
00052
00053     (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
00054
00055     (#) For the Multi-Processor mode, initialize the UART registers by calling
00056         the HAL_MultiProcessor_Init() API.
00057
00058      [..]
00059        (@) The specific UART interrupts (Transmission complete interrupt,
00060             RXNE interrupt and Error Interrupts) will be managed using the macros
00061             __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
00062             and receive process.
00063
00064      [..]
00065        (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
00066             low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
00067             HAL_UART_MspInit() API.
00068
00069      [..]
00070         Three operation modes are available within this driver :
00071
00072      *** Polling mode IO operation ***
00073      =================================
00074      [..]
00075        (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
00076        (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
00077
00078      *** Interrupt mode IO operation ***
00079      ===================================
00080      [..]
00081        (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
00082        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00083             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00084        (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
00085        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00086             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00087        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00088             add his own code by customization of function pointer HAL_UART_ErrorCallback
00089
00090      *** DMA mode IO operation ***
00091      ==============================
00092      [..]
00093        (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
00094        (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
00095             add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
00096        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00097             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00098        (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
00099        (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
00100             add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
00101        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00102             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00103        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00104             add his own code by customization of function pointer HAL_UART_ErrorCallback
00105        (+) Pause the DMA Transfer using HAL_UART_DMAPause()
00106        (+) Resume the DMA Transfer using HAL_UART_DMAResume()
00107        (+) Stop the DMA Transfer using HAL_UART_DMAStop()
00108
00109      *** UART HAL driver macros list ***
00110      =============================================
00111      [..]
00112        Below the list of most used macros in UART HAL driver.
00113
00114       (+) __HAL_UART_ENABLE: Enable the UART peripheral
00115       (+) __HAL_UART_DISABLE: Disable the UART peripheral
00116       (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
00117       (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
00118       (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
00119       (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
00120       (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
00121
00122      [..]
00123        (@) You can refer to the UART HAL driver header file for more useful macros
00124
00125   @endverbatim
00126   ******************************************************************************
00127   * @attention
00128   *
00129   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00130   *
00131   * Redistribution and use in source and binary forms, with or without modification,
00132   * are permitted provided that the following conditions are met:
00133   *   1. Redistributions of source code must retain the above copyright notice,
00134   *      this list of conditions and the following disclaimer.
00135   *   2. Redistributions in binary form must reproduce the above copyright notice,
00136   *      this list of conditions and the following disclaimer in the documentation
00137   *      and/or other materials provided with the distribution.
00138   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00139   *      may be used to endorse or promote products derived from this software
00140   *      without specific prior written permission.
00141   *
00142   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00143   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00144   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00145   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00146   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00147   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00148   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00149   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00150   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00151   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00152   *
00153   ******************************************************************************
00154   */
00155
00156 /* Includes ------------------------------------------------------------------*/
00157 #include "stm32f4xx_hal.h"
00158
00159 /** @addtogroup STM32F4xx_HAL_Driver
00160   * @{
00161   */
00162
00163 /** @defgroup UART UART
00164   * @brief HAL UART module driver
00165   * @{
00166   */
00167 #ifdef HAL_UART_MODULE_ENABLED
00168
00169 /* Private typedef -----------------------------------------------------------*/
00170 /* Private define ------------------------------------------------------------*/
00171 /** @addtogroup UART_Private_Constants
00172   * @{
00173   */
00174 /**
00175   * @}
00176   */
00177 /* Private macro -------------------------------------------------------------*/
00178 /* Private variables ---------------------------------------------------------*/
00179 /* Private function prototypes -----------------------------------------------*/
00180 /** @addtogroup UART_Private_Functions   UART Private Functions
00181   * @{
00182   */
00183 static void UART_SetConfig (UART_HandleTypeDef *huart);
00184 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
00185 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00186 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
00187 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00188 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00189 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00190 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00191 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00192 static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00193 /**
00194   * @}
00195   */
00196
00197 /* Exported functions ---------------------------------------------------------*/
00198 /** @defgroup UART_Exported_Functions UART Exported Functions
00199   * @{
00200   */
00201
00202 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00203   *  @brief    Initialization and Configuration functions
00204   *
00205 @verbatim
00206 ===============================================================================
00207             ##### Initialization and Configuration functions #####
00208  ===============================================================================
00209     [..]
00210     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00211     in asynchronous mode.
00212       (+) For the asynchronous mode only these parameters can be configured:
00213         (++) Baud Rate
00214         (++) Word Length
00215         (++) Stop Bit
00216         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00217              in the data register is transmitted but is changed by the parity bit.
00218              Depending on the frame length defined by the M bit (8-bits or 9-bits),
00219              please refer to Reference manual for possible UART frame formats.
00220         (++) Hardware flow control
00221         (++) Receiver/transmitter modes
00222         (++) Over Sampling Method
00223     [..]
00224     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
00225     follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
00226     configuration procedures (details for the procedures are available in reference manual (RM0329)).
00227
00228 @endverbatim
00229   * @{
00230   */
00231
00232 /**
00233   * @brief  Initializes the UART mode according to the specified parameters in
00234   *         the UART_InitTypeDef and create the associated handle.
00235   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00236   *                the configuration information for the specified UART module.
00237   * @retval HAL status
00238   */
00239 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00240 {
00241   /* Check the UART handle allocation */
00242   if(huart == NULL)
00243   {
00244     return HAL_ERROR;
00245   }
00246
00247   /* Check the parameters */
00248   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00249   {
00250     /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
00251     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00252     assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
00253   }
00254   else
00255   {
00256     assert_param(IS_UART_INSTANCE(huart->Instance));
00257   }
00258   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
00259   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
00260
00261   if(huart->gState == HAL_UART_STATE_RESET)
00262   {
00263     /* Allocate lock resource and initialize it */
00264     huart->Lock = HAL_UNLOCKED;
00265     /* Init the low level hardware */
00266     HAL_UART_MspInit(huart);
00267   }
00268
00269   huart->gState = HAL_UART_STATE_BUSY;
00270
00271   /* Disable the peripheral */
00272   __HAL_UART_DISABLE(huart);
00273
00274   /* Set the UART Communication parameters */
00275   UART_SetConfig(huart);
00276
00277   /* In asynchronous mode, the following bits must be kept cleared:
00278      - LINEN and CLKEN bits in the USART_CR2 register,
00279      - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00280   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00281   huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00282
00283   /* Enable the peripheral */
00284   __HAL_UART_ENABLE(huart);
00285
00286   /* Initialize the UART state */
00287   huart->ErrorCode = HAL_UART_ERROR_NONE;
00288   huart->gState= HAL_UART_STATE_READY;
00289   huart->RxState= HAL_UART_STATE_READY;
00290
00291   return HAL_OK;
00292 }
00293
00294 /**
00295   * @brief  Initializes the half-duplex mode according to the specified
00296   *         parameters in the UART_InitTypeDef and create the associated handle.
00297   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00298   *                the configuration information for the specified UART module.
00299   * @retval HAL status
00300   */
00301 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00302 {
00303   /* Check the UART handle allocation */
00304   if(huart == NULL)
00305   {
00306     return HAL_ERROR;
00307   }
00308
00309   /* Check the parameters */
00310   assert_param(IS_UART_INSTANCE(huart->Instance));
00311   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
00312   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
00313
00314   if(huart->gState == HAL_UART_STATE_RESET)
00315   {
00316     /* Allocate lock resource and initialize it */
00317     huart->Lock = HAL_UNLOCKED;
00318     /* Init the low level hardware */
00319     HAL_UART_MspInit(huart);
00320   }
00321
00322   huart->gState = HAL_UART_STATE_BUSY;
00323
00324   /* Disable the peripheral */
00325   __HAL_UART_DISABLE(huart);
00326
00327   /* Set the UART Communication parameters */
00328   UART_SetConfig(huart);
00329
00330   /* In half-duplex mode, the following bits must be kept cleared:
00331      - LINEN and CLKEN bits in the USART_CR2 register,
00332      - SCEN and IREN bits in the USART_CR3 register.*/
00333   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00334   huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
00335
00336   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00337   huart->Instance->CR3 |= USART_CR3_HDSEL;
00338
00339   /* Enable the peripheral */
00340   __HAL_UART_ENABLE(huart);
00341
00342   /* Initialize the UART state*/
00343   huart->ErrorCode = HAL_UART_ERROR_NONE;
00344   huart->gState= HAL_UART_STATE_READY;
00345   huart->RxState= HAL_UART_STATE_READY;
00346
00347   return HAL_OK;
00348 }
00349
00350 /**
00351   * @brief  Initializes the LIN mode according to the specified
00352   *         parameters in the UART_InitTypeDef and create the associated handle.
00353   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00354   *                the configuration information for the specified UART module.
00355   * @param  BreakDetectLength: Specifies the LIN break detection length.
00356   *         This parameter can be one of the following values:
00357   *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
00358   *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00362 {
00363   /* Check the UART handle allocation */
00364   if(huart == NULL)
00365   {
00366     return HAL_ERROR;
00367   }
00368
00369   /* Check the parameters */
00370   assert_param(IS_UART_INSTANCE(huart->Instance));
00371   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00372   assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
00373   assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
00374
00375   if(huart->gState == HAL_UART_STATE_RESET)
00376   {
00377     /* Allocate lock resource and initialize it */
00378     huart->Lock = HAL_UNLOCKED;
00379     /* Init the low level hardware */
00380     HAL_UART_MspInit(huart);
00381   }
00382
00383   huart->gState = HAL_UART_STATE_BUSY;
00384
00385   /* Disable the peripheral */
00386   __HAL_UART_DISABLE(huart);
00387
00388   /* Set the UART Communication parameters */
00389   UART_SetConfig(huart);
00390
00391   /* In LIN mode, the following bits must be kept cleared:
00392      - LINEN and CLKEN bits in the USART_CR2 register,
00393      - SCEN and IREN bits in the USART_CR3 register.*/
00394   huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
00395   huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
00396
00397   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00398   huart->Instance->CR2 |= USART_CR2_LINEN;
00399
00400   /* Set the USART LIN Break detection length. */
00401   huart->Instance->CR2 &= ~(USART_CR2_LBDL);
00402   huart->Instance->CR2 |= BreakDetectLength;
00403
00404   /* Enable the peripheral */
00405   __HAL_UART_ENABLE(huart);
00406
00407   /* Initialize the UART state*/
00408   huart->ErrorCode = HAL_UART_ERROR_NONE;
00409   huart->gState= HAL_UART_STATE_READY;
00410   huart->RxState= HAL_UART_STATE_READY;
00411
00412   return HAL_OK;
00413 }
00414
00415 /**
00416   * @brief  Initializes the Multi-Processor mode according to the specified
00417   *         parameters in the UART_InitTypeDef and create the associated handle.
00418   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00419   *                the configuration information for the specified UART module.
00420   * @param  Address: USART address
00421   * @param  WakeUpMethod: specifies the USART wake-up method.
00422   *          This parameter can be one of the following values:
00423   *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
00424   *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
00425   * @retval HAL status
00426   */
00427 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00428 {
00429   /* Check the UART handle allocation */
00430   if(huart == NULL)
00431   {
00432     return HAL_ERROR;
00433   }
00434
00435   /* Check the parameters */
00436   assert_param(IS_UART_INSTANCE(huart->Instance));
00437   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00438   assert_param(IS_UART_ADDRESS(Address));
00439   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
00440   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
00441
00442   if(huart->gState == HAL_UART_STATE_RESET)
00443   {
00444     /* Allocate lock resource and initialize it */
00445     huart->Lock = HAL_UNLOCKED;
00446     /* Init the low level hardware */
00447     HAL_UART_MspInit(huart);
00448   }
00449
00450   huart->gState = HAL_UART_STATE_BUSY;
00451
00452   /* Disable the peripheral */
00453   __HAL_UART_DISABLE(huart);
00454
00455   /* Set the UART Communication parameters */
00456   UART_SetConfig(huart);
00457
00458   /* In Multi-Processor mode, the following bits must be kept cleared:
00459      - LINEN and CLKEN bits in the USART_CR2 register,
00460      - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
00461   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00462   huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00463
00464   /* Clear the USART address */
00465   huart->Instance->CR2 &= ~(USART_CR2_ADD);
00466   /* Set the USART address node */
00467   huart->Instance->CR2 |= Address;
00468
00469   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00470   huart->Instance->CR1 &= ~(USART_CR1_WAKE);
00471   huart->Instance->CR1 |= WakeUpMethod;
00472
00473   /* Enable the peripheral */
00474   __HAL_UART_ENABLE(huart);
00475
00476   /* Initialize the UART state */
00477   huart->ErrorCode = HAL_UART_ERROR_NONE;
00478   huart->gState= HAL_UART_STATE_READY;
00479   huart->RxState= HAL_UART_STATE_READY;
00480
00481   return HAL_OK;
00482 }
00483
00484 /**
00485   * @brief  DeInitializes the UART peripheral.
00486   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00487   *                the configuration information for the specified UART module.
00488   * @retval HAL status
00489   */
00490 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00491 {
00492   /* Check the UART handle allocation */
00493   if(huart == NULL)
00494   {
00495     return HAL_ERROR;
00496   }
00497
00498   /* Check the parameters */
00499   assert_param(IS_UART_INSTANCE(huart->Instance));
00500
00501   huart->gState = HAL_UART_STATE_BUSY;
00502
00503   /* DeInit the low level hardware */
00504   HAL_UART_MspDeInit(huart);
00505
00506   huart->ErrorCode = HAL_UART_ERROR_NONE;
00507   huart->gState = HAL_UART_STATE_RESET;
00508   huart->RxState = HAL_UART_STATE_RESET;
00509
00510   /* Process Lock */
00511   __HAL_UNLOCK(huart);
00512
00513   return HAL_OK;
00514 }
00515
00516 /**
00517   * @brief  UART MSP Init.
00518   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00519   *                the configuration information for the specified UART module.
00520   * @retval None
00521   */
00522  __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00523 {
00524    /* Prevent unused argument(s) compilation warning */
00525   UNUSED(huart);
00526   /* NOTE: This function Should not be modified, when the callback is needed,
00527            the HAL_UART_MspInit could be implemented in the user file
00528    */
00529 }
00530
00531 /**
00532   * @brief  UART MSP DeInit.
00533   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00534   *                the configuration information for the specified UART module.
00535   * @retval None
00536   */
00537  __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00538 {
00539   /* Prevent unused argument(s) compilation warning */
00540   UNUSED(huart);
00541   /* NOTE: This function Should not be modified, when the callback is needed,
00542            the HAL_UART_MspDeInit could be implemented in the user file
00543    */
00544 }
00545
00546 /**
00547   * @}
00548   */
00549
00550 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00551   *  @brief UART Transmit and Receive functions
00552   *
00553 @verbatim
00554   ==============================================================================
00555                       ##### IO operation functions #####
00556   ==============================================================================
00557   [..]
00558     This subsection provides a set of functions allowing to manage the UART asynchronous
00559     and Half duplex data transfers.
00560
00561     (#) There are two modes of transfer:
00562        (++) Blocking mode: The communication is performed in polling mode.
00563             The HAL status of all data processing is returned by the same function
00564             after finishing transfer.
00565        (++) Non blocking mode: The communication is performed using Interrupts
00566             or DMA, these APIs return the HAL status.
00567             The end of the data processing will be indicated through the
00568             dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00569             using DMA mode.
00570             The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00571             will be executed respectively at the end of the transmit or receive process.
00572             The HAL_UART_ErrorCallback() user callback will be executed when
00573             a communication error is detected.
00574
00575     (#) Blocking mode APIs are:
00576         (++) HAL_UART_Transmit()
00577         (++) HAL_UART_Receive()
00578
00579     (#) Non Blocking mode APIs with Interrupt are:
00580         (++) HAL_UART_Transmit_IT()
00581         (++) HAL_UART_Receive_IT()
00582         (++) HAL_UART_IRQHandler()
00583
00584     (#) Non Blocking mode functions with DMA are:
00585         (++) HAL_UART_Transmit_DMA()
00586         (++) HAL_UART_Receive_DMA()
00587
00588     (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
00589         (++) HAL_UART_TxCpltCallback()
00590         (++) HAL_UART_RxCpltCallback()
00591         (++) HAL_UART_ErrorCallback()
00592
00593     [..]
00594       (@) In the Half duplex communication, it is forbidden to run the transmit
00595           and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
00596           can't be useful.
00597
00598 @endverbatim
00599   * @{
00600   */
00601
00602 /**
00603   * @brief  Sends an amount of data in blocking mode.
00604   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00605   *                the configuration information for the specified UART module.
00606   * @param  pData: Pointer to data buffer
00607   * @param  Size: Amount of data to be sent
00608   * @param  Timeout: Timeout duration
00609   * @retval HAL status
00610   */
00611 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00612 {
00613   uint16_t* tmp;
00614
00615   /* Check that a Tx process is not already ongoing */
00616   if(huart->gState == HAL_UART_STATE_READY)
00617   {
00618     if((pData == NULL ) || (Size == 0U))
00619     {
00620       return  HAL_ERROR;
00621     }
00622
00623     /* Process Locked */
00624     __HAL_LOCK(huart);
00625
00626     huart->ErrorCode = HAL_UART_ERROR_NONE;
00627     huart->gState = HAL_UART_STATE_BUSY_TX;
00628
00629     huart->TxXferSize = Size;
00630     huart->TxXferCount = Size;
00631     while(huart->TxXferCount > 0U)
00632     {
00633       huart->TxXferCount--;
00634       if(huart->Init.WordLength == UART_WORDLENGTH_9B)
00635       {
00636         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00637         {
00638           return HAL_TIMEOUT;
00639         }
00640         tmp = (uint16_t*) pData;
00641         huart->Instance->DR = (*tmp & (uint16_t)0x01FFU);
00642         if(huart->Init.Parity == UART_PARITY_NONE)
00643         {
00644           pData +=2U;
00645         }
00646         else
00647         {
00648           pData +=1U;
00649         }
00650       }
00651       else
00652       {
00653         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00654         {
00655           return HAL_TIMEOUT;
00656         }
00657         huart->Instance->DR = (*pData++ & (uint8_t)0xFFU);
00658       }
00659     }
00660
00661     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
00662     {
00663       return HAL_TIMEOUT;
00664     }
00665
00666     /* At end of Tx process, restore huart->gState to Ready */
00667       huart->gState = HAL_UART_STATE_READY;
00668
00669     /* Process Unlocked */
00670     __HAL_UNLOCK(huart);
00671
00672     return HAL_OK;
00673   }
00674   else
00675   {
00676     return HAL_BUSY;
00677   }
00678 }
00679
00680 /**
00681   * @brief  Receives an amount of data in blocking mode.
00682   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00683   *                the configuration information for the specified UART module.
00684   * @param  pData: Pointer to data buffer
00685   * @param  Size: Amount of data to be received
00686   * @param  Timeout: Timeout duration
00687   * @retval HAL status
00688   */
00689 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00690 {
00691   uint16_t* tmp;
00692
00693   /* Check that a Rx process is not already ongoing */
00694   if(huart->RxState == HAL_UART_STATE_READY)
00695   {
00696     if((pData == NULL ) || (Size == 0U))
00697     {
00698       return  HAL_ERROR;
00699     }
00700
00701     /* Process Locked */
00702     __HAL_LOCK(huart);
00703
00704     huart->ErrorCode = HAL_UART_ERROR_NONE;
00705     huart->RxState = HAL_UART_STATE_BUSY_RX;
00706
00707     huart->RxXferSize = Size;
00708     huart->RxXferCount = Size;
00709
00710     /* Check the remain data to be received */
00711     while(huart->RxXferCount > 0U)
00712     {
00713       huart->RxXferCount--;
00714       if(huart->Init.WordLength == UART_WORDLENGTH_9B)
00715       {
00716         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00717         {
00718           return HAL_TIMEOUT;
00719         }
00720         tmp = (uint16_t*) pData;
00721         if(huart->Init.Parity == UART_PARITY_NONE)
00722         {
00723           *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FFU);
00724           pData +=2U;
00725         }
00726         else
00727         {
00728           *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FFU);
00729           pData +=1U;
00730         }
00731
00732       }
00733       else
00734       {
00735         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00736         {
00737           return HAL_TIMEOUT;
00738         }
00739         if(huart->Init.Parity == UART_PARITY_NONE)
00740         {
00741           *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FFU);
00742         }
00743         else
00744         {
00745           *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007FU);
00746         }
00747
00748       }
00749     }
00750
00751     /* At end of Rx process, restore huart->RxState to Ready */
00752     huart->RxState = HAL_UART_STATE_READY;
00753
00754     /* Process Unlocked */
00755     __HAL_UNLOCK(huart);
00756
00757     return HAL_OK;
00758   }
00759   else
00760   {
00761     return HAL_BUSY;
00762   }
00763 }
00764
00765 /**
00766   * @brief  Sends an amount of data in non blocking mode.
00767   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00768   *                the configuration information for the specified UART module.
00769   * @param  pData: Pointer to data buffer
00770   * @param  Size: Amount of data to be sent
00771   * @retval HAL status
00772   */
00773 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00774 {
00775   /* Check that a Tx process is not already ongoing */
00776   if(huart->gState == HAL_UART_STATE_READY)
00777   {
00778     if((pData == NULL ) || (Size == 0U))
00779     {
00780       return HAL_ERROR;
00781     }
00782
00783     /* Process Locked */
00784     __HAL_LOCK(huart);
00785
00786     huart->pTxBuffPtr = pData;
00787     huart->TxXferSize = Size;
00788     huart->TxXferCount = Size;
00789
00790     huart->ErrorCode = HAL_UART_ERROR_NONE;
00791     huart->gState = HAL_UART_STATE_BUSY_TX;
00792
00793     /* Process Unlocked */
00794     __HAL_UNLOCK(huart);
00795
00796     /* Enable the UART Transmit data register empty Interrupt */
00797     __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
00798
00799     return HAL_OK;
00800   }
00801   else
00802   {
00803     return HAL_BUSY;
00804   }
00805 }
00806
00807 /**
00808   * @brief  Receives an amount of data in non blocking mode
00809   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00810   *                the configuration information for the specified UART module.
00811   * @param  pData: Pointer to data buffer
00812   * @param  Size: Amount of data to be received
00813   * @retval HAL status
00814   */
00815 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00816 {
00817   /* Check that a Rx process is not already ongoing */
00818   if(huart->RxState == HAL_UART_STATE_READY)
00819   {
00820     if((pData == NULL ) || (Size == 0U))
00821     {
00822       return HAL_ERROR;
00823     }
00824
00825     /* Process Locked */
00826     __HAL_LOCK(huart);
00827
00828     huart->pRxBuffPtr = pData;
00829     huart->RxXferSize = Size;
00830     huart->RxXferCount = Size;
00831
00832     huart->ErrorCode = HAL_UART_ERROR_NONE;
00833     huart->RxState = HAL_UART_STATE_BUSY_RX;
00834
00835     /* Enable the UART Parity Error Interrupt */
00836     __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
00837
00838     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00839     __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
00840
00841     /* Process Unlocked */
00842     __HAL_UNLOCK(huart);
00843
00844     /* Enable the UART Data Register not empty Interrupt */
00845     __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
00846
00847     return HAL_OK;
00848   }
00849   else
00850   {
00851     return HAL_BUSY;
00852   }
00853 }
00854
00855 /**
00856   * @brief  Sends an amount of data in non blocking mode.
00857   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00858   *                the configuration information for the specified UART module.
00859   * @param  pData: Pointer to data buffer
00860   * @param  Size: Amount of data to be sent
00861   * @retval HAL status
00862   */
00863 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00864 {
00865   uint32_t *tmp;
00866
00867   /* Check that a Tx process is not already ongoing */
00868   if(huart->gState == HAL_UART_STATE_READY)
00869   {
00870     if((pData == NULL ) || (Size == 0U))
00871     {
00872       return HAL_ERROR;
00873     }
00874
00875     /* Process Locked */
00876     __HAL_LOCK(huart);
00877
00878     huart->pTxBuffPtr = pData;
00879     huart->TxXferSize = Size;
00880     huart->TxXferCount = Size;
00881
00882     huart->ErrorCode = HAL_UART_ERROR_NONE;
00883     huart->gState = HAL_UART_STATE_BUSY_TX;
00884
00885     /* Set the UART DMA transfer complete callback */
00886     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
00887
00888     /* Set the UART DMA Half transfer complete callback */
00889     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
00890
00891     /* Set the DMA error callback */
00892     huart->hdmatx->XferErrorCallback = UART_DMAError;
00893
00894     /* Enable the UART transmit DMA Stream */
00895     tmp = (uint32_t*)&pData;
00896     HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
00897
00898     /* Clear the TC flag in the SR register by writing 0 to it */
00899     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
00900
00901     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00902        in the UART CR3 register */
00903     huart->Instance->CR3 |= USART_CR3_DMAT;
00904
00905     /* Process Unlocked */
00906     __HAL_UNLOCK(huart);
00907
00908     return HAL_OK;
00909   }
00910   else
00911   {
00912     return HAL_BUSY;
00913   }
00914 }
00915
00916 /**
00917   * @brief  Receives an amount of data in non blocking mode.
00918   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00919   *                the configuration information for the specified UART module.
00920   * @param  pData: Pointer to data buffer
00921   * @param  Size: Amount of data to be received
00922   * @note   When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
00923   * @retval HAL status
00924   */
00925 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00926 {
00927   uint32_t *tmp;
00928
00929   /* Check that a Rx process is not already ongoing */
00930   if(huart->RxState == HAL_UART_STATE_READY)
00931   {
00932     if((pData == NULL ) || (Size == 0U))
00933     {
00934       return HAL_ERROR;
00935     }
00936
00937     /* Process Locked */
00938     __HAL_LOCK(huart);
00939
00940     huart->pRxBuffPtr = pData;
00941     huart->RxXferSize = Size;
00942
00943     huart->ErrorCode = HAL_UART_ERROR_NONE;
00944     huart->RxState = HAL_UART_STATE_BUSY_RX;
00945
00946     /* Set the UART DMA transfer complete callback */
00947     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
00948
00949     /* Set the UART DMA Half transfer complete callback */
00950     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
00951
00952     /* Set the DMA error callback */
00953     huart->hdmarx->XferErrorCallback = UART_DMAError;
00954
00955     /* Enable the DMA Stream */
00956     tmp = (uint32_t*)&pData;
00957     HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
00958
00959     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00960     in the UART CR3 register */
00961     huart->Instance->CR3 |= USART_CR3_DMAR;
00962
00963     /* Process Unlocked */
00964     __HAL_UNLOCK(huart);
00965
00966     return HAL_OK;
00967   }
00968   else
00969   {
00970     return HAL_BUSY;
00971   }
00972 }
00973
00974 /**
00975   * @brief Pauses the DMA Transfer.
00976   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00977   *                the configuration information for the specified UART module.
00978   * @retval HAL status
00979   */
00980 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
00981 {
00982   /* Process Locked */
00983   __HAL_LOCK(huart);
00984
00985   if(huart->gState == HAL_UART_STATE_BUSY_TX)
00986   {
00987     /* Disable the UART DMA Tx request */
00988     huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
00989   }
00990   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
00991   {
00992     /* Disable the UART DMA Rx request */
00993     huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
00994   }
00995
00996   /* Process Unlocked */
00997   __HAL_UNLOCK(huart);
00998
00999   return HAL_OK;
01000 }
01001
01002 /**
01003   * @brief Resumes the DMA Transfer.
01004   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01005   *                the configuration information for the specified UART module.
01006   * @retval HAL status
01007   */
01008 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01009 {
01010   /* Process Locked */
01011   __HAL_LOCK(huart);
01012
01013   if(huart->gState == HAL_UART_STATE_BUSY_TX)
01014   {
01015     /* Enable the UART DMA Tx request */
01016     huart->Instance->CR3 |= USART_CR3_DMAT;
01017   }
01018   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
01019   {
01020     /* Clear the Overrun flag before resuming the Rx transfer*/
01021     __HAL_UART_CLEAR_OREFLAG(huart);
01022     /* Enable the UART DMA Rx request */
01023     huart->Instance->CR3 |= USART_CR3_DMAR;
01024   }
01025
01026   /* Process Unlocked */
01027   __HAL_UNLOCK(huart);
01028
01029   return HAL_OK;
01030 }
01031
01032 /**
01033   * @brief Stops the DMA Transfer.
01034   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01035   *                the configuration information for the specified UART module.
01036   * @retval HAL status
01037   */
01038 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01039 {
01040   /* The Lock is not implemented on this API to allow the user application
01041      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
01042      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01043      and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
01044      */
01045
01046   /* Disable the UART Tx/Rx DMA requests */
01047   huart->Instance->CR3 &= ~USART_CR3_DMAT;
01048   huart->Instance->CR3 &= ~USART_CR3_DMAR;
01049
01050   /* Abort the UART DMA tx Stream */
01051   if(huart->hdmatx != NULL)
01052   {
01053     HAL_DMA_Abort(huart->hdmatx);
01054   }
01055   /* Abort the UART DMA rx Stream */
01056   if(huart->hdmarx != NULL)
01057   {
01058     HAL_DMA_Abort(huart->hdmarx);
01059   }
01060
01061   huart->gState = HAL_UART_STATE_READY;
01062   huart->RxState = HAL_UART_STATE_READY;
01063
01064   return HAL_OK;
01065 }
01066
01067 /**
01068   * @brief  This function handles UART interrupt request.
01069   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01070   *                the configuration information for the specified UART module.
01071   * @retval None
01072   */
01073 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
01074 {
01075   uint32_t tmp1 = 0U, tmp2 = 0U;
01076
01077   tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE);
01078   tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE);
01079   /* UART parity error interrupt occurred ------------------------------------*/
01080   if((tmp1 != RESET) && (tmp2 != RESET))
01081   {
01082     __HAL_UART_CLEAR_PEFLAG(huart);
01083
01084     huart->ErrorCode |= HAL_UART_ERROR_PE;
01085   }
01086
01087   tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE);
01088   tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
01089   /* UART frame error interrupt occurred -------------------------------------*/
01090   if((tmp1 != RESET) && (tmp2 != RESET))
01091   {
01092     __HAL_UART_CLEAR_FEFLAG(huart);
01093
01094     huart->ErrorCode |= HAL_UART_ERROR_FE;
01095   }
01096
01097   tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE);
01098   tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
01099   /* UART noise error interrupt occurred -------------------------------------*/
01100   if((tmp1 != RESET) && (tmp2 != RESET))
01101   {
01102     __HAL_UART_CLEAR_NEFLAG(huart);
01103
01104     huart->ErrorCode |= HAL_UART_ERROR_NE;
01105   }
01106
01107   tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE);
01108   tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
01109   /* UART Over-Run interrupt occurred ----------------------------------------*/
01110   if((tmp1 != RESET) && (tmp2 != RESET))
01111   {
01112     __HAL_UART_CLEAR_OREFLAG(huart);
01113
01114     huart->ErrorCode |= HAL_UART_ERROR_ORE;
01115   }
01116
01117   tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE);
01118   tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE);
01119   /* UART in mode Receiver ---------------------------------------------------*/
01120   if((tmp1 != RESET) && (tmp2 != RESET))
01121   {
01122     UART_Receive_IT(huart);
01123   }
01124
01125   tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE);
01126   tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE);
01127   /* UART in mode Transmitter ------------------------------------------------*/
01128   if((tmp1 != RESET) && (tmp2 != RESET))
01129   {
01130     UART_Transmit_IT(huart);
01131   }
01132
01133   tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
01134   tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
01135   /* UART in mode Transmitter end --------------------------------------------*/
01136   if((tmp1 != RESET) && (tmp2 != RESET))
01137   {
01138     UART_EndTransmit_IT(huart);
01139   }
01140
01141   if(huart->ErrorCode != HAL_UART_ERROR_NONE)
01142   {
01143     /* Set the UART state ready to be able to start again the process */
01144     huart->gState = HAL_UART_STATE_READY;
01145     huart->RxState = HAL_UART_STATE_READY;
01146
01147     HAL_UART_ErrorCallback(huart);
01148   }
01149 }
01150
01151 /**
01152   * @brief  Tx Transfer completed callbacks.
01153   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01154   *                the configuration information for the specified UART module.
01155   * @retval None
01156   */
01157  __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
01158 {
01159   /* Prevent unused argument(s) compilation warning */
01160   UNUSED(huart);
01161   /* NOTE: This function Should not be modified, when the callback is needed,
01162            the HAL_UART_TxCpltCallback could be implemented in the user file
01163    */
01164 }
01165
01166 /**
01167   * @brief  Tx Half Transfer completed callbacks.
01168   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01169   *                the configuration information for the specified UART module.
01170   * @retval None
01171   */
01172  __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
01173 {
01174   /* Prevent unused argument(s) compilation warning */
01175   UNUSED(huart);
01176   /* NOTE: This function Should not be modified, when the callback is needed,
01177            the HAL_UART_TxCpltCallback could be implemented in the user file
01178    */
01179 }
01180
01181 /**
01182   * @brief  Rx Transfer completed callbacks.
01183   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01184   *                the configuration information for the specified UART module.
01185   * @retval None
01186   */
01187 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
01188 {
01189   /* Prevent unused argument(s) compilation warning */
01190   UNUSED(huart);
01191   /* NOTE: This function Should not be modified, when the callback is needed,
01192            the HAL_UART_TxCpltCallback could be implemented in the user file
01193    */
01194 }
01195
01196 /**
01197   * @brief  Rx Half Transfer completed callbacks.
01198   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01199   *                the configuration information for the specified UART module.
01200   * @retval None
01201   */
01202 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
01203 {
01204   /* Prevent unused argument(s) compilation warning */
01205   UNUSED(huart);
01206   /* NOTE: This function Should not be modified, when the callback is needed,
01207            the HAL_UART_TxCpltCallback could be implemented in the user file
01208    */
01209 }
01210
01211 /**
01212   * @brief  UART error callbacks.
01213   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01214   *                the configuration information for the specified UART module.
01215   * @retval None
01216   */
01217  __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
01218 {
01219   /* Prevent unused argument(s) compilation warning */
01220   UNUSED(huart);
01221   /* NOTE: This function Should not be modified, when the callback is needed,
01222            the HAL_UART_ErrorCallback could be implemented in the user file
01223    */
01224 }
01225
01226 /**
01227   * @}
01228   */
01229
01230 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
01231   *  @brief   UART control functions
01232   *
01233 @verbatim
01234   ==============================================================================
01235                       ##### Peripheral Control functions #####
01236   ==============================================================================
01237   [..]
01238     This subsection provides a set of functions allowing to control the UART:
01239     (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
01240     (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
01241     (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
01242
01243 @endverbatim
01244   * @{
01245   */
01246
01247 /**
01248   * @brief  Transmits break characters.
01249   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01250   *                the configuration information for the specified UART module.
01251   * @retval HAL status
01252   */
01253 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
01254 {
01255   /* Check the parameters */
01256   assert_param(IS_UART_INSTANCE(huart->Instance));
01257
01258   /* Process Locked */
01259   __HAL_LOCK(huart);
01260
01261   huart->gState = HAL_UART_STATE_BUSY;
01262
01263   /* Send break characters */
01264   huart->Instance->CR1 |= USART_CR1_SBK;
01265
01266   huart->gState = HAL_UART_STATE_READY;
01267
01268   /* Process Unlocked */
01269   __HAL_UNLOCK(huart);
01270
01271   return HAL_OK;
01272 }
01273
01274 /**
01275   * @brief  Enters the UART in mute mode.
01276   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01277   *                the configuration information for the specified UART module.
01278   * @retval HAL status
01279   */
01280 HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
01281 {
01282   /* Check the parameters */
01283   assert_param(IS_UART_INSTANCE(huart->Instance));
01284
01285   /* Process Locked */
01286   __HAL_LOCK(huart);
01287
01288   huart->gState = HAL_UART_STATE_BUSY;
01289
01290   /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
01291   huart->Instance->CR1 |= USART_CR1_RWU;
01292
01293   huart->gState = HAL_UART_STATE_READY;
01294
01295   /* Process Unlocked */
01296   __HAL_UNLOCK(huart);
01297
01298   return HAL_OK;
01299 }
01300
01301 /**
01302   * @brief  Exits the UART mute mode: wake up software.
01303   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01304   *                the configuration information for the specified UART module.
01305   * @retval HAL status
01306   */
01307 HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
01308 {
01309   /* Check the parameters */
01310   assert_param(IS_UART_INSTANCE(huart->Instance));
01311
01312   /* Process Locked */
01313   __HAL_LOCK(huart);
01314
01315   huart->gState = HAL_UART_STATE_BUSY;
01316
01317   /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
01318   huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU);
01319
01320   huart->gState = HAL_UART_STATE_READY;
01321
01322   /* Process Unlocked */
01323   __HAL_UNLOCK(huart);
01324
01325   return HAL_OK;
01326 }
01327
01328 /**
01329   * @brief  Enables the UART transmitter and disables the UART receiver.
01330   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01331   *                the configuration information for the specified UART module.
01332   * @retval HAL status
01333   */
01334 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
01335 {
01336   uint32_t tmpreg = 0x00U;
01337
01338   /* Process Locked */
01339   __HAL_LOCK(huart);
01340
01341   huart->gState = HAL_UART_STATE_BUSY;
01342
01343   /*-------------------------- USART CR1 Configuration -----------------------*/
01344   tmpreg = huart->Instance->CR1;
01345
01346   /* Clear TE and RE bits */
01347   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
01348
01349   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
01350   tmpreg |= (uint32_t)USART_CR1_TE;
01351
01352   /* Write to USART CR1 */
01353   huart->Instance->CR1 = (uint32_t)tmpreg;
01354
01355   huart->gState = HAL_UART_STATE_READY;
01356
01357   /* Process Unlocked */
01358   __HAL_UNLOCK(huart);
01359
01360   return HAL_OK;
01361 }
01362
01363 /**
01364   * @brief  Enables the UART receiver and disables the UART transmitter.
01365   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01366   *                the configuration information for the specified UART module.
01367   * @retval HAL status
01368   */
01369 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
01370 {
01371   uint32_t tmpreg = 0x00U;
01372
01373   /* Process Locked */
01374   __HAL_LOCK(huart);
01375
01376   huart->gState = HAL_UART_STATE_BUSY;
01377
01378   /*-------------------------- USART CR1 Configuration -----------------------*/
01379   tmpreg = huart->Instance->CR1;
01380
01381   /* Clear TE and RE bits */
01382   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
01383
01384   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
01385   tmpreg |= (uint32_t)USART_CR1_RE;
01386
01387   /* Write to USART CR1 */
01388   huart->Instance->CR1 = (uint32_t)tmpreg;
01389
01390   huart->gState = HAL_UART_STATE_READY;
01391
01392   /* Process Unlocked */
01393   __HAL_UNLOCK(huart);
01394
01395   return HAL_OK;
01396 }
01397
01398 /**
01399   * @}
01400   */
01401
01402 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
01403   *  @brief   UART State and Errors functions
01404   *
01405 @verbatim
01406   ==============================================================================
01407                  ##### Peripheral State and Errors functions #####
01408   ==============================================================================
01409  [..]
01410    This subsection provides a set of functions allowing to return the State of
01411    UART communication process, return Peripheral Errors occurred during communication
01412    process
01413    (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
01414    (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
01415
01416 @endverbatim
01417   * @{
01418   */
01419
01420 /**
01421   * @brief  Returns the UART state.
01422   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01423   *                the configuration information for the specified UART module.
01424   * @retval HAL state
01425   */
01426 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
01427 {
01428   uint32_t temp1= 0x00U, temp2 = 0x00U;
01429   temp1 = huart->gState;
01430   temp2 = huart->RxState;
01431
01432   return (HAL_UART_StateTypeDef)(temp1 | temp2);
01433 }
01434
01435 /**
01436 * @brief  Return the UART error code
01437 * @param  huart : pointer to a UART_HandleTypeDef structure that contains
01438   *              the configuration information for the specified UART.
01439 * @retval UART Error Code
01440 */
01441 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
01442 {
01443   return huart->ErrorCode;
01444 }
01445
01446 /**
01447   * @}
01448   */
01449
01450 /**
01451   * @brief  DMA UART transmit process complete callback.
01452   * @param  hdma: DMA handle
01453   * @retval None
01454   */
01455 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01456 {
01457   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01458   /* DMA Normal mode*/
01459   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01460   {
01461     huart->TxXferCount = 0U;
01462
01463     /* Disable the DMA transfer for transmit request by setting the DMAT bit
01464        in the UART CR3 register */
01465     huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
01466
01467     /* Enable the UART Transmit Complete Interrupt */
01468     __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
01469
01470   }
01471   /* DMA Circular mode */
01472   else
01473   {
01474     HAL_UART_TxCpltCallback(huart);
01475   }
01476 }
01477
01478 /**
01479   * @brief DMA UART transmit process half complete callback
01480   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01481   *                the configuration information for the specified DMA module.
01482   * @retval None
01483   */
01484 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01485 {
01486   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01487
01488   HAL_UART_TxHalfCpltCallback(huart);
01489 }
01490
01491 /**
01492   * @brief  DMA UART receive process complete callback.
01493   * @param  hdma: DMA handle
01494   * @retval None
01495   */
01496 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01497 {
01498   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01499   /* DMA Normal mode*/
01500   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01501   {
01502     huart->RxXferCount = 0U;
01503
01504     /* Disable the DMA transfer for the receiver request by setting the DMAR bit
01505        in the UART CR3 register */
01506     huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
01507
01508     /* At end of Rx process, restore huart->RxState to Ready */
01509     huart->RxState = HAL_UART_STATE_READY;
01510   }
01511   HAL_UART_RxCpltCallback(huart);
01512 }
01513
01514 /**
01515   * @brief DMA UART receive process half complete callback
01516   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01517   *                the configuration information for the specified DMA module.
01518   * @retval None
01519   */
01520 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01521 {
01522   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01523
01524   HAL_UART_RxHalfCpltCallback(huart);
01525 }
01526
01527 /**
01528   * @brief  DMA UART communication error callback.
01529   * @param  hdma: DMA handle
01530   * @retval None
01531   */
01532 static void UART_DMAError(DMA_HandleTypeDef *hdma)
01533 {
01534   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01535   huart->RxXferCount = 0U;
01536   huart->TxXferCount = 0U;
01537   huart->gState= HAL_UART_STATE_READY;
01538   huart->RxState= HAL_UART_STATE_READY;
01539   huart->ErrorCode |= HAL_UART_ERROR_DMA;
01540   HAL_UART_ErrorCallback(huart);
01541 }
01542
01543 /**
01544   * @brief  This function handles UART Communication Timeout.
01545   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01546   *                the configuration information for the specified UART module.
01547   * @param  Flag: specifies the UART flag to check.
01548   * @param  Status: The new Flag status (SET or RESET).
01549   * @param  Timeout: Timeout duration
01550   * @retval HAL status
01551   */
01552 static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01553 {
01554   uint32_t tickstart = 0U;
01555
01556   /* Get tick */
01557   tickstart = HAL_GetTick();
01558
01559   /* Wait until flag is set */
01560   if(Status == RESET)
01561   {
01562     while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
01563     {
01564       /* Check for the Timeout */
01565       if(Timeout != HAL_MAX_DELAY)
01566       {
01567         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01568         {
01569           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01570           __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
01571           __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
01572           __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
01573           __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
01574
01575           huart->gState= HAL_UART_STATE_READY;
01576                   huart->RxState= HAL_UART_STATE_READY;
01577
01578           /* Process Unlocked */
01579           __HAL_UNLOCK(huart);
01580
01581           return HAL_TIMEOUT;
01582         }
01583       }
01584     }
01585   }
01586   else
01587   {
01588     while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
01589     {
01590       /* Check for the Timeout */
01591       if(Timeout != HAL_MAX_DELAY)
01592       {
01593         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01594         {
01595           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01596           __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
01597           __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
01598           __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
01599           __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
01600
01601           huart->gState= HAL_UART_STATE_READY;
01602                   huart->RxState= HAL_UART_STATE_READY;
01603
01604           /* Process Unlocked */
01605           __HAL_UNLOCK(huart);
01606
01607           return HAL_TIMEOUT;
01608         }
01609       }
01610     }
01611   }
01612   return HAL_OK;
01613 }
01614
01615 /**
01616   * @brief  Sends an amount of data in non blocking mode.
01617   * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
01618   *                the configuration information for the specified UART module.
01619   * @retval HAL status
01620   */
01621 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
01622 {
01623   uint16_t* tmp;
01624
01625   /* Check that a Tx process is ongoing */
01626   if(huart->gState == HAL_UART_STATE_BUSY_TX)
01627   {
01628     if(huart->Init.WordLength == UART_WORDLENGTH_9B)
01629     {
01630       tmp = (uint16_t*) huart->pTxBuffPtr;
01631       huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
01632       if(huart->Init.Parity == UART_PARITY_NONE)
01633       {
01634         huart->pTxBuffPtr += 2U;
01635       }
01636       else
01637       {
01638         huart->pTxBuffPtr += 1U;
01639       }
01640     }
01641     else
01642     {
01643       huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FFU);
01644     }
01645
01646     if(--huart->TxXferCount == 0U)
01647     {
01648       /* Disable the UART Transmit Complete Interrupt */
01649       __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
01650
01651       /* Enable the UART Transmit Complete Interrupt */
01652       __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
01653     }
01654     return HAL_OK;
01655   }
01656   else
01657   {
01658     return HAL_BUSY;
01659   }
01660 }
01661
01662
01663 /**
01664   * @brief  Wraps up transmission in non blocking mode.
01665   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01666   *                the configuration information for the specified UART module.
01667   * @retval HAL status
01668   */
01669 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
01670 {
01671   /* Disable the UART Transmit Complete Interrupt */
01672   __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
01673
01674   /* Tx process is ended, restore huart->gState to Ready */
01675   huart->gState = HAL_UART_STATE_READY;
01676
01677   HAL_UART_TxCpltCallback(huart);
01678
01679   return HAL_OK;
01680 }
01681
01682 /**
01683   * @brief  Receives an amount of data in non blocking mode
01684   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01685   *                the configuration information for the specified UART module.
01686   * @retval HAL status
01687   */
01688 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
01689 {
01690   uint16_t* tmp;
01691
01692   /* Check that a Rx process is ongoing */
01693   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
01694   {
01695     if(huart->Init.WordLength == UART_WORDLENGTH_9B)
01696     {
01697       tmp = (uint16_t*) huart->pRxBuffPtr;
01698       if(huart->Init.Parity == UART_PARITY_NONE)
01699       {
01700         *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FFU);
01701         huart->pRxBuffPtr += 2U;
01702       }
01703       else
01704       {
01705         *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FFU);
01706         huart->pRxBuffPtr += 1U;
01707       }
01708     }
01709     else
01710     {
01711       if(huart->Init.Parity == UART_PARITY_NONE)
01712       {
01713         *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FFU);
01714       }
01715       else
01716       {
01717         *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007FU);
01718       }
01719     }
01720
01721     if(--huart->RxXferCount == 0U)
01722     {
01723       __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
01724
01725       /* Disable the UART Parity Error Interrupt */
01726       __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
01727
01728       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01729       __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
01730
01731           /* Rx process is completed, restore huart->RxState to Ready */
01732       huart->RxState = HAL_UART_STATE_READY;
01733
01734       HAL_UART_RxCpltCallback(huart);
01735
01736       return HAL_OK;
01737     }
01738     return HAL_OK;
01739   }
01740   else
01741   {
01742     return HAL_BUSY;
01743   }
01744 }
01745
01746 /**
01747   * @brief  Configures the UART peripheral.
01748   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01749   *                the configuration information for the specified UART module.
01750   * @retval None
01751   */
01752 static void UART_SetConfig(UART_HandleTypeDef *huart)
01753 {
01754   uint32_t tmpreg = 0x00U;
01755
01756   /* Check the parameters */
01757   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
01758   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
01759   assert_param(IS_UART_PARITY(huart->Init.Parity));
01760   assert_param(IS_UART_MODE(huart->Init.Mode));
01761
01762   /*-------------------------- USART CR2 Configuration -----------------------*/
01763   tmpreg = huart->Instance->CR2;
01764
01765   /* Clear STOP[13:12] bits */
01766   tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
01767
01768   /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */
01769   tmpreg |= (uint32_t)huart->Init.StopBits;
01770
01771   /* Write to USART CR2 */
01772   huart->Instance->CR2 = (uint32_t)tmpreg;
01773
01774   /*-------------------------- USART CR1 Configuration -----------------------*/
01775   tmpreg = huart->Instance->CR1;
01776
01777   /* Clear M, PCE, PS, TE and RE bits */
01778   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
01779                                    USART_CR1_RE | USART_CR1_OVER8));
01780
01781   /* Configure the UART Word Length, Parity and mode:
01782      Set the M bits according to huart->Init.WordLength value
01783      Set PCE and PS bits according to huart->Init.Parity value
01784      Set TE and RE bits according to huart->Init.Mode value
01785      Set OVER8 bit according to huart->Init.OverSampling value */
01786   tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
01787
01788   /* Write to USART CR1 */
01789   huart->Instance->CR1 = (uint32_t)tmpreg;
01790
01791   /*-------------------------- USART CR3 Configuration -----------------------*/
01792   tmpreg = huart->Instance->CR3;
01793
01794   /* Clear CTSE and RTSE bits */
01795   tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
01796
01797   /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
01798   tmpreg |= huart->Init.HwFlowCtl;
01799
01800   /* Write to USART CR3 */
01801   huart->Instance->CR3 = (uint32_t)tmpreg;
01802
01803   /* Check the Over Sampling */
01804   if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
01805   {
01806     /*-------------------------- USART BRR Configuration ---------------------*/
01807     if((huart->Instance == USART1) || (huart->Instance == USART6))
01808     {
01809       huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
01810     }
01811     else
01812     {
01813       huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
01814     }
01815   }
01816   else
01817   {
01818     /*-------------------------- USART BRR Configuration ---------------------*/
01819     if((huart->Instance == USART1) || (huart->Instance == USART6))
01820     {
01821       huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
01822     }
01823     else
01824     {
01825       huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
01826     }
01827   }
01828 }
01829
01830 /**
01831   * @}
01832   */
01833
01834 #endif /* HAL_UART_MODULE_ENABLED */
01835 /**
01836   * @}
01837   */
01838
01839 /**
01840   * @}
01841   */
01842
01843 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_uart.h Source File

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stm32f4xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of UART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_UART_H
00040 #define __STM32F4xx_HAL_UART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup UART_Exported_Types UART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief UART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
00070                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
00071                                            Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
00072
00073   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00074                                            This parameter can be a value of @ref UART_Word_Length */
00075
00076   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00077                                            This parameter can be a value of @ref UART_Stop_Bits */
00078
00079   uint32_t Parity;                    /*!< Specifies the parity mode.
00080                                            This parameter can be a value of @ref UART_Parity
00081                                            @note When parity is enabled, the computed parity is inserted
00082                                                  at the MSB position of the transmitted data (9th bit when
00083                                                  the word length is set to 9 data bits; 8th bit when the
00084                                                  word length is set to 8 data bits). */
00085
00086   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00087                                            This parameter can be a value of @ref UART_Mode */
00088
00089   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
00090                                            or disabled.
00091                                            This parameter can be a value of @ref UART_Hardware_Flow_Control */
00092
00093   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
00094                                            This parameter can be a value of @ref UART_Over_Sampling */
00095 }UART_InitTypeDef;
00096
00097 /**
00098   * @brief HAL UART State structures definition
00099   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
00100   *        - gState contains UART state information related to global Handle management
00101   *          and also information related to Tx operations.
00102   *          gState value coding follow below described bitmap :
00103   *          b7-b6  Error information
00104   *             00 : No Error
00105   *             01 : (Not Used)
00106   *             10 : Timeout
00107   *             11 : Error
00108   *          b5     IP initilisation status
00109   *             0  : Reset (IP not initialized)
00110   *             1  : Init done (IP not initialized. HAL UART Init function already called)
00111   *          b4-b3  (not used)
00112   *             xx : Should be set to 00
00113   *          b2     Intrinsic process state
00114   *             0  : Ready
00115   *             1  : Busy (IP busy with some configuration or internal operations)
00116   *          b1     (not used)
00117   *             x  : Should be set to 0
00118   *          b0     Tx state
00119   *             0  : Ready (no Tx operation ongoing)
00120   *             1  : Busy (Tx operation ongoing)
00121   *        - RxState contains information related to Rx operations.
00122   *          RxState value coding follow below described bitmap :
00123   *          b7-b6  (not used)
00124   *             xx : Should be set to 00
00125   *          b5     IP initilisation status
00126   *             0  : Reset (IP not initialized)
00127   *             1  : Init done (IP not initialized)
00128   *          b4-b2  (not used)
00129   *            xxx : Should be set to 000
00130   *          b1     Rx state
00131   *             0  : Ready (no Rx operation ongoing)
00132   *             1  : Busy (Rx operation ongoing)
00133   *          b0     (not used)
00134   *             x  : Should be set to 0.
00135   */
00136 typedef enum
00137 {
00138   HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00139                                                    Value is allowed for gState and RxState */
00140   HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00141                                                    Value is allowed for gState and RxState */
00142   HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
00143                                                    Value is allowed for gState only */
00144   HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00145                                                    Value is allowed for gState only */
00146   HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00147                                                    Value is allowed for RxState only */
00148   HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
00149                                                    Not to be used for neither gState nor RxState.
00150                                                    Value is result of combination (Or) between gState and RxState values */
00151   HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
00152                                                    Value is allowed for gState only */
00153   HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
00154                                                    Value is allowed for gState only */
00155 }HAL_UART_StateTypeDef;
00156
00157 /**
00158   * @brief  UART handle Structure definition
00159   */
00160 typedef struct
00161 {
00162   USART_TypeDef                 *Instance;        /*!< UART registers base address        */
00163
00164   UART_InitTypeDef              Init;             /*!< UART communication parameters      */
00165
00166   uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
00167
00168   uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
00169
00170   uint16_t                      TxXferCount;      /*!< UART Tx Transfer Counter           */
00171
00172   uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
00173
00174   uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
00175
00176   uint16_t                      RxXferCount;      /*!< UART Rx Transfer Counter           */
00177
00178   DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
00179
00180   DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
00181
00182   HAL_LockTypeDef               Lock;             /*!< Locking object                     */
00183
00184   __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
00185                                                        and also related to Tx operations.
00186                                                        This parameter can be a value of @ref HAL_UART_StateTypeDef */
00187
00188   __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
00189                                                        This parameter can be a value of @ref HAL_UART_StateTypeDef */
00190
00191   __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
00192
00193 }UART_HandleTypeDef;
00194 /**
00195   * @}
00196   */
00197
00198 /* Exported constants --------------------------------------------------------*/
00199 /** @defgroup UART_Exported_Constants UART Exported constants
00200   * @{
00201   */
00202
00203 /** @defgroup UART_Error_Code UART Error Code
00204   * @brief    UART Error Code
00205   * @{
00206   */
00207 #define HAL_UART_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
00208 #define HAL_UART_ERROR_PE           ((uint32_t)0x00000001U)   /*!< Parity error        */
00209 #define HAL_UART_ERROR_NE           ((uint32_t)0x00000002U)   /*!< Noise error         */
00210 #define HAL_UART_ERROR_FE           ((uint32_t)0x00000004U)   /*!< Frame error         */
00211 #define HAL_UART_ERROR_ORE          ((uint32_t)0x00000008U)   /*!< Overrun error       */
00212 #define HAL_UART_ERROR_DMA          ((uint32_t)0x00000010U)   /*!< DMA transfer error  */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup UART_Word_Length UART Word Length
00218   * @{
00219   */
00220 #define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)
00221 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup UART_Stop_Bits UART Number of Stop Bits
00227   * @{
00228   */
00229 #define UART_STOPBITS_1                     ((uint32_t)0x00000000U)
00230 #define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup UART_Parity UART Parity
00236   * @{
00237   */
00238 #define UART_PARITY_NONE                    ((uint32_t)0x00000000U)
00239 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00240 #define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00246   * @{
00247   */
00248 #define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000U)
00249 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
00250 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
00251 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup UART_Mode UART Transfer Mode
00257   * @{
00258   */
00259 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
00260 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
00261 #define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00262 /**
00263   * @}
00264   */
00265
00266  /** @defgroup UART_State UART State
00267   * @{
00268   */
00269 #define UART_STATE_DISABLE                  ((uint32_t)0x00000000U)
00270 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup UART_Over_Sampling UART Over Sampling
00276   * @{
00277   */
00278 #define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000U)
00279 #define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
00285   * @{
00286   */
00287 #define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000U)
00288 #define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)0x00000020U)
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup UART_WakeUp_functions  UART Wakeup Functions
00294   * @{
00295   */
00296 #define UART_WAKEUPMETHOD_IDLELINE                ((uint32_t)0x00000000U)
00297 #define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)0x00000800U)
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup UART_Flags   UART FLags
00303   *        Elements values convention: 0xXXXX
00304   *           - 0xXXXX  : Flag mask in the SR register
00305   * @{
00306   */
00307 #define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
00308 #define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
00309 #define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
00310 #define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
00311 #define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
00312 #define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
00313 #define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
00314 #define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
00315 #define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
00316 #define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
00317 /**
00318   * @}
00319   */
00320
00321 /** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
00322   *        Elements values convention: 0xY000XXXX
00323   *           - XXXX  : Interrupt mask (16 bits) in the Y register
00324   *           - Y  : Interrupt source register (2bits)
00325   *                 - 0001: CR1 register
00326   *                 - 0010: CR2 register
00327   *                 - 0011: CR3 register
00328   *
00329   * @{
00330   */
00331
00332 #define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00333 #define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00334 #define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00335 #define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00336 #define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00337
00338 #define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
00339
00340 #define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
00341 #define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00342 /**
00343   * @}
00344   */
00345
00346 /**
00347   * @}
00348   */
00349
00350 /* Exported macro ------------------------------------------------------------*/
00351 /** @defgroup UART_Exported_Macros UART Exported Macros
00352   * @{
00353   */
00354
00355 /** @brief Reset UART handle gstate & RxState
00356   * @param  __HANDLE__: specifies the UART Handle.
00357   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00358   *         UART peripheral.
00359   * @retval None
00360   */
00361 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00362                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00363                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00364                                                      } while(0)
00365
00366 /** @brief  Flushes the UART DR register
00367   * @param  __HANDLE__: specifies the UART Handle.
00368   */
00369 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
00370
00371 /** @brief  Checks whether the specified UART flag is set or not.
00372   * @param  __HANDLE__: specifies the UART Handle.
00373   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00374   *         UART peripheral.
00375   * @param  __FLAG__: specifies the flag to check.
00376   *        This parameter can be one of the following values:
00377   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
00378   *            @arg UART_FLAG_LBD:  LIN Break detection flag
00379   *            @arg UART_FLAG_TXE:  Transmit data register empty flag
00380   *            @arg UART_FLAG_TC:   Transmission Complete flag
00381   *            @arg UART_FLAG_RXNE: Receive data register not empty flag
00382   *            @arg UART_FLAG_IDLE: Idle Line detection flag
00383   *            @arg UART_FLAG_ORE:  Overrun Error flag
00384   *            @arg UART_FLAG_NE:   Noise Error flag
00385   *            @arg UART_FLAG_FE:   Framing Error flag
00386   *            @arg UART_FLAG_PE:   Parity Error flag
00387   * @retval The new state of __FLAG__ (TRUE or FALSE).
00388   */
00389
00390 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00391
00392 /** @brief  Clears the specified UART pending flag.
00393   * @param  __HANDLE__: specifies the UART Handle.
00394   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00395   *         UART peripheral.
00396   * @param  __FLAG__: specifies the flag to check.
00397   *          This parameter can be any combination of the following values:
00398   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
00399   *            @arg UART_FLAG_LBD:  LIN Break detection flag.
00400   *            @arg UART_FLAG_TC:   Transmission Complete flag.
00401   *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
00402   *
00403   * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
00404   *          error) and IDLE (Idle line detected) flags are cleared by software
00405   *          sequence: a read operation to USART_SR register followed by a read
00406   *          operation to USART_DR register.
00407   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00408   * @note   TC flag can be also cleared by software sequence: a read operation to
00409   *          USART_SR register followed by a write operation to USART_DR register.
00410   * @note   TXE flag is cleared only by a write to the USART_DR register.
00411   *
00412   * @retval None
00413   */
00414 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00415
00416 /** @brief  Clear the UART PE pending flag.
00417   * @param  __HANDLE__: specifies the UART Handle.
00418   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00419   *         UART peripheral.
00420   * @retval None
00421   */
00422 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
00423   do{                                           \
00424     __IO uint32_t tmpreg = 0x00U;                \
00425     tmpreg = (__HANDLE__)->Instance->SR;        \
00426     tmpreg = (__HANDLE__)->Instance->DR;        \
00427     UNUSED(tmpreg);                             \
00428   } while(0)
00429
00430 /** @brief  Clear the UART FE pending flag.
00431   * @param  __HANDLE__: specifies the UART Handle.
00432   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00433   *         UART peripheral.
00434   * @retval None
00435   */
00436 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00437
00438 /** @brief  Clear the UART NE pending flag.
00439   * @param  __HANDLE__: specifies the UART Handle.
00440   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00441   *         UART peripheral.
00442   * @retval None
00443   */
00444 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00445
00446 /** @brief  Clear the UART ORE pending flag.
00447   * @param  __HANDLE__: specifies the UART Handle.
00448   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00449   *         UART peripheral.
00450   * @retval None
00451   */
00452 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00453
00454 /** @brief  Clear the UART IDLE pending flag.
00455   * @param  __HANDLE__: specifies the UART Handle.
00456   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00457   *         UART peripheral.
00458   * @retval None
00459   */
00460 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00461
00462 /** @brief  Enable the specified UART interrupt.
00463   * @param  __HANDLE__: specifies the UART Handle.
00464   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00465   *         UART peripheral.
00466   * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
00467   *          This parameter can be one of the following values:
00468   *            @arg UART_IT_CTS:  CTS change interrupt
00469   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00470   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00471   *            @arg UART_IT_TC:   Transmission complete interrupt
00472   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00473   *            @arg UART_IT_IDLE: Idle line detection interrupt
00474   *            @arg UART_IT_PE:   Parity Error interrupt
00475   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00476   * @retval None
00477   */
00478 #define UART_IT_MASK  ((uint32_t)0x0000FFFFU)
00479 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
00480                                                            (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
00481                                                         ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
00482 /** @brief  Disable the specified UART interrupt.
00483   * @param  __HANDLE__: specifies the UART Handle.
00484   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00485   *         UART peripheral.
00486   * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
00487   *          This parameter can be one of the following values:
00488   *            @arg UART_IT_CTS:  CTS change interrupt
00489   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00490   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00491   *            @arg UART_IT_TC:   Transmission complete interrupt
00492   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00493   *            @arg UART_IT_IDLE: Idle line detection interrupt
00494   *            @arg UART_IT_PE:   Parity Error interrupt
00495   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00496   * @retval None
00497   */
00498 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
00499                                                            (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
00500                                                         ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
00501
00502 /** @brief  Checks whether the specified UART interrupt has occurred or not.
00503   * @param  __HANDLE__: specifies the UART Handle.
00504   *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
00505   *         UART peripheral.
00506   * @param  __IT__: specifies the UART interrupt source to check.
00507   *          This parameter can be one of the following values:
00508   *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
00509   *            @arg UART_IT_LBD: LIN Break detection interrupt
00510   *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
00511   *            @arg UART_IT_TC:  Transmission complete interrupt
00512   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00513   *            @arg UART_IT_IDLE: Idle line detection interrupt
00514   *            @arg USART_IT_ERR: Error interrupt
00515   * @retval The new state of __IT__ (TRUE or FALSE).
00516   */
00517 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
00518                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
00519
00520 /** @brief  Enable CTS flow control
00521   *         This macro allows to enable CTS hardware flow control for a given UART instance,
00522   *         without need to call HAL_UART_Init() function.
00523   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00524   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00525   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00526   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00527   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00528   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00529   * @param  __HANDLE__: specifies the UART Handle.
00530   *         The Handle Instance can be USART1, USART2 or LPUART.
00531   * @retval None
00532   */
00533 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
00534   do{                                                      \
00535     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
00536     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
00537   } while(0)
00538
00539 /** @brief  Disable CTS flow control
00540   *         This macro allows to disable CTS hardware flow control for a given UART instance,
00541   *         without need to call HAL_UART_Init() function.
00542   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00543   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00544   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00545   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00546   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00547   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00548   * @param  __HANDLE__: specifies the UART Handle.
00549   *         The Handle Instance can be USART1, USART2 or LPUART.
00550   * @retval None
00551   */
00552 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
00553   do{                                                       \
00554     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
00555     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
00556   } while(0)
00557
00558 /** @brief  Enable RTS flow control
00559   *         This macro allows to enable RTS hardware flow control for a given UART instance,
00560   *         without need to call HAL_UART_Init() function.
00561   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00562   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00563   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00564   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00565   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00566   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00567   * @param  __HANDLE__: specifies the UART Handle.
00568   *         The Handle Instance can be USART1, USART2 or LPUART.
00569   * @retval None
00570   */
00571 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
00572   do{                                                     \
00573     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
00574     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
00575   } while(0)
00576
00577 /** @brief  Disable RTS flow control
00578   *         This macro allows to disable RTS hardware flow control for a given UART instance,
00579   *         without need to call HAL_UART_Init() function.
00580   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00581   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00582   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00583   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00584   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00585   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00586   * @param  __HANDLE__: specifies the UART Handle.
00587   *         The Handle Instance can be USART1, USART2 or LPUART.
00588   * @retval None
00589   */
00590 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
00591   do{                                                      \
00592     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
00593     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
00594   } while(0)
00595
00596 /** @brief  macros to enables the UART's one bit sample method
00597   * @param  __HANDLE__: specifies the UART Handle.
00598   * @retval None
00599   */
00600 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00601
00602 /** @brief  macros to disables the UART's one bit sample method
00603   * @param  __HANDLE__: specifies the UART Handle.
00604   * @retval None
00605   */
00606 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
00607
00608 /** @brief  Enable UART
00609   * @param  __HANDLE__: specifies the UART Handle.
00610   * @retval None
00611   */
00612 #define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00613
00614 /** @brief  Disable UART
00615   * @param  __HANDLE__: specifies the UART Handle.
00616   * @retval None
00617   */
00618 #define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00619 /**
00620   * @}
00621   */
00622
00623 /* Exported functions --------------------------------------------------------*/
00624 /** @addtogroup UART_Exported_Functions
00625   * @{
00626   */
00627
00628 /** @addtogroup UART_Exported_Functions_Group1
00629   * @{
00630   */
00631 /* Initialization/de-initialization functions  **********************************/
00632 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
00633 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
00634 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
00635 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
00636 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
00637 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
00638 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
00639 /**
00640   * @}
00641   */
00642
00643 /** @addtogroup UART_Exported_Functions_Group2
00644   * @{
00645   */
00646 /* IO operation functions *******************************************************/
00647 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00648 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00649 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00650 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00651 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00652 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00653 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
00654 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
00655 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
00656 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
00657 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
00658 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
00659 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
00660 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
00661 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
00662 /**
00663   * @}
00664   */
00665
00666 /** @addtogroup UART_Exported_Functions_Group3
00667   * @{
00668   */
00669 /* Peripheral Control functions  ************************************************/
00670 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
00671 HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
00672 HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
00673 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
00674 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
00675 /**
00676   * @}
00677   */
00678
00679 /** @addtogroup UART_Exported_Functions_Group4
00680   * @{
00681   */
00682 /* Peripheral State functions  **************************************************/
00683 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
00684 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
00685 /**
00686   * @}
00687   */
00688
00689 /**
00690   * @}
00691   */
00692 /* Private types -------------------------------------------------------------*/
00693 /* Private variables ---------------------------------------------------------*/
00694 /* Private constants ---------------------------------------------------------*/
00695 /** @defgroup UART_Private_Constants UART Private Constants
00696   * @{
00697   */
00698 /** @brief UART interruptions flag mask
00699   *
00700   */
00701 #define UART_CR1_REG_INDEX               1U
00702 #define UART_CR2_REG_INDEX               2U
00703 #define UART_CR3_REG_INDEX               3U
00704 /**
00705   * @}
00706   */
00707
00708 /* Private macros ------------------------------------------------------------*/
00709 /** @defgroup UART_Private_Macros UART Private Macros
00710   * @{
00711   */
00712 #define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
00713                                      ((LENGTH) == UART_WORDLENGTH_9B))
00714 #define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
00715 #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
00716                                     ((STOPBITS) == UART_STOPBITS_2))
00717 #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
00718                                 ((PARITY) == UART_PARITY_EVEN) || \
00719                                 ((PARITY) == UART_PARITY_ODD))
00720 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
00721                               (((CONTROL) == UART_HWCONTROL_NONE) || \
00722                                ((CONTROL) == UART_HWCONTROL_RTS) || \
00723                                ((CONTROL) == UART_HWCONTROL_CTS) || \
00724                                ((CONTROL) == UART_HWCONTROL_RTS_CTS))
00725 #define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00U))
00726 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
00727                               ((STATE) == UART_STATE_ENABLE))
00728 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
00729                                         ((SAMPLING) == UART_OVERSAMPLING_8))
00730 #define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
00731 #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
00732                                                  ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
00733 #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
00734                                       ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
00735 #define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
00736 #define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
00737
00738 #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
00739 #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
00740 #define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00741 /* UART BRR = mantissa + overflow + fraction
00742             = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
00743 #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
00744                                                         (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
00745                                                         (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
00746
00747 #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25U)/(2U*(_BAUD_)))
00748 #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
00749 #define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
00750 /* UART BRR = mantissa + overflow + fraction
00751             = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
00752 #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
00753                                                         ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
00754                                                         (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
00755
00756 /**
00757   * @}
00758   */
00759
00760 /* Private functions ---------------------------------------------------------*/
00761 /** @defgroup UART_Private_Functions UART Private Functions
00762   * @{
00763   */
00764
00765 /**
00766   * @}
00767   */
00768
00769 /**
00770   * @}
00771   */
00772
00773 /**
00774   * @}
00775   */
00776
00777 #ifdef __cplusplus
00778 }
00779 #endif
00780
00781 #endif /* __STM32F4xx_HAL_UART_H */
00782
00783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:52 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_usart.c Source File

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stm32f4xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   USART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     The USART HAL driver can be used as follows:
00019
00020     (#) Declare a USART_HandleTypeDef handle structure.
00021     (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
00022         (##) Enable the USARTx interface clock.
00023         (##) USART pins configuration:
00024              (+++) Enable the clock for the USART GPIOs.
00025              (+++) Configure these USART pins as alternate function pull-up.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00027              HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00028              (+++) Configure the USARTx interrupt priority.
00029              (+++) Enable the NVIC USART IRQ handle.
00030         (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00031              HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00032              (+++) Declare a DMA handle structure for the Tx/Rx stream.
00033              (+++) Enable the DMAx interface clock.
00034              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00035              (+++) Configure the DMA Tx/Rx Stream.
00036              (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00037              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
00038
00039     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00040         flow control and Mode(Receiver/Transmitter) in the husart Init structure.
00041
00042     (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00043         (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00044              by calling the customized HAL_USART_MspInit(&husart) API.
00045
00046         -@@- The specific USART interrupts (Transmission complete interrupt,
00047              RXNE interrupt and Error Interrupts) will be managed using the macros
00048              __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00049
00050     (#) Three operation modes are available within this driver :
00051
00052      *** Polling mode IO operation ***
00053      =================================
00054      [..]
00055        (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
00056        (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
00057
00058      *** Interrupt mode IO operation ***
00059      ===================================
00060      [..]
00061        (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
00062        (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
00063             add his own code by customization of function pointer HAL_USART_TxCpltCallback
00064        (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
00065        (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
00066             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00067        (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
00068             add his own code by customization of function pointer HAL_USART_ErrorCallback
00069
00070      *** DMA mode IO operation ***
00071      ==============================
00072      [..]
00073        (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
00074        (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
00075             add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
00076        (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
00077             add his own code by customization of function pointer HAL_USART_TxCpltCallback
00078        (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
00079        (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
00080             add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
00081        (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
00082             add his own code by customization of function pointer HAL_USART_RxCpltCallback
00083        (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
00084             add his own code by customization of function pointer HAL_USART_ErrorCallback
00085        (+) Pause the DMA Transfer using HAL_USART_DMAPause()
00086        (+) Resume the DMA Transfer using HAL_USART_DMAResume()
00087        (+) Stop the DMA Transfer using HAL_USART_DMAStop()
00088
00089      *** USART HAL driver macros list ***
00090      =============================================
00091      [..]
00092        Below the list of most used macros in USART HAL driver.
00093
00094        (+) __HAL_USART_ENABLE: Enable the USART peripheral
00095        (+) __HAL_USART_DISABLE: Disable the USART peripheral
00096        (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
00097        (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
00098        (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
00099        (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
00100
00101      [..]
00102        (@) You can refer to the USART HAL driver header file for more useful macros
00103
00104   @endverbatim
00105   ******************************************************************************
00106   * @attention
00107   *
00108   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00109   *
00110   * Redistribution and use in source and binary forms, with or without modification,
00111   * are permitted provided that the following conditions are met:
00112   *   1. Redistributions of source code must retain the above copyright notice,
00113   *      this list of conditions and the following disclaimer.
00114   *   2. Redistributions in binary form must reproduce the above copyright notice,
00115   *      this list of conditions and the following disclaimer in the documentation
00116   *      and/or other materials provided with the distribution.
00117   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00118   *      may be used to endorse or promote products derived from this software
00119   *      without specific prior written permission.
00120   *
00121   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00122   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00123   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00124   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00125   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00126   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00127   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00128   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00129   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00130   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00131   *
00132   ******************************************************************************
00133   */
00134
00135 /* Includes ------------------------------------------------------------------*/
00136 #include "stm32f4xx_hal.h"
00137
00138 /** @addtogroup STM32F4xx_HAL_Driver
00139   * @{
00140   */
00141
00142 /** @defgroup USART USART
00143   * @brief HAL USART Synchronous module driver
00144   * @{
00145   */
00146 #ifdef HAL_USART_MODULE_ENABLED
00147 /* Private typedef -----------------------------------------------------------*/
00148 /* Private define ------------------------------------------------------------*/
00149 /** @addtogroup USART_Private_Constants
00150   * @{
00151   */
00152 #define DUMMY_DATA           0xFFFFU
00153 #define USART_TIMEOUT_VALUE  22000U
00154 /**
00155   * @}
00156   */
00157 /* Private macro -------------------------------------------------------------*/
00158 /* Private variables ---------------------------------------------------------*/
00159 /* Private function prototypes -----------------------------------------------*/
00160 /* Private functions ---------------------------------------------------------*/
00161 /** @addtogroup USART_Private_Functions
00162   * @{
00163   */
00164 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
00165 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00166 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
00167 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
00168 static void USART_SetConfig (USART_HandleTypeDef *husart);
00169 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00170 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00171 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00172 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00173 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00174 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00175 /**
00176   * @}
00177   */
00178
00179 /* Exported functions --------------------------------------------------------*/
00180 /** @defgroup USART_Exported_Functions USART Exported Functions
00181   * @{
00182   */
00183
00184 /** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
00185   *  @brief    Initialization and Configuration functions
00186   *
00187 @verbatim
00188   ==============================================================================
00189               ##### Initialization and Configuration functions #####
00190   ==============================================================================
00191   [..]
00192   This subsection provides a set of functions allowing to initialize the USART
00193   in asynchronous and in synchronous modes.
00194   (+) For the asynchronous mode only these parameters can be configured:
00195       (++) Baud Rate
00196       (++) Word Length
00197       (++) Stop Bit
00198       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00199            in the data register is transmitted but is changed by the parity bit.
00200            Depending on the frame length defined by the M bit (8-bits or 9-bits),
00201            please refer to Reference manual for possible USART frame formats.
00202       (++) USART polarity
00203       (++) USART phase
00204       (++) USART LastBit
00205       (++) Receiver/transmitter modes
00206
00207   [..]
00208     The HAL_USART_Init() function follows the USART  synchronous configuration
00209     procedure (details for the procedure are available in reference manual (RM0329)).
00210
00211 @endverbatim
00212   * @{
00213   */
00214
00215 /**
00216   * @brief  Initializes the USART mode according to the specified
00217   *         parameters in the USART_InitTypeDef and create the associated handle.
00218   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00219   *                the configuration information for the specified USART module.
00220   * @retval HAL status
00221   */
00222 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00223 {
00224   /* Check the USART handle allocation */
00225   if(husart == NULL)
00226   {
00227     return HAL_ERROR;
00228   }
00229
00230   /* Check the parameters */
00231   assert_param(IS_USART_INSTANCE(husart->Instance));
00232
00233   if(husart->State == HAL_USART_STATE_RESET)
00234   {
00235     /* Allocate lock resource and initialize it */
00236     husart->Lock = HAL_UNLOCKED;
00237     /* Init the low level hardware */
00238     HAL_USART_MspInit(husart);
00239   }
00240
00241   husart->State = HAL_USART_STATE_BUSY;
00242
00243   /* Set the USART Communication parameters */
00244   USART_SetConfig(husart);
00245
00246   /* In USART mode, the following bits must be kept cleared:
00247      - LINEN bit in the USART_CR2 register
00248      - HDSEL, SCEN and IREN bits in the USART_CR3 register */
00249   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00250   husart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL);
00251
00252   /* Enable the Peripheral */
00253   __HAL_USART_ENABLE(husart);
00254
00255   /* Initialize the USART state */
00256   husart->ErrorCode = HAL_USART_ERROR_NONE;
00257   husart->State= HAL_USART_STATE_READY;
00258
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @brief  DeInitializes the USART peripheral.
00264   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00265   *                the configuration information for the specified USART module.
00266   * @retval HAL status
00267   */
00268 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00269 {
00270    /* Check the USART handle allocation */
00271   if(husart == NULL)
00272   {
00273     return HAL_ERROR;
00274   }
00275
00276   /* Check the parameters */
00277   assert_param(IS_USART_INSTANCE(husart->Instance));
00278
00279   husart->State = HAL_USART_STATE_BUSY;
00280
00281   /* Disable the Peripheral */
00282   __HAL_USART_DISABLE(husart);
00283
00284   /* DeInit the low level hardware */
00285   HAL_USART_MspDeInit(husart);
00286
00287   husart->ErrorCode = HAL_USART_ERROR_NONE;
00288   husart->State = HAL_USART_STATE_RESET;
00289
00290   /* Release Lock */
00291   __HAL_UNLOCK(husart);
00292
00293   return HAL_OK;
00294 }
00295
00296 /**
00297   * @brief  USART MSP Init.
00298   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00299   *                the configuration information for the specified USART module.
00300   * @retval None
00301   */
00302  __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00303 {
00304   /* Prevent unused argument(s) compilation warning */
00305   UNUSED(husart);
00306   /* NOTE: This function Should not be modified, when the callback is needed,
00307            the HAL_USART_MspInit could be implemented in the user file
00308    */
00309 }
00310
00311 /**
00312   * @brief  USART MSP DeInit.
00313   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00314   *                the configuration information for the specified USART module.
00315   * @retval None
00316   */
00317  __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00318 {
00319   /* Prevent unused argument(s) compilation warning */
00320   UNUSED(husart);
00321   /* NOTE: This function Should not be modified, when the callback is needed,
00322            the HAL_USART_MspDeInit could be implemented in the user file
00323    */
00324 }
00325
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00331   *  @brief   USART Transmit and Receive functions
00332   *
00333 @verbatim
00334   ==============================================================================
00335                          ##### IO operation functions #####
00336   ==============================================================================
00337   [..]
00338     This subsection provides a set of functions allowing to manage the USART synchronous
00339     data transfers.
00340
00341   [..]
00342     The USART supports master mode only: it cannot receive or send data related to an input
00343     clock (SCLK is always an output).
00344
00345     (#) There are two modes of transfer:
00346         (++) Blocking mode: The communication is performed in polling mode.
00347              The HAL status of all data processing is returned by the same function
00348              after finishing transfer.
00349         (++) No-Blocking mode: The communication is performed using Interrupts
00350              or DMA, These API's return the HAL status.
00351              The end of the data processing will be indicated through the
00352              dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00353              using DMA mode.
00354              The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
00355               user callbacks
00356              will be executed respectively at the end of the transmit or Receive process
00357              The HAL_USART_ErrorCallback() user callback will be executed when a communication
00358              error is detected
00359
00360     (#) Blocking mode APIs are :
00361         (++) HAL_USART_Transmit() in simplex mode
00362         (++) HAL_USART_Receive() in full duplex receive only
00363         (++) HAL_USART_TransmitReceive() in full duplex mode
00364
00365     (#) Non Blocking mode APIs with Interrupt are :
00366         (++) HAL_USART_Transmit_IT()in simplex mode
00367         (++) HAL_USART_Receive_IT() in full duplex receive only
00368         (++) HAL_USART_TransmitReceive_IT() in full duplex mode
00369         (++) HAL_USART_IRQHandler()
00370
00371     (#) Non Blocking mode functions with DMA are :
00372         (++) HAL_USART_Transmit_DMA()in simplex mode
00373         (++) HAL_USART_Receive_DMA() in full duplex receive only
00374         (++) HAL_USART_TransmitReceie_DMA() in full duplex mode
00375         (++) HAL_USART_DMAPause()
00376         (++) HAL_USART_DMAResume()
00377         (++) HAL_USART_DMAStop()
00378
00379     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00380         (++) HAL_USART_TxHalfCpltCallback()
00381         (++) HAL_USART_TxCpltCallback()
00382         (++) HAL_USART_RxHalfCpltCallback()
00383         (++) HAL_USART_RxCpltCallback()
00384         (++) HAL_USART_ErrorCallback()
00385         (++) HAL_USART_TxRxCpltCallback()
00386
00387 @endverbatim
00388   * @{
00389   */
00390
00391 /**
00392   * @brief  Simplex Send an amount of data in blocking mode.
00393   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00394   *                the configuration information for the specified USART module.
00395   * @param  pTxData: Pointer to data buffer
00396   * @param  Size: Amount of data to be sent
00397   * @param  Timeout: Timeout duration
00398   * @retval HAL status
00399   */
00400 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00401 {
00402   uint16_t* tmp;
00403
00404   if(husart->State == HAL_USART_STATE_READY)
00405   {
00406     if((pTxData == NULL) || (Size == 0U))
00407     {
00408       return  HAL_ERROR;
00409     }
00410
00411     /* Process Locked */
00412     __HAL_LOCK(husart);
00413
00414     husart->ErrorCode = HAL_USART_ERROR_NONE;
00415     husart->State = HAL_USART_STATE_BUSY_TX;
00416
00417     husart->TxXferSize = Size;
00418     husart->TxXferCount = Size;
00419     while(husart->TxXferCount > 0U)
00420     {
00421       husart->TxXferCount--;
00422       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00423       {
00424         /* Wait for TC flag in order to write data in DR */
00425         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00426         {
00427           return HAL_TIMEOUT;
00428         }
00429         tmp = (uint16_t*) pTxData;
00430         husart->Instance->DR = (*tmp & (uint16_t)0x01FFU);
00431         if(husart->Init.Parity == USART_PARITY_NONE)
00432         {
00433           pTxData += 2U;
00434         }
00435         else
00436         {
00437           pTxData += 1U;
00438         }
00439       }
00440       else
00441       {
00442         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00443         {
00444           return HAL_TIMEOUT;
00445         }
00446         husart->Instance->DR = (*pTxData++ & (uint8_t)0xFFU);
00447       }
00448     }
00449
00450     if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
00451     {
00452       return HAL_TIMEOUT;
00453     }
00454
00455     husart->State = HAL_USART_STATE_READY;
00456
00457     /* Process Unlocked */
00458     __HAL_UNLOCK(husart);
00459
00460     return HAL_OK;
00461   }
00462   else
00463   {
00464     return HAL_BUSY;
00465   }
00466 }
00467
00468 /**
00469   * @brief  Full-Duplex Receive an amount of data in blocking mode.
00470   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00471   *                the configuration information for the specified USART module.
00472   * @param  pRxData: Pointer to data buffer
00473   * @param  Size: Amount of data to be received
00474   * @param  Timeout: Timeout duration
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00478 {
00479   uint16_t* tmp;
00480
00481   if(husart->State == HAL_USART_STATE_READY)
00482   {
00483     if((pRxData == NULL) || (Size == 0U))
00484     {
00485       return  HAL_ERROR;
00486     }
00487     /* Process Locked */
00488     __HAL_LOCK(husart);
00489
00490     husart->ErrorCode = HAL_USART_ERROR_NONE;
00491     husart->State = HAL_USART_STATE_BUSY_RX;
00492
00493     husart->RxXferSize = Size;
00494     husart->RxXferCount = Size;
00495     /* Check the remain data to be received */
00496     while(husart->RxXferCount > 0U)
00497     {
00498       husart->RxXferCount--;
00499       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00500       {
00501         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
00502         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00503         {
00504           return HAL_TIMEOUT;
00505         }
00506         /* Send dummy byte in order to generate clock */
00507         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
00508
00509         /* Wait for RXNE Flag */
00510         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00511         {
00512           return HAL_TIMEOUT;
00513         }
00514         tmp = (uint16_t*) pRxData ;
00515         if(husart->Init.Parity == USART_PARITY_NONE)
00516         {
00517           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
00518           pRxData +=2;
00519         }
00520         else
00521         {
00522           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
00523           pRxData +=1;
00524         }
00525       }
00526       else
00527       {
00528         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
00529         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00530         {
00531           return HAL_TIMEOUT;
00532         }
00533
00534         /* Send Dummy Byte in order to generate clock */
00535         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FFU);
00536
00537         /* Wait until RXNE flag is set to receive the byte */
00538         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00539         {
00540           return HAL_TIMEOUT;
00541         }
00542         if(husart->Init.Parity == USART_PARITY_NONE)
00543         {
00544           /* Receive data */
00545           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
00546         }
00547         else
00548         {
00549           /* Receive data */
00550           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
00551         }
00552
00553       }
00554     }
00555
00556     husart->State = HAL_USART_STATE_READY;
00557
00558     /* Process Unlocked */
00559     __HAL_UNLOCK(husart);
00560
00561     return HAL_OK;
00562   }
00563   else
00564   {
00565     return HAL_BUSY;
00566   }
00567 }
00568
00569 /**
00570   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
00571   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00572   *                the configuration information for the specified USART module.
00573   * @param  pTxData: Pointer to data transmitted buffer
00574   * @param  pRxData: Pointer to data received buffer
00575   * @param  Size: Amount of data to be sent
00576    * @param  Timeout: Timeout duration
00577   * @retval HAL status
00578   */
00579 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00580 {
00581   uint16_t* tmp;
00582
00583   if(husart->State == HAL_USART_STATE_READY)
00584   {
00585     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00586     {
00587       return  HAL_ERROR;
00588     }
00589     /* Process Locked */
00590     __HAL_LOCK(husart);
00591
00592     husart->ErrorCode = HAL_USART_ERROR_NONE;
00593     husart->State = HAL_USART_STATE_BUSY_RX;
00594
00595     husart->RxXferSize = Size;
00596     husart->TxXferSize = Size;
00597     husart->TxXferCount = Size;
00598     husart->RxXferCount = Size;
00599
00600     /* Check the remain data to be received */
00601     while(husart->TxXferCount > 0U)
00602     {
00603       husart->TxXferCount--;
00604       husart->RxXferCount--;
00605       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00606       {
00607         /* Wait for TC flag in order to write data in DR */
00608         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00609         {
00610           return HAL_TIMEOUT;
00611         }
00612         tmp = (uint16_t*) pTxData;
00613         husart->Instance->DR = (*tmp & (uint16_t)0x01FFU);
00614         if(husart->Init.Parity == USART_PARITY_NONE)
00615         {
00616           pTxData += 2U;
00617         }
00618         else
00619         {
00620           pTxData += 1U;
00621         }
00622
00623         /* Wait for RXNE Flag */
00624         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00625         {
00626           return HAL_TIMEOUT;
00627         }
00628         tmp = (uint16_t*) pRxData ;
00629         if(husart->Init.Parity == USART_PARITY_NONE)
00630         {
00631           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
00632           pRxData += 2U;
00633         }
00634         else
00635         {
00636           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
00637           pRxData += 1U;
00638         }
00639       }
00640       else
00641       {
00642         /* Wait for TC flag in order to write data in DR */
00643         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
00644         {
00645           return HAL_TIMEOUT;
00646         }
00647         husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FFU);
00648
00649         /* Wait for RXNE Flag */
00650         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
00651         {
00652           return HAL_TIMEOUT;
00653         }
00654         if(husart->Init.Parity == USART_PARITY_NONE)
00655         {
00656           /* Receive data */
00657           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
00658         }
00659         else
00660         {
00661           /* Receive data */
00662           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
00663         }
00664       }
00665     }
00666
00667     husart->State = HAL_USART_STATE_READY;
00668
00669     /* Process Unlocked */
00670     __HAL_UNLOCK(husart);
00671
00672     return HAL_OK;
00673   }
00674   else
00675   {
00676     return HAL_BUSY;
00677   }
00678 }
00679
00680 /**
00681   * @brief  Simplex Send an amount of data in non-blocking mode.
00682   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00683   *                the configuration information for the specified USART module.
00684   * @param  pTxData: Pointer to data buffer
00685   * @param  Size: Amount of data to be sent
00686   * @retval HAL status
00687   * @note   The USART errors are not managed to avoid the overrun error.
00688   */
00689 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00690 {
00691   if(husart->State == HAL_USART_STATE_READY)
00692   {
00693     if((pTxData == NULL) || (Size == 0U))
00694     {
00695       return HAL_ERROR;
00696     }
00697
00698     /* Process Locked */
00699     __HAL_LOCK(husart);
00700
00701     husart->pTxBuffPtr = pTxData;
00702     husart->TxXferSize = Size;
00703     husart->TxXferCount = Size;
00704
00705     husart->ErrorCode = HAL_USART_ERROR_NONE;
00706     husart->State = HAL_USART_STATE_BUSY_TX;
00707
00708     /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
00709        are not managed by the USART transmit process to avoid the overrun interrupt
00710        when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
00711        to benefit for the frame error and noise interrupts the USART mode should be
00712        configured only for transmit "USART_MODE_TX"
00713        The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
00714        Noise error interrupt */
00715
00716     /* Process Unlocked */
00717     __HAL_UNLOCK(husart);
00718
00719     /* Enable the USART Transmit Data Register Empty Interrupt */
00720     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00721
00722     return HAL_OK;
00723   }
00724   else
00725   {
00726     return HAL_BUSY;
00727   }
00728 }
00729
00730 /**
00731   * @brief  Simplex Receive an amount of data in non-blocking mode.
00732   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00733   *                the configuration information for the specified USART module.
00734   * @param  pRxData: Pointer to data buffer
00735   * @param  Size: Amount of data to be received
00736   * @retval HAL status
00737   */
00738 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00739 {
00740   if(husart->State == HAL_USART_STATE_READY)
00741   {
00742     if((pRxData == NULL) || (Size == 0U))
00743     {
00744       return HAL_ERROR;
00745     }
00746     /* Process Locked */
00747     __HAL_LOCK(husart);
00748
00749     husart->pRxBuffPtr = pRxData;
00750     husart->RxXferSize = Size;
00751     husart->RxXferCount = Size;
00752
00753     husart->ErrorCode = HAL_USART_ERROR_NONE;
00754     husart->State = HAL_USART_STATE_BUSY_RX;
00755
00756     /* Process Unlocked */
00757     __HAL_UNLOCK(husart);
00758
00759     /* Enable the USART Data Register not empty Interrupt */
00760     __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
00761
00762     /* Enable the USART Parity Error Interrupt */
00763     __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
00764
00765     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00766     __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
00767
00768     /* Send dummy byte in order to generate the clock for the slave to send data */
00769     husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
00770
00771     return HAL_OK;
00772   }
00773   else
00774   {
00775     return HAL_BUSY;
00776   }
00777 }
00778
00779 /**
00780   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
00781   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00782   *                the configuration information for the specified USART module.
00783   * @param  pTxData: Pointer to data transmitted buffer
00784   * @param  pRxData: Pointer to data received buffer
00785   * @param  Size: Amount of data to be received
00786   * @retval HAL status
00787   */
00788 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
00789 {
00790   if(husart->State == HAL_USART_STATE_READY)
00791   {
00792     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00793     {
00794       return HAL_ERROR;
00795     }
00796     /* Process Locked */
00797     __HAL_LOCK(husart);
00798
00799     husart->pRxBuffPtr = pRxData;
00800     husart->RxXferSize = Size;
00801     husart->RxXferCount = Size;
00802     husart->pTxBuffPtr = pTxData;
00803     husart->TxXferSize = Size;
00804     husart->TxXferCount = Size;
00805
00806     husart->ErrorCode = HAL_USART_ERROR_NONE;
00807     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00808
00809     /* Process Unlocked */
00810     __HAL_UNLOCK(husart);
00811
00812     /* Enable the USART Data Register not empty Interrupt */
00813     __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
00814
00815     /* Enable the USART Parity Error Interrupt */
00816     __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
00817
00818     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00819     __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
00820
00821     /* Enable the USART Transmit Data Register Empty Interrupt */
00822     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00823
00824     return HAL_OK;
00825   }
00826   else
00827   {
00828     return HAL_BUSY;
00829   }
00830 }
00831
00832 /**
00833   * @brief  Simplex Send an amount of data in non-blocking mode.
00834   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00835   *                the configuration information for the specified USART module.
00836   * @param  pTxData: Pointer to data buffer
00837   * @param  Size: Amount of data to be sent
00838   * @retval HAL status
00839   */
00840 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00841 {
00842   uint32_t *tmp;
00843
00844   if(husart->State == HAL_USART_STATE_READY)
00845   {
00846     if((pTxData == NULL) || (Size == 0U))
00847     {
00848       return HAL_ERROR;
00849     }
00850     /* Process Locked */
00851     __HAL_LOCK(husart);
00852
00853     husart->pTxBuffPtr = pTxData;
00854     husart->TxXferSize = Size;
00855     husart->TxXferCount = Size;
00856
00857     husart->ErrorCode = HAL_USART_ERROR_NONE;
00858     husart->State = HAL_USART_STATE_BUSY_TX;
00859
00860     /* Set the USART DMA transfer complete callback */
00861     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00862
00863     /* Set the USART DMA Half transfer complete callback */
00864     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00865
00866     /* Set the DMA error callback */
00867     husart->hdmatx->XferErrorCallback = USART_DMAError;
00868
00869     /* Enable the USART transmit DMA Stream */
00870     tmp = (uint32_t*)&pTxData;
00871     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
00872
00873     /* Clear the TC flag in the SR register by writing 0 to it */
00874     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
00875
00876     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00877        in the USART CR3 register */
00878     husart->Instance->CR3 |= USART_CR3_DMAT;
00879
00880     /* Process Unlocked */
00881     __HAL_UNLOCK(husart);
00882
00883     return HAL_OK;
00884   }
00885   else
00886   {
00887     return HAL_BUSY;
00888   }
00889 }
00890
00891 /**
00892   * @brief  Full-Duplex Receive an amount of data in non-blocking mode.
00893   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00894   *                the configuration information for the specified USART module.
00895   * @param  pRxData: Pointer to data buffer
00896   * @param  Size: Amount of data to be received
00897   * @retval HAL status
00898   * @note   The USART DMA transmit stream must be configured in order to generate the clock for the slave.
00899   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
00900   */
00901 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00902 {
00903   uint32_t *tmp;
00904
00905   if(husart->State == HAL_USART_STATE_READY)
00906   {
00907     if((pRxData == NULL) || (Size == 0U))
00908     {
00909       return HAL_ERROR;
00910     }
00911
00912     /* Process Locked */
00913     __HAL_LOCK(husart);
00914
00915     husart->pRxBuffPtr = pRxData;
00916     husart->RxXferSize = Size;
00917     husart->pTxBuffPtr = pRxData;
00918     husart->TxXferSize = Size;
00919
00920     husart->ErrorCode = HAL_USART_ERROR_NONE;
00921     husart->State = HAL_USART_STATE_BUSY_RX;
00922
00923     /* Set the USART DMA Rx transfer complete callback */
00924     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00925
00926     /* Set the USART DMA Half transfer complete callback */
00927     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00928
00929     /* Set the USART DMA Rx transfer error callback */
00930     husart->hdmarx->XferErrorCallback = USART_DMAError;
00931
00932     /* Enable the USART receive DMA Stream */
00933     tmp = (uint32_t*)&pRxData;
00934     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
00935
00936     /* Enable the USART transmit DMA Stream: the transmit stream is used in order
00937        to generate in the non-blocking mode the clock to the slave device,
00938        this mode isn't a simplex receive mode but a full-duplex receive one */
00939     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
00940
00941     /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
00942        when using the USART in circular mode */
00943     __HAL_USART_CLEAR_OREFLAG(husart);
00944
00945     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00946        in the USART CR3 register */
00947     husart->Instance->CR3 |= USART_CR3_DMAR;
00948
00949     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00950        in the USART CR3 register */
00951     husart->Instance->CR3 |= USART_CR3_DMAT;
00952
00953     /* Process Unlocked */
00954     __HAL_UNLOCK(husart);
00955
00956     return HAL_OK;
00957   }
00958   else
00959   {
00960     return HAL_BUSY;
00961   }
00962 }
00963
00964 /**
00965   * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
00966   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00967   *                the configuration information for the specified USART module.
00968   * @param  pTxData: Pointer to data transmitted buffer
00969   * @param  pRxData: Pointer to data received buffer
00970   * @param  Size: Amount of data to be received
00971   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
00972   * @retval HAL status
00973   */
00974 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
00975 {
00976   uint32_t *tmp;
00977
00978   if(husart->State == HAL_USART_STATE_READY)
00979   {
00980     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00981     {
00982       return HAL_ERROR;
00983     }
00984     /* Process Locked */
00985     __HAL_LOCK(husart);
00986
00987     husart->pRxBuffPtr = pRxData;
00988     husart->RxXferSize = Size;
00989     husart->pTxBuffPtr = pTxData;
00990     husart->TxXferSize = Size;
00991
00992     husart->ErrorCode = HAL_USART_ERROR_NONE;
00993     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00994
00995     /* Set the USART DMA Rx transfer complete callback */
00996     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00997
00998     /* Set the USART DMA Half transfer complete callback */
00999     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01000
01001     /* Set the USART DMA Tx transfer complete callback */
01002     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01003
01004     /* Set the USART DMA Half transfer complete callback */
01005     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01006
01007     /* Set the USART DMA Tx transfer error callback */
01008     husart->hdmatx->XferErrorCallback = USART_DMAError;
01009
01010     /* Set the USART DMA Rx transfer error callback */
01011     husart->hdmarx->XferErrorCallback = USART_DMAError;
01012
01013     /* Enable the USART receive DMA Stream */
01014     tmp = (uint32_t*)&pRxData;
01015     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
01016
01017     /* Enable the USART transmit DMA Stream */
01018     tmp = (uint32_t*)&pTxData;
01019     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
01020
01021     /* Clear the TC flag in the SR register by writing 0 to it */
01022     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
01023
01024     /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
01025     __HAL_USART_CLEAR_OREFLAG(husart);
01026
01027     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01028        in the USART CR3 register */
01029     husart->Instance->CR3 |= USART_CR3_DMAR;
01030
01031     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01032        in the USART CR3 register */
01033     husart->Instance->CR3 |= USART_CR3_DMAT;
01034
01035     /* Process Unlocked */
01036     __HAL_UNLOCK(husart);
01037
01038     return HAL_OK;
01039   }
01040   else
01041   {
01042     return HAL_BUSY;
01043   }
01044 }
01045
01046 /**
01047   * @brief Pauses the DMA Transfer.
01048   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01049   *                the configuration information for the specified USART module.
01050   * @retval HAL status
01051   */
01052 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01053 {
01054   /* Process Locked */
01055   __HAL_LOCK(husart);
01056
01057   /* Disable the USART DMA Tx request */
01058   husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
01059
01060   /* Process Unlocked */
01061   __HAL_UNLOCK(husart);
01062
01063   return HAL_OK;
01064 }
01065
01066 /**
01067   * @brief Resumes the DMA Transfer.
01068   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01069   *                the configuration information for the specified USART module.
01070   * @retval HAL status
01071   */
01072 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01073 {
01074   /* Process Locked */
01075   __HAL_LOCK(husart);
01076
01077   /* Enable the USART DMA Tx request */
01078   husart->Instance->CR3 |= USART_CR3_DMAT;
01079
01080   /* Process Unlocked */
01081   __HAL_UNLOCK(husart);
01082
01083   return HAL_OK;
01084 }
01085
01086 /**
01087   * @brief Stops the DMA Transfer.
01088   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01089   *                the configuration information for the specified USART module.
01090   * @retval HAL status
01091   */
01092 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01093 {
01094   /* The Lock is not implemented on this API to allow the user application
01095      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
01096      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01097      and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
01098      */
01099
01100   /* Abort the USART DMA Tx Stream */
01101   if(husart->hdmatx != NULL)
01102   {
01103     HAL_DMA_Abort(husart->hdmatx);
01104   }
01105   /* Abort the USART DMA Rx Stream */
01106   if(husart->hdmarx != NULL)
01107   {
01108     HAL_DMA_Abort(husart->hdmarx);
01109   }
01110
01111   /* Disable the USART Tx/Rx DMA requests */
01112   husart->Instance->CR3 &= ~USART_CR3_DMAT;
01113   husart->Instance->CR3 &= ~USART_CR3_DMAR;
01114
01115   husart->State = HAL_USART_STATE_READY;
01116
01117   return HAL_OK;
01118 }
01119
01120 /**
01121   * @brief  This function handles USART interrupt request.
01122   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01123   *                the configuration information for the specified USART module.
01124   * @retval None
01125   */
01126 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
01127 {
01128   uint32_t tmp1 = 0U, tmp2 = 0U;
01129
01130   tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE);
01131   tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE);
01132   /* USART parity error interrupt occurred -----------------------------------*/
01133   if((tmp1 != RESET) && (tmp2 != RESET))
01134   {
01135     __HAL_USART_CLEAR_PEFLAG(husart);
01136     husart->ErrorCode |= HAL_USART_ERROR_PE;
01137   }
01138
01139   tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE);
01140   tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
01141   /* USART frame error interrupt occurred ------------------------------------*/
01142   if((tmp1 != RESET) && (tmp2 != RESET))
01143   {
01144     __HAL_USART_CLEAR_FEFLAG(husart);
01145     husart->ErrorCode |= HAL_USART_ERROR_FE;
01146   }
01147
01148   tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE);
01149   tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
01150   /* USART noise error interrupt occurred ------------------------------------*/
01151   if((tmp1 != RESET) && (tmp2 != RESET))
01152   {
01153     __HAL_USART_CLEAR_NEFLAG(husart);
01154     husart->ErrorCode |= HAL_USART_ERROR_NE;
01155   }
01156
01157   tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE);
01158   tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
01159   /* USART Over-Run interrupt occurred ---------------------------------------*/
01160   if((tmp1 != RESET) && (tmp2 != RESET))
01161   {
01162     __HAL_USART_CLEAR_OREFLAG(husart);
01163     husart->ErrorCode |= HAL_USART_ERROR_ORE;
01164   }
01165
01166   if(husart->ErrorCode != HAL_USART_ERROR_NONE)
01167   {
01168     /* Set the USART state ready to be able to start again the process */
01169     husart->State = HAL_USART_STATE_READY;
01170
01171     HAL_USART_ErrorCallback(husart);
01172   }
01173
01174   tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE);
01175   tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE);
01176   /* USART in mode Receiver --------------------------------------------------*/
01177   if((tmp1 != RESET) && (tmp2 != RESET))
01178   {
01179     if(husart->State == HAL_USART_STATE_BUSY_RX)
01180     {
01181       USART_Receive_IT(husart);
01182     }
01183     else
01184     {
01185       USART_TransmitReceive_IT(husart);
01186     }
01187   }
01188
01189   tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE);
01190   tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE);
01191   /* USART in mode Transmitter -----------------------------------------------*/
01192   if((tmp1 != RESET) && (tmp2 != RESET))
01193   {
01194     if(husart->State == HAL_USART_STATE_BUSY_TX)
01195     {
01196       USART_Transmit_IT(husart);
01197     }
01198     else
01199     {
01200       USART_TransmitReceive_IT(husart);
01201     }
01202   }
01203
01204   tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
01205   tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
01206   /* USART in mode Transmitter (transmission end) ----------------------------*/
01207   if((tmp1 != RESET) && (tmp2 != RESET))
01208   {
01209     USART_EndTransmit_IT(husart);
01210   }
01211 }
01212
01213 /**
01214   * @brief  Tx Transfer completed callbacks.
01215   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01216   *                the configuration information for the specified USART module.
01217   * @retval None
01218   */
01219  __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
01220 {
01221   /* Prevent unused argument(s) compilation warning */
01222   UNUSED(husart);
01223   /* NOTE: This function Should not be modified, when the callback is needed,
01224            the HAL_USART_TxCpltCallback could be implemented in the user file
01225    */
01226 }
01227
01228 /**
01229   * @brief  Tx Half Transfer completed callbacks.
01230   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01231   *                the configuration information for the specified USART module.
01232   * @retval None
01233   */
01234  __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
01235 {
01236   /* Prevent unused argument(s) compilation warning */
01237   UNUSED(husart);
01238   /* NOTE: This function Should not be modified, when the callback is needed,
01239            the HAL_USART_TxCpltCallback could be implemented in the user file
01240    */
01241 }
01242
01243 /**
01244   * @brief  Rx Transfer completed callbacks.
01245   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01246   *                the configuration information for the specified USART module.
01247   * @retval None
01248   */
01249 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
01250 {
01251   /* Prevent unused argument(s) compilation warning */
01252   UNUSED(husart);
01253   /* NOTE: This function Should not be modified, when the callback is needed,
01254            the HAL_USART_TxCpltCallback could be implemented in the user file
01255    */
01256 }
01257
01258 /**
01259   * @brief  Rx Half Transfer completed callbacks.
01260   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01261   *                the configuration information for the specified USART module.
01262   * @retval None
01263   */
01264 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
01265 {
01266   /* Prevent unused argument(s) compilation warning */
01267   UNUSED(husart);
01268   /* NOTE: This function Should not be modified, when the callback is needed,
01269            the HAL_USART_TxCpltCallback could be implemented in the user file
01270    */
01271 }
01272
01273 /**
01274   * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
01275   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01276   *                the configuration information for the specified USART module.
01277   * @retval None
01278   */
01279 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
01280 {
01281   /* Prevent unused argument(s) compilation warning */
01282   UNUSED(husart);
01283   /* NOTE: This function Should not be modified, when the callback is needed,
01284            the HAL_USART_TxCpltCallback could be implemented in the user file
01285    */
01286 }
01287
01288 /**
01289   * @brief  USART error callbacks.
01290   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01291   *                the configuration information for the specified USART module.
01292   * @retval None
01293   */
01294  __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
01295 {
01296   /* Prevent unused argument(s) compilation warning */
01297   UNUSED(husart);
01298   /* NOTE: This function Should not be modified, when the callback is needed,
01299            the HAL_USART_ErrorCallback could be implemented in the user file
01300    */
01301 }
01302
01303 /**
01304   * @}
01305   */
01306
01307 /** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
01308   *  @brief   USART State and Errors functions
01309   *
01310 @verbatim
01311   ==============================================================================
01312                   ##### Peripheral State and Errors functions #####
01313   ==============================================================================
01314   [..]
01315     This subsection provides a set of functions allowing to return the State of
01316     USART communication
01317     process, return Peripheral Errors occurred during communication process
01318      (+) HAL_USART_GetState() API can be helpful to check in run-time the state
01319          of the USART peripheral.
01320      (+) HAL_USART_GetError() check in run-time errors that could be occurred during
01321          communication.
01322 @endverbatim
01323   * @{
01324   */
01325
01326 /**
01327   * @brief  Returns the USART state.
01328   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01329   *                the configuration information for the specified USART module.
01330   * @retval HAL state
01331   */
01332 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
01333 {
01334   return husart->State;
01335 }
01336
01337 /**
01338   * @brief  Return the USART error code
01339   * @param  husart : pointer to a USART_HandleTypeDef structure that contains
01340   *              the configuration information for the specified USART.
01341   * @retval USART Error Code
01342   */
01343 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
01344 {
01345   return husart->ErrorCode;
01346 }
01347
01348 /**
01349   * @}
01350   */
01351
01352
01353 /**
01354   * @brief  DMA USART transmit process complete callback.
01355   * @param  hdma: DMA handle
01356   * @retval None
01357   */
01358 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01359 {
01360   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01361   /* DMA Normal mode */
01362   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01363   {
01364     husart->TxXferCount = 0U;
01365     if(husart->State == HAL_USART_STATE_BUSY_TX)
01366     {
01367       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01368          in the USART CR3 register */
01369       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01370
01371       /* Enable the USART Transmit Complete Interrupt */
01372       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01373     }
01374   }
01375   /* DMA Circular mode */
01376   else
01377   {
01378     if(husart->State == HAL_USART_STATE_BUSY_TX)
01379     {
01380       HAL_USART_TxCpltCallback(husart);
01381     }
01382   }
01383 }
01384
01385 /**
01386   * @brief DMA USART transmit process half complete callback
01387   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01388   *                the configuration information for the specified DMA module.
01389   * @retval None
01390   */
01391 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01392 {
01393   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01394
01395   HAL_USART_TxHalfCpltCallback(husart);
01396 }
01397
01398 /**
01399   * @brief  DMA USART receive process complete callback.
01400   * @param  hdma: DMA handle
01401   * @retval None
01402   */
01403 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01404 {
01405   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01406   /* DMA Normal mode */
01407   if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
01408   {
01409     husart->RxXferCount = 0U;
01410     if(husart->State == HAL_USART_STATE_BUSY_RX)
01411     {
01412       /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
01413          in the USART CR3 register */
01414       husart->Instance->CR3 &= ~(USART_CR3_DMAR);
01415
01416       husart->State= HAL_USART_STATE_READY;
01417       HAL_USART_RxCpltCallback(husart);
01418     }
01419     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01420     else
01421     {
01422       /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
01423          in the USART CR3 register */
01424       husart->Instance->CR3 &= ~(USART_CR3_DMAR);
01425       husart->Instance->CR3 &= ~(USART_CR3_DMAT);
01426
01427       husart->State= HAL_USART_STATE_READY;
01428       HAL_USART_TxRxCpltCallback(husart);
01429     }
01430   }
01431   /* DMA circular mode */
01432   else
01433   {
01434     if(husart->State == HAL_USART_STATE_BUSY_RX)
01435     {
01436       HAL_USART_RxCpltCallback(husart);
01437     }
01438     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01439     else
01440     {
01441       HAL_USART_TxRxCpltCallback(husart);
01442     }
01443   }
01444 }
01445
01446 /**
01447   * @brief DMA USART receive process half complete callback
01448   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01449   *                the configuration information for the specified DMA module.
01450   * @retval None
01451   */
01452 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01453 {
01454   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01455
01456   HAL_USART_RxHalfCpltCallback(husart);
01457 }
01458
01459 /**
01460   * @brief  DMA USART communication error callback.
01461   * @param  hdma: DMA handle
01462   * @retval None
01463   */
01464 static void USART_DMAError(DMA_HandleTypeDef *hdma)
01465 {
01466   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01467
01468   husart->RxXferCount = 0U;
01469   husart->TxXferCount = 0U;
01470   husart->ErrorCode |= HAL_USART_ERROR_DMA;
01471   husart->State= HAL_USART_STATE_READY;
01472
01473   HAL_USART_ErrorCallback(husart);
01474 }
01475
01476 /**
01477   * @brief  This function handles USART Communication Timeout.
01478   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01479   *                the configuration information for the specified USART module.
01480   * @param  Flag: specifies the USART flag to check.
01481   * @param  Status: The new Flag status (SET or RESET).
01482   * @param  Timeout: Timeout duration
01483   * @retval HAL status
01484   */
01485 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01486 {
01487   uint32_t tickstart = 0U;
01488
01489   /* Get tick */
01490   tickstart = HAL_GetTick();
01491
01492   /* Wait until flag is set */
01493   if(Status == RESET)
01494   {
01495     while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
01496     {
01497       /* Check for the Timeout */
01498       if(Timeout != HAL_MAX_DELAY)
01499       {
01500         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01501         {
01502           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01503           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01504           __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01505           __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01506           __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01507
01508           husart->State= HAL_USART_STATE_READY;
01509
01510           /* Process Unlocked */
01511           __HAL_UNLOCK(husart);
01512
01513           return HAL_TIMEOUT;
01514         }
01515       }
01516     }
01517   }
01518   else
01519   {
01520     while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
01521     {
01522       /* Check for the Timeout */
01523       if(Timeout != HAL_MAX_DELAY)
01524       {
01525         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01526         {
01527           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01528           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01529           __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01530           __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01531           __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01532
01533           husart->State= HAL_USART_STATE_READY;
01534
01535           /* Process Unlocked */
01536           __HAL_UNLOCK(husart);
01537
01538           return HAL_TIMEOUT;
01539         }
01540       }
01541     }
01542   }
01543   return HAL_OK;
01544 }
01545
01546
01547 /**
01548   * @brief  Simplex Send an amount of data in non-blocking mode.
01549   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01550   *                the configuration information for the specified USART module.
01551   * @retval HAL status
01552   * @note   The USART errors are not managed to avoid the overrun error.
01553   */
01554 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
01555 {
01556   uint16_t* tmp;
01557
01558   if(husart->State == HAL_USART_STATE_BUSY_TX)
01559   {
01560     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
01561     {
01562       tmp = (uint16_t*) husart->pTxBuffPtr;
01563       husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
01564       if(husart->Init.Parity == USART_PARITY_NONE)
01565       {
01566         husart->pTxBuffPtr += 2U;
01567       }
01568       else
01569       {
01570         husart->pTxBuffPtr += 1U;
01571       }
01572     }
01573     else
01574     {
01575       husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FFU);
01576     }
01577
01578     if(--husart->TxXferCount == 0U)
01579     {
01580       /* Disable the USART Transmit data register empty Interrupt */
01581       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01582
01583       /* Enable the USART Transmit Complete Interrupt */
01584       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01585     }
01586     return HAL_OK;
01587   }
01588   else
01589   {
01590     return HAL_BUSY;
01591   }
01592 }
01593
01594 /**
01595   * @brief  Wraps up transmission in non blocking mode.
01596   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01597   *                the configuration information for the specified USART module.
01598   * @retval HAL status
01599   */
01600 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
01601 {
01602   /* Disable the USART Transmit Complete Interrupt */
01603   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
01604
01605   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01606   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01607
01608   husart->State = HAL_USART_STATE_READY;
01609
01610   HAL_USART_TxCpltCallback(husart);
01611
01612   return HAL_OK;
01613 }
01614
01615 /**
01616   * @brief  Simplex Receive an amount of data in non-blocking mode.
01617   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01618   *                the configuration information for the specified USART module.
01619   * @retval HAL status
01620   */
01621 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
01622 {
01623   uint16_t* tmp;
01624   if(husart->State == HAL_USART_STATE_BUSY_RX)
01625   {
01626     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
01627     {
01628       tmp = (uint16_t*) husart->pRxBuffPtr;
01629       if(husart->Init.Parity == USART_PARITY_NONE)
01630       {
01631         *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
01632         husart->pRxBuffPtr += 2U;
01633       }
01634       else
01635       {
01636         *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
01637         husart->pRxBuffPtr += 1U;
01638       }
01639       if(--husart->RxXferCount != 0x00U)
01640       {
01641         /* Send dummy byte in order to generate the clock for the slave to send the next data */
01642         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FFU);
01643       }
01644     }
01645     else
01646     {
01647       if(husart->Init.Parity == USART_PARITY_NONE)
01648       {
01649         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
01650       }
01651       else
01652       {
01653         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
01654       }
01655
01656       if(--husart->RxXferCount != 0x00U)
01657       {
01658         /* Send dummy byte in order to generate the clock for the slave to send the next data */
01659         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FFU);
01660       }
01661     }
01662
01663     if(husart->RxXferCount == 0U)
01664     {
01665       /* Disable the USART RXNE Interrupt */
01666       __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01667
01668       /* Disable the USART Parity Error Interrupt */
01669       __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01670
01671       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01672       __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01673
01674       husart->State = HAL_USART_STATE_READY;
01675       HAL_USART_RxCpltCallback(husart);
01676
01677       return HAL_OK;
01678     }
01679     return HAL_OK;
01680   }
01681   else
01682   {
01683     return HAL_BUSY;
01684   }
01685 }
01686
01687 /**
01688   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
01689   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01690   *                the configuration information for the specified USART module.
01691   * @retval HAL status
01692   */
01693 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
01694 {
01695   uint16_t* tmp;
01696
01697   if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
01698   {
01699     if(husart->TxXferCount != 0x00U)
01700     {
01701       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
01702       {
01703         if(husart->Init.WordLength == USART_WORDLENGTH_9B)
01704         {
01705           tmp = (uint16_t*) husart->pTxBuffPtr;
01706           husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
01707           if(husart->Init.Parity == USART_PARITY_NONE)
01708           {
01709             husart->pTxBuffPtr += 2U;
01710           }
01711           else
01712           {
01713             husart->pTxBuffPtr += 1U;
01714           }
01715         }
01716         else
01717         {
01718           husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FFU);
01719         }
01720         husart->TxXferCount--;
01721
01722         /* Check the latest data transmitted */
01723         if(husart->TxXferCount == 0U)
01724         {
01725            __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01726         }
01727       }
01728     }
01729
01730     if(husart->RxXferCount != 0x00U)
01731     {
01732       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
01733       {
01734         if(husart->Init.WordLength == USART_WORDLENGTH_9B)
01735         {
01736           tmp = (uint16_t*) husart->pRxBuffPtr;
01737           if(husart->Init.Parity == USART_PARITY_NONE)
01738           {
01739             *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FFU);
01740             husart->pRxBuffPtr += 2U;
01741           }
01742           else
01743           {
01744             *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FFU);
01745             husart->pRxBuffPtr += 1U;
01746           }
01747         }
01748         else
01749         {
01750           if(husart->Init.Parity == USART_PARITY_NONE)
01751           {
01752             *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FFU);
01753           }
01754           else
01755           {
01756             *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007FU);
01757           }
01758         }
01759         husart->RxXferCount--;
01760       }
01761     }
01762
01763     /* Check the latest data received */
01764     if(husart->RxXferCount == 0U)
01765     {
01766       __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01767
01768       /* Disable the USART Parity Error Interrupt */
01769       __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01770
01771       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01772       __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01773
01774       husart->State = HAL_USART_STATE_READY;
01775
01776       HAL_USART_TxRxCpltCallback(husart);
01777
01778       return HAL_OK;
01779     }
01780
01781     return HAL_OK;
01782   }
01783   else
01784   {
01785     return HAL_BUSY;
01786   }
01787 }
01788
01789 /**
01790   * @brief  Configures the USART peripheral.
01791   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01792   *                the configuration information for the specified USART module.
01793   * @retval None
01794   */
01795 static void USART_SetConfig(USART_HandleTypeDef *husart)
01796 {
01797   uint32_t tmpreg = 0x00U;
01798
01799   /* Check the parameters */
01800   assert_param(IS_USART_INSTANCE(husart->Instance));
01801   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
01802   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
01803   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
01804   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
01805   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
01806   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
01807   assert_param(IS_USART_PARITY(husart->Init.Parity));
01808   assert_param(IS_USART_MODE(husart->Init.Mode));
01809
01810   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
01811      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
01812   husart->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
01813
01814   /*---------------------------- USART CR2 Configuration ---------------------*/
01815   tmpreg = husart->Instance->CR2;
01816   /* Clear CLKEN, CPOL, CPHA and LBCL bits */
01817   tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP));
01818   /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
01819   /* Set CPOL bit according to husart->Init.CLKPolarity value */
01820   /* Set CPHA bit according to husart->Init.CLKPhase value */
01821   /* Set LBCL bit according to husart->Init.CLKLastBit value */
01822   /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
01823   tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity |
01824                       husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
01825   /* Write to USART CR2 */
01826   husart->Instance->CR2 = (uint32_t)tmpreg;
01827
01828   /*-------------------------- USART CR1 Configuration -----------------------*/
01829   tmpreg = husart->Instance->CR1;
01830
01831   /* Clear M, PCE, PS, TE, RE and OVER8 bits */
01832   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
01833                                    USART_CR1_RE | USART_CR1_OVER8));
01834
01835   /* Configure the USART Word Length, Parity and mode:
01836      Set the M bits according to husart->Init.WordLength value
01837      Set PCE and PS bits according to husart->Init.Parity value
01838      Set TE and RE bits according to husart->Init.Mode value
01839      Force OVER8 bit to 1 in order to reach the max USART frequencies */
01840   tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
01841
01842   /* Write to USART CR1 */
01843   husart->Instance->CR1 = (uint32_t)tmpreg;
01844
01845   /*-------------------------- USART CR3 Configuration -----------------------*/
01846   /* Clear CTSE and RTSE bits */
01847   husart->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
01848
01849   /*-------------------------- USART BRR Configuration -----------------------*/
01850   if((husart->Instance == USART1) || (husart->Instance == USART6))
01851   {
01852     husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
01853   }
01854   else
01855   {
01856     husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
01857   }
01858 }
01859
01860 /**
01861   * @}
01862   */
01863
01864 #endif /* HAL_USART_MODULE_ENABLED */
01865 /**
01866   * @}
01867   */
01868
01869 /**
01870   * @}
01871   */
01872
01873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_usart.h Source File

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stm32f4xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of USART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_USART_H
00040 #define __STM32F4xx_HAL_USART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup USART_Exported_Types USART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief USART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                            - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
00070                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
00071
00072   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00073                                            This parameter can be a value of @ref USART_Word_Length */
00074
00075   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00076                                            This parameter can be a value of @ref USART_Stop_Bits */
00077
00078   uint32_t Parity;                   /*!< Specifies the parity mode.
00079                                            This parameter can be a value of @ref USART_Parity
00080                                            @note When parity is enabled, the computed parity is inserted
00081                                                  at the MSB position of the transmitted data (9th bit when
00082                                                  the word length is set to 9 data bits; 8th bit when the
00083                                                  word length is set to 8 data bits). */
00084
00085   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00086                                            This parameter can be a value of @ref USART_Mode */
00087
00088   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00089                                            This parameter can be a value of @ref USART_Clock_Polarity */
00090
00091   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00092                                            This parameter can be a value of @ref USART_Clock_Phase */
00093
00094   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00095                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00096                                            This parameter can be a value of @ref USART_Last_Bit */
00097 }USART_InitTypeDef;
00098
00099 /**
00100   * @brief HAL State structures definition
00101   */
00102 typedef enum
00103 {
00104   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized   */
00105   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
00106   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */
00107   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing */
00108   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing */
00109   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00110   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */
00111   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error */
00112 }HAL_USART_StateTypeDef;
00113
00114 /**
00115   * @brief  USART handle Structure definition
00116   */
00117 typedef struct
00118 {
00119   USART_TypeDef                 *Instance;        /* USART registers base address        */
00120
00121   USART_InitTypeDef             Init;             /* Usart communication parameters      */
00122
00123   uint8_t                       *pTxBuffPtr;      /* Pointer to Usart Tx transfer Buffer */
00124
00125   uint16_t                      TxXferSize;       /* Usart Tx Transfer size              */
00126
00127   __IO uint16_t                 TxXferCount;      /* Usart Tx Transfer Counter           */
00128
00129   uint8_t                       *pRxBuffPtr;      /* Pointer to Usart Rx transfer Buffer */
00130
00131   uint16_t                      RxXferSize;       /* Usart Rx Transfer size              */
00132
00133   __IO uint16_t                 RxXferCount;      /* Usart Rx Transfer Counter           */
00134
00135   DMA_HandleTypeDef             *hdmatx;          /* Usart Tx DMA Handle parameters      */
00136
00137   DMA_HandleTypeDef             *hdmarx;          /* Usart Rx DMA Handle parameters      */
00138
00139   HAL_LockTypeDef                Lock;            /* Locking object                      */
00140
00141   __IO HAL_USART_StateTypeDef    State;           /* Usart communication state           */
00142
00143   __IO uint32_t                  ErrorCode;       /* USART Error code                    */
00144
00145 }USART_HandleTypeDef;
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /** @defgroup USART_Exported_Constants USART Exported Constants
00152   * @{
00153   */
00154
00155 /** @defgroup USART_Error_Code USART Error Code
00156   * @brief    USART Error Code
00157   * @{
00158   */
00159 #define HAL_USART_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
00160 #define HAL_USART_ERROR_PE           ((uint32_t)0x00000001U)   /*!< Parity error        */
00161 #define HAL_USART_ERROR_NE           ((uint32_t)0x00000002U)   /*!< Noise error         */
00162 #define HAL_USART_ERROR_FE           ((uint32_t)0x00000004U)   /*!< Frame error         */
00163 #define HAL_USART_ERROR_ORE          ((uint32_t)0x00000008U)   /*!< Overrun error       */
00164 #define HAL_USART_ERROR_DMA          ((uint32_t)0x00000010U)   /*!< DMA transfer error  */
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup USART_Word_Length USART Word Length
00170   * @{
00171   */
00172 #define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)
00173 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
00179   * @{
00180   */
00181 #define USART_STOPBITS_1                     ((uint32_t)0x00000000U)
00182 #define USART_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
00183 #define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
00184 #define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup USART_Parity USART Parity
00190   * @{
00191   */
00192 #define USART_PARITY_NONE                    ((uint32_t)0x00000000U)
00193 #define USART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00194 #define USART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup USART_Mode USART Mode
00200   * @{
00201   */
00202 #define USART_MODE_RX                        ((uint32_t)USART_CR1_RE)
00203 #define USART_MODE_TX                        ((uint32_t)USART_CR1_TE)
00204 #define USART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup USART_Clock USART Clock
00210   * @{
00211   */
00212 #define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000U)
00213 #define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup USART_Clock_Polarity USART Clock Polarity
00219   * @{
00220   */
00221 #define USART_POLARITY_LOW                   ((uint32_t)0x00000000U)
00222 #define USART_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup USART_Clock_Phase  USART Clock Phase
00228   * @{
00229   */
00230 #define USART_PHASE_1EDGE                    ((uint32_t)0x00000000U)
00231 #define USART_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup USART_Last_Bit  USART Last Bit
00237   * @{
00238   */
00239 #define USART_LASTBIT_DISABLE                ((uint32_t)0x00000000U)
00240 #define USART_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup USART_NACK_State USART NACK State
00246   * @{
00247   */
00248 #define USART_NACK_ENABLE           ((uint32_t)USART_CR3_NACK)
00249 #define USART_NACK_DISABLE          ((uint32_t)0x00000000U)
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup USART_Flags USART Flags
00255   *        Elements values convention: 0xXXXX
00256   *           - 0xXXXX  : Flag mask in the SR register
00257   * @{
00258   */
00259 #define USART_FLAG_TXE                       ((uint32_t)0x00000080U)
00260 #define USART_FLAG_TC                        ((uint32_t)0x00000040U)
00261 #define USART_FLAG_RXNE                      ((uint32_t)0x00000020U)
00262 #define USART_FLAG_IDLE                      ((uint32_t)0x00000010U)
00263 #define USART_FLAG_ORE                       ((uint32_t)0x00000008U)
00264 #define USART_FLAG_NE                        ((uint32_t)0x00000004U)
00265 #define USART_FLAG_FE                        ((uint32_t)0x00000002U)
00266 #define USART_FLAG_PE                        ((uint32_t)0x00000001U)
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00272   *        Elements values convention: 0xY000XXXX
00273   *           - XXXX  : Interrupt mask in the XX register
00274   *           - Y  : Interrupt source register (2bits)
00275   *                 - 01: CR1 register
00276   *                 - 10: CR2 register
00277   *                 - 11: CR3 register
00278   *
00279   * @{
00280   */
00281 #define USART_IT_PE                     ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00282 #define USART_IT_TXE                    ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00283 #define USART_IT_TC                     ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00284 #define USART_IT_RXNE                   ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00285 #define USART_IT_IDLE                   ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00286
00287 #define USART_IT_LBD                    ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
00288
00289 #define USART_IT_CTS                    ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
00290 #define USART_IT_ERR                    ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
00299 /* Exported macro ------------------------------------------------------------*/
00300 /** @defgroup USART_Exported_Macros USART Exported Macros
00301   * @{
00302   */
00303
00304 /** @brief Reset USART handle state
00305   * @param  __HANDLE__: specifies the USART Handle.
00306   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00307   * @retval None
00308   */
00309 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00310
00311 /** @brief  Checks whether the specified Smartcard flag is set or not.
00312   * @param  __HANDLE__: specifies the USART Handle.
00313   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00314   * @param  __FLAG__: specifies the flag to check.
00315   *        This parameter can be one of the following values:
00316   *            @arg USART_FLAG_TXE:  Transmit data register empty flag
00317   *            @arg USART_FLAG_TC:   Transmission Complete flag
00318   *            @arg USART_FLAG_RXNE: Receive data register not empty flag
00319   *            @arg USART_FLAG_IDLE: Idle Line detection flag
00320   *            @arg USART_FLAG_ORE:  Overrun Error flag
00321   *            @arg USART_FLAG_NE:   Noise Error flag
00322   *            @arg USART_FLAG_FE:   Framing Error flag
00323   *            @arg USART_FLAG_PE:   Parity Error flag
00324   * @retval The new state of __FLAG__ (TRUE or FALSE).
00325   */
00326 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00327
00328 /** @brief  Clears the specified Smartcard pending flags.
00329   * @param  __HANDLE__: specifies the USART Handle.
00330   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00331   * @param  __FLAG__: specifies the flag to check.
00332   *          This parameter can be any combination of the following values:
00333   *            @arg USART_FLAG_TC:   Transmission Complete flag.
00334   *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
00335   *
00336   * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
00337   *          error) and IDLE (Idle line detected) flags are cleared by software
00338   *          sequence: a read operation to USART_SR register followed by a read
00339   *          operation to USART_DR register.
00340   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00341   * @note   TC flag can be also cleared by software sequence: a read operation to
00342   *          USART_SR register followed by a write operation to USART_DR register.
00343   * @note   TXE flag is cleared only by a write to the USART_DR register.
00344   *
00345   * @retval None
00346   */
00347 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00348
00349 /** @brief  Clear the USART PE pending flag.
00350   * @param  __HANDLE__: specifies the USART Handle.
00351   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00352   * @retval None
00353   */
00354 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)    \
00355   do{                                           \
00356     __IO uint32_t tmpreg = 0x00U;                \
00357     tmpreg = (__HANDLE__)->Instance->SR;        \
00358     tmpreg = (__HANDLE__)->Instance->DR;        \
00359     UNUSED(tmpreg);                             \
00360   } while(0)
00361
00362 /** @brief  Clear the USART FE pending flag.
00363   * @param  __HANDLE__: specifies the USART Handle.
00364   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00365   * @retval None
00366   */
00367 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00368
00369 /** @brief  Clear the USART NE pending flag.
00370   * @param  __HANDLE__: specifies the USART Handle.
00371   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00372   * @retval None
00373   */
00374 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00375
00376 /** @brief  Clear the UART ORE pending flag.
00377   * @param  __HANDLE__: specifies the USART Handle.
00378   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00379   * @retval None
00380   */
00381 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00382
00383 /** @brief  Clear the USART IDLE pending flag.
00384   * @param  __HANDLE__: specifies the USART Handle.
00385   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00386   * @retval None
00387   */
00388 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00389
00390 /** @brief  Enables or disables the specified USART interrupts.
00391   * @param  __HANDLE__: specifies the USART Handle.
00392   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00393   * @param  __INTERRUPT__: specifies the USART interrupt source to check.
00394   *          This parameter can be one of the following values:
00395   *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
00396   *            @arg USART_IT_TC:   Transmission complete interrupt
00397   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00398   *            @arg USART_IT_IDLE: Idle line detection interrupt
00399   *            @arg USART_IT_PE:   Parity Error interrupt
00400   *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00401   *          This parameter can be: ENABLE or DISABLE.
00402   * @retval None
00403   */
00404 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
00405                                                             (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
00406                                                              ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
00407 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
00408                                                             (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
00409                                                              ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
00410
00411 /** @brief  Checks whether the specified USART interrupt has occurred or not.
00412   * @param  __HANDLE__: specifies the USART Handle.
00413   *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
00414   * @param  __IT__: specifies the USART interrupt source to check.
00415   *          This parameter can be one of the following values:
00416   *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
00417   *            @arg USART_IT_TC:  Transmission complete interrupt
00418   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00419   *            @arg USART_IT_IDLE: Idle line detection interrupt
00420   *            @arg USART_IT_ERR: Error interrupt
00421   *            @arg USART_IT_PE: Parity Error interrupt
00422   * @retval The new state of __IT__ (TRUE or FALSE).
00423   */
00424 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
00425                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
00426
00427 /** @brief  Macro to enable the USART's one bit sample method
00428   * @param  __HANDLE__: specifies the USART Handle.
00429   * @retval None
00430   */
00431 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00432
00433 /** @brief  Macro to disable the USART's one bit sample method
00434   * @param  __HANDLE__: specifies the USART Handle.
00435   * @retval None
00436   */
00437 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
00438
00439 /** @brief  Enable USART
00440   * @param  __HANDLE__: specifies the USART Handle.
00441   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00442   * @retval None
00443   */
00444 #define __HAL_USART_ENABLE(__HANDLE__)               ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00445
00446 /** @brief  Disable USART
00447   * @param  __HANDLE__: specifies the USART Handle.
00448   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00449   * @retval None
00450   */
00451 #define __HAL_USART_DISABLE(__HANDLE__)              ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00452
00453 /**
00454   * @}
00455   */
00456 /* Exported functions --------------------------------------------------------*/
00457 /** @addtogroup USART_Exported_Functions
00458   * @{
00459   */
00460
00461 /** @addtogroup USART_Exported_Functions_Group1
00462   * @{
00463   */
00464 /* Initialization/de-initialization functions  **********************************/
00465 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00466 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00467 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00468 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00469 /**
00470   * @}
00471   */
00472
00473 /** @addtogroup USART_Exported_Functions_Group2
00474   * @{
00475   */
00476 /* IO operation functions *******************************************************/
00477 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
00478 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00479 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00480 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00481 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00482 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
00483 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00484 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00485 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00486 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00487 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00488 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00489 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00490 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00491 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00492 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00493 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00494 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00495 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00496 /**
00497   * @}
00498   */
00499
00500 /** @addtogroup USART_Exported_Functions_Group3
00501   * @{
00502   */
00503 /* Peripheral State functions  ************************************************/
00504 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
00505 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
00506 /**
00507   * @}
00508   */
00509
00510 /**
00511   * @}
00512   */
00513 /* Private types -------------------------------------------------------------*/
00514 /* Private variables ---------------------------------------------------------*/
00515 /* Private constants ---------------------------------------------------------*/
00516 /** @defgroup USART_Private_Constants USART Private Constants
00517   * @{
00518   */
00519 /** @brief USART interruptions flag mask
00520   *
00521   */
00522 #define USART_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
00523                                    USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
00524
00525 #define USART_CR1_REG_INDEX             1U
00526 #define USART_CR2_REG_INDEX             2U
00527 #define USART_CR3_REG_INDEX             3U
00528 /**
00529   * @}
00530   */
00531
00532 /* Private macros ------------------------------------------------------------*/
00533 /** @defgroup USART_Private_Macros USART Private Macros
00534   * @{
00535   */
00536 #define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
00537                                    ((NACK) == USART_NACK_DISABLE))
00538 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
00539                                        ((LASTBIT) == USART_LASTBIT_ENABLE))
00540 #define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
00541 #define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
00542 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
00543                                ((CLOCK) == USART_CLOCK_ENABLE))
00544 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
00545                                           ((LENGTH) == USART_WORDLENGTH_9B))
00546 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
00547                                          ((STOPBITS) == USART_STOPBITS_0_5) || \
00548                                          ((STOPBITS) == USART_STOPBITS_1_5) || \
00549                                          ((STOPBITS) == USART_STOPBITS_2))
00550 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
00551                                      ((PARITY) == USART_PARITY_EVEN) || \
00552                                      ((PARITY) == USART_PARITY_ODD))
00553 #define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00U) && ((MODE) != (uint32_t)0x00U))
00554 #define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
00555
00556 #define USART_DIV(_PCLK_, _BAUD_)                  (((_PCLK_)*25U)/(2U*(_BAUD_)))
00557 #define USART_DIVMANT(_PCLK_, _BAUD_)              (USART_DIV((_PCLK_), (_BAUD_))/100U)
00558 #define USART_DIVFRAQ(_PCLK_, _BAUD_)              (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00559 #define USART_BRR(_PCLK_, _BAUD_)                  ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
00560 /**
00561   * @}
00562   */
00563
00564 /* Private functions ---------------------------------------------------------*/
00565 /** @defgroup USART_Private_Functions USART Private Functions
00566   * @{
00567   */
00568
00569 /**
00570   * @}
00571   */
00572
00573 /**
00574   * @}
00575   */
00576
00577 /**
00578   * @}
00579   */
00580
00581 #ifdef __cplusplus
00582 }
00583 #endif
00584
00585 #endif /* __STM32F4xx_HAL_USART_H */
00586
00587 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_wwdg.c Source File

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stm32f4xx_hal_wwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   WWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Window Watchdog (WWDG) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State functions
00013   @verbatim
00014   ==============================================================================
00015                       ##### WWDG specific features #####
00016   ==============================================================================
00017   [..]
00018     Once enabled the WWDG generates a system reset on expiry of a programmed
00019     time period, unless the program refreshes the counter (downcounter)
00020     before reaching 0x3F value (i.e. a reset is generated when the counter
00021     value rolls over from 0x40 to 0x3F).
00022
00023     (+) An MCU reset is also generated if the counter value is refreshed
00024         before the counter has reached the refresh window value. This
00025         implies that the counter must be refreshed in a limited window.
00026     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00027     (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
00028         reset occurs.
00029     (+) The WWDG counter input clock is derived from the APB clock divided
00030         by a programmable prescaler.
00031     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
00032     (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
00033     (+) WWDG Counter refresh is allowed between the following limits :
00034         (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
00035         (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
00036
00037     (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms
00038
00039
00040                      ##### How to use this driver #####
00041   ==============================================================================
00042   [..]
00043     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00044     (+) Set the WWDG prescaler, refresh window and counter value
00045         using HAL_WWDG_Init() function.
00046     (+) Start the WWDG using HAL_WWDG_Start() function.
00047         When the WWDG is enabled the counter value should be configured to
00048         a value greater than 0x40 to prevent generating an immediate reset.
00049     (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
00050         generated when the counter reaches 0x40, and then start the WWDG using
00051         HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
00052         add his own code by customization of function pointer HAL_WWDG_WakeupCallback
00053         Once enabled, EWI interrupt cannot be disabled except by a system reset.
00054     (+) Then the application program must refresh the WWDG counter at regular
00055         intervals during normal operation to prevent an MCU reset, using
00056         HAL_WWDG_Refresh() function. This operation must occur only when
00057         the counter is lower than the refresh window value already programmed.
00058
00059      *** WWDG HAL driver macros list ***
00060      ==================================
00061      [..]
00062        Below the list of most used macros in WWDG HAL driver.
00063
00064       (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
00065       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
00066       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
00067       (+) __HAL_WWDG_ENABLE_IT:  Enables the WWDG early wake-up interrupt
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f4xx_hal.h"
00102
00103 /** @addtogroup STM32F4xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup WWDG WWDG
00108   * @brief WWDG HAL module driver.
00109   * @{
00110   */
00111
00112 #ifdef HAL_WWDG_MODULE_ENABLED
00113
00114 /* Private typedef -----------------------------------------------------------*/
00115 /* Private define ------------------------------------------------------------*/
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00121   * @{
00122   */
00123
00124 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
00125  *  @brief    Initialization and Configuration functions.
00126  *
00127 @verbatim
00128   ==============================================================================
00129           ##### Initialization and de-initialization functions #####
00130   ==============================================================================
00131   [..]
00132     This section provides functions allowing to:
00133     (+) Initialize the WWDG according to the specified parameters
00134         in the WWDG_InitTypeDef and create the associated handle
00135     (+) DeInitialize the WWDG peripheral
00136     (+) Initialize the WWDG MSP
00137     (+) DeInitialize the WWDG MSP
00138
00139 @endverbatim
00140   * @{
00141   */
00142
00143 /**
00144   * @brief  Initializes the WWDG according to the specified
00145   *         parameters in the WWDG_InitTypeDef and creates the associated handle.
00146   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00147   *              the configuration information for the specified WWDG module.
00148   * @retval HAL status
00149   */
00150 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00151 {
00152   /* Check the WWDG handle allocation */
00153   if(hwwdg == NULL)
00154   {
00155     return HAL_ERROR;
00156   }
00157
00158   /* Check the parameters */
00159   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00160   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00161   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00162   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00163
00164   if(hwwdg->State == HAL_WWDG_STATE_RESET)
00165   {
00166     /* Allocate lock resource and initialize it */
00167     hwwdg->Lock = HAL_UNLOCKED;
00168     /* Init the low level hardware */
00169     HAL_WWDG_MspInit(hwwdg);
00170   }
00171
00172   /* Change WWDG peripheral state */
00173   hwwdg->State = HAL_WWDG_STATE_BUSY;
00174
00175   /* Set WWDG Prescaler and Window */
00176   MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
00177   /* Set WWDG Counter */
00178   MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
00179
00180   /* Change WWDG peripheral state */
00181   hwwdg->State = HAL_WWDG_STATE_READY;
00182
00183   /* Return function status */
00184   return HAL_OK;
00185 }
00186
00187 /**
00188   * @brief  DeInitializes the WWDG peripheral.
00189   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00190   *              the configuration information for the specified WWDG module.
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
00194 {
00195   /* Check the WWDG handle allocation */
00196   if(hwwdg == NULL)
00197   {
00198     return HAL_ERROR;
00199   }
00200
00201   /* Check the parameters */
00202   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00203
00204   /* Change WWDG peripheral state */
00205   hwwdg->State = HAL_WWDG_STATE_BUSY;
00206
00207   /* DeInit the low level hardware */
00208   HAL_WWDG_MspDeInit(hwwdg);
00209
00210   /* Reset WWDG Control register */
00211   hwwdg->Instance->CR  = (uint32_t)0x0000007FU;
00212
00213   /* Reset WWDG Configuration register */
00214   hwwdg->Instance->CFR = (uint32_t)0x0000007FU;
00215
00216   /* Reset WWDG Status register */
00217   hwwdg->Instance->SR  = 0U;
00218
00219   /* Change WWDG peripheral state */
00220   hwwdg->State = HAL_WWDG_STATE_RESET;
00221
00222   /* Release Lock */
00223   __HAL_UNLOCK(hwwdg);
00224
00225   /* Return function status */
00226   return HAL_OK;
00227 }
00228
00229 /**
00230   * @brief  Initializes the WWDG MSP.
00231   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00232   *              the configuration information for the specified WWDG module.
00233   * @retval None
00234   */
00235 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00236 {
00237   /* Prevent unused argument(s) compilation warning */
00238   UNUSED(hwwdg);
00239   /* NOTE: This function Should not be modified, when the callback is needed,
00240            the HAL_WWDG_MspInit could be implemented in the user file
00241    */
00242 }
00243
00244 /**
00245   * @brief  DeInitializes the WWDG MSP.
00246   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00247   *              the configuration information for the specified WWDG module.
00248   * @retval None
00249   */
00250 __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
00251 {
00252   /* Prevent unused argument(s) compilation warning */
00253   UNUSED(hwwdg);
00254   /* NOTE: This function Should not be modified, when the callback is needed,
00255            the HAL_WWDG_MspDeInit could be implemented in the user file
00256    */
00257 }
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00264  *  @brief    IO operation functions
00265  *
00266 @verbatim
00267   ==============================================================================
00268                        ##### IO operation functions #####
00269   ==============================================================================
00270   [..]
00271     This section provides functions allowing to:
00272     (+) Start the WWDG.
00273     (+) Refresh the WWDG.
00274     (+) Handle WWDG interrupt request.
00275
00276 @endverbatim
00277   * @{
00278   */
00279
00280 /**
00281   * @brief  Starts the WWDG.
00282   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00283   *              the configuration information for the specified WWDG module.
00284   * @retval HAL status
00285   */
00286 HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
00287 {
00288   /* Process Locked */
00289   __HAL_LOCK(hwwdg);
00290
00291   /* Change WWDG peripheral state */
00292   hwwdg->State = HAL_WWDG_STATE_BUSY;
00293
00294   /* Enable the peripheral */
00295   __HAL_WWDG_ENABLE(hwwdg);
00296
00297   /* Change WWDG peripheral state */
00298   hwwdg->State = HAL_WWDG_STATE_READY;
00299
00300   /* Process Unlocked */
00301   __HAL_UNLOCK(hwwdg);
00302
00303   /* Return function status */
00304   return HAL_OK;
00305 }
00306
00307 /**
00308   * @brief  Starts the WWDG with interrupt enabled.
00309   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00310   *              the configuration information for the specified WWDG module.
00311   * @retval HAL status
00312   */
00313 HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
00314 {
00315   /* Process Locked */
00316   __HAL_LOCK(hwwdg);
00317
00318   /* Change WWDG peripheral state */
00319   hwwdg->State = HAL_WWDG_STATE_BUSY;
00320
00321   /* Enable the Early Wakeup Interrupt */
00322   __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
00323
00324   /* Enable the peripheral */
00325   __HAL_WWDG_ENABLE(hwwdg);
00326
00327   /* Return function status */
00328   return HAL_OK;
00329 }
00330
00331 /**
00332   * @brief  Refreshes the WWDG.
00333   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00334   *              the configuration information for the specified WWDG module.
00335   * @param  Counter: value of counter to put in WWDG counter
00336   * @retval HAL status
00337   */
00338 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
00339 {
00340   /* Process Locked */
00341   __HAL_LOCK(hwwdg);
00342
00343   /* Change WWDG peripheral state */
00344   hwwdg->State = HAL_WWDG_STATE_BUSY;
00345
00346   /* Check the parameters */
00347   assert_param(IS_WWDG_COUNTER(Counter));
00348
00349   /* Write to WWDG CR the WWDG Counter value to refresh with */
00350   MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
00351
00352   /* Change WWDG peripheral state */
00353   hwwdg->State = HAL_WWDG_STATE_READY;
00354
00355   /* Process Unlocked */
00356   __HAL_UNLOCK(hwwdg);
00357
00358   /* Return function status */
00359   return HAL_OK;
00360 }
00361
00362 /**
00363   * @brief  Handles WWDG interrupt request.
00364   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00365   *         or data logging must be performed before the actual reset is generated.
00366   *         The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
00367   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00368   *         generated and the corresponding Interrupt Service Routine (ISR) can
00369   *         be used to trigger specific actions (such as communications or data
00370   *         logging), before resetting the device.
00371   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00372   *              the configuration information for the specified WWDG module.
00373   * @retval None
00374   */
00375 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00376 {
00377   /* Check if Early Wakeup Interrupt is enable */
00378   if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00379   {
00380     /* Check if WWDG Early Wakeup Interrupt occurred */
00381     if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00382     {
00383       /* Early Wakeup callback */
00384       HAL_WWDG_WakeupCallback(hwwdg);
00385
00386       /* Change WWDG peripheral state */
00387       hwwdg->State = HAL_WWDG_STATE_READY;
00388
00389       /* Clear the WWDG Early Wakeup flag */
00390       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00391
00392       /* Process Unlocked */
00393       __HAL_UNLOCK(hwwdg);
00394     }
00395   }
00396 }
00397
00398 /**
00399   * @brief  Early Wakeup WWDG callback.
00400   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00401   *              the configuration information for the specified WWDG module.
00402   * @retval None
00403   */
00404 __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
00405 {
00406   /* Prevent unused argument(s) compilation warning */
00407   UNUSED(hwwdg);
00408   /* NOTE: This function Should not be modified, when the callback is needed,
00409            the HAL_WWDG_WakeupCallback could be implemented in the user file
00410    */
00411 }
00412
00413 /**
00414   * @}
00415   */
00416
00417 /** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
00418  *  @brief    Peripheral State functions.
00419  *
00420 @verbatim
00421   ==============================================================================
00422                         ##### Peripheral State functions #####
00423   ==============================================================================
00424   [..]
00425     This subsection permits to get in run-time the status of the peripheral
00426     and the data flow.
00427
00428 @endverbatim
00429   * @{
00430   */
00431
00432 /**
00433   * @brief  Returns the WWDG state.
00434   * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
00435   *              the configuration information for the specified WWDG module.
00436   * @retval HAL state
00437   */
00438 HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
00439 {
00440   return hwwdg->State;
00441 }
00442
00443 /**
00444   * @}
00445   */
00446
00447 /**
00448   * @}
00449   */
00450
00451 #endif /* HAL_WWDG_MODULE_ENABLED */
00452 /**
00453   * @}
00454   */
00455
00456 /**
00457   * @}
00458   */
00459
00460 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: stm32f4xx_hal_wwdg.h Source File

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stm32f4xx_hal_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.4.4
00006   * @date    22-January-2016
00007   * @brief   Header file of WWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F4xx_HAL_WWDG_H
00040 #define __STM32F4xx_HAL_WWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f4xx_hal_def.h"
00048
00049 /** @addtogroup STM32F4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup WWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  WWDG HAL State Structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_WWDG_STATE_RESET     = 0x00U,  /*!< WWDG not yet initialized or disabled */
00068   HAL_WWDG_STATE_READY     = 0x01U,  /*!< WWDG initialized and ready for use   */
00069   HAL_WWDG_STATE_BUSY      = 0x02U,  /*!< WWDG internal process is ongoing     */
00070   HAL_WWDG_STATE_TIMEOUT   = 0x03U,  /*!< WWDG timeout state                   */
00071   HAL_WWDG_STATE_ERROR     = 0x04U   /*!< WWDG error state                     */
00072 }HAL_WWDG_StateTypeDef;
00073
00074 /**
00075   * @brief  WWDG Init structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t Prescaler;  /*!< Specifies the prescaler value of the WWDG.
00080                             This parameter can be a value of @ref WWDG_Prescaler */
00081
00082   uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
00083                             This parameter must be a number lower than Max_Data = 0x80 */
00084
00085   uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
00086                             This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00087
00088 }WWDG_InitTypeDef;
00089
00090 /**
00091   * @brief  WWDG handle Structure definition
00092   */
00093 typedef struct
00094 {
00095   WWDG_TypeDef                 *Instance;  /*!< Register base address    */
00096
00097   WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
00098
00099   HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
00100
00101   __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
00102
00103 }WWDG_HandleTypeDef;
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported constants --------------------------------------------------------*/
00109 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00110   * @{
00111   */
00112
00113 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00114   * @{
00115   */
00116 #define WWDG_IT_EWI                       WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00122   * @brief WWDG Flag definition
00123   * @{
00124   */
00125 #define WWDG_FLAG_EWIF                    WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup WWDG_Prescaler WWDG Prescaler
00131   * @{
00132   */
00133 #define WWDG_PRESCALER_1                 ((uint32_t)0x00000000U)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
00134 #define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
00135 #define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
00136 #define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
00137 /**
00138   * @}
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported macro ------------------------------------------------------------*/
00146 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00147   * @{
00148   */
00149
00150 /** @brief Reset WWDG handle state
00151   * @param  __HANDLE__: WWDG handle
00152   * @retval None
00153   */
00154 #define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
00155
00156 /**
00157   * @brief  Enables the WWDG peripheral.
00158   * @param  __HANDLE__: WWDG handle
00159   * @retval None
00160   */
00161 #define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00162
00163 /**
00164   * @brief  Disables the WWDG peripheral.
00165   * @param  __HANDLE__: WWDG handle
00166   * @note   WARNING: This is a dummy macro for HAL code alignment.
00167   *         Once enable, WWDG Peripheral cannot be disabled except by a system reset.
00168   * @retval None
00169   */
00170 #define __HAL_WWDG_DISABLE(__HANDLE__)                      /* dummy  macro */
00171
00172 /**
00173   * @brief  Gets the selected WWDG's it status.
00174   * @param  __HANDLE__: WWDG handle
00175   * @param  __INTERRUPT__: specifies the it to check.
00176   *        This parameter can be one of the following values:
00177   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00178   * @retval The new state of WWDG_FLAG (SET or RESET).
00179   */
00180 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)       __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00181
00182 /** @brief  Clear the WWDG's interrupt pending bits
00183   *         bits to clear the selected interrupt pending bits.
00184   * @param  __HANDLE__: WWDG handle
00185   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00186   *         This parameter can be one of the following values:
00187   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00188   */
00189 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)     __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00190
00191 /**
00192   * @brief  Enables the WWDG early wakeup interrupt.
00193   * @param  __HANDLE__: WWDG handle
00194   * @param  __INTERRUPT__: specifies the interrupt to enable.
00195   *         This parameter can be one of the following values:
00196   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00197   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00198   * @retval None
00199   */
00200 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00201
00202 /**
00203   * @brief  Disables the WWDG early wakeup interrupt.
00204   * @param  __HANDLE__: WWDG handle
00205   * @param  __INTERRUPT__: specifies the interrupt to disable.
00206   *         This parameter can be one of the following values:
00207   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00208   * @note   WARNING: This is a dummy macro for HAL code alignment.
00209   *         Once enabled this interrupt cannot be disabled except by a system reset.
00210   * @retval None
00211   */
00212 #define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__)                   /* dummy  macro */
00213
00214 /**
00215   * @brief  Gets the selected WWDG's flag status.
00216   * @param  __HANDLE__: WWDG handle
00217   * @param  __FLAG__: specifies the flag to check.
00218   *         This parameter can be one of the following values:
00219   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00220   * @retval The new state of WWDG_FLAG (SET or RESET).
00221   */
00222 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00223
00224 /**
00225   * @brief  Clears the WWDG's pending flags.
00226   * @param  __HANDLE__: WWDG handle
00227   * @param  __FLAG__: specifies the flag to clear.
00228   *         This parameter can be one of the following values:
00229   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00230   * @retval None
00231   */
00232 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
00233
00234 /** @brief  Checks if the specified WWDG interrupt source is enabled or disabled.
00235   * @param  __HANDLE__: WWDG Handle.
00236   * @param  __INTERRUPT__: specifies the WWDG interrupt source to check.
00237   *          This parameter can be one of the following values:
00238   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00239   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00240   */
00241 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
00242
00243 /**
00244   * @}
00245   */
00246
00247 /* Exported functions --------------------------------------------------------*/
00248 /** @addtogroup WWDG_Exported_Functions
00249   * @{
00250   */
00251
00252 /** @addtogroup WWDG_Exported_Functions_Group1
00253   * @{
00254   */
00255 /* Initialization/de-initialization functions  **********************************/
00256 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00257 HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
00258 void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00259 void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
00260 void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
00261 /**
00262   * @}
00263   */
00264
00265 /** @addtogroup WWDG_Exported_Functions_Group2
00266   * @{
00267   */
00268 /* I/O operation functions ******************************************************/
00269 HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
00270 HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
00271 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
00272 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00273 /**
00274   * @}
00275   */
00276
00277 /** @addtogroup WWDG_Exported_Functions_Group3
00278   * @{
00279   */
00280 /* Peripheral State functions  **************************************************/
00281 HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
00282 /**
00283   * @}
00284   */
00285
00286 /**
00287   * @}
00288   */
00289
00290 /* Private types -------------------------------------------------------------*/
00291 /* Private variables ---------------------------------------------------------*/
00292 /* Private constants ---------------------------------------------------------*/
00293 /** @defgroup WWDG_Private_Constants WWDG Private Constants
00294   * @{
00295   */
00296 /** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress
00297   * @brief WWDG registers bit address in the alias region
00298   * @{
00299   */
00300
00301 /* --- CFR Register ---*/
00302 /* Alias word address of EWI bit */
00303 #define WWDG_CFR_BASE   (uint32_t)(WWDG_BASE + 0x04U)
00304
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Private macros ------------------------------------------------------------*/
00314 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00315   * @{
00316   */
00317 #define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
00318                                           ((__PRESCALER__) == WWDG_PRESCALER_2) || \
00319                                           ((__PRESCALER__) == WWDG_PRESCALER_4) || \
00320                                           ((__PRESCALER__) == WWDG_PRESCALER_8))
00321 #define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7FU)
00322 #define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40U) && ((__COUNTER__) <= 0x7FU))
00323 /**
00324   * @}
00325   */
00326
00327 /* Private functions ---------------------------------------------------------*/
00328 /** @defgroup WWDG_Private_Functions WWDG Private Functions
00329   * @{
00330   */
00331
00332 /**
00333   * @}
00334   */
00335
00336 /**
00337   * @}
00338   */
00339
00340 /**
00341   * @}
00342   */
00343 #ifdef __cplusplus
00344 }
00345 #endif
00346
00347 #endif /* __STM32F4xx_HAL_WWDG_H */
00348
00349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Jan 29 2016 15:36:53 for STM32F410Rx HAL User Manual by doxygen 1.7.6.1


STM32F410Rx HAL User Manual: userManualMainpage.txt File Reference

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